Patched in Tegra support.

475 files changed, 167 insertions, 24783 deletions

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt
deleted file mode 100644
index ecdb57d69db..00000000000
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-Altera SOCFPGA Reset Manager
-
-Required properties:
-- compatible : "altr,rst-mgr"
-- reg : Should contain 1 register ranges(address and length)
-
-Example:
-         rstmgr@ffd05000 {
-                compatible = "altr,rst-mgr";
-                reg = <0xffd05000 0x1000>;
-        };
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt
deleted file mode 100644
index 07c65e3cdcb..00000000000
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-Altera SOCFPGA System Manager
-
-Required properties:
-- compatible : "altr,sys-mgr"
-- reg : Should contain 1 register ranges(address and length)
-
-Example:
-         sysmgr@ffd08000 {
-                compatible = "altr,sys-mgr";
-                reg = <0xffd08000 0x1000>;
-        };
diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
deleted file mode 100644
index 52478c83d0c..00000000000
--- a/Documentation/devicetree/bindings/arm/arch_timer.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-* ARM architected timer
-
-ARM Cortex-A7 and Cortex-A15 have a per-core architected timer, which
-provides per-cpu timers.
-
-The timer is attached to a GIC to deliver its per-processor interrupts.
-
-** Timer node properties:
-
-- compatible : Should at least contain "arm,armv7-timer".
-
-- interrupts : Interrupt list for secure, non-secure, virtual and
-  hypervisor timers, in that order.
-
-- clock-frequency : The frequency of the main counter, in Hz. Optional.
-
-Example:
-
-        timer {
-                compatible = "arm,cortex-a15-timer",
-                             "arm,armv7-timer";
-                interrupts = <1 13 0xf08>,
-                             <1 14 0xf08>,
-                             <1 11 0xf08>,
-                             <1 10 0xf08>;
-                clock-frequency = <100000000>;
-        };
diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards
index db5858e32d3..91f26148af7 100644
--- a/Documentation/devicetree/bindings/arm/arm-boards
+++ b/Documentation/devicetree/bindings/arm/arm-boards
@@ -1,19 +1,3 @@
-ARM Integrator/AP (Application Platform) and Integrator/CP (Compact Platform)
------------------------------------------------------------------------------
-ARM's oldest Linux-supported platform with connectors for different core
-tiles of ARMv4, ARMv5 and ARMv6 type.
-
-Required properties (in root node):
-        compatible = "arm,integrator-ap";  /* Application Platform */
-        compatible = "arm,integrator-cp";  /* Compact Platform */
-
-FPGA type interrupt controllers, see the versatile-fpga-irq binding doc.
-
-In the root node the Integrator/CP must have a /cpcon node pointing
-to the CP control registers, and the Integrator/AP must have a
-/syscon node pointing to the Integrator/AP system controller.
-
-
 ARM Versatile Application and Platform Baseboards
 -------------------------------------------------
 ARM's development hardware platform with connectors for customizable
diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt b/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
deleted file mode 100644
index 61df564c0d2..00000000000
--- a/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-Marvell Armada 370 and Armada XP Interrupt Controller
------------------------------------------------------
-
-Required properties:
-- compatible: Should be "marvell,mpic"
-- interrupt-controller: Identifies the node as an interrupt controller.
-- #interrupt-cells: The number of cells to define the interrupts. Should be 1.
-  The cell is the IRQ number
-
-- reg: Should contain PMIC registers location and length. First pair
-  for the main interrupt registers, second pair for the per-CPU
-  interrupt registers. For this last pair, to be compliant with SMP
-  support, the "virtual" must be use (For the record, these registers
-  automatically map to the interrupt controller registers of the
-  current CPU)
-
-
-
-Example:
-
-        mpic: interrupt-controller@d0020000 {
-              compatible = "marvell,mpic";
-              #interrupt-cells = <1>;
-              #address-cells = <1>;
-              #size-cells = <1>;
-              interrupt-controller;
-              reg = <0xd0020a00 0x1d0>,
-                    <0xd0021070 0x58>;
-        };
diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt b/Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt
deleted file mode 100644
index 926b4d6aae7..00000000000
--- a/Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-Power Management Service Unit(PMSU)
------------------------------------
-Available on Marvell SOCs: Armada 370 and Armada XP
-
-Required properties:
-
-- compatible: "marvell,armada-370-xp-pmsu"
-
-- reg: Should contain PMSU registers location and length. First pair
-  for the per-CPU SW Reset Control registers, second pair for the
-  Power Management Service Unit.
-
-Example:
-
-armada-370-xp-pmsu@d0022000 {
-        compatible = "marvell,armada-370-xp-pmsu";
-        reg = <0xd0022100 0x430>,
-              <0xd0020800 0x20>;
-};
-
diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt b/Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt
deleted file mode 100644
index 64830118b01..00000000000
--- a/Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-Marvell Armada 370 and Armada XP Global Timers
-----------------------------------------------
-
-Required properties:
-- compatible: Should be "marvell,armada-370-xp-timer"
-- interrupts: Should contain the list of Global Timer interrupts
-- reg: Should contain the base address of the Global Timer registers
-- clocks: clock driving the timer hardware
-
-Optional properties:
-- marvell,timer-25Mhz: Tells whether the Global timer supports the 25
-  Mhz fixed mode (available on Armada XP and not on Armada 370)
diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp.txt b/Documentation/devicetree/bindings/arm/armada-370-xp.txt
deleted file mode 100644
index c6ed90ea6e1..00000000000
--- a/Documentation/devicetree/bindings/arm/armada-370-xp.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-Marvell Armada 370 and Armada XP Platforms Device Tree Bindings
----------------------------------------------------------------
-
-Boards with a SoC of the Marvell Armada 370 and Armada XP families
-shall have the following property:
-
-Required root node property:
-
-compatible: must contain "marvell,armada-370-xp"
-
-In addition, boards using the Marvell Armada 370 SoC shall have the
-following property:
-
-Required root node property:
-
-compatible: must contain "marvell,armada370"
-
-In addition, boards using the Marvell Armada XP SoC shall have the
-following property:
-
-Required root node property:
-
-compatible: must contain "marvell,armadaxp"
-
diff --git a/Documentation/devicetree/bindings/arm/atmel-adc.txt b/Documentation/devicetree/bindings/arm/atmel-adc.txt
deleted file mode 100644
index c63097d6afe..00000000000
--- a/Documentation/devicetree/bindings/arm/atmel-adc.txt
+++ /dev/null
@@ -1,65 +0,0 @@
-* AT91's Analog to Digital Converter (ADC)
-
-Required properties:
-  - compatible: Should be "atmel,at91sam9260-adc"
-  - reg: Should contain ADC registers location and length
-  - interrupts: Should contain the IRQ line for the ADC
-  - atmel,adc-channel-base: Offset of the first channel data register
-  - atmel,adc-channels-used: Bitmask of the channels muxed and enable for this
-    device
-  - atmel,adc-drdy-mask: Mask of the DRDY interruption in the ADC
-  - atmel,adc-num-channels: Number of channels available in the ADC
-  - atmel,adc-startup-time: Startup Time of the ADC in microseconds as
-    defined in the datasheet
-  - atmel,adc-status-register: Offset of the Interrupt Status Register
-  - atmel,adc-trigger-register: Offset of the Trigger Register
-  - atmel,adc-vref: Reference voltage in millivolts for the conversions
-
-Optional properties:
-  - atmel,adc-use-external: Boolean to enable of external triggers
- 
-Optional trigger Nodes:
-  - Required properties:
-    * trigger-name: Name of the trigger exposed to the user
-    * trigger-value: Value to put in the Trigger register
-      to activate this trigger
-  - Optional properties:
-    * trigger-external: Is the trigger an external trigger?
-
-Examples:
-adc0: adc@fffb0000 {
-        compatible = "atmel,at91sam9260-adc";
-        reg = <0xfffb0000 0x100>;
-        interrupts = <20 4>;
-        atmel,adc-channel-base = <0x30>;
-        atmel,adc-channels-used = <0xff>;
-        atmel,adc-drdy-mask = <0x10000>;
-        atmel,adc-num-channels = <8>;
-        atmel,adc-startup-time = <40>;
-        atmel,adc-status-register = <0x1c>;
-        atmel,adc-trigger-register = <0x08>;
-        atmel,adc-use-external;
-        atmel,adc-vref = <3300>;
-
-        trigger@0 {
-                trigger-name = "external-rising";
-                trigger-value = <0x1>;
-                trigger-external;
-        };
-        trigger@1 {
-                trigger-name = "external-falling";
-                trigger-value = <0x2>;
-                trigger-external;
-        };
-
-        trigger@2 {
-                trigger-name = "external-any";
-                trigger-value = <0x3>;
-                trigger-external;
-        };
-
-        trigger@3 {
-                trigger-name = "continuous";
-                trigger-value = <0x6>;
-        };
-};
diff --git a/Documentation/devicetree/bindings/arm/atmel-aic.txt b/Documentation/devicetree/bindings/arm/atmel-aic.txt
deleted file mode 100644
index 19078bf5cca..00000000000
--- a/Documentation/devicetree/bindings/arm/atmel-aic.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-* Advanced Interrupt Controller (AIC)
-
-Required properties:
-- compatible: Should be "atmel,<chip>-aic"
-- interrupt-controller: Identifies the node as an interrupt controller.
-- interrupt-parent: For single AIC system, it is an empty property.
-- #interrupt-cells: The number of cells to define the interrupts. It sould be 3.
-  The first cell is the IRQ number (aka "Peripheral IDentifier" on datasheet).
-  The second cell is used to specify flags:
-    bits[3:0] trigger type and level flags:
-      1 = low-to-high edge triggered.
-      2 = high-to-low edge triggered.
-      4 = active high level-sensitive.
-      8 = active low level-sensitive.
-      Valid combinations are 1, 2, 3, 4, 8.
-      Default flag for internal sources should be set to 4 (active high).
-  The third cell is used to specify the irq priority from 0 (lowest) to 7
-  (highest).
-- reg: Should contain AIC registers location and length
-- atmel,external-irqs: u32 array of external irqs.
-
-Examples:
-        /*
-         * AIC
-         */
-        aic: interrupt-controller@fffff000 {
-                compatible = "atmel,at91rm9200-aic";
-                interrupt-controller;
-                interrupt-parent;
-                #interrupt-cells = <3>;
-                reg = <0xfffff000 0x200>;
-        };
-
-        /*
-         * An interrupt generating device that is wired to an AIC.
-         */
-        dma: dma-controller@ffffec00 {
-                compatible = "atmel,at91sam9g45-dma";
-                reg = <0xffffec00 0x200>;
-                interrupts = <21 4 5>;
-        };
diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
deleted file mode 100644
index 1196290082d..00000000000
--- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
+++ /dev/null
@@ -1,98 +0,0 @@
-Atmel AT91 device tree bindings.
-================================
-
-PIT Timer required properties:
-- compatible: Should be "atmel,at91sam9260-pit"
-- reg: Should contain registers location and length
-- interrupts: Should contain interrupt for the PIT which is the IRQ line
-  shared across all System Controller members.
-
-System Timer (ST) required properties:
-- compatible: Should be "atmel,at91rm9200-st"
-- reg: Should contain registers location and length
-- interrupts: Should contain interrupt for the ST which is the IRQ line
-  shared across all System Controller members.
-
-TC/TCLIB Timer required properties:
-- compatible: Should be "atmel,<chip>-tcb".
-  <chip> can be "at91rm9200" or "at91sam9x5"
-- reg: Should contain registers location and length
-- interrupts: Should contain all interrupts for the TC block
-  Note that you can specify several interrupt cells if the TC
-  block has one interrupt per channel.
-
-Examples:
-
-One interrupt per TC block:
-        tcb0: timer@fff7c000 {
-                compatible = "atmel,at91rm9200-tcb";
-                reg = <0xfff7c000 0x100>;
-                interrupts = <18 4>;
-        };
-
-One interrupt per TC channel in a TC block:
-        tcb1: timer@fffdc000 {
-                compatible = "atmel,at91rm9200-tcb";
-                reg = <0xfffdc000 0x100>;
-                interrupts = <26 4 27 4 28 4>;
-        };
-
-RSTC Reset Controller required properties:
-- compatible: Should be "atmel,<chip>-rstc".
-  <chip> can be "at91sam9260" or "at91sam9g45"
-- reg: Should contain registers location and length
-
-Example:
-
-        rstc@fffffd00 {
-                compatible = "atmel,at91sam9260-rstc";
-                reg = <0xfffffd00 0x10>;
-        };
-
-RAMC SDRAM/DDR Controller required properties:
-- compatible: Should be "atmel,at91sam9260-sdramc",
-                        "atmel,at91sam9g45-ddramc",
-- reg: Should contain registers location and length
-  For at91sam9263 and at91sam9g45 you must specify 2 entries.
-
-Examples:
-
-        ramc0: ramc@ffffe800 {
-                compatible = "atmel,at91sam9g45-ddramc";
-                reg = <0xffffe800 0x200>;
-        };
-
-        ramc0: ramc@ffffe400 {
-                compatible = "atmel,at91sam9g45-ddramc";
-                reg = <0xffffe400 0x200
-                       0xffffe600 0x200>;
-        };
-
-SHDWC Shutdown Controller
-
-required properties:
-- compatible: Should be "atmel,<chip>-shdwc".
-  <chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5".
-- reg: Should contain registers location and length
-
-optional properties:
-- atmel,wakeup-mode: String, operation mode of the wakeup mode.
-  Supported values are: "none", "high", "low", "any".
-- atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf).
-
-optional at91sam9260 properties:
-- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
-
-optional at91sam9rl properties:
-- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
-- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
-
-optional at91sam9x5 properties:
-- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
-
-Example:
-
-        rstc@fffffd00 {
-                compatible = "atmel,at91sam9260-rstc";
-                reg = <0xfffffd00 0x10>;
-        };
diff --git a/Documentation/devicetree/bindings/arm/atmel-pmc.txt b/Documentation/devicetree/bindings/arm/atmel-pmc.txt
deleted file mode 100644
index 389bed5056e..00000000000
--- a/Documentation/devicetree/bindings/arm/atmel-pmc.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-* Power Management Controller (PMC)
-
-Required properties:
-- compatible: Should be "atmel,at91rm9200-pmc"
-- reg: Should contain PMC registers location and length
-
-Examples:
-        pmc: pmc@fffffc00 {
-                compatible = "atmel,at91rm9200-pmc";
-                reg = <0xfffffc00 0x100>;
-        };
diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm11351.txt b/Documentation/devicetree/bindings/arm/bcm/bcm11351.txt
deleted file mode 100644
index fb7b5cd2652..00000000000
--- a/Documentation/devicetree/bindings/arm/bcm/bcm11351.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-Broadcom BCM11351 device tree bindings
--------------------------------------------
-
-Boards with the bcm281xx SoC family (which includes bcm11130, bcm11140,
-bcm11351, bcm28145, bcm28155 SoCs) shall have the following properties:
-
-Required root node property:
-
-compatible = "bcm,bcm11351";
diff --git a/Documentation/devicetree/bindings/arm/bcm2835.txt b/Documentation/devicetree/bindings/arm/bcm2835.txt
deleted file mode 100644
index ac683480c48..00000000000
--- a/Documentation/devicetree/bindings/arm/bcm2835.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-Broadcom BCM2835 device tree bindings
--------------------------------------------
-
-Boards with the BCM2835 SoC shall have the following properties:
-
-Required root node property:
-
-compatible = "brcm,bcm2835";
diff --git a/Documentation/devicetree/bindings/arm/calxeda.txt b/Documentation/devicetree/bindings/arm/calxeda.txt
deleted file mode 100644
index 25fcf96795c..00000000000
--- a/Documentation/devicetree/bindings/arm/calxeda.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-Calxeda Platforms Device Tree Bindings
------------------------------------------------
-
-Boards with Calxeda Cortex-A9 based ECX-1000 (Highbank) SOC shall have the
-following properties.
-
-Required root node properties:
-    - compatible = "calxeda,highbank";
-
-
-Boards with Calxeda Cortex-A15 based ECX-2000 SOC shall have the following
-properties.
-
-Required root node properties:
-    - compatible = "calxeda,ecx-2000";
diff --git a/Documentation/devicetree/bindings/arm/calxeda/combophy.txt b/Documentation/devicetree/bindings/arm/calxeda/combophy.txt
deleted file mode 100644
index 6622bdb2e8b..00000000000
--- a/Documentation/devicetree/bindings/arm/calxeda/combophy.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-Calxeda Highbank Combination Phys for SATA
-
-Properties:
-- compatible : Should be "calxeda,hb-combophy"
-- #phy-cells: Should be 1.
-- reg : Address and size for Combination Phy registers.
-- phydev: device ID for programming the combophy.
-
-Example:
-
-        combophy5: combo-phy@fff5d000 {
-                compatible = "calxeda,hb-combophy";
-                #phy-cells = <1>;
-                reg = <0xfff5d000 0x1000>;
-                phydev = <31>;
-        };
-
diff --git a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt
deleted file mode 100644
index 94e642a33db..00000000000
--- a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-Calxeda Highbank L2 cache ECC
-
-Properties:
-- compatible : Should be "calxeda,hb-sregs-l2-ecc"
-- reg : Address and size for ECC error interrupt clear registers.
-- interrupts : Should be single bit error interrupt, then double bit error
-        interrupt.
-
-Example:
-
-        sregs@fff3c200 {
-                compatible = "calxeda,hb-sregs-l2-ecc";
-                reg = <0xfff3c200 0x100>;
-                interrupts = <0 71 4  0 72 4>;
-        };
diff --git a/Documentation/devicetree/bindings/arm/calxeda/mem-ctrlr.txt b/Documentation/devicetree/bindings/arm/calxeda/mem-ctrlr.txt
deleted file mode 100644
index f770ac0893d..00000000000
--- a/Documentation/devicetree/bindings/arm/calxeda/mem-ctrlr.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-Calxeda DDR memory controller
-
-Properties:
-- compatible : Should be "calxeda,hb-ddr-ctrl"
-- reg : Address and size for DDR controller registers.
-- interrupts : Interrupt for DDR controller.
-
-Example:
-
-        memory-controller@fff00000 {
-                compatible = "calxeda,hb-ddr-ctrl";
-                reg = <0xfff00000 0x1000>;
-                interrupts = <0 91 4>;
-        };
diff --git a/Documentation/devicetree/bindings/arm/coherency-fabric.txt b/Documentation/devicetree/bindings/arm/coherency-fabric.txt
deleted file mode 100644
index 17d8cd10755..00000000000
--- a/Documentation/devicetree/bindings/arm/coherency-fabric.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-Coherency fabric
-----------------
-Available on Marvell SOCs: Armada 370 and Armada XP
-
-Required properties:
-
-- compatible: "marvell,coherency-fabric"
-
-- reg: Should contain coherency fabric registers location and
-  length. First pair for the coherency fabric registers, second pair
-  for the per-CPU fabric registers registers.
-
-Example:
-
-coherency-fabric@d0020200 {
-        compatible = "marvell,coherency-fabric";
-        reg = <0xd0020200 0xb0>,
-                <0xd0021810 0x1c>;
-
-};
-
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
deleted file mode 100644
index f32494dbfe1..00000000000
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ /dev/null
@@ -1,77 +0,0 @@
-* ARM CPUs binding description
-
-The device tree allows to describe the layout of CPUs in a system through
-the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
-defining properties for every cpu.
-
-Bindings for CPU nodes follow the ePAPR standard, available from:
-
-http://devicetree.org
-
-For the ARM architecture every CPU node must contain the following properties:
-
-- device_type:  must be "cpu"
-- reg:          property matching the CPU MPIDR[23:0] register bits
-                reg[31:24] bits must be set to 0
-- compatible:   should be one of:
-                "arm,arm1020"
-                "arm,arm1020e"
-                "arm,arm1022"
-                "arm,arm1026"
-                "arm,arm720"
-                "arm,arm740"
-                "arm,arm7tdmi"
-                "arm,arm920"
-                "arm,arm922"
-                "arm,arm925"
-                "arm,arm926"
-                "arm,arm940"
-                "arm,arm946"
-                "arm,arm9tdmi"
-                "arm,cortex-a5"
-                "arm,cortex-a7"
-                "arm,cortex-a8"
-                "arm,cortex-a9"
-                "arm,cortex-a15"
-                "arm,arm1136"
-                "arm,arm1156"
-                "arm,arm1176"
-                "arm,arm11mpcore"
-                "faraday,fa526"
-                "intel,sa110"
-                "intel,sa1100"
-                "marvell,feroceon"
-                "marvell,mohawk"
-                "marvell,xsc3"
-                "marvell,xscale"
-
-Example:
-
-        cpus {
-                #size-cells = <0>;
-                #address-cells = <1>;
-
-                CPU0: cpu@0 {
-                        device_type = "cpu";
-                        compatible = "arm,cortex-a15";
-                        reg = <0x0>;
-                };
-
-                CPU1: cpu@1 {
-                        device_type = "cpu";
-                        compatible = "arm,cortex-a15";
-                        reg = <0x1>;
-                };
-
-                CPU2: cpu@100 {
-                        device_type = "cpu";
-                        compatible = "arm,cortex-a7";
-                        reg = <0x100>;
-                };
-
-                CPU3: cpu@101 {
-                        device_type = "cpu";
-                        compatible = "arm,cortex-a7";
-                        reg = <0x101>;
-                };
-        };
diff --git a/Documentation/devicetree/bindings/arm/davinci.txt b/Documentation/devicetree/bindings/arm/davinci.txt
deleted file mode 100644
index cfaeda4274e..00000000000
--- a/Documentation/devicetree/bindings/arm/davinci.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-Texas Instruments DaVinci Platforms Device Tree Bindings
---------------------------------------------------------
-
-DA850/OMAP-L138/AM18x Evaluation Module (EVM) board
-Required root node properties:
-    - compatible = "ti,da850-evm", "ti,da850";
-
-EnBW AM1808 based CMC board
-Required root node properties:
-    - compatible = "enbw,cmc", "ti,da850;
-
-Generic DaVinci Boards
-----------------------
-
-DA850/OMAP-L138/AM18x generic board
-Required root node properties:
-    - compatible = "ti,da850";
diff --git a/Documentation/devicetree/bindings/arm/davinci/cp-intc.txt b/Documentation/devicetree/bindings/arm/davinci/cp-intc.txt
deleted file mode 100644
index 597e8a089fe..00000000000
--- a/Documentation/devicetree/bindings/arm/davinci/cp-intc.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-* TI Common Platform Interrupt Controller
-
-Common Platform Interrupt Controller (cp_intc) is used on
-OMAP-L1x SoCs and can support several configurable number
-of interrupts.
-
-Main node required properties:
-
-- compatible : should be:
-        "ti,cp-intc"
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an
-  interrupt source. The type shall be a <u32> and the value shall be 1.
-
-  The cell contains the interrupt number in the range [0-128].
-- ti,intc-size: Number of interrupts handled by the interrupt controller.
-- reg: physical base address and size of the intc registers map.
-
-Example:
-
-        intc: interrupt-controller@1 {
-                compatible = "ti,cp-intc";
-                interrupt-controller;
-                #interrupt-cells = <1>;
-                ti,intc-size = <101>;
-                reg = <0xfffee000 0x2000>;
-        };
diff --git a/Documentation/devicetree/bindings/arm/davinci/nand.txt b/Documentation/devicetree/bindings/arm/davinci/nand.txt
deleted file mode 100644
index 3545ea704b5..00000000000
--- a/Documentation/devicetree/bindings/arm/davinci/nand.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-* Texas Instruments Davinci NAND
-
-This file provides information, what the device node for the
-davinci nand interface contain.
-
-Required properties:
-- compatible: "ti,davinci-nand";
-- reg : contain 2 offset/length values:
-        - offset and length for the access window
-        - offset and length for accessing the aemif control registers
-- ti,davinci-chipselect: Indicates on the davinci_nand driver which
-                         chipselect is used for accessing the nand.
-
-Recommended properties :
-- ti,davinci-mask-ale: mask for ale
-- ti,davinci-mask-cle: mask for cle
-- ti,davinci-mask-chipsel: mask for chipselect
-- ti,davinci-ecc-mode: ECC mode valid values for davinci driver:
-                - "none"
-                - "soft"
-                - "hw"
-- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
-- ti,davinci-nand-buswidth: buswidth 8 or 16
-- ti,davinci-nand-use-bbt: use flash based bad block table support.
-
-nand device bindings may contain additional sub-nodes describing
-partitions of the address space. See partition.txt for more detail.
-
-Example(da850 EVM ):
-nand_cs3@62000000 {
-        compatible = "ti,davinci-nand";
-        reg = <0x62000000 0x807ff
-                0x68000000 0x8000>;
-        ti,davinci-chipselect = <1>;
-        ti,davinci-mask-ale = <0>;
-        ti,davinci-mask-cle = <0>;
-        ti,davinci-mask-chipsel = <0>;
-        ti,davinci-ecc-mode = "hw";
-        ti,davinci-ecc-bits = <4>;
-        ti,davinci-nand-use-bbt;
-
-        partition@180000 {
-                label = "ubifs";
-                reg = <0x180000 0x7e80000>;
-        };
-};
diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
deleted file mode 100644
index 5216b419016..00000000000
--- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-* Samsung Exynos Power Domains
-
-Exynos processors include support for multiple power domains which are used
-to gate power to one or more peripherals on the processor.
-
-Required Properties:
-- compatible: should be one of the following.
-    * samsung,exynos4210-pd - for exynos4210 type power domain.
-- reg: physical base address of the controller and length of memory mapped
-    region.
-
-Node of a device using power domains must have a samsung,power-domain property
-defined with a phandle to respective power domain.
-
-Example:
-
-        lcd0: power-domain-lcd0 {
-                compatible = "samsung,exynos4210-pd";
-                reg = <0x10023C00 0x10>;
-        };
-
-Example of the node using power domain:
-
-        node {
-                /* ... */
-                samsung,power-domain = <&lcd0>;
-                /* ... */
-        };
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
deleted file mode 100644
index f79818711e8..00000000000
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ /dev/null
@@ -1,68 +0,0 @@
-Freescale i.MX Platforms Device Tree Bindings
------------------------------------------------
-
-i.MX23 Evaluation Kit
-Required root node properties:
-    - compatible = "fsl,imx23-evk", "fsl,imx23";
-
-i.MX28 Evaluation Kit
-Required root node properties:
-    - compatible = "fsl,imx28-evk", "fsl,imx28";
-
-i.MX51 Babbage Board
-Required root node properties:
-    - compatible = "fsl,imx51-babbage", "fsl,imx51";
-
-i.MX53 Automotive Reference Design Board
-Required root node properties:
-    - compatible = "fsl,imx53-ard", "fsl,imx53";
-
-i.MX53 Evaluation Kit
-Required root node properties:
-    - compatible = "fsl,imx53-evk", "fsl,imx53";
-
-i.MX53 Quick Start Board
-Required root node properties:
-    - compatible = "fsl,imx53-qsb", "fsl,imx53";
-
-i.MX53 Smart Mobile Reference Design Board
-Required root node properties:
-    - compatible = "fsl,imx53-smd", "fsl,imx53";
-
-i.MX6 Quad Armadillo2 Board
-Required root node properties:
-    - compatible = "fsl,imx6q-arm2", "fsl,imx6q";
-
-i.MX6 Quad SABRE Lite Board
-Required root node properties:
-    - compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
-
-i.MX6 Quad SABRE Smart Device Board
-Required root node properties:
-    - compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
-
-i.MX6 Quad SABRE Automotive Board
-Required root node properties:
-    - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
-
-Generic i.MX boards
--------------------
-
-No iomux setup is done for these boards, so this must have been configured
-by the bootloader for boards to work with the generic bindings.
-
-i.MX27 generic board
-Required root node properties:
-    - compatible = "fsl,imx27";
-
-i.MX51 generic board
-Required root node properties:
-    - compatible = "fsl,imx51";
-
-i.MX53 generic board
-Required root node properties:
-    - compatible = "fsl,imx53";
-
-i.MX6q generic board
-Required root node properties:
-    - compatible = "fsl,imx6q";
diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
deleted file mode 100644
index 62eb8df1e08..00000000000
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ /dev/null
@@ -1,90 +0,0 @@
-* ARM Generic Interrupt Controller
-
-ARM SMP cores are often associated with a GIC, providing per processor
-interrupts (PPI), shared processor interrupts (SPI) and software
-generated interrupts (SGI).
-
-Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
-Secondary GICs are cascaded into the upward interrupt controller and do not
-have PPIs or SGIs.
-
-Main node required properties:
-
-- compatible : should be one of:
-        "arm,cortex-a15-gic"
-        "arm,cortex-a9-gic"
-        "arm,cortex-a7-gic"
-        "arm,arm11mp-gic"
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an
-  interrupt source.  The type shall be a <u32> and the value shall be 3.
-
-  The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
-  interrupts.
-
-  The 2nd cell contains the interrupt number for the interrupt type.
-  SPI interrupts are in the range [0-987].  PPI interrupts are in the
-  range [0-15].
-
-  The 3rd cell is the flags, encoded as follows:
-        bits[3:0] trigger type and level flags.
-                1 = low-to-high edge triggered
-                2 = high-to-low edge triggered
-                4 = active high level-sensitive
-                8 = active low level-sensitive
-        bits[15:8] PPI interrupt cpu mask.  Each bit corresponds to each of
-        the 8 possible cpus attached to the GIC.  A bit set to '1' indicated
-        the interrupt is wired to that CPU.  Only valid for PPI interrupts.
-
-- reg : Specifies base physical address(s) and size of the GIC registers. The
-  first region is the GIC distributor register base and size. The 2nd region is
-  the GIC cpu interface register base and size.
-
-Optional
-- interrupts    : Interrupt source of the parent interrupt controller on
-  secondary GICs, or VGIC maintainance interrupt on primary GIC (see
-  below).
-
-- cpu-offset    : per-cpu offset within the distributor and cpu interface
-  regions, used when the GIC doesn't have banked registers. The offset is
-  cpu-offset * cpu-nr.
-
-Example:
-
-        intc: interrupt-controller@fff11000 {
-                compatible = "arm,cortex-a9-gic";
-                #interrupt-cells = <3>;
-                #address-cells = <1>;
-                interrupt-controller;
-                reg = <0xfff11000 0x1000>,
-                      <0xfff10100 0x100>;
-        };
-
-
-* GIC virtualization extensions (VGIC)
-
-For ARM cores that support the virtualization extensions, additional
-properties must be described (they only exist if the GIC is the
-primary interrupt controller).
-
-Required properties:
-
-- reg : Additional regions specifying the base physical address and
-  size of the VGIC registers. The first additional region is the GIC
-  virtual interface control register base and size. The 2nd additional
-  region is the GIC virtual cpu interface register base and size.
-
-- interrupts : VGIC maintainance interrupt.
-
-Example:
-
-        interrupt-controller@2c001000 {
-                compatible = "arm,cortex-a15-gic";
-                #interrupt-cells = <3>;
-                interrupt-controller;
-                reg = <0x2c001000 0x1000>,
-                      <0x2c002000 0x1000>,
-                      <0x2c004000 0x2000>,
-                      <0x2c006000 0x2000>;
-                interrupts = <1 9 0xf04>;
-        };
diff --git a/Documentation/devicetree/bindings/arm/insignal-boards.txt b/Documentation/devicetree/bindings/arm/insignal-boards.txt
deleted file mode 100644
index 524c3dc5d80..00000000000
--- a/Documentation/devicetree/bindings/arm/insignal-boards.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-* Insignal's Exynos4210 based Origen evaluation board
-
-Origen low-cost evaluation board is based on Samsung's Exynos4210 SoC.
-
-Required root node properties:
-    - compatible = should be one or more of the following.
-        (a) "samsung,smdkv310" - for Samsung's SMDKV310 eval board.
-        (b) "samsung,exynos4210"  - for boards based on Exynos4210 SoC.
diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
deleted file mode 100644
index cbef09b5c8a..00000000000
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ /dev/null
@@ -1,53 +0,0 @@
-* ARM L2 Cache Controller
-
-ARM cores often have a separate level 2 cache controller. There are various
-implementations of the L2 cache controller with compatible programming models.
-The ARM L2 cache representation in the device tree should be done as follows:
-
-Required properties:
-
-- compatible : should be one of:
-        "arm,pl310-cache"
-        "arm,l220-cache"
-        "arm,l210-cache"
-        "marvell,aurora-system-cache": Marvell Controller designed to be
-     compatible with the ARM one, with system cache mode (meaning
-     maintenance operations on L1 are broadcasted to the L2 and L2
-     performs the same operation).
-        "marvell,"aurora-outer-cache: Marvell Controller designed to be
-         compatible with the ARM one with outer cache mode.
-- cache-unified : Specifies the cache is a unified cache.
-- cache-level : Should be set to 2 for a level 2 cache.
-- reg : Physical base address and size of cache controller's memory mapped
-  registers.
-
-Optional properties:
-
-- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of
-  read, write and setup latencies. Minimum valid values are 1. Controllers
-  without setup latency control should use a value of 0.
-- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of
-  read, write and setup latencies. Controllers without setup latency control
-  should use 0. Controllers without separate read and write Tag RAM latency
-  values should only use the first cell.
-- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.
-- arm,filter-ranges : <start length> Starting address and length of window to
-  filter. Addresses in the filter window are directed to the M1 port. Other
-  addresses will go to the M0 port.
-- interrupts : 1 combined interrupt.
-- cache-id-part: cache id part number to be used if it is not present
-  on hardware
-- wt-override: If present then L2 is forced to Write through mode
-
-Example:
-
-L2: cache-controller {
-        compatible = "arm,pl310-cache";
-        reg = <0xfff12000 0x1000>;
-        arm,data-latency = <1 1 1>;
-        arm,tag-latency = <2 2 2>;
-        arm,filter-ranges = <0x80000000 0x8000000>;
-        cache-unified;
-        cache-level = <2>;
-        interrupts = <45>;
-};
diff --git a/Documentation/devicetree/bindings/arm/lpc32xx-mic.txt b/Documentation/devicetree/bindings/arm/lpc32xx-mic.txt
deleted file mode 100644
index 539adca19e8..00000000000
--- a/Documentation/devicetree/bindings/arm/lpc32xx-mic.txt
+++ /dev/null
@@ -1,38 +0,0 @@
-* NXP LPC32xx Main Interrupt Controller
-  (MIC, including SIC1 and SIC2 secondary controllers)
-
-Required properties:
-- compatible: Should be "nxp,lpc3220-mic"
-- interrupt-controller: Identifies the node as an interrupt controller.
-- interrupt-parent: Empty for the interrupt controller itself
-- #interrupt-cells: The number of cells to define the interrupts. Should be 2.
-  The first cell is the IRQ number
-  The second cell is used to specify mode:
-      1 = low-to-high edge triggered
-      2 = high-to-low edge triggered
-      4 = active high level-sensitive
-      8 = active low level-sensitive
-      Default for internal sources should be set to 4 (active high).
-- reg: Should contain MIC registers location and length
-
-Examples:
-        /*
-         * MIC
-         */
-        mic: interrupt-controller@40008000 {
-                compatible = "nxp,lpc3220-mic";
-                interrupt-controller;
-                interrupt-parent;
-                #interrupt-cells = <2>;
-                reg = <0x40008000 0xC000>;
-        };
-
-        /*
-         * ADC
-         */
-        adc@40048000 {
-                compatible = "nxp,lpc3220-adc";
-                reg = <0x40048000 0x1000>;
-                interrupt-parent = <&mic>;
-                interrupts = <39 4>;
-        };
diff --git a/Documentation/devicetree/bindings/arm/lpc32xx.txt b/Documentation/devicetree/bindings/arm/lpc32xx.txt
deleted file mode 100644
index 56ec8ddc4a3..00000000000
--- a/Documentation/devicetree/bindings/arm/lpc32xx.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-NXP LPC32xx Platforms Device Tree Bindings
-------------------------------------------
-
-Boards with the NXP LPC32xx SoC shall have the following properties:
-
-Required root node property:
-
-compatible: must be "nxp,lpc3220", "nxp,lpc3230", "nxp,lpc3240" or "nxp,lpc3250"
diff --git a/Documentation/devicetree/bindings/arm/mrvl/intc.txt b/Documentation/devicetree/bindings/arm/mrvl/intc.txt
deleted file mode 100644
index 8b53273cb22..00000000000
--- a/Documentation/devicetree/bindings/arm/mrvl/intc.txt
+++ /dev/null
@@ -1,60 +0,0 @@
-* Marvell MMP Interrupt controller
-
-Required properties:
-- compatible : Should be "mrvl,mmp-intc", "mrvl,mmp2-intc" or
-  "mrvl,mmp2-mux-intc"
-- reg : Address and length of the register set of the interrupt controller.
-  If the interrupt controller is intc, address and length means the range
-  of the whold interrupt controller. If the interrupt controller is mux-intc,
-  address and length means one register. Since address of mux-intc is in the
-  range of intc. mux-intc is secondary interrupt controller.
-- reg-names : Name of the register set of the interrupt controller. It's
-  only required in mux-intc interrupt controller.
-- interrupts : Should be the port interrupt shared by mux interrupts. It's
-  only required in mux-intc interrupt controller.
-- interrupt-controller : Identifies the node as an interrupt controller.
-- #interrupt-cells : Specifies the number of cells needed to encode an
-  interrupt source.
-- mrvl,intc-nr-irqs : Specifies the number of interrupts in the interrupt
-  controller.
-- mrvl,clr-mfp-irq : Specifies the interrupt that needs to clear MFP edge
-  detection first.
-
-Example:
-        intc: interrupt-controller@d4282000 {
-                compatible = "mrvl,mmp2-intc";
-                interrupt-controller;
-                #interrupt-cells = <1>;
-                reg = <0xd4282000 0x1000>;
-                mrvl,intc-nr-irqs = <64>;
-        };
-
-        intcmux4@d4282150 {
-                compatible = "mrvl,mmp2-mux-intc";
-                interrupts = <4>;
-                interrupt-controller;
-                #interrupt-cells = <1>;
-                reg = <0x150 0x4>, <0x168 0x4>;
-                reg-names = "mux status", "mux mask";
-                mrvl,intc-nr-irqs = <2>;
-        };
-
-* Marvell Orion Interrupt controller
-
-Required properties
-- compatible :  Should be "marvell,orion-intc".
-- #interrupt-cells: Specifies the number of cells needed to encode an
-  interrupt source. Supported value is <1>.
-- interrupt-controller : Declare this node to be an interrupt controller.
-- reg : Interrupt mask address. A list of 4 byte ranges, one per controller.
-        One entry in the list represents 32 interrupts.
-
-Example:
-
-        intc: interrupt-controller {
-                compatible = "marvell,orion-intc", "marvell,intc";
-                interrupt-controller;
-                #interrupt-cells = <1>;
-                reg = <0xfed20204 0x04>,
-                      <0xfed20214 0x04>;
-        };
diff --git a/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt b/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt
deleted file mode 100644
index 117d741a2e4..00000000000
--- a/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-Marvell Platforms Device Tree Bindings
-----------------------------------------------------
-
-PXA168 Aspenite Board
-Required root node properties:
-        - compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168";
-
-PXA910 DKB Board
-Required root node properties:
-        - compatible = "mrvl,pxa910-dkb";
-
-MMP2 Brownstone Board
-Required root node properties:
-        - compatible = "mrvl,mmp2-brownstone";
diff --git a/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt b/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt
deleted file mode 100644
index 31af1cbb60b..00000000000
--- a/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-* Marvell Tauros2 Cache
-
-Required properties:
-- compatible : Should be "marvell,tauros2-cache".
-- marvell,tauros2-cache-features : Specify the features supported for the
-  tauros2 cache.
-  The features including
-    CACHE_TAUROS2_PREFETCH_ON       (1 << 0)
-    CACHE_TAUROS2_LINEFILL_BURST8   (1 << 1)
-  The definition can be found at
-  arch/arm/include/asm/hardware/cache-tauros2.h
-
-Example:
-        L2: l2-cache {
-                compatible = "marvell,tauros2-cache";
-                marvell,tauros2-cache-features = <0x3>;
-        };
diff --git a/Documentation/devicetree/bindings/arm/mrvl/timer.txt b/Documentation/devicetree/bindings/arm/mrvl/timer.txt
deleted file mode 100644
index 9a6e251462e..00000000000
--- a/Documentation/devicetree/bindings/arm/mrvl/timer.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-* Marvell MMP Timer controller
-
-Required properties:
-- compatible : Should be "mrvl,mmp-timer".
-- reg : Address and length of the register set of timer controller.
-- interrupts : Should be the interrupt number.
-
-Example:
-        timer0: timer@d4014000 {
-                compatible = "mrvl,mmp-timer";
-                reg = <0xd4014000 0x100>;
-                interrupts = <13>;
-        };
diff --git a/Documentation/devicetree/bindings/arm/msm/timer.txt b/Documentation/devicetree/bindings/arm/msm/timer.txt
deleted file mode 100644
index 8c5907b9cae..00000000000
--- a/Documentation/devicetree/bindings/arm/msm/timer.txt
+++ /dev/null
@@ -1,38 +0,0 @@
-* MSM Timer
-
-Properties:
-
-- compatible : Should at least contain "qcom,msm-timer". More specific
-  properties such as "qcom,msm-gpt" and "qcom,msm-dgt" specify a general
-  purpose timer and a debug timer respectively.
-
-- interrupts : Interrupt indicating a match event.
-
-- reg : Specifies the base address of the timer registers. The second region
-  specifies an optional register used to configure the clock divider.
-
-- clock-frequency : The frequency of the timer in Hz.
-
-Optional:
-
-- cpu-offset : per-cpu offset used when the timer is accessed without the
-  CPU remapping facilities. The offset is cpu-offset * cpu-nr.
-
-Example:
-
-       timer@200a004 {
-               compatible = "qcom,msm-gpt", "qcom,msm-timer";
-               interrupts = <1 2 0x301>;
-               reg = <0x0200a004 0x10>;
-               clock-frequency = <32768>;
-               cpu-offset = <0x40000>;
-       };
-
-       timer@200a024 {
-               compatible = "qcom,msm-dgt", "qcom,msm-timer";
-               interrupts = <1 3 0x301>;
-               reg = <0x0200a024 0x10>,
-                     <0x0200a034 0x4>;
-               clock-frequency = <6750000>;
-               cpu-offset = <0x40000>;
-       };
diff --git a/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt b/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt
deleted file mode 100644
index 081c6a786c8..00000000000
--- a/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-MVEBU System Controller
------------------------
-MVEBU (Marvell SOCs: Armada 370/XP, Dove, mv78xx0, Kirkwood, Orion5x)
-
-Required properties:
-
-- compatible: one of:
-        - "marvell,orion-system-controller"
-        - "marvell,armada-370-xp-system-controller"
-- reg: Should contain system controller registers location and length.
-
-Example:
-
-        system-controller@d0018200 {
-                compatible = "marvell,armada-370-xp-system-controller";
-                reg = <0xd0018200 0x500>;
-        };
diff --git a/Documentation/devicetree/bindings/arm/olimex.txt b/Documentation/devicetree/bindings/arm/olimex.txt
deleted file mode 100644
index 007fb5c685a..00000000000
--- a/Documentation/devicetree/bindings/arm/olimex.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Olimex i.MX Platforms Device Tree Bindings
-------------------------------------------
-
-i.MX23 Olinuxino Low Cost Board
-Required root node properties:
-    - compatible = "olimex,imx23-olinuxino", "fsl,imx23";
diff --git a/Documentation/devicetree/bindings/arm/omap/counter.txt b/Documentation/devicetree/bindings/arm/omap/counter.txt
deleted file mode 100644
index 5bd8aa09131..00000000000
--- a/Documentation/devicetree/bindings/arm/omap/counter.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-OMAP Counter-32K bindings
-
-Required properties:
-- compatible:   Must be "ti,omap-counter32k" for OMAP controllers
-- reg:          Contains timer register address range (base address and length)
-- ti,hwmods:    Name of the hwmod associated to the counter, which is typically
-                "counter_32k"
-
-Example:
-
-counter32k: counter@4a304000 {
-        compatible = "ti,omap-counter32k";
-        reg = <0x4a304000 0x20>;
-        ti,hwmods = "counter_32k";
-};
diff --git a/Documentation/devicetree/bindings/arm/omap/dsp.txt b/Documentation/devicetree/bindings/arm/omap/dsp.txt
deleted file mode 100644
index d3830a32ce0..00000000000
--- a/Documentation/devicetree/bindings/arm/omap/dsp.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-* TI - DSP (Digital Signal Processor)
-
-TI DSP included in OMAP SoC
-
-Required properties:
-- compatible : Should be "ti,omap3-c64" for OMAP3 & 4
-- ti,hwmods: "dsp"
-
-Examples:
-
-dsp {
-    compatible = "ti,omap3-c64";
-    ti,hwmods = "dsp";
-};
diff --git a/Documentation/devicetree/bindings/arm/omap/intc.txt b/Documentation/devicetree/bindings/arm/omap/intc.txt
deleted file mode 100644
index f2583e6ec06..00000000000
--- a/Documentation/devicetree/bindings/arm/omap/intc.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-* OMAP Interrupt Controller
-
-OMAP2/3 are using a TI interrupt controller that can support several
-configurable number of interrupts.
-
-Main node required properties:
-
-- compatible : should be:
-        "ti,omap2-intc"
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an
-  interrupt source. The type shall be a <u32> and the value shall be 1.
-
-  The cell contains the interrupt number in the range [0-128].
-- ti,intc-size: Number of interrupts handled by the interrupt controller.
-- reg: physical base address and size of the intc registers map.
-
-Example:
-
-        intc: interrupt-controller@1 {
-                compatible = "ti,omap2-intc";
-                interrupt-controller;
-                #interrupt-cells = <1>;
-                ti,intc-size = <96>;
-                reg = <0x48200000 0x1000>;
-        };
-
diff --git a/Documentation/devicetree/bindings/arm/omap/iva.txt b/Documentation/devicetree/bindings/arm/omap/iva.txt
deleted file mode 100644
index 6d629517135..00000000000
--- a/Documentation/devicetree/bindings/arm/omap/iva.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-* TI - IVA (Imaging and Video Accelerator) subsystem
-
-The IVA contain various audio, video or imaging HW accelerator
-depending of the version.
-
-Required properties:
-- compatible : Should be:
-  - "ti,ivahd" for OMAP4
-  - "ti,iva2.2" for OMAP3
-  - "ti,iva2.1" for OMAP2430
-  - "ti,iva1" for OMAP2420
-- ti,hwmods: "iva"
-
-Examples:
-
-iva {
-    compatible = "ti,ivahd", "ti,iva";
-    ti,hwmods = "iva";
-};
diff --git a/Documentation/devicetree/bindings/arm/omap/l3-noc.txt b/Documentation/devicetree/bindings/arm/omap/l3-noc.txt
deleted file mode 100644
index 6888a5efc86..00000000000
--- a/Documentation/devicetree/bindings/arm/omap/l3-noc.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-* TI - L3 Network On Chip (NoC)
-
-This version is an implementation of the generic NoC IP
-provided by Arteris.
-
-Required properties:
-- compatible : Should be "ti,omap3-l3-smx" for OMAP3 family
-               Should be "ti,omap4-l3-noc" for OMAP4 family
-- ti,hwmods: "l3_main_1", ... One hwmod for each noc domain.
-
-Examples:
-
-ocp {
-        compatible = "ti,omap4-l3-noc", "simple-bus";
-        #address-cells = <1>;
-        #size-cells = <1>;
-        ranges;
-        ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
-};
diff --git a/Documentation/devicetree/bindings/arm/omap/mpu.txt b/Documentation/devicetree/bindings/arm/omap/mpu.txt
deleted file mode 100644
index 1a5a42ce21b..00000000000
--- a/Documentation/devicetree/bindings/arm/omap/mpu.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-* TI - MPU (Main Processor Unit) subsystem
-
-The MPU subsystem contain one or several ARM cores
-depending of the version.
-The MPU contain CPUs, GIC, L2 cache and a local PRCM.
-
-Required properties:
-- compatible : Should be "ti,omap3-mpu" for OMAP3
-               Should be "ti,omap4-mpu" for OMAP4
-- ti,hwmods: "mpu"
-
-Examples:
-
-- For an OMAP4 SMP system:
-
-mpu {
-    compatible = "ti,omap4-mpu";
-    ti,hwmods = "mpu";
-};
-
-
-- For an OMAP3 monocore system:
-
-mpu {
-    compatible = "ti,omap3-mpu";
-    ti,hwmods = "mpu";
-};
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
deleted file mode 100644
index d0051a75058..00000000000
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-* Texas Instruments OMAP
-
-OMAP is currently using a static file per SoC family to describe the
-IPs present in the SoC.
-On top of that an omap_device is created to extend the platform_device
-capabilities and to allow binding with one or several hwmods.
-The hwmods will contain all the information to build the device:
-address range, irq lines, dma lines, interconnect, PRCM register,
-clock domain, input clocks.
-For the moment just point to the existing hwmod, the next step will be
-to move data from hwmod to device-tree representation.
-
-
-Required properties:
-- compatible: Every devices present in OMAP SoC should be in the
-  form: "ti,XXX"
-- ti,hwmods: list of hwmod names (ascii strings), that comes from the OMAP
-  HW documentation, attached to a device. Must contain at least
-  one hwmod.
-
-Optional properties:
-- ti,no_idle_on_suspend: When present, it prevents the PM to idle the module
-  during suspend.
-
-
-Example:
-
-spinlock@1 {
-    compatible = "ti,omap4-spinlock";
-    ti,hwmods = "spinlock";
-};
-
-
-Boards:
-
-- OMAP3 BeagleBoard : Low cost community board
-  compatible = "ti,omap3-beagle", "ti,omap3"
-
-- OMAP3 Tobi with Overo : Commercial expansion board with daughter board
-  compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3"
-
-- OMAP4 SDP : Software Developement Board
-  compatible = "ti,omap4-sdp", "ti,omap4430"
-
-- OMAP4 PandaBoard : Low cost community board
-  compatible = "ti,omap4-panda", "ti,omap4430"
-
-- OMAP3 EVM : Software Developement Board for OMAP35x, AM/DM37x
-  compatible = "ti,omap3-evm", "ti,omap3"
-
-- AM335X EVM : Software Developement Board for AM335x
-  compatible = "ti,am335x-evm", "ti,am33xx", "ti,omap3"
-
-- AM335X Bone : Low cost community board
-  compatible = "ti,am335x-bone", "ti,am33xx", "ti,omap3"
-
-- OMAP5 EVM : Evaluation Module
-  compatible = "ti,omap5-evm", "ti,omap5"
diff --git a/Documentation/devicetree/bindings/arm/omap/timer.txt b/Documentation/devicetree/bindings/arm/omap/timer.txt
deleted file mode 100644
index 8732d4d41f8..00000000000
--- a/Documentation/devicetree/bindings/arm/omap/timer.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-OMAP Timer bindings
-
-Required properties:
-- compatible:           Must be "ti,omap2-timer" for OMAP2+ controllers.
-- reg:                  Contains timer register address range (base address and
-                        length).
-- interrupts:           Contains the interrupt information for the timer. The
-                        format is being dependent on which interrupt controller
-                        the OMAP device uses.
-- ti,hwmods:            Name of the hwmod associated to the timer, "timer<X>",
-                        where <X> is the instance number of the timer from the
-                        HW spec.
-
-Optional properties:
-- ti,timer-alwon:       Indicates the timer is in an alway-on power domain.
-- ti,timer-dsp:         Indicates the timer can interrupt the on-chip DSP in
-                        addition to the ARM CPU.
-- ti,timer-pwm:         Indicates the timer can generate a PWM output.
-- ti,timer-secure:      Indicates the timer is reserved on a secure OMAP device
-                        and therefore cannot be used by the kernel.
-
-Example:
-
-timer12: timer@48304000 {
-        compatible = "ti,omap2-timer";
-        reg = <0x48304000 0x400>;
-        interrupts = <95>;
-        ti,hwmods = "timer12"
-        ti,timer-alwon;
-        ti,timer-secure;
-};
diff --git a/Documentation/devicetree/bindings/arm/picoxcell.txt b/Documentation/devicetree/bindings/arm/picoxcell.txt
deleted file mode 100644
index e75c0ef51e6..00000000000
--- a/Documentation/devicetree/bindings/arm/picoxcell.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-Picochip picoXcell device tree bindings.
-========================================
-
-Required root node properties:
-    - compatible:
-        - "picochip,pc7302-pc3x3" : PC7302 development board with PC3X3 device.
-        - "picochip,pc7302-pc3x2" : PC7302 development board with PC3X2 device.
-        - "picochip,pc3x3" : picoXcell PC3X3 device based board.
-        - "picochip,pc3x2" : picoXcell PC3X2 device based board.
-
-Timers required properties:
-    - compatible = "picochip,pc3x2-timer"
-    - interrupts : The single IRQ line for the timer.
-    - clock-freq : The frequency in HZ of the timer.
-    - reg : The register bank for the timer.
-
-Note: two timers are required - one for the scheduler clock and one for the
-event tick/NOHZ.
-
-VIC required properties:
-    - compatible = "arm,pl192-vic".
-    - interrupt-controller.
-    - reg : The register bank for the device.
-    - #interrupt-cells : Must be 1.
diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt
index 343781b9f24..1c044eb320c 100644
--- a/Documentation/devicetree/bindings/arm/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/pmu.txt
@@ -7,12 +7,8 @@ representation in the device tree should be done as under:-
 Required properties:
 
 - compatible : should be one of
-        "arm,cortex-a15-pmu"
         "arm,cortex-a9-pmu"
         "arm,cortex-a8-pmu"
-        "arm,cortex-a7-pmu"
-        "arm,cortex-a5-pmu"
-        "arm,arm11mpcore-pmu"
         "arm,arm1176-pmu"
         "arm,arm1136-pmu"
 - interrupts : 1 combined interrupt or 1 per core.
diff --git a/Documentation/devicetree/bindings/arm/primecell.txt b/Documentation/devicetree/bindings/arm/primecell.txt
index 64fc82bc892..1d5d7a870ec 100644
--- a/Documentation/devicetree/bindings/arm/primecell.txt
+++ b/Documentation/devicetree/bindings/arm/primecell.txt
@@ -6,24 +6,16 @@ driver matching.
 
 Required properties:
 
-- compatible : should be a specific name for the peripheral and
-               "arm,primecell".  The specific name will match the ARM
-               engineering name for the logic block in the form: "arm,pl???"
+- compatible : should be a specific value for peripheral and "arm,primecell"
 
 Optional properties:
 
 - arm,primecell-periphid : Value to override the h/w value with
-- clocks : From common clock binding. First clock is phandle to clock for apb
-        pclk. Additional clocks are optional and specific to those peripherals.
-- clock-names : From common clock binding. Shall be "apb_pclk" for first clock.
 
 Example:
 
 serial@fff36000 {
         compatible = "arm,pl011", "arm,primecell";
         arm,primecell-periphid = <0x00341011>;
-        clocks = <&pclk>;
-        clock-names = "apb_pclk";
-        
 };
 
diff --git a/Documentation/devicetree/bindings/arm/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung-boards.txt
deleted file mode 100644
index 0bf68be56fd..00000000000
--- a/Documentation/devicetree/bindings/arm/samsung-boards.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-* Samsung's Exynos4210 based SMDKV310 evaluation board
-
-SMDKV310 evaluation board is based on Samsung's Exynos4210 SoC.
-
-Required root node properties:
-    - compatible = should be one or more of the following.
-        (a) "samsung,smdkv310" - for Samsung's SMDKV310 eval board.
-        (b) "samsung,exynos4210"  - for boards based on Exynos4210 SoC.
diff --git a/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt b/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt
deleted file mode 100644
index f2f2171e530..00000000000
--- a/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt
+++ /dev/null
@@ -1,52 +0,0 @@
-* Samsung Exynos Interrupt Combiner Controller
-
-Samsung's Exynos4 architecture includes a interrupt combiner controller which
-can combine interrupt sources as a group and provide a single interrupt request
-for the group. The interrupt request from each group are connected to a parent
-interrupt controller, such as GIC in case of Exynos4210.
-
-The interrupt combiner controller consists of multiple combiners. Upto eight
-interrupt sources can be connected to a combiner. The combiner outputs one
-combined interrupt for its eight interrupt sources. The combined interrupt
-is usually connected to a parent interrupt controller.
-
-A single node in the device tree is used to describe the interrupt combiner
-controller module (which includes multiple combiners). A combiner in the
-interrupt controller module shares config/control registers with other
-combiners. For example, a 32-bit interrupt enable/disable config register
-can accommodate upto 4 interrupt combiners (with each combiner supporting
-upto 8 interrupt sources).
-
-Required properties:
-- compatible: should be "samsung,exynos4210-combiner".
-- interrupt-controller: Identifies the node as an interrupt controller.
-- #interrupt-cells: should be <2>. The meaning of the cells are
-        * First Cell: Combiner Group Number.
-        * Second Cell: Interrupt number within the group.
-- reg: Base address and size of interrupt combiner registers.
-- interrupts: The list of interrupts generated by the combiners which are then
-    connected to a parent interrupt controller. The format of the interrupt
-    specifier depends in the interrupt parent controller.
-
-Optional properties:
-- samsung,combiner-nr: The number of interrupt combiners supported. If this
-  property is not specified, the default number of combiners is assumed
-  to be 16.
-- interrupt-parent: pHandle of the parent interrupt controller, if not
-  inherited from the parent node.
-
-
-Example:
-
-        The following is a an example from the Exynos4210 SoC dtsi file.
-
-        combiner:interrupt-controller@10440000 {
-                compatible = "samsung,exynos4210-combiner";
-                interrupt-controller;
-                #interrupt-cells = <2>;
-                reg = <0x10440000 0x1000>;
-                interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
-                             <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
-                             <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
-                             <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
-        };
diff --git a/Documentation/devicetree/bindings/arm/sirf.txt b/Documentation/devicetree/bindings/arm/sirf.txt
index 1881e1c6dda..6b07f65b32d 100644
--- a/Documentation/devicetree/bindings/arm/sirf.txt
+++ b/Documentation/devicetree/bindings/arm/sirf.txt
@@ -1,3 +1,3 @@
-prima2 "cb" evaluation board
+prima2 "cb" evalutation board
 Required root node properties:
     - compatible = "sirf,prima2-cb", "sirf,prima2";
diff --git a/Documentation/devicetree/bindings/arm/spear-timer.txt b/Documentation/devicetree/bindings/arm/spear-timer.txt
deleted file mode 100644
index c0017221cf5..00000000000
--- a/Documentation/devicetree/bindings/arm/spear-timer.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-* SPEAr ARM Timer
-
-** Timer node required properties:
-
-- compatible : Should be:
-        "st,spear-timer"
-- reg: Address range of the timer registers
-- interrupt-parent: Should be the phandle for the interrupt controller
-  that services interrupts for this device
-- interrupt: Should contain the timer interrupt number
-
-Example:
-
-        timer@f0000000 {
-                compatible = "st,spear-timer";
-                reg = <0xf0000000 0x400>;
-                interrupts = <2>;
-        };
diff --git a/Documentation/devicetree/bindings/arm/spear.txt b/Documentation/devicetree/bindings/arm/spear.txt
deleted file mode 100644
index 0d42949df6c..00000000000
--- a/Documentation/devicetree/bindings/arm/spear.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-ST SPEAr Platforms Device Tree Bindings
----------------------------------------
-
-Boards with the ST SPEAr600 SoC shall have the following properties:
-Required root node property:
-compatible = "st,spear600";
-
-Boards with the ST SPEAr300 SoC shall have the following properties:
-Required root node property:
-compatible = "st,spear300";
-
-Boards with the ST SPEAr310 SoC shall have the following properties:
-Required root node property:
-compatible = "st,spear310";
-
-Boards with the ST SPEAr320 SoC shall have the following properties:
-Required root node property:
-compatible = "st,spear320";
-
-Boards with the ST SPEAr1310 SoC shall have the following properties:
-Required root node property:
-compatible = "st,spear1310";
-
-Boards with the ST SPEAr1340 SoC shall have the following properties:
-Required root node property:
-compatible = "st,spear1340";
diff --git a/Documentation/devicetree/bindings/arm/spear/shirq.txt b/Documentation/devicetree/bindings/arm/spear/shirq.txt
deleted file mode 100644
index 13fbb8866bd..00000000000
--- a/Documentation/devicetree/bindings/arm/spear/shirq.txt
+++ /dev/null
@@ -1,48 +0,0 @@
-* SPEAr Shared IRQ layer (shirq)
-
-SPEAr3xx architecture includes shared/multiplexed irqs for certain set
-of devices. The multiplexor provides a single interrupt to parent
-interrupt controller (VIC) on behalf of a group of devices.
-
-There can be multiple groups available on SPEAr3xx variants but not
-exceeding 4. The number of devices in a group can differ, further they
-may share same set of status/mask registers spanning across different
-bit masks. Also in some cases the group may not have enable or other
-registers. This makes software little complex.
-
-A single node in the device tree is used to describe the shared
-interrupt multiplexor (one node for all groups). A group in the
-interrupt controller shares config/control registers with other groups.
-For example, a 32-bit interrupt enable/disable config register can
-accommodate upto 4 interrupt groups.
-
-Required properties:
-  - compatible: should be, either of
-     - "st,spear300-shirq"
-     - "st,spear310-shirq"
-     - "st,spear320-shirq"
-  - interrupt-controller: Identifies the node as an interrupt controller.
-  - #interrupt-cells: should be <1> which basically contains the offset
-    (starting from 0) of interrupts for all the groups.
-  - reg: Base address and size of shirq registers.
-  - interrupts: The list of interrupts generated by the groups which are
-    then connected to a parent interrupt controller. Each group is
-    associated with one of the interrupts, hence number of interrupts (to
-    parent) is equal to number of groups. The format of the interrupt
-    specifier depends in the interrupt parent controller.
-
-  Optional properties:
-  - interrupt-parent: pHandle of the parent interrupt controller, if not
-    inherited from the parent node.
-
-Example:
-
-The following is an example from the SPEAr320 SoC dtsi file.
-
-shirq: interrupt-controller@0xb3000000 {
-        compatible = "st,spear320-shirq";
-        reg = <0xb3000000 0x1000>;
-        interrupts = <28 29 30 1>;
-        #interrupt-cells = <1>;
-        interrupt-controller;
-};
diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt
deleted file mode 100644
index 6e69d2e5e76..00000000000
--- a/Documentation/devicetree/bindings/arm/tegra.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-NVIDIA Tegra device tree bindings
--------------------------------------------
-
-Boards with the tegra20 SoC shall have the following properties:
-
-Required root node property:
-
-compatible = "nvidia,tegra20";
-
-Boards with the tegra30 SoC shall have the following properties:
-
-Required root node property:
-
-compatible = "nvidia,tegra30";
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt
deleted file mode 100644
index 234406d41c1..00000000000
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-NVIDIA Tegra AHB
-
-Required properties:
-- compatible : "nvidia,tegra20-ahb" or "nvidia,tegra30-ahb"
-- reg : Should contain 1 register ranges(address and length)
-
-Example:
-        ahb: ahb@6000c004 {
-                compatible = "nvidia,tegra20-ahb";
-                reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
-        };
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt
deleted file mode 100644
index 4c33b29dc66..00000000000
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt
+++ /dev/null
@@ -1,100 +0,0 @@
-Embedded Memory Controller
-
-Properties:
-- name : Should be emc
-- #address-cells : Should be 1
-- #size-cells : Should be 0
-- compatible : Should contain "nvidia,tegra20-emc".
-- reg : Offset and length of the register set for the device
-- nvidia,use-ram-code : If present, the sub-nodes will be addressed
-  and chosen using the ramcode board selector. If omitted, only one
-  set of tables can be present and said tables will be used
-  irrespective of ram-code configuration.
-
-Child device nodes describe the memory settings for different configurations and clock rates.
-
-Example:
-
-        memory-controller@7000f400 {
-                #address-cells = < 1 >;
-                #size-cells = < 0 >;
-                compatible = "nvidia,tegra20-emc";
-                reg = <0x7000f4000 0x200>;
-        }
-
-
-Embedded Memory Controller ram-code table
-
-If the emc node has the nvidia,use-ram-code property present, then the
-next level of nodes below the emc table are used to specify which settings
-apply for which ram-code settings.
-
-If the emc node lacks the nvidia,use-ram-code property, this level is omitted
-and the tables are stored directly under the emc node (see below).
-
-Properties:
-
-- name : Should be emc-tables
-- nvidia,ram-code : the binary representation of the ram-code board strappings
-  for which this node (and children) are valid.
-
-
-
-Embedded Memory Controller configuration table
-
-This is a table containing the EMC register settings for the various
-operating speeds of the memory controller. They are always located as
-subnodes of the emc controller node.
-
-There are two ways of specifying which tables to use:
-
-* The simplest is if there is just one set of tables in the device tree,
-  and they will always be used (based on which frequency is used).
-  This is the preferred method, especially when firmware can fill in
-  this information based on the specific system information and just
-  pass it on to the kernel.
-
-* The slightly more complex one is when more than one memory configuration
-  might exist on the system.  The Tegra20 platform handles this during
-  early boot by selecting one out of possible 4 memory settings based
-  on a 2-pin "ram code" bootstrap setting on the board. The values of
-  these strappings can be read through a register in the SoC, and thus
-  used to select which tables to use.
-
-Properties:
-- name : Should be emc-table
-- compatible : Should contain "nvidia,tegra20-emc-table".
-- reg : either an opaque enumerator to tell different tables apart, or
-  the valid frequency for which the table should be used (in kHz).
-- clock-frequency : the clock frequency for the EMC at which this
-  table should be used (in kHz).
-- nvidia,emc-registers : a 46 word array of EMC registers to be programmed
-  for operation at the 'clock-frequency' setting.
-  The order and contents of the registers are:
-    RC, RFC, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, RRD, REXT,
-    WDV, QUSE, QRST, QSAFE, RDV, REFRESH, BURST_REFRESH_NUM, PDEX2WR,
-    PDEX2RD, PCHG2PDEN, ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, TCKE, TFAW,
-    TRPAB, TCLKSTABLE, TCLKSTOP, TREFBW, QUSE_EXTRA, FBIO_CFG6, ODT_WRITE,
-    ODT_READ, FBIO_CFG5, CFG_DIG_DLL, DLL_XFORM_DQS, DLL_XFORM_QUSE,
-    ZCAL_REF_CNT, ZCAL_WAIT_CNT, AUTO_CAL_INTERVAL, CFG_CLKTRIM_0,
-    CFG_CLKTRIM_1, CFG_CLKTRIM_2
-
-                emc-table@166000 {
-                        reg = <166000>;
-                        compatible = "nvidia,tegra20-emc-table";
-                        clock-frequency = < 166000 >;
-                        nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-                                                 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-                                                 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-                                                 0 0 0 0 >;
-                };
-
-                emc-table@333000 {
-                        reg = <333000>;
-                        compatible = "nvidia,tegra20-emc-table";
-                        clock-frequency = < 333000 >;
-                        nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-                                                 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-                                                 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-                                                 0 0 0 0 >;
-                };
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt
deleted file mode 100644
index 866d93421eb..00000000000
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-NVIDIA Tegra20 MC(Memory Controller)
-
-Required properties:
-- compatible : "nvidia,tegra20-mc"
-- reg : Should contain 2 register ranges(address and length); see the
-  example below. Note that the MC registers are interleaved with the
-  GART registers, and hence must be represented as multiple ranges.
-- interrupts : Should contain MC General interrupt.
-
-Example:
-        memory-controller@0x7000f000 {
-                compatible = "nvidia,tegra20-mc";
-                reg = <0x7000f000 0x024
-                       0x7000f03c 0x3c4>;
-                interrupts = <0 77 0x04>;
-        };
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
deleted file mode 100644
index b5846e21cc2..00000000000
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-NVIDIA Tegra Power Management Controller (PMC)
-
-Properties:
-- name : Should be pmc
-- compatible : Should contain "nvidia,tegra<chip>-pmc".
-- reg : Offset and length of the register set for the device
-- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
-  The PMU is an external Power Management Unit, whose interrupt output
-  signal is fed into the PMC. This signal is optionally inverted, and then
-  fed into the ARM GIC. The PMC is not involved in the detection or
-  handling of this interrupt signal, merely its inversion.
-
-Example:
-
-pmc@7000f400 {
-        compatible = "nvidia,tegra20-pmc";
-        reg = <0x7000e400 0x400>;
-        nvidia,invert-interrupt;
-};
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt
deleted file mode 100644
index bdf1a612422..00000000000
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-NVIDIA Tegra30 MC(Memory Controller)
-
-Required properties:
-- compatible : "nvidia,tegra30-mc"
-- reg : Should contain 4 register ranges(address and length); see the
-  example below. Note that the MC registers are interleaved with the
-  SMMU registers, and hence must be represented as multiple ranges.
-- interrupts : Should contain MC General interrupt.
-
-Example:
-        memory-controller {
-                compatible = "nvidia,tegra30-mc";
-                reg = <0x7000f000 0x010
-                       0x7000f03c 0x1b4
-                       0x7000f200 0x028
-                       0x7000f284 0x17c>;
-                interrupts = <0 77 0x04>;
-        };
diff --git a/Documentation/devicetree/bindings/arm/twd.txt b/Documentation/devicetree/bindings/arm/twd.txt
deleted file mode 100644
index 75b8610939f..00000000000
--- a/Documentation/devicetree/bindings/arm/twd.txt
+++ /dev/null
@@ -1,48 +0,0 @@
-* ARM Timer Watchdog
-
-ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
-Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
-and watchdog.
-
-The TWD is usually attached to a GIC to deliver its two per-processor
-interrupts.
-
-** Timer node required properties:
-
-- compatible : Should be one of:
-        "arm,cortex-a9-twd-timer"
-        "arm,cortex-a5-twd-timer"
-        "arm,arm11mp-twd-timer"
-
-- interrupts : One interrupt to each core
-
-- reg : Specify the base address and the size of the TWD timer
-        register window.
-
-Example:
-
-        twd-timer@2c000600 {
-                compatible = "arm,arm11mp-twd-timer"";
-                reg = <0x2c000600 0x20>;
-                interrupts = <1 13 0xf01>;
-        };
-
-** Watchdog node properties:
-
-- compatible : Should be one of:
-        "arm,cortex-a9-twd-wdt"
-        "arm,cortex-a5-twd-wdt"
-        "arm,arm11mp-twd-wdt"
-
-- interrupts : One interrupt to each core
-
-- reg : Specify the base address and the size of the TWD watchdog
-        register window.
-
-Example:
-
-        twd-watchdog@2c000620 {
-                compatible = "arm,arm11mp-twd-wdt";
-                reg = <0x2c000620 0x20>;
-                interrupts = <1 14 0xf01>;
-        };
diff --git a/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt b/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt
deleted file mode 100644
index 9989eda755d..00000000000
--- a/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-* ARM Versatile FPGA interrupt controller
-
-One or more FPGA IRQ controllers can be synthesized in an ARM reference board
-such as the Integrator or Versatile family. The output of these different
-controllers are OR:ed together and fed to the CPU tile's IRQ input. Each
-instance can handle up to 32 interrupts.
-
-Required properties:
-- compatible: "arm,versatile-fpga-irq"
-- interrupt-controller: Identifies the node as an interrupt controller
-- #interrupt-cells: The number of cells to define the interrupts.  Must be 1
-  as the FPGA IRQ controller has no configuration options for interrupt
-  sources.  The cell is a u32 and defines the interrupt number.
-- reg: The register bank for the FPGA interrupt controller.
-- clear-mask: a u32 number representing the mask written to clear all IRQs
-  on the controller at boot for example.
-- valid-mask: a u32 number representing a bit mask determining which of
-  the interrupts are valid. Unconnected/unused lines are set to 0, and
-  the system till not make it possible for devices to request these
-  interrupts.
-
-Example:
-
-pic: pic@14000000 {
-        compatible = "arm,versatile-fpga-irq";
-        #interrupt-cells = <1>;
-        interrupt-controller;
-        reg = <0x14000000 0x100>;
-        clear-mask = <0xffffffff>;
-        valid-mask = <0x003fffff>;
-};
diff --git a/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt b/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt
deleted file mode 100644
index 9cf3f25544c..00000000000
--- a/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-ARM Versatile Express system registers
---------------------------------------
-
-This is a system control registers block, providing multiple low level
-platform functions like board detection and identification, software
-interrupt generation, MMC and NOR Flash control etc.
-
-Required node properties:
-- compatible value : = "arm,vexpress,sysreg";
-- reg : physical base address and the size of the registers window
-- gpio-controller : specifies that the node is a GPIO controller
-- #gpio-cells : size of the GPIO specifier, should be 2:
-  - first cell is the pseudo-GPIO line number:
-    0 - MMC CARDIN
-    1 - MMC WPROT
-    2 - NOR FLASH WPn
-  - second cell can take standard GPIO flags (currently ignored).
-
-Example:
-        v2m_sysreg: sysreg@10000000 {
-                compatible = "arm,vexpress-sysreg";
-                reg = <0x10000000 0x1000>;
-                gpio-controller;
-                #gpio-cells = <2>;
-        };
-
-This block also can also act a bridge to the platform's configuration
-bus via "system control" interface, addressing devices with site number,
-position in the board stack, config controller, function and device
-numbers - see motherboard's TRM for more details.
-
-The node describing a config device must refer to the sysreg node via
-"arm,vexpress,config-bridge" phandle (can be also defined in the node's
-parent) and relies on the board topology properties - see main vexpress
-node documentation for more details. It must must also define the
-following property:
-- arm,vexpress-sysreg,func : must contain two cells:
-  - first cell defines function number (eg. 1 for clock generator,
-    2 for voltage regulators etc.)
-  - device number (eg. osc 0, osc 1 etc.)
-
-Example:
-        mcc {
-                arm,vexpress,config-bridge = <&v2m_sysreg>;
-
-                osc@0 {
-                        compatible = "arm,vexpress-osc";
-                        arm,vexpress-sysreg,func = <1 0>;
-                };
-        };
diff --git a/Documentation/devicetree/bindings/arm/vexpress.txt b/Documentation/devicetree/bindings/arm/vexpress.txt
deleted file mode 100644
index ae49161e478..00000000000
--- a/Documentation/devicetree/bindings/arm/vexpress.txt
+++ /dev/null
@@ -1,224 +0,0 @@
-ARM Versatile Express boards family
------------------------------------
-
-ARM's Versatile Express platform consists of a motherboard and one
-or more daughterboards (tiles). The motherboard provides a set of
-peripherals. Processor and RAM "live" on the tiles.
-
-The motherboard and each core tile should be described by a separate
-Device Tree source file, with the tile's description including
-the motherboard file using a /include/ directive. As the motherboard
-can be initialized in one of two different configurations ("memory
-maps"), care must be taken to include the correct one.
-
-
-Root node
----------
-
-Required properties in the root node:
-- compatible value:
-        compatible = "arm,vexpress,<model>", "arm,vexpress";
-  where <model> is the full tile model name (as used in the tile's
-    Technical Reference Manual), eg.:
-    - for Coretile Express A5x2 (V2P-CA5s):
-        compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
-    - for Coretile Express A9x4 (V2P-CA9):
-        compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
-  If a tile comes in several variants or can be used in more then one
-  configuration, the compatible value should be:
-        compatible = "arm,vexpress,<model>,<variant>", \
-                                "arm,vexpress,<model>", "arm,vexpress";
-  eg:
-    - Coretile Express A15x2 (V2P-CA15) with Tech Chip 1:
-        compatible = "arm,vexpress,v2p-ca15,tc1", \
-                                "arm,vexpress,v2p-ca15", "arm,vexpress";
-    - LogicTile Express 13MG (V2F-2XV6) running Cortex-A7 (3 cores) SMM:
-        compatible = "arm,vexpress,v2f-2xv6,ca7x3", \
-                                "arm,vexpress,v2f-2xv6", "arm,vexpress";
-
-Optional properties in the root node:
-- tile model name (use name from the tile's Technical Reference
-  Manual, eg. "V2P-CA5s")
-        model = "<model>";
-- tile's HBI number (unique ARM's board model ID, visible on the
-  PCB's silkscreen) in hexadecimal transcription:
-        arm,hbi = <0xhbi>
-  eg:
-  - for Coretile Express A5x2 (V2P-CA5s) HBI-0191:
-        arm,hbi = <0x191>;
-  - Coretile Express A9x4 (V2P-CA9) HBI-0225:
-        arm,hbi = <0x225>;
-
-
-CPU nodes
----------
-
-Top-level standard "cpus" node is required. It must contain a node
-with device_type = "cpu" property for every available core, eg.:
-
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                cpu@0 {
-                        device_type = "cpu";
-                        compatible = "arm,cortex-a5";
-                        reg = <0>;
-                };
-        };
-
-
-Configuration infrastructure
-----------------------------
-
-The platform has an elaborated configuration system, consisting of
-microcontrollers residing on the mother- and daughterboards known
-as Motherboard/Daughterboard Configuration Controller (MCC and DCC).
-The controllers are responsible for the platform initialization
-(reset generation, flash programming, FPGA bitfiles loading etc.)
-but also control clock generators, voltage regulators, gather
-environmental data like temperature, power consumption etc. Even
-the video output switch (FPGA) is controlled that way.
-
-Nodes describing devices controlled by this infrastructure should
-point at the bridge device node:
-- bridge phandle:
-        arm,vexpress,config-bridge = <phandle>;
-This property can be also defined in a parent node (eg. for a DCC)
-and is effective for all children.
-
-
-Platform topology
------------------
-
-As Versatile Express can be configured in number of physically
-different setups, the device tree should describe platform topology.
-Root node and main motherboard node must define the following
-property, describing physical location of the children nodes:
-- site number:
-        arm,vexpress,site = <number>;
-  where 0 means motherboard, 1 or 2 are daugtherboard sites,
-  0xf means "master" site (site containing main CPU tile)
-- when daughterboards are stacked on one site, their position
-  in the stack be be described with:
-        arm,vexpress,position = <number>;
-- when describing tiles consisting more than one DCC, its number
-  can be described with:
-        arm,vexpress,dcc = <number>;
-
-Any of the numbers above defaults to zero if not defined in
-the node or any of its parent.
-
-
-Motherboard
------------
-
-The motherboard description file provides a single "motherboard" node
-using 2 address cells corresponding to the Static Memory Bus used
-between the motherboard and the tile. The first cell defines the Chip
-Select (CS) line number, the second cell address offset within the CS.
-All interrupt lines between the motherboard and the tile are active
-high and are described using single cell.
-
-Optional properties of the "motherboard" node:
-- motherboard's memory map variant:
-        arm,v2m-memory-map = "<name>";
-  where name is one of:
-  - "rs1" - for RS1 map (i.a. peripherals on CS3); this map is also
-            referred to as "ARM Cortex-A Series memory map":
-        arm,v2m-memory-map = "rs1";
-  When this property is missing, the motherboard is using the original
-  memory map (also known as the "Legacy memory map", primarily used
-  with the original CoreTile Express A9x4) with peripherals on CS7.
-
-Motherboard .dtsi files provide a set of labelled peripherals that
-can be used to obtain required phandle in the tile's "aliases" node:
-- UARTs, note that the numbers correspond to the physical connectors
-  on the motherboard's back panel:
-        v2m_serial0, v2m_serial1, v2m_serial2 and v2m_serial3
-- I2C controllers:
-        v2m_i2c_dvi and v2m_i2c_pcie
-- SP804 timers:
-        v2m_timer01 and v2m_timer23
-
-The tile description should define a "smb" node, describing the
-Static Memory Bus between the tile and motherboard. It must define
-the following properties:
-- "simple-bus" compatible value (to ensure creation of the children)
-        compatible = "simple-bus";
-- mapping of the SMB CS/offset addresses into main address space:
-        #address-cells = <2>;
-        #size-cells = <1>;
-        ranges = <...>;
-- interrupts mapping:
-        #interrupt-cells = <1>;
-        interrupt-map-mask = <0 0 63>;
-        interrupt-map = <...>;
-
-
-Example of a VE tile description (simplified)
----------------------------------------------
-
-/dts-v1/;
-
-/ {
-        model = "V2P-CA5s";
-        arm,hbi = <0x225>;
-        arm,vexpress,site = <0xf>;
-        compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress";
-        interrupt-parent = <&gic>;
-        #address-cells = <1>;
-        #size-cells = <1>;
-
-        chosen { };
-
-        aliases {
-                serial0 = &v2m_serial0;
-        };
-
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                cpu@0 {
-                        device_type = "cpu";
-                        compatible = "arm,cortex-a5";
-                        reg = <0>;
-                };
-        };
-
-        gic: interrupt-controller@2c001000 {
-                compatible = "arm,cortex-a9-gic";
-                #interrupt-cells = <3>;
-                #address-cells = <0>;
-                interrupt-controller;
-                reg = <0x2c001000 0x1000>,
-                      <0x2c000100 0x100>;
-        };
-
-        dcc {
-                compatible = "simple-bus";
-                arm,vexpress,config-bridge = <&v2m_sysreg>;
-
-                osc@0 {
-                        compatible = "arm,vexpress-osc";
-                };
-        };
-
-        smb {
-                compatible = "simple-bus";
-
-                #address-cells = <2>;
-                #size-cells = <1>;
-                /* CS0 is visible at 0x08000000 */
-                ranges = <0 0 0x08000000 0x04000000>;
-
-                #interrupt-cells = <1>;
-                interrupt-map-mask = <0 0 63>;
-                /* Active high IRQ 0 is connected to GIC's SPI0 */
-                interrupt-map = <0 0 0 &gic 0 0 4>;
-
-                /include/ "vexpress-v2m-rs1.dtsi"
-        };
-};
-
diff --git a/Documentation/devicetree/bindings/arm/vic.txt b/Documentation/devicetree/bindings/arm/vic.txt
deleted file mode 100644
index 266716b2343..00000000000
--- a/Documentation/devicetree/bindings/arm/vic.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-* ARM Vectored Interrupt Controller
-
-One or more Vectored Interrupt Controllers (VIC's) can be connected in an ARM
-system for interrupt routing.  For multiple controllers they can either be
-nested or have the outputs wire-OR'd together.
-
-Required properties:
-
-- compatible : should be one of
-        "arm,pl190-vic"
-        "arm,pl192-vic"
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : The number of cells to define the interrupts.  Must be 1 as
-  the VIC has no configuration options for interrupt sources.  The cell is a u32
-  and defines the interrupt number.
-- reg : The register bank for the VIC.
-
-Optional properties:
-
-- interrupts : Interrupt source for parent controllers if the VIC is nested.
-
-Example:
-
-        vic0: interrupt-controller@60000 {
-                compatible = "arm,pl192-vic";
-                interrupt-controller;
-                #interrupt-cells = <1>;
-                reg = <0x60000 0x1000>;
-        };
diff --git a/Documentation/devicetree/bindings/arm/vt8500.txt b/Documentation/devicetree/bindings/arm/vt8500.txt
deleted file mode 100644
index d657832c681..00000000000
--- a/Documentation/devicetree/bindings/arm/vt8500.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-VIA/Wondermedia VT8500 Platforms Device Tree Bindings
----------------------------------------
-
-Boards with the VIA VT8500 SoC shall have the following properties:
-Required root node property:
-compatible = "via,vt8500";
-
-Boards with the Wondermedia WM8505 SoC shall have the following properties:
-Required root node property:
-compatible = "wm,wm8505";
-
-Boards with the Wondermedia WM8650 SoC shall have the following properties:
-Required root node property:
-compatible = "wm,wm8650";
diff --git a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt
deleted file mode 100644
index 0a4ce1051b0..00000000000
--- a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-VIA/Wondermedia VT8500 Interrupt Controller
------------------------------------------------------
-
-Required properties:
-- compatible : "via,vt8500-intc"
-- reg : Should contain 1 register ranges(address and length)
-- #interrupt-cells : should be <1>
-
-Example:
-
-        intc: interrupt-controller@d8140000 {
-                compatible = "via,vt8500-intc";
-                interrupt-controller;
-                reg = <0xd8140000 0x10000>;
-                #interrupt-cells = <1>;
-        };
diff --git a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt
deleted file mode 100644
index 521b9c7de93..00000000000
--- a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-VIA/Wondermedia VT8500 Power Management Controller
------------------------------------------------------
-
-Required properties:
-- compatible : "via,vt8500-pmc"
-- reg : Should contain 1 register ranges(address and length)
-
-Example:
-
-        pmc@d8130000 {
-                compatible = "via,vt8500-pmc";
-                reg = <0xd8130000 0x1000>;
-        };
diff --git a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt
deleted file mode 100644
index 901c73f0d8e..00000000000
--- a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-VIA/Wondermedia VT8500 Timer
------------------------------------------------------
-
-Required properties:
-- compatible : "via,vt8500-timer"
-- reg : Should contain 1 register ranges(address and length)
-- interrupts : interrupt for the timer
-
-Example:
-
-        timer@d8130100 {
-                compatible = "via,vt8500-timer";
-                reg = <0xd8130100 0x28>;
-                interrupts = <36>;
-        };
diff --git a/Documentation/devicetree/bindings/arm/xen.txt b/Documentation/devicetree/bindings/arm/xen.txt
deleted file mode 100644
index 0f7b9c2109f..00000000000
--- a/Documentation/devicetree/bindings/arm/xen.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-* Xen hypervisor device tree bindings
-
-Xen ARM virtual platforms shall have a top-level "hypervisor" node with
-the following properties:
-
-- compatible:
-        compatible = "xen,xen-<version>", "xen,xen";
-  where <version> is the version of the Xen ABI of the platform.
-
-- reg: specifies the base physical address and size of a region in
-  memory where the grant table should be mapped to, using an
-  HYPERVISOR_memory_op hypercall. The memory region is large enough to map
-  the whole grant table (it is larger or equal to gnttab_max_grant_frames()).
-
-- interrupts: the interrupt used by Xen to inject event notifications.
-  A GIC node is also required.
-
-
-Example (assuming #address-cells = <2> and #size-cells = <2>):
-
-hypervisor {
-        compatible = "xen,xen-4.3", "xen,xen";
-        reg = <0 0xb0000000 0 0x20000>;
-        interrupts = <1 15 0xf08>;
-};
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt
deleted file mode 100644
index b519f9b699c..00000000000
--- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-* AHCI SATA Controller
-
-SATA nodes are defined to describe on-chip Serial ATA controllers.
-Each SATA controller should have its own node.
-
-Required properties:
-- compatible        : compatible list, contains "calxeda,hb-ahci" or "snps,spear-ahci"
-- interrupts        : <interrupt mapping for SATA IRQ>
-- reg               : <registers mapping>
-
-Optional properties:
-- calxeda,port-phys: phandle-combophy and lane assignment, which maps each
-                        SATA port to a combophy and a lane within that
-                        combophy
-- dma-coherent      : Present if dma operations are coherent
-
-Example:
-        sata@ffe08000 {
-                compatible = "calxeda,hb-ahci";
-                reg = <0xffe08000 0x1000>;
-                interrupts = <115>;
-                calxeda,port-phys = <&combophy5 0 &combophy0 0 &combophy0 1
-                                        &combophy0 2 &combophy0 3>;
-
-        };
diff --git a/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt b/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt
deleted file mode 100644
index 93986a5a801..00000000000
--- a/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt
+++ /dev/null
@@ -1,30 +0,0 @@
-* Compact Flash
-
-The Cavium Compact Flash device is connected to the Octeon Boot Bus,
-and is thus a child of the Boot Bus device.  It can read and write
-industry standard compact flash devices.
-
-Properties:
-- compatible: "cavium,ebt3000-compact-flash";
-
-  Compatibility with many Cavium evaluation boards.
-
-- reg: The base address of the the CF chip select banks.  Depending on
-  the device configuration, there may be one or two banks.
-
-- cavium,bus-width: The width of the connection to the CF devices.  Valid
-  values are 8 and 16.
-
-- cavium,true-ide: Optional, if present the CF connection is in True IDE mode.
-
-- cavium,dma-engine-handle: Optional, a phandle for the DMA Engine connected
-  to this device.
-
-Example:
-        compact-flash@5,0 {
-                compatible = "cavium,ebt3000-compact-flash";
-                reg = <5 0 0x10000>, <6 0 0x10000>;
-                cavium,bus-width = <16>;
-                cavium,true-ide;
-                cavium,dma-engine-handle = <&dma0>;
-        };
diff --git a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt b/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
deleted file mode 100644
index 37824fac688..00000000000
--- a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-* Samsung SATA PHY Controller
-
-SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
-Each SATA PHY controller should have its own node.
-
-Required properties:
-- compatible        : compatible list, contains "samsung,exynos5-sata-phy"
-- reg               : <registers mapping>
-
-Example:
-        sata@ffe07000 {
-                compatible = "samsung,exynos5-sata-phy";
-                reg = <0xffe07000 0x1000>;
-        };
diff --git a/Documentation/devicetree/bindings/ata/exynos-sata.txt b/Documentation/devicetree/bindings/ata/exynos-sata.txt
deleted file mode 100644
index 0849f1025e3..00000000000
--- a/Documentation/devicetree/bindings/ata/exynos-sata.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-* Samsung AHCI SATA Controller
-
-SATA nodes are defined to describe on-chip Serial ATA controllers.
-Each SATA controller should have its own node.
-
-Required properties:
-- compatible        : compatible list, contains "samsung,exynos5-sata"
-- interrupts        : <interrupt mapping for SATA IRQ>
-- reg               : <registers mapping>
-- samsung,sata-freq : <frequency in MHz>
-
-Example:
-        sata@ffe08000 {
-                compatible = "samsung,exynos5-sata";
-                reg = <0xffe08000 0x1000>;
-                interrupts = <115>;
-        };
diff --git a/Documentation/devicetree/bindings/ata/marvell.txt b/Documentation/devicetree/bindings/ata/marvell.txt
deleted file mode 100644
index b5cdd20cde9..00000000000
--- a/Documentation/devicetree/bindings/ata/marvell.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-* Marvell Orion SATA
-
-Required Properties:
-- compatibility : "marvell,orion-sata"
-- reg           : Address range of controller
-- interrupts    : Interrupt controller is using
-- nr-ports      : Number of SATA ports in use.
-
-Example:
-
-        sata@80000 {
-                compatible = "marvell,orion-sata";
-                reg = <0x80000 0x5000>;
-                interrupts = <21>;
-                nr-ports = <2>;
-        }
diff --git a/Documentation/devicetree/bindings/ata/pata-arasan.txt b/Documentation/devicetree/bindings/ata/pata-arasan.txt
deleted file mode 100644
index 95ec7f825ed..00000000000
--- a/Documentation/devicetree/bindings/ata/pata-arasan.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-* ARASAN PATA COMPACT FLASH CONTROLLER
-
-Required properties:
-- compatible: "arasan,cf-spear1340"
-- reg: Address range of the CF registers
-- interrupt-parent: Should be the phandle for the interrupt controller
-  that services interrupts for this device
-- interrupt: Should contain the CF interrupt number
-
-Example:
-
-        cf@fc000000 {
-                compatible = "arasan,cf-spear1340";
-                reg = <0xfc000000 0x1000>;
-                interrupt-parent = <&vic1>;
-                interrupts = <12>;
-        };
diff --git a/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt b/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
deleted file mode 100644
index 63dd8051521..00000000000
--- a/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-* OMAP OCP2SCP - ocp interface to scp interface
-
-properties:
-- compatible : Should be "ti,omap-ocp2scp"
-- reg : Address and length of the register set for the device
-- #address-cells, #size-cells : Must be present if the device has sub-nodes
-- ranges : the child address space are mapped 1:1 onto the parent address space
-- ti,hwmods : must be "ocp2scp_usb_phy"
-
-Sub-nodes:
-All the devices connected to ocp2scp are described using sub-node to ocp2scp
-
-ocp2scp@4a0ad000 {
-        compatible = "ti,omap-ocp2scp";
-        reg = <0x4a0ad000 0x1f>;
-        #address-cells = <1>;
-        #size-cells = <1>;
-        ranges;
-        ti,hwmods = "ocp2scp_usb_phy";
-
-        subnode1 {
-        ...
-        };
-
-        subnode2 {
-        ...
-        };
-};
diff --git a/Documentation/devicetree/bindings/c6x/clocks.txt b/Documentation/devicetree/bindings/c6x/clocks.txt
deleted file mode 100644
index a04f5fd3012..00000000000
--- a/Documentation/devicetree/bindings/c6x/clocks.txt
+++ /dev/null
@@ -1,40 +0,0 @@
-C6X PLL Clock Controllers
--------------------------
-
-This is a first-cut support for the SoC clock controllers. This is still
-under development and will probably change as the common device tree
-clock support is added to the kernel.
-
-Required properties:
-
-- compatible: "ti,c64x+pll"
-    May also have SoC-specific value to support SoC-specific initialization
-    in the driver. One of:
-        "ti,c6455-pll"
-        "ti,c6457-pll"
-        "ti,c6472-pll"
-        "ti,c6474-pll"
-
-- reg: base address and size of register area
-- clock-frequency: input clock frequency in hz
-
-
-Optional properties:
-
-- ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode
-
-- ti,c64x+pll-reset-delay:  CPU cycles to delay after PLL reset
-
-- ti,c64x+pll-lock-delay:   CPU cycles to delay after PLL frequency change
-
-Example:
-
-        clock-controller@29a0000 {
-                compatible = "ti,c6472-pll", "ti,c64x+pll";
-                reg = <0x029a0000 0x200>;
-                clock-frequency = <25000000>;
-
-                ti,c64x+pll-bypass-delay = <200>;
-                ti,c64x+pll-reset-delay = <12000>;
-                ti,c64x+pll-lock-delay = <80000>;
-        };
diff --git a/Documentation/devicetree/bindings/c6x/dscr.txt b/Documentation/devicetree/bindings/c6x/dscr.txt
deleted file mode 100644
index d847758f2b2..00000000000
--- a/Documentation/devicetree/bindings/c6x/dscr.txt
+++ /dev/null
@@ -1,127 +0,0 @@
-Device State Configuration Registers
-------------------------------------
-
-TI C6X SoCs contain a region of miscellaneous registers which provide various
-function for SoC control or status. Details vary considerably among from SoC
-to SoC with no two being alike.
-
-In general, the Device State Configuraion Registers (DSCR) will provide one or
-more configuration registers often protected by a lock register where one or
-more key values must be written to a lock register in order to unlock the
-configuration register for writes. These configuration register may be used to
-enable (and disable in some cases) SoC pin drivers, select peripheral clock
-sources (internal or pin), etc. In some cases, a configuration register is
-write once or the individual bits are write once. In addition to device config,
-the DSCR block may provide registers which which are used to reset peripherals,
-provide device ID information, provide ethernet MAC addresses, as well as other
-miscellaneous functions.
-
-For device state control (enable/disable), each device control is assigned an
-id which is used by individual device drivers to control the state as needed.
-
-Required properties:
-
-- compatible: must be "ti,c64x+dscr"
-- reg: register area base and size
-
-Optional properties:
-
-  NOTE: These are optional in that not all SoCs will have all properties. For
-        SoCs which do support a given property, leaving the property out of the
-        device tree will result in reduced functionality or possibly driver
-        failure.
-
-- ti,dscr-devstat
-    offset of the devstat register
-
-- ti,dscr-silicon-rev
-    offset, start bit, and bitsize of silicon revision field
-
-- ti,dscr-rmii-resets
-    offset and bitmask of RMII reset field. May have multiple tuples if more
-    than one ethernet port is available.
-
-- ti,dscr-locked-regs
-    possibly multiple tuples describing registers which are write protected by
-    a lock register. Each tuple consists of the register offset, lock register
-    offsset, and the key value used to unlock the register.
-
-- ti,dscr-kick-regs
-    offset and key values of two "kick" registers used to write protect other
-    registers in DSCR. On SoCs using kick registers, the first key must be
-    written to the first kick register and the second key must be written to
-    the second register before other registers in the area are write-enabled.
-
-- ti,dscr-mac-fuse-regs
-    MAC addresses are contained in two registers. Each element of a MAC address
-    is contained in a single byte. This property has two tuples. Each tuple has
-    a register offset and four cells representing bytes in the register from
-    most significant to least. The value of these four cells is the MAC byte
-    index (1-6) of the byte within the register. A value of 0 means the byte
-    is unused in the MAC address.
-
-- ti,dscr-devstate-ctl-regs
-    This property describes the bitfields used to control the state of devices.
-    Each tuple describes a range of identical bitfields used to control one or
-    more devices (one bitfield per device). The layout of each tuple is:
-
-        start_id num_ids reg enable disable start_bit nbits
-
-    Where:
-        start_id is device id for the first device control in the range
-        num_ids is the number of device controls in the range
-        reg is the offset of the register holding the control bits
-        enable is the value to enable a device
-        disable is the value to disable a device (0xffffffff if cannot disable)
-        start_bit is the bit number of the first bit in the range
-        nbits is the number of bits per device control
-
-- ti,dscr-devstate-stat-regs
-    This property describes the bitfields used to provide device state status
-    for device states controlled by the DSCR. Each tuple describes a range of
-    identical bitfields used to provide status for one or more devices (one
-    bitfield per device). The layout of each tuple is:
-
-        start_id num_ids reg enable disable start_bit nbits
-
-    Where:
-        start_id is device id for the first device status in the range
-        num_ids is the number of devices covered by the range
-        reg is the offset of the register holding the status bits
-        enable is the value indicating device is enabled
-        disable is the value indicating device is disabled
-        start_bit is the bit number of the first bit in the range
-        nbits is the number of bits per device status
-
-- ti,dscr-privperm
-    Offset and default value for register used to set access privilege for
-    some SoC devices.
-
-
-Example:
-
-        device-state-config-regs@2a80000 {
-                compatible = "ti,c64x+dscr";
-                reg = <0x02a80000 0x41000>;
-
-                ti,dscr-devstat = <0>;
-                ti,dscr-silicon-rev = <8 28 0xf>;
-                ti,dscr-rmii-resets = <0x40020 0x00040000>;
-
-                ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>;
-                ti,dscr-devstate-ctl-regs =
-                         <0 12 0x40008 1 0  0  2
-                          12 1 0x40008 3 0 30  2
-                          13 2 0x4002c 1 0xffffffff 0 1>;
-                ti,dscr-devstate-stat-regs =
-                        <0 10 0x40014 1 0  0  3
-                         10 2 0x40018 1 0  0  3>;
-
-                ti,dscr-mac-fuse-regs = <0x700 1 2 3 4
-                                         0x704 5 6 0 0>;
-
-                ti,dscr-privperm = <0x41c 0xaaaaaaaa>;
-
-                ti,dscr-kick-regs = <0x38 0x83E70B13
-                                     0x3c 0x95A4F1E0>;
-        };
diff --git a/Documentation/devicetree/bindings/c6x/emifa.txt b/Documentation/devicetree/bindings/c6x/emifa.txt
deleted file mode 100644
index 0ff6e9b9a13..00000000000
--- a/Documentation/devicetree/bindings/c6x/emifa.txt
+++ /dev/null
@@ -1,62 +0,0 @@
-External Memory Interface
--------------------------
-
-The emifa node describes a simple external bus controller found on some C6X
-SoCs. This interface provides external busses with a number of chip selects.
-
-Required properties:
-
-- compatible: must be "ti,c64x+emifa", "simple-bus"
-- reg: register area base and size
-- #address-cells: must be 2 (chip-select + offset)
-- #size-cells: must be 1
-- ranges: mapping from EMIFA space to parent space
-
-
-Optional properties:
-
-- ti,dscr-dev-enable: Device ID if EMIF is enabled/disabled from DSCR
-
-- ti,emifa-burst-priority:
-      Number of memory transfers after which the EMIF will elevate the priority
-      of the oldest command in the command FIFO. Setting this field to 255
-      disables this feature, thereby allowing old commands to stay in the FIFO
-      indefinitely.
-
-- ti,emifa-ce-config:
-      Configuration values for each of the supported chip selects.
-
-Example:
-
-        emifa@70000000 {
-                compatible = "ti,c64x+emifa", "simple-bus";
-                #address-cells = <2>;
-                #size-cells = <1>;
-                reg = <0x70000000 0x100>;
-                ranges = <0x2 0x0 0xa0000000 0x00000008
-                          0x3 0x0 0xb0000000 0x00400000
-                          0x4 0x0 0xc0000000 0x10000000
-                          0x5 0x0 0xD0000000 0x10000000>;
-
-                ti,dscr-dev-enable = <13>;
-                ti,emifa-burst-priority = <255>;
-                ti,emifa-ce-config = <0x00240120
-                                      0x00240120
-                                      0x00240122
-                                      0x00240122>;
-
-                flash@3,0 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "cfi-flash";
-                        reg = <0x3 0x0 0x400000>;
-                        bank-width = <1>;
-                        device-width = <1>;
-                        partition@0 {
-                                reg = <0x0 0x400000>;
-                                label = "NOR";
-                        };
-                };
-        };
-
-This shows a flash chip attached to chip select 3.
diff --git a/Documentation/devicetree/bindings/c6x/interrupt.txt b/Documentation/devicetree/bindings/c6x/interrupt.txt
deleted file mode 100644
index 42bb796cc4a..00000000000
--- a/Documentation/devicetree/bindings/c6x/interrupt.txt
+++ /dev/null
@@ -1,104 +0,0 @@
-C6X Interrupt Chips
--------------------
-
-* C64X+ Core Interrupt Controller
-
-  The core interrupt controller provides 16 prioritized interrupts to the
-  C64X+ core. Priority 0 and 1 are used for reset and NMI respectively.
-  Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
-  sources coming from outside the core.
-
-  Required properties:
-  --------------------
-  - compatible: Should be "ti,c64x+core-pic";
-  - #interrupt-cells: <1>
-
-  Interrupt Specifier Definition
-  ------------------------------
-  Single cell specifying the core interrupt priority level (4-15) where
-  4 is highest priority and 15 is lowest priority.
-
-  Example
-  -------
-  core_pic: interrupt-controller@0 {
-        interrupt-controller;
-        #interrupt-cells = <1>;
-        compatible = "ti,c64x+core-pic";
-  };
-
-
-
-* C64x+ Megamodule Interrupt Controller
-
-  The megamodule PIC consists of four interrupt mupliplexers each of which
-  combine up to 32 interrupt inputs into a single interrupt output which
-  may be cascaded into the core interrupt controller. The megamodule PIC
-  has a total of 12 outputs cascading into the core interrupt controller.
-  One for each core interrupt priority level. In addition to the combined
-  interrupt sources, individual megamodule interrupts may be cascaded to
-  the core interrupt controller. When an individual interrupt is cascaded,
-  it is no longer handled through a megamodule interrupt combiner and is
-  considered to have the core interrupt controller as the parent.
-
-  Required properties:
-  --------------------
-  - compatible: "ti,c64x+megamod-pic"
-  - interrupt-controller
-  - #interrupt-cells: <1>
-  - reg: base address and size of register area
-  - interrupt-parent: must be core interrupt controller
-  - interrupts: This should have four cells; one for each interrupt combiner.
-                The cells contain the core priority interrupt to which the
-                corresponding combiner output is wired.
-
-  Optional properties:
-  --------------------
-  - ti,c64x+megamod-pic-mux: Array of 12 cells correspnding to the 12 core
-                             priority interrupts. The first cell corresponds to
-                             core priority 4 and the last cell corresponds to
-                             core priority 15. The value of each cell is the
-                             megamodule interrupt source which is MUXed to
-                             the core interrupt corresponding to the cell
-                             position. Allowed values are 4 - 127. Mapping for
-                             interrupts 0 - 3 (combined interrupt sources) are
-                             ignored.
-
-  Interrupt Specifier Definition
-  ------------------------------
-  Single cell specifying the megamodule interrupt source (4-127). Note that
-  interrupts mapped directly to the core with "ti,c64x+megamod-pic-mux" will
-  use the core interrupt controller as their parent and the specifier will
-  be the core priority level, not the megamodule interrupt number.
-
-  Examples
-  --------
-  megamod_pic: interrupt-controller@1800000 {
-        compatible = "ti,c64x+megamod-pic";
-        interrupt-controller;
-        #interrupt-cells = <1>;
-        reg = <0x1800000 0x1000>;
-        interrupt-parent = <&core_pic>;
-        interrupts = < 12 13 14 15 >;
-  };
-
-  This is a minimal example where all individual interrupts go through a
-  combiner. Combiner-0 is mapped to core interrupt 12, combiner-1 is mapped
-  to interrupt 13, etc.
-
-
-  megamod_pic: interrupt-controller@1800000 {
-        compatible = "ti,c64x+megamod-pic";
-        interrupt-controller;
-        #interrupt-cells = <1>;
-        reg = <0x1800000 0x1000>;
-        interrupt-parent = <&core_pic>;
-        interrupts = < 12 13 14 15 >;
-        ti,c64x+megamod-pic-mux = <  0  0  0  0
-                                    32  0  0  0
-                                     0  0  0  0 >;
-  };
-
-  This the same as the first example except that megamodule interrupt 32 is
-  mapped directly to core priority interrupt 8. The node using this interrupt
-  must set the core controller as its interrupt parent and use 8 in the
-  interrupt specifier value.
diff --git a/Documentation/devicetree/bindings/c6x/soc.txt b/Documentation/devicetree/bindings/c6x/soc.txt
deleted file mode 100644
index b1e4973b576..00000000000
--- a/Documentation/devicetree/bindings/c6x/soc.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-C6X System-on-Chip
-------------------
-
-Required properties:
-
-- compatible: "simple-bus"
-- #address-cells: must be 1
-- #size-cells: must be 1
-- ranges
-
-Optional properties:
-
-- model: specific SoC model
-
-- nodes for IP blocks within SoC
-
-
-Example:
-
-        soc {
-                compatible = "simple-bus";
-                model = "tms320c6455";
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-
-                ...
-        };
diff --git a/Documentation/devicetree/bindings/c6x/timer64.txt b/Documentation/devicetree/bindings/c6x/timer64.txt
deleted file mode 100644
index 95911fe7022..00000000000
--- a/Documentation/devicetree/bindings/c6x/timer64.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-Timer64
--------
-
-The timer64 node describes C6X event timers.
-
-Required properties:
-
-- compatible: must be "ti,c64x+timer64"
-- reg: base address and size of register region
-- interrupt-parent: interrupt controller
-- interrupts: interrupt id
-
-Optional properties:
-
-- ti,dscr-dev-enable: Device ID used to enable timer IP through DSCR interface.
-
-- ti,core-mask: on multi-core SoCs, bitmask of cores allowed to use this timer.
-
-Example:
-        timer0: timer@25e0000 {
-                compatible = "ti,c64x+timer64";
-                ti,core-mask = < 0x01 >;
-                reg = <0x25e0000 0x40>;
-                interrupt-parent = <&megamod_pic>;
-                interrupts = < 16 >;
-        };
diff --git a/Documentation/devicetree/bindings/clock/calxeda.txt b/Documentation/devicetree/bindings/clock/calxeda.txt
deleted file mode 100644
index 0a6ac1bdcda..00000000000
--- a/Documentation/devicetree/bindings/clock/calxeda.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-Device Tree Clock bindings for Calxeda highbank platform
-
-This binding uses the common clock binding[1].
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Required properties:
-- compatible : shall be one of the following:
-        "calxeda,hb-pll-clock" - for a PLL clock
-        "calxeda,hb-a9periph-clock" - The A9 peripheral clock divided from the
-                A9 clock.
-        "calxeda,hb-a9bus-clock" - The A9 bus clock divided from the A9 clock.
-        "calxeda,hb-emmc-clock" - Divided clock for MMC/SD controller.
-- reg : shall be the control register offset from SYSREGs base for the clock.
-- clocks : shall be the input parent clock phandle for the clock. This is
-        either an oscillator or a pll output.
-- #clock-cells : from common clock binding; shall be set to 0.
diff --git a/Documentation/devicetree/bindings/clock/clock-bindings.txt b/Documentation/devicetree/bindings/clock/clock-bindings.txt
deleted file mode 100644
index eb65d417f8c..00000000000
--- a/Documentation/devicetree/bindings/clock/clock-bindings.txt
+++ /dev/null
@@ -1,117 +0,0 @@
-This binding is a work-in-progress, and are based on some experimental
-work by benh[1].
-
-Sources of clock signal can be represented by any node in the device
-tree.  Those nodes are designated as clock providers.  Clock consumer
-nodes use a phandle and clock specifier pair to connect clock provider
-outputs to clock inputs.  Similar to the gpio specifiers, a clock
-specifier is an array of one more more cells identifying the clock
-output on a device.  The length of a clock specifier is defined by the
-value of a #clock-cells property in the clock provider node.
-
-[1] http://patchwork.ozlabs.org/patch/31551/
-
-==Clock providers==
-
-Required properties:
-#clock-cells:      Number of cells in a clock specifier; Typically 0 for nodes
-                   with a single clock output and 1 for nodes with multiple
-                   clock outputs.
-
-Optional properties:
-clock-output-names: Recommended to be a list of strings of clock output signal
-                    names indexed by the first cell in the clock specifier.
-                    However, the meaning of clock-output-names is domain
-                    specific to the clock provider, and is only provided to
-                    encourage using the same meaning for the majority of clock
-                    providers.  This format may not work for clock providers
-                    using a complex clock specifier format.  In those cases it
-                    is recommended to omit this property and create a binding
-                    specific names property.
-
-                    Clock consumer nodes must never directly reference
-                    the provider's clock-output-names property.
-
-For example:
-
-    oscillator {
-        #clock-cells = <1>;
-        clock-output-names = "ckil", "ckih";
-    };
-
-- this node defines a device with two clock outputs, the first named
-  "ckil" and the second named "ckih".  Consumer nodes always reference
-  clocks by index. The names should reflect the clock output signal
-  names for the device.
-
-==Clock consumers==
-
-Required properties:
-clocks:         List of phandle and clock specifier pairs, one pair
-                for each clock input to the device.  Note: if the
-                clock provider specifies '0' for #clock-cells, then
-                only the phandle portion of the pair will appear.
-
-Optional properties:
-clock-names:    List of clock input name strings sorted in the same
-                order as the clocks property.  Consumers drivers
-                will use clock-names to match clock input names
-                with clocks specifiers.
-clock-ranges:   Empty property indicating that child nodes can inherit named
-                clocks from this node. Useful for bus nodes to provide a
-                clock to their children.
-
-For example:
-
-    device {
-        clocks = <&osc 1>, <&ref 0>;
-        clock-names = "baud", "register";
-    };
-
-
-This represents a device with two clock inputs, named "baud" and "register".
-The baud clock is connected to output 1 of the &osc device, and the register
-clock is connected to output 0 of the &ref.
-
-==Example==
-
-    /* external oscillator */
-    osc: oscillator {
-        compatible = "fixed-clock";
-        #clock-cells = <1>;
-        clock-frequency  = <32678>;
-        clock-output-names = "osc";
-    };
-
-    /* phase-locked-loop device, generates a higher frequency clock
-     * from the external oscillator reference */
-    pll: pll@4c000 {
-        compatible = "vendor,some-pll-interface"
-        #clock-cells = <1>;
-        clocks = <&osc 0>;
-        clock-names = "ref";
-        reg = <0x4c000 0x1000>;
-        clock-output-names = "pll", "pll-switched";
-    };
-
-    /* UART, using the low frequency oscillator for the baud clock,
-     * and the high frequency switched PLL output for register
-     * clocking */
-    uart@a000 {
-        compatible = "fsl,imx-uart";
-        reg = <0xa000 0x1000>;
-        interrupts = <33>;
-        clocks = <&osc 0>, <&pll 1>;
-        clock-names = "baud", "register";
-    };
-
-This DT fragment defines three devices: an external oscillator to provide a
-low-frequency reference clock, a PLL device to generate a higher frequency
-clock signal, and a UART.
-
-* The oscillator is fixed-frequency, and provides one clock output, named "osc".
-* The PLL is both a clock provider and a clock consumer. It uses the clock
-  signal generated by the external oscillator, and provides two output signals
-  ("pll" and "pll-switched").
-* The UART has its baud clock connected the external oscillator and its
-  register clock connected to the PLL clock (the "pll-switched" signal)
diff --git a/Documentation/devicetree/bindings/clock/fixed-clock.txt b/Documentation/devicetree/bindings/clock/fixed-clock.txt
deleted file mode 100644
index 0b1fe782409..00000000000
--- a/Documentation/devicetree/bindings/clock/fixed-clock.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-Binding for simple fixed-rate clock sources.
-
-This binding uses the common clock binding[1].
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Required properties:
-- compatible : shall be "fixed-clock".
-- #clock-cells : from common clock binding; shall be set to 0.
-- clock-frequency : frequency of clock in Hz. Should be a single cell.
-
-Optional properties:
-- gpios : From common gpio binding; gpio connection to clock enable pin.
-- clock-output-names : From common clock binding.
-
-Example:
-        clock {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                clock-frequency = <1000000000>;
-        };
diff --git a/Documentation/devicetree/bindings/clock/imx23-clock.txt b/Documentation/devicetree/bindings/clock/imx23-clock.txt
deleted file mode 100644
index 5083c0b834b..00000000000
--- a/Documentation/devicetree/bindings/clock/imx23-clock.txt
+++ /dev/null
@@ -1,71 +0,0 @@
-* Clock bindings for Freescale i.MX23
-
-Required properties:
-- compatible: Should be "fsl,imx23-clkctrl"
-- reg: Address and length of the register set
-- #clock-cells: Should be <1>
-
-The clock consumer should specify the desired clock by having the clock
-ID in its "clocks" phandle cell.  The following is a full list of i.MX23
-clocks and IDs.
-
-        Clock           ID
-        ------------------
-        ref_xtal        0
-        pll             1
-        ref_cpu         2
-        ref_emi         3
-        ref_pix         4
-        ref_io          5
-        saif_sel        6
-        lcdif_sel       7
-        gpmi_sel        8
-        ssp_sel         9
-        emi_sel         10
-        cpu             11
-        etm_sel         12
-        cpu_pll         13
-        cpu_xtal        14
-        hbus            15
-        xbus            16
-        lcdif_div       17
-        ssp_div         18
-        gpmi_div        19
-        emi_pll         20
-        emi_xtal        21
-        etm_div         22
-        saif_div        23
-        clk32k_div      24
-        rtc             25
-        adc             26
-        spdif_div       27
-        clk32k          28
-        dri             29
-        pwm             30
-        filt            31
-        uart            32
-        ssp             33
-        gpmi            34
-        spdif           35
-        emi             36
-        saif            37
-        lcdif           38
-        etm             39
-        usb             40
-        usb_phy         41
-
-Examples:
-
-clks: clkctrl@80040000 {
-        compatible = "fsl,imx23-clkctrl";
-        reg = <0x80040000 0x2000>;
-        #clock-cells = <1>;
-};
-
-auart0: serial@8006c000 {
-        compatible = "fsl,imx23-auart";
-        reg = <0x8006c000 0x2000>;
-        interrupts = <24 25 23>;
-        clocks = <&clks 32>;
-        status = "disabled";
-};
diff --git a/Documentation/devicetree/bindings/clock/imx25-clock.txt b/Documentation/devicetree/bindings/clock/imx25-clock.txt
deleted file mode 100644
index db4f2f05c4d..00000000000
--- a/Documentation/devicetree/bindings/clock/imx25-clock.txt
+++ /dev/null
@@ -1,158 +0,0 @@
-* Clock bindings for Freescale i.MX25
-
-Required properties:
-- compatible: Should be "fsl,imx25-ccm"
-- reg: Address and length of the register set
-- interrupts: Should contain CCM interrupt
-- #clock-cells: Should be <1>
-
-The clock consumer should specify the desired clock by having the clock
-ID in its "clocks" phandle cell.  The following is a full list of i.MX25
-clocks and IDs.
-
-        Clock                   ID
-        ---------------------------
-        dummy                   0
-        osc                     1
-        mpll                    2
-        upll                    3
-        mpll_cpu_3_4            4
-        cpu_sel                 5
-        cpu                     6
-        ahb                     7
-        usb_div                 8
-        ipg                     9
-        per0_sel                10
-        per1_sel                11
-        per2_sel                12
-        per3_sel                13
-        per4_sel                14
-        per5_sel                15
-        per6_sel                16
-        per7_sel                17
-        per8_sel                18
-        per9_sel                19
-        per10_sel               20
-        per11_sel               21
-        per12_sel               22
-        per13_sel               23
-        per14_sel               24
-        per15_sel               25
-        per0                    26
-        per1                    27
-        per2                    28
-        per3                    29
-        per4                    30
-        per5                    31
-        per6                    32
-        per7                    33
-        per8                    34
-        per9                    35
-        per10                   36
-        per11                   37
-        per12                   38
-        per13                   39
-        per14                   40
-        per15                   41
-        csi_ipg_per             42
-        epit_ipg_per            43
-        esai_ipg_per            44
-        esdhc1_ipg_per          45
-        esdhc2_ipg_per          46
-        gpt_ipg_per             47
-        i2c_ipg_per             48
-        lcdc_ipg_per            49
-        nfc_ipg_per             50
-        owire_ipg_per           51
-        pwm_ipg_per             52
-        sim1_ipg_per            53
-        sim2_ipg_per            54
-        ssi1_ipg_per            55
-        ssi2_ipg_per            56
-        uart_ipg_per            57
-        ata_ahb                 58
-        reserved                59
-        csi_ahb                 60
-        emi_ahb                 61
-        esai_ahb                62
-        esdhc1_ahb              63
-        esdhc2_ahb              64
-        fec_ahb                 65
-        lcdc_ahb                66
-        rtic_ahb                67
-        sdma_ahb                68
-        slcdc_ahb               69
-        usbotg_ahb              70
-        reserved                71
-        reserved                72
-        reserved                73
-        reserved                74
-        can1_ipg                75
-        can2_ipg                76
-        csi_ipg                 77
-        cspi1_ipg               78
-        cspi2_ipg               79
-        cspi3_ipg               80
-        dryice_ipg              81
-        ect_ipg                 82
-        epit1_ipg               83
-        epit2_ipg               84
-        reserved                85
-        esdhc1_ipg              86
-        esdhc2_ipg              87
-        fec_ipg                 88
-        reserved                89
-        reserved                90
-        reserved                91
-        gpt1_ipg                92
-        gpt2_ipg                93
-        gpt3_ipg                94
-        gpt4_ipg                95
-        reserved                96
-        reserved                97
-        reserved                98
-        iim_ipg                 99
-        reserved                100
-        reserved                101
-        kpp_ipg                 102
-        lcdc_ipg                103
-        reserved                104
-        pwm1_ipg                105
-        pwm2_ipg                106
-        pwm3_ipg                107
-        pwm4_ipg                108
-        rngb_ipg                109
-        reserved                110
-        scc_ipg                 111
-        sdma_ipg                112
-        sim1_ipg                113
-        sim2_ipg                114
-        slcdc_ipg               115
-        spba_ipg                116
-        ssi1_ipg                117
-        ssi2_ipg                118
-        tsc_ipg                 119
-        uart1_ipg               120
-        uart2_ipg               121
-        uart3_ipg               122
-        uart4_ipg               123
-        uart5_ipg               124
-        reserved                125
-        wdt_ipg                 126
-
-Examples:
-
-clks: ccm@53f80000 {
-        compatible = "fsl,imx25-ccm";
-        reg = <0x53f80000 0x4000>;
-        interrupts = <31>;
-};
-
-uart1: serial@43f90000 {
-        compatible = "fsl,imx25-uart", "fsl,imx21-uart";
-        reg = <0x43f90000 0x4000>;
-        interrupts = <45>;
-        clocks = <&clks 79>, <&clks 50>;
-        clock-names = "ipg", "per";
-        status = "disabled";
-};
diff --git a/Documentation/devicetree/bindings/clock/imx28-clock.txt b/Documentation/devicetree/bindings/clock/imx28-clock.txt
deleted file mode 100644
index e6587af62ff..00000000000
--- a/Documentation/devicetree/bindings/clock/imx28-clock.txt
+++ /dev/null
@@ -1,94 +0,0 @@
-* Clock bindings for Freescale i.MX28
-
-Required properties:
-- compatible: Should be "fsl,imx28-clkctrl"
-- reg: Address and length of the register set
-- #clock-cells: Should be <1>
-
-The clock consumer should specify the desired clock by having the clock
-ID in its "clocks" phandle cell.  The following is a full list of i.MX28
-clocks and IDs.
-
-        Clock           ID
-        ------------------
-        ref_xtal        0
-        pll0            1
-        pll1            2
-        pll2            3
-        ref_cpu         4
-        ref_emi         5
-        ref_io0         6
-        ref_io1         7
-        ref_pix         8
-        ref_hsadc       9
-        ref_gpmi        10
-        saif0_sel       11
-        saif1_sel       12
-        gpmi_sel        13
-        ssp0_sel        14
-        ssp1_sel        15
-        ssp2_sel        16
-        ssp3_sel        17
-        emi_sel         18
-        etm_sel         19
-        lcdif_sel       20
-        cpu             21
-        ptp_sel         22
-        cpu_pll         23
-        cpu_xtal        24
-        hbus            25
-        xbus            26
-        ssp0_div        27
-        ssp1_div        28
-        ssp2_div        29
-        ssp3_div        30
-        gpmi_div        31
-        emi_pll         32
-        emi_xtal        33
-        lcdif_div       34
-        etm_div         35
-        ptp             36
-        saif0_div       37
-        saif1_div       38
-        clk32k_div      39
-        rtc             40
-        lradc           41
-        spdif_div       42
-        clk32k          43
-        pwm             44
-        uart            45
-        ssp0            46
-        ssp1            47
-        ssp2            48
-        ssp3            49
-        gpmi            50
-        spdif           51
-        emi             52
-        saif0           53
-        saif1           54
-        lcdif           55
-        etm             56
-        fec             57
-        can0            58
-        can1            59
-        usb0            60
-        usb1            61
-        usb0_phy        62
-        usb1_phy        63
-        enet_out        64
-
-Examples:
-
-clks: clkctrl@80040000 {
-        compatible = "fsl,imx28-clkctrl";
-        reg = <0x80040000 0x2000>;
-        #clock-cells = <1>;
-};
-
-auart0: serial@8006a000 {
-        compatible = "fsl,imx28-auart", "fsl,imx23-auart";
-        reg = <0x8006a000 0x2000>;
-        interrupts = <112 70 71>;
-        clocks = <&clks 45>;
-        status = "disabled";
-};
diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt
deleted file mode 100644
index 04ad47876be..00000000000
--- a/Documentation/devicetree/bindings/clock/imx5-clock.txt
+++ /dev/null
@@ -1,191 +0,0 @@
-* Clock bindings for Freescale i.MX5
-
-Required properties:
-- compatible: Should be "fsl,<soc>-ccm" , where <soc> can be imx51 or imx53
-- reg: Address and length of the register set
-- interrupts: Should contain CCM interrupt
-- #clock-cells: Should be <1>
-
-The clock consumer should specify the desired clock by having the clock
-ID in its "clocks" phandle cell.  The following is a full list of i.MX5
-clocks and IDs.
-
-        Clock                   ID
-        ---------------------------
-        dummy                   0
-        ckil                    1
-        osc                     2
-        ckih1                   3
-        ckih2                   4
-        ahb                     5
-        ipg                     6
-        axi_a                   7
-        axi_b                   8
-        uart_pred               9
-        uart_root               10
-        esdhc_a_pred            11
-        esdhc_b_pred            12
-        esdhc_c_s               13
-        esdhc_d_s               14
-        emi_sel                 15
-        emi_slow_podf           16
-        nfc_podf                17
-        ecspi_pred              18
-        ecspi_podf              19
-        usboh3_pred             20
-        usboh3_podf             21
-        usb_phy_pred            22
-        usb_phy_podf            23
-        cpu_podf                24
-        di_pred                 25
-        tve_di                  26
-        tve_s                   27
-        uart1_ipg_gate          28
-        uart1_per_gate          29
-        uart2_ipg_gate          30
-        uart2_per_gate          31
-        uart3_ipg_gate          32
-        uart3_per_gate          33
-        i2c1_gate               34
-        i2c2_gate               35
-        gpt_ipg_gate            36
-        pwm1_ipg_gate           37
-        pwm1_hf_gate            38
-        pwm2_ipg_gate           39
-        pwm2_hf_gate            40
-        gpt_hf_gate             41
-        fec_gate                42
-        usboh3_per_gate         43
-        esdhc1_ipg_gate         44
-        esdhc2_ipg_gate         45
-        esdhc3_ipg_gate         46
-        esdhc4_ipg_gate         47
-        ssi1_ipg_gate           48
-        ssi2_ipg_gate           49
-        ssi3_ipg_gate           50
-        ecspi1_ipg_gate         51
-        ecspi1_per_gate         52
-        ecspi2_ipg_gate         53
-        ecspi2_per_gate         54
-        cspi_ipg_gate           55
-        sdma_gate               56
-        emi_slow_gate           57
-        ipu_s                   58
-        ipu_gate                59
-        nfc_gate                60
-        ipu_di1_gate            61
-        vpu_s                   62
-        vpu_gate                63
-        vpu_reference_gate      64
-        uart4_ipg_gate          65
-        uart4_per_gate          66
-        uart5_ipg_gate          67
-        uart5_per_gate          68
-        tve_gate                69
-        tve_pred                70
-        esdhc1_per_gate         71
-        esdhc2_per_gate         72
-        esdhc3_per_gate         73
-        esdhc4_per_gate         74
-        usb_phy_gate            75
-        hsi2c_gate              76
-        mipi_hsc1_gate          77
-        mipi_hsc2_gate          78
-        mipi_esc_gate           79
-        mipi_hsp_gate           80
-        ldb_di1_div_3_5         81
-        ldb_di1_div             82
-        ldb_di0_div_3_5         83
-        ldb_di0_div             84
-        ldb_di1_gate            85
-        can2_serial_gate        86
-        can2_ipg_gate           87
-        i2c3_gate               88
-        lp_apm                  89
-        periph_apm              90
-        main_bus                91
-        ahb_max                 92
-        aips_tz1                93
-        aips_tz2                94
-        tmax1                   95
-        tmax2                   96
-        tmax3                   97
-        spba                    98
-        uart_sel                99
-        esdhc_a_sel             100
-        esdhc_b_sel             101
-        esdhc_a_podf            102
-        esdhc_b_podf            103
-        ecspi_sel               104
-        usboh3_sel              105
-        usb_phy_sel             106
-        iim_gate                107
-        usboh3_gate             108
-        emi_fast_gate           109
-        ipu_di0_gate            110
-        gpc_dvfs                111
-        pll1_sw                 112
-        pll2_sw                 113
-        pll3_sw                 114
-        ipu_di0_sel             115
-        ipu_di1_sel             116
-        tve_ext_sel             117
-        mx51_mipi               118
-        pll4_sw                 119
-        ldb_di1_sel             120
-        di_pll4_podf            121
-        ldb_di0_sel             122
-        ldb_di0_gate            123
-        usb_phy1_gate           124
-        usb_phy2_gate           125
-        per_lp_apm              126
-        per_pred1               127
-        per_pred2               128
-        per_podf                129
-        per_root                130
-        ssi_apm                 131
-        ssi1_root_sel           132
-        ssi2_root_sel           133
-        ssi3_root_sel           134
-        ssi_ext1_sel            135
-        ssi_ext2_sel            136
-        ssi_ext1_com_sel        137
-        ssi_ext2_com_sel        138
-        ssi1_root_pred          139
-        ssi1_root_podf          140
-        ssi2_root_pred          141
-        ssi2_root_podf          142
-        ssi_ext1_pred           143
-        ssi_ext1_podf           144
-        ssi_ext2_pred           145
-        ssi_ext2_podf           146
-        ssi1_root_gate          147
-        ssi2_root_gate          148
-        ssi3_root_gate          149
-        ssi_ext1_gate           150
-        ssi_ext2_gate           151
-        epit1_ipg_gate          152
-        epit1_hf_gate           153
-        epit2_ipg_gate          154
-        epit2_hf_gate           155
-        can_sel                 156
-        can1_serial_gate        157
-        can1_ipg_gate           158
-
-Examples (for mx53):
-
-clks: ccm@53fd4000{
-        compatible = "fsl,imx53-ccm";
-        reg = <0x53fd4000 0x4000>;
-        interrupts = <0 71 0x04 0 72 0x04>;
-        #clock-cells = <1>;
-};
-
-can1: can@53fc8000 {
-        compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
-        reg = <0x53fc8000 0x4000>;
-        interrupts = <82>;
-        clocks = <&clks 158>, <&clks 157>;
-        clock-names = "ipg", "per";
-        status = "disabled";
-};
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
deleted file mode 100644
index f73fdf59556..00000000000
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+++ /dev/null
@@ -1,223 +0,0 @@
-* Clock bindings for Freescale i.MX6 Quad
-
-Required properties:
-- compatible: Should be "fsl,imx6q-ccm"
-- reg: Address and length of the register set
-- interrupts: Should contain CCM interrupt
-- #clock-cells: Should be <1>
-
-The clock consumer should specify the desired clock by having the clock
-ID in its "clocks" phandle cell.  The following is a full list of i.MX6Q
-clocks and IDs.
-
-        Clock                   ID
-        ---------------------------
-        dummy                   0
-        ckil                    1
-        ckih                    2
-        osc                     3
-        pll2_pfd0_352m          4
-        pll2_pfd1_594m          5
-        pll2_pfd2_396m          6
-        pll3_pfd0_720m          7
-        pll3_pfd1_540m          8
-        pll3_pfd2_508m          9
-        pll3_pfd3_454m          10
-        pll2_198m               11
-        pll3_120m               12
-        pll3_80m                13
-        pll3_60m                14
-        twd                     15
-        step                    16
-        pll1_sw                 17
-        periph_pre              18
-        periph2_pre             19
-        periph_clk2_sel         20
-        periph2_clk2_sel        21
-        axi_sel                 22
-        esai_sel                23
-        asrc_sel                24
-        spdif_sel               25
-        gpu2d_axi               26
-        gpu3d_axi               27
-        gpu2d_core_sel          28
-        gpu3d_core_sel          29
-        gpu3d_shader_sel        30
-        ipu1_sel                31
-        ipu2_sel                32
-        ldb_di0_sel             33
-        ldb_di1_sel             34
-        ipu1_di0_pre_sel        35
-        ipu1_di1_pre_sel        36
-        ipu2_di0_pre_sel        37
-        ipu2_di1_pre_sel        38
-        ipu1_di0_sel            39
-        ipu1_di1_sel            40
-        ipu2_di0_sel            41
-        ipu2_di1_sel            42
-        hsi_tx_sel              43
-        pcie_axi_sel            44
-        ssi1_sel                45
-        ssi2_sel                46
-        ssi3_sel                47
-        usdhc1_sel              48
-        usdhc2_sel              49
-        usdhc3_sel              50
-        usdhc4_sel              51
-        enfc_sel                52
-        emi_sel                 53
-        emi_slow_sel            54
-        vdo_axi_sel             55
-        vpu_axi_sel             56
-        cko1_sel                57
-        periph                  58
-        periph2                 59
-        periph_clk2             60
-        periph2_clk2            61
-        ipg                     62
-        ipg_per                 63
-        esai_pred               64
-        esai_podf               65
-        asrc_pred               66
-        asrc_podf               67
-        spdif_pred              68
-        spdif_podf              69
-        can_root                70
-        ecspi_root              71
-        gpu2d_core_podf         72
-        gpu3d_core_podf         73
-        gpu3d_shader            74
-        ipu1_podf               75
-        ipu2_podf               76
-        ldb_di0_podf            77
-        ldb_di1_podf            78
-        ipu1_di0_pre            79
-        ipu1_di1_pre            80
-        ipu2_di0_pre            81
-        ipu2_di1_pre            82
-        hsi_tx_podf             83
-        ssi1_pred               84
-        ssi1_podf               85
-        ssi2_pred               86
-        ssi2_podf               87
-        ssi3_pred               88
-        ssi3_podf               89
-        uart_serial_podf        90
-        usdhc1_podf             91
-        usdhc2_podf             92
-        usdhc3_podf             93
-        usdhc4_podf             94
-        enfc_pred               95
-        enfc_podf               96
-        emi_podf                97
-        emi_slow_podf           98
-        vpu_axi_podf            99
-        cko1_podf               100
-        axi                     101
-        mmdc_ch0_axi_podf       102
-        mmdc_ch1_axi_podf       103
-        arm                     104
-        ahb                     105
-        apbh_dma                106
-        asrc                    107
-        can1_ipg                108
-        can1_serial             109
-        can2_ipg                110
-        can2_serial             111
-        ecspi1                  112
-        ecspi2                  113
-        ecspi3                  114
-        ecspi4                  115
-        ecspi5                  116
-        enet                    117
-        esai                    118
-        gpt_ipg                 119
-        gpt_ipg_per             120
-        gpu2d_core              121
-        gpu3d_core              122
-        hdmi_iahb               123
-        hdmi_isfr               124
-        i2c1                    125
-        i2c2                    126
-        i2c3                    127
-        iim                     128
-        enfc                    129
-        ipu1                    130
-        ipu1_di0                131
-        ipu1_di1                132
-        ipu2                    133
-        ipu2_di0                134
-        ldb_di0                 135
-        ldb_di1                 136
-        ipu2_di1                137
-        hsi_tx                  138
-        mlb                     139
-        mmdc_ch0_axi            140
-        mmdc_ch1_axi            141
-        ocram                   142
-        openvg_axi              143
-        pcie_axi                144
-        pwm1                    145
-        pwm2                    146
-        pwm3                    147
-        pwm4                    148
-        per1_bch                149
-        gpmi_bch_apb            150
-        gpmi_bch                151
-        gpmi_io                 152
-        gpmi_apb                153
-        sata                    154
-        sdma                    155
-        spba                    156
-        ssi1                    157
-        ssi2                    158
-        ssi3                    159
-        uart_ipg                160
-        uart_serial             161
-        usboh3                  162
-        usdhc1                  163
-        usdhc2                  164
-        usdhc3                  165
-        usdhc4                  166
-        vdo_axi                 167
-        vpu_axi                 168
-        cko1                    169
-        pll1_sys                170
-        pll2_bus                171
-        pll3_usb_otg            172
-        pll4_audio              173
-        pll5_video              174
-        pll8_mlb                175
-        pll7_usb_host           176
-        pll6_enet               177
-        ssi1_ipg                178
-        ssi2_ipg                179
-        ssi3_ipg                180
-        rom                     181
-        usbphy1                 182
-        usbphy2                 183
-        ldb_di0_div_3_5         184
-        ldb_di1_div_3_5         185
-        sata_ref                186
-        sata_ref_100m           187
-        pcie_ref                188
-        pcie_ref_125m           189
-        enet_ref                190
-
-Examples:
-
-clks: ccm@020c4000 {
-        compatible = "fsl,imx6q-ccm";
-        reg = <0x020c4000 0x4000>;
-        interrupts = <0 87 0x04 0 88 0x04>;
-        #clock-cells = <1>;
-};
-
-uart1: serial@02020000 {
-        compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
-        reg = <0x02020000 0x4000>;
-        interrupts = <0 26 0x04>;
-        clocks = <&clks 160>, <&clks 161>;
-        clock-names = "ipg", "per";
-        status = "disabled";
-};
diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
deleted file mode 100644
index 1e662948661..00000000000
--- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
+++ /dev/null
@@ -1,47 +0,0 @@
-* Core Clock bindings for Marvell MVEBU SoCs
-
-Marvell MVEBU SoCs usually allow to determine core clock frequencies by
-reading the Sample-At-Reset (SAR) register. The core clock consumer should
-specify the desired clock by having the clock ID in its "clocks" phandle cell.
-
-The following is a list of provided IDs and clock names on Armada 370/XP:
- 0 = tclk    (Internal Bus clock)
- 1 = cpuclk  (CPU clock)
- 2 = nbclk   (L2 Cache clock)
- 3 = hclk    (DRAM control clock)
- 4 = dramclk (DDR clock)
-
-The following is a list of provided IDs and clock names on Kirkwood and Dove:
- 0 = tclk   (Internal Bus clock)
- 1 = cpuclk (CPU0 clock)
- 2 = l2clk  (L2 Cache clock derived from CPU0 clock)
- 3 = ddrclk (DDR controller clock derived from CPU0 clock)
-
-Required properties:
-- compatible : shall be one of the following:
-        "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
-        "marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
-        "marvell,dove-core-clock" - for Dove SoC core clocks
-        "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
-        "marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
-- reg : shall be the register address of the Sample-At-Reset (SAR) register
-- #clock-cells : from common clock binding; shall be set to 1
-
-Optional properties:
-- clock-output-names : from common clock binding; allows overwrite default clock
-        output names ("tclk", "cpuclk", "l2clk", "ddrclk")
-
-Example:
-
-core_clk: core-clocks@d0214 {
-        compatible = "marvell,dove-core-clock";
-        reg = <0xd0214 0x4>;
-        #clock-cells = <1>;
-};
-
-spi0: spi@10600 {
-        compatible = "marvell,orion-spi";
-        /* ... */
-        /* get tclk from core clock provider */
-        clocks = <&core_clk 0>;
-};
diff --git a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
deleted file mode 100644
index feb83013071..00000000000
--- a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-Device Tree Clock bindings for cpu clock of Marvell EBU platforms
-
-Required properties:
-- compatible : shall be one of the following:
-        "marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
-- reg : Address and length of the clock complex register set
-- #clock-cells : should be set to 1.
-- clocks : shall be the input parent clock phandle for the clock.
-
-cpuclk: clock-complex@d0018700 {
-        #clock-cells = <1>;
-        compatible = "marvell,armada-xp-cpu-clock";
-        reg = <0xd0018700 0xA0>;
-        clocks = <&coreclk 1>;
-}
-
-cpu@0 {
-        compatible = "marvell,sheeva-v7";
-        reg = <0>;
-        clocks = <&cpuclk 0>;
-};
diff --git a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
deleted file mode 100644
index 7337005ef5e..00000000000
--- a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
+++ /dev/null
@@ -1,119 +0,0 @@
-* Gated Clock bindings for Marvell Orion SoCs
-
-Marvell Dove and Kirkwood allow some peripheral clocks to be gated to save
-some power. The clock consumer should specify the desired clock by having
-the clock ID in its "clocks" phandle cell. The clock ID is directly mapped to
-the corresponding clock gating control bit in HW to ease manual clock lookup
-in datasheet.
-
-The following is a list of provided IDs for Armada 370:
-ID      Clock   Peripheral
------------------------------------
-0       Audio   AC97 Cntrl
-1       pex0_en PCIe 0 Clock out
-2       pex1_en PCIe 1 Clock out
-3       ge1     Gigabit Ethernet 1
-4       ge0     Gigabit Ethernet 0
-5       pex0    PCIe Cntrl 0
-9       pex1    PCIe Cntrl 1
-15      sata0   SATA Host 0
-17      sdio    SDHCI Host
-25      tdm     Time Division Mplx
-28      ddr     DDR Cntrl
-30      sata1   SATA Host 0
-
-The following is a list of provided IDs for Armada XP:
-ID      Clock   Peripheral
------------------------------------
-0       audio   Audio Cntrl
-1       ge3     Gigabit Ethernet 3
-2       ge2     Gigabit Ethernet 2
-3       ge1     Gigabit Ethernet 1
-4       ge0     Gigabit Ethernet 0
-5       pex0    PCIe Cntrl 0
-6       pex1    PCIe Cntrl 1
-7       pex2    PCIe Cntrl 2
-8       pex3    PCIe Cntrl 3
-13      bp
-14      sata0lnk
-15      sata0   SATA Host 0
-16      lcd     LCD Cntrl
-17      sdio    SDHCI Host
-18      usb0    USB Host 0
-19      usb1    USB Host 1
-20      usb2    USB Host 2
-22      xor0    XOR DMA 0
-23      crypto  CESA engine
-25      tdm     Time Division Mplx
-28      xor1    XOR DMA 1
-29      sata1lnk
-30      sata1   SATA Host 0
-
-The following is a list of provided IDs for Dove:
-ID      Clock   Peripheral
------------------------------------
-0       usb0    USB Host 0
-1       usb1    USB Host 1
-2       ge      Gigabit Ethernet
-3       sata    SATA Host
-4       pex0    PCIe Cntrl 0
-5       pex1    PCIe Cntrl 1
-8       sdio0   SDHCI Host 0
-9       sdio1   SDHCI Host 1
-10      nand    NAND Cntrl
-11      camera  Camera Cntrl
-12      i2s0    I2S Cntrl 0
-13      i2s1    I2S Cntrl 1
-15      crypto  CESA engine
-21      ac97    AC97 Cntrl
-22      pdma    Peripheral DMA
-23      xor0    XOR DMA 0
-24      xor1    XOR DMA 1
-30      gephy   Gigabit Ethernel PHY
-Note: gephy(30) is implemented as a parent clock of ge(2)
-
-The following is a list of provided IDs for Kirkwood:
-ID      Clock   Peripheral
------------------------------------
-0       ge0     Gigabit Ethernet 0
-2       pex0    PCIe Cntrl 0
-3       usb0    USB Host 0
-4       sdio    SDIO Cntrl
-5       tsu     Transp. Stream Unit
-6       dunit   SDRAM Cntrl
-7       runit   Runit
-8       xor0    XOR DMA 0
-9       audio   I2S Cntrl 0
-14      sata0   SATA Host 0
-15      sata1   SATA Host 1
-16      xor1    XOR DMA 1
-17      crypto  CESA engine
-18      pex1    PCIe Cntrl 1
-19      ge1     Gigabit Ethernet 0
-20      tdm     Time Division Mplx
-
-Required properties:
-- compatible : shall be one of the following:
-        "marvell,dove-gating-clock" - for Dove SoC clock gating
-        "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
-- reg : shall be the register address of the Clock Gating Control register
-- #clock-cells : from common clock binding; shall be set to 1
-
-Optional properties:
-- clocks : default parent clock phandle (e.g. tclk)
-
-Example:
-
-gate_clk: clock-gating-control@d0038 {
-        compatible = "marvell,dove-gating-clock";
-        reg = <0xd0038 0x4>;
-        /* default parent clock is tclk */
-        clocks = <&core_clk 0>;
-        #clock-cells = <1>;
-};
-
-sdio0: sdio@92000 {
-        compatible = "marvell,dove-sdhci";
-        /* get clk gate bit 8 (sdio0) */
-        clocks = <&gate_clk 8>;
-};
diff --git a/Documentation/devicetree/bindings/clock/vt8500.txt b/Documentation/devicetree/bindings/clock/vt8500.txt
deleted file mode 100644
index a880c70d004..00000000000
--- a/Documentation/devicetree/bindings/clock/vt8500.txt
+++ /dev/null
@@ -1,72 +0,0 @@
-Device Tree Clock bindings for arch-vt8500
-
-This binding uses the common clock binding[1].
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Required properties:
-- compatible : shall be one of the following:
-        "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
-        "wm,wm8650-pll-clock" - for a WM8650 PLL clock
-        "via,vt8500-device-clock" - for a VT/WM device clock
-
-Required properties for PLL clocks:
-- reg : shall be the control register offset from PMC base for the pll clock.
-- clocks : shall be the input parent clock phandle for the clock. This should
-        be the reference clock.
-- #clock-cells : from common clock binding; shall be set to 0.
-
-Required properties for device clocks:
-- clocks : shall be the input parent clock phandle for the clock. This should
-        be a pll output.
-- #clock-cells : from common clock binding; shall be set to 0.
-
-
-Device Clocks
-
-Device clocks are required to have one or both of the following sets of
-properties:
-
-
-Gated device clocks:
-
-Required properties:
-- enable-reg : shall be the register offset from PMC base for the enable
-        register.
-- enable-bit : shall be the bit within enable-reg to enable/disable the clock.
-
-
-Divisor device clocks:
-
-Required property:
-- divisor-reg : shall be the register offset from PMC base for the divisor
-        register.
-Optional property:
-- divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f
-        if not specified.
-
-
-For example:
-
-ref25: ref25M {
-        #clock-cells = <0>;
-        compatible = "fixed-clock";
-        clock-frequency = <25000000>;
-};
-
-plla: plla {
-        #clock-cells = <0>;
-        compatible = "wm,wm8650-pll-clock";
-        clocks = <&ref25>;
-        reg = <0x200>;
-};
-
-sdhc: sdhc {
-        #clock-cells = <0>;
-        compatible = "via,vt8500-device-clock";
-        clocks = <&pllb>;
-        divisor-reg = <0x328>;
-        divisor-mask = <0x3f>;
-        enable-reg = <0x254>;
-        enable-bit = <18>;
-};
diff --git a/Documentation/devicetree/bindings/clock/zynq-7000.txt b/Documentation/devicetree/bindings/clock/zynq-7000.txt
deleted file mode 100644
index 23ae1db1bc1..00000000000
--- a/Documentation/devicetree/bindings/clock/zynq-7000.txt
+++ /dev/null
@@ -1,55 +0,0 @@
-Device Tree Clock bindings for the Zynq 7000 EPP
-
-The Zynq EPP has several different clk providers, each with there own bindings.
-The purpose of this document is to document their usage.
-
-See clock_bindings.txt for more information on the generic clock bindings.
-See Chapter 25 of Zynq TRM for more information about Zynq clocks.
-
-== PLLs ==
-
-Used to describe the ARM_PLL, DDR_PLL, and IO_PLL.
-
-Required properties:
-- #clock-cells : shall be 0 (only one clock is output from this node)
-- compatible : "xlnx,zynq-pll"
-- reg : pair of u32 values, which are the address offsets within the SLCR
-        of the relevant PLL_CTRL register and PLL_CFG register respectively
-- clocks : phandle for parent clock.  should be the phandle for ps_clk
-
-Optional properties:
-- clock-output-names : name of the output clock
-
-Example:
-        armpll: armpll {
-                #clock-cells = <0>;
-                compatible = "xlnx,zynq-pll";
-                clocks = <&ps_clk>;
-                reg = <0x100 0x110>;
-                clock-output-names = "armpll";
-        };
-
-== Peripheral clocks ==
-
-Describes clock node for the SDIO, SMC, SPI, QSPI, and UART clocks.
-
-Required properties:
-- #clock-cells : shall be 1
-- compatible : "xlnx,zynq-periph-clock"
-- reg : a single u32 value, describing the offset within the SLCR where
-        the CLK_CTRL register is found for this peripheral
-- clocks : phandle for parent clocks.  should hold phandles for
-           the IO_PLL, ARM_PLL, and DDR_PLL in order
-- clock-output-names : names of the output clock(s).  For peripherals that have
-                       two output clocks (for example, the UART), two clocks
-                       should be listed.
-
-Example:
-        uart_clk: uart_clk {
-                #clock-cells = <1>;
-                compatible = "xlnx,zynq-periph-clock";
-                clocks = <&iopll &armpll &ddrpll>;
-                reg = <0x154>;
-                clock-output-names = "uart0_ref_clk",
-                                     "uart1_ref_clk";
-        };
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt
deleted file mode 100644
index 4416ccc3347..00000000000
--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt
+++ /dev/null
@@ -1,55 +0,0 @@
-Generic CPU0 cpufreq driver
-
-It is a generic cpufreq driver for CPU0 frequency management.  It
-supports both uniprocessor (UP) and symmetric multiprocessor (SMP)
-systems which share clock and voltage across all CPUs.
-
-Both required and optional properties listed below must be defined
-under node /cpus/cpu@0.
-
-Required properties:
-- operating-points: Refer to Documentation/devicetree/bindings/power/opp.txt
-  for details
-
-Optional properties:
-- clock-latency: Specify the possible maximum transition latency for clock,
-  in unit of nanoseconds.
-- voltage-tolerance: Specify the CPU voltage tolerance in percentage.
-
-Examples:
-
-cpus {
-        #address-cells = <1>;
-        #size-cells = <0>;
-
-        cpu@0 {
-                compatible = "arm,cortex-a9";
-                reg = <0>;
-                next-level-cache = <&L2>;
-                operating-points = <
-                        /* kHz    uV */
-                        792000  1100000
-                        396000  950000
-                        198000  850000
-                >;
-                transition-latency = <61036>; /* two CLK32 periods */
-        };
-
-        cpu@1 {
-                compatible = "arm,cortex-a9";
-                reg = <1>;
-                next-level-cache = <&L2>;
-        };
-
-        cpu@2 {
-                compatible = "arm,cortex-a9";
-                reg = <2>;
-                next-level-cache = <&L2>;
-        };
-
-        cpu@3 {
-                compatible = "arm,cortex-a9";
-                reg = <3>;
-                next-level-cache = <&L2>;
-        };
-};
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-spear.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-spear.txt
deleted file mode 100644
index f3d44984d91..00000000000
--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-spear.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-SPEAr cpufreq driver
--------------------
-
-SPEAr SoC cpufreq driver for CPU frequency scaling.
-It supports both uniprocessor (UP) and symmetric multiprocessor (SMP) systems
-which share clock across all CPUs.
-
-Required properties:
-- cpufreq_tbl: Table of frequencies CPU could be transitioned into, in the
-  increasing order.
-
-Optional properties:
-- clock-latency: Specify the possible maximum transition latency for clock, in
-  unit of nanoseconds.
-
-Both required and optional properties listed above must be defined under node
-/cpus/cpu@0.
-
-Examples:
---------
-cpus {
-
-        <...>
-
-        cpu@0 {
-                compatible = "arm,cortex-a9";
-                reg = <0>;
-
-                <...>
-
-                cpufreq_tbl = < 166000
-                                200000
-                                250000
-                                300000
-                                400000
-                                500000
-                                600000 >;
-        };
-
-        <...>
-
-};
diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
index fc9ce6f1688..bf57ecd5d73 100644
--- a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
+++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
@@ -9,7 +9,6 @@ Copyright (C) 2008-2011 Freescale Semiconductor Inc.
    -Run Time Integrity Check (RTIC) Node
    -Run Time Integrity Check (RTIC) Memory Node
    -Secure Non-Volatile Storage (SNVS) Node
-   -Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
    -Full Example
 
 NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
@@ -54,8 +53,7 @@ PROPERTIES
    - compatible
       Usage: required
       Value type: <string>
-      Definition: Must include "fsl,sec-v4.0". Also includes SEC
-           ERA versions (optional) with which the device is compatible.
+      Definition: Must include "fsl,sec-v4.0"
 
    - #address-cells
        Usage: required
@@ -107,7 +105,7 @@ PROPERTIES
 
 EXAMPLE
         crypto@300000 {
-                compatible = "fsl,sec-v4.0", "fsl,sec-era-v2.0";
+                compatible = "fsl,sec-v4.0";
                 #address-cells = <1>;
                 #size-cells = <1>;
                 reg = <0x300000 0x10000>;
@@ -296,27 +294,6 @@ Secure Non-Volatile Storage (SNVS) Node
           address and length of the SEC4 configuration
           registers.
 
-   - #address-cells
-       Usage: required
-       Value type: <u32>
-       Definition: A standard property.  Defines the number of cells
-           for representing physical addresses in child nodes.  Must
-           have a value of 1.
-
-   - #size-cells
-       Usage: required
-       Value type: <u32>
-       Definition: A standard property.  Defines the number of cells
-           for representing the size of physical addresses in
-           child nodes.  Must have a value of 1.
-
-   - ranges
-       Usage: required
-       Value type: <prop-encoded-array>
-       Definition: A standard property.  Specifies the physical address
-           range of the SNVS register space.  A triplet that includes
-           the child address, parent address, & length.
-
    - interrupts
       Usage: required
       Value type: <prop_encoded-array>
@@ -337,34 +314,11 @@ EXAMPLE
         sec_mon@314000 {
                 compatible = "fsl,sec-v4.0-mon";
                 reg = <0x314000 0x1000>;
-                ranges = <0 0x314000 0x1000>;
                 interrupt-parent = <&mpic>;
                 interrupts = <93 2>;
         };
 
 =====================================================================
-Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
-
-  A SNVS child node that defines SNVS LP RTC.
-
-  - compatible
-      Usage: required
-      Value type: <string>
-      Definition: Must include "fsl,sec-v4.0-mon-rtc-lp".
-
-  - reg
-      Usage: required
-      Value type: <prop-encoded-array>
-      Definition: A standard property.  Specifies the physical
-          address and length of the SNVS LP configuration registers.
-
-EXAMPLE
-        sec_mon_rtc_lp@314000 {
-                compatible = "fsl,sec-v4.0-mon-rtc-lp";
-                reg = <0x34 0x58>;
-        };
-
-=====================================================================
 FULL EXAMPLE
 
         crypto: crypto@300000 {
@@ -436,14 +390,8 @@ FULL EXAMPLE
         sec_mon: sec_mon@314000 {
                 compatible = "fsl,sec-v4.0-mon";
                 reg = <0x314000 0x1000>;
-                ranges = <0 0x314000 0x1000>;
                 interrupt-parent = <&mpic>;
                 interrupts = <93 2>;
-
-                sec_mon_rtc_lp@34 {
-                        compatible = "fsl,sec-v4.0-mon-rtc-lp";
-                        reg = <0x34 0x58>;
-                };
         };
 
 =====================================================================
diff --git a/Documentation/devicetree/bindings/crypto/mv_cesa.txt b/Documentation/devicetree/bindings/crypto/mv_cesa.txt
deleted file mode 100644
index 47229b1a594..00000000000
--- a/Documentation/devicetree/bindings/crypto/mv_cesa.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-Marvell Cryptographic Engines And Security Accelerator
-
-Required properties:
-- compatible : should be "marvell,orion-crypto"
-- reg : base physical address of the engine and length of memory mapped
-        region, followed by base physical address of sram and its memory
-        length
-- reg-names : "regs" , "sram";
-- interrupts : interrupt number
-
-Examples:
-
-        crypto@30000 {
-                compatible = "marvell,orion-crypto";
-                reg = <0x30000 0x10000>,
-                      <0x4000000 0x800>;
-                reg-names = "regs" , "sram";
-                interrupts = <22>;
-                status = "okay";
-        };
diff --git a/Documentation/devicetree/bindings/crypto/picochip-spacc.txt b/Documentation/devicetree/bindings/crypto/picochip-spacc.txt
deleted file mode 100644
index d8609ece1f4..00000000000
--- a/Documentation/devicetree/bindings/crypto/picochip-spacc.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-Picochip picoXcell SPAcc (Security Protocol Accelerator) bindings
-
-Picochip picoXcell devices contain crypto offload engines that may be used for
-IPSEC and femtocell layer 2 ciphering.
-
-Required properties:
-  - compatible : "picochip,spacc-ipsec" for the IPSEC offload engine
-    "picochip,spacc-l2" for the femtocell layer 2 ciphering engine.
-  - reg : Offset and length of the register set for this device
-  - interrupt-parent : The interrupt controller that controls the SPAcc
-    interrupt.
-  - interrupts : The interrupt line from the SPAcc.
-  - ref-clock : The input clock that drives the SPAcc.
-
-Example SPAcc node:
-
-spacc@10000 {
-        compatible = "picochip,spacc-ipsec";
-        reg = <0x100000 0x10000>;
-        interrupt-parent = <&vic0>;
-        interrupts = <24>;
-        ref-clock = <&ipsec_clk>, "ref";
-};
diff --git a/Documentation/devicetree/bindings/dma/arm-pl330.txt b/Documentation/devicetree/bindings/dma/arm-pl330.txt
deleted file mode 100644
index 36e27d54260..00000000000
--- a/Documentation/devicetree/bindings/dma/arm-pl330.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-* ARM PrimeCell PL330 DMA Controller
-
-The ARM PrimeCell PL330 DMA controller can move blocks of memory contents
-between memory and peripherals or memory to memory.
-
-Required properties:
-  - compatible: should include both "arm,pl330" and "arm,primecell".
-  - reg: physical base address of the controller and length of memory mapped
-    region.
-  - interrupts: interrupt number to the cpu.
-
-Optional properties:
-- dma-coherent      : Present if dma operations are coherent
-
-Example:
-
-        pdma0: pdma@12680000 {
-                compatible = "arm,pl330", "arm,primecell";
-                reg = <0x12680000 0x1000>;
-                interrupts = <99>;
-        };
-
-Client drivers (device nodes requiring dma transfers from dev-to-mem or
-mem-to-dev) should specify the DMA channel numbers using a two-value pair
-as shown below.
-
-  [property name]  = <[phandle of the dma controller] [dma request id]>;
-
-      where 'dma request id' is the dma request number which is connected
-      to the client controller. The 'property name' is recommended to be
-      of the form <name>-dma-channel.
-
-  Example:  tx-dma-channel = <&pdma0 12>;
diff --git a/Documentation/devicetree/bindings/dma/atmel-dma.txt b/Documentation/devicetree/bindings/dma/atmel-dma.txt
deleted file mode 100644
index 3c046ee6e8b..00000000000
--- a/Documentation/devicetree/bindings/dma/atmel-dma.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-* Atmel Direct Memory Access Controller (DMA)
-
-Required properties:
-- compatible: Should be "atmel,<chip>-dma"
-- reg: Should contain DMA registers location and length
-- interrupts: Should contain DMA interrupt
-
-Examples:
-
-dma@ffffec00 {
-        compatible = "atmel,at91sam9g45-dma";
-        reg = <0xffffec00 0x200>;
-        interrupts = <21>;
-};
diff --git a/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt b/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt
deleted file mode 100644
index ded0398d3bd..00000000000
--- a/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-* Freescale MXS DMA
-
-Required properties:
-- compatible : Should be "fsl,<chip>-dma-apbh" or "fsl,<chip>-dma-apbx"
-- reg : Should contain registers location and length
-
-Supported chips:
-imx23, imx28.
-
-Examples:
-dma-apbh@80004000 {
-        compatible = "fsl,imx28-dma-apbh";
-        reg = <0x80004000 2000>;
-};
-
-dma-apbx@80024000 {
-        compatible = "fsl,imx28-dma-apbx";
-        reg = <0x80024000 2000>;
-};
diff --git a/Documentation/devicetree/bindings/dma/mmp-dma.txt b/Documentation/devicetree/bindings/dma/mmp-dma.txt
deleted file mode 100644
index a4fa4efa1d8..00000000000
--- a/Documentation/devicetree/bindings/dma/mmp-dma.txt
+++ /dev/null
@@ -1,74 +0,0 @@
-* MARVELL MMP DMA controller
-
-Marvell Peripheral DMA Controller
-Used platfroms: pxa688, pxa910, pxa3xx, etc
-
-Required properties:
-- compatible: Should be "marvell,pdma-1.0"
-- reg: Should contain DMA registers location and length.
-- interrupts: Either contain all of the per-channel DMA interrupts
-                or one irq for pdma device
-- #dma-channels: Number of DMA channels supported by the controller.
-
-"marvell,pdma-1.0"
-Used platfroms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688.
-
-Examples:
-
-/*
- * Each channel has specific irq
- * ICU parse out irq channel from ICU register,
- * while DMA controller may not able to distinguish the irq channel
- * Using this method, interrupt-parent is required as demuxer
- * For example, pxa688 icu register 0x128, bit 0~15 is PDMA channel irq,
- * 18~21 is ADMA irq
- */
-pdma: dma-controller@d4000000 {
-              compatible = "marvell,pdma-1.0";
-              reg = <0xd4000000 0x10000>;
-              interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
-              interrupt-parent = <&intcmux32>;
-              #dma-channels = <16>;
-      };
-
-/*
- * One irq for all channels
- * Dmaengine driver (DMA controller) distinguish irq channel via
- * parsing internal register
- */
-pdma: dma-controller@d4000000 {
-              compatible = "marvell,pdma-1.0";
-              reg = <0xd4000000 0x10000>;
-              interrupts = <47>;
-              #dma-channels = <16>;
-      };
-
-
-Marvell Two Channel DMA Controller used specifically for audio
-Used platfroms: pxa688, pxa910
-
-Required properties:
-- compatible: Should be "marvell,adma-1.0" or "marvell,pxa910-squ"
-- reg: Should contain DMA registers location and length.
-- interrupts: Either contain all of the per-channel DMA interrupts
-                or one irq for dma device
-
-"marvell,adma-1.0" used on pxa688
-"marvell,pxa910-squ" used on pxa910
-
-Examples:
-
-/* each channel has specific irq */
-adma0: dma-controller@d42a0800 {
-              compatible = "marvell,adma-1.0";
-              reg = <0xd42a0800 0x100>;
-              interrupts = <18 19>;
-              interrupt-parent = <&intcmux32>;
-      };
-
-/* One irq for all channels */
-squ: dma-controller@d42a0800 {
-              compatible = "marvell,pxa910-squ";
-              reg = <0xd42a0800 0x100>;
-              interrupts = <46>;
-      };
diff --git a/Documentation/devicetree/bindings/dma/mv-xor.txt b/Documentation/devicetree/bindings/dma/mv-xor.txt
deleted file mode 100644
index 7c6cb7fcecd..00000000000
--- a/Documentation/devicetree/bindings/dma/mv-xor.txt
+++ /dev/null
@@ -1,40 +0,0 @@
-* Marvell XOR engines
-
-Required properties:
-- compatible: Should be "marvell,orion-xor"
-- reg: Should contain registers location and length (two sets)
-    the first set is the low registers, the second set the high
-    registers for the XOR engine.
-- clocks: pointer to the reference clock
-
-The DT node must also contains sub-nodes for each XOR channel that the
-XOR engine has. Those sub-nodes have the following required
-properties:
-- interrupts: interrupt of the XOR channel
-
-And the following optional properties:
-- dmacap,memcpy to indicate that the XOR channel is capable of memcpy operations
-- dmacap,memset to indicate that the XOR channel is capable of memset operations
-- dmacap,xor to indicate that the XOR channel is capable of xor operations
-
-Example:
-
-xor@d0060900 {
-        compatible = "marvell,orion-xor";
-        reg = <0xd0060900 0x100
-               0xd0060b00 0x100>;
-        clocks = <&coreclk 0>;
-        status = "okay";
-
-        xor00 {
-              interrupts = <51>;
-              dmacap,memcpy;
-              dmacap,xor;
-        };
-        xor01 {
-              interrupts = <52>;
-              dmacap,memcpy;
-              dmacap,xor;
-              dmacap,memset;
-        };
-};
diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt b/Documentation/devicetree/bindings/dma/snps-dma.txt
deleted file mode 100644
index c0d85dbcada..00000000000
--- a/Documentation/devicetree/bindings/dma/snps-dma.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-* Synopsys Designware DMA Controller
-
-Required properties:
-- compatible: "snps,dma-spear1340"
-- reg: Address range of the DMAC registers
-- interrupt-parent: Should be the phandle for the interrupt controller
-  that services interrupts for this device
-- interrupt: Should contain the DMAC interrupt number
-
-Example:
-
-        dma@fc000000 {
-                compatible = "snps,dma-spear1340";
-                reg = <0xfc000000 0x1000>;
-                interrupt-parent = <&vic1>;
-                interrupts = <12>;
-        };
diff --git a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
deleted file mode 100644
index 90fa7da525b..00000000000
--- a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
+++ /dev/null
@@ -1,30 +0,0 @@
-* NVIDIA Tegra APB DMA controller
-
-Required properties:
-- compatible: Should be "nvidia,<chip>-apbdma"
-- reg: Should contain DMA registers location and length. This shuld include
-  all of the per-channel registers.
-- interrupts: Should contain all of the per-channel DMA interrupts.
-
-Examples:
-
-apbdma: dma@6000a000 {
-        compatible = "nvidia,tegra20-apbdma";
-        reg = <0x6000a000 0x1200>;
-        interrupts = < 0 136 0x04
-                       0 137 0x04
-                       0 138 0x04
-                       0 139 0x04
-                       0 140 0x04
-                       0 141 0x04
-                       0 142 0x04
-                       0 143 0x04
-                       0 144 0x04
-                       0 145 0x04
-                       0 146 0x04
-                       0 147 0x04
-                       0 148 0x04
-                       0 149 0x04
-                       0 150 0x04
-                       0 151 0x04 >;
-};
diff --git a/Documentation/devicetree/bindings/drm/exynos/hdmi.txt b/Documentation/devicetree/bindings/drm/exynos/hdmi.txt
deleted file mode 100644
index 589edee3739..00000000000
--- a/Documentation/devicetree/bindings/drm/exynos/hdmi.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-Device-Tree bindings for drm hdmi driver
-
-Required properties:
-- compatible: value should be "samsung,exynos5-hdmi".
-- reg: physical base address of the hdmi and length of memory mapped
-        region.
-- interrupts: interrupt number to the cpu.
-- hpd-gpio: following information about the hotplug gpio pin.
-        a) phandle of the gpio controller node.
-        b) pin number within the gpio controller.
-        c) pin function mode.
-        d) optional flags and pull up/down.
-        e) drive strength.
-
-Example:
-
-        hdmi {
-                compatible = "samsung,exynos5-hdmi";
-                reg = <0x14530000 0x100000>;
-                interrupts = <0 95 0>;
-                hpd-gpio = <&gpx3 7 0xf 1 3>;
-        };
diff --git a/Documentation/devicetree/bindings/drm/exynos/hdmiddc.txt b/Documentation/devicetree/bindings/drm/exynos/hdmiddc.txt
deleted file mode 100644
index fa166d94580..00000000000
--- a/Documentation/devicetree/bindings/drm/exynos/hdmiddc.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-Device-Tree bindings for hdmiddc driver
-
-Required properties:
-- compatible: value should be "samsung,exynos5-hdmiddc".
-- reg: I2C address of the hdmiddc device.
-
-Example:
-
-        hdmiddc {
-                compatible = "samsung,exynos5-hdmiddc";
-                reg = <0x50>;
-        };
diff --git a/Documentation/devicetree/bindings/drm/exynos/hdmiphy.txt b/Documentation/devicetree/bindings/drm/exynos/hdmiphy.txt
deleted file mode 100644
index 858f4f9b902..00000000000
--- a/Documentation/devicetree/bindings/drm/exynos/hdmiphy.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-Device-Tree bindings for hdmiphy driver
-
-Required properties:
-- compatible: value should be "samsung,exynos5-hdmiphy".
-- reg: I2C address of the hdmiphy device.
-
-Example:
-
-        hdmiphy {
-                compatible = "samsung,exynos5-hdmiphy";
-                reg = <0x38>;
-        };
diff --git a/Documentation/devicetree/bindings/drm/exynos/mixer.txt b/Documentation/devicetree/bindings/drm/exynos/mixer.txt
deleted file mode 100644
index 9b2ea034356..00000000000
--- a/Documentation/devicetree/bindings/drm/exynos/mixer.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-Device-Tree bindings for mixer driver
-
-Required properties:
-- compatible: value should be "samsung,exynos5-mixer".
-- reg: physical base address of the mixer and length of memory mapped
-        region.
-- interrupts: interrupt number to the cpu.
-
-Example:
-
-        mixer {
-                compatible = "samsung,exynos5-mixer";
-                reg = <0x14450000 0x10000>;
-                interrupts = <0 94 0>;
-        };
diff --git a/Documentation/devicetree/bindings/fb/mxsfb.txt b/Documentation/devicetree/bindings/fb/mxsfb.txt
deleted file mode 100644
index b41e5e52a67..00000000000
--- a/Documentation/devicetree/bindings/fb/mxsfb.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-* Freescale MXS LCD Interface (LCDIF)
-
-Required properties:
-- compatible: Should be "fsl,<chip>-lcdif".  Supported chips include
-  imx23 and imx28.
-- reg: Address and length of the register set for lcdif
-- interrupts: Should contain lcdif interrupts
-
-Optional properties:
-- panel-enable-gpios : Should specify the gpio for panel enable
-
-Examples:
-
-lcdif@80030000 {
-        compatible = "fsl,imx28-lcdif";
-        reg = <0x80030000 2000>;
-        interrupts = <38 86>;
-        panel-enable-gpios = <&gpio3 30 0>;
-};
diff --git a/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt b/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt
deleted file mode 100644
index 9d6dcd3fe7f..00000000000
--- a/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt
+++ /dev/null
@@ -1,49 +0,0 @@
-* General Purpose Input Output (GPIO) bus.
-
-Properties:
-- compatible: "cavium,octeon-3860-gpio"
-
-  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
-
-- reg: The base address of the GPIO unit's register bank.
-
-- gpio-controller: This is a GPIO controller.
-
-- #gpio-cells: Must be <2>.  The first cell is the GPIO pin.
-
-- interrupt-controller: The GPIO controller is also an interrupt
-  controller, many of its pins may be configured as an interrupt
-  source.
-
-- #interrupt-cells: Must be <2>.  The first cell is the GPIO pin
-   connected to the interrupt source.  The second cell is the interrupt
-   triggering protocol and may have one of four values:
-   1 - edge triggered on the rising edge.
-   2 - edge triggered on the falling edge
-   4 - level triggered active high.
-   8 - level triggered active low.
-
-- interrupts: Interrupt routing for each pin.
-
-Example:
-
-        gpio-controller@1070000000800 {
-                #gpio-cells = <2>;
-                compatible = "cavium,octeon-3860-gpio";
-                reg = <0x10700 0x00000800 0x0 0x100>;
-                gpio-controller;
-                /* Interrupts are specified by two parts:
-                 * 1) GPIO pin number (0..15)
-                 * 2) Triggering (1 - edge rising
-                 *                2 - edge falling
-                 *                4 - level active high
-                 *                8 - level active low)
-                 */
-                interrupt-controller;
-                #interrupt-cells = <2>;
-                /* The GPIO pin connect to 16 consecutive CUI bits */
-                interrupts = <0 16>, <0 17>, <0 18>, <0 19>,
-                             <0 20>, <0 21>, <0 22>, <0 23>,
-                             <0 24>, <0 25>, <0 26>, <0 27>,
-                             <0 28>, <0 29>, <0 30>, <0 31>;
-        };
diff --git a/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt b/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt
index dbd22e0df21..4363ae4b3c1 100644
--- a/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt
@@ -8,25 +8,15 @@ Required properties:
   by low 16 pins and the second one is for high 16 pins.
 - gpio-controller : Marks the device node as a gpio controller.
 - #gpio-cells : Should be two.  The first cell is the pin number and
-  the second cell is used to specify the gpio polarity:
-      0 = active high
-      1 = active low
-- interrupt-controller: Marks the device node as an interrupt controller.
-- #interrupt-cells : Should be 2.  The first cell is the GPIO number.
-  The second cell bits[3:0] is used to specify trigger type and level flags:
-      1 = low-to-high edge triggered.
-      2 = high-to-low edge triggered.
-      4 = active high level-sensitive.
-      8 = active low level-sensitive.
+  the second cell is used to specify optional parameters (currently
+  unused).
 
 Example:
 
 gpio0: gpio@73f84000 {
-        compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
+        compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
         reg = <0x73f84000 0x4000>;
         interrupts = <50 51>;
         gpio-controller;
         #gpio-cells = <2>;
-        interrupt-controller;
-        #interrupt-cells = <2>;
 };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-74x164.txt b/Documentation/devicetree/bindings/gpio/gpio-74x164.txt
deleted file mode 100644
index cc2608021f2..00000000000
--- a/Documentation/devicetree/bindings/gpio/gpio-74x164.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-* Generic 8-bits shift register GPIO driver
-
-Required properties:
-- compatible : Should be "fairchild,74hc595"
-- reg : chip select number
-- gpio-controller : Marks the device node as a gpio controller.
-- #gpio-cells : Should be two.  The first cell is the pin number and
-  the second cell is used to specify the gpio polarity:
-      0 = active high
-      1 = active low
-- registers-number: Number of daisy-chained shift registers
-
-Example:
-
-gpio5: gpio5@0 {
-        compatible = "fairchild,74hc595";
-        reg = <0>;
-        gpio-controller;
-        #gpio-cells = <2>;
-        registers-number = <4>;
-        spi-max-frequency = <100000>;
-};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-adnp.txt b/Documentation/devicetree/bindings/gpio/gpio-adnp.txt
deleted file mode 100644
index af66b272483..00000000000
--- a/Documentation/devicetree/bindings/gpio/gpio-adnp.txt
+++ /dev/null
@@ -1,34 +0,0 @@
-Avionic Design N-bit GPIO expander bindings
-
-Required properties:
-- compatible: should be "ad,gpio-adnp"
-- reg: The I2C slave address for this device.
-- interrupt-parent: phandle of the parent interrupt controller.
-- interrupts: Interrupt specifier for the controllers interrupt.
-- #gpio-cells: Should be 2. The first cell is the GPIO number and the
-  second cell is used to specify optional parameters:
-  - bit 0: polarity (0: normal, 1: inverted)
-- gpio-controller: Marks the device as a GPIO controller
-- nr-gpios: The number of pins supported by the controller.
-
-The GPIO expander can optionally be used as an interrupt controller, in
-which case it uses the default two cell specifier as described in
-Documentation/devicetree/bindings/interrupt-controller/interrupts.txt.
-
-Example:
-
-        gpioext: gpio-controller@41 {
-                compatible = "ad,gpio-adnp";
-                reg = <0x41>;
-
-                interrupt-parent = <&gpio>;
-                interrupts = <160 1>;
-
-                gpio-controller;
-                #gpio-cells = <2>;
-
-                interrupt-controller;
-                #interrupt-cells = <2>;
-
-                nr-gpios = <64>;
-        };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-fan.txt b/Documentation/devicetree/bindings/gpio/gpio-fan.txt
deleted file mode 100644
index 2dd457a3469..00000000000
--- a/Documentation/devicetree/bindings/gpio/gpio-fan.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-Bindings for fan connected to GPIO lines
-
-Required properties:
-- compatible : "gpio-fan"
-- gpios: Specifies the pins that map to bits in the control value,
-  ordered MSB-->LSB.
-- gpio-fan,speed-map: A mapping of possible fan RPM speeds and the
-  control value that should be set to achieve them. This array
-  must have the RPM values in ascending order.
-
-Optional properties:
-- alarm-gpios: This pin going active indicates something is wrong with
-  the fan, and a udev event will be fired.
-
-Examples:
-
-        gpio_fan {
-                compatible = "gpio-fan";
-                gpios = <&gpio1 14 1
-                         &gpio1 13 1>;
-                gpio-fan,speed-map = <0    0
-                                      3000 1
-                                      6000 2>;
-                alarm-gpios = <&gpio1 15 1>;
-        };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mm-lantiq.txt b/Documentation/devicetree/bindings/gpio/gpio-mm-lantiq.txt
deleted file mode 100644
index f93d51478d5..00000000000
--- a/Documentation/devicetree/bindings/gpio/gpio-mm-lantiq.txt
+++ /dev/null
@@ -1,38 +0,0 @@
-Lantiq SoC External Bus memory mapped GPIO controller
-
-By attaching hardware latches to the EBU it is possible to create output
-only gpios. This driver configures a special memory address, which when
-written to outputs 16 bit to the latches.
-
-The node describing the memory mapped GPIOs needs to be a child of the node
-describing the "lantiq,localbus".
-
-Required properties:
-- compatible : Should be "lantiq,gpio-mm-lantiq"
-- reg : Address and length of the register set for the device
-- #gpio-cells : Should be two.  The first cell is the pin number and
-  the second cell is used to specify optional parameters (currently
-  unused).
-- gpio-controller : Marks the device node as a gpio controller.
-
-Optional properties:
-- lantiq,shadow : The default value that we shall assume as already set on the
-  shift register cascade.
-
-Example:
-
-localbus@0 {
-        #address-cells = <2>;
-        #size-cells = <1>;
-        ranges = <0 0 0x0 0x3ffffff /* addrsel0 */
-                1 0 0x4000000 0x4000010>; /* addsel1 */
-        compatible = "lantiq,localbus", "simple-bus";
-
-        gpio_mm0: gpio@4000000 {
-                compatible = "lantiq,gpio-mm";
-                reg = <1 0x0 0x10>;
-                gpio-controller;
-                #gpio-cells = <2>;
-                lantiq,shadow = <0x77f>
-        };
-}
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
deleted file mode 100644
index a6f3bec1da7..00000000000
--- a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
+++ /dev/null
@@ -1,53 +0,0 @@
-* Marvell EBU GPIO controller
-
-Required properties:
-
-- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio"
-  or "marvell,armadaxp-gpio". "marvell,orion-gpio" should be used for
-  Orion, Kirkwood, Dove, Discovery (except MV78200) and Armada
-  370. "marvell,mv78200-gpio" should be used for the Discovery
-  MV78200. "marvel,armadaxp-gpio" should be used for all Armada XP
-  SoCs (MV78230, MV78260, MV78460).
-
-- reg: Address and length of the register set for the device. Only one
-  entry is expected, except for the "marvell,armadaxp-gpio" variant
-  for which two entries are expected: one for the general registers,
-  one for the per-cpu registers.
-
-- interrupts: The list of interrupts that are used for all the pins
-  managed by this GPIO bank. There can be more than one interrupt
-  (example: 1 interrupt per 8 pins on Armada XP, which means 4
-  interrupts per bank of 32 GPIOs).
-
-- interrupt-controller: identifies the node as an interrupt controller
-
-- #interrupt-cells: specifies the number of cells needed to encode an
-  interrupt source. Should be two.
-  The first cell is the GPIO number.
-  The second cell is used to specify flags:
-    bits[3:0] trigger type and level flags:
-      1 = low-to-high edge triggered.
-      2 = high-to-low edge triggered.
-      4 = active high level-sensitive.
-      8 = active low level-sensitive.
-
-- gpio-controller: marks the device node as a gpio controller
-
-- ngpios: number of GPIOs this controller has
-
-- #gpio-cells: Should be two. The first cell is the pin number. The
-  second cell is reserved for flags, unused at the moment.
-
-Example:
-
-                gpio0: gpio@d0018100 {
-                        compatible = "marvell,armadaxp-gpio";
-                        reg = <0xd0018100 0x40>,
-                            <0xd0018800 0x30>;
-                        ngpios = <32>;
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                        interrupts = <16>, <17>, <18>, <19>;
-                };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mxs.txt b/Documentation/devicetree/bindings/gpio/gpio-mxs.txt
deleted file mode 100644
index 1e677a47b83..00000000000
--- a/Documentation/devicetree/bindings/gpio/gpio-mxs.txt
+++ /dev/null
@@ -1,88 +0,0 @@
-* Freescale MXS GPIO controller
-
-The Freescale MXS GPIO controller is part of MXS PIN controller.  The
-GPIOs are organized in port/bank.  Each port consists of 32 GPIOs.
-
-As the GPIO controller is embedded in the PIN controller and all the
-GPIO ports share the same IO space with PIN controller, the GPIO node
-will be represented as sub-nodes of MXS pinctrl node.
-
-Required properties for GPIO node:
-- compatible : Should be "fsl,<soc>-gpio".  The supported SoCs include
-  imx23 and imx28.
-- interrupts : Should be the port interrupt shared by all 32 pins.
-- gpio-controller : Marks the device node as a gpio controller.
-- #gpio-cells : Should be two.  The first cell is the pin number and
-  the second cell is used to specify the gpio polarity:
-      0 = active high
-      1 = active low
-- interrupt-controller: Marks the device node as an interrupt controller.
-- #interrupt-cells : Should be 2.  The first cell is the GPIO number.
-  The second cell bits[3:0] is used to specify trigger type and level flags:
-      1 = low-to-high edge triggered.
-      2 = high-to-low edge triggered.
-      4 = active high level-sensitive.
-      8 = active low level-sensitive.
-
-Note: Each GPIO port should have an alias correctly numbered in "aliases"
-node.
-
-Examples:
-
-aliases {
-        gpio0 = &gpio0;
-        gpio1 = &gpio1;
-        gpio2 = &gpio2;
-        gpio3 = &gpio3;
-        gpio4 = &gpio4;
-};
-
-pinctrl@80018000 {
-        compatible = "fsl,imx28-pinctrl", "simple-bus";
-        reg = <0x80018000 2000>;
-
-        gpio0: gpio@0 {
-                compatible = "fsl,imx28-gpio";
-                interrupts = <127>;
-                gpio-controller;
-                #gpio-cells = <2>;
-                interrupt-controller;
-                #interrupt-cells = <2>;
-        };
-
-        gpio1: gpio@1 {
-                compatible = "fsl,imx28-gpio";
-                interrupts = <126>;
-                gpio-controller;
-                #gpio-cells = <2>;
-                interrupt-controller;
-                #interrupt-cells = <2>;
-        };
-
-        gpio2: gpio@2 {
-                compatible = "fsl,imx28-gpio";
-                interrupts = <125>;
-                gpio-controller;
-                #gpio-cells = <2>;
-                interrupt-controller;
-                #interrupt-cells = <2>;
-        };
-
-        gpio3: gpio@3 {
-                compatible = "fsl,imx28-gpio";
-                interrupts = <124>;
-                gpio-controller;
-                #gpio-cells = <2>;
-                interrupt-controller;
-                #interrupt-cells = <2>;
-        };
-
-        gpio4: gpio@4 {
-                compatible = "fsl,imx28-gpio";
-                interrupts = <123>;
-                gpio-controller;
-                #gpio-cells = <2>;
-                interrupt-controller;
-                #interrupt-cells = <2>;
-        };
-};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-nmk.txt b/Documentation/devicetree/bindings/gpio/gpio-nmk.txt
deleted file mode 100644
index 8315ac7780e..00000000000
--- a/Documentation/devicetree/bindings/gpio/gpio-nmk.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-Nomadik GPIO controller
-
-Required properties:
-- compatible            : Should be "st,nomadik-gpio".
-- reg                   : Physical base address and length of the controller's registers.
-- interrupts            : The interrupt outputs from the controller.
-- #gpio-cells           : Should be two:
-                            The first cell is the pin number.
-                            The second cell is used to specify optional parameters:
-                              - bits[3:0] trigger type and level flags:
-                                  1 = low-to-high edge triggered.
-                                  2 = high-to-low edge triggered.
-                                  4 = active high level-sensitive.
-                                  8 = active low level-sensitive.
-- gpio-controller       : Marks the device node as a GPIO controller.
-- interrupt-controller  : Marks the device node as an interrupt controller.
-- gpio-bank             : Specifies which bank a controller owns.
-- st,supports-sleepmode : Specifies whether controller can sleep or not
-
-Example:
-
-                gpio1: gpio@8012e080 {
-                        compatible = "st,nomadik-gpio";
-                        reg =  <0x8012e080 0x80>;
-                        interrupts = <0 120 0x4>;
-                        #gpio-cells = <2>;
-                        gpio-controller;
-                        interrupt-controller;
-                        st,supports-sleepmode;
-                        gpio-bank = <1>;
-                };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-omap.txt b/Documentation/devicetree/bindings/gpio/gpio-omap.txt
deleted file mode 100644
index bff51a2fee1..00000000000
--- a/Documentation/devicetree/bindings/gpio/gpio-omap.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-OMAP GPIO controller bindings
-
-Required properties:
-- compatible:
-  - "ti,omap2-gpio" for OMAP2 controllers
-  - "ti,omap3-gpio" for OMAP3 controllers
-  - "ti,omap4-gpio" for OMAP4 controllers
-- #gpio-cells : Should be two.
-  - first cell is the pin number
-  - second cell is used to specify optional parameters (unused)
-- gpio-controller : Marks the device node as a GPIO controller.
-- #interrupt-cells : Should be 2.
-- interrupt-controller: Mark the device node as an interrupt controller
-  The first cell is the GPIO number.
-  The second cell is used to specify flags:
-    bits[3:0] trigger type and level flags:
-      1 = low-to-high edge triggered.
-      2 = high-to-low edge triggered.
-      4 = active high level-sensitive.
-      8 = active low level-sensitive.
-
-OMAP specific properties:
-- ti,hwmods: Name of the hwmod associated to the GPIO:
-  "gpio<X>", <X> being the 1-based instance number from the HW spec
-
-
-Example:
-
-gpio4: gpio4 {
-    compatible = "ti,omap4-gpio";
-    ti,hwmods = "gpio4";
-    #gpio-cells = <2>;
-    gpio-controller;
-    #interrupt-cells = <2>;
-    interrupt-controller;
-};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-poweroff.txt b/Documentation/devicetree/bindings/gpio/gpio-poweroff.txt
deleted file mode 100644
index d4eab9227ea..00000000000
--- a/Documentation/devicetree/bindings/gpio/gpio-poweroff.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-Driver a GPIO line that can be used to turn the power off.
-
-The driver supports both level triggered and edge triggered power off.
-At driver load time, the driver will request the given gpio line and
-install a pm_power_off handler. If the optional properties 'input' is
-not found, the GPIO line will be driven in the inactive
-state. Otherwise its configured as an input.
-
-When the pm_power_off is called, the gpio is configured as an output,
-and drive active, so triggering a level triggered power off
-condition. This will also cause an inactive->active edge condition, so
-triggering positive edge triggered power off. After a delay of 100ms,
-the GPIO is set to inactive, thus causing an active->inactive edge,
-triggering negative edge triggered power off. After another 100ms
-delay the GPIO is driver active again. If the power is still on and
-the CPU still running after a 3000ms delay, a WARN_ON(1) is emitted.
-
-Required properties:
-- compatible : should be "gpio-poweroff".
-- gpios : The GPIO to set high/low, see "gpios property" in
-  Documentation/devicetree/bindings/gpio/gpio.txt. If the pin should be
-  low to power down the board set it to "Active Low", otherwise set
-  gpio to "Active High".
-
-Optional properties:
-- input : Initially configure the GPIO line as an input. Only reconfigure
-  it to an output when the pm_power_off function is called. If this optional
-  property is not specified, the GPIO is initialized as an output in its
-  inactive state.
-
-Examples:
-
-gpio-poweroff {
-        compatible = "gpio-poweroff";
-        gpios = <&gpio 4 0>;
-};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
deleted file mode 100644
index f1e5dfecf55..00000000000
--- a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
+++ /dev/null
@@ -1,84 +0,0 @@
-Samsung Exynos4 GPIO Controller
-
-Required properties:
-- compatible: Compatible property value should be "samsung,exynos4-gpio>".
-
-- reg: Physical base address of the controller and length of memory mapped
-  region.
-
-- #gpio-cells: Should be 4. The syntax of the gpio specifier used by client nodes
-  should be the following with values derived from the SoC user manual.
-     <[phandle of the gpio controller node]
-      [pin number within the gpio controller]
-      [mux function]
-      [flags and pull up/down]
-      [drive strength]>
-
-  Values for gpio specifier:
-  - Pin number: is a value between 0 to 7.
-  - Flags and Pull Up/Down: 0 - Pull Up/Down Disabled.
-                            1 - Pull Down Enabled.
-                            3 - Pull Up Enabled.
-          Bit 16 (0x00010000) - Input is active low.
-  - Drive Strength: 0 - 1x,
-                    1 - 3x,
-                    2 - 2x,
-                    3 - 4x
-
-- gpio-controller: Specifies that the node is a gpio controller.
-- #address-cells: should be 1.
-- #size-cells: should be 1.
-
-Example:
-
-        gpa0: gpio-controller@11400000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "samsung,exynos4-gpio";
-                reg = <0x11400000 0x20>;
-                #gpio-cells = <4>;
-                gpio-controller;
-        };
-
-
-Samsung S3C24XX GPIO Controller
-
-Required properties:
-- compatible: Compatible property value should be "samsung,s3c24xx-gpio".
-
-- reg: Physical base address of the controller and length of memory mapped
-  region.
-
-- #gpio-cells: Should be 3. The syntax of the gpio specifier used by client nodes
-  should be the following with values derived from the SoC user manual.
-     <[phandle of the gpio controller node]
-      [pin number within the gpio controller]
-      [mux function]
-      [flags and pull up/down]
-
-  Values for gpio specifier:
-  - Pin number: depending on the controller a number from 0 up to 15.
-  - Mux function: Depending on the SoC and the gpio bank the gpio can be set
-                  as input, output or a special function
-  - Flags and Pull Up/Down: the values to use differ for the individual SoCs
-                    example S3C2416/S3C2450:
-                            0 - Pull Up/Down Disabled.
-                            1 - Pull Down Enabled.
-                            2 - Pull Up Enabled.
-          Bit 16 (0x00010000) - Input is active low.
-  Consult the user manual for the correct values of Mux and Pull Up/Down.
-
-- gpio-controller: Specifies that the node is a gpio controller.
-- #address-cells: should be 1.
-- #size-cells: should be 1.
-
-Example:
-
-        gpa: gpio-controller@56000000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "samsung,s3c24xx-gpio";
-                reg = <0x56000000 0x10>;
-                #gpio-cells = <3>;
-                gpio-controller;
-        };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-stmpe.txt b/Documentation/devicetree/bindings/gpio/gpio-stmpe.txt
deleted file mode 100644
index a0e4cf88521..00000000000
--- a/Documentation/devicetree/bindings/gpio/gpio-stmpe.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-STMPE gpio
-----------
-
-Required properties:
- - compatible: "st,stmpe-gpio"
-
-Optional properties:
- - st,norequest-mask: bitmask specifying which GPIOs should _not_ be requestable
-   due to different usage (e.g. touch, keypad)
-
-Node name must be stmpe_gpio and should be child node of stmpe node to which it
-belongs.
-
-Example:
-        stmpe_gpio {
-                compatible = "st,stmpe-gpio";
-                st,norequest-mask = <0x20>;     //gpio 5 can't be used
-        };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt b/Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt
deleted file mode 100644
index 854de130a97..00000000000
--- a/Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-Lantiq SoC Serial To Parallel (STP) GPIO controller
-
-The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
-peripheral controller used to drive external shift register cascades. At most
-3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
-to drive the 2 LSBs of the cascade automatically.
-
-
-Required properties:
-- compatible : Should be "lantiq,gpio-stp-xway"
-- reg : Address and length of the register set for the device
-- #gpio-cells : Should be two.  The first cell is the pin number and
-  the second cell is used to specify optional parameters (currently
-  unused).
-- gpio-controller : Marks the device node as a gpio controller.
-
-Optional properties:
-- lantiq,shadow : The default value that we shall assume as already set on the
-  shift register cascade.
-- lantiq,groups : Set the 3 bit mask to select which of the 3 groups are enabled
-  in the shift register cascade.
-- lantiq,dsl : The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit
-  property can enable this feature.
-- lantiq,phy1 : The gphy1 core can control 3 bits of the gpio cascade.
-- lantiq,phy2 : The gphy2 core can control 3 bits of the gpio cascade.
-- lantiq,rising : use rising instead of falling edge for the shift register
-
-Example:
-
-gpio1: stp@E100BB0 {
-        compatible = "lantiq,gpio-stp-xway";
-        reg = <0xE100BB0 0x40>;
-        #gpio-cells = <2>;
-        gpio-controller;
-
-        lantiq,shadow = <0xffff>;
-        lantiq,groups = <0x7>;
-        lantiq,dsl = <0x3>;
-        lantiq,phy1 = <0x7>;
-        lantiq,phy2 = <0x7>;
-        /* lantiq,rising; */
-};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt b/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt
deleted file mode 100644
index 66788fda1db..00000000000
--- a/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-twl4030 GPIO controller bindings
-
-Required properties:
-- compatible:
-  - "ti,twl4030-gpio" for twl4030 GPIO controller
-- #gpio-cells : Should be two.
-  - first cell is the pin number
-  - second cell is used to specify optional parameters (unused)
-- gpio-controller : Marks the device node as a GPIO controller.
-- #interrupt-cells : Should be 2.
-- interrupt-controller: Mark the device node as an interrupt controller
-  The first cell is the GPIO number.
-  The second cell is not used.
-- ti,use-leds : Enables LEDA and LEDB outputs if set
-- ti,debounce : if n-th bit is set, debounces GPIO-n
-- ti,mmc-cd : if n-th bit is set, GPIO-n controls VMMC(n+1)
-- ti,pullups : if n-th bit is set, set a pullup on GPIO-n
-- ti,pulldowns : if n-th bit is set, set a pulldown on GPIO-n
-
-Example:
-
-twl_gpio: gpio {
-    compatible = "ti,twl4030-gpio";
-    #gpio-cells = <2>;
-    gpio-controller;
-    #interrupt-cells = <2>;
-    interrupt-controller;
-    ti,use-leds;
-};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-vt8500.txt b/Documentation/devicetree/bindings/gpio/gpio-vt8500.txt
deleted file mode 100644
index f4dc5233167..00000000000
--- a/Documentation/devicetree/bindings/gpio/gpio-vt8500.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-VIA/Wondermedia VT8500 GPIO Controller
------------------------------------------------------
-
-Required properties:
-- compatible : "via,vt8500-gpio", "wm,wm8505-gpio"
-        or "wm,wm8650-gpio" depending on your SoC
-- reg : Should contain 1 register range (address and length)
-- #gpio-cells : should be <3>.
-        1) bank
-        2) pin number
-        3) flags - should be 0
-
-Example:
-
-        gpio: gpio-controller@d8110000 {
-                compatible = "via,vt8500-gpio";
-                gpio-controller;
-                reg = <0xd8110000 0x10000>;
-                #gpio-cells = <3>;
-        };
-
-        vibrate {
-                gpios = <&gpio 0 1 0>; /* Bank 0, Pin 1, No flags */
-        };
diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt
index a33628759d3..4e16ba4feab 100644
--- a/Documentation/devicetree/bindings/gpio/gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio.txt
@@ -75,40 +75,4 @@ Example of two SOC GPIO banks defined as gpio-controller nodes:
                 gpio-controller;
         };
 
-2.1) gpio-controller and pinctrl subsystem
-------------------------------------------
 
-gpio-controller on a SOC might be tightly coupled with the pinctrl
-subsystem, in the sense that the pins can be used by other functions
-together with optional gpio feature.
-
-While the pin allocation is totally managed by the pin ctrl subsystem,
-gpio (under gpiolib) is still maintained by gpio drivers. It may happen
-that different pin ranges in a SoC is managed by different gpio drivers.
-
-This makes it logical to let gpio drivers announce their pin ranges to
-the pin ctrl subsystem and call 'pinctrl_request_gpio' in order to
-request the corresponding pin before any gpio usage.
-
-For this, the gpio controller can use a pinctrl phandle and pins to
-announce the pinrange to the pin ctrl subsystem. For example,
-
-        qe_pio_e: gpio-controller@1460 {
-                #gpio-cells = <2>;
-                compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
-                reg = <0x1460 0x18>;
-                gpio-controller;
-                gpio-ranges = <&pinctrl1 20 10>, <&pinctrl2 50 20>;
-
-    }
-
-where,
-   &pinctrl1 and &pinctrl2 is the phandle to the pinctrl DT node.
-
-   Next values specify the base pin and number of pins for the range
-   handled by 'qe_pio_e' gpio. In the given example from base pin 20 to
-   pin 29 under pinctrl1 and pin 50 to pin 69 under pinctrl2 is handled
-   by this gpio controller.
-
-The pinctrl node must have "#gpio-range-cells" property to show number of
-arguments to pass with phandle from gpio controllers node.
diff --git a/Documentation/devicetree/bindings/gpio/gpio_atmel.txt b/Documentation/devicetree/bindings/gpio/gpio_atmel.txt
deleted file mode 100644
index 85f8c0d084f..00000000000
--- a/Documentation/devicetree/bindings/gpio/gpio_atmel.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-* Atmel GPIO controller (PIO)
-
-Required properties:
-- compatible: "atmel,<chip>-gpio", where <chip> is at91rm9200 or at91sam9x5.
-- reg: Should contain GPIO controller registers location and length
-- interrupts: Should be the port interrupt shared by all the pins.
-- #gpio-cells: Should be two.  The first cell is the pin number and
-  the second cell is used to specify optional parameters (currently
-  unused).
-- gpio-controller: Marks the device node as a GPIO controller.
-
-optional properties:
-- #gpio-lines: Number of gpio if absent 32.
-
-
-Example:
-        pioA: gpio@fffff200 {
-                compatible = "atmel,at91rm9200-gpio";
-                reg = <0xfffff200 0x100>;
-                interrupts = <2 4>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                #gpio-lines = <19>;
-        };
-
diff --git a/Documentation/devicetree/bindings/gpio/gpio_lpc32xx.txt b/Documentation/devicetree/bindings/gpio/gpio_lpc32xx.txt
deleted file mode 100644
index 49819367a01..00000000000
--- a/Documentation/devicetree/bindings/gpio/gpio_lpc32xx.txt
+++ /dev/null
@@ -1,43 +0,0 @@
-NXP LPC32xx SoC GPIO controller
-
-Required properties:
-- compatible: must be "nxp,lpc3220-gpio"
-- reg: Physical base address and length of the controller's registers.
-- gpio-controller: Marks the device node as a GPIO controller.
-- #gpio-cells: Should be 3:
-   1) bank:
-      0: GPIO P0
-      1: GPIO P1
-      2: GPIO P2
-      3: GPIO P3
-      4: GPI P3
-      5: GPO P3
-   2) pin number
-   3) optional parameters:
-      - bit 0 specifies polarity (0 for normal, 1 for inverted)
-- reg: Index of the GPIO group
-
-Example:
-
-        gpio: gpio@40028000 {
-                compatible = "nxp,lpc3220-gpio";
-                reg = <0x40028000 0x1000>;
-                gpio-controller;
-                #gpio-cells = <3>; /* bank, pin, flags */
-        };
-
-        leds {
-                compatible = "gpio-leds";
-
-                led0 {
-                        gpios = <&gpio 5 1 1>; /* GPO_P3 1, active low */
-                        linux,default-trigger = "heartbeat";
-                        default-state = "off";
-                };
-
-                led1 {
-                        gpios = <&gpio 5 14 1>; /* GPO_P3 14, active low */
-                        linux,default-trigger = "timer";
-                        default-state = "off";
-                };
-        };
diff --git a/Documentation/devicetree/bindings/gpio/leds-ns2.txt b/Documentation/devicetree/bindings/gpio/leds-ns2.txt
deleted file mode 100644
index aef3aca34d2..00000000000
--- a/Documentation/devicetree/bindings/gpio/leds-ns2.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-Binding for dual-GPIO LED found on Network Space v2 (and parents).
-
-Required properties:
-- compatible: "lacie,ns2-leds".
-
-Each LED is represented as a sub-node of the ns2-leds device.
-
-Required sub-node properties:
-- cmd-gpio: Command LED GPIO. See OF device-tree GPIO specification.
-- slow-gpio: Slow LED GPIO. See OF device-tree GPIO specification.
-
-Optional sub-node properties:
-- label: Name for this LED. If omitted, the label is taken from the node name.
-- linux,default-trigger: Trigger assigned to the LED.
-
-Example:
-
-ns2-leds {
-        compatible = "lacie,ns2-leds";
-
-        blue-sata {
-                label = "ns2:blue:sata";
-                slow-gpio = <&gpio0 29 0>;
-                cmd-gpio = <&gpio0 30 0>;
-        };
-};
diff --git a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
deleted file mode 100644
index e13787498bc..00000000000
--- a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
+++ /dev/null
@@ -1,52 +0,0 @@
-* Marvell PXA GPIO controller
-
-Required properties:
-- compatible : Should be "mrvl,pxa-gpio" or "mrvl,mmp-gpio"
-- reg : Address and length of the register set for the device
-- interrupts : Should be the port interrupt shared by all gpio pins.
-  There're three gpio interrupts in arch-pxa, and they're gpio0,
-  gpio1 and gpio_mux. There're only one gpio interrupt in arch-mmp,
-  gpio_mux.
-- interrupt-name : Should be the name of irq resource. Each interrupt
-  binds its interrupt-name.
-- interrupt-controller : Identifies the node as an interrupt controller.
-- #interrupt-cells: Specifies the number of cells needed to encode an
-  interrupt source.
-- gpio-controller : Marks the device node as a gpio controller.
-- #gpio-cells : Should be one.  It is the pin number.
-
-Example:
-
-        gpio: gpio@d4019000 {
-                compatible = "mrvl,mmp-gpio";
-                reg = <0xd4019000 0x1000>;
-                interrupts = <49>;
-                interrupt-name = "gpio_mux";
-                gpio-controller;
-                #gpio-cells = <1>;
-                interrupt-controller;
-                #interrupt-cells = <1>;
-      };
-
-* Marvell Orion GPIO Controller
-
-Required properties:
-- compatible         : Should be "marvell,orion-gpio"
-- reg                : Address and length of the register set for controller.
-- gpio-controller    : So we know this is a gpio controller.
-- ngpio              : How many gpios this controller has.
-- interrupts         : Up to 4 Interrupts for the controller.
-
-Optional properties:
-- mask-offset        : For SMP Orions, offset for Nth CPU
-
-Example:
-
-                gpio0: gpio@10100 {
-                        compatible = "marvell,orion-gpio";
-                        #gpio-cells = <2>;
-                        gpio-controller;
-                        reg = <0x10100 0x40>;
-                        ngpio = <32>;
-                        interrupts = <35>, <36>, <37>, <38>;
-                };
diff --git a/Documentation/devicetree/bindings/gpio/nvidia,tegra20-gpio.txt b/Documentation/devicetree/bindings/gpio/nvidia,tegra20-gpio.txt
deleted file mode 100644
index 023c9526e5f..00000000000
--- a/Documentation/devicetree/bindings/gpio/nvidia,tegra20-gpio.txt
+++ /dev/null
@@ -1,40 +0,0 @@
-NVIDIA Tegra GPIO controller
-
-Required properties:
-- compatible : "nvidia,tegra<chip>-gpio"
-- reg : Physical base address and length of the controller's registers.
-- interrupts : The interrupt outputs from the controller. For Tegra20,
-  there should be 7 interrupts specified, and for Tegra30, there should
-  be 8 interrupts specified.
-- #gpio-cells : Should be two. The first cell is the pin number and the
-  second cell is used to specify optional parameters:
-  - bit 0 specifies polarity (0 for normal, 1 for inverted)
-- gpio-controller : Marks the device node as a GPIO controller.
-- #interrupt-cells : Should be 2.
-  The first cell is the GPIO number.
-  The second cell is used to specify flags:
-    bits[3:0] trigger type and level flags:
-      1 = low-to-high edge triggered.
-      2 = high-to-low edge triggered.
-      4 = active high level-sensitive.
-      8 = active low level-sensitive.
-      Valid combinations are 1, 2, 3, 4, 8.
-- interrupt-controller : Marks the device node as an interrupt controller.
-
-Example:
-
-gpio: gpio@6000d000 {
-        compatible = "nvidia,tegra20-gpio";
-        reg = < 0x6000d000 0x1000 >;
-        interrupts = < 0 32 0x04
-                       0 33 0x04
-                       0 34 0x04
-                       0 35 0x04
-                       0 55 0x04
-                       0 87 0x04
-                       0 89 0x04 >;
-        #gpio-cells = <2>;
-        gpio-controller;
-        #interrupt-cells = <2>;
-        interrupt-controller;
-};
diff --git a/Documentation/devicetree/bindings/gpio/pl061-gpio.txt b/Documentation/devicetree/bindings/gpio/pl061-gpio.txt
deleted file mode 100644
index a2c416bcbcc..00000000000
--- a/Documentation/devicetree/bindings/gpio/pl061-gpio.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-ARM PL061 GPIO controller
-
-Required properties:
-- compatible : "arm,pl061", "arm,primecell"
-- #gpio-cells : Should be two. The first cell is the pin number and the
-  second cell is used to specify optional parameters:
-  - bit 0 specifies polarity (0 for normal, 1 for inverted)
-- gpio-controller : Marks the device node as a GPIO controller.
-- interrupts : Interrupt mapping for GPIO IRQ.
-
diff --git a/Documentation/devicetree/bindings/gpio/sodaville.txt b/Documentation/devicetree/bindings/gpio/sodaville.txt
deleted file mode 100644
index 563eff22b97..00000000000
--- a/Documentation/devicetree/bindings/gpio/sodaville.txt
+++ /dev/null
@@ -1,48 +0,0 @@
-GPIO controller on CE4100 / Sodaville SoCs
-==========================================
-
-The bindings for CE4100's GPIO controller match the generic description
-which is covered by the gpio.txt file in this folder.
-
-The only additional property is the intel,muxctl property which holds the
-value which is written into the MUXCNTL register.
-
-There is no compatible property for now because the driver is probed via
-PCI id (vendor 0x8086 device 0x2e67).
-
-The interrupt specifier consists of two cells encoded as follows:
- - <1st cell>: The interrupt-number that identifies the interrupt source.
- - <2nd cell>: The level-sense information, encoded as follows:
-                4 - active high level-sensitive
-                8 - active low level-sensitive
-
-Example of the GPIO device and one user:
-
-        pcigpio: gpio@b,1 {
-                        /* two cells for GPIO and interrupt */
-                        #gpio-cells = <2>;
-                        #interrupt-cells = <2>;
-                        compatible = "pci8086,2e67.2",
-                                           "pci8086,2e67",
-                                           "pciclassff0000",
-                                           "pciclassff00";
-
-                        reg = <0x15900 0x0 0x0 0x0 0x0>;
-                        /* Interrupt line of the gpio device */
-                        interrupts = <15 1>;
-                        /* It is an interrupt and GPIO controller itself */
-                        interrupt-controller;
-                        gpio-controller;
-                        intel,muxctl = <0>;
-        };
-
-        testuser@20 {
-                        compatible = "example,testuser";
-                        /* User the 11th GPIO line as an active high triggered
-                         * level interrupt
-                         */
-                        interrupts = <11 8>;
-                        interrupt-parent = <&pcigpio>;
-                        /* Use this GPIO also with the gpio functions */
-                        gpios = <&pcigpio 11 0>;
-        };
diff --git a/Documentation/devicetree/bindings/gpio/spear_spics.txt b/Documentation/devicetree/bindings/gpio/spear_spics.txt
deleted file mode 100644
index 96c37eb1507..00000000000
--- a/Documentation/devicetree/bindings/gpio/spear_spics.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-=== ST Microelectronics SPEAr SPI CS Driver ===
-
-SPEAr platform provides a provision to control chipselects of ARM PL022 Prime
-Cell spi controller through its system registers, which otherwise remains under
-PL022 control. If chipselect remain under PL022 control then they would be
-released as soon as transfer is over and TxFIFO becomes empty. This is not
-desired by some of the device protocols above spi which expect (multiple)
-transfers without releasing their chipselects.
-
-Chipselects can be controlled by software by turning them as GPIOs. SPEAr
-provides another interface through system registers through which software can
-directly control each PL022 chipselect. Hence, it is natural for SPEAr to export
-the control of this interface as gpio.
-
-Required properties:
-
-  * compatible: should be defined as "st,spear-spics-gpio"
-  * reg: mentioning address range of spics controller
-  * st-spics,peripcfg-reg: peripheral configuration register offset
-  * st-spics,sw-enable-bit: bit offset to enable sw control
-  * st-spics,cs-value-bit: bit offset to drive chipselect low or high
-  * st-spics,cs-enable-mask: chip select number bit mask
-  * st-spics,cs-enable-shift: chip select number program offset
-  * gpio-controller: Marks the device node as gpio controller
-  * #gpio-cells: should be 1 and will mention chip select number
-
-All the above bit offsets are within peripcfg register.
-
-Example:
--------
-spics: spics@e0700000{
-        compatible = "st,spear-spics-gpio";
-        reg = <0xe0700000 0x1000>;
-        st-spics,peripcfg-reg = <0x3b0>;
-        st-spics,sw-enable-bit = <12>;
-        st-spics,cs-value-bit = <11>;
-        st-spics,cs-enable-mask = <3>;
-        st-spics,cs-enable-shift = <8>;
-        gpio-controller;
-        #gpio-cells = <2>;
-};
-
-
-spi0: spi@e0100000 {
-        status = "okay";
-        num-cs = <3>;
-        cs-gpios = <&gpio1 7 0>, <&spics 0>,
-                   <&spics 1>;
-        ...
-}
diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
deleted file mode 100644
index b4fa934ae3a..00000000000
--- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
+++ /dev/null
@@ -1,191 +0,0 @@
-NVIDIA Tegra host1x
-
-Required properties:
-- compatible: "nvidia,tegra<chip>-host1x"
-- reg: Physical base address and length of the controller's registers.
-- interrupts: The interrupt outputs from the controller.
-- #address-cells: The number of cells used to represent physical base addresses
-  in the host1x address space. Should be 1.
-- #size-cells: The number of cells used to represent the size of an address
-  range in the host1x address space. Should be 1.
-- ranges: The mapping of the host1x address space to the CPU address space.
-
-The host1x top-level node defines a number of children, each representing one
-of the following host1x client modules:
-
-- mpe: video encoder
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-mpe"
-  - reg: Physical base address and length of the controller's registers.
-  - interrupts: The interrupt outputs from the controller.
-
-- vi: video input
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-vi"
-  - reg: Physical base address and length of the controller's registers.
-  - interrupts: The interrupt outputs from the controller.
-
-- epp: encoder pre-processor
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-epp"
-  - reg: Physical base address and length of the controller's registers.
-  - interrupts: The interrupt outputs from the controller.
-
-- isp: image signal processor
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-isp"
-  - reg: Physical base address and length of the controller's registers.
-  - interrupts: The interrupt outputs from the controller.
-
-- gr2d: 2D graphics engine
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-gr2d"
-  - reg: Physical base address and length of the controller's registers.
-  - interrupts: The interrupt outputs from the controller.
-
-- gr3d: 3D graphics engine
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-gr3d"
-  - reg: Physical base address and length of the controller's registers.
-
-- dc: display controller
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-dc"
-  - reg: Physical base address and length of the controller's registers.
-  - interrupts: The interrupt outputs from the controller.
-
-  Each display controller node has a child node, named "rgb", that represents
-  the RGB output associated with the controller. It can take the following
-  optional properties:
-  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
-  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
-  - nvidia,edid: supplies a binary EDID blob
-
-- hdmi: High Definition Multimedia Interface
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-hdmi"
-  - reg: Physical base address and length of the controller's registers.
-  - interrupts: The interrupt outputs from the controller.
-  - vdd-supply: regulator for supply voltage
-  - pll-supply: regulator for PLL
-
-  Optional properties:
-  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
-  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
-  - nvidia,edid: supplies a binary EDID blob
-
-- tvo: TV encoder output
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-tvo"
-  - reg: Physical base address and length of the controller's registers.
-  - interrupts: The interrupt outputs from the controller.
-
-- dsi: display serial interface
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-dsi"
-  - reg: Physical base address and length of the controller's registers.
-
-Example:
-
-/ {
-        ...
-
-        host1x {
-                compatible = "nvidia,tegra20-host1x", "simple-bus";
-                reg = <0x50000000 0x00024000>;
-                interrupts = <0 65 0x04   /* mpcore syncpt */
-                              0 67 0x04>; /* mpcore general */
-
-                #address-cells = <1>;
-                #size-cells = <1>;
-
-                ranges = <0x54000000 0x54000000 0x04000000>;
-
-                mpe {
-                        compatible = "nvidia,tegra20-mpe";
-                        reg = <0x54040000 0x00040000>;
-                        interrupts = <0 68 0x04>;
-                };
-
-                vi {
-                        compatible = "nvidia,tegra20-vi";
-                        reg = <0x54080000 0x00040000>;
-                        interrupts = <0 69 0x04>;
-                };
-
-                epp {
-                        compatible = "nvidia,tegra20-epp";
-                        reg = <0x540c0000 0x00040000>;
-                        interrupts = <0 70 0x04>;
-                };
-
-                isp {
-                        compatible = "nvidia,tegra20-isp";
-                        reg = <0x54100000 0x00040000>;
-                        interrupts = <0 71 0x04>;
-                };
-
-                gr2d {
-                        compatible = "nvidia,tegra20-gr2d";
-                        reg = <0x54140000 0x00040000>;
-                        interrupts = <0 72 0x04>;
-                };
-
-                gr3d {
-                        compatible = "nvidia,tegra20-gr3d";
-                        reg = <0x54180000 0x00040000>;
-                };
-
-                dc@54200000 {
-                        compatible = "nvidia,tegra20-dc";
-                        reg = <0x54200000 0x00040000>;
-                        interrupts = <0 73 0x04>;
-
-                        rgb {
-                                status = "disabled";
-                        };
-                };
-
-                dc@54240000 {
-                        compatible = "nvidia,tegra20-dc";
-                        reg = <0x54240000 0x00040000>;
-                        interrupts = <0 74 0x04>;
-
-                        rgb {
-                                status = "disabled";
-                        };
-                };
-
-                hdmi {
-                        compatible = "nvidia,tegra20-hdmi";
-                        reg = <0x54280000 0x00040000>;
-                        interrupts = <0 75 0x04>;
-                        status = "disabled";
-                };
-
-                tvo {
-                        compatible = "nvidia,tegra20-tvo";
-                        reg = <0x542c0000 0x00040000>;
-                        interrupts = <0 76 0x04>;
-                        status = "disabled";
-                };
-
-                dsi {
-                        compatible = "nvidia,tegra20-dsi";
-                        reg = <0x54300000 0x00040000>;
-                        status = "disabled";
-                };
-        };
-
-        ...
-};
diff --git a/Documentation/devicetree/bindings/hwmon/vexpress.txt b/Documentation/devicetree/bindings/hwmon/vexpress.txt
deleted file mode 100644
index 9c27ed694bb..00000000000
--- a/Documentation/devicetree/bindings/hwmon/vexpress.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-Versatile Express hwmon sensors
--------------------------------
-
-Requires node properties:
-- "compatible" value : one of
-        "arm,vexpress-volt"
-        "arm,vexpress-amp"
-        "arm,vexpress-temp"
-        "arm,vexpress-power"
-        "arm,vexpress-energy"
-- "arm,vexpress-sysreg,func" when controlled via vexpress-sysreg
-  (see Documentation/devicetree/bindings/arm/vexpress-sysreg.txt
-  for more details)
-
-Optional node properties:
-- label : string describing the monitored value
-
-Example:
-        energy@0 {
-                compatible = "arm,vexpress-energy";
-                arm,vexpress-sysreg,func = <13 0>;
-                label = "A15 Jcore";
-        };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-at91.txt b/Documentation/devicetree/bindings/i2c/i2c-at91.txt
deleted file mode 100644
index b689a0d9441..00000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-at91.txt
+++ /dev/null
@@ -1,30 +0,0 @@
-I2C for Atmel platforms
-
-Required properties :
-- compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c",
-     "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c"
-     or "atmel,at91sam9x5-i2c"
-- reg: physical base address of the controller and length of memory mapped
-     region.
-- interrupts: interrupt number to the cpu.
-- #address-cells = <1>;
-- #size-cells = <0>;
-
-Optional properties:
-- Child nodes conforming to i2c bus binding
-
-Examples :
-
-i2c0: i2c@fff84000 {
-        compatible = "atmel,at91sam9g20-i2c";
-        reg = <0xfff84000 0x100>;
-        interrupts = <12 4 6>;
-        #address-cells = <1>;
-        #size-cells = <0>;
-
-        24c512@50 {
-                compatible = "24c512";
-                reg = <0x50>;
-                pagesize = <128>;
-        }
-}
diff --git a/Documentation/devicetree/bindings/i2c/i2c-cbus-gpio.txt b/Documentation/devicetree/bindings/i2c/i2c-cbus-gpio.txt
deleted file mode 100644
index 8ce9cd2855b..00000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-cbus-gpio.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-Device tree bindings for i2c-cbus-gpio driver
-
-Required properties:
-        - compatible = "i2c-cbus-gpio";
-        - gpios: clk, dat, sel
-        - #address-cells = <1>;
-        - #size-cells = <0>;
-
-Optional properties:
-        - child nodes conforming to i2c bus binding
-
-Example:
-
-i2c@0 {
-        compatible = "i2c-cbus-gpio";
-        gpios = <&gpio 66 0 /* clk */
-                 &gpio 65 0 /* dat */
-                 &gpio 64 0 /* sel */
-                >;
-        #address-cells = <1>;
-        #size-cells = <0>;
-
-        retu-mfd: retu@1 {
-                compatible = "retu-mfd";
-                reg = <0x1>;
-        };
-};
diff --git a/Documentation/devicetree/bindings/i2c/i2c-davinci.txt b/Documentation/devicetree/bindings/i2c/i2c-davinci.txt
deleted file mode 100644
index 2dc935b4113..00000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-davinci.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-* Texas Instruments Davinci I2C
-
-This file provides information, what the device node for the
-davinci i2c interface contain.
-
-Required properties:
-- compatible: "ti,davinci-i2c";
-- reg : Offset and length of the register set for the device
-
-Recommended properties :
-- interrupts : standard interrupt property.
-- clock-frequency : desired I2C bus clock frequency in Hz.
-
-Example (enbw_cmc board):
-        i2c@1c22000 {
-                compatible = "ti,davinci-i2c";
-                reg = <0x22000 0x1000>;
-                clock-frequency = <100000>;
-                interrupts = <15>;
-                interrupt-parent = <&intc>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                dtt@48 {
-                        compatible = "national,lm75";
-                        reg = <0x48>;
-                };
-        };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-designware.txt b/Documentation/devicetree/bindings/i2c/i2c-designware.txt
deleted file mode 100644
index e42a2ee233e..00000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-designware.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-* Synopsys DesignWare I2C
-
-Required properties :
-
- - compatible : should be "snps,designware-i2c"
- - reg : Offset and length of the register set for the device
- - interrupts : <IRQ> where IRQ is the interrupt number.
-
-Recommended properties :
-
- - clock-frequency : desired I2C bus clock frequency in Hz.
-
-Example :
-
-        i2c@f0000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "snps,designware-i2c";
-                reg = <0xf0000 0x1000>;
-                interrupts = <11>;
-                clock-frequency = <400000>;
-        };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-gpio.txt b/Documentation/devicetree/bindings/i2c/i2c-gpio.txt
deleted file mode 100644
index 4f8ec947c6b..00000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-gpio.txt
+++ /dev/null
@@ -1,32 +0,0 @@
-Device-Tree bindings for i2c gpio driver
-
-Required properties:
-        - compatible = "i2c-gpio";
-        - gpios: sda and scl gpio
-
-
-Optional properties:
-        - i2c-gpio,sda-open-drain: sda as open drain
-        - i2c-gpio,scl-open-drain: scl as open drain
-        - i2c-gpio,scl-output-only: scl as output only
-        - i2c-gpio,delay-us: delay between GPIO operations (may depend on each platform)
-        - i2c-gpio,timeout-ms: timeout to get data
-
-Example nodes:
-
-i2c@0 {
-        compatible = "i2c-gpio";
-        gpios = <&pioA 23 0 /* sda */
-                 &pioA 24 0 /* scl */
-                >;
-        i2c-gpio,sda-open-drain;
-        i2c-gpio,scl-open-drain;
-        i2c-gpio,delay-us = <2>;        /* ~100 kHz */
-        #address-cells = <1>;
-        #size-cells = <0>;
-
-        rv3029c2@56 {
-                compatible = "rv3029c2";
-                reg = <0x56>;
-        };
-};
diff --git a/Documentation/devicetree/bindings/i2c/i2c-imx.txt b/Documentation/devicetree/bindings/i2c/i2c-imx.txt
deleted file mode 100644
index 3614242e773..00000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-imx.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-* Freescale Inter IC (I2C) and High Speed Inter IC (HS-I2C) for i.MX
-
-Required properties:
-- compatible : Should be "fsl,<chip>-i2c"
-- reg : Should contain I2C/HS-I2C registers location and length
-- interrupts : Should contain I2C/HS-I2C interrupt
-
-Optional properties:
-- clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz.
-  The absence of the propoerty indicates the default frequency 100 kHz.
-
-Examples:
-
-i2c@83fc4000 { /* I2C2 on i.MX51 */
-        compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
-        reg = <0x83fc4000 0x4000>;
-        interrupts = <63>;
-};
-
-i2c@70038000 { /* HS-I2C on i.MX51 */
-        compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
-        reg = <0x70038000 0x4000>;
-        interrupts = <64>;
-        clock-frequency = <400000>;
-};
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mpc.txt b/Documentation/devicetree/bindings/i2c/i2c-mpc.txt
deleted file mode 100644
index 1eacd6b20ed..00000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-mpc.txt
+++ /dev/null
@@ -1,64 +0,0 @@
-* I2C
-
-Required properties :
-
- - reg : Offset and length of the register set for the device
- - compatible : should be "fsl,CHIP-i2c" where CHIP is the name of a
-   compatible processor, e.g. mpc8313, mpc8543, mpc8544, mpc5121,
-   mpc5200 or mpc5200b. For the mpc5121, an additional node
-   "fsl,mpc5121-i2c-ctrl" is required as shown in the example below.
-
-Recommended properties :
-
- - interrupts : <a b> where a is the interrupt number and b is a
-   field that represents an encoding of the sense and level
-   information for the interrupt.  This should be encoded based on
-   the information in section 2) depending on the type of interrupt
-   controller you have.
- - interrupt-parent : the phandle for the interrupt controller that
-   services interrupts for this device.
- - fsl,preserve-clocking : boolean; if defined, the clock settings
-   from the bootloader are preserved (not touched).
- - clock-frequency : desired I2C bus clock frequency in Hz.
- - fsl,timeout : I2C bus timeout in microseconds.
-
-Examples :
-
-        /* MPC5121 based board */
-        i2c@1740 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "fsl,mpc5121-i2c", "fsl-i2c";
-                reg = <0x1740 0x20>;
-                interrupts = <11 0x8>;
-                interrupt-parent = <&ipic>;
-                clock-frequency = <100000>;
-        };
-
-        i2ccontrol@1760 {
-                compatible = "fsl,mpc5121-i2c-ctrl";
-                reg = <0x1760 0x8>;
-        };
-
-        /* MPC5200B based board */
-        i2c@3d00 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
-                reg = <0x3d00 0x40>;
-                interrupts = <2 15 0>;
-                interrupt-parent = <&mpc5200_pic>;
-                fsl,preserve-clocking;
-        };
-
-        /* MPC8544 base board */
-        i2c@3100 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "fsl,mpc8544-i2c", "fsl-i2c";
-                reg = <0x3100 0x100>;
-                interrupts = <43 2>;
-                interrupt-parent = <&mpic>;
-                clock-frequency = <400000>;
-                fsl,timeout = <10000>;
-        };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.txt
deleted file mode 100644
index 66709a82554..00000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.txt
+++ /dev/null
@@ -1,81 +0,0 @@
-GPIO-based I2C Bus Mux
-
-This binding describes an I2C bus multiplexer that uses GPIOs to
-route the I2C signals.
-
-                                  +-----+  +-----+
-                                  | dev |  | dev |
-    +------------+                +-----+  +-----+
-    | SoC        |                   |        |
-    |            |          /--------+--------+
-    |   +------+ |  +------+    child bus A, on GPIO value set to 0
-    |   | I2C  |-|--| Mux  |
-    |   +------+ |  +--+---+    child bus B, on GPIO value set to 1
-    |            |     |    \----------+--------+--------+
-    |   +------+ |     |               |        |        |
-    |   | GPIO |-|-----+            +-----+  +-----+  +-----+
-    |   +------+ |                  | dev |  | dev |  | dev |
-    +------------+                  +-----+  +-----+  +-----+
-
-Required properties:
-- compatible: i2c-mux-gpio
-- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
-  port is connected to.
-- mux-gpios: list of gpios used to control the muxer
-* Standard I2C mux properties. See mux.txt in this directory.
-* I2C child bus nodes. See mux.txt in this directory.
-
-Optional properties:
-- idle-state: value to set the muxer to when idle. When no value is
-  given, it defaults to the last value used.
-
-For each i2c child node, an I2C child bus will be created. They will
-be numbered based on their order in the device tree.
-
-Whenever an access is made to a device on a child bus, the value set
-in the revelant node's reg property will be output using the list of
-GPIOs, the first in the list holding the least-significant value.
-
-If an idle state is defined, using the idle-state (optional) property,
-whenever an access is not being made to a device on a child bus, the
-GPIOs will be set according to the idle value.
-
-If an idle state is not defined, the most recently used value will be
-left programmed into hardware whenever no access is being made to a
-device on a child bus.
-
-Example:
-        i2cmux {
-                compatible = "i2c-mux-gpio";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                mux-gpios = <&gpio1 22 0 &gpio1 23 0>;
-                i2c-parent = <&i2c1>;
-
-                i2c@1 {
-                        reg = <1>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        ssd1307: oled@3c {
-                                compatible = "solomon,ssd1307fb-i2c";
-                                reg = <0x3c>;
-                                pwms = <&pwm 4 3000>;
-                                reset-gpios = <&gpio2 7 1>;
-                                reset-active-low;
-                        };
-                };
-
-                i2c@3 {
-                        reg = <3>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        pca9555: pca9555@20 {
-                                compatible = "nxp,pca9555";
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                reg = <0x20>;
-                        };
-                };
-        };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.txt
deleted file mode 100644
index ae8af1694e9..00000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.txt
+++ /dev/null
@@ -1,93 +0,0 @@
-Pinctrl-based I2C Bus Mux
-
-This binding describes an I2C bus multiplexer that uses pin multiplexing to
-route the I2C signals, and represents the pin multiplexing configuration
-using the pinctrl device tree bindings.
-
-                                 +-----+  +-----+
-                                 | dev |  | dev |
-    +------------------------+   +-----+  +-----+
-    | SoC                    |      |        |
-    |                   /----|------+--------+
-    |   +---+   +------+     | child bus A, on first set of pins
-    |   |I2C|---|Pinmux|     |
-    |   +---+   +------+     | child bus B, on second set of pins
-    |                   \----|------+--------+--------+
-    |                        |      |        |        |
-    +------------------------+  +-----+  +-----+  +-----+
-                                | dev |  | dev |  | dev |
-                                +-----+  +-----+  +-----+
-
-Required properties:
-- compatible: i2c-mux-pinctrl
-- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
-  port is connected to.
-
-Also required are:
-
-* Standard pinctrl properties that specify the pin mux state for each child
-  bus. See ../pinctrl/pinctrl-bindings.txt.
-
-* Standard I2C mux properties. See mux.txt in this directory.
-
-* I2C child bus nodes. See mux.txt in this directory.
-
-For each named state defined in the pinctrl-names property, an I2C child bus
-will be created. I2C child bus numbers are assigned based on the index into
-the pinctrl-names property.
-
-The only exception is that no bus will be created for a state named "idle". If
-such a state is defined, it must be the last entry in pinctrl-names. For
-example:
-
-        pinctrl-names = "ddc", "pta", "idle"  ->  ddc = bus 0, pta = bus 1
-        pinctrl-names = "ddc", "idle", "pta"  ->  Invalid ("idle" not last)
-        pinctrl-names = "idle", "ddc", "pta"  ->  Invalid ("idle" not last)
-
-Whenever an access is made to a device on a child bus, the relevant pinctrl
-state will be programmed into hardware.
-
-If an idle state is defined, whenever an access is not being made to a device
-on a child bus, the idle pinctrl state will be programmed into hardware.
-
-If an idle state is not defined, the most recently used pinctrl state will be
-left programmed into hardware whenever no access is being made of a device on
-a child bus.
-
-Example:
-
-        i2cmux {
-                compatible = "i2c-mux-pinctrl";
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                i2c-parent = <&i2c1>;
-
-                pinctrl-names = "ddc", "pta", "idle";
-                pinctrl-0 = <&state_i2cmux_ddc>;
-                pinctrl-1 = <&state_i2cmux_pta>;
-                pinctrl-2 = <&state_i2cmux_idle>;
-
-                i2c@0 {
-                        reg = <0>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        eeprom {
-                                compatible = "eeprom";
-                                reg = <0x50>;
-                        };
-                };
-
-                i2c@1 {
-                        reg = <1>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        eeprom {
-                                compatible = "eeprom";
-                                reg = <0x50>;
-                        };
-                };
-        };
-
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux.txt b/Documentation/devicetree/bindings/i2c/i2c-mux.txt
deleted file mode 100644
index af84cce5cd7..00000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-mux.txt
+++ /dev/null
@@ -1,60 +0,0 @@
-Common i2c bus multiplexer/switch properties.
-
-An i2c bus multiplexer/switch will have several child busses that are
-numbered uniquely in a device dependent manner.  The nodes for an i2c bus
-multiplexer/switch will have one child node for each child
-bus.
-
-Required properties:
-- #address-cells = <1>;
-- #size-cells = <0>;
-
-Required properties for child nodes:
-- #address-cells = <1>;
-- #size-cells = <0>;
-- reg : The sub-bus number.
-
-Optional properties for child nodes:
-- Other properties specific to the multiplexer/switch hardware.
-- Child nodes conforming to i2c bus binding
-
-
-Example :
-
-        /*
-           An NXP pca9548 8 channel I2C multiplexer at address 0x70
-           with two NXP pca8574 GPIO expanders attached, one each to
-           ports 3 and 4.
-         */
-
-        mux@70 {
-                compatible = "nxp,pca9548";
-                reg = <0x70>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                i2c@3 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        reg = <3>;
-
-                        gpio1: gpio@38 {
-                                compatible = "nxp,pca8574";
-                                reg = <0x38>;
-                                #gpio-cells = <2>;
-                                gpio-controller;
-                        };
-                };
-                i2c@4 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        reg = <4>;
-
-                        gpio2: gpio@38 {
-                                compatible = "nxp,pca8574";
-                                reg = <0x38>;
-                                #gpio-cells = <2>;
-                                gpio-controller;
-                        };
-                };
-        };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt b/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt
deleted file mode 100644
index f46d928aa73..00000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-
-* Marvell MV64XXX I2C controller
-
-Required properties :
-
- - reg             : Offset and length of the register set for the device
- - compatible      : Should be "marvell,mv64xxx-i2c"
- - interrupts      : The interrupt number
- - clock-frequency : Desired I2C bus clock frequency in Hz.
-
-Examples:
-
-        i2c@11000 {
-                compatible = "marvell,mv64xxx-i2c";
-                reg = <0x11000 0x20>;
-                interrupts = <29>;
-                clock-frequency = <100000>;
-        };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mxs.txt b/Documentation/devicetree/bindings/i2c/i2c-mxs.txt
deleted file mode 100644
index 7a3fe9e5f4c..00000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-mxs.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-* Freescale MXS Inter IC (I2C) Controller
-
-Required properties:
-- compatible: Should be "fsl,<chip>-i2c"
-- reg: Should contain registers location and length
-- interrupts: Should contain ERROR and DMA interrupts
-- clock-frequency: Desired I2C bus clock frequency in Hz.
-                   Only 100000Hz and 400000Hz modes are supported.
-- fsl,i2c-dma-channel: APBX DMA channel for the I2C
-
-Examples:
-
-i2c0: i2c@80058000 {
-        #address-cells = <1>;
-        #size-cells = <0>;
-        compatible = "fsl,imx28-i2c";
-        reg = <0x80058000 2000>;
-        interrupts = <111 68>;
-        clock-frequency = <100000>;
-        fsl,i2c-dma-channel = <6>;
-};
diff --git a/Documentation/devicetree/bindings/i2c/i2c-nomadik.txt b/Documentation/devicetree/bindings/i2c/i2c-nomadik.txt
deleted file mode 100644
index 72065b0ff68..00000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-nomadik.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-I2C for Nomadik based systems
-
-Required (non-standard) properties:
- - Nil
-
-Recommended (non-standard) properties:
- - clock-frequency : Maximum bus clock frequency for the device
-
-Optional (non-standard) properties:
- - Nil
-
-Example :
-
-i2c@80004000 {
-        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
-        reg = <0x80004000 0x1000>;
-        interrupts = <0 21 0x4>;
-        #address-cells = <1>;
-        #size-cells = <0>;
-        v-i2c-supply = <&db8500_vape_reg>;
-
-        clock-frequency = <400000>;
-};
diff --git a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
deleted file mode 100644
index 1637c298a1b..00000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-Device tree configuration for i2c-ocores
-
-Required properties:
-- compatible      : "opencores,i2c-ocores" or "aeroflexgaisler,i2cmst"
-- reg             : bus address start and address range size of device
-- interrupts      : interrupt number
-- clock-frequency : frequency of bus clock in Hz
-- #address-cells  : should be <1>
-- #size-cells     : should be <0>
-
-Optional properties:
-- reg-shift       : device register offsets are shifted by this value
-- reg-io-width    : io register width in bytes (1, 2 or 4)
-- regstep         : deprecated, use reg-shift above
-
-Example:
-
-        i2c0: ocores@a0000000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "opencores,i2c-ocores";
-                reg = <0xa0000000 0x8>;
-                interrupts = <10>;
-                clock-frequency = <20000000>;
-
-                reg-shift = <0>;        /* 8 bit registers */
-                reg-io-width = <1>;     /* 8 bit read/write */
-
-                dummy@60 {
-                        compatible = "dummy";
-                        reg = <0x60>;
-                };
-        };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-octeon.txt b/Documentation/devicetree/bindings/i2c/i2c-octeon.txt
deleted file mode 100644
index dced82ebe31..00000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-octeon.txt
+++ /dev/null
@@ -1,34 +0,0 @@
-* Two Wire Serial Interface (TWSI) / I2C
-
-- compatible: "cavium,octeon-3860-twsi"
-
-  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
-
-- reg: The base address of the TWSI/I2C bus controller register bank.
-
-- #address-cells: Must be <1>.
-
-- #size-cells: Must be <0>.  I2C addresses have no size component.
-
-- interrupts: A single interrupt specifier.
-
-- clock-frequency: The I2C bus clock rate in Hz.
-
-Example:
-        twsi0: i2c@1180000001000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "cavium,octeon-3860-twsi";
-                reg = <0x11800 0x00001000 0x0 0x200>;
-                interrupts = <0 45>;
-                clock-frequency = <100000>;
-
-                rtc@68 {
-                        compatible = "dallas,ds1337";
-                        reg = <0x68>;
-                };
-                tmp@4c {
-                        compatible = "ti,tmp421";
-                        reg = <0x4c>;
-                };
-        };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-omap.txt b/Documentation/devicetree/bindings/i2c/i2c-omap.txt
deleted file mode 100644
index 56564aa4b44..00000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-omap.txt
+++ /dev/null
@@ -1,30 +0,0 @@
-I2C for OMAP platforms
-
-Required properties :
-- compatible : Must be "ti,omap3-i2c" or "ti,omap4-i2c"
-- ti,hwmods : Must be "i2c<n>", n being the instance number (1-based)
-- #address-cells = <1>;
-- #size-cells = <0>;
-
-Recommended properties :
-- clock-frequency : Desired I2C bus clock frequency in Hz. Otherwise
-  the default 100 kHz frequency will be used.
-
-Optional properties:
-- Child nodes conforming to i2c bus binding
-
-Note: Current implementation will fetch base address, irq and dma
-from omap hwmod data base during device registration.
-Future plan is to migrate hwmod data base contents into device tree
-blob so that, all the required data will be used from device tree dts
-file.
-
-Examples :
-
-i2c1: i2c@0 {
-    compatible = "ti,omap3-i2c";
-    #address-cells = <1>;
-    #size-cells = <0>;
-    ti,hwmods = "i2c1";
-    clock-frequency = <400000>;
-};
diff --git a/Documentation/devicetree/bindings/i2c/i2c-pnx.txt b/Documentation/devicetree/bindings/i2c/i2c-pnx.txt
deleted file mode 100644
index fe98ada33ee..00000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-pnx.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-* NXP PNX I2C Controller
-
-Required properties:
-
- - reg: Offset and length of the register set for the device
- - compatible: should be "nxp,pnx-i2c"
- - interrupts: configure one interrupt line
- - #address-cells: always 1 (for i2c addresses)
- - #size-cells: always 0
- - interrupt-parent: the phandle for the interrupt controller that
-   services interrupts for this device.
-
-Optional properties:
-
- - clock-frequency: desired I2C bus clock frequency in Hz, Default: 100000 Hz
-
-Examples:
-
-        i2c1: i2c@400a0000 {
-                compatible = "nxp,pnx-i2c";
-                reg = <0x400a0000 0x100>;
-                interrupt-parent = <&mic>;
-                interrupts = <51 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-        };
-
-        i2c2: i2c@400a8000 {
-                compatible = "nxp,pnx-i2c";
-                reg = <0x400a8000 0x100>;
-                interrupt-parent = <&mic>;
-                interrupts = <50 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                clock-frequency = <100000>;
-        };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-pxa-pci-ce4100.txt b/Documentation/devicetree/bindings/i2c/i2c-pxa-pci-ce4100.txt
deleted file mode 100644
index 569b1624851..00000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-pxa-pci-ce4100.txt
+++ /dev/null
@@ -1,93 +0,0 @@
-CE4100 I2C
-----------
-
-CE4100 has one PCI device which is described as the I2C-Controller. This
-PCI device has three PCI-bars, each bar contains a complete I2C
-controller. So we have a total of three independent I2C-Controllers
-which share only an interrupt line.
-The driver is probed via the PCI-ID and is gathering the information of
-attached devices from the devices tree.
-Grant Likely recommended to use the ranges property to map the PCI-Bar
-number to its physical address and to use this to find the child nodes
-of the specific I2C controller. This were his exact words:
-
-       Here's where the magic happens.  Each entry in
-       ranges describes how the parent pci address space
-       (middle group of 3) is translated to the local
-       address space (first group of 2) and the size of
-       each range (last cell).  In this particular case,
-       the first cell of the local address is chosen to be
-       1:1 mapped to the BARs, and the second is the
-       offset from be base of the BAR (which would be
-       non-zero if you had 2 or more devices mapped off
-       the same BAR)
-
-       ranges allows the address mapping to be described
-       in a way that the OS can interpret without
-       requiring custom device driver code.
-
-This is an example which is used on FalconFalls:
-------------------------------------------------
-        i2c-controller@b,2 {
-                #address-cells = <2>;
-                #size-cells = <1>;
-                compatible = "pci8086,2e68.2",
-                                "pci8086,2e68",
-                                "pciclass,ff0000",
-                                "pciclass,ff00";
-
-                reg = <0x15a00 0x0 0x0 0x0 0x0>;
-                interrupts = <16 1>;
-
-                /* as described by Grant, the first number in the group of
-                * three is the bar number followed by the 64bit bar address
-                * followed by size of the mapping. The bar address
-                * requires also a valid translation in parents ranges
-                * property.
-                */
-                ranges = <0 0   0x02000000 0 0xdffe0500 0x100
-                          1 0   0x02000000 0 0xdffe0600 0x100
-                          2 0   0x02000000 0 0xdffe0700 0x100>;
-
-                i2c@0 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "intel,ce4100-i2c-controller";
-
-                        /* The first number in the reg property is the
-                        * number of the bar
-                        */
-                        reg = <0 0 0x100>;
-
-                        /* This I2C controller has no devices */
-                };
-
-                i2c@1 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "intel,ce4100-i2c-controller";
-                        reg = <1 0 0x100>;
-
-                        /* This I2C controller has one gpio controller */
-                        gpio@26 {
-                                #gpio-cells = <2>;
-                                compatible = "ti,pcf8575";
-                                reg = <0x26>;
-                                gpio-controller;
-                        };
-                };
-
-                i2c@2 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "intel,ce4100-i2c-controller";
-                        reg = <2 0 0x100>;
-
-                        gpio@26 {
-                                #gpio-cells = <2>;
-                                compatible = "ti,pcf8575";
-                                reg = <0x26>;
-                                gpio-controller;
-                        };
-                };
-        };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-pxa.txt b/Documentation/devicetree/bindings/i2c/i2c-pxa.txt
deleted file mode 100644
index 12b78ac507e..00000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-pxa.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-* Marvell MMP I2C controller
-
-Required properties :
-
- - reg : Offset and length of the register set for the device
- - compatible : should be "mrvl,mmp-twsi" where mmp is the name of a
-   compatible processor, e.g. pxa168, pxa910, mmp2, mmp3.
-   For the pxa2xx/pxa3xx, an additional node "mrvl,pxa-i2c" is required
-   as shown in the example below.
-
-Recommended properties :
-
- - interrupts : the interrupt number
- - interrupt-parent : the phandle for the interrupt controller that
-   services interrupts for this device. If the parent is the default
-   interrupt controller in device tree, it could be ignored.
- - mrvl,i2c-polling : Disable interrupt of i2c controller. Polling
-   status register of i2c controller instead.
- - mrvl,i2c-fast-mode : Enable fast mode of i2c controller.
-
-Examples:
-        twsi1: i2c@d4011000 {
-                compatible = "mrvl,mmp-twsi";
-                reg = <0xd4011000 0x1000>;
-                interrupts = <7>;
-                mrvl,i2c-fast-mode;
-        };
-        
-        twsi2: i2c@d4025000 {
-                compatible = "mrvl,mmp-twsi";
-                reg = <0xd4025000 0x1000>;
-                interrupts = <58>;
-        };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt b/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
deleted file mode 100644
index e9611ace879..00000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
+++ /dev/null
@@ -1,55 +0,0 @@
-* Samsung's I2C controller
-
-The Samsung's I2C controller is used to interface with I2C devices.
-
-Required properties:
-  - compatible: value should be either of the following.
-      (a) "samsung, s3c2410-i2c", for i2c compatible with s3c2410 i2c.
-      (b) "samsung, s3c2440-i2c", for i2c compatible with s3c2440 i2c.
-      (c) "samsung, s3c2440-hdmiphy-i2c", for s3c2440-like i2c used
-          inside HDMIPHY block found on several samsung SoCs
-  - reg: physical base address of the controller and length of memory mapped
-    region.
-  - interrupts: interrupt number to the cpu.
-  - samsung,i2c-sda-delay: Delay (in ns) applied to data line (SDA) edges.
-
-Required for all cases except "samsung,s3c2440-hdmiphy-i2c":
-  - Samsung GPIO variant (deprecated):
-    - gpios: The order of the gpios should be the following: <SDA, SCL>.
-      The gpio specifier depends on the gpio controller. Required in all
-      cases except for "samsung,s3c2440-hdmiphy-i2c" whose input/output
-      lines are permanently wired to the respective clienta
-  - Pinctrl variant (preferred, if available):
-    - pinctrl-0: Pin control group to be used for this controller.
-    - pinctrl-names: Should contain only one value - "default".
-
-Optional properties:
-  - samsung,i2c-slave-addr: Slave address in multi-master enviroment. If not
-    specified, default value is 0.
-  - samsung,i2c-max-bus-freq: Desired frequency in Hz of the bus. If not
-    specified, the default value in Hz is 100000.
-
-Example:
-
-        i2c@13870000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x13870000 0x100>;
-                interrupts = <345>;
-                samsung,i2c-sda-delay = <100>;
-                samsung,i2c-max-bus-freq = <100000>;
-                /* Samsung GPIO variant begins here */
-                gpios = <&gpd1 2 0 /* SDA */
-                         &gpd1 3 0 /* SCL */>;
-                /* Samsung GPIO variant ends here */
-                /* Pinctrl variant begins here */
-                pinctrl-0 = <&i2c3_bus>;
-                pinctrl-names = "default";
-                /* Pinctrl variant ends here */
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                wm8994@1a {
-                        compatible = "wlf,wm8994";
-                        reg = <0x1a>;
-                };
-        };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-sirf.txt b/Documentation/devicetree/bindings/i2c/i2c-sirf.txt
deleted file mode 100644
index 7baf9e133fa..00000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-sirf.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-I2C for SiRFprimaII platforms
-
-Required properties :
-- compatible : Must be "sirf,prima2-i2c"
-- reg: physical base address of the controller and length of memory mapped
-     region.
-- interrupts: interrupt number to the cpu.
-
-Optional properties:
-- clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz.
-  The absence of the propoerty indicates the default frequency 100 kHz.
-
-Examples :
-
-i2c0: i2c@b00e0000 {
-    compatible = "sirf,prima2-i2c";
-    reg = <0xb00e0000 0x10000>;
-    interrupts = <24>;
-};
diff --git a/Documentation/devicetree/bindings/i2c/i2c-versatile.txt b/Documentation/devicetree/bindings/i2c/i2c-versatile.txt
deleted file mode 100644
index 361d31c51b6..00000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-versatile.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-i2c Controller on ARM Versatile platform:
-
-Required properties:
-- compatible : Must be "arm,versatile-i2c";
-- reg
-- #address-cells = <1>;
-- #size-cells = <0>;
-
-Optional properties:
-- Child nodes conforming to i2c bus binding
diff --git a/Documentation/devicetree/bindings/i2c/i2c-xiic.txt b/Documentation/devicetree/bindings/i2c/i2c-xiic.txt
deleted file mode 100644
index ceabbe91ae4..00000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-xiic.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-Xilinx IIC controller:
-
-Required properties:
-- compatible : Must be "xlnx,xps-iic-2.00.a"
-- reg : IIC register location and length
-- interrupts : IIC controller unterrupt
-- #address-cells = <1>
-- #size-cells = <0>
-
-Optional properties:
-- Child nodes conforming to i2c bus binding
-
-Example:
-
-        axi_iic_0: i2c@40800000 {
-                compatible = "xlnx,xps-iic-2.00.a";
-                interrupts = < 1 2 >;
-                reg = < 0x40800000 0x10000 >;
-
-                #size-cells = <0>;
-                #address-cells = <1>;
-        };
diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
deleted file mode 100644
index 446859fcdca..00000000000
--- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt
+++ /dev/null
@@ -1,61 +0,0 @@
-This is a list of trivial i2c devices that have simple device tree
-bindings, consisting only of a compatible field, an address and
-possibly an interrupt line.
-
-If a device needs more specific bindings, such as properties to
-describe some aspect of it, there needs to be a specific binding
-document for it just like any other devices.
-
-
-Compatible              Vendor / Chip
-==========              =============
-ad,ad7414               SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
-ad,adm9240              ADM9240:  Complete System Hardware Monitor for uProcessor-Based Systems
-adi,adt7461             +/-1C TDM Extended Temp Range I.C
-adt7461                 +/-1C TDM Extended Temp Range I.C
-at,24c08                i2c serial eeprom  (24cxx)
-atmel,24c02             i2c serial eeprom  (24cxx)
-catalyst,24c32          i2c serial eeprom
-dallas,ds1307           64 x 8, Serial, I2C Real-Time Clock
-dallas,ds1338           I2C RTC with 56-Byte NV RAM
-dallas,ds1339           I2C Serial Real-Time Clock
-dallas,ds1340           I2C RTC with Trickle Charger
-dallas,ds1374           I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output
-dallas,ds1631           High-Precision Digital Thermometer
-dallas,ds1682           Total-Elapsed-Time Recorder with Alarm
-dallas,ds1775           Tiny Digital Thermometer and Thermostat
-dallas,ds3232           Extremely Accurate I²C RTC with Integrated Crystal and SRAM
-dallas,ds4510           CPU Supervisor with Nonvolatile Memory and Programmable I/O
-dallas,ds75             Digital Thermometer and Thermostat
-dialog,da9053           DA9053: flexible system level PMIC with multicore support
-epson,rx8025            High-Stability. I2C-Bus INTERFACE REAL TIME CLOCK MODULE
-epson,rx8581            I2C-BUS INTERFACE REAL TIME CLOCK MODULE
-fsl,mag3110             MAG3110: Xtrinsic High Accuracy, 3D Magnetometer
-fsl,mc13892             MC13892: Power Management Integrated Circuit (PMIC) for i.MX35/51
-fsl,mma8450             MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer
-fsl,mpr121              MPR121: Proximity Capacitive Touch Sensor Controller
-fsl,sgtl5000            SGTL5000: Ultra Low-Power Audio Codec
-maxim,ds1050            5 Bit Programmable, Pulse-Width Modulator
-maxim,max1237           Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
-maxim,max6625           9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface
-mc,rv3029c2             Real Time Clock Module with I2C-Bus
-national,lm75           I2C TEMP SENSOR
-national,lm80           Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor
-national,lm92           ±0.33°C Accurate, 12-Bit + Sign Temperature Sensor and Thermal Window Comparator with Two-Wire Interface
-nxp,pca9556             Octal SMBus and I2C registered interface
-nxp,pca9557             8-bit I2C-bus and SMBus I/O port with reset
-nxp,pcf8563             Real-time clock/calendar
-ovti,ov5642             OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI and Embedded TrueFocus
-pericom,pt7c4338        Real-time Clock Module
-plx,pex8648             48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch
-ramtron,24c64           i2c serial eeprom  (24cxx)
-ricoh,rs5c372a          I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
-samsung,24ad0xd1        S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power)
-st-micro,24c256         i2c serial eeprom  (24cxx)
-stm,m41t00              Serial Access TIMEKEEPER
-stm,m41t62              Serial real-time clock (RTC) with alarm
-stm,m41t80              M41T80 - SERIAL ACCESS RTC WITH ALARMS
-taos,tsl2550            Ambient Light Sensor with SMBUS/Two Wire Serial Interface
-ti,tsc2003              I2C Touch-Screen Controller
-ti,tmp102               Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
-ti,tmp275               Digital Temperature Sensor
diff --git a/Documentation/devicetree/bindings/input/fsl-mma8450.txt b/Documentation/devicetree/bindings/input/fsl-mma8450.txt
index 0b96e5737d3..a00c94ccbde 100644
--- a/Documentation/devicetree/bindings/input/fsl-mma8450.txt
+++ b/Documentation/devicetree/bindings/input/fsl-mma8450.txt
@@ -2,7 +2,6 @@
 
 Required properties:
 - compatible : "fsl,mma8450".
-- reg: the I2C address of MMA8450
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/input/gpio-keys-polled.txt b/Documentation/devicetree/bindings/input/gpio-keys-polled.txt
deleted file mode 100644
index 313abefa37c..00000000000
--- a/Documentation/devicetree/bindings/input/gpio-keys-polled.txt
+++ /dev/null
@@ -1,38 +0,0 @@
-Device-Tree bindings for input/gpio_keys_polled.c keyboard driver
-
-Required properties:
-        - compatible = "gpio-keys-polled";
-        - poll-interval: Poll interval time in milliseconds
-
-Optional properties:
-        - autorepeat: Boolean, Enable auto repeat feature of Linux input
-          subsystem.
-
-Each button (key) is represented as a sub-node of "gpio-keys-polled":
-Subnode properties:
-
-        - gpios: OF device-tree gpio specification.
-        - label: Descriptive name of the key.
-        - linux,code: Keycode to emit.
-
-Optional subnode-properties:
-        - linux,input-type: Specify event type this button/key generates.
-          If not specified defaults to <1> == EV_KEY.
-        - debounce-interval: Debouncing interval time in milliseconds.
-          If not specified defaults to 5.
-        - gpio-key,wakeup: Boolean, button can wake-up the system.
-
-Example nodes:
-
-        gpio_keys_polled {
-                        compatible = "gpio-keys-polled";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        poll-interval = <100>;
-                        autorepeat;
-                        button@21 {
-                                label = "GPIO Key UP";
-                                linux,code = <103>;
-                                gpios = <&gpio1 0 1>;
-                        };
-                        ...
diff --git a/Documentation/devicetree/bindings/input/gpio-matrix-keypad.txt b/Documentation/devicetree/bindings/input/gpio-matrix-keypad.txt
deleted file mode 100644
index ead641c65e0..00000000000
--- a/Documentation/devicetree/bindings/input/gpio-matrix-keypad.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-* GPIO driven matrix keypad device tree bindings
-
-GPIO driven matrix keypad is used to interface a SoC with a matrix keypad.
-The matrix keypad supports multiple row and column lines, a key can be
-placed at each intersection of a unique row and a unique column. The matrix
-keypad can sense a key-press and key-release by means of GPIO lines and
-report the event using GPIO interrupts to the cpu.
-
-Required Properties:
-- compatible:           Should be "gpio-matrix-keypad"
-- row-gpios:            List of gpios used as row lines. The gpio specifier
-                        for this property depends on the gpio controller to
-                        which these row lines are connected.
-- col-gpios:            List of gpios used as column lines. The gpio specifier
-                        for this property depends on the gpio controller to
-                        which these column lines are connected.
-- linux,keymap:         The definition can be found at
-                        bindings/input/matrix-keymap.txt
-
-Optional Properties:
-- linux,no-autorepeat:  do no enable autorepeat feature.
-- linux,wakeup:         use any event on keypad as wakeup event.
-- debounce-delay-ms:    debounce interval in milliseconds
-- col-scan-delay-us:    delay, measured in microseconds, that is needed
-                        before we can scan keypad after activating column gpio
-
-Example:
-        matrix-keypad {
-                compatible = "gpio-matrix-keypad";
-                debounce-delay-ms = <5>;
-                col-scan-delay-us = <2>;
-
-                row-gpios = <&gpio2 25 0
-                             &gpio2 26 0
-                             &gpio2 27 0>;
-
-                col-gpios = <&gpio2 21 0
-                             &gpio2 22 0>;
-
-                linux,keymap = <0x0000008B
-                                0x0100009E
-                                0x02000069
-                                0x0001006A
-                                0x0101001C
-                                0x0201006C>;
-        };
diff --git a/Documentation/devicetree/bindings/input/lpc32xx-key.txt b/Documentation/devicetree/bindings/input/lpc32xx-key.txt
deleted file mode 100644
index 31afd5014c4..00000000000
--- a/Documentation/devicetree/bindings/input/lpc32xx-key.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-NXP LPC32xx Key Scan Interface
-
-Required Properties:
-- compatible: Should be "nxp,lpc3220-key"
-- reg: Physical base address of the controller and length of memory mapped
-  region.
-- interrupts: The interrupt number to the cpu.
-- keypad,num-rows: Number of rows and columns, e.g. 1: 1x1, 6: 6x6
-- keypad,num-columns: Must be equal to keypad,num-rows since LPC32xx only
-  supports square matrices
-- nxp,debounce-delay-ms: Debounce delay in ms
-- nxp,scan-delay-ms: Repeated scan period in ms
-- linux,keymap: the key-code to be reported when the key is pressed
-  and released, see also
-  Documentation/devicetree/bindings/input/matrix-keymap.txt
-
-Example:
-
-        key@40050000 {
-                compatible = "nxp,lpc3220-key";
-                reg = <0x40050000 0x1000>;
-                interrupts = <54 0>;
-                keypad,num-rows = <1>;
-                keypad,num-columns = <1>;
-                nxp,debounce-delay-ms = <3>;
-                nxp,scan-delay-ms = <34>;
-                linux,keymap = <0x00000002>;
-        };
diff --git a/Documentation/devicetree/bindings/input/matrix-keymap.txt b/Documentation/devicetree/bindings/input/matrix-keymap.txt
deleted file mode 100644
index 3cd8b98ccd2..00000000000
--- a/Documentation/devicetree/bindings/input/matrix-keymap.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-A simple common binding for matrix-connected key boards. Currently targeted at
-defining the keys in the scope of linux key codes since that is a stable and
-standardized interface at this time.
-
-Required properties:
-- linux,keymap: an array of packed 1-cell entries containing the equivalent
-  of row, column and linux key-code. The 32-bit big endian cell is packed
-  as:
-        row << 24 | column << 16 | key-code
-
-Optional properties:
-Some users of this binding might choose to specify secondary keymaps for
-cases where there is a modifier key such as a Fn key. Proposed names
-for said properties are "linux,fn-keymap" or with another descriptive
-word for the modifier other from "Fn".
-
-Example:
-        linux,keymap = < 0x00030012
-                         0x0102003a >;
diff --git a/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt b/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
deleted file mode 100644
index 72683be6de3..00000000000
--- a/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-* Tegra keyboard controller
-
-Required properties:
-- compatible: "nvidia,tegra20-kbc"
-
-Optional properties, in addition to those specified by the shared
-matrix-keyboard bindings:
-
-- linux,fn-keymap: a second keymap, same specification as the
-  matrix-keyboard-controller spec but to be used when the KEY_FN modifier
-  key is pressed.
-- nvidia,debounce-delay-ms: delay in milliseconds per row scan for debouncing
-- nvidia,repeat-delay-ms: delay in milliseconds before repeat starts
-- nvidia,ghost-filter: enable ghost filtering for this device
-- nvidia,wakeup-source: configure keyboard as a wakeup source for suspend/resume
-
-Example:
-
-keyboard: keyboard {
-        compatible = "nvidia,tegra20-kbc";
-        reg = <0x7000e200 0x100>;
-        nvidia,ghost-filter;
-};
diff --git a/Documentation/devicetree/bindings/input/omap-keypad.txt b/Documentation/devicetree/bindings/input/omap-keypad.txt
deleted file mode 100644
index f2fa5e10493..00000000000
--- a/Documentation/devicetree/bindings/input/omap-keypad.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-* TI's Keypad Controller device tree bindings
-
-TI's Keypad controller is used to interface a SoC with a matrix-type
-keypad device. The keypad controller supports multiple row and column lines.
-A key can be placed at each intersection of a unique row and a unique column.
-The keypad controller can sense a key-press and key-release and report the
-event using a interrupt to the cpu.
-
-Required SoC Specific Properties:
-- compatible: should be one of the following
-   - "ti,omap4-keypad": For controllers compatible with omap4 keypad
-      controller.
-
-Required Board Specific Properties, in addition to those specified by
-the shared matrix-keyboard bindings:
-- keypad,num-rows: Number of row lines connected to the keypad
-  controller.
-
-- keypad,num-columns: Number of column lines connected to the
-  keypad controller.
-
-Optional Properties specific to linux:
-- linux,keypad-no-autorepeat: do no enable autorepeat feature.
-
-Example:
-        keypad@4ae1c000{
-                compatible = "ti,omap4-keypad";
-                keypad,num-rows = <2>;
-                keypad,num-columns = <8>;
-                linux,keypad-no-autorepeat;
-        };
diff --git a/Documentation/devicetree/bindings/input/pwm-beeper.txt b/Documentation/devicetree/bindings/input/pwm-beeper.txt
deleted file mode 100644
index be332ae4f2d..00000000000
--- a/Documentation/devicetree/bindings/input/pwm-beeper.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-* PWM beeper device tree bindings
-
-Registers a PWM device as beeper.
-
-Required properties:
-- compatible: should be "pwm-beeper"
-- pwms: phandle to the physical PWM device
diff --git a/Documentation/devicetree/bindings/input/rotary-encoder.txt b/Documentation/devicetree/bindings/input/rotary-encoder.txt
deleted file mode 100644
index 331549593ed..00000000000
--- a/Documentation/devicetree/bindings/input/rotary-encoder.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-Rotary encoder DT bindings
-
-Required properties:
-- gpios: a spec for two GPIOs to be used
-
-Optional properties:
-- linux,axis: the input subsystem axis to map to this rotary encoder.
-  Defaults to 0 (ABS_X / REL_X)
-- rotary-encoder,steps: Number of steps in a full turnaround of the
-  encoder. Only relevant for absolute axis. Defaults to 24 which is a
-  typical value for such devices.
-- rotary-encoder,relative-axis: register a relative axis rather than an
-  absolute one. Relative axis will only generate +1/-1 events on the input
-  device, hence no steps need to be passed.
-- rotary-encoder,rollover: Automatic rollove when the rotary value becomes
-  greater than the specified steps or smaller than 0. For absolute axis only.
-- rotary-encoder,half-period: Makes the driver work on half-period mode.
-
-See Documentation/input/rotary-encoder.txt for more information.
-
-Example:
-
-                rotary@0 {
-                        compatible = "rotary-encoder";
-                        gpios = <&gpio 19 1>, <&gpio 20 0>; /* GPIO19 is inverted */
-                        linux,axis = <0>; /* REL_X */
-                        rotary-encoder,relative-axis;
-                };
-
-                rotary@1 {
-                        compatible = "rotary-encoder";
-                        gpios = <&gpio 21 0>, <&gpio 22 0>;
-                        linux,axis = <1>; /* ABS_Y */
-                        rotary-encoder,steps = <24>;
-                        rotary-encoder,rollover;
-                };
diff --git a/Documentation/devicetree/bindings/input/samsung-keypad.txt b/Documentation/devicetree/bindings/input/samsung-keypad.txt
deleted file mode 100644
index ce3e394c0e6..00000000000
--- a/Documentation/devicetree/bindings/input/samsung-keypad.txt
+++ /dev/null
@@ -1,88 +0,0 @@
-* Samsung's Keypad Controller device tree bindings
-
-Samsung's Keypad controller is used to interface a SoC with a matrix-type
-keypad device. The keypad controller supports multiple row and column lines.
-A key can be placed at each intersection of a unique row and a unique column.
-The keypad controller can sense a key-press and key-release and report the
-event using a interrupt to the cpu.
-
-Required SoC Specific Properties:
-- compatible: should be one of the following
-  - "samsung,s3c6410-keypad": For controllers compatible with s3c6410 keypad
-    controller.
-  - "samsung,s5pv210-keypad": For controllers compatible with s5pv210 keypad
-    controller.
-
-- reg: physical base address of the controller and length of memory mapped
-  region.
-
-- interrupts: The interrupt number to the cpu.
-
-Required Board Specific Properties:
-- samsung,keypad-num-rows: Number of row lines connected to the keypad
-  controller.
-
-- samsung,keypad-num-columns: Number of column lines connected to the
-  keypad controller.
-
-- row-gpios: List of gpios used as row lines. The gpio specifier for
-  this property depends on the gpio controller to which these row lines
-  are connected.
-
-- col-gpios: List of gpios used as column lines. The gpio specifier for
-  this property depends on the gpio controller to which these column
-  lines are connected.
-
-- Keys represented as child nodes: Each key connected to the keypad
-  controller is represented as a child node to the keypad controller
-  device node and should include the following properties.
-  - keypad,row: the row number to which the key is connected.
-  - keypad,column: the column number to which the key is connected.
-  - linux,code: the key-code to be reported when the key is pressed
-    and released.
-
-Optional Properties specific to linux:
-- linux,keypad-no-autorepeat: do no enable autorepeat feature.
-- linux,keypad-wakeup: use any event on keypad as wakeup event.
-
-
-Example:
-        keypad@100A0000 {
-                compatible = "samsung,s5pv210-keypad";
-                reg = <0x100A0000 0x100>;
-                interrupts = <173>;
-                samsung,keypad-num-rows = <2>;
-                samsung,keypad-num-columns = <8>;
-                linux,input-no-autorepeat;
-                linux,input-wakeup;
-
-                row-gpios = <&gpx2 0 3 3 0
-                             &gpx2 1 3 3 0>;
-
-                col-gpios = <&gpx1 0 3 0 0
-                             &gpx1 1 3 0 0
-                             &gpx1 2 3 0 0
-                             &gpx1 3 3 0 0
-                             &gpx1 4 3 0 0
-                             &gpx1 5 3 0 0
-                             &gpx1 6 3 0 0
-                             &gpx1 7 3 0 0>;
-
-                key_1 {
-                        keypad,row = <0>;
-                        keypad,column = <3>;
-                        linux,code = <2>;
-                };
-
-                key_2 {
-                        keypad,row = <0>;
-                        keypad,column = <4>;
-                        linux,code = <3>;
-                };
-
-                key_3 {
-                        keypad,row = <0>;
-                        keypad,column = <5>;
-                        linux,code = <4>;
-                };
-        };
diff --git a/Documentation/devicetree/bindings/input/spear-keyboard.txt b/Documentation/devicetree/bindings/input/spear-keyboard.txt
deleted file mode 100644
index 4a846d26da2..00000000000
--- a/Documentation/devicetree/bindings/input/spear-keyboard.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-* SPEAr keyboard controller
-
-Required properties:
-- compatible: "st,spear300-kbd"
-
-Optional properties, in addition to those specified by the shared
-matrix-keyboard bindings:
-- autorepeat: bool: enables key autorepeat
-- st,mode: keyboard mode: 0 - 9x9, 1 - 6x6, 2 - 2x2
-
-Example:
-
-kbd@fc400000 {
-        compatible = "st,spear300-kbd";
-        reg = <0xfc400000 0x100>;
-        linux,keymap = < 0x00030012
-                         0x0102003a >;
-        autorepeat;
-        st,mode = <0>;
-};
diff --git a/Documentation/devicetree/bindings/input/stmpe-keypad.txt b/Documentation/devicetree/bindings/input/stmpe-keypad.txt
deleted file mode 100644
index 1b97222e8a0..00000000000
--- a/Documentation/devicetree/bindings/input/stmpe-keypad.txt
+++ /dev/null
@@ -1,39 +0,0 @@
-* STMPE Keypad
-
-Required properties:
- - compatible               : "st,stmpe-keypad"
- - linux,keymap             : See ./matrix-keymap.txt
-
-Optional properties:
- - debounce-interval        : Debouncing interval time in milliseconds
- - st,scan-count            : Scanning cycles elapsed before key data is updated
- - st,no-autorepeat         : If specified device will not autorepeat
-
-Example:
-
-        stmpe_keypad {
-                compatible = "st,stmpe-keypad";
-
-                debounce-interval = <64>;
-                st,scan-count = <8>;
-                st,no-autorepeat;
-
-                linux,keymap = <0x205006b
-                                0x4010074
-                                0x3050072
-                                0x1030004
-                                0x502006a
-                                0x500000a
-                                0x5008b
-                                0x706001c
-                                0x405000b
-                                0x6070003
-                                0x3040067
-                                0x303006c
-                                0x60400e7
-                                0x602009e
-                                0x4020073
-                                0x5050002
-                                0x4030069
-                                0x3020008>;
-        };
diff --git a/Documentation/devicetree/bindings/input/tca8418_keypad.txt b/Documentation/devicetree/bindings/input/tca8418_keypad.txt
deleted file mode 100644
index 2a1538f0053..00000000000
--- a/Documentation/devicetree/bindings/input/tca8418_keypad.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-
-Required properties:
-- compatible: "ti,tca8418"
-- reg: the I2C address
-- interrupts: IRQ line number, should trigger on falling edge
-- keypad,num-rows: The number of rows
-- keypad,num-columns: The number of columns
-- linux,keymap: Keys definitions, see keypad-matrix.
diff --git a/Documentation/devicetree/bindings/input/touchscreen/bu21013.txt b/Documentation/devicetree/bindings/input/touchscreen/bu21013.txt
deleted file mode 100644
index ca5a2c86480..00000000000
--- a/Documentation/devicetree/bindings/input/touchscreen/bu21013.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-* Rohm BU21013 Touch Screen
-
-Required properties:
- - compatible              : "rohm,bu21013_tp"
- - reg                     :  I2C device address
-
-Optional properties:
- - touch-gpio              : GPIO pin registering a touch event
- - <supply_name>-supply    : Phandle to a regulator supply
- - rohm,touch-max-x        : Maximum outward permitted limit in the X axis
- - rohm,touch-max-y        : Maximum outward permitted limit in the Y axis
- - rohm,flip-x             : Flip touch coordinates on the X axis
- - rohm,flip-y             : Flip touch coordinates on the Y axis
-
-Example:
-
-        i2c@80110000 {
-                bu21013_tp@0x5c {
-                        compatible = "rohm,bu21013_tp";
-                        reg = <0x5c>;
-                        touch-gpio = <&gpio2 20 0x4>;
-                        avdd-supply = <&ab8500_ldo_aux1_reg>;
-
-                        rohm,touch-max-x = <384>;
-                        rohm,touch-max-y = <704>;
-                        rohm,flip-y;
-                };
-        };
diff --git a/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt b/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt
deleted file mode 100644
index df70318a617..00000000000
--- a/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-* EETI eGalax Multiple Touch Controller
-
-Required properties:
-- compatible: must be "eeti,egalax_ts"
-- reg: i2c slave address
-- interrupt-parent: the phandle for the interrupt controller
-- interrupts: touch controller interrupt
-- wakeup-gpios: the gpio pin to be used for waking up the controller
-  as well as uased as irq pin
-
-Example:
-
-        egalax_ts@04 {
-                compatible = "eeti,egalax_ts";
-                reg = <0x04>;
-                interrupt-parent = <&gpio1>;
-                interrupts = <9 2>;
-                wakeup-gpios = <&gpio1 9 0>;
-        };
diff --git a/Documentation/devicetree/bindings/input/touchscreen/lpc32xx-tsc.txt b/Documentation/devicetree/bindings/input/touchscreen/lpc32xx-tsc.txt
deleted file mode 100644
index 41cbf4b7a67..00000000000
--- a/Documentation/devicetree/bindings/input/touchscreen/lpc32xx-tsc.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-* NXP LPC32xx SoC Touchscreen Controller (TSC)
-
-Required properties:
-- compatible: must be "nxp,lpc3220-tsc"
-- reg: physical base address of the controller and length of memory mapped
-  region.
-- interrupts: The TSC/ADC interrupt
-
-Example:
-
-        tsc@40048000 {
-                compatible = "nxp,lpc3220-tsc";
-                reg = <0x40048000 0x1000>;
-                interrupt-parent = <&mic>;
-                interrupts = <39 0>;
-        };
diff --git a/Documentation/devicetree/bindings/input/touchscreen/mms114.txt b/Documentation/devicetree/bindings/input/touchscreen/mms114.txt
deleted file mode 100644
index 89d4c56c567..00000000000
--- a/Documentation/devicetree/bindings/input/touchscreen/mms114.txt
+++ /dev/null
@@ -1,34 +0,0 @@
-* MELFAS MMS114 touchscreen controller
-
-Required properties:
-- compatible: must be "melfas,mms114"
-- reg: I2C address of the chip
-- interrupts: interrupt to which the chip is connected
-- x-size: horizontal resolution of touchscreen
-- y-size: vertical resolution of touchscreen
-
-Optional properties:
-- contact-threshold:
-- moving-threshold:
-- x-invert: invert X axis
-- y-invert: invert Y axis
-
-Example:
-
-        i2c@00000000 {
-                /* ... */
-
-                touchscreen@48 {
-                        compatible = "melfas,mms114";
-                        reg = <0x48>;
-                        interrupts = <39 0>;
-                        x-size = <720>;
-                        y-size = <1280>;
-                        contact-threshold = <10>;
-                        moving-threshold = <10>;
-                        x-invert;
-                        y-invert;
-                };
-
-                /* ... */
-        };
diff --git a/Documentation/devicetree/bindings/input/touchscreen/stmpe.txt b/Documentation/devicetree/bindings/input/touchscreen/stmpe.txt
deleted file mode 100644
index 127baa31a77..00000000000
--- a/Documentation/devicetree/bindings/input/touchscreen/stmpe.txt
+++ /dev/null
@@ -1,43 +0,0 @@
-STMPE Touchscreen
-----------------
-
-Required properties:
- - compatible: "st,stmpe-ts"
-
-Optional properties:
-- st,sample-time: ADC converstion time in number of clock.  (0 -> 36 clocks, 1 ->
-  44 clocks, 2 -> 56 clocks, 3 -> 64 clocks, 4 -> 80 clocks, 5 -> 96 clocks, 6
-  -> 144 clocks), recommended is 4.
-- st,mod-12b: ADC Bit mode (0 -> 10bit ADC, 1 -> 12bit ADC)
-- st,ref-sel: ADC reference source (0 -> internal reference, 1 -> external
-  reference)
-- st,adc-freq: ADC Clock speed (0 -> 1.625 MHz, 1 -> 3.25 MHz, 2 || 3 -> 6.5 MHz)
-- st,ave-ctrl: Sample average control (0 -> 1 sample, 1 -> 2 samples, 2 -> 4
-  samples, 3 -> 8 samples)
-- st,touch-det-delay: Touch detect interrupt delay (0 -> 10 us, 1 -> 50 us, 2 ->
-  100 us, 3 -> 500 us, 4-> 1 ms, 5 -> 5 ms, 6 -> 10 ms, 7 -> 50 ms) recommended
-  is 3
-- st,settling: Panel driver settling time (0 -> 10 us, 1 -> 100 us, 2 -> 500 us, 3
-  -> 1 ms, 4 -> 5 ms, 5 -> 10 ms, 6 for 50 ms, 7 -> 100 ms) recommended is 2
-- st,fraction-z: Length of the fractional part in z (fraction-z ([0..7]) = Count of
-  the fractional part) recommended is 7
-- st,i-drive: current limit value of the touchscreen drivers (0 -> 20 mA typical 35
-  mA max, 1 -> 50 mA typical 80 mA max)
-
-Node name must be stmpe_touchscreen and should be child node of stmpe node to
-which it belongs.
-
-Example:
-
-        stmpe_touchscreen {
-                compatible = "st,stmpe-ts";
-                st,sample-time = <4>;
-                st,mod-12b = <1>;
-                st,ref-sel = <0>;
-                st,adc-freq = <1>;
-                st,ave-ctrl = <1>;
-                st,touch-det-delay = <2>;
-                st,settling = <2>;
-                st,fraction-z = <7>;
-                st,i-drive = <1>;
-        };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt
deleted file mode 100644
index 7f9fb85f545..00000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt
+++ /dev/null
@@ -1,104 +0,0 @@
-Allwinner Sunxi Interrupt Controller
-
-Required properties:
-
-- compatible : should be "allwinner,sunxi-ic"
-- reg : Specifies base physical address and size of the registers.
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an
-  interrupt source. The value shall be 1.
-
-The interrupt sources are as follows:
-
-0: ENMI
-1: UART0
-2: UART1
-3: UART2
-4: UART3
-5: IR0
-6: IR1
-7: I2C0
-8: I2C1
-9: I2C2
-10: SPI0
-11: SPI1
-12: SPI2
-13: SPDIF
-14: AC97
-15: TS
-16: I2S
-17: UART4
-18: UART5
-19: UART6
-20: UART7
-21: KEYPAD
-22: TIMER0
-23: TIMER1
-24: TIMER2
-25: TIMER3
-26: CAN
-27: DMA
-28: PIO
-29: TOUCH_PANEL
-30: AUDIO_CODEC
-31: LRADC
-32: SDMC0
-33: SDMC1
-34: SDMC2
-35: SDMC3
-36: MEMSTICK
-37: NAND
-38: USB0
-39: USB1
-40: USB2
-41: SCR
-42: CSI0
-43: CSI1
-44: LCDCTRL0
-45: LCDCTRL1
-46: MP
-47: DEFEBE0
-48: DEFEBE1
-49: PMU
-50: SPI3
-51: TZASC
-52: PATA
-53: VE
-54: SS
-55: EMAC
-56: SATA
-57: GPS
-58: HDMI
-59: TVE
-60: ACE
-61: TVD
-62: PS2_0
-63: PS2_1
-64: USB3
-65: USB4
-66: PLE_PFM
-67: TIMER4
-68: TIMER5
-69: GPU_GP
-70: GPU_GPMMU
-71: GPU_PP0
-72: GPU_PPMMU0
-73: GPU_PMU
-74: GPU_RSV0
-75: GPU_RSV1
-76: GPU_RSV2
-77: GPU_RSV3
-78: GPU_RSV4
-79: GPU_RSV5
-80: GPU_RSV6
-82: SYNC_TIMER0
-83: SYNC_TIMER1
-
-Example:
-
-intc: interrupt-controller {
-        compatible = "allwinner,sunxi-ic";
-        reg = <0x01c20400 0x400>;
-        interrupt-controller;
-        #interrupt-cells = <2>;
-};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
deleted file mode 100644
index 7da578d7212..00000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
+++ /dev/null
@@ -1,110 +0,0 @@
-BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
-
-The BCM2835 contains a custom top-level interrupt controller, which supports
-72 interrupt sources using a 2-level register scheme. The interrupt
-controller, or the HW block containing it, is referred to occasionally
-as "armctrl" in the SoC documentation, hence naming of this binding.
-
-Required properties:
-
-- compatible : should be "brcm,bcm2835-armctrl-ic"
-- reg : Specifies base physical address and size of the registers.
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an
-  interrupt source. The value shall be 2.
-
-  The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic
-  pending" register, or 1/2 respectively for interrupts in the "IRQ pending
-  1/2" register.
-
-  The 2nd cell contains the interrupt number within the bank. Valid values
-  are 0..7 for bank 0, and 0..31 for bank 1.
-
-The interrupt sources are as follows:
-
-Bank 0:
-0: ARM_TIMER
-1: ARM_MAILBOX
-2: ARM_DOORBELL_0
-3: ARM_DOORBELL_1
-4: VPU0_HALTED
-5: VPU1_HALTED
-6: ILLEGAL_TYPE0
-7: ILLEGAL_TYPE1
-
-Bank 1:
-0: TIMER0
-1: TIMER1
-2: TIMER2
-3: TIMER3
-4: CODEC0
-5: CODEC1
-6: CODEC2
-7: VC_JPEG
-8: ISP
-9: VC_USB
-10: VC_3D
-11: TRANSPOSER
-12: MULTICORESYNC0
-13: MULTICORESYNC1
-14: MULTICORESYNC2
-15: MULTICORESYNC3
-16: DMA0
-17: DMA1
-18: VC_DMA2
-19: VC_DMA3
-20: DMA4
-21: DMA5
-22: DMA6
-23: DMA7
-24: DMA8
-25: DMA9
-26: DMA10
-27: DMA11
-28: DMA12
-29: AUX
-30: ARM
-31: VPUDMA
-
-Bank 2:
-0: HOSTPORT
-1: VIDEOSCALER
-2: CCP2TX
-3: SDC
-4: DSI0
-5: AVE
-6: CAM0
-7: CAM1
-8: HDMI0
-9: HDMI1
-10: PIXELVALVE1
-11: I2CSPISLV
-12: DSI1
-13: PWA0
-14: PWA1
-15: CPR
-16: SMI
-17: GPIO0
-18: GPIO1
-19: GPIO2
-20: GPIO3
-21: VC_I2C
-22: VC_SPI
-23: VC_I2SPCM
-24: VC_SDIO
-25: VC_UART
-26: SLIMBUS
-27: VEC
-28: CPG
-29: RNG
-30: VC_ARASANSDIO
-31: AVSPMON
-
-Example:
-
-intc: interrupt-controller {
-        compatible = "brcm,bcm2835-armctrl-ic";
-        reg = <0x7e00b200 0x200>;
-        interrupt-controller;
-        #interrupt-cells = <2>;
-};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt b/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
deleted file mode 100644
index 72a06c0ab1d..00000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+++ /dev/null
@@ -1,95 +0,0 @@
-Specifying interrupt information for devices
-============================================
-
-1) Interrupt client nodes
--------------------------
-
-Nodes that describe devices which generate interrupts must contain an
-"interrupts" property. This property must contain a list of interrupt
-specifiers, one per output interrupt. The format of the interrupt specifier is
-determined by the interrupt controller to which the interrupts are routed; see
-section 2 below for details.
-
-The "interrupt-parent" property is used to specify the controller to which
-interrupts are routed and contains a single phandle referring to the interrupt
-controller node. This property is inherited, so it may be specified in an
-interrupt client node or in any of its parent nodes.
-
-2) Interrupt controller nodes
------------------------------
-
-A device is marked as an interrupt controller with the "interrupt-controller"
-property. This is a empty, boolean property. An additional "#interrupt-cells"
-property defines the number of cells needed to specify a single interrupt.
-
-It is the responsibility of the interrupt controller's binding to define the
-length and format of the interrupt specifier. The following two variants are
-commonly used:
-
-  a) one cell
-  -----------
-  The #interrupt-cells property is set to 1 and the single cell defines the
-  index of the interrupt within the controller.
-
-  Example:
-
-        vic: intc@10140000 {
-                compatible = "arm,versatile-vic";
-                interrupt-controller;
-                #interrupt-cells = <1>;
-                reg = <0x10140000 0x1000>;
-        };
-
-        sic: intc@10003000 {
-                compatible = "arm,versatile-sic";
-                interrupt-controller;
-                #interrupt-cells = <1>;
-                reg = <0x10003000 0x1000>;
-                interrupt-parent = <&vic>;
-                interrupts = <31>; /* Cascaded to vic */
-        };
-
-  b) two cells
-  ------------
-  The #interrupt-cells property is set to 2 and the first cell defines the
-  index of the interrupt within the controller, while the second cell is used
-  to specify any of the following flags:
-    - bits[3:0] trigger type and level flags
-        1 = low-to-high edge triggered
-        2 = high-to-low edge triggered
-        4 = active high level-sensitive
-        8 = active low level-sensitive
-
-  Example:
-
-        i2c@7000c000 {
-                gpioext: gpio-adnp@41 {
-                        compatible = "ad,gpio-adnp";
-                        reg = <0x41>;
-
-                        interrupt-parent = <&gpio>;
-                        interrupts = <160 1>;
-
-                        gpio-controller;
-                        #gpio-cells = <1>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-
-                        nr-gpios = <64>;
-                };
-
-                sx8634@2b {
-                        compatible = "smtc,sx8634";
-                        reg = <0x2b>;
-
-                        interrupt-parent = <&gpioext>;
-                        interrupts = <3 0x8>;
-
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        threshold = <0x40>;
-                        sensitivity = <7>;
-                };
-        };
diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt b/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt
deleted file mode 100644
index 099d9362ebc..00000000000
--- a/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-NVIDIA Tegra 20 GART
-
-Required properties:
-- compatible: "nvidia,tegra20-gart"
-- reg: Two pairs of cells specifying the physical address and size of
-  the memory controller registers and the GART aperture respectively.
-
-Example:
-
-        gart {
-                compatible = "nvidia,tegra20-gart";
-                reg = <0x7000f024 0x00000018    /* controller registers */
-                       0x58000000 0x02000000>;  /* GART aperture */
-        };
diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt b/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt
deleted file mode 100644
index 89fb5434b73..00000000000
--- a/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-NVIDIA Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit)
-
-Required properties:
-- compatible : "nvidia,tegra30-smmu"
-- reg : Should contain 3 register banks(address and length) for each
-  of the SMMU register blocks.
-- interrupts : Should contain MC General interrupt.
-- nvidia,#asids : # of ASIDs
-- dma-window : IOVA start address and length.
-- nvidia,ahb : phandle to the ahb bus connected to SMMU.
-
-Example:
-        smmu {
-                compatible = "nvidia,tegra30-smmu";
-                reg = <0x7000f010 0x02c
-                       0x7000f1f0 0x010
-                       0x7000f228 0x05c>;
-                nvidia,#asids = <4>;            /* # of ASIDs */
-                dma-window = <0 0x40000000>;    /* IOVA start & length */
-                nvidia,ahb = <&ahb>;
-        };
diff --git a/Documentation/devicetree/bindings/leds/common.txt b/Documentation/devicetree/bindings/leds/common.txt
deleted file mode 100644
index 2d88816dd55..00000000000
--- a/Documentation/devicetree/bindings/leds/common.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-Common leds properties.
-
-Optional properties for child nodes:
-- label : The label for this LED.  If omitted, the label is
-  taken from the node name (excluding the unit address).
-
-- linux,default-trigger :  This parameter, if present, is a
-    string defining the trigger assigned to the LED.  Current triggers are:
-     "backlight" - LED will act as a back-light, controlled by the framebuffer
-                   system
-     "default-on" - LED will turn on (but for leds-gpio see "default-state"
-                    property in Documentation/devicetree/bindings/gpio/led.txt)
-     "heartbeat" - LED "double" flashes at a load average based rate
-     "ide-disk" - LED indicates disk activity
-     "timer" - LED flashes at a fixed, configurable rate
-
-Examples:
-
-system-status {
-        label = "Status";
-        linux,default-trigger = "heartbeat";
-        ...
-};
diff --git a/Documentation/devicetree/bindings/leds/leds-gpio.txt b/Documentation/devicetree/bindings/leds/leds-gpio.txt
deleted file mode 100644
index df1b3080f6b..00000000000
--- a/Documentation/devicetree/bindings/leds/leds-gpio.txt
+++ /dev/null
@@ -1,52 +0,0 @@
-LEDs connected to GPIO lines
-
-Required properties:
-- compatible : should be "gpio-leds".
-
-Each LED is represented as a sub-node of the gpio-leds device.  Each
-node's name represents the name of the corresponding LED.
-
-LED sub-node properties:
-- gpios :  Should specify the LED's GPIO, see "gpios property" in
-  Documentation/devicetree/bindings/gpio/gpio.txt.  Active low LEDs should be
-  indicated using flags in the GPIO specifier.
-- label :  (optional)
-  see Documentation/devicetree/bindings/leds/common.txt
-- linux,default-trigger :  (optional)
-  see Documentation/devicetree/bindings/leds/common.txt
-- default-state:  (optional) The initial state of the LED.  Valid
-  values are "on", "off", and "keep".  If the LED is already on or off
-  and the default-state property is set the to same value, then no
-  glitch should be produced where the LED momentarily turns off (or
-  on).  The "keep" setting will keep the LED at whatever its current
-  state is, without producing a glitch.  The default is off if this
-  property is not present.
-
-Examples:
-
-leds {
-        compatible = "gpio-leds";
-        hdd {
-                label = "IDE Activity";
-                gpios = <&mcu_pio 0 1>; /* Active low */
-                linux,default-trigger = "ide-disk";
-        };
-
-        fault {
-                gpios = <&mcu_pio 1 0>;
-                /* Keep LED on if BIOS detected hardware fault */
-                default-state = "keep";
-        };
-};
-
-run-control {
-        compatible = "gpio-leds";
-        red {
-                gpios = <&mpc8572 6 0>;
-                default-state = "off";
-        };
-        green {
-                gpios = <&mpc8572 7 0>;
-                default-state = "on";
-        };
-};
diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt b/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt
deleted file mode 100644
index 9ceb19e0c7f..00000000000
--- a/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt
+++ /dev/null
@@ -1,52 +0,0 @@
-* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin
-
-Required properties:
-- compatible : Should be "jedec,lpddr2-timings"
-- min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
-- max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>
-
-Optional properties:
-
-The following properties represent AC timing parameters from the memory
-data-sheet of the device for a given speed-bin. All these properties are
-of type <u32> and the default unit is ps (pico seconds). Parameters with
-a different unit have a suffix indicating the unit such as 'tRAS-max-ns'
-- tRCD
-- tWR
-- tRAS-min
-- tRRD
-- tWTR
-- tXP
-- tRTP
-- tDQSCK-max
-- tFAW
-- tZQCS
-- tZQinit
-- tRPab
-- tZQCL
-- tCKESR
-- tRAS-max-ns
-- tDQSCK-max-derated
-
-Example:
-
-timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
-        compatible      = "jedec,lpddr2-timings";
-        min-freq        = <10000000>;
-        max-freq        = <400000000>;
-        tRPab           = <21000>;
-        tRCD            = <18000>;
-        tWR             = <15000>;
-        tRAS-min        = <42000>;
-        tRRD            = <10000>;
-        tWTR            = <7500>;
-        tXP             = <7500>;
-        tRTP            = <7500>;
-        tCKESR          = <15000>;
-        tDQSCK-max      = <5500>;
-        tFAW            = <50000>;
-        tZQCS           = <90000>;
-        tZQCL           = <360000>;
-        tZQinit         = <1000000>;
-        tRAS-max-ns     = <70000>;
-};
diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt b/Documentation/devicetree/bindings/lpddr2/lpddr2.txt
deleted file mode 100644
index 58354a075e1..00000000000
--- a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt
+++ /dev/null
@@ -1,102 +0,0 @@
-* LPDDR2 SDRAM memories compliant to JEDEC JESD209-2
-
-Required properties:
-- compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2",
-  "jedec,lpddr2-s4"
-
-  "ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type
-
-  "ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type
-
-  "ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type
-
-- density  : <u32> representing density in Mb (Mega bits)
-
-- io-width : <u32> representing bus width. Possible values are 8, 16, and 32
-
-Optional properties:
-
-The following optional properties represent the minimum value of some AC
-timing parameters of the DDR device in terms of number of clock cycles.
-These values shall be obtained from the device data-sheet.
-- tRRD-min-tck
-- tWTR-min-tck
-- tXP-min-tck
-- tRTP-min-tck
-- tCKE-min-tck
-- tRPab-min-tck
-- tRCD-min-tck
-- tWR-min-tck
-- tRASmin-min-tck
-- tCKESR-min-tck
-- tFAW-min-tck
-
-Child nodes:
-- The lpddr2 node may have one or more child nodes of type "lpddr2-timings".
-  "lpddr2-timings" provides AC timing parameters of the device for
-  a given speed-bin. The user may provide the timings for as many
-  speed-bins as is required. Please see Documentation/devicetree/
-  bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings"
-
-Example:
-
-elpida_ECB240ABACN : lpddr2 {
-        compatible      = "Elpida,ECB240ABACN","jedec,lpddr2-s4";
-        density         = <2048>;
-        io-width        = <32>;
-
-        tRPab-min-tck   = <3>;
-        tRCD-min-tck    = <3>;
-        tWR-min-tck     = <3>;
-        tRASmin-min-tck = <3>;
-        tRRD-min-tck    = <2>;
-        tWTR-min-tck    = <2>;
-        tXP-min-tck     = <2>;
-        tRTP-min-tck    = <2>;
-        tCKE-min-tck    = <3>;
-        tCKESR-min-tck  = <3>;
-        tFAW-min-tck    = <8>;
-
-        timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
-                compatible      = "jedec,lpddr2-timings";
-                min-freq        = <10000000>;
-                max-freq        = <400000000>;
-                tRPab           = <21000>;
-                tRCD            = <18000>;
-                tWR             = <15000>;
-                tRAS-min        = <42000>;
-                tRRD            = <10000>;
-                tWTR            = <7500>;
-                tXP             = <7500>;
-                tRTP            = <7500>;
-                tCKESR          = <15000>;
-                tDQSCK-max      = <5500>;
-                tFAW            = <50000>;
-                tZQCS           = <90000>;
-                tZQCL           = <360000>;
-                tZQinit         = <1000000>;
-                tRAS-max-ns     = <70000>;
-        };
-
-        timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
-                compatible      = "jedec,lpddr2-timings";
-                min-freq        = <10000000>;
-                max-freq        = <200000000>;
-                tRPab           = <21000>;
-                tRCD            = <18000>;
-                tWR             = <15000>;
-                tRAS-min        = <42000>;
-                tRRD            = <10000>;
-                tWTR            = <10000>;
-                tXP             = <7500>;
-                tRTP            = <7500>;
-                tCKESR          = <15000>;
-                tDQSCK-max      = <5500>;
-                tFAW            = <50000>;
-                tZQCS           = <90000>;
-                tZQCL           = <360000>;
-                tZQinit         = <1000000>;
-                tRAS-max-ns     = <70000>;
-        };
-
-}
diff --git a/Documentation/devicetree/bindings/media/exynos5-gsc.txt b/Documentation/devicetree/bindings/media/exynos5-gsc.txt
deleted file mode 100644
index 0604d42f38d..00000000000
--- a/Documentation/devicetree/bindings/media/exynos5-gsc.txt
+++ /dev/null
@@ -1,30 +0,0 @@
-* Samsung Exynos5 G-Scaler device
-
-G-Scaler is used for scaling and color space conversion on EXYNOS5 SoCs.
-
-Required properties:
-- compatible: should be "samsung,exynos5-gsc"
-- reg: should contain G-Scaler physical address location and length.
-- interrupts: should contain G-Scaler interrupt number
-
-Example:
-
-gsc_0:  gsc@0x13e00000 {
-        compatible = "samsung,exynos5-gsc";
-        reg = <0x13e00000 0x1000>;
-        interrupts = <0 85 0>;
-};
-
-Aliases:
-Each G-Scaler node should have a numbered alias in the aliases node,
-in the form of gscN, N = 0...3. G-Scaler driver uses these aliases
-to retrieve the device IDs using "of_alias_get_id()" call.
-
-Example:
-
-aliases {
-        gsc0 =&gsc_0;
-        gsc1 =&gsc_1;
-        gsc2 =&gsc_2;
-        gsc3 =&gsc_3;
-};
diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt
deleted file mode 100644
index 67ec3d4ccc7..00000000000
--- a/Documentation/devicetree/bindings/media/s5p-mfc.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-* Samsung Multi Format Codec (MFC)
-
-Multi Format Codec (MFC) is the IP present in Samsung SoCs which
-supports high resolution decoding and encoding functionalities.
-The MFC device driver is a v4l2 driver which can encode/decode
-video raw/elementary streams and has support for all popular
-video codecs.
-
-Required properties:
-  - compatible : value should be either one among the following
-        (a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs
-        (b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs
-
-  - reg : Physical base address of the IP registers and length of memory
-          mapped region.
-
-  - interrupts : MFC interrupt number to the CPU.
-
-  - samsung,mfc-r : Base address of the first memory bank used by MFC
-                    for DMA contiguous memory allocation and its size.
-
-  - samsung,mfc-l : Base address of the second memory bank used by MFC
-                    for DMA contiguous memory allocation and its size.
diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
deleted file mode 100644
index 938f8e1ba20..00000000000
--- a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
+++ /dev/null
@@ -1,55 +0,0 @@
-* EMIF family of TI SDRAM controllers
-
-EMIF - External Memory Interface - is an SDRAM controller used in
-TI SoCs. EMIF supports, based on the IP revision, one or more of
-DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
-of the EMIF IP and memory parts attached to it.
-
-Required properties:
-- compatible    : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
-  is the IP revision of the specific EMIF instance.
-
-- phy-type      : <u32> indicating the DDR phy type. Following are the
-  allowed values
-  <1>   : Attila PHY
-  <2>   : Intelli PHY
-
-- device-handle : phandle to a "lpddr2" node representing the memory part
-
-- ti,hwmods     : For TI hwmods processing and omap device creation
-  the value shall be "emif<n>" where <n> is the number of the EMIF
-  instance with base 1.
-
-Optional properties:
-- cs1-used              : Have this property if CS1 of this EMIF
-  instance has a memory part attached to it. If there is a memory
-  part attached to CS1, it should be the same type as the one on CS0,
-  so there is no need to give the details of this memory part.
-
-- cal-resistor-per-cs   : Have this property if the board has one
-  calibration resistor per chip-select.
-
-- hw-caps-read-idle-ctrl: Have this property if the controller
-  supports read idle window programming
-
-- hw-caps-dll-calib-ctrl: Have this property if the controller
-  supports dll calibration control
-
-- hw-caps-ll-interface  : Have this property if the controller
-  has a low latency interface and corresponding interrupt events
-
-- hw-caps-temp-alert    : Have this property if the controller
-  has capability for generating SDRAM temperature alerts
-
-Example:
-
-emif1: emif@0x4c000000 {
-        compatible      = "ti,emif-4d";
-        ti,hwmods       = "emif2";
-        phy-type        = <1>;
-        device-handle   = <&elpida_ECB240ABACN>;
-        cs1-used;
-        hw-caps-read-idle-ctrl;
-        hw-caps-ll-interface;
-        hw-caps-temp-alert;
-};
diff --git a/Documentation/devicetree/bindings/mfd/88pm860x.txt b/Documentation/devicetree/bindings/mfd/88pm860x.txt
deleted file mode 100644
index 63f3ee33759..00000000000
--- a/Documentation/devicetree/bindings/mfd/88pm860x.txt
+++ /dev/null
@@ -1,85 +0,0 @@
-* Marvell 88PM860x Power Management IC
-
-Required parent device properties:
-- compatible : "marvell,88pm860x"
-- reg : the I2C slave address for the 88pm860x chip
-- interrupts : IRQ line for the 88pm860x chip
-- interrupt-controller: describes the 88pm860x as an interrupt controller (has its own domain)
-- #interrupt-cells : should be 1.
-                - The cell is the 88pm860x local IRQ number
-
-Optional parent device properties:
-- marvell,88pm860x-irq-read-clr: inicates whether interrupt status is cleared by read
-- marvell,88pm860x-slave-addr: 88pm860x are two chips solution. <reg> stores the I2C address
-                                of one chip, and this property stores the I2C address of
-                                another chip.
-
-88pm860x consists of a large and varied group of sub-devices:
-
-Device                   Supply Names    Description
-------                   ------------    -----------
-88pm860x-onkey          :               : On key
-88pm860x-rtc            :               : RTC
-88pm8607                :               : Regulators
-88pm860x-backlight      :               : Backlight
-88pm860x-led            :               : Led
-88pm860x-touch          :               : Touchscreen
-
-Example:
-
-        pmic: 88pm860x@34 {
-                compatible = "marvell,88pm860x";
-                reg = <0x34>;
-                interrupts = <4>;
-                interrupt-parent = <&intc>;
-                interrupt-controller;
-                #interrupt-cells = <1>;
-
-                marvell,88pm860x-irq-read-clr;
-                marvell,88pm860x-slave-addr = <0x11>;
-
-                regulators {
-                        BUCK1 {
-                                regulator-min-microvolt = <1000000>;
-                                regulator-max-microvolt = <1500000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-                        LDO1 {
-                                regulator-min-microvolt = <1200000>;
-                                regulator-max-microvolt = <2800000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-                };
-                rtc {
-                        marvell,88pm860x-vrtc = <1>;
-                };
-                touch {
-                        marvell,88pm860x-gpadc-prebias = <1>;
-                        marvell,88pm860x-gpadc-slot-cycle = <1>;
-                        marvell,88pm860x-tsi-prebias = <6>;
-                        marvell,88pm860x-pen-prebias = <16>;
-                        marvell,88pm860x-pen-prechg = <2>;
-                        marvell,88pm860x-resistor-X = <300>;
-                };
-                backlights {
-                        backlight-0 {
-                                marvell,88pm860x-iset = <4>;
-                                marvell,88pm860x-pwm = <3>;
-                        };
-                        backlight-2 {
-                        };
-                };
-                leds {
-                        led0-red {
-                                marvell,88pm860x-iset = <12>;
-                        };
-                        led0-green {
-                                marvell,88pm860x-iset = <12>;
-                        };
-                        led0-blue {
-                                marvell,88pm860x-iset = <12>;
-                        };
-                };
-        };
diff --git a/Documentation/devicetree/bindings/mfd/ab8500.txt b/Documentation/devicetree/bindings/mfd/ab8500.txt
deleted file mode 100644
index 13b707b7355..00000000000
--- a/Documentation/devicetree/bindings/mfd/ab8500.txt
+++ /dev/null
@@ -1,163 +0,0 @@
-* AB8500 Multi-Functional Device (MFD)
-
-Required parent device properties:
-- compatible             : contains "stericsson,ab8500";
-- interrupts             : contains the IRQ line for the AB8500
-- interrupt-controller   : describes the AB8500 as an Interrupt Controller (has its own domain)
-- #interrupt-cells       : should be 2, for 2-cell format
-                            - The first cell is the AB8500 local IRQ number
-                            - The second cell is used to specify optional parameters
-                              - bits[3:0] trigger type and level flags:
-                                  1 = low-to-high edge triggered
-                                  2 = high-to-low edge triggered
-                                  4 = active high level-sensitive
-                                  8 = active low level-sensitive
-
-Optional parent device properties:
-- reg                    : contains the PRCMU mailbox address for the AB8500 i2c port
-
-The AB8500 consists of a large and varied group of sub-devices:
-
-Device                     IRQ Names              Supply Names   Description
-------                     ---------              ------------   -----------
-ab8500-bm                :                      :              : Battery Manager
-ab8500-btemp             :                      :              : Battery Temperature
-ab8500-charger           :                      :              : Battery Charger
-ab8500-codec             :                      :              : Audio Codec
-ab8500-fg                :                      : vddadc       : Fuel Gauge
-                         : NCONV_ACCU           :              : Accumulate N Sample Conversion
-                         : BATT_OVV             :              : Battery Over Voltage
-                         : LOW_BAT_F            :              : LOW threshold battery voltage
-                         : CC_INT_CALIB         :              : Coulomb Counter Internal Calibration
-                         : CCEOC                :              : Coulomb Counter End of Conversion
-ab8500-btemp             :                      : vtvout       : Battery Temperature
-                         : BAT_CTRL_INDB        :              : Battery Removal Indicator
-                         : BTEMP_LOW            :              : Btemp < BtempLow, if battery temperature is lower than -10°C
-                         : BTEMP_LOW_MEDIUM     :              : BtempLow < Btemp < BtempMedium,if battery temperature is between -10 and 0°C
-                         : BTEMP_MEDIUM_HIGH    :              : BtempMedium < Btemp < BtempHigh,if battery temperature is between 0°C and“MaxTemp
-                         : BTEMP_HIGH           :              : Btemp > BtempHigh, if battery temperature is higher than “MaxTemp
-ab8500-charger           :                      : vddadc       : Charger interface
-                         : MAIN_CH_UNPLUG_DET   :              : main charger unplug detection management (not in 8505)
-                         : MAIN_CHARGE_PLUG_DET :              : main charger plug detection management (not in 8505)
-                         : MAIN_EXT_CH_NOT_OK   :              : main charger not OK
-                         : MAIN_CH_TH_PROT_R    :              : Die temp is above main charger
-                         : MAIN_CH_TH_PROT_F    :              : Die temp is below main charger
-                         : VBUS_DET_F           :              : VBUS falling detected
-                         : VBUS_DET_R           :              : VBUS rising detected
-                         : USB_LINK_STATUS      :              : USB link status has changed
-                         : USB_CH_TH_PROT_R     :              : Die temp is above usb charger
-                         : USB_CH_TH_PROT_F     :              : Die temp is below usb charger
-                         : USB_CHARGER_NOT_OKR  :              : allowed USB charger not ok detection
-                         : VBUS_OVV             :              : Overvoltage on Vbus ball detected (USB charge is stopped)
-                         : CH_WD_EXP            :              : Charger watchdog detected
-ab8500-gpadc             : HW_CONV_END          : vddadc       : Analogue to Digital Converter
-                           SW_CONV_END          :              :
-ab8500-gpio              :                      :              : GPIO Controller
-ab8500-ponkey            : ONKEY_DBF            :              : Power-on Key
-                           ONKEY_DBR            :              :
-ab8500-pwm               :                      :              : Pulse Width Modulator
-ab8500-regulator         :                      :              : Regulators
-ab8500-rtc               : 60S                  :              : Real Time Clock
-                         : ALARM                :              :
-ab8500-sysctrl           :                      :              : System Control
-ab8500-usb               : ID_WAKEUP_R          : vddulpivio18 : Universal Serial Bus
-                         : ID_WAKEUP_F          : v-ape        :
-                         : VBUS_DET_F           : musb_1v8     :
-                         : VBUS_DET_R           :              :
-                         : USB_LINK_STATUS      :              :
-                         : USB_ADP_PROBE_PLUG   :              :
-                         : USB_ADP_PROBE_UNPLUG :              :
-
-Required child device properties:
-- compatible             : "stericsson,ab8500-[bm|btemp|charger|fg|gpadc|gpio|ponkey|
-                                               pwm|regulator|rtc|sysctrl|usb]";
-
-Optional child device properties:
-- interrupts             : contains the device IRQ(s) using the 2-cell format (see above)
-- interrupt-names        : contains names of IRQ resource in the order in which they were
-                           supplied in the interrupts property
-- <supply_name>-supply   : contains a phandle to the regulator supply node in Device Tree
-
-Non-standard child device properties:
- - Audio CODEC:
-   - stericsson,amic[1|2]-type-single-ended : Single-ended Analoge Mic (default: differential)
-   - stericsson,amic1a-bias-vamic2          : Analoge Mic wishes to use a non-standard Vamic
-   - stericsson,amic1b-bias-vamic2          : Analoge Mic wishes to use a non-standard Vamic
-   - stericsson,amic2-bias-vamic1           : Analoge Mic wishes to use a non-standard Vamic
-   - stericsson,earpeice-cmv                : Earpeice voltage (only: 950 | 1100 | 1270 | 1580)
-
-ab8500@5 {
-         compatible = "stericsson,ab8500";
-         reg = <5>; /* mailbox 5 is i2c */
-         interrupts = <0 40 0x4>;
-         interrupt-controller;
-         #interrupt-cells = <2>;
-
-         ab8500-rtc {
-                 compatible = "stericsson,ab8500-rtc";
-                 interrupts = <17 0x4
-                               18 0x4>;
-                 interrupt-names = "60S", "ALARM";
-         };
-
-        ab8500-gpadc {
-                compatible = "stericsson,ab8500-gpadc";
-                interrupts = <32 0x4
-                              39 0x4>;
-                interrupt-names = "HW_CONV_END", "SW_CONV_END";
-                vddadc-supply = <&ab8500_ldo_tvout_reg>;
-        };
-
-        ab8500-usb {
-                compatible = "stericsson,ab8500-usb";
-                interrupts = < 90 0x4
-                               96 0x4
-                               14 0x4
-                               15 0x4
-                               79 0x4
-                               74 0x4
-                               75 0x4>;
-                interrupt-names = "ID_WAKEUP_R",
-                                  "ID_WAKEUP_F",
-                                  "VBUS_DET_F",
-                                  "VBUS_DET_R",
-                                  "USB_LINK_STATUS",
-                                  "USB_ADP_PROBE_PLUG",
-                                  "USB_ADP_PROBE_UNPLUG";
-                vddulpivio18-supply = <&ab8500_ldo_initcore_reg>;
-                v-ape-supply = <&db8500_vape_reg>;
-                musb_1v8-supply = <&db8500_vsmps2_reg>;
-        };
-
-        ab8500-ponkey {
-                compatible = "stericsson,ab8500-ponkey";
-                interrupts = <6 0x4
-                              7 0x4>;
-                interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
-        };
-
-        ab8500-sysctrl {
-                compatible = "stericsson,ab8500-sysctrl";
-        };
-
-        ab8500-pwm {
-                compatible = "stericsson,ab8500-pwm";
-        };
-
-        codec: ab8500-codec {
-                compatible = "stericsson,ab8500-codec";
-
-                stericsson,earpeice-cmv = <950>; /* Units in mV. */
-        };
-
-        ab8500-regulators {
-                compatible = "stericsson,ab8500-regulator";
-
-                ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
-                        /*
-                         * See: Documentation/devicetree/bindings/regulator/regulator.txt
-                         * for more information on regulators
-                         */
-                };
-        };
-};
diff --git a/Documentation/devicetree/bindings/mfd/da9052-i2c.txt b/Documentation/devicetree/bindings/mfd/da9052-i2c.txt
deleted file mode 100644
index 1857f4a6b9a..00000000000
--- a/Documentation/devicetree/bindings/mfd/da9052-i2c.txt
+++ /dev/null
@@ -1,60 +0,0 @@
-* Dialog DA9052/53 Power Management Integrated Circuit (PMIC)
-
-Required properties:
-- compatible : Should be "dlg,da9052", "dlg,da9053-aa",
-                         "dlg,da9053-ab", or "dlg,da9053-bb"
-
-Sub-nodes:
-- regulators : Contain the regulator nodes. The DA9052/53 regulators are
-  bound using their names as listed below:
-
-    buck0     : regulator BUCK0
-    buck1     : regulator BUCK1
-    buck2     : regulator BUCK2
-    buck3     : regulator BUCK3
-    ldo4      : regulator LDO4
-    ldo5      : regulator LDO5
-    ldo6      : regulator LDO6
-    ldo7      : regulator LDO7
-    ldo8      : regulator LDO8
-    ldo9      : regulator LDO9
-    ldo10     : regulator LDO10
-    ldo11     : regulator LDO11
-    ldo12     : regulator LDO12
-    ldo13     : regulator LDO13
-
-  The bindings details of individual regulator device can be found in:
-  Documentation/devicetree/bindings/regulator/regulator.txt
-
-Examples:
-
-i2c@63fc8000 { /* I2C1 */
-        status = "okay";
-
-        pmic: dialog@48 {
-                compatible = "dlg,da9053-aa";
-                reg = <0x48>;
-
-                regulators {
-                        buck0 {
-                                regulator-min-microvolt = <500000>;
-                                regulator-max-microvolt = <2075000>;
-                        };
-
-                        buck1 {
-                                regulator-min-microvolt = <500000>;
-                                regulator-max-microvolt = <2075000>;
-                        };
-
-                        buck2 {
-                                regulator-min-microvolt = <925000>;
-                                regulator-max-microvolt = <2500000>;
-                        };
-
-                        buck3 {
-                                regulator-min-microvolt = <925000>;
-                                regulator-max-microvolt = <2500000>;
-                        };
-                };
-        };
-};
diff --git a/Documentation/devicetree/bindings/mfd/max77686.txt b/Documentation/devicetree/bindings/mfd/max77686.txt
deleted file mode 100644
index c6a3469d343..00000000000
--- a/Documentation/devicetree/bindings/mfd/max77686.txt
+++ /dev/null
@@ -1,59 +0,0 @@
-Maxim MAX77686 multi-function device
-
-MAX77686 is a Mulitifunction device with PMIC, RTC and Charger on chip. It is
-interfaced to host controller using i2c interface. PMIC and Charger submodules
-are addressed using same i2c slave address whereas RTC submodule uses
-different i2c slave address,presently for which we are statically creating i2c
-client while probing.This document describes the binding for mfd device and
-PMIC submodule.
-
-Required properties:
-- compatible : Must be "maxim,max77686";
-- reg : Specifies the i2c slave address of PMIC block.
-- interrupts : This i2c device has an IRQ line connected to the main SoC.
-- interrupt-parent : The parent interrupt controller.
-
-Optional node:
-- voltage-regulators : The regulators of max77686 have to be instantiated
-  under subnode named "voltage-regulators" using the following format.
-
-        regulator_name {
-                regulator-compatible = LDOn/BUCKn
-                standard regulator constraints....
-        };
-        refer Documentation/devicetree/bindings/regulator/regulator.txt
-
-  The regulator-compatible property of regulator should initialized with string
-to get matched with their hardware counterparts as follow:
-
-        -LDOn   :       for LDOs, where n can lie in range 1 to 26.
-                        example: LDO1, LDO2, LDO26.
-        -BUCKn  :       for BUCKs, where n can lie in range 1 to 9.
-                        example: BUCK1, BUCK5, BUCK9.
-
-Example:
-
-        max77686@09 {
-                compatible = "maxim,max77686";
-                interrupt-parent = <&wakeup_eint>;
-                interrupts = <26 0>;
-                reg = <0x09>;
-
-                voltage-regulators {
-                        ldo11_reg {
-                                regulator-compatible = "LDO11";
-                                regulator-name = "vdd_ldo11";
-                                regulator-min-microvolt = <1900000>;
-                                regulator-max-microvolt = <1900000>;
-                                regulator-always-on;
-                        };
-
-                        buck1_reg {
-                                regulator-compatible = "BUCK1";
-                                regulator-name = "vdd_mif";
-                                regulator-min-microvolt = <950000>;
-                                regulator-max-microvolt = <1300000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                        };
-        }
diff --git a/Documentation/devicetree/bindings/mfd/mc13xxx.txt b/Documentation/devicetree/bindings/mfd/mc13xxx.txt
deleted file mode 100644
index baf07987ae6..00000000000
--- a/Documentation/devicetree/bindings/mfd/mc13xxx.txt
+++ /dev/null
@@ -1,78 +0,0 @@
-* Freescale MC13783/MC13892 Power Management Integrated Circuit (PMIC)
-
-Required properties:
-- compatible : Should be "fsl,mc13783" or "fsl,mc13892"
-
-Optional properties:
-- fsl,mc13xxx-uses-adc : Indicate the ADC is being used
-- fsl,mc13xxx-uses-codec : Indicate the Audio Codec is being used
-- fsl,mc13xxx-uses-rtc : Indicate the RTC is being used
-- fsl,mc13xxx-uses-touch : Indicate the touchscreen controller is being used
-
-Sub-nodes:
-- regulators : Contain the regulator nodes.  The MC13892 regulators are
-  bound using their names as listed below with their registers and bits
-  for enabling.
-
-    vcoincell : regulator VCOINCELL (register 13, bit 23)
-    sw1       : regulator SW1       (register 24, bit 0)
-    sw2       : regulator SW2       (register 25, bit 0)
-    sw3       : regulator SW3       (register 26, bit 0)
-    sw4       : regulator SW4       (register 27, bit 0)
-    swbst     : regulator SWBST     (register 29, bit 20)
-    vgen1     : regulator VGEN1     (register 32, bit 0)
-    viohi     : regulator VIOHI     (register 32, bit 3)
-    vdig      : regulator VDIG      (register 32, bit 9)
-    vgen2     : regulator VGEN2     (register 32, bit 12)
-    vpll      : regulator VPLL      (register 32, bit 15)
-    vusb2     : regulator VUSB2     (register 32, bit 18)
-    vgen3     : regulator VGEN3     (register 33, bit 0)
-    vcam      : regulator VCAM      (register 33, bit 6)
-    vvideo    : regulator VVIDEO    (register 33, bit 12)
-    vaudio    : regulator VAUDIO    (register 33, bit 15)
-    vsd       : regulator VSD       (register 33, bit 18)
-    gpo1      : regulator GPO1      (register 34, bit 6)
-    gpo2      : regulator GPO2      (register 34, bit 8)
-    gpo3      : regulator GPO3      (register 34, bit 10)
-    gpo4      : regulator GPO4      (register 34, bit 12)
-    pwgt1spi  : regulator PWGT1SPI  (register 34, bit 15)
-    pwgt2spi  : regulator PWGT2SPI  (register 34, bit 16)
-    vusb      : regulator VUSB      (register 50, bit 3)
-
-  The bindings details of individual regulator device can be found in:
-  Documentation/devicetree/bindings/regulator/regulator.txt
-
-Examples:
-
-ecspi@70010000 { /* ECSPI1 */
-        fsl,spi-num-chipselects = <2>;
-        cs-gpios = <&gpio4 24 0>, /* GPIO4_24 */
-                   <&gpio4 25 0>; /* GPIO4_25 */
-        status = "okay";
-
-        pmic: mc13892@0 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "fsl,mc13892";
-                spi-max-frequency = <6000000>;
-                reg = <0>;
-                interrupt-parent = <&gpio0>;
-                interrupts = <8>;
-
-                regulators {
-                        sw1_reg: mc13892__sw1 {
-                                regulator-min-microvolt = <600000>;
-                                regulator-max-microvolt = <1375000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-
-                        sw2_reg: mc13892__sw2 {
-                                regulator-min-microvolt = <900000>;
-                                regulator-max-microvolt = <1850000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-                };
-        };
-};
diff --git a/Documentation/devicetree/bindings/mfd/stmpe.txt b/Documentation/devicetree/bindings/mfd/stmpe.txt
deleted file mode 100644
index 56edb552068..00000000000
--- a/Documentation/devicetree/bindings/mfd/stmpe.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-* ST Microelectronics STMPE Multi-Functional Device
-
-STMPE is an MFD device which may expose the following inbuilt devices: gpio,
-keypad, touchscreen, adc, pwm, rotator.
-
-Required properties:
- - compatible                   : "st,stmpe[610|801|811|1601|2401|2403]"
- - reg                          : I2C/SPI address of the device
-
-Optional properties:
- - interrupts                   : The interrupt outputs from the controller
- - interrupt-controller         : Marks the device node as an interrupt controller
- - interrupt-parent             : Specifies which IRQ controller we're connected to
- - wakeup-source                : Marks the input device as wakable
- - st,autosleep-timeout         : Valid entries (ms); 4, 16, 32, 64, 128, 256, 512 and 1024
-
-Example:
-
-        stmpe1601: stmpe1601@40 {
-                compatible = "st,stmpe1601";
-                reg = <0x40>;
-                interrupts = <26 0x4>;
-                interrupt-parent = <&gpio6>;
-                interrupt-controller;
-
-                wakeup-source;
-                st,autosleep-timeout = <1024>;
-        };
diff --git a/Documentation/devicetree/bindings/mfd/syscon.txt b/Documentation/devicetree/bindings/mfd/syscon.txt
deleted file mode 100644
index fe8150bb324..00000000000
--- a/Documentation/devicetree/bindings/mfd/syscon.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-* System Controller Registers R/W driver
-
-System controller node represents a register region containing a set
-of miscellaneous registers. The registers are not cohesive enough to
-represent as any specific type of device. The typical use-case is for
-some other node's driver, or platform-specific code, to acquire a
-reference to the syscon node (e.g. by phandle, node path, or search
-using a specific compatible value), interrogate the node (or associated
-OS driver) to determine the location of the registers, and access the
-registers directly.
-
-Required properties:
-- compatible: Should contain "syscon".
-- reg: the register region can be accessed from syscon
-
-Examples:
-gpr: iomuxc-gpr@020e0000 {
-        compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
-        reg = <0x020e0000 0x38>;
-};
diff --git a/Documentation/devicetree/bindings/mfd/tps65910.txt b/Documentation/devicetree/bindings/mfd/tps65910.txt
deleted file mode 100644
index 2e3304888ff..00000000000
--- a/Documentation/devicetree/bindings/mfd/tps65910.txt
+++ /dev/null
@@ -1,201 +0,0 @@
-TPS65910 Power Management Integrated Circuit
-
-Required properties:
-- compatible: "ti,tps65910" or "ti,tps65911"
-- reg: I2C slave address
-- interrupts: the interrupt outputs of the controller
-- #gpio-cells: number of cells to describe a GPIO, this should be 2.
-  The first cell is the GPIO number.
-  The second cell is used to specify additional options <unused>.
-- gpio-controller: mark the device as a GPIO controller
-- #interrupt-cells: the number of cells to describe an IRQ, this should be 2.
-  The first cell is the IRQ number.
-  The second cell is the flags, encoded as the trigger masks from
-  Documentation/devicetree/bindings/interrupts.txt
-- regulators: This is the list of child nodes that specify the regulator
-  initialization data for defined regulators. Not all regulators for the given
-  device need to be present. The definition for each of these nodes is defined
-  using the standard binding for regulators found at
-  Documentation/devicetree/bindings/regulator/regulator.txt.
-  The regulator is matched with the regulator-compatible.
-
-  The valid regulator-compatible values are:
-  tps65910: vrtc, vio, vdd1, vdd2, vdd3, vdig1, vdig2, vpll, vdac, vaux1,
-            vaux2, vaux33, vmmc
-  tps65911: vrtc, vio, vdd1, vdd3, vddctrl, ldo1, ldo2, ldo3, ldo4, ldo5,
-            ldo6, ldo7, ldo8
-
-- xxx-supply: Input voltage supply regulator.
-  These entries are require if regulators are enabled for a device. Missing of these
-  properties can cause the regulator registration fails.
-  If some of input supply is powered through battery or always-on supply then
-  also it is require to have these parameters with proper node handle of always
-  on power supply.
-  tps65910:
-        vcc1-supply: VDD1 input.
-        vcc2-supply: VDD2 input.
-        vcc3-supply: VAUX33 and VMMC input.
-        vcc4-supply: VAUX1 and VAUX2 input.
-        vcc5-supply: VPLL and VDAC input.
-        vcc6-supply: VDIG1 and VDIG2 input.
-        vcc7-supply: VRTC input.
-        vccio-supply: VIO input.
-  tps65911:
-        vcc1-supply: VDD1 input.
-        vcc2-supply: VDD2 input.
-        vcc3-supply: LDO6, LDO7 and LDO8 input.
-        vcc4-supply: LDO5 input.
-        vcc5-supply: LDO3 and LDO4 input.
-        vcc6-supply: LDO1 and LDO2 input.
-        vcc7-supply: VRTC input.
-        vccio-supply: VIO input.
-
-Optional properties:
-- ti,vmbch-threshold: (tps65911) main battery charged threshold
-  comparator. (see VMBCH_VSEL in TPS65910 datasheet)
-- ti,vmbch2-threshold: (tps65911) main battery discharged threshold
-  comparator. (see VMBCH_VSEL in TPS65910 datasheet)
-- ti,en-ck32k-xtal: enable external 32-kHz crystal oscillator (see CK32K_CTRL
-  in TPS6591X datasheet)
-- ti,en-gpio-sleep: enable sleep control for gpios
-  There should be 9 entries here, one for each gpio.
-- ti,system-power-controller: Telling whether or not this pmic is controlling
-  the system power.
-
-Regulator Optional properties:
-- ti,regulator-ext-sleep-control: enable external sleep
-  control through external inputs [0 (not enabled), 1 (EN1), 2 (EN2) or 4(EN3)]
-  If this property is not defined, it defaults to 0 (not enabled).
-
-Example:
-
-        pmu: tps65910@d2 {
-                compatible = "ti,tps65910";
-                reg = <0xd2>;
-                interrupt-parent = <&intc>;
-                interrupts = < 0 118 0x04 >;
-
-                #gpio-cells = <2>;
-                gpio-controller;
-
-                #interrupt-cells = <2>;
-                interrupt-controller;
-
-                ti,system-power-controller;
-
-                ti,vmbch-threshold = 0;
-                ti,vmbch2-threshold = 0;
-                ti,en-ck32k-xtal;
-                ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>;
-
-                vcc1-supply = <&reg_parent>;
-                vcc2-supply = <&some_reg>;
-                vcc3-supply = <...>;
-                vcc4-supply = <...>;
-                vcc5-supply = <...>;
-                vcc6-supply = <...>;
-                vcc7-supply = <...>;
-                vccio-supply = <...>;
-
-                regulators {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        vdd1_reg: regulator@0 {
-                                regulator-compatible = "vdd1";
-                                reg = <0>;
-                                regulator-min-microvolt = < 600000>;
-                                regulator-max-microvolt = <1500000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                                ti,regulator-ext-sleep-control = <0>;
-                        };
-                        vdd2_reg: regulator@1 {
-                                regulator-compatible = "vdd2";
-                                reg = <1>;
-                                regulator-min-microvolt = < 600000>;
-                                regulator-max-microvolt = <1500000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                                ti,regulator-ext-sleep-control = <4>;
-                        };
-                        vddctrl_reg: regulator@2 {
-                                regulator-compatible = "vddctrl";
-                                reg = <2>;
-                                regulator-min-microvolt = < 600000>;
-                                regulator-max-microvolt = <1400000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                                ti,regulator-ext-sleep-control = <0>;
-                        };
-                        vio_reg: regulator@3 {
-                                regulator-compatible = "vio";
-                                reg = <3>;
-                                regulator-min-microvolt = <1500000>;
-                                regulator-max-microvolt = <1800000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                                ti,regulator-ext-sleep-control = <1>;
-                        };
-                        ldo1_reg: regulator@4 {
-                                regulator-compatible = "ldo1";
-                                reg = <4>;
-                                regulator-min-microvolt = <1000000>;
-                                regulator-max-microvolt = <3300000>;
-                                ti,regulator-ext-sleep-control = <0>;
-                        };
-                        ldo2_reg: regulator@5 {
-                                regulator-compatible = "ldo2";
-                                reg = <5>;
-                                regulator-min-microvolt = <1050000>;
-                                regulator-max-microvolt = <1050000>;
-                                ti,regulator-ext-sleep-control = <0>;
-                        };
-                        ldo3_reg: regulator@6 {
-                                regulator-compatible = "ldo3";
-                                reg = <6>;
-                                regulator-min-microvolt = <1000000>;
-                                regulator-max-microvolt = <3300000>;
-                                ti,regulator-ext-sleep-control = <0>;
-                        };
-                        ldo4_reg: regulator@7 {
-                                regulator-compatible = "ldo4";
-                                reg = <7>;
-                                regulator-min-microvolt = <1000000>;
-                                regulator-max-microvolt = <3300000>;
-                                regulator-always-on;
-                                ti,regulator-ext-sleep-control = <0>;
-                        };
-                        ldo5_reg: regulator@8 {
-                                regulator-compatible = "ldo5";
-                                reg = <8>;
-                                regulator-min-microvolt = <1000000>;
-                                regulator-max-microvolt = <3300000>;
-                                ti,regulator-ext-sleep-control = <0>;
-                        };
-                        ldo6_reg: regulator@9 {
-                                regulator-compatible = "ldo6";
-                                reg = <9>;
-                                regulator-min-microvolt = <1200000>;
-                                regulator-max-microvolt = <1200000>;
-                                ti,regulator-ext-sleep-control = <0>;
-                        };
-                        ldo7_reg: regulator@10 {
-                                regulator-compatible = "ldo7";
-                                reg = <10>;
-                                regulator-min-microvolt = <1200000>;
-                                regulator-max-microvolt = <1200000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                                ti,regulator-ext-sleep-control = <1>;
-                        };
-                        ldo8_reg: regulator@11 {
-                                regulator-compatible = "ldo8";
-                                reg = <11>;
-                                regulator-min-microvolt = <1000000>;
-                                regulator-max-microvolt = <3300000>;
-                                regulator-always-on;
-                                ti,regulator-ext-sleep-control = <1>;
-                        };
-                };
-        };
diff --git a/Documentation/devicetree/bindings/mfd/twl-familly.txt b/Documentation/devicetree/bindings/mfd/twl-familly.txt
deleted file mode 100644
index a66fcf94675..00000000000
--- a/Documentation/devicetree/bindings/mfd/twl-familly.txt
+++ /dev/null
@@ -1,47 +0,0 @@
-Texas Instruments TWL family
-
-The TWLs are Integrated Power Management Chips.
-Some version might contain much more analog function like
-USB transceiver or Audio amplifier.
-These chips are connected to an i2c bus.
-
-
-Required properties:
-- compatible : Must be "ti,twl4030";
-  For Integrated power-management/audio CODEC device used in OMAP3
-  based boards
-- compatible : Must be "ti,twl6030";
-  For Integrated power-management used in OMAP4 based boards
-- interrupts : This i2c device has an IRQ line connected to the main SoC
-- interrupt-controller : Since the twl support several interrupts internally,
-  it is considered as an interrupt controller cascaded to the SoC one.
-- #interrupt-cells = <1>;
-- interrupt-parent : The parent interrupt controller.
-
-Optional node:
-- Child nodes contain in the twl. The twl family is made of several variants
-  that support a different number of features.
-  The children nodes will thus depend of the capability of the variant.
-
-
-Example:
-/*
- * Integrated Power Management Chip
- * http://www.ti.com/lit/ds/symlink/twl6030.pdf
- */
-twl@48 {
-    compatible = "ti,twl6030";
-    reg = <0x48>;
-    interrupts = <39>; /* IRQ_SYS_1N cascaded to gic */
-    interrupt-controller;
-    #interrupt-cells = <1>;
-    interrupt-parent = <&gic>;
-    #address-cells = <1>;
-    #size-cells = <0>;
-
-    twl_rtc {
-        compatible = "ti,twl_rtc";
-        interrupts = <11>;
-        reg = <0>;
-    };
-};
diff --git a/Documentation/devicetree/bindings/mfd/twl4030-audio.txt b/Documentation/devicetree/bindings/mfd/twl4030-audio.txt
deleted file mode 100644
index 414d2ae0adf..00000000000
--- a/Documentation/devicetree/bindings/mfd/twl4030-audio.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-Texas Instruments TWL family (twl4030) audio module
-
-The audio module inside the TWL family consist of an audio codec and a vibra
-driver.
-
-Required properties:
-- compatible : must be "ti,twl4030-audio"
-
-Optional properties, nodes:
-
-Audio functionality:
-- codec { }: Need to be present if the audio functionality is used. Within this
-             section the following options can be used:
-- ti,digimic_delay: Delay need after enabling the digimic to reduce artifacts
-                    from the start of the recorded sample (in ms)
--ti,ramp_delay_value: HS ramp delay configuration to reduce pop noise
--ti,hs_extmute: Use external mute for HS pop reduction
--ti,hs_extmute_gpio: Use external GPIO to control the external mute
--ti,offset_cncl_path: Offset cancellation path selection, refer to TRM for the
-                      valid values.
-
-Vibra functionality
-- ti,enable-vibra: Need to be set to <1> if the vibra functionality is used. if
-                   missing or it is 0, the vibra functionality is disabled.
-
-Example:
-&i2c1 {
-        clock-frequency = <2600000>;
-
-        twl: twl@48 {
-                reg = <0x48>;
-                interrupts = <7>; /* SYS_NIRQ cascaded to intc */
-                interrupt-parent = <&intc>;
-
-                twl_audio: audio {
-                        compatible = "ti,twl4030-audio";
-
-                        ti,enable-vibra = <1>;
-
-                        codec {
-                                ti,ramp_delay_value = <3>;
-                        };
-
-                };
-        };
-};
diff --git a/Documentation/devicetree/bindings/mfd/twl6040.txt b/Documentation/devicetree/bindings/mfd/twl6040.txt
deleted file mode 100644
index 0f5dd709d75..00000000000
--- a/Documentation/devicetree/bindings/mfd/twl6040.txt
+++ /dev/null
@@ -1,65 +0,0 @@
-Texas Instruments TWL6040 family
-
-The TWL6040s are 8-channel high quality low-power audio codecs providing audio,
-vibra and GPO functionality on OMAP4+ platforms.
-They are connected ot the host processor via i2c for commands, McPDM for audio
-data and commands.
-
-Required properties:
-- compatible : "ti,twl6040" for twl6040, "ti,twl6041" for twl6041
-- reg: must be 0x4b for i2c address
-- interrupts: twl6040 has one interrupt line connecteded to the main SoC
-- interrupt-parent: The parent interrupt controller
-- gpio-controller:
-- #gpio-cells = <1>: twl6040 provides GPO lines.
-- twl6040,audpwron-gpio: Power on GPIO line for the twl6040
-
-- vio-supply: Regulator for the twl6040 VIO supply
-- v2v1-supply: Regulator for the twl6040 V2V1 supply
-
-Optional properties, nodes:
-- enable-active-high: To power on the twl6040 during boot.
-
-Vibra functionality
-Required properties:
-- vddvibl-supply: Regulator for the left vibra motor
-- vddvibr-supply: Regulator for the right vibra motor
-- vibra { }: Configuration section for vibra parameters containing the following
-             properties:
-- ti,vibldrv-res: Resistance parameter for left driver
-- ti,vibrdrv-res: Resistance parameter for right driver
-- ti,viblmotor-res: Resistance parameter for left motor
-- ti,viblmotor-res: Resistance parameter for right motor
-
-Optional properties within vibra { } section:
-- vddvibl_uV: If the vddvibl default voltage need to be changed
-- vddvibr_uV: If the vddvibr default voltage need to be changed
-
-Example:
-&i2c1 {
-        twl6040: twl@4b {
-                compatible = "ti,twl6040";
-
-                interrupts = <0 119 4>;
-                interrupt-parent = <&gic>;
-                twl6040,audpwron-gpio = <&gpio4 31 0>;
-
-                vio-supply = <&v1v8>;
-                v2v1-supply = <&v2v1>;
-                enable-active-high;
-
-                /* regulators for vibra motor */
-                vddvibl-supply = <&vbat>;
-                vddvibr-supply = <&vbat>;
-
-                vibra {
-                        /* Vibra driver, motor resistance parameters */
-                        ti,vibldrv-res = <8>;
-                        ti,vibrdrv-res = <3>;
-                        ti,viblmotor-res = <10>;
-                        ti,vibrmotor-res = <10>;
-                };
-        };
-};
-
-/include/ "twl6040.dtsi"
diff --git a/Documentation/devicetree/bindings/mips/cavium/bootbus.txt b/Documentation/devicetree/bindings/mips/cavium/bootbus.txt
deleted file mode 100644
index 6581478225a..00000000000
--- a/Documentation/devicetree/bindings/mips/cavium/bootbus.txt
+++ /dev/null
@@ -1,126 +0,0 @@
-* Boot Bus
-
-The Octeon Boot Bus is a configurable parallel bus with 8 chip
-selects.  Each chip select is independently configurable.
-
-Properties:
-- compatible: "cavium,octeon-3860-bootbus"
-
-  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
-
-- reg: The base address of the Boot Bus' register bank.
-
-- #address-cells: Must be <2>.  The first cell is the chip select
-   within the bootbus.  The second cell is the offset from the chip select.
-
-- #size-cells: Must be <1>.
-
-- ranges: There must be one one triplet of (child-bus-address,
-  parent-bus-address, length) for each active chip select.  If the
-  length element for any triplet is zero, the chip select is disabled,
-  making it inactive.
-
-The configuration parameters for each chip select are stored in child
-nodes.
-
-Configuration Properties:
-- compatible:  "cavium,octeon-3860-bootbus-config"
-
-- cavium,cs-index: A single cell indicating the chip select that
-  corresponds to this configuration.
-
-- cavium,t-adr: A cell specifying the ADR timing (in nS).
-
-- cavium,t-ce: A cell specifying the CE timing (in nS).
-
-- cavium,t-oe: A cell specifying the OE timing (in nS).
-
-- cavium,t-we: A cell specifying the WE timing (in nS).
-
-- cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS).
-
-- cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS).
-
-- cavium,t-pause: A cell specifying the PAUSE timing (in nS).
-
-- cavium,t-wait: A cell specifying the WAIT timing (in nS).
-
-- cavium,t-page: A cell specifying the PAGE timing (in nS).
-
-- cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS).
-
-- cavium,pages: A cell specifying the PAGES parameter (0 = 8 bytes, 1
-  = 2 bytes, 2 = 4 bytes, 3 = 8 bytes).
-
-- cavium,wait-mode: Optional.  If present, wait mode (WAITM) is selected.
-
-- cavium,page-mode: Optional.  If present, page mode (PAGEM) is selected.
-
-- cavium,bus-width: A cell specifying the WIDTH parameter (in bits) of
-  the bus for this chip select.
-
-- cavium,ale-mode: Optional.  If present, ALE mode is selected.
-
-- cavium,sam-mode: Optional.  If present, SAM mode is selected.
-
-- cavium,or-mode: Optional.  If present, OR mode is selected.
-
-Example:
-        bootbus: bootbus@1180000000000 {
-                compatible = "cavium,octeon-3860-bootbus";
-                reg = <0x11800 0x00000000 0x0 0x200>;
-                /* The chip select number and offset */
-                #address-cells = <2>;
-                /* The size of the chip select region */
-                #size-cells = <1>;
-                ranges = <0 0  0x0 0x1f400000  0xc00000>,
-                         <1 0  0x10000 0x30000000  0>,
-                         <2 0  0x10000 0x40000000  0>,
-                         <3 0  0x10000 0x50000000  0>,
-                         <4 0  0x0 0x1d020000  0x10000>,
-                         <5 0  0x0 0x1d040000  0x10000>,
-                         <6 0  0x0 0x1d050000  0x10000>,
-                         <7 0  0x10000 0x90000000  0>;
-
-                        cavium,cs-config@0 {
-                        compatible = "cavium,octeon-3860-bootbus-config";
-                        cavium,cs-index = <0>;
-                        cavium,t-adr  = <20>;
-                        cavium,t-ce   = <60>;
-                        cavium,t-oe   = <60>;
-                        cavium,t-we   = <45>;
-                        cavium,t-rd-hld = <35>;
-                        cavium,t-wr-hld = <45>;
-                        cavium,t-pause  = <0>;
-                        cavium,t-wait   = <0>;
-                        cavium,t-page   = <35>;
-                        cavium,t-rd-dly = <0>;
-
-                        cavium,pages     = <0>;
-                        cavium,bus-width = <8>;
-                };
-                .
-                .
-                .
-                cavium,cs-config@6 {
-                        compatible = "cavium,octeon-3860-bootbus-config";
-                        cavium,cs-index = <6>;
-                        cavium,t-adr  = <5>;
-                        cavium,t-ce   = <300>;
-                        cavium,t-oe   = <270>;
-                        cavium,t-we   = <150>;
-                        cavium,t-rd-hld = <100>;
-                        cavium,t-wr-hld = <70>;
-                        cavium,t-pause  = <0>;
-                        cavium,t-wait   = <0>;
-                        cavium,t-page   = <320>;
-                        cavium,t-rd-dly = <0>;
-
-                        cavium,pages     = <0>;
-                        cavium,wait-mode;
-                        cavium,bus-width = <16>;
-                };
-                .
-                .
-                .
-        };
diff --git a/Documentation/devicetree/bindings/mips/cavium/ciu.txt b/Documentation/devicetree/bindings/mips/cavium/ciu.txt
deleted file mode 100644
index 2c2d0746b43..00000000000
--- a/Documentation/devicetree/bindings/mips/cavium/ciu.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-* Central Interrupt Unit
-
-Properties:
-- compatible: "cavium,octeon-3860-ciu"
-
-  Compatibility with all cn3XXX, cn5XXX and cn63XX SOCs.
-
-- interrupt-controller:  This is an interrupt controller.
-
-- reg: The base address of the CIU's register bank.
-
-- #interrupt-cells: Must be <2>.  The first cell is the bank within
-   the CIU and may have a value of 0 or 1.  The second cell is the bit
-   within the bank and may have a value between 0 and 63.
-
-Example:
-        interrupt-controller@1070000000000 {
-                compatible = "cavium,octeon-3860-ciu";
-                interrupt-controller;
-                /* Interrupts are specified by two parts:
-                 * 1) Controller register (0 or 1)
-                 * 2) Bit within the register (0..63)
-                 */
-                #interrupt-cells = <2>;
-                reg = <0x10700 0x00000000 0x0 0x7000>;
-        };
diff --git a/Documentation/devicetree/bindings/mips/cavium/ciu2.txt b/Documentation/devicetree/bindings/mips/cavium/ciu2.txt
deleted file mode 100644
index 0ec7ba8bbbc..00000000000
--- a/Documentation/devicetree/bindings/mips/cavium/ciu2.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-* Central Interrupt Unit
-
-Properties:
-- compatible: "cavium,octeon-6880-ciu2"
-
-  Compatibility with 68XX SOCs.
-
-- interrupt-controller:  This is an interrupt controller.
-
-- reg: The base address of the CIU's register bank.
-
-- #interrupt-cells: Must be <2>.  The first cell is the bank within
-  the CIU and may have a value between 0 and 63.  The second cell is
-  the bit within the bank and may also have a value between 0 and 63.
-
-Example:
-        interrupt-controller@1070100000000 {
-                compatible = "cavium,octeon-6880-ciu2";
-                interrupt-controller;
-                /* Interrupts are specified by two parts:
-                 * 1) Controller register (0..63)
-                 * 2) Bit within the register (0..63)
-                 */
-                #address-cells = <0>;
-                #interrupt-cells = <2>;
-                reg = <0x10701 0x00000000 0x0 0x4000000>;
-        };
diff --git a/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt b/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt
deleted file mode 100644
index cb4291e3b1d..00000000000
--- a/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-* DMA Engine.
-
-The Octeon DMA Engine transfers between the Boot Bus and main memory.
-The DMA Engine will be refered to by phandle by any device that is
-connected to it.
-
-Properties:
-- compatible: "cavium,octeon-5750-bootbus-dma"
-
-  Compatibility with all cn52XX, cn56XX and cn6XXX SOCs.
-
-- reg: The base address of the DMA Engine's register bank.
-
-- interrupts: A single interrupt specifier.
-
-Example:
-        dma0: dma-engine@1180000000100 {
-                compatible = "cavium,octeon-5750-bootbus-dma";
-                reg = <0x11800 0x00000100 0x0 0x8>;
-                interrupts = <0 63>;
-        };
diff --git a/Documentation/devicetree/bindings/mips/cavium/uctl.txt b/Documentation/devicetree/bindings/mips/cavium/uctl.txt
deleted file mode 100644
index aa66b9b8d80..00000000000
--- a/Documentation/devicetree/bindings/mips/cavium/uctl.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-* UCTL USB controller glue
-
-Properties:
-- compatible: "cavium,octeon-6335-uctl"
-
-  Compatibility with all cn6XXX SOCs.
-
-- reg: The base address of the UCTL register bank.
-
-- #address-cells: Must be <2>.
-
-- #size-cells: Must be <2>.
-
-- ranges: Empty to signify direct mapping of the children.
-
-- refclk-frequency: A single cell containing the reference clock
-  frequency in Hz.
-
-- refclk-type: A string describing the reference clock connection
-  either "crystal" or "external".
-
-Example:
-        uctl@118006f000000 {
-                compatible = "cavium,octeon-6335-uctl";
-                reg = <0x11800 0x6f000000 0x0 0x100>;
-                ranges; /* Direct mapping */
-                #address-cells = <2>;
-                #size-cells = <2>;
-                /* 12MHz, 24MHz and 48MHz allowed */
-                refclk-frequency = <24000000>;
-                /* Either "crystal" or "external" */
-                refclk-type = "crystal";
-
-                ehci@16f0000000000 {
-                        compatible = "cavium,octeon-6335-ehci","usb-ehci";
-                        reg = <0x16f00 0x00000000 0x0 0x100>;
-                        interrupts = <0 56>;
-                        big-endian-regs;
-                };
-                ohci@16f0000000400 {
-                        compatible = "cavium,octeon-6335-ohci","usb-ohci";
-                        reg = <0x16f00 0x00000400 0x0 0x100>;
-                        interrupts = <0 56>;
-                        big-endian-regs;
-                };
-        };
diff --git a/Documentation/devicetree/bindings/misc/at25.txt b/Documentation/devicetree/bindings/misc/at25.txt
deleted file mode 100644
index 1d3447165c3..00000000000
--- a/Documentation/devicetree/bindings/misc/at25.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-EEPROMs (SPI) compatible with Atmel at25.
-
-Required properties:
-- compatible : "atmel,at25".
-- reg : chip select number
-- spi-max-frequency : max spi frequency to use
-- pagesize : size of the eeprom page
-- size : total eeprom size in bytes
-- address-width : number of address bits (one of 8, 16, or 24)
-
-Optional properties:
-- spi-cpha : SPI shifted clock phase, as per spi-bus bindings.
-- spi-cpol : SPI inverse clock polarity, as per spi-bus bindings.
-- read-only : this parameter-less property disables writes to the eeprom
-
-Obsolete legacy properties are can be used in place of "size", "pagesize",
-"address-width", and "read-only":
-- at25,byte-len : total eeprom size in bytes
-- at25,addr-mode : addr-mode flags, as defined in include/linux/spi/eeprom.h
-- at25,page-size : size of the eeprom page
-
-Additional compatible properties are also allowed.
-
-Example:
-        at25@0 {
-                compatible = "atmel,at25", "st,m95256";
-                reg = <0>
-                spi-max-frequency = <5000000>;
-                spi-cpha;
-                spi-cpol;
-
-                pagesize = <64>;
-                size = <32768>;
-                address-width = <16>;
-        };
diff --git a/Documentation/devicetree/bindings/misc/atmel-ssc.txt b/Documentation/devicetree/bindings/misc/atmel-ssc.txt
deleted file mode 100644
index 38e51ad2e07..00000000000
--- a/Documentation/devicetree/bindings/misc/atmel-ssc.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-* Atmel SSC driver.
-
-Required properties:
-- compatible: "atmel,at91rm9200-ssc" or "atmel,at91sam9g45-ssc"
-        - atmel,at91rm9200-ssc: support pdc transfer
-        - atmel,at91sam9g45-ssc: support dma transfer
-- reg: Should contain SSC registers location and length
-- interrupts: Should contain SSC interrupt
-
-Example:
-ssc0: ssc@fffbc000 {
-        compatible = "atmel,at91rm9200-ssc";
-        reg = <0xfffbc000 0x4000>;
-        interrupts = <14 4 5>;
-};
diff --git a/Documentation/devicetree/bindings/misc/bmp085.txt b/Documentation/devicetree/bindings/misc/bmp085.txt
deleted file mode 100644
index 91dfda2e4e1..00000000000
--- a/Documentation/devicetree/bindings/misc/bmp085.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-BMP085/BMP18x digital pressure sensors
-
-Required properties:
-- compatible: bosch,bmp085
-
-Optional properties:
-- chip-id: configurable chip id for non-default chip revisions
-- temp-measurement-period: temperature measurement period (milliseconds)
-- default-oversampling: default oversampling value to be used at startup,
-  value range is 0-3 with rising sensitivity.
-
-Example:
-
-pressure@77 {
-        compatible = "bosch,bmp085";
-        reg = <0x77>;
-        chip-id = <10>;
-        temp-measurement-period = <100>;
-        default-oversampling = <2>;
-};
diff --git a/Documentation/devicetree/bindings/misc/ifm-csi.txt b/Documentation/devicetree/bindings/misc/ifm-csi.txt
deleted file mode 100644
index 5bdfffb0b9f..00000000000
--- a/Documentation/devicetree/bindings/misc/ifm-csi.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-IFM camera sensor interface on mpc5200 LocalPlus bus
-
-Required properties:
-- compatible: "ifm,o2d-csi"
-- reg: specifies sensor chip select number and associated address range
-- interrupts: external interrupt line number and interrupt sense mode
-  of the interrupt line signaling frame valid events
-- gpios: three gpio-specifiers for "capture", "reset" and "master enable"
-  GPIOs (strictly in this order).
-- ifm,csi-clk-handle: the phandle to a node in the DT describing the sensor
-  clock generator. This node is usually a general purpose timer controller.
-- ifm,csi-addr-bus-width: address bus width (valid values are 16, 24, 25)
-- ifm,csi-data-bus-width: data bus width (valid values are 8 and 16)
-- ifm,csi-wait-cycles: sensor bus wait cycles
-
-Optional properties:
-- ifm,csi-byte-swap: if this property is present, the byte swapping on
-  the bus will be enabled.
-
-Example:
-
-        csi@3,0 {
-                compatible = "ifm,o2d-csi";
-                reg = <3 0 0x00100000>;         /* CS 3, 1 MiB range */
-                interrupts = <1 1 2>;           /* IRQ1, edge falling */
-
-                ifm,csi-clk-handle = <&timer7>;
-                gpios = <&gpio_simple 23 0      /* image_capture */
-                         &gpio_simple 26 0      /* image_reset */
-                         &gpio_simple 29 0>;    /* image_master_en */
-
-                ifm,csi-addr-bus-width = <24>;
-                ifm,csi-data-bus-width = <8>;
-                ifm,csi-wait-cycles = <0>;
-        };
-
-The base address of the used chip select is specified in the
-ranges property of the parent localbus node, for example:
-
-        ranges = <0 0 0xff000000 0x01000000
-                  3 0 0xe3000000 0x00100000>;
diff --git a/Documentation/devicetree/bindings/misc/lis302.txt b/Documentation/devicetree/bindings/misc/lis302.txt
deleted file mode 100644
index 6def86f6b05..00000000000
--- a/Documentation/devicetree/bindings/misc/lis302.txt
+++ /dev/null
@@ -1,112 +0,0 @@
-LIS302 accelerometer devicetree bindings
-
-This device is matched via its bus drivers, and has a number of properties
-that apply in on the generic device (independent from the bus).
-
-
-Required properties for the SPI bindings:
- - compatible:          should be set to "st,lis3lv02d_spi"
- - reg:                 the chipselect index
- - spi-max-frequency:   maximal bus speed, should be set to 1000000 unless
-                        constrained by external circuitry
- - interrupts:          the interrupt generated by the device
-
-Required properties for the I2C bindings:
- - compatible:          should be set to "st,lis3lv02d"
- - reg:                 i2c slave address
- - Vdd-supply:          The input supply for Vdd
- - Vdd_IO-supply:       The input supply for Vdd_IO
-
-
-Optional properties for all bus drivers:
-
- - st,click-single-{x,y,z}:     if present, tells the device to issue an
-                                interrupt on single click events on the
-                                x/y/z axis.
- - st,click-double-{x,y,z}:     if present, tells the device to issue an
-                                interrupt on double click events on the
-                                x/y/z axis.
- - st,click-thresh-{x,y,z}:     set the x/y/z axis threshold
- - st,click-click-time-limit:   click time limit, from 0 to 127.5msec
-                                with step of 0.5 msec
- - st,click-latency:            click latency, from 0 to 255 msec with
-                                step of 1 msec.
- - st,click-window:             click window, from 0 to 255 msec with
-                                step of 1 msec.
- - st,irq{1,2}-disable:         disable IRQ 1/2
- - st,irq{1,2}-ff-wu-1:         raise IRQ 1/2 on FF_WU_1 condition
- - st,irq{1,2}-ff-wu-2:         raise IRQ 1/2 on FF_WU_2 condition
- - st,irq{1,2}-data-ready:      raise IRQ 1/2 on data ready contition
- - st,irq{1,2}-click:           raise IRQ 1/2 on click condition
- - st,irq-open-drain:           consider IRQ lines open-drain
- - st,irq-active-low:           make IRQ lines active low
- - st,wu-duration-1:            duration register for Free-Fall/Wake-Up
-                                interrupt 1
- - st,wu-duration-2:            duration register for Free-Fall/Wake-Up
-                                interrupt 2
- - st,wakeup-{x,y,z}-{lo,hi}:   set wakeup condition on x/y/z axis for
-                                upper/lower limit
- - st,highpass-cutoff-hz=:      1, 2, 4 or 8 for 1Hz, 2Hz, 4Hz or 8Hz of
-                                highpass cut-off frequency
- - st,hipass{1,2}-disable:      disable highpass 1/2.
- - st,default-rate=:            set the default rate
- - st,axis-{x,y,z}=:            set the axis to map to the three coordinates
- - st,{min,max}-limit-{x,y,z}   set the min/max limits for x/y/z axis
-                                (used by self-test)
-
-
-Example for a SPI device node:
-
-        lis302@0 {
-                compatible = "st,lis302dl-spi";
-                reg = <0>;
-                spi-max-frequency = <1000000>;
-                interrupt-parent = <&gpio>;
-                interrupts = <104 0>;
-
-                st,click-single-x;
-                st,click-single-y;
-                st,click-single-z;
-                st,click-thresh-x = <10>;
-                st,click-thresh-y = <10>;
-                st,click-thresh-z = <10>;
-                st,irq1-click;
-                st,irq2-click;
-                st,wakeup-x-lo;
-                st,wakeup-x-hi;
-                st,wakeup-y-lo;
-                st,wakeup-y-hi;
-                st,wakeup-z-lo;
-                st,wakeup-z-hi;
-        };
-
-Example for a I2C device node:
-
-        lis331dlh: lis331dlh@18 {
-                compatible = "st,lis331dlh", "st,lis3lv02d";
-                reg = <0x18>;
-                Vdd-supply = <&lis3_reg>;
-                Vdd_IO-supply = <&lis3_reg>;
-
-                st,click-single-x;
-                st,click-single-y;
-                st,click-single-z;
-                st,click-thresh-x = <10>;
-                st,click-thresh-y = <10>;
-                st,click-thresh-z = <10>;
-                st,irq1-click;
-                st,irq2-click;
-                st,wakeup-x-lo;
-                st,wakeup-x-hi;
-                st,wakeup-y-lo;
-                st,wakeup-y-hi;
-                st,wakeup-z-lo;
-                st,wakeup-z-hi;
-                st,min-limit-x = <120>;
-                st,min-limit-y = <120>;
-                st,min-limit-z = <140>;
-                st,max-limit-x = <550>;
-                st,max-limit-y = <550>;
-                st,max-limit-z = <750>;
-        };
-
diff --git a/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt b/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt
deleted file mode 100644
index 0a85c70cd30..00000000000
--- a/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt
+++ /dev/null
@@ -1,68 +0,0 @@
-* Atmel High Speed MultiMedia Card Interface
-
-This controller on atmel products provides an interface for MMC, SD and SDIO
-types of memory cards.
-
-This file documents differences between the core properties described
-by mmc.txt and the properties used by the atmel-mci driver.
-
-1) MCI node
-
-Required properties:
-- compatible: should be "atmel,hsmci"
-- #address-cells: should be one. The cell is the slot id.
-- #size-cells: should be zero.
-- at least one slot node
-
-The node contains child nodes for each slot that the platform uses
-
-Example MCI node:
-
-mmc0: mmc@f0008000 {
-        compatible = "atmel,hsmci";
-        reg = <0xf0008000 0x600>;
-        interrupts = <12 4>;
-        #address-cells = <1>;
-        #size-cells = <0>;
-
-        [ child node definitions...]
-};
-
-2) slot nodes
-
-Required properties:
-- reg: should contain the slot id.
-- bus-width: number of data lines connected to the controller
-
-Optional properties:
-- cd-gpios: specify GPIOs for card detection
-- cd-inverted: invert the value of external card detect gpio line
-- wp-gpios: specify GPIOs for write protection
-
-Example slot node:
-
-slot@0 {
-        reg = <0>;
-        bus-width = <4>;
-        cd-gpios = <&pioD 15 0>
-        cd-inverted;
-};
-
-Example full MCI node:
-mmc0: mmc@f0008000 {
-        compatible = "atmel,hsmci";
-        reg = <0xf0008000 0x600>;
-        interrupts = <12 4>;
-        #address-cells = <1>;
-        #size-cells = <0>;
-        slot@0 {
-                reg = <0>;
-                bus-width = <4>;
-                cd-gpios = <&pioD 15 0>
-                cd-inverted;
-        };
-        slot@1 {
-                reg = <1>;
-                bus-width = <4>;
-        };
-};
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
deleted file mode 100644
index 79276895333..00000000000
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ /dev/null
@@ -1,87 +0,0 @@
-* Samsung Exynos specific extensions to the Synopsis Designware Mobile
-  Storage Host Controller
-
-The Synopsis designware mobile storage host controller is used to interface
-a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
-differences between the core Synopsis dw mshc controller properties described
-by synposis-dw-mshc.txt and the properties used by the Samsung Exynos specific
-extensions to the Synopsis Designware Mobile Storage Host Controller.
-
-Required Properties:
-
-* compatible: should be
-        - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
-          specific extentions.
-        - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
-          specific extentions.
-        - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
-          specific extentions.
-
-* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
-  unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
-  ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7.
-
-* samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
-  in transmit mode and CIU clock phase shift value in receive mode for single
-  data rate mode operation. Refer notes below for the order of the cells and the
-  valid values.
-
-* samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
-  in transmit mode and CIU clock phase shift value in receive mode for double
-  data rate mode operation. Refer notes below for the order of the cells and the
-  valid values.
-
-  Notes for the sdr-timing and ddr-timing values:
-
-    The order of the cells should be
-      - First Cell: CIU clock phase shift value for tx mode.
-      - Second Cell: CIU clock phase shift value for rx mode.
-
-    Valid values for SDR and DDR CIU clock timing for Exynos5250:
-      - valid value for tx phase shift and rx phase shift is 0 to 7.
-      - when CIU clock divider value is set to 3, all possible 8 phase shift
-        values can be used.
-      - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
-        phase shift clocks should be 0.
-
-Required properties for a slot:
-
-* gpios: specifies a list of gpios used for command, clock and data bus. The
-  first gpio is the command line and the second gpio is the clock line. The
-  rest of the gpios (depending on the bus-width property) are the data lines in
-  no particular order. The format of the gpio specifier depends on the gpio
-  controller.
-
-Example:
-
-  The MSHC controller node can be split into two portions, SoC specific and
-  board specific portions as listed below.
-
-        dwmmc0@12200000 {
-                compatible = "samsung,exynos5250-dw-mshc";
-                reg = <0x12200000 0x1000>;
-                interrupts = <0 75 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-        };
-
-        dwmmc0@12200000 {
-                num-slots = <1>;
-                supports-highspeed;
-                broken-cd;
-                fifo-depth = <0x80>;
-                card-detect-delay = <200>;
-                samsung,dw-mshc-ciu-div = <3>;
-                samsung,dw-mshc-sdr-timing = <2 3>;
-                samsung,dw-mshc-ddr-timing = <1 2>;
-
-                slot@0 {
-                        reg = <0>;
-                        bus-width = <8>;
-                        gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
-                                <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
-                                <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,
-                                <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
-                                <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;
-                };
-        };
diff --git a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
index bd9be0b5bc2..64bcb8be973 100644
--- a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
+++ b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
@@ -3,22 +3,19 @@
 The Enhanced Secure Digital Host Controller provides an interface
 for MMC, SD, and SDIO types of memory cards.
 
-This file documents differences between the core properties described
-by mmc.txt and the properties used by the sdhci-esdhc driver.
-
 Required properties:
+  - compatible : should be
+    "fsl,<chip>-esdhc", "fsl,esdhc"
+  - reg : should contain eSDHC registers location and length.
+  - interrupts : should contain eSDHC interrupt.
   - interrupt-parent : interrupt source phandle.
   - clock-frequency : specifies eSDHC base clock frequency.
-
-Optional properties:
-  - sdhci,wp-inverted : specifies that eSDHC controller reports
-    inverted write-protect state; New devices should use the generic
-    "wp-inverted" property.
-  - sdhci,1-bit-only : specifies that a controller can only handle
-    1-bit data transfers. New devices should use the generic
-    "bus-width = <1>" property.
-  - sdhci,auto-cmd12: specifies that a controller can only handle auto
-    CMD12.
+  - sdhci,wp-inverted : (optional) specifies that eSDHC controller
+    reports inverted write-protect state;
+  - sdhci,1-bit-only : (optional) specifies that a controller can
+    only handle 1-bit data transfers.
+  - sdhci,auto-cmd12: (optional) specifies that a controller can
+    only handle auto CMD12.
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
index 1dd622546d0..ab22fe6e73a 100644
--- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
+++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
@@ -3,15 +3,17 @@
 The Enhanced Secure Digital Host Controller on Freescale i.MX family
 provides an interface for MMC, SD, and SDIO types of memory cards.
 
-This file documents differences between the core properties described
-by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
-
 Required properties:
 - compatible : Should be "fsl,<chip>-esdhc"
+- reg : Should contain eSDHC registers location and length
+- interrupts : Should contain eSDHC interrupt
 
 Optional properties:
-- fsl,cd-controller : Indicate to use controller internal card detection
-- fsl,wp-controller : Indicate to use controller internal write protection
+- fsl,card-wired : Indicate the card is wired to host permanently
+- fsl,cd-internal : Indicate to use controller internal card detection
+- fsl,wp-internal : Indicate to use controller internal write protection
+- cd-gpios : Specify GPIOs for card detection
+- wp-gpios : Specify GPIOs for write protection
 
 Examples:
 
@@ -19,14 +21,14 @@ esdhc@70004000 {
         compatible = "fsl,imx51-esdhc";
         reg = <0x70004000 0x4000>;
         interrupts = <1>;
-        fsl,cd-controller;
-        fsl,wp-controller;
+        fsl,cd-internal;
+        fsl,wp-internal;
 };
 
 esdhc@70008000 {
         compatible = "fsl,imx51-esdhc";
         reg = <0x70008000 0x4000>;
         interrupts = <2>;
-        cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */
-        wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */
+        cd-gpios = <&gpio0 6 0>; /* GPIO1_6 */
+        wp-gpios = <&gpio0 5 0>; /* GPIO1_5 */
 };
diff --git a/Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt b/Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt
index 0e5e2ec4001..89a0084df2f 100644
--- a/Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt
+++ b/Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt
@@ -1,9 +1,8 @@
 MMC/SD/SDIO slot directly connected to a SPI bus
 
-This file documents differences between the core properties described
-by mmc.txt and the properties used by the mmc_spi driver.
-
 Required properties:
+- compatible : should be "mmc-spi-slot".
+- reg : should specify SPI address (chip-select number).
 - spi-max-frequency : maximum frequency for this device (Hz).
 - voltage-ranges : two cells are required, first cell specifies minimum
   slot voltage (mV), second cell specifies maximum slot voltage (mV).
@@ -11,8 +10,8 @@ Required properties:
 
 Optional properties:
 - gpios : may specify GPIOs in this order: Card-Detect GPIO,
-  Write-Protect GPIO. Note that this does not follow the
-  binding from mmc.txt, for historical reasons.
+  Write-Protect GPIO.
+- interrupts : the interrupt of a card detect interrupt.
 - interrupt-parent : the phandle for the interrupt controller that
   services interrupts for this device.
 
diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt b/Documentation/devicetree/bindings/mmc/mmc.txt
deleted file mode 100644
index a591c6741d7..00000000000
--- a/Documentation/devicetree/bindings/mmc/mmc.txt
+++ /dev/null
@@ -1,44 +0,0 @@
-These properties are common to multiple MMC host controllers. Any host
-that requires the respective functionality should implement them using
-these definitions.
-
-Interpreted by the OF core:
-- reg: Registers location and length.
-- interrupts: Interrupts used by the MMC controller.
-
-Required properties:
-- bus-width: Number of data lines, can be <1>, <4>, or <8>
-
-Card detection:
-If no property below is supplied, standard SDHCI card detect is used.
-Only one of the properties in this section should be supplied:
-  - broken-cd: There is no card detection available; polling must be used.
-  - cd-gpios: Specify GPIOs for card detection, see gpio binding
-  - non-removable: non-removable slot (like eMMC); assume always present.
-
-Optional properties:
-- wp-gpios: Specify GPIOs for write protection, see gpio binding
-- cd-inverted: when present, polarity on the cd gpio line is inverted
-- wp-inverted: when present, polarity on the wp gpio line is inverted
-- max-frequency: maximum operating clock frequency
-- no-1-8-v: when present, denotes that 1.8v card voltage is not supported on
-  this system, even if the controller claims it is.
-
-Optional SDIO properties:
-- keep-power-in-suspend: Preserves card power during a suspend/resume cycle
-- enable-sdio-wakeup: Enables wake up of host system on SDIO IRQ assertion
-
-Example:
-
-sdhci@ab000000 {
-        compatible = "sdhci";
-        reg = <0xab000000 0x200>;
-        interrupts = <23>;
-        bus-width = <4>;
-        cd-gpios = <&gpio 69 0>;
-        cd-inverted;
-        wp-gpios = <&gpio 70 0>;
-        max-frequency = <50000000>;
-        keep-power-in-suspend;
-        enable-sdio-wakeup;
-}
diff --git a/Documentation/devicetree/bindings/mmc/mmci.txt b/Documentation/devicetree/bindings/mmc/mmci.txt
deleted file mode 100644
index 2b584cae352..00000000000
--- a/Documentation/devicetree/bindings/mmc/mmci.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-* ARM PrimeCell MultiMedia Card Interface (MMCI) PL180/1
-
-The ARM PrimeCell MMCI PL180 and PL181 provides an interface for
-reading and writing to MultiMedia and SD cards alike.
-
-This file documents differences between the core properties described
-by mmc.txt and the properties used by the mmci driver.
-
-Required properties:
-- compatible             : contains "arm,pl18x", "arm,primecell".
-- arm,primecell-periphid : contains the PrimeCell Peripheral ID.
-
-Optional properties:
-- mmc-cap-mmc-highspeed  : indicates whether MMC is high speed capable
-- mmc-cap-sd-highspeed   : indicates whether SD is high speed capable
diff --git a/Documentation/devicetree/bindings/mmc/mxs-mmc.txt b/Documentation/devicetree/bindings/mmc/mxs-mmc.txt
deleted file mode 100644
index 54949f6faed..00000000000
--- a/Documentation/devicetree/bindings/mmc/mxs-mmc.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-* Freescale MXS MMC controller
-
-The Freescale MXS Synchronous Serial Ports (SSP) can act as a MMC controller
-to support MMC, SD, and SDIO types of memory cards.
-
-This file documents differences between the core properties in mmc.txt
-and the properties used by the mxsmmc driver.
-
-Required properties:
-- compatible: Should be "fsl,<chip>-mmc".  The supported chips include
-  imx23 and imx28.
-- interrupts: Should contain ERROR and DMA interrupts
-- fsl,ssp-dma-channel: APBH DMA channel for the SSP
-
-Examples:
-
-ssp0: ssp@80010000 {
-        compatible = "fsl,imx28-mmc";
-        reg = <0x80010000 2000>;
-        interrupts = <96 82>;
-        fsl,ssp-dma-channel = <0>;
-        bus-width = <8>;
-};
diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
deleted file mode 100644
index c6d7b11db9e..00000000000
--- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-* NVIDIA Tegra Secure Digital Host Controller
-
-This controller on Tegra family SoCs provides an interface for MMC, SD,
-and SDIO types of memory cards.
-
-This file documents differences between the core properties described
-by mmc.txt and the properties used by the sdhci-tegra driver.
-
-Required properties:
-- compatible : Should be "nvidia,<chip>-sdhci"
-
-Optional properties:
-- power-gpios : Specify GPIOs for power control
-
-Example:
-
-sdhci@c8000200 {
-        compatible = "nvidia,tegra20-sdhci";
-        reg = <0xc8000200 0x200>;
-        interrupts = <47>;
-        cd-gpios = <&gpio 69 0>; /* gpio PI5 */
-        wp-gpios = <&gpio 57 0>; /* gpio PH1 */
-        power-gpios = <&gpio 155 0>; /* gpio PT3 */
-        bus-width = <8>;
-};
diff --git a/Documentation/devicetree/bindings/mmc/pxa-mmc.txt b/Documentation/devicetree/bindings/mmc/pxa-mmc.txt
deleted file mode 100644
index b7025de7dce..00000000000
--- a/Documentation/devicetree/bindings/mmc/pxa-mmc.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-* PXA MMC drivers
-
-Driver bindings for the PXA MCI (MMC/SDIO) interfaces
-
-Required properties:
-- compatible: Should be "marvell,pxa-mmc".
-- vmmc-supply: A regulator for VMMC
-
-Optional properties:
-- marvell,detect-delay-ms: sets the detection delay timeout in ms.
-- marvell,gpio-power: GPIO spec for the card power enable pin
-
-This file documents differences between the core properties in mmc.txt
-and the properties used by the pxa-mmc driver.
-
-Examples:
-
-mmc0: mmc@41100000 {
-        compatible = "marvell,pxa-mmc";
-        reg = <0x41100000 0x1000>;
-        interrupts = <23>;
-        cd-gpios = <&gpio 23 0>;
-        wp-gpios = <&gpio 24 0>;
-};
-
diff --git a/Documentation/devicetree/bindings/mmc/samsung-sdhci.txt b/Documentation/devicetree/bindings/mmc/samsung-sdhci.txt
deleted file mode 100644
index 97e9e315400..00000000000
--- a/Documentation/devicetree/bindings/mmc/samsung-sdhci.txt
+++ /dev/null
@@ -1,59 +0,0 @@
-* Samsung's SDHCI Controller device tree bindings
-
-Samsung's SDHCI controller is used as a connectivity interface with external
-MMC, SD and eMMC storage mediums. This file documents differences between the
-core mmc properties described by mmc.txt and the properties used by the
-Samsung implmentation of the SDHCI controller.
-
-Note: The mmc core bindings documentation states that if none of the core
-card-detect bindings are used, then the standard sdhci card detect mechanism
-is used. The Samsung's SDHCI controller bindings extends this as listed below.
-
-[A] The property "samsung,cd-pinmux-gpio" can be used as stated in the
-    "Optional Board Specific Properties" section below.
-
-Required SoC Specific Properties:
-- compatible: should be one of the following
-  - "samsung,s3c6410-sdhci": For controllers compatible with s3c6410 sdhci
-    controller.
-  - "samsung,exynos4210-sdhci": For controllers compatible with Exynos4 sdhci
-    controller.
-
-Required Board Specific Properties:
-- Samsung GPIO variant (will be completely replaced by pinctrl):
-  - gpios: Should specify the gpios used for clock, command and data lines. The
-    gpio specifier format depends on the gpio controller.
-- Pinctrl variant (preferred if available):
-  - pinctrl-0: Should specify pin control groups used for this controller.
-  - pinctrl-names: Should contain only one value - "default".
-
-Optional Board Specific Properties:
-- samsung,cd-pinmux-gpio: Specifies the card detect line that is routed
-  through a pinmux to the card-detect pin of the card slot. This property
-  should be used only if none of the mmc core card-detect properties are
-  used. Only for Samsung GPIO variant.
-
-Example:
-        sdhci@12530000 {
-                compatible = "samsung,exynos4210-sdhci";
-                reg = <0x12530000 0x100>;
-                interrupts = <0 75 0>;
-                bus-width = <4>;
-                cd-gpios = <&gpk2 2 2 3 3>;
-
-                /* Samsung GPIO variant */
-                gpios = <&gpk2 0 2 0 3>,  /* clock line */
-                        <&gpk2 1 2 0 3>,  /* command line */
-                        <&gpk2 3 2 3 3>,  /* data line 0 */
-                        <&gpk2 4 2 3 3>,  /* data line 1 */
-                        <&gpk2 5 2 3 3>,  /* data line 2 */
-                        <&gpk2 6 2 3 3>;  /* data line 3 */
-
-                /* Pinctrl variant */
-                pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>;
-                pinctrl-names = "default";
-        };
-
-        Note: This example shows both SoC specific and board specific properties
-        in a single device node. The properties can be actually be seperated
-        into SoC specific node and board specific node.
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-dove.txt b/Documentation/devicetree/bindings/mmc/sdhci-dove.txt
deleted file mode 100644
index ae9aab9abcd..00000000000
--- a/Documentation/devicetree/bindings/mmc/sdhci-dove.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-* Marvell sdhci-dove controller
-
-This file documents differences between the core properties in mmc.txt
-and the properties used by the sdhci-pxav2 and sdhci-pxav3 drivers.
-
-- compatible: Should be "marvell,dove-sdhci".
-
-Example:
-
-sdio0: sdio@92000 {
-        compatible = "marvell,dove-sdhci";
-        reg = <0x92000 0x100>;
-        interrupts = <35>;
-};
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt b/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt
deleted file mode 100644
index dbe98a3c183..00000000000
--- a/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-* Marvell sdhci-pxa v2/v3 controller
-
-This file documents differences between the core properties in mmc.txt
-and the properties used by the sdhci-pxav2 and sdhci-pxav3 drivers.
-
-Required properties:
-- compatible: Should be "mrvl,pxav2-mmc" or "mrvl,pxav3-mmc".
-
-Optional properties:
-- mrvl,clk-delay-cycles: Specify a number of cycles to delay for tuning.
-
-Example:
-
-sdhci@d4280800 {
-        compatible = "mrvl,pxav3-mmc";
-        reg = <0xd4280800 0x800>;
-        bus-width = <8>;
-        interrupts = <27>;
-        non-removable;
-        mrvl,clk-delay-cycles = <31>;
-};
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-spear.txt b/Documentation/devicetree/bindings/mmc/sdhci-spear.txt
deleted file mode 100644
index fd3643e7e46..00000000000
--- a/Documentation/devicetree/bindings/mmc/sdhci-spear.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-* SPEAr SDHCI Controller
-
-This file documents differences between the core properties in mmc.txt
-and the properties used by the sdhci-spear driver.
-
-Required properties:
-- compatible: "st,spear300-sdhci"
-
-Optional properties:
-- cd-gpios: card detect gpio, with zero flags.
-
-Example:
-
-        sdhci@fc000000 {
-                compatible = "st,spear300-sdhci";
-                reg = <0xfc000000 0x1000>;
-                cd-gpios = <&gpio0 6 0>;
-        };
diff --git a/Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt
deleted file mode 100644
index 06cd32d0805..00000000000
--- a/Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt
+++ /dev/null
@@ -1,79 +0,0 @@
-* Synopsis Designware Mobile Storage Host Controller
-
-The Synopsis designware mobile storage host controller is used to interface
-a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
-differences between the core mmc properties described by mmc.txt and the
-properties used by the Synopsis Designware Mobile Storage Host Controller.
-
-Required Properties:
-
-* compatible: should be
-        - snps,dw-mshc: for controllers compliant with synopsis dw-mshc.
-* #address-cells: should be 1.
-* #size-cells: should be 0.
-
-# Slots: The slot specific information are contained within child-nodes with
-  each child-node representing a supported slot. There should be atleast one
-  child node representing a card slot. The name of the child node representing
-  the slot is recommended to be slot@n where n is the unique number of the slot
-  connnected to the controller. The following are optional properties which
-  can be included in the slot child node.
-
-        * reg: specifies the physical slot number. The valid values of this
-          property is 0 to (num-slots -1), where num-slots is the value
-          specified by the num-slots property.
-
-        * bus-width: as documented in mmc core bindings.
-
-        * wp-gpios: specifies the write protect gpio line. The format of the
-          gpio specifier depends on the gpio controller. If the write-protect
-          line is not available, this property is optional.
-
-Optional properties:
-
-* num-slots: specifies the number of slots supported by the controller.
-  The number of physical slots actually used could be equal or less than the
-  value specified by num-slots. If this property is not specified, the value
-  of num-slot property is assumed to be 1.
-
-* fifo-depth: The maximum size of the tx/rx fifo's. If this property is not
-  specified, the default value of the fifo size is determined from the
-  controller registers.
-
-* card-detect-delay: Delay in milli-seconds before detecting card after card
-  insert event. The default value is 0.
-
-* supports-highspeed: Enables support for high speed cards (upto 50MHz)
-
-* broken-cd: as documented in mmc core bindings.
-
-Aliases:
-
-- All the MSHC controller nodes should be represented in the aliases node using
-  the following format 'mshc{n}' where n is a unique number for the alias.
-
-Example:
-
-The MSHC controller node can be split into two portions, SoC specific and
-board specific portions as listed below.
-
-        dwmmc0@12200000 {
-                compatible = "snps,dw-mshc";
-                reg = <0x12200000 0x1000>;
-                interrupts = <0 75 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-        };
-
-        dwmmc0@12200000 {
-                num-slots = <1>;
-                supports-highspeed;
-                broken-cd;
-                fifo-depth = <0x80>;
-                card-detect-delay = <200>;
-
-                slot@0 {
-                        reg = <0>;
-                        bus-width = <8>;
-                };
-        };
diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
deleted file mode 100644
index ed271fc255b..00000000000
--- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-* TI Highspeed MMC host controller for OMAP
-
-The Highspeed MMC Host Controller on TI OMAP family
-provides an interface for MMC, SD, and SDIO types of memory cards.
-
-This file documents differences between the core properties described
-by mmc.txt and the properties used by the omap_hsmmc driver.
-
-Required properties:
-- compatible:
- Should be "ti,omap2-hsmmc", for OMAP2 controllers
- Should be "ti,omap3-hsmmc", for OMAP3 controllers
- Should be "ti,omap4-hsmmc", for OMAP4 controllers
-- ti,hwmods: Must be "mmc<n>", n is controller instance starting 1
-
-Optional properties:
-ti,dual-volt: boolean, supports dual voltage cards
-<supply-name>-supply: phandle to the regulator device tree node
-"supply-name" examples are "vmmc", "vmmc_aux" etc
-ti,non-removable: non-removable slot (like eMMC)
-ti,needs-special-reset: Requires a special softreset sequence
-ti,needs-special-hs-handling: HSMMC IP needs special setting for handling High Speed
-
-Example:
-        mmc1: mmc@0x4809c000 {
-                compatible = "ti,omap4-hsmmc";
-                reg = <0x4809c000 0x400>;
-                ti,hwmods = "mmc1";
-                ti,dual-volt;
-                bus-width = <4>;
-                vmmc-supply = <&vmmc>; /* phandle to regulator node */
-                ti,non-removable;
-        };
diff --git a/Documentation/devicetree/bindings/mmc/vt8500-sdmmc.txt b/Documentation/devicetree/bindings/mmc/vt8500-sdmmc.txt
deleted file mode 100644
index d7fb6abb3eb..00000000000
--- a/Documentation/devicetree/bindings/mmc/vt8500-sdmmc.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-* Wondermedia WM8505/WM8650 SD/MMC Host Controller
-
-This file documents differences between the core properties described
-by mmc.txt and the properties used by the wmt-sdmmc driver.
-
-Required properties:
-- compatible: Should be "wm,wm8505-sdhc".
-- interrupts: Two interrupts are required - regular irq and dma irq.
-
-Optional properties:
-- sdon-inverted: SD_ON bit is inverted on the controller
-
-Examples:
-
-sdhc@d800a000 {
-        compatible = "wm,wm8505-sdhc";
-        reg = <0xd800a000 0x1000>;
-        interrupts = <20 21>;
-        clocks = <&sdhc>;
-        bus-width = <4>;
-        sdon-inverted;
-};
-
diff --git a/Documentation/devicetree/bindings/mtd/arm-versatile.txt b/Documentation/devicetree/bindings/mtd/arm-versatile.txt
index beace4b89da..476845db94d 100644
--- a/Documentation/devicetree/bindings/mtd/arm-versatile.txt
+++ b/Documentation/devicetree/bindings/mtd/arm-versatile.txt
@@ -4,5 +4,5 @@ Required properties:
 - compatible : must be "arm,versatile-flash";
 - bank-width : width in bytes of flash interface.
 
-The device tree may optionally contain sub-nodes describing partitions of the
-address space. See partition.txt for more detail.
+Optional properties:
+- Subnode partition map from mtd flash binding
diff --git a/Documentation/devicetree/bindings/mtd/atmel-dataflash.txt b/Documentation/devicetree/bindings/mtd/atmel-dataflash.txt
deleted file mode 100644
index 1889a4db5b7..00000000000
--- a/Documentation/devicetree/bindings/mtd/atmel-dataflash.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-* Atmel Data Flash
-
-Required properties:
-- compatible : "atmel,<model>", "atmel,<series>", "atmel,dataflash".
-
-The device tree may optionally contain sub-nodes describing partitions of the
-address space. See partition.txt for more detail.
-
-Example:
-
-flash@1 {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
-        spi-max-frequency = <25000000>;
-        reg = <1>;
-};
diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
deleted file mode 100644
index d555421ea49..00000000000
--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+++ /dev/null
@@ -1,79 +0,0 @@
-Atmel NAND flash
-
-Required properties:
-- compatible : "atmel,at91rm9200-nand".
-- reg : should specify localbus address and size used for the chip,
-        and hardware ECC controller if available.
-        If the hardware ECC is PMECC, it should contain address and size for
-        PMECC, PMECC Error Location controller and ROM which has lookup tables.
-- atmel,nand-addr-offset : offset for the address latch.
-- atmel,nand-cmd-offset : offset for the command latch.
-- #address-cells, #size-cells : Must be present if the device has sub-nodes
-  representing partitions.
-
-- gpios : specifies the gpio pins to control the NAND device. detect is an
-  optional gpio and may be set to 0 if not present.
-
-Optional properties:
-- nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default.
-  Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
-  "soft_bch".
-- atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware.
-  Only supported by at91sam9x5 or later sam9 product.
-- atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
-  Controller. Supported values are: 2, 4, 8, 12, 24.
-- atmel,pmecc-sector-size : sector size for ECC computation. Supported values
-  are: 512, 1024.
-- atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM
-  for different sector size. First one is for sector size 512, the next is for
-  sector size 1024.
-- nand-bus-width : 8 or 16 bus width if not present 8
-- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
-
-Examples:
-nand0: nand@40000000,0 {
-        compatible = "atmel,at91rm9200-nand";
-        #address-cells = <1>;
-        #size-cells = <1>;
-        reg = <0x40000000 0x10000000
-               0xffffe800 0x200
-              >;
-        atmel,nand-addr-offset = <21>;  /* ale */
-        atmel,nand-cmd-offset = <22>;   /* cle */
-        nand-on-flash-bbt;
-        nand-ecc-mode = "soft";
-        gpios = <&pioC 13 0     /* rdy */
-                 &pioC 14 0     /* nce */
-                 0              /* cd */
-                >;
-        partition@0 {
-                ...
-        };
-};
-
-/* for PMECC supported chips */
-nand0: nand@40000000 {
-        compatible = "atmel,at91rm9200-nand";
-        #address-cells = <1>;
-        #size-cells = <1>;
-        reg = < 0x40000000 0x10000000   /* bus addr & size */
-                0xffffe000 0x00000600   /* PMECC addr & size */
-                0xffffe600 0x00000200   /* PMECC ERRLOC addr & size */
-                0x00100000 0x00100000   /* ROM addr & size */
-                >;
-        atmel,nand-addr-offset = <21>;  /* ale */
-        atmel,nand-cmd-offset = <22>;   /* cle */
-        nand-on-flash-bbt;
-        nand-ecc-mode = "hw";
-        atmel,has-pmecc;        /* enable PMECC */
-        atmel,pmecc-cap = <2>;
-        atmel,pmecc-sector-size = <512>;
-        atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
-        gpios = <&pioD 5 0      /* rdy */
-                 &pioD 4 0      /* nce */
-                 0              /* cd */
-                >;
-        partition@0 {
-                ...
-        };
-};
diff --git a/Documentation/devicetree/bindings/mtd/denali-nand.txt b/Documentation/devicetree/bindings/mtd/denali-nand.txt
deleted file mode 100644
index b04d03a1d49..00000000000
--- a/Documentation/devicetree/bindings/mtd/denali-nand.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-* Denali NAND controller
-
-Required properties:
-  - compatible : should be "denali,denali-nand-dt"
-  - reg : should contain registers location and length for data and reg.
-  - reg-names: Should contain the reg names "nand_data" and "denali_reg"
-  - interrupts : The interrupt number.
-  - dm-mask : DMA bit mask
-
-The device tree may optionally contain sub-nodes describing partitions of the
-address space. See partition.txt for more detail.
-
-Examples:
-
-nand: nand@ff900000 {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        compatible = "denali,denali-nand-dt";
-        reg = <0xff900000 0x100000>, <0xffb80000 0x10000>;
-        reg-names = "nand_data", "denali_reg";
-        interrupts = <0 144 4>;
-        dma-mask = <0xffffffff>;
-};
diff --git a/Documentation/devicetree/bindings/mtd/flctl-nand.txt b/Documentation/devicetree/bindings/mtd/flctl-nand.txt
deleted file mode 100644
index 427f46dc60a..00000000000
--- a/Documentation/devicetree/bindings/mtd/flctl-nand.txt
+++ /dev/null
@@ -1,49 +0,0 @@
-FLCTL NAND controller
-
-Required properties:
-- compatible : "renesas,shmobile-flctl-sh7372"
-- reg : Address range of the FLCTL
-- interrupts : flste IRQ number
-- nand-bus-width : bus width to NAND chip
-
-Optional properties:
-- dmas: DMA specifier(s)
-- dma-names: name for each DMA specifier. Valid names are
-             "data_tx", "data_rx", "ecc_tx", "ecc_rx"
-
-The DMA fields are not used yet in the driver but are listed here for
-completing the bindings.
-
-The device tree may optionally contain sub-nodes describing partitions of the
-address space. See partition.txt for more detail.
-
-Example:
-
-        flctl@e6a30000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "renesas,shmobile-flctl-sh7372";
-                reg = <0xe6a30000 0x100>;
-                interrupts = <0x0d80>;
-
-                nand-bus-width = <16>;
-
-                dmas = <&dmac 1 /* data_tx */
-                        &dmac 2;> /* data_rx */
-                dma-names = "data_tx", "data_rx";
-
-                system@0 {
-                        label = "system";
-                        reg = <0x0 0x8000000>;
-                };
-
-                userdata@8000000 {
-                        label = "userdata";
-                        reg = <0x8000000 0x10000000>;
-                };
-
-                cache@18000000 {
-                        label = "cache";
-                        reg = <0x18000000 0x8000000>;
-                };
-        };
diff --git a/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt b/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt
index fce4894f5a9..00f1f546b32 100644
--- a/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt
@@ -19,10 +19,6 @@ Optional properties:
         read registers (tR). Required if property "gpios" is not used
         (R/B# pins not connected).
 
-Each flash chip described may optionally contain additional sub-nodes
-describing partitions of the address space. See partition.txt for more
-detail.
-
 Examples:
 
 upm@1,0 {
diff --git a/Documentation/devicetree/bindings/mtd/fsmc-nand.txt b/Documentation/devicetree/bindings/mtd/fsmc-nand.txt
deleted file mode 100644
index e3ea32e7de3..00000000000
--- a/Documentation/devicetree/bindings/mtd/fsmc-nand.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-* FSMC NAND
-
-Required properties:
-- compatible : "st,spear600-fsmc-nand"
-- reg : Address range of the mtd chip
-- reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"
-
-Optional properties:
-- bank-width : Width (in bytes) of the device.  If not present, the width
-  defaults to 1 byte
-- nand-skip-bbtscan: Indicates the the BBT scanning should be skipped
-
-Example:
-
-        fsmc: flash@d1800000 {
-                compatible = "st,spear600-fsmc-nand";
-                #address-cells = <1>;
-                #size-cells = <1>;
-                reg = <0xd1800000 0x1000        /* FSMC Register */
-                       0xd2000000 0x0010        /* NAND Base DATA */
-                       0xd2020000 0x0010        /* NAND Base ADDR */
-                       0xd2010000 0x0010>;      /* NAND Base CMD */
-                reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
-
-                bank-width = <1>;
-                nand-skip-bbtscan;
-
-                partition@0 {
-                        ...
-                };
-        };
diff --git a/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt b/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt
deleted file mode 100644
index 36ef07d3c90..00000000000
--- a/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt
+++ /dev/null
@@ -1,47 +0,0 @@
-GPIO assisted NAND flash
-
-The GPIO assisted NAND flash uses a memory mapped interface to
-read/write the NAND commands and data and GPIO pins for the control
-signals.
-
-Required properties:
-- compatible : "gpio-control-nand"
-- reg : should specify localbus chip select and size used for the chip.  The
-  resource describes the data bus connected to the NAND flash and all accesses
-  are made in native endianness.
-- #address-cells, #size-cells : Must be present if the device has sub-nodes
-  representing partitions.
-- gpios : specifies the gpio pins to control the NAND device.  nwp is an
-  optional gpio and may be set to 0 if not present.
-
-Optional properties:
-- bank-width : Width (in bytes) of the device.  If not present, the width
-  defaults to 1 byte.
-- chip-delay : chip dependent delay for transferring data from array to
-  read registers (tR).  If not present then a default of 20us is used.
-- gpio-control-nand,io-sync-reg : A 64-bit physical address for a read
-  location used to guard against bus reordering with regards to accesses to
-  the GPIO's and the NAND flash data bus.  If present, then after changing
-  GPIO state and before and after command byte writes, this register will be
-  read to ensure that the GPIO accesses have completed.
-
-The device tree may optionally contain sub-nodes describing partitions of the
-address space. See partition.txt for more detail.
-
-Examples:
-
-gpio-nand@1,0 {
-        compatible = "gpio-control-nand";
-        reg = <1 0x0000 0x2>;
-        #address-cells = <1>;
-        #size-cells = <1>;
-        gpios = <&banka 1 0     /* rdy */
-                 &banka 2 0     /* nce */
-                 &banka 3 0     /* ale */
-                 &banka 4 0     /* cle */
-                 0              /* nwp */>;
-
-        partition@0 {
-        ...
-        };
-};
diff --git a/Documentation/devicetree/bindings/mtd/gpmi-nand.txt b/Documentation/devicetree/bindings/mtd/gpmi-nand.txt
deleted file mode 100644
index 3fb3f901536..00000000000
--- a/Documentation/devicetree/bindings/mtd/gpmi-nand.txt
+++ /dev/null
@@ -1,37 +0,0 @@
-* Freescale General-Purpose Media Interface (GPMI)
-
-The GPMI nand controller provides an interface to control the
-NAND flash chips. We support only one NAND chip now.
-
-Required properties:
-  - compatible : should be "fsl,<chip>-gpmi-nand"
-  - reg : should contain registers location and length for gpmi and bch.
-  - reg-names: Should contain the reg names "gpmi-nand" and "bch"
-  - interrupts : The first is the DMA interrupt number for GPMI.
-                 The second is the BCH interrupt number.
-  - interrupt-names : The interrupt names "gpmi-dma", "bch";
-  - fsl,gpmi-dma-channel : Should contain the dma channel it uses.
-
-Optional properties:
-  - nand-on-flash-bbt: boolean to enable on flash bbt option if not
-                       present false
-
-The device tree may optionally contain sub-nodes describing partitions of the
-address space. See partition.txt for more detail.
-
-Examples:
-
-gpmi-nand@8000c000 {
-        compatible = "fsl,imx28-gpmi-nand";
-        #address-cells = <1>;
-        #size-cells = <1>;
-        reg = <0x8000c000 2000>, <0x8000a000 2000>;
-        reg-names = "gpmi-nand", "bch";
-        interrupts = <88>, <41>;
-        interrupt-names = "gpmi-dma", "bch";
-        fsl,gpmi-dma-channel = <4>;
-
-        partition@0 {
-        ...
-        };
-};
diff --git a/Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt b/Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt
deleted file mode 100644
index d0a37252eb2..00000000000
--- a/Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-NXP LPC32xx SoC NAND MLC controller
-
-Required properties:
-- compatible: "nxp,lpc3220-mlc"
-- reg: Address and size of the controller
-- interrupts: The NAND interrupt specification
-- gpios: GPIO specification for NAND write protect
-
-The following required properties are very controller specific. See the LPC32xx
-User Manual 7.5.14 MLC NAND Timing Register (the values here are specified in
-Hz, to make them independent of actual clock speed and to provide for good
-accuracy:)
-- nxp,tcea_delay: TCEA_DELAY
-- nxp,busy_delay: BUSY_DELAY
-- nxp,nand_ta: NAND_TA
-- nxp,rd_high: RD_HIGH
-- nxp,rd_low: RD_LOW
-- nxp,wr_high: WR_HIGH
-- nxp,wr_low: WR_LOW
-
-Optional subnodes:
-- Partitions, see Documentation/devicetree/bindings/mtd/partition.txt
-
-Example:
-
-        mlc: flash@200A8000 {
-                compatible = "nxp,lpc3220-mlc";
-                reg = <0x200A8000 0x11000>;
-                interrupts = <11 0>;
-                #address-cells = <1>;
-                #size-cells = <1>;
-
-                nxp,tcea-delay = <333333333>;
-                nxp,busy-delay = <10000000>;
-                nxp,nand-ta = <18181818>;
-                nxp,rd-high = <31250000>;
-                nxp,rd-low = <45454545>;
-                nxp,wr-high = <40000000>;
-                nxp,wr-low = <83333333>;
-                gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
-
-                mtd0@00000000 {
-                        label = "boot";
-                        reg = <0x00000000 0x00064000>;
-                        read-only;
-                };
-
-                ...
-
-        };
diff --git a/Documentation/devicetree/bindings/mtd/lpc32xx-slc.txt b/Documentation/devicetree/bindings/mtd/lpc32xx-slc.txt
deleted file mode 100644
index d94edc0fc55..00000000000
--- a/Documentation/devicetree/bindings/mtd/lpc32xx-slc.txt
+++ /dev/null
@@ -1,52 +0,0 @@
-NXP LPC32xx SoC NAND SLC controller
-
-Required properties:
-- compatible: "nxp,lpc3220-slc"
-- reg: Address and size of the controller
-- nand-on-flash-bbt: Use bad block table on flash
-- gpios: GPIO specification for NAND write protect
-
-The following required properties are very controller specific. See the LPC32xx
-User Manual:
-- nxp,wdr-clks: Delay before Ready signal is tested on write (W_RDY)
-- nxp,rdr-clks: Delay before Ready signal is tested on read (R_RDY)
-(The following values are specified in Hz, to make them independent of actual
-clock speed:)
-- nxp,wwidth: Write pulse width (W_WIDTH)
-- nxp,whold: Write hold time (W_HOLD)
-- nxp,wsetup: Write setup time (W_SETUP)
-- nxp,rwidth: Read pulse width (R_WIDTH)
-- nxp,rhold: Read hold time (R_HOLD)
-- nxp,rsetup: Read setup time (R_SETUP)
-
-Optional subnodes:
-- Partitions, see Documentation/devicetree/bindings/mtd/partition.txt
-
-Example:
-
-        slc: flash@20020000 {
-                compatible = "nxp,lpc3220-slc";
-                reg = <0x20020000 0x1000>;
-                #address-cells = <1>;
-                #size-cells = <1>;
-
-                nxp,wdr-clks = <14>;
-                nxp,wwidth = <40000000>;
-                nxp,whold = <100000000>;
-                nxp,wsetup = <100000000>;
-                nxp,rdr-clks = <14>;
-                nxp,rwidth = <40000000>;
-                nxp,rhold = <66666666>;
-                nxp,rsetup = <100000000>;
-                nand-on-flash-bbt;
-                gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
-
-                mtd0@00000000 {
-                        label = "phy3250-boot";
-                        reg = <0x00000000 0x00064000>;
-                        read-only;
-                };
-
-                ...
-
-        };
diff --git a/Documentation/devicetree/bindings/mtd/m25p80.txt b/Documentation/devicetree/bindings/mtd/m25p80.txt
deleted file mode 100644
index 6d3d5760947..00000000000
--- a/Documentation/devicetree/bindings/mtd/m25p80.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-* MTD SPI driver for ST M25Pxx (and similar) serial flash chips
-
-Required properties:
-- #address-cells, #size-cells : Must be present if the device has sub-nodes
-  representing partitions.
-- compatible : Should be the manufacturer and the name of the chip. Bear in mind
-               the DT binding is not Linux-only, but in case of Linux, see the
-               "m25p_ids" table in drivers/mtd/devices/m25p80.c for the list of
-               supported chips.
-- reg : Chip-Select number
-- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at
-
-Optional properties:
-- m25p,fast-read : Use the "fast read" opcode to read data from the chip instead
-                   of the usual "read" opcode. This opcode is not supported by
-                   all chips and support for it can not be detected at runtime.
-                   Refer to your chips' datasheet to check if this is supported
-                   by your chip.
-
-Example:
-
-        flash: m25p80@0 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "spansion,m25p80";
-                reg = <0>;
-                spi-max-frequency = <40000000>;
-                m25p,fast-read;
-        };
diff --git a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt
index dab7847fc80..80152cb567d 100644
--- a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt
+++ b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt
@@ -16,16 +16,6 @@ file systems on embedded devices.
  - #address-cells, #size-cells : Must be present if the device has
    sub-nodes representing partitions (see below).  In this case
    both #address-cells and #size-cells must be equal to 1.
- - no-unaligned-direct-access: boolean to disable the default direct
-   mapping of the flash.
-   On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause
-   problems with JFFS2 usage, as the local bus (LPB) doesn't support
-   unaligned accesses as implemented in the JFFS2 code via memcpy().
-   By defining "no-unaligned-direct-access", the flash will not be
-   exposed directly to the MTD users (e.g. JFFS2) any more.
- - linux,mtd-name: allow to specify the mtd name for retro capability with
-   physmap-flash drivers as boot loader pass the mtd partition via the old
-   device name physmap-flash.
 
 For JEDEC compatible devices, the following additional properties
 are defined:
@@ -33,8 +23,27 @@ are defined:
  - vendor-id : Contains the flash chip's vendor id (1 byte).
  - device-id : Contains the flash chip's device id (1 byte).
 
-The device tree may optionally contain sub-nodes describing partitions of the
-address space. See partition.txt for more detail.
+In addition to the information on the mtd bank itself, the
+device tree may optionally contain additional information
+describing partitions of the address space.  This can be
+used on platforms which have strong conventions about which
+portions of a flash are used for what purposes, but which don't
+use an on-flash partition table such as RedBoot.
+
+Each partition is represented as a sub-node of the mtd device.
+Each node's name represents the name of the corresponding
+partition of the mtd device.
+
+Flash partitions
+ - reg : The partition's offset and size within the mtd bank.
+ - label : (optional) The label / name for this partition.
+   If omitted, the label is taken from the node name (excluding
+   the unit address).
+ - read-only : (optional) This parameter, if present, is a hint to
+   Linux that this partition should only be mounted
+   read-only.  This is usually used for flash partitions
+   containing early-boot firmware images or data which should not
+   be clobbered.
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/mtd/mxc-nand.txt b/Documentation/devicetree/bindings/mtd/mxc-nand.txt
deleted file mode 100644
index b5833d11c7b..00000000000
--- a/Documentation/devicetree/bindings/mtd/mxc-nand.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-* Freescale's mxc_nand
-
-Required properties:
-- compatible: "fsl,imxXX-nand"
-- reg: address range of the nfc block
-- interrupts: irq to be used
-- nand-bus-width: see nand.txt
-- nand-ecc-mode: see nand.txt
-- nand-on-flash-bbt: see nand.txt
-
-Example:
-
-        nand@d8000000 {
-                compatible = "fsl,imx27-nand";
-                reg = <0xd8000000 0x1000>;
-                interrupts = <29>;
-                nand-bus-width = <8>;
-                nand-ecc-mode = "hw";
-        };
diff --git a/Documentation/devicetree/bindings/mtd/nand.txt b/Documentation/devicetree/bindings/mtd/nand.txt
deleted file mode 100644
index 03855c8c492..00000000000
--- a/Documentation/devicetree/bindings/mtd/nand.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-* MTD generic binding
-
-- nand-ecc-mode : String, operation mode of the NAND ecc mode.
-  Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
-  "soft_bch".
-- nand-bus-width : 8 or 16 bus width if not present 8
-- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
diff --git a/Documentation/devicetree/bindings/mtd/orion-nand.txt b/Documentation/devicetree/bindings/mtd/orion-nand.txt
deleted file mode 100644
index 2d6ab660e60..00000000000
--- a/Documentation/devicetree/bindings/mtd/orion-nand.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-NAND support for Marvell Orion SoC platforms
-
-Required properties:
-- compatible : "marvell,orion-nand".
-- reg : Base physical address of the NAND and length of memory mapped
-        region
-
-Optional properties:
-- cle : Address line number connected to CLE. Default is 0
-- ale : Address line number connected to ALE. Default is 1
-- bank-width : Width in bytes of the device. Default is 1
-- chip-delay : Chip dependent delay for transferring data from array to read
-               registers in usecs
-
-The device tree may optionally contain sub-nodes describing partitions of the
-address space. See partition.txt for more detail.
-
-Example:
-
-nand@f4000000 {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        cle = <0>;
-        ale = <1>;
-        bank-width = <1>;
-        chip-delay = <25>;
-        compatible = "marvell,orion-nand";
-        reg = <0xf4000000 0x400>;
-
-        partition@0 {
-                label = "u-boot";
-                reg = <0x0000000 0x100000>;
-                read-only;
-        };
-
-        partition@100000 {
-                label = "uImage";
-                reg = <0x0100000 0x200000>;
-        };
-
-        partition@300000 {
-                label = "dtb";
-                reg = <0x0300000 0x100000>;
-        };
-
-        partition@400000 {
-                label = "root";
-                reg = <0x0400000 0x7d00000>;
-        };
-};
diff --git a/Documentation/devicetree/bindings/mtd/partition.txt b/Documentation/devicetree/bindings/mtd/partition.txt
deleted file mode 100644
index 6e1f61f1e78..00000000000
--- a/Documentation/devicetree/bindings/mtd/partition.txt
+++ /dev/null
@@ -1,38 +0,0 @@
-Representing flash partitions in devicetree
-
-Partitions can be represented by sub-nodes of an mtd device. This can be used
-on platforms which have strong conventions about which portions of a flash are
-used for what purposes, but which don't use an on-flash partition table such
-as RedBoot.
-
-#address-cells & #size-cells must both be present in the mtd device and be
-equal to 1.
-
-Required properties:
-- reg : The partition's offset and size within the mtd bank.
-
-Optional properties:
-- label : The label / name for this partition.  If omitted, the label is taken
-  from the node name (excluding the unit address).
-- read-only : This parameter, if present, is a hint to Linux that this
-  partition should only be mounted read-only. This is usually used for flash
-  partitions containing early-boot firmware images or data which should not be
-  clobbered.
-
-Examples:
-
-
-flash@0 {
-        #address-cells = <1>;
-        #size-cells = <1>;
-
-        partition@0 {
-                label = "u-boot";
-                reg = <0x0000000 0x100000>;
-                read-only;
-        };
-
-        uimage@100000 {
-                reg = <0x0100000 0x200000>;
-        };
-};
diff --git a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
deleted file mode 100644
index f1421e2bbab..00000000000
--- a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-PXA3xx NAND DT bindings
-
-Required properties:
-
- - compatible:          Should be "marvell,pxa3xx-nand"
- - reg:                 The register base for the controller
- - interrupts:          The interrupt to map
- - #address-cells:      Set to <1> if the node includes partitions
-
-Optional properties:
-
- - marvell,nand-enable-arbiter: Set to enable the bus arbiter
- - marvell,nand-keep-config:    Set to keep the NAND controller config as set
-                                by the bootloader
- - num-cs:                      Number of chipselect lines to usw
-
-Example:
-
-        nand0: nand@43100000 {
-                compatible = "marvell,pxa3xx-nand";
-                reg = <0x43100000 90>;
-                interrupts = <45>;
-                #address-cells = <1>;
-
-                marvell,nand-enable-arbiter;
-                marvell,nand-keep-config;
-                num-cs = <1>;
-
-                /* partitions (optional) */
-        };
-
diff --git a/Documentation/devicetree/bindings/mtd/spear_smi.txt b/Documentation/devicetree/bindings/mtd/spear_smi.txt
deleted file mode 100644
index 7248aadd89e..00000000000
--- a/Documentation/devicetree/bindings/mtd/spear_smi.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-* SPEAr SMI
-
-Required properties:
-- compatible : "st,spear600-smi"
-- reg : Address range of the mtd chip
-- #address-cells, #size-cells : Must be present if the device has sub-nodes
-  representing partitions.
-- interrupt-parent: Should be the phandle for the interrupt controller
-  that services interrupts for this device
-- interrupts: Should contain the STMMAC interrupts
-- clock-rate : Functional clock rate of SMI in Hz
-
-Optional properties:
-- st,smi-fast-mode : Flash supports read in fast mode
-
-Example:
-
-        smi: flash@fc000000 {
-                compatible = "st,spear600-smi";
-                #address-cells = <1>;
-                #size-cells = <1>;
-                reg = <0xfc000000 0x1000>;
-                interrupt-parent = <&vic1>;
-                interrupts = <12>;
-                clock-rate = <50000000>;        /* 50MHz */
-
-                flash@f8000000 {
-                        st,smi-fast-mode;
-                        ...
-                };
-        };
diff --git a/Documentation/devicetree/bindings/net/broadcom-bcm87xx.txt b/Documentation/devicetree/bindings/net/broadcom-bcm87xx.txt
deleted file mode 100644
index 7c86d5e28a0..00000000000
--- a/Documentation/devicetree/bindings/net/broadcom-bcm87xx.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-The Broadcom BCM87XX devices are a family of 10G Ethernet PHYs.  They
-have these bindings in addition to the standard PHY bindings.
-
-Compatible: Should contain "broadcom,bcm8706" or "broadcom,bcm8727" and
-            "ethernet-phy-ieee802.3-c45"
-
-Optional Properties:
-
-- broadcom,c45-reg-init : one of more sets of 4 cells.  The first cell
-  is the MDIO Manageable Device (MMD) address, the second a register
-  address within the MMD, the third cell contains a mask to be ANDed
-  with the existing register value, and the fourth cell is ORed with
-  he result to yield the new register value.  If the third cell has a
-  value of zero, no read of the existing value is performed.
-
-Example:
-
-        ethernet-phy@5 {
-                reg = <5>;
-                compatible = "broadcom,bcm8706", "ethernet-phy-ieee802.3-c45";
-                interrupt-parent = <&gpio>;
-                interrupts = <12 8>; /* Pin 12, active low */
-                /*
-                 * Set PMD Digital Control Register for
-                 * GPIO[1] Tx/Rx
-                 * GPIO[0] R64 Sync Acquired
-                 */
-                broadcom,c45-reg-init = <1 0xc808 0xff8f 0x70>;
-        };
diff --git a/Documentation/devicetree/bindings/net/calxeda-xgmac.txt b/Documentation/devicetree/bindings/net/calxeda-xgmac.txt
deleted file mode 100644
index c8ae996bd8f..00000000000
--- a/Documentation/devicetree/bindings/net/calxeda-xgmac.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-* Calxeda Highbank 10Gb XGMAC Ethernet
-
-Required properties:
-- compatible : Should be "calxeda,hb-xgmac"
-- reg : Address and length of the register set for the device
-- interrupts : Should contain 3 xgmac interrupts. The 1st is main interrupt.
-  The 2nd is pwr mgt interrupt. The 3rd is low power state interrupt.
-
-Optional properties:
-- dma-coherent      : Present if dma operations are coherent
-
-Example:
-
-ethernet@fff50000 {
-        compatible = "calxeda,hb-xgmac";
-        reg = <0xfff50000 0x1000>;
-        interrupts = <0 77 4  0 78 4  0 79 4>;
-};
diff --git a/Documentation/devicetree/bindings/net/can/c_can.txt b/Documentation/devicetree/bindings/net/can/c_can.txt
deleted file mode 100644
index 8f1ae81228e..00000000000
--- a/Documentation/devicetree/bindings/net/can/c_can.txt
+++ /dev/null
@@ -1,49 +0,0 @@
-Bosch C_CAN/D_CAN controller Device Tree Bindings
--------------------------------------------------
-
-Required properties:
-- compatible            : Should be "bosch,c_can" for C_CAN controllers and
-                          "bosch,d_can" for D_CAN controllers.
-- reg                   : physical base address and size of the C_CAN/D_CAN
-                          registers map
-- interrupts            : property with a value describing the interrupt
-                          number
-
-Optional properties:
-- ti,hwmods             : Must be "d_can<n>" or "c_can<n>", n being the
-                          instance number
-
-Note: "ti,hwmods" field is used to fetch the base address and irq
-resources from TI, omap hwmod data base during device registration.
-Future plan is to migrate hwmod data base contents into device tree
-blob so that, all the required data will be used from device tree dts
-file.
-
-Example:
-
-Step1: SoC common .dtsi file
-
-        dcan1: d_can@481d0000 {
-                compatible = "bosch,d_can";
-                reg = <0x481d0000 0x2000>;
-                interrupts = <55>;
-                interrupt-parent = <&intc>;
-                status = "disabled";
-        };
-
-(or)
-
-        dcan1: d_can@481d0000 {
-                compatible = "bosch,d_can";
-                ti,hwmods = "d_can1";
-                reg = <0x481d0000 0x2000>;
-                interrupts = <55>;
-                interrupt-parent = <&intc>;
-                status = "disabled";
-        };
-
-Step 2: board specific .dts file
-
-        &dcan1 {
-                status = "okay";
-        };
diff --git a/Documentation/devicetree/bindings/net/can/cc770.txt b/Documentation/devicetree/bindings/net/can/cc770.txt
deleted file mode 100644
index 77027bf6460..00000000000
--- a/Documentation/devicetree/bindings/net/can/cc770.txt
+++ /dev/null
@@ -1,53 +0,0 @@
-Memory mapped Bosch CC770 and Intel AN82527 CAN controller
-
-Note: The CC770 is a CAN controller from Bosch, which is 100%
-compatible with the old AN82527 from Intel, but with "bugs" being fixed.
-
-Required properties:
-
-- compatible : should be "bosch,cc770" for the CC770 and "intc,82527"
-        for the AN82527.
-
-- reg : should specify the chip select, address offset and size required
-        to map the registers of the controller. The size is usually 0x80.
-
-- interrupts : property with a value describing the interrupt source
-        (number and sensitivity) required for the controller.
-
-Optional properties:
-
-- bosch,external-clock-frequency : frequency of the external oscillator
-        clock in Hz. Note that the internal clock frequency used by the
-        controller is half of that value. If not specified, a default
-        value of 16000000 (16 MHz) is used.
-
-- bosch,clock-out-frequency : slock frequency in Hz on the CLKOUT pin.
-        If not specified or if the specified value is 0, the CLKOUT pin
-        will be disabled.
-
-- bosch,slew-rate : slew rate of the CLKOUT signal. If not specified,
-        a resonable value will be calculated.
-
-- bosch,disconnect-rx0-input : see data sheet.
-
-- bosch,disconnect-rx1-input : see data sheet.
-
-- bosch,disconnect-tx1-output : see data sheet.
-
-- bosch,polarity-dominant : see data sheet.
-
-- bosch,divide-memory-clock : see data sheet.
-
-- bosch,iso-low-speed-mux : see data sheet.
-
-For further information, please have a look to the CC770 or AN82527.
-
-Examples:
-
-can@3,100 {
-        compatible = "bosch,cc770";
-        reg = <3 0x100 0x80>;
-        interrupts = <2 0>;
-        interrupt-parent = <&mpic>;
-        bosch,external-clock-frequency = <16000000>;
-};
diff --git a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
index 8ff324eaa88..1a729f08986 100644
--- a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
+++ b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
@@ -1,27 +1,61 @@
-Flexcan CAN controller on Freescale's ARM and PowerPC system-on-a-chip (SOC).
-
-Required properties:
-
-- compatible : Should be "fsl,<processor>-flexcan"
-
-  An implementation should also claim any of the following compatibles
-  that it is fully backwards compatible with:
-
-  - fsl,p1010-flexcan
-
-- reg : Offset and length of the register set for this device
-- interrupts : Interrupt tuple for this device
-
-Optional properties:
-
-- clock-frequency : The oscillator frequency driving the flexcan device
-
-Example:
-
-        can@1c000 {
-                compatible = "fsl,p1010-flexcan";
+CAN Device Tree Bindings
+------------------------
+2011 Freescale Semiconductor, Inc.
+
+fsl,flexcan-v1.0 nodes
+-----------------------
+In addition to the required compatible-, reg- and interrupt-properties, you can
+also specify which clock source shall be used for the controller.
+
+CPI Clock- Can Protocol Interface Clock
+        This CLK_SRC bit of CTRL(control register) selects the clock source to
+        the CAN Protocol Interface(CPI) to be either the peripheral clock
+        (driven by the PLL) or the crystal oscillator clock. The selected clock
+        is the one fed to the prescaler to generate the Serial Clock (Sclock).
+        The PRESDIV field of CTRL(control register) controls a prescaler that
+        generates the Serial Clock (Sclock), whose period defines the
+        time quantum used to compose the CAN waveform.
+
+Can Engine Clock Source
+        There are two sources for CAN clock
+        - Platform Clock  It represents the bus clock
+        - Oscillator Clock
+
+        Peripheral Clock (PLL)
+        --------------
+                     |
+                    ---------                 -------------
+                    |       |CPI Clock        | Prescaler |       Sclock
+                    |       |---------------->| (1.. 256) |------------>
+                    ---------                 -------------
+                     |  |
+        --------------  ---------------------CLK_SRC
+        Oscillator Clock
+
+- fsl,flexcan-clock-source : CAN Engine Clock Source.This property selects
+                             the peripheral clock. PLL clock is fed to the
+                             prescaler to generate the Serial Clock (Sclock).
+                             Valid values are "oscillator" and "platform"
+                             "oscillator": CAN engine clock source is oscillator clock.
+                             "platform" The CAN engine clock source is the bus clock
+                             (platform clock).
+
+- fsl,flexcan-clock-divider : for the reference and system clock, an additional
+                              clock divider can be specified.
+- clock-frequency: frequency required to calculate the bitrate for FlexCAN.
+
+Note:
+        - v1.0 of flexcan-v1.0 represent the IP block version for P1010 SOC.
+        - P1010 does not have oscillator as the Clock Source.So the default
+          Clock Source is platform clock.
+Examples:
+
+        can0@1c000 {
+                compatible = "fsl,flexcan-v1.0";
                 reg = <0x1c000 0x1000>;
                 interrupts = <48 0x2>;
                 interrupt-parent = <&mpic>;
-                clock-frequency = <200000000>; // filled in by bootloader
+                fsl,flexcan-clock-source = "platform";
+                fsl,flexcan-clock-divider = <2>;
+                clock-frequency = <fixed by u-boot>;
         };
diff --git a/Documentation/devicetree/bindings/net/can/grcan.txt b/Documentation/devicetree/bindings/net/can/grcan.txt
deleted file mode 100644
index 34ef3498f88..00000000000
--- a/Documentation/devicetree/bindings/net/can/grcan.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-Aeroflex Gaisler GRCAN and GRHCAN CAN controllers.
-
-The GRCAN and CRHCAN CAN controllers are available in the GRLIB VHDL IP core
-library.
-
-Note: These properties are built from the AMBA plug&play in a Leon SPARC system
-(the ordinary environment for GRCAN and GRHCAN). There are no dts files for
-sparc.
-
-Required properties:
-
-- name : Should be "GAISLER_GRCAN", "01_03d", "GAISLER_GRHCAN" or "01_034"
-
-- reg : Address and length of the register set for the device
-
-- freq : Frequency of the external oscillator clock in Hz (the frequency of
-        the amba bus in the ordinary case)
-
-- interrupts : Interrupt number for this device
-
-Optional properties:
-
-- systemid : If not present or if the value of the least significant 16 bits
-        of this 32-bit property is smaller than GRCAN_TXBUG_SAFE_GRLIB_VERSION
-        a bug workaround is activated.
-
-For further information look in the documentation for the GLIB IP core library:
-http://www.gaisler.com/products/grlib/grip.pdf
diff --git a/Documentation/devicetree/bindings/net/cavium-mdio.txt b/Documentation/devicetree/bindings/net/cavium-mdio.txt
deleted file mode 100644
index 04cb7491d23..00000000000
--- a/Documentation/devicetree/bindings/net/cavium-mdio.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-* System Management Interface (SMI) / MDIO
-
-Properties:
-- compatible: "cavium,octeon-3860-mdio"
-
-  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
-
-- reg: The base address of the MDIO bus controller register bank.
-
-- #address-cells: Must be <1>.
-
-- #size-cells: Must be <0>.  MDIO addresses have no size component.
-
-Typically an MDIO bus might have several children.
-
-Example:
-        mdio@1180000001800 {
-                compatible = "cavium,octeon-3860-mdio";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                reg = <0x11800 0x00001800 0x0 0x40>;
-
-                ethernet-phy@0 {
-                        ...
-                        reg = <0>;
-                };
-        };
diff --git a/Documentation/devicetree/bindings/net/cavium-mix.txt b/Documentation/devicetree/bindings/net/cavium-mix.txt
deleted file mode 100644
index 5da628db68b..00000000000
--- a/Documentation/devicetree/bindings/net/cavium-mix.txt
+++ /dev/null
@@ -1,39 +0,0 @@
-* MIX Ethernet controller.
-
-Properties:
-- compatible: "cavium,octeon-5750-mix"
-
-  Compatibility with all cn5XXX and cn6XXX SOCs populated with MIX
-  devices.
-
-- reg: The base addresses of four separate register banks.  The first
-  bank contains the MIX registers.  The second bank the corresponding
-  AGL registers.  The third bank are the AGL registers shared by all
-  MIX devices present.  The fourth bank is the AGL_PRT_CTL shared by
-  all MIX devices present.
-
-- cell-index: A single cell specifying which portion of the shared
-  register banks corresponds to this MIX device.
-
-- interrupts: Two interrupt specifiers.  The first is the MIX
-  interrupt routing and the second the routing for the AGL interrupts.
-
-- mac-address: Optional, the MAC address to assign to the device.
-
-- local-mac-address: Optional, the MAC address to assign to the device
-  if mac-address is not specified.
-
-- phy-handle: Optional, a phandle for the PHY device connected to this device.
-
-Example:
-        ethernet@1070000100800 {
-                compatible = "cavium,octeon-5750-mix";
-                reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */
-                      <0x11800 0xE0000800 0x0 0x300>, /* AGL */
-                      <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED  */
-                      <0x11800 0xE0002008 0x0 0x8>;   /* AGL_PRT_CTL */
-                cell-index = <1>;
-                interrupts = <1 18>, < 1 46>;
-                local-mac-address = [ 00 0f b7 10 63 54 ];
-                phy-handle = <&phy1>;
-        };
diff --git a/Documentation/devicetree/bindings/net/cavium-pip.txt b/Documentation/devicetree/bindings/net/cavium-pip.txt
deleted file mode 100644
index d4c53ba04b3..00000000000
--- a/Documentation/devicetree/bindings/net/cavium-pip.txt
+++ /dev/null
@@ -1,98 +0,0 @@
-* PIP Ethernet nexus.
-
-The PIP Ethernet nexus can control several data packet input/output
-devices.  The devices have a two level grouping scheme.  There may be
-several interfaces, and each interface may have several ports.  These
-ports might be an individual Ethernet PHY.
-
-
-Properties for the PIP nexus:
-- compatible: "cavium,octeon-3860-pip"
-
-  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
-
-- reg: The base address of the PIP's register bank.
-
-- #address-cells: Must be <1>.
-
-- #size-cells: Must be <0>.
-
-Properties for PIP interfaces which is a child the PIP nexus:
-- compatible: "cavium,octeon-3860-pip-interface"
-
-  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
-
-- reg: The interface number.
-
-- #address-cells: Must be <1>.
-
-- #size-cells: Must be <0>.
-
-Properties for PIP port which is a child the PIP interface:
-- compatible: "cavium,octeon-3860-pip-port"
-
-  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
-
-- reg: The port number within the interface group.
-
-- mac-address: Optional, the MAC address to assign to the device.
-
-- local-mac-address: Optional, the MAC address to assign to the device
-  if mac-address is not specified.
-
-- phy-handle: Optional, a phandle for the PHY device connected to this device.
-
-Example:
-
-        pip@11800a0000000 {
-                compatible = "cavium,octeon-3860-pip";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                reg = <0x11800 0xa0000000 0x0 0x2000>;
-
-                interface@0 {
-                        compatible = "cavium,octeon-3860-pip-interface";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        reg = <0>; /* interface */
-
-                        ethernet@0 {
-                                compatible = "cavium,octeon-3860-pip-port";
-                                reg = <0x0>; /* Port */
-                                local-mac-address = [ 00 0f b7 10 63 60 ];
-                                phy-handle = <&phy2>;
-                        };
-                        ethernet@1 {
-                                compatible = "cavium,octeon-3860-pip-port";
-                                reg = <0x1>; /* Port */
-                                local-mac-address = [ 00 0f b7 10 63 61 ];
-                                phy-handle = <&phy3>;
-                        };
-                        ethernet@2 {
-                                compatible = "cavium,octeon-3860-pip-port";
-                                reg = <0x2>; /* Port */
-                                local-mac-address = [ 00 0f b7 10 63 62 ];
-                                phy-handle = <&phy4>;
-                        };
-                        ethernet@3 {
-                                compatible = "cavium,octeon-3860-pip-port";
-                                reg = <0x3>; /* Port */
-                                local-mac-address = [ 00 0f b7 10 63 63 ];
-                                phy-handle = <&phy5>;
-                        };
-                };
-
-                interface@1 {
-                        compatible = "cavium,octeon-3860-pip-interface";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        reg = <1>; /* interface */
-
-                        ethernet@0 {
-                                compatible = "cavium,octeon-3860-pip-port";
-                                reg = <0x0>; /* Port */
-                                local-mac-address = [ 00 0f b7 10 63 64 ];
-                                phy-handle = <&phy6>;
-                        };
-                };
-        };
diff --git a/Documentation/devicetree/bindings/net/cdns-emac.txt b/Documentation/devicetree/bindings/net/cdns-emac.txt
deleted file mode 100644
index 09055c2495f..00000000000
--- a/Documentation/devicetree/bindings/net/cdns-emac.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-* Cadence EMAC Ethernet controller
-
-Required properties:
-- compatible: Should be "cdns,[<chip>-]{emac}"
-  Use "cdns,at91rm9200-emac" Atmel at91rm9200 SoC.
-  or the generic form: "cdns,emac".
-- reg: Address and length of the register set for the device
-- interrupts: Should contain macb interrupt
-- phy-mode: String, operation mode of the PHY interface.
-  Supported values are: "mii", "rmii".
-
-Optional properties:
-- local-mac-address: 6 bytes, mac address
-
-Examples:
-
-        macb0: ethernet@fffc4000 {
-                compatible = "cdns,at91rm9200-emac";
-                reg = <0xfffc4000 0x4000>;
-                interrupts = <21>;
-                phy-mode = "rmii";
-                local-mac-address = [3a 0e 03 04 05 06];
-        };
diff --git a/Documentation/devicetree/bindings/net/cpsw.txt b/Documentation/devicetree/bindings/net/cpsw.txt
deleted file mode 100644
index 6ddd0286a9b..00000000000
--- a/Documentation/devicetree/bindings/net/cpsw.txt
+++ /dev/null
@@ -1,87 +0,0 @@
-TI SoC Ethernet Switch Controller Device Tree Bindings
-------------------------------------------------------
-
-Required properties:
-- compatible            : Should be "ti,cpsw"
-- reg                   : physical base address and size of the cpsw
-                          registers map
-- interrupts            : property with a value describing the interrupt
-                          number
-- interrupt-parent      : The parent interrupt controller
-- cpdma_channels        : Specifies number of channels in CPDMA
-- ale_entries           : Specifies No of entries ALE can hold
-- bd_ram_size           : Specifies internal descriptor RAM size
-- rx_descs              : Specifies number of Rx descriptors
-- mac_control           : Specifies Default MAC control register content
-                          for the specific platform
-- slaves                : Specifies number for slaves
-- cpts_active_slave     : Specifies the slave to use for time stamping
-- cpts_clock_mult       : Numerator to convert input clock ticks into nanoseconds
-- cpts_clock_shift      : Denominator to convert input clock ticks into nanoseconds
-- phy_id                : Specifies slave phy id
-- mac-address           : Specifies slave MAC address
-
-Optional properties:
-- ti,hwmods             : Must be "cpgmac0"
-- no_bd_ram             : Must be 0 or 1
-
-Note: "ti,hwmods" field is used to fetch the base address and irq
-resources from TI, omap hwmod data base during device registration.
-Future plan is to migrate hwmod data base contents into device tree
-blob so that, all the required data will be used from device tree dts
-file.
-
-Examples:
-
-        mac: ethernet@4A100000 {
-                compatible = "ti,cpsw";
-                reg = <0x4A100000 0x1000>;
-                interrupts = <55 0x4>;
-                interrupt-parent = <&intc>;
-                cpdma_channels = <8>;
-                ale_entries = <1024>;
-                bd_ram_size = <0x2000>;
-                no_bd_ram = <0>;
-                rx_descs = <64>;
-                mac_control = <0x20>;
-                slaves = <2>;
-                cpts_active_slave = <0>;
-                cpts_clock_mult = <0x80000000>;
-                cpts_clock_shift = <29>;
-                cpsw_emac0: slave@0 {
-                        phy_id = <&davinci_mdio>, <0>;
-                        /* Filled in by U-Boot */
-                        mac-address = [ 00 00 00 00 00 00 ];
-                };
-                cpsw_emac1: slave@1 {
-                        phy_id = <&davinci_mdio>, <1>;
-                        /* Filled in by U-Boot */
-                        mac-address = [ 00 00 00 00 00 00 ];
-                };
-        };
-
-(or)
-        mac: ethernet@4A100000 {
-                compatible = "ti,cpsw";
-                ti,hwmods = "cpgmac0";
-                cpdma_channels = <8>;
-                ale_entries = <1024>;
-                bd_ram_size = <0x2000>;
-                no_bd_ram = <0>;
-                rx_descs = <64>;
-                mac_control = <0x20>;
-                slaves = <2>;
-                cpts_active_slave = <0>;
-                cpts_clock_mult = <0x80000000>;
-                cpts_clock_shift = <29>;
-                cpsw_emac0: slave@0 {
-                        phy_id = <&davinci_mdio>, <0>;
-                        /* Filled in by U-Boot */
-                        mac-address = [ 00 00 00 00 00 00 ];
-                };
-                cpsw_emac1: slave@1 {
-                        phy_id = <&davinci_mdio>, <1>;
-                        /* Filled in by U-Boot */
-                        mac-address = [ 00 00 00 00 00 00 ];
-                };
-        };
diff --git a/Documentation/devicetree/bindings/net/davinci-mdio.txt b/Documentation/devicetree/bindings/net/davinci-mdio.txt
deleted file mode 100644
index 72efaaf764f..00000000000
--- a/Documentation/devicetree/bindings/net/davinci-mdio.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-TI SoC Davinci MDIO Controller Device Tree Bindings
----------------------------------------------------
-
-Required properties:
-- compatible            : Should be "ti,davinci_mdio"
-- reg                   : physical base address and size of the davinci mdio
-                          registers map
-- bus_freq              : Mdio Bus frequency
-
-Optional properties:
-- ti,hwmods             : Must be "davinci_mdio"
-
-Note: "ti,hwmods" field is used to fetch the base address and irq
-resources from TI, omap hwmod data base during device registration.
-Future plan is to migrate hwmod data base contents into device tree
-blob so that, all the required data will be used from device tree dts
-file.
-
-Examples:
-
-        mdio: davinci_mdio@4A101000 {
-                compatible = "ti,cpsw";
-                reg = <0x4A101000 0x1000>;
-                bus_freq = <1000000>;
-        };
-
-(or)
-
-        mdio: davinci_mdio@4A101000 {
-                compatible = "ti,cpsw";
-                ti,hwmods = "davinci_mdio";
-                bus_freq = <1000000>;
-        };
diff --git a/Documentation/devicetree/bindings/net/davinci_emac.txt b/Documentation/devicetree/bindings/net/davinci_emac.txt
deleted file mode 100644
index 48b259e29e8..00000000000
--- a/Documentation/devicetree/bindings/net/davinci_emac.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-* Texas Instruments Davinci EMAC
-
-This file provides information, what the device node
-for the davinci_emac interface contains.
-
-Required properties:
-- compatible: "ti,davinci-dm6467-emac";
-- reg: Offset and length of the register set for the device
-- ti,davinci-ctrl-reg-offset: offset to control register
-- ti,davinci-ctrl-mod-reg-offset: offset to control module register
-- ti,davinci-ctrl-ram-offset: offset to control module ram
-- ti,davinci-ctrl-ram-size: size of control module ram
-- ti,davinci-rmii-en: use RMII
-- ti,davinci-no-bd-ram: has the emac controller BD RAM
-- phy-handle: Contains a phandle to an Ethernet PHY.
-              if not, davinci_emac driver defaults to 100/FULL
-- interrupts: interrupt mapping for the davinci emac interrupts sources:
-              4 sources: <Receive Threshold Interrupt
-                          Receive Interrupt
-                          Transmit Interrupt
-                          Miscellaneous Interrupt>
-
-Optional properties:
-- local-mac-address : 6 bytes, mac address
-
-Example (enbw_cmc board):
-        eth0: emac@1e20000 {
-                compatible = "ti,davinci-dm6467-emac";
-                reg = <0x220000 0x4000>;
-                ti,davinci-ctrl-reg-offset = <0x3000>;
-                ti,davinci-ctrl-mod-reg-offset = <0x2000>;
-                ti,davinci-ctrl-ram-offset = <0>;
-                ti,davinci-ctrl-ram-size = <0x2000>;
-                local-mac-address = [ 00 00 00 00 00 00 ];
-                interrupts = <33
-                                34
-                                35
-                                36
-                                >;
-                interrupt-parent = <&intc>;
-        };
diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt
index d5363922140..de439517dff 100644
--- a/Documentation/devicetree/bindings/net/fsl-fec.txt
+++ b/Documentation/devicetree/bindings/net/fsl-fec.txt
@@ -7,22 +7,18 @@ Required properties:
 - phy-mode : String, operation mode of the PHY interface.
   Supported values are: "mii", "gmii", "sgmii", "tbi", "rmii",
   "rgmii", "rgmii-id", "rgmii-rxid", "rgmii-txid", "rtbi", "smii".
+- phy-reset-gpios : Should specify the gpio for phy reset
 
 Optional properties:
 - local-mac-address : 6 bytes, mac address
-- phy-reset-gpios : Should specify the gpio for phy reset
-- phy-reset-duration : Reset duration in milliseconds.  Should present
-  only if property "phy-reset-gpios" is available.  Missing the property
-  will have the duration be 1 millisecond.  Numbers greater than 1000 are
-  invalid and 1 millisecond will be used instead.
 
 Example:
 
-ethernet@83fec000 {
+fec@83fec000 {
         compatible = "fsl,imx51-fec", "fsl,imx27-fec";
         reg = <0x83fec000 0x4000>;
         interrupts = <87>;
         phy-mode = "mii";
-        phy-reset-gpios = <&gpio2 14 0>; /* GPIO2_14 */
+        phy-reset-gpios = <&gpio1 14 0>; /* GPIO2_14 */
         local-mac-address = [00 04 9F 01 1B B9];
 };
diff --git a/Documentation/devicetree/bindings/net/lpc-eth.txt b/Documentation/devicetree/bindings/net/lpc-eth.txt
deleted file mode 100644
index 585021acd17..00000000000
--- a/Documentation/devicetree/bindings/net/lpc-eth.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-* NXP LPC32xx SoC Ethernet Controller
-
-Required properties:
-- compatible: Should be "nxp,lpc-eth"
-- reg: Address and length of the register set for the device
-- interrupts: Should contain ethernet controller interrupt
-
-Optional properties:
-- phy-mode: String, operation mode of the PHY interface.
-  Supported values are: "mii", "rmii" (default)
-- use-iram: Use LPC32xx internal SRAM (IRAM) for DMA buffering
-- local-mac-address : 6 bytes, mac address
-
-Example:
-
-        mac: ethernet@31060000 {
-                compatible = "nxp,lpc-eth";
-                reg = <0x31060000 0x1000>;
-                interrupt-parent = <&mic>;
-                interrupts = <29 0>;
-
-                phy-mode = "rmii";
-                use-iram;
-        };
diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt
deleted file mode 100644
index 44afa0e5057..00000000000
--- a/Documentation/devicetree/bindings/net/macb.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-* Cadence MACB/GEM Ethernet controller
-
-Required properties:
-- compatible: Should be "cdns,[<chip>-]{macb|gem}"
-  Use "cdns,at91sam9260-macb" Atmel at91sam9260 and at91sam9263 SoCs.
-  Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb".
-  Use "cnds,pc302-gem" for Picochip picoXcell pc302 and later devices based on
-  the Cadence GEM, or the generic form: "cdns,gem".
-- reg: Address and length of the register set for the device
-- interrupts: Should contain macb interrupt
-- phy-mode: String, operation mode of the PHY interface.
-  Supported values are: "mii", "rmii", "gmii", "rgmii".
-
-Optional properties:
-- local-mac-address: 6 bytes, mac address
-
-Examples:
-
-        macb0: ethernet@fffc4000 {
-                compatible = "cdns,at32ap7000-macb";
-                reg = <0xfffc4000 0x4000>;
-                interrupts = <21>;
-                phy-mode = "rmii";
-                local-mac-address = [3a 0e 03 04 05 06];
-        };
diff --git a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
deleted file mode 100644
index 859a6fa7569..00000000000
--- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-* Marvell Armada 370 / Armada XP Ethernet Controller (NETA)
-
-Required properties:
-- compatible: should be "marvell,armada-370-neta".
-- reg: address and length of the register set for the device.
-- interrupts: interrupt for the device
-- phy: A phandle to a phy node defining the PHY address (as the reg
-  property, a single integer).
-- phy-mode: The interface between the SoC and the PHY (a string that
-  of_get_phy_mode() can understand)
-- clocks: a pointer to the reference clock for this device.
-
-Example:
-
-ethernet@d0070000 {
-        compatible = "marvell,armada-370-neta";
-        reg = <0xd0070000 0x2500>;
-        interrupts = <8>;
-        clocks = <&gate_clk 4>;
-        status = "okay";
-        phy = <&phy0>;
-        phy-mode = "rgmii-id";
-};
diff --git a/Documentation/devicetree/bindings/net/marvell-orion-mdio.txt b/Documentation/devicetree/bindings/net/marvell-orion-mdio.txt
deleted file mode 100644
index 34e7aafa321..00000000000
--- a/Documentation/devicetree/bindings/net/marvell-orion-mdio.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-* Marvell MDIO Ethernet Controller interface
-
-The Ethernet controllers of the Marvel Kirkwood, Dove, Orion5x,
-MV78xx0, Armada 370 and Armada XP have an identical unit that provides
-an interface with the MDIO bus. This driver handles this MDIO
-interface.
-
-Required properties:
-- compatible: "marvell,orion-mdio"
-- reg: address and length of the SMI register
-
-The child nodes of the MDIO driver are the individual PHY devices
-connected to this MDIO bus. They must have a "reg" property given the
-PHY address on the MDIO bus.
-
-Example at the SoC level:
-
-mdio {
-        #address-cells = <1>;
-        #size-cells = <0>;
-        compatible = "marvell,orion-mdio";
-        reg = <0xd0072004 0x4>;
-};
-
-And at the board level:
-
-mdio {
-        phy0: ethernet-phy@0 {
-                reg = <0>;
-        };
-
-        phy1: ethernet-phy@1 {
-                reg = <1>;
-        };
-}
diff --git a/Documentation/devicetree/bindings/net/mdio-gpio.txt b/Documentation/devicetree/bindings/net/mdio-gpio.txt
index c79bab02536..bc954952901 100644
--- a/Documentation/devicetree/bindings/net/mdio-gpio.txt
+++ b/Documentation/devicetree/bindings/net/mdio-gpio.txt
@@ -8,16 +8,9 @@ gpios property as described in section VIII.1 in the following order:
 
 MDC, MDIO.
 
-Note: Each gpio-mdio bus should have an alias correctly numbered in "aliases"
-node.
-
 Example:
 
-aliases {
-        mdio-gpio0 = <&mdio0>;
-};
-
-mdio0: mdio {
+mdio {
         compatible = "virtual,mdio-gpio";
         #address-cells = <1>;
         #size-cells = <0>;
diff --git a/Documentation/devicetree/bindings/net/mdio-mux-gpio.txt b/Documentation/devicetree/bindings/net/mdio-mux-gpio.txt
deleted file mode 100644
index 79384113c2b..00000000000
--- a/Documentation/devicetree/bindings/net/mdio-mux-gpio.txt
+++ /dev/null
@@ -1,127 +0,0 @@
-Properties for an MDIO bus multiplexer/switch controlled by GPIO pins.
-
-This is a special case of a MDIO bus multiplexer.  One or more GPIO
-lines are used to control which child bus is connected.
-
-Required properties in addition to the generic multiplexer properties:
-
-- compatible : mdio-mux-gpio.
-- gpios : GPIO specifiers for each GPIO line.  One or more must be specified.
-
-
-Example :
-
-        /* The parent MDIO bus. */
-        smi1: mdio@1180000001900 {
-                compatible = "cavium,octeon-3860-mdio";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                reg = <0x11800 0x00001900 0x0 0x40>;
-        };
-
-        /*
-           An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
-           pair of GPIO lines.  Child busses 2 and 3 populated with 4
-           PHYs each.
-         */
-        mdio-mux {
-                compatible = "mdio-mux-gpio";
-                gpios = <&gpio1 3 0>, <&gpio1 4 0>;
-                mdio-parent-bus = <&smi1>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                mdio@2 {
-                        reg = <2>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        phy11: ethernet-phy@1 {
-                                reg = <1>;
-                                compatible = "marvell,88e1149r";
-                                marvell,reg-init = <3 0x10 0 0x5777>,
-                                        <3 0x11 0 0x00aa>,
-                                        <3 0x12 0 0x4105>,
-                                        <3 0x13 0 0x0a60>;
-                                interrupt-parent = <&gpio>;
-                                interrupts = <10 8>; /* Pin 10, active low */
-                        };
-                        phy12: ethernet-phy@2 {
-                                reg = <2>;
-                                compatible = "marvell,88e1149r";
-                                marvell,reg-init = <3 0x10 0 0x5777>,
-                                        <3 0x11 0 0x00aa>,
-                                        <3 0x12 0 0x4105>,
-                                        <3 0x13 0 0x0a60>;
-                                interrupt-parent = <&gpio>;
-                                interrupts = <10 8>; /* Pin 10, active low */
-                        };
-                        phy13: ethernet-phy@3 {
-                                reg = <3>;
-                                compatible = "marvell,88e1149r";
-                                marvell,reg-init = <3 0x10 0 0x5777>,
-                                        <3 0x11 0 0x00aa>,
-                                        <3 0x12 0 0x4105>,
-                                        <3 0x13 0 0x0a60>;
-                                interrupt-parent = <&gpio>;
-                                interrupts = <10 8>; /* Pin 10, active low */
-                        };
-                        phy14: ethernet-phy@4 {
-                                reg = <4>;
-                                compatible = "marvell,88e1149r";
-                                marvell,reg-init = <3 0x10 0 0x5777>,
-                                        <3 0x11 0 0x00aa>,
-                                        <3 0x12 0 0x4105>,
-                                        <3 0x13 0 0x0a60>;
-                                interrupt-parent = <&gpio>;
-                                interrupts = <10 8>; /* Pin 10, active low */
-                        };
-                };
-
-                mdio@3 {
-                        reg = <3>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        phy21: ethernet-phy@1 {
-                                reg = <1>;
-                                compatible = "marvell,88e1149r";
-                                marvell,reg-init = <3 0x10 0 0x5777>,
-                                        <3 0x11 0 0x00aa>,
-                                        <3 0x12 0 0x4105>,
-                                        <3 0x13 0 0x0a60>;
-                                interrupt-parent = <&gpio>;
-                                interrupts = <12 8>; /* Pin 12, active low */
-                        };
-                        phy22: ethernet-phy@2 {
-                                reg = <2>;
-                                compatible = "marvell,88e1149r";
-                                marvell,reg-init = <3 0x10 0 0x5777>,
-                                        <3 0x11 0 0x00aa>,
-                                        <3 0x12 0 0x4105>,
-                                        <3 0x13 0 0x0a60>;
-                                interrupt-parent = <&gpio>;
-                                interrupts = <12 8>; /* Pin 12, active low */
-                        };
-                        phy23: ethernet-phy@3 {
-                                reg = <3>;
-                                compatible = "marvell,88e1149r";
-                                marvell,reg-init = <3 0x10 0 0x5777>,
-                                        <3 0x11 0 0x00aa>,
-                                        <3 0x12 0 0x4105>,
-                                        <3 0x13 0 0x0a60>;
-                                interrupt-parent = <&gpio>;
-                                interrupts = <12 8>; /* Pin 12, active low */
-                        };
-                        phy24: ethernet-phy@4 {
-                                reg = <4>;
-                                compatible = "marvell,88e1149r";
-                                marvell,reg-init = <3 0x10 0 0x5777>,
-                                        <3 0x11 0 0x00aa>,
-                                        <3 0x12 0 0x4105>,
-                                        <3 0x13 0 0x0a60>;
-                                interrupt-parent = <&gpio>;
-                                interrupts = <12 8>; /* Pin 12, active low */
-                        };
-                };
-        };
diff --git a/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt b/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt
deleted file mode 100644
index 8516929c725..00000000000
--- a/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt
+++ /dev/null
@@ -1,75 +0,0 @@
-Properties for an MDIO bus multiplexer controlled by a memory-mapped device
-
-This is a special case of a MDIO bus multiplexer.  A memory-mapped device,
-like an FPGA, is used to control which child bus is connected.  The mdio-mux
-node must be a child of the memory-mapped device.  The driver currently only
-supports devices with eight-bit registers.
-
-Required properties in addition to the generic multiplexer properties:
-
-- compatible : string, must contain "mdio-mux-mmioreg"
-
-- reg : integer, contains the offset of the register that controls the bus
-        multiplexer.  The size field in the 'reg' property is the size of
-        register, and must therefore be 1.
-
-- mux-mask : integer, contains an eight-bit mask that specifies which
-        bits in the register control the actual bus multiplexer.  The
-        'reg' property of each child mdio-mux node must be constrained by
-        this mask.
-
-Example:
-
-The FPGA node defines a memory-mapped FPGA with a register space of 0x30 bytes.
-For the "EMI2" MDIO bus, register 9 (BRDCFG1) controls the mux on that bus.
-A bitmask of 0x6 means that bits 1 and 2 (bit 0 is lsb) are the bits on
-BRDCFG1 that control the actual mux.
-
-        /* The FPGA node */
-        fpga: board-control@3,0 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis";
-                reg = <3 0 0x30>;
-                ranges = <0 3 0 0x30>;
-
-                mdio-mux-emi2 {
-                        compatible = "mdio-mux-mmioreg", "mdio-mux";
-                        mdio-parent-bus = <&xmdio0>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        reg = <9 1>; // BRDCFG1
-                        mux-mask = <0x6>; // EMI2
-
-                        emi2_slot1: mdio@0 {    // Slot 1 XAUI (FM2)
-                                reg = <0>;
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                phy_xgmii_slot1: ethernet-phy@0 {
-                                        compatible = "ethernet-phy-ieee802.3-c45";
-                                        reg = <4>;
-                                };
-                        };
-
-                        emi2_slot2: mdio@2 {    // Slot 2 XAUI (FM1)
-                                reg = <2>;
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                phy_xgmii_slot2: ethernet-phy@4 {
-                                        compatible = "ethernet-phy-ieee802.3-c45";
-                                        reg = <0>;
-                                };
-                        };
-                };
-        };
-
-        /* The parent MDIO bus. */
-        xmdio0: mdio@f1000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "fsl,fman-xmdio";
-                reg = <0xf1000 0x1000>;
-                interrupts = <100 1 0 0>;
-        };
diff --git a/Documentation/devicetree/bindings/net/mdio-mux.txt b/Documentation/devicetree/bindings/net/mdio-mux.txt
deleted file mode 100644
index f65606f8d63..00000000000
--- a/Documentation/devicetree/bindings/net/mdio-mux.txt
+++ /dev/null
@@ -1,136 +0,0 @@
-Common MDIO bus multiplexer/switch properties.
-
-An MDIO bus multiplexer/switch will have several child busses that are
-numbered uniquely in a device dependent manner.  The nodes for an MDIO
-bus multiplexer/switch will have one child node for each child bus.
-
-Required properties:
-- mdio-parent-bus : phandle to the parent MDIO bus.
-- #address-cells = <1>;
-- #size-cells = <0>;
-
-Optional properties:
-- Other properties specific to the multiplexer/switch hardware.
-
-Required properties for child nodes:
-- #address-cells = <1>;
-- #size-cells = <0>;
-- reg : The sub-bus number.
-
-
-Example :
-
-        /* The parent MDIO bus. */
-        smi1: mdio@1180000001900 {
-                compatible = "cavium,octeon-3860-mdio";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                reg = <0x11800 0x00001900 0x0 0x40>;
-        };
-
-        /*
-           An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
-           pair of GPIO lines.  Child busses 2 and 3 populated with 4
-           PHYs each.
-         */
-        mdio-mux {
-                compatible = "mdio-mux-gpio";
-                gpios = <&gpio1 3 0>, <&gpio1 4 0>;
-                mdio-parent-bus = <&smi1>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                mdio@2 {
-                        reg = <2>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        phy11: ethernet-phy@1 {
-                                reg = <1>;
-                                compatible = "marvell,88e1149r";
-                                marvell,reg-init = <3 0x10 0 0x5777>,
-                                        <3 0x11 0 0x00aa>,
-                                        <3 0x12 0 0x4105>,
-                                        <3 0x13 0 0x0a60>;
-                                interrupt-parent = <&gpio>;
-                                interrupts = <10 8>; /* Pin 10, active low */
-                        };
-                        phy12: ethernet-phy@2 {
-                                reg = <2>;
-                                compatible = "marvell,88e1149r";
-                                marvell,reg-init = <3 0x10 0 0x5777>,
-                                        <3 0x11 0 0x00aa>,
-                                        <3 0x12 0 0x4105>,
-                                        <3 0x13 0 0x0a60>;
-                                interrupt-parent = <&gpio>;
-                                interrupts = <10 8>; /* Pin 10, active low */
-                        };
-                        phy13: ethernet-phy@3 {
-                                reg = <3>;
-                                compatible = "marvell,88e1149r";
-                                marvell,reg-init = <3 0x10 0 0x5777>,
-                                        <3 0x11 0 0x00aa>,
-                                        <3 0x12 0 0x4105>,
-                                        <3 0x13 0 0x0a60>;
-                                interrupt-parent = <&gpio>;
-                                interrupts = <10 8>; /* Pin 10, active low */
-                        };
-                        phy14: ethernet-phy@4 {
-                                reg = <4>;
-                                compatible = "marvell,88e1149r";
-                                marvell,reg-init = <3 0x10 0 0x5777>,
-                                        <3 0x11 0 0x00aa>,
-                                        <3 0x12 0 0x4105>,
-                                        <3 0x13 0 0x0a60>;
-                                interrupt-parent = <&gpio>;
-                                interrupts = <10 8>; /* Pin 10, active low */
-                        };
-                };
-
-                mdio@3 {
-                        reg = <3>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        phy21: ethernet-phy@1 {
-                                reg = <1>;
-                                compatible = "marvell,88e1149r";
-                                marvell,reg-init = <3 0x10 0 0x5777>,
-                                        <3 0x11 0 0x00aa>,
-                                        <3 0x12 0 0x4105>,
-                                        <3 0x13 0 0x0a60>;
-                                interrupt-parent = <&gpio>;
-                                interrupts = <12 8>; /* Pin 12, active low */
-                        };
-                        phy22: ethernet-phy@2 {
-                                reg = <2>;
-                                compatible = "marvell,88e1149r";
-                                marvell,reg-init = <3 0x10 0 0x5777>,
-                                        <3 0x11 0 0x00aa>,
-                                        <3 0x12 0 0x4105>,
-                                        <3 0x13 0 0x0a60>;
-                                interrupt-parent = <&gpio>;
-                                interrupts = <12 8>; /* Pin 12, active low */
-                        };
-                        phy23: ethernet-phy@3 {
-                                reg = <3>;
-                                compatible = "marvell,88e1149r";
-                                marvell,reg-init = <3 0x10 0 0x5777>,
-                                        <3 0x11 0 0x00aa>,
-                                        <3 0x12 0 0x4105>,
-                                        <3 0x13 0 0x0a60>;
-                                interrupt-parent = <&gpio>;
-                                interrupts = <12 8>; /* Pin 12, active low */
-                        };
-                        phy24: ethernet-phy@4 {
-                                reg = <4>;
-                                compatible = "marvell,88e1149r";
-                                marvell,reg-init = <3 0x10 0 0x5777>,
-                                        <3 0x11 0 0x00aa>,
-                                        <3 0x12 0 0x4105>,
-                                        <3 0x13 0 0x0a60>;
-                                interrupt-parent = <&gpio>;
-                                interrupts = <12 8>; /* Pin 12, active low */
-                        };
-                };
-        };
diff --git a/Documentation/devicetree/bindings/net/phy.txt b/Documentation/devicetree/bindings/net/phy.txt
index 7cd18fbfcf7..bb8c742eb8c 100644
--- a/Documentation/devicetree/bindings/net/phy.txt
+++ b/Documentation/devicetree/bindings/net/phy.txt
@@ -14,20 +14,10 @@ Required properties:
  - linux,phandle :  phandle for this node; likely referenced by an
    ethernet controller node.
 
-Optional Properties:
-
-- compatible: Compatible list, may contain
-  "ethernet-phy-ieee802.3-c22" or "ethernet-phy-ieee802.3-c45" for
-  PHYs that implement IEEE802.3 clause 22 or IEEE802.3 clause 45
-  specifications. If neither of these are specified, the default is to
-  assume clause 22. The compatible list may also contain other
-  elements.
-
 Example:
 
 ethernet-phy@0 {
-        compatible = "ethernet-phy-ieee802.3-c22";
-        linux,phandle = <2452000>;
+        linux,phandle = <2452000>
         interrupt-parent = <40000>;
         interrupts = <35 1>;
         reg = <0>;
diff --git a/Documentation/devicetree/bindings/net/smsc911x.txt b/Documentation/devicetree/bindings/net/smsc911x.txt
deleted file mode 100644
index adb5b5744ec..00000000000
--- a/Documentation/devicetree/bindings/net/smsc911x.txt
+++ /dev/null
@@ -1,38 +0,0 @@
-* Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller
-
-Required properties:
-- compatible : Should be "smsc,lan<model>", "smsc,lan9115"
-- reg : Address and length of the io space for SMSC LAN
-- interrupts : Should contain SMSC LAN interrupt line
-- interrupt-parent : Should be the phandle for the interrupt controller
-  that services interrupts for this device
-- phy-mode : String, operation mode of the PHY interface.
-  Supported values are: "mii", "gmii", "sgmii", "tbi", "rmii",
-  "rgmii", "rgmii-id", "rgmii-rxid", "rgmii-txid", "rtbi", "smii".
-
-Optional properties:
-- reg-shift : Specify the quantity to shift the register offsets by
-- reg-io-width : Specify the size (in bytes) of the IO accesses that
-  should be performed on the device.  Valid value for SMSC LAN is
-  2 or 4.  If it's omitted or invalid, the size would be 2.
-- smsc,irq-active-high : Indicates the IRQ polarity is active-high
-- smsc,irq-push-pull : Indicates the IRQ type is push-pull
-- smsc,force-internal-phy : Forces SMSC LAN controller to use
-  internal PHY
-- smsc,force-external-phy : Forces SMSC LAN controller to use
-  external PHY
-- smsc,save-mac-address : Indicates that mac address needs to be saved
-  before resetting the controller
-- local-mac-address : 6 bytes, mac address
-
-Examples:
-
-lan9220@f4000000 {
-        compatible = "smsc,lan9220", "smsc,lan9115";
-        reg = <0xf4000000 0x2000000>;
-        phy-mode = "mii";
-        interrupt-parent = <&gpio1>;
-        interrupts = <31>;
-        reg-io-width = <4>;
-        smsc,irq-push-pull;
-};
diff --git a/Documentation/devicetree/bindings/net/stmmac.txt b/Documentation/devicetree/bindings/net/stmmac.txt
deleted file mode 100644
index 060bbf098ef..00000000000
--- a/Documentation/devicetree/bindings/net/stmmac.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-* STMicroelectronics 10/100/1000 Ethernet driver (GMAC)
-
-Required properties:
-- compatible: Should be "snps,dwmac-<ip_version>" "snps,dwmac"
-        For backwards compatibility: "st,spear600-gmac" is also supported.
-- reg: Address and length of the register set for the device
-- interrupt-parent: Should be the phandle for the interrupt controller
-  that services interrupts for this device
-- interrupts: Should contain the STMMAC interrupts
-- interrupt-names: Should contain the interrupt names "macirq"
-  "eth_wake_irq" if this interrupt is supported in the "interrupts"
-  property
-- phy-mode: String, operation mode of the PHY interface.
-  Supported values are: "mii", "rmii", "gmii", "rgmii".
-
-Optional properties:
-- mac-address: 6 bytes, mac address
-
-Examples:
-
-        gmac0: ethernet@e0800000 {
-                compatible = "st,spear600-gmac";
-                reg = <0xe0800000 0x8000>;
-                interrupt-parent = <&vic1>;
-                interrupts = <24 23>;
-                interrupt-names = "macirq", "eth_wake_irq";
-                mac-address = [000000000000]; /* Filled in by U-Boot */
-                phy-mode = "gmii";
-        };
diff --git a/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt b/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
deleted file mode 100644
index 5aeee53ff9f..00000000000
--- a/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-NVIDIA compliant embedded controller
-
-Required properties:
-- compatible : should be "nvidia,nvec".
-- reg : the iomem of the i2c slave controller
-- interrupts : the interrupt line of the i2c slave controller
-- clock-frequency : the frequency of the i2c bus
-- gpios : the gpio used for ec request
-- slave-addr: the i2c address of the slave controller
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
deleted file mode 100644
index 3a268127b05..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
+++ /dev/null
@@ -1,141 +0,0 @@
-* Atmel AT91 Pinmux Controller
-
-The AT91 Pinmux Controler, enables the IC
-to share one PAD to several functional blocks. The sharing is done by
-multiplexing the PAD input/output signals. For each PAD there are up to
-8 muxing options (called periph modes). Since different modules require
-different PAD settings (like pull up, keeper, etc) the contoller controls
-also the PAD settings parameters.
-
-Please refer to pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices, including the meaning of the
-phrase "pin configuration node".
-
-Atmel AT91 pin configuration node is a node of a group of pins which can be
-used for a specific device or function. This node represents both mux and config
-of the pins in that group. The 'pins' selects the function mode(also named pin
-mode) this pin can work on and the 'config' configures various pad settings
-such as pull-up, multi drive, etc.
-
-Required properties for iomux controller:
-- compatible: "atmel,at91rm9200-pinctrl"
-- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
-  configured in this periph mode. All the periph and bank need to be describe.
-
-How to create such array:
-
-Each column will represent the possible peripheral of the pinctrl
-Each line will represent a pio bank
-
-Take an example on the 9260
-Peripheral: 2 ( A and B)
-Bank: 3 (A, B and C)
-=>
-
-  /*    A         B     */
-  0xffffffff 0xffc00c3b  /* pioA */
-  0xffffffff 0x7fff3ccf  /* pioB */
-  0xffffffff 0x007fffff  /* pioC */
-
-For each peripheral/bank we will descibe in a u32 if a pin can can be
-configured in it by putting 1 to the pin bit (1 << pin)
-
-Let's take the pioA on peripheral B
-From the datasheet Table 10-2.
-Peripheral B
-PA0     MCDB0
-PA1     MCCDB
-PA2
-PA3     MCDB3
-PA4     MCDB2
-PA5     MCDB1
-PA6
-PA7
-PA8
-PA9
-PA10    ETX2
-PA11    ETX3
-PA12
-PA13
-PA14
-PA15
-PA16
-PA17
-PA18
-PA19
-PA20
-PA21
-PA22    ETXER
-PA23    ETX2
-PA24    ETX3
-PA25    ERX2
-PA26    ERX3
-PA27    ERXCK
-PA28    ECRS
-PA29    ECOL
-PA30    RXD4
-PA31    TXD4
-
-=> 0xffc00c3b
-
-Required properties for pin configuration node:
-- atmel,pins: 4 integers array, represents a group of pins mux and config
-  setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
-  The PERIPH 0 means gpio.
-
-Bits used for CONFIG:
-PULL_UP         (1 << 0): indicate this pin need a pull up.
-MULTIDRIVE      (1 << 1): indicate this pin need to be configured as multidrive.
-DEGLITCH        (1 << 2): indicate this pin need deglitch.
-PULL_DOWN       (1 << 3): indicate this pin need a pull down.
-DIS_SCHMIT      (1 << 4): indicate this pin need to disable schmit trigger.
-DEBOUNCE        (1 << 16): indicate this pin need debounce.
-DEBOUNCE_VAL    (0x3fff << 17): debounce val.
-
-NOTE:
-Some requirements for using atmel,at91rm9200-pinctrl binding:
-1. We have pin function node defined under at91 controller node to represent
-   what pinmux functions this SoC supports.
-2. The driver can use the function node's name and pin configuration node's
-   name describe the pin function and group hierarchy.
-   For example, Linux at91 pinctrl driver takes the function node's name
-   as the function name and pin configuration node's name as group name to
-   create the map table.
-3. Each pin configuration node should have a phandle, devices can set pins
-   configurations by referring to the phandle of that pin configuration node.
-4. The gpio controller must be describe in the pinctrl simple-bus.
-
-Examples:
-
-pinctrl@fffff400 {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        ranges;
-        compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
-        reg = <0xfffff400 0x600>;
-
-        atmel,mux-mask = <
-              /*    A         B     */
-               0xffffffff 0xffc00c3b  /* pioA */
-               0xffffffff 0x7fff3ccf  /* pioB */
-               0xffffffff 0x007fffff  /* pioC */
-              >;
-
-        /* shared pinctrl settings */
-        dbgu {
-                pinctrl_dbgu: dbgu-0 {
-                        atmel,pins =
-                                <1 14 0x1 0x0   /* PB14 periph A */
-                                 1 15 0x1 0x1>; /* PB15 periph with pullup */
-                };
-        };
-};
-
-dbgu: serial@fffff200 {
-        compatible = "atmel,at91sam9260-usart";
-        reg = <0xfffff200 0x200>;
-        interrupts = <1 4 7>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_dbgu>;
-        status = "disabled";
-};
diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt
deleted file mode 100644
index 8edc20e1b09..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt
+++ /dev/null
@@ -1,74 +0,0 @@
-Broadcom BCM2835 GPIO (and pinmux) controller
-
-The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt
-controller, and pinmux/control device.
-
-Required properties:
-- compatible: "brcm,bcm2835-gpio"
-- reg: Should contain the physical address of the GPIO module's registes.
-- gpio-controller: Marks the device node as a GPIO controller.
-- #gpio-cells : Should be two. The first cell is the pin number and the
-  second cell is used to specify optional parameters:
-  - bit 0 specifies polarity (0 for normal, 1 for inverted)
-- interrupts : The interrupt outputs from the controller. One interrupt per
-  individual bank followed by the "all banks" interrupt.
-- interrupt-controller: Marks the device node as an interrupt controller.
-- #interrupt-cells : Should be 2.
-  The first cell is the GPIO number.
-  The second cell is used to specify flags:
-    bits[3:0] trigger type and level flags:
-      1 = low-to-high edge triggered.
-      2 = high-to-low edge triggered.
-      4 = active high level-sensitive.
-      8 = active low level-sensitive.
-    Valid combinations are 1, 2, 3, 4, 8.
-
-Please refer to ../gpio/gpio.txt for a general description of GPIO bindings.
-
-Please refer to pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices, including the meaning of the
-phrase "pin configuration node".
-
-Each pin configuration node lists the pin(s) to which it applies, and one or
-more of the mux function to select on those pin(s), and pull-up/down
-configuration. Each subnode only affects those parameters that are explicitly
-listed. In other words, a subnode that lists only a mux function implies no
-information about any pull configuration. Similarly, a subnode that lists only
-a pul parameter implies no information about the mux function.
-
-Required subnode-properties:
-- brcm,pins: An array of cells. Each cell contains the ID of a pin. Valid IDs
-  are the integer GPIO IDs; 0==GPIO0, 1==GPIO1, ... 53==GPIO53.
-
-Optional subnode-properties:
-- brcm,function: Integer, containing the function to mux to the pin(s):
-  0: GPIO in
-  1: GPIO out
-  2: alt5
-  3: alt4
-  4: alt0
-  5: alt1
-  6: alt2
-  7: alt3
-- brcm,pull: Integer, representing the pull-down/up to apply to the pin(s):
-  0: none
-  1: down
-  2: up
-
-Each of brcm,function and brcm,pull may contain either a single value which
-will be applied to all pins in brcm,pins, or 1 value for each entry in
-brcm,pins.
-
-Example:
-
-        gpio: gpio {
-                compatible = "brcm,bcm2835-gpio";
-                reg = <0x2200000 0xb4>;
-                interrupts = <2 17>, <2 19>, <2 18>, <2 20>;
-
-                gpio-controller;
-                #gpio-cells = <2>;
-
-                interrupt-controller;
-                #interrupt-cells = <2>;
-        };
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
deleted file mode 100644
index ab19e6bc7d3..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
+++ /dev/null
@@ -1,95 +0,0 @@
-* Freescale IOMUX Controller (IOMUXC) for i.MX
-
-The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC
-to share one PAD to several functional blocks. The sharing is done by
-multiplexing the PAD input/output signals. For each PAD there are up to
-8 muxing options (called ALT modes). Since different modules require
-different PAD settings (like pull up, keeper, etc) the IOMUXC controls
-also the PAD settings parameters.
-
-Please refer to pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices, including the meaning of the
-phrase "pin configuration node".
-
-Freescale IMX pin configuration node is a node of a group of pins which can be
-used for a specific device or function. This node represents both mux and config
-of the pins in that group. The 'mux' selects the function mode(also named mux
-mode) this pin can work on and the 'config' configures various pad settings
-such as pull-up, open drain, drive strength, etc.
-
-Required properties for iomux controller:
-- compatible: "fsl,<soc>-iomuxc"
-  Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
-
-Required properties for pin configuration node:
-- fsl,pins: two integers array, represents a group of pins mux and config
-  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
-  pin working on a specific function, CONFIG is the pad setting value like
-  pull-up on this pin. Please refer to fsl,<soc>-pinctrl.txt for the valid
-  pins and functions of each SoC.
-
-Bits used for CONFIG:
-NO_PAD_CTL(1 << 31): indicate this pin does not need config.
-
-SION(1 << 30): Software Input On Field.
-Force the selected mux mode input path no matter of MUX_MODE functionality.
-By default the input path is determined by functionality of the selected
-mux mode (regular).
-
-Other bits are used for PAD setting.
-Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part
-of bits definitions.
-
-NOTE:
-Some requirements for using fsl,imx-pinctrl binding:
-1. We have pin function node defined under iomux controller node to represent
-   what pinmux functions this SoC supports.
-2. The pin configuration node intends to work on a specific function should
-   to be defined under that specific function node.
-   The function node's name should represent well about what function
-   this group of pins in this pin configuration node are working on.
-3. The driver can use the function node's name and pin configuration node's
-   name describe the pin function and group hierarchy.
-   For example, Linux IMX pinctrl driver takes the function node's name
-   as the function name and pin configuration node's name as group name to
-   create the map table.
-4. Each pin configuration node should have a phandle, devices can set pins
-   configurations by referring to the phandle of that pin configuration node.
-
-Examples:
-usdhc@0219c000 { /* uSDHC4 */
-        fsl,card-wired;
-        vmmc-supply = <&reg_3p3v>;
-        status = "okay";
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc4_1>;
-};
-
-iomuxc@020e0000 {
-        compatible = "fsl,imx6q-iomuxc";
-        reg = <0x020e0000 0x4000>;
-
-        /* shared pinctrl settings */
-        usdhc4 {
-                pinctrl_usdhc4_1: usdhc4grp-1 {
-                        fsl,pins = <1386 0x17059        /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
-                                    1392 0x10059        /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
-                                    1462 0x17059        /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
-                                    1470 0x17059        /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
-                                    1478 0x17059        /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
-                                    1486 0x17059        /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
-                                    1493 0x17059        /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
-                                    1501 0x17059        /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
-                                    1509 0x17059        /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
-                                    1517 0x17059>;      /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
-                };
-        };
-        ....
-};
-Refer to the IOMUXC controller chapter in imx6q datasheet,
-0x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed,
-80Ohm driver strength and Fast Slew Rate.
-User should refer to each SoC spec to set the correct value.
-
-TODO: when dtc macro support is available, we can change above raw data
-to dt macro which can get better readability in dts file.
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt
deleted file mode 100644
index 1183f1a3be3..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt
+++ /dev/null
@@ -1,984 +0,0 @@
-* Freescale IMX35 IOMUX Controller
-
-Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
-and usage.
-
-Required properties:
-- compatible: "fsl,imx35-iomuxc"
-- fsl,pins: two integers array, represents a group of pins mux and config
-  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
-  pin working on a specific function, CONFIG is the pad setting value like
-  pull-up for this pin. Please refer to imx35 datasheet for the valid pad
-  config settings.
-
-CONFIG bits definition:
-PAD_CTL_DRIVE_VOLAGAGE_18       (1 << 13)
-PAD_CTL_DRIVE_VOLAGAGE_33       (0 << 13)
-PAD_CTL_HYS                     (1 << 8)
-PAD_CTL_PKE                     (1 << 7)
-PAD_CTL_PUE                     (1 << 6)
-PAD_CTL_PUS_100K_DOWN           (0 << 4)
-PAD_CTL_PUS_47K_UP              (1 << 4)
-PAD_CTL_PUS_100K_UP             (2 << 4)
-PAD_CTL_PUS_22K_UP              (3 << 4)
-PAD_CTL_ODE_CMOS                (0 << 3)
-PAD_CTL_ODE_OPENDRAIN           (1 << 3)
-PAD_CTL_DSE_NOMINAL             (0 << 1)
-PAD_CTL_DSE_HIGH                (1 << 1)
-PAD_CTL_DSE_MAX                 (2 << 1)
-PAD_CTL_SRE_FAST                (1 << 0)
-PAD_CTL_SRE_SLOW                (0 << 0)
-
-See below for available PIN_FUNC_ID for imx35:
-0 MX35_PAD_CAPTURE__GPT_CAPIN1
-1 MX35_PAD_CAPTURE__GPT_CMPOUT2
-2 MX35_PAD_CAPTURE__CSPI2_SS1
-3 MX35_PAD_CAPTURE__EPIT1_EPITO
-4 MX35_PAD_CAPTURE__CCM_CLK32K
-5 MX35_PAD_CAPTURE__GPIO1_4
-6 MX35_PAD_COMPARE__GPT_CMPOUT1
-7 MX35_PAD_COMPARE__GPT_CAPIN2
-8 MX35_PAD_COMPARE__GPT_CMPOUT3
-9 MX35_PAD_COMPARE__EPIT2_EPITO
-10 MX35_PAD_COMPARE__GPIO1_5
-11 MX35_PAD_COMPARE__SDMA_EXTDMA_2
-12 MX35_PAD_WDOG_RST__WDOG_WDOG_B
-13 MX35_PAD_WDOG_RST__IPU_FLASH_STROBE
-14 MX35_PAD_WDOG_RST__GPIO1_6
-15 MX35_PAD_GPIO1_0__GPIO1_0
-16 MX35_PAD_GPIO1_0__CCM_PMIC_RDY
-17 MX35_PAD_GPIO1_0__OWIRE_LINE
-18 MX35_PAD_GPIO1_0__SDMA_EXTDMA_0
-19 MX35_PAD_GPIO1_1__GPIO1_1
-20 MX35_PAD_GPIO1_1__PWM_PWMO
-21 MX35_PAD_GPIO1_1__CSPI1_SS2
-22 MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT
-23 MX35_PAD_GPIO1_1__SDMA_EXTDMA_1
-24 MX35_PAD_GPIO2_0__GPIO2_0
-25 MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK
-26 MX35_PAD_GPIO3_0__GPIO3_0
-27 MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK
-28 MX35_PAD_RESET_IN_B__CCM_RESET_IN_B
-29 MX35_PAD_POR_B__CCM_POR_B
-30 MX35_PAD_CLKO__CCM_CLKO
-31 MX35_PAD_CLKO__GPIO1_8
-32 MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0
-33 MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1
-34 MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0
-35 MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1
-36 MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26
-37 MX35_PAD_VSTBY__CCM_VSTBY
-38 MX35_PAD_VSTBY__GPIO1_7
-39 MX35_PAD_A0__EMI_EIM_DA_L_0
-40 MX35_PAD_A1__EMI_EIM_DA_L_1
-41 MX35_PAD_A2__EMI_EIM_DA_L_2
-42 MX35_PAD_A3__EMI_EIM_DA_L_3
-43 MX35_PAD_A4__EMI_EIM_DA_L_4
-44 MX35_PAD_A5__EMI_EIM_DA_L_5
-45 MX35_PAD_A6__EMI_EIM_DA_L_6
-46 MX35_PAD_A7__EMI_EIM_DA_L_7
-47 MX35_PAD_A8__EMI_EIM_DA_H_8
-48 MX35_PAD_A9__EMI_EIM_DA_H_9
-49 MX35_PAD_A10__EMI_EIM_DA_H_10
-50 MX35_PAD_MA10__EMI_MA10
-51 MX35_PAD_A11__EMI_EIM_DA_H_11
-52 MX35_PAD_A12__EMI_EIM_DA_H_12
-53 MX35_PAD_A13__EMI_EIM_DA_H_13
-54 MX35_PAD_A14__EMI_EIM_DA_H2_14
-55 MX35_PAD_A15__EMI_EIM_DA_H2_15
-56 MX35_PAD_A16__EMI_EIM_A_16
-57 MX35_PAD_A17__EMI_EIM_A_17
-58 MX35_PAD_A18__EMI_EIM_A_18
-59 MX35_PAD_A19__EMI_EIM_A_19
-60 MX35_PAD_A20__EMI_EIM_A_20
-61 MX35_PAD_A21__EMI_EIM_A_21
-62 MX35_PAD_A22__EMI_EIM_A_22
-63 MX35_PAD_A23__EMI_EIM_A_23
-64 MX35_PAD_A24__EMI_EIM_A_24
-65 MX35_PAD_A25__EMI_EIM_A_25
-66 MX35_PAD_SDBA1__EMI_EIM_SDBA1
-67 MX35_PAD_SDBA0__EMI_EIM_SDBA0
-68 MX35_PAD_SD0__EMI_DRAM_D_0
-69 MX35_PAD_SD1__EMI_DRAM_D_1
-70 MX35_PAD_SD2__EMI_DRAM_D_2
-71 MX35_PAD_SD3__EMI_DRAM_D_3
-72 MX35_PAD_SD4__EMI_DRAM_D_4
-73 MX35_PAD_SD5__EMI_DRAM_D_5
-74 MX35_PAD_SD6__EMI_DRAM_D_6
-75 MX35_PAD_SD7__EMI_DRAM_D_7
-76 MX35_PAD_SD8__EMI_DRAM_D_8
-77 MX35_PAD_SD9__EMI_DRAM_D_9
-78 MX35_PAD_SD10__EMI_DRAM_D_10
-79 MX35_PAD_SD11__EMI_DRAM_D_11
-80 MX35_PAD_SD12__EMI_DRAM_D_12
-81 MX35_PAD_SD13__EMI_DRAM_D_13
-82 MX35_PAD_SD14__EMI_DRAM_D_14
-83 MX35_PAD_SD15__EMI_DRAM_D_15
-84 MX35_PAD_SD16__EMI_DRAM_D_16
-85 MX35_PAD_SD17__EMI_DRAM_D_17
-86 MX35_PAD_SD18__EMI_DRAM_D_18
-87 MX35_PAD_SD19__EMI_DRAM_D_19
-88 MX35_PAD_SD20__EMI_DRAM_D_20
-89 MX35_PAD_SD21__EMI_DRAM_D_21
-90 MX35_PAD_SD22__EMI_DRAM_D_22
-91 MX35_PAD_SD23__EMI_DRAM_D_23
-92 MX35_PAD_SD24__EMI_DRAM_D_24
-93 MX35_PAD_SD25__EMI_DRAM_D_25
-94 MX35_PAD_SD26__EMI_DRAM_D_26
-95 MX35_PAD_SD27__EMI_DRAM_D_27
-96 MX35_PAD_SD28__EMI_DRAM_D_28
-97 MX35_PAD_SD29__EMI_DRAM_D_29
-98 MX35_PAD_SD30__EMI_DRAM_D_30
-99 MX35_PAD_SD31__EMI_DRAM_D_31
-100 MX35_PAD_DQM0__EMI_DRAM_DQM_0
-101 MX35_PAD_DQM1__EMI_DRAM_DQM_1
-102 MX35_PAD_DQM2__EMI_DRAM_DQM_2
-103 MX35_PAD_DQM3__EMI_DRAM_DQM_3
-104 MX35_PAD_EB0__EMI_EIM_EB0_B
-105 MX35_PAD_EB1__EMI_EIM_EB1_B
-106 MX35_PAD_OE__EMI_EIM_OE
-107 MX35_PAD_CS0__EMI_EIM_CS0
-108 MX35_PAD_CS1__EMI_EIM_CS1
-109 MX35_PAD_CS1__EMI_NANDF_CE3
-110 MX35_PAD_CS2__EMI_EIM_CS2
-111 MX35_PAD_CS3__EMI_EIM_CS3
-112 MX35_PAD_CS4__EMI_EIM_CS4
-113 MX35_PAD_CS4__EMI_DTACK_B
-114 MX35_PAD_CS4__EMI_NANDF_CE1
-115 MX35_PAD_CS4__GPIO1_20
-116 MX35_PAD_CS5__EMI_EIM_CS5
-117 MX35_PAD_CS5__CSPI2_SS2
-118 MX35_PAD_CS5__CSPI1_SS2
-119 MX35_PAD_CS5__EMI_NANDF_CE2
-120 MX35_PAD_CS5__GPIO1_21
-121 MX35_PAD_NF_CE0__EMI_NANDF_CE0
-122 MX35_PAD_NF_CE0__GPIO1_22
-123 MX35_PAD_ECB__EMI_EIM_ECB
-124 MX35_PAD_LBA__EMI_EIM_LBA
-125 MX35_PAD_BCLK__EMI_EIM_BCLK
-126 MX35_PAD_RW__EMI_EIM_RW
-127 MX35_PAD_RAS__EMI_DRAM_RAS
-128 MX35_PAD_CAS__EMI_DRAM_CAS
-129 MX35_PAD_SDWE__EMI_DRAM_SDWE
-130 MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0
-131 MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1
-132 MX35_PAD_SDCLK__EMI_DRAM_SDCLK
-133 MX35_PAD_SDQS0__EMI_DRAM_SDQS_0
-134 MX35_PAD_SDQS1__EMI_DRAM_SDQS_1
-135 MX35_PAD_SDQS2__EMI_DRAM_SDQS_2
-136 MX35_PAD_SDQS3__EMI_DRAM_SDQS_3
-137 MX35_PAD_NFWE_B__EMI_NANDF_WE_B
-138 MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3
-139 MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC
-140 MX35_PAD_NFWE_B__GPIO2_18
-141 MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0
-142 MX35_PAD_NFRE_B__EMI_NANDF_RE_B
-143 MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR
-144 MX35_PAD_NFRE_B__IPU_DISPB_BCLK
-145 MX35_PAD_NFRE_B__GPIO2_19
-146 MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1
-147 MX35_PAD_NFALE__EMI_NANDF_ALE
-148 MX35_PAD_NFALE__USB_TOP_USBH2_STP
-149 MX35_PAD_NFALE__IPU_DISPB_CS0
-150 MX35_PAD_NFALE__GPIO2_20
-151 MX35_PAD_NFALE__ARM11P_TOP_TRACE_2
-152 MX35_PAD_NFCLE__EMI_NANDF_CLE
-153 MX35_PAD_NFCLE__USB_TOP_USBH2_NXT
-154 MX35_PAD_NFCLE__IPU_DISPB_PAR_RS
-155 MX35_PAD_NFCLE__GPIO2_21
-156 MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3
-157 MX35_PAD_NFWP_B__EMI_NANDF_WP_B
-158 MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7
-159 MX35_PAD_NFWP_B__IPU_DISPB_WR
-160 MX35_PAD_NFWP_B__GPIO2_22
-161 MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL
-162 MX35_PAD_NFRB__EMI_NANDF_RB
-163 MX35_PAD_NFRB__IPU_DISPB_RD
-164 MX35_PAD_NFRB__GPIO2_23
-165 MX35_PAD_NFRB__ARM11P_TOP_TRCLK
-166 MX35_PAD_D15__EMI_EIM_D_15
-167 MX35_PAD_D14__EMI_EIM_D_14
-168 MX35_PAD_D13__EMI_EIM_D_13
-169 MX35_PAD_D12__EMI_EIM_D_12
-170 MX35_PAD_D11__EMI_EIM_D_11
-171 MX35_PAD_D10__EMI_EIM_D_10
-172 MX35_PAD_D9__EMI_EIM_D_9
-173 MX35_PAD_D8__EMI_EIM_D_8
-174 MX35_PAD_D7__EMI_EIM_D_7
-175 MX35_PAD_D6__EMI_EIM_D_6
-176 MX35_PAD_D5__EMI_EIM_D_5
-177 MX35_PAD_D4__EMI_EIM_D_4
-178 MX35_PAD_D3__EMI_EIM_D_3
-179 MX35_PAD_D2__EMI_EIM_D_2
-180 MX35_PAD_D1__EMI_EIM_D_1
-181 MX35_PAD_D0__EMI_EIM_D_0
-182 MX35_PAD_CSI_D8__IPU_CSI_D_8
-183 MX35_PAD_CSI_D8__KPP_COL_0
-184 MX35_PAD_CSI_D8__GPIO1_20
-185 MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13
-186 MX35_PAD_CSI_D9__IPU_CSI_D_9
-187 MX35_PAD_CSI_D9__KPP_COL_1
-188 MX35_PAD_CSI_D9__GPIO1_21
-189 MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14
-190 MX35_PAD_CSI_D10__IPU_CSI_D_10
-191 MX35_PAD_CSI_D10__KPP_COL_2
-192 MX35_PAD_CSI_D10__GPIO1_22
-193 MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15
-194 MX35_PAD_CSI_D11__IPU_CSI_D_11
-195 MX35_PAD_CSI_D11__KPP_COL_3
-196 MX35_PAD_CSI_D11__GPIO1_23
-197 MX35_PAD_CSI_D12__IPU_CSI_D_12
-198 MX35_PAD_CSI_D12__KPP_ROW_0
-199 MX35_PAD_CSI_D12__GPIO1_24
-200 MX35_PAD_CSI_D13__IPU_CSI_D_13
-201 MX35_PAD_CSI_D13__KPP_ROW_1
-202 MX35_PAD_CSI_D13__GPIO1_25
-203 MX35_PAD_CSI_D14__IPU_CSI_D_14
-204 MX35_PAD_CSI_D14__KPP_ROW_2
-205 MX35_PAD_CSI_D14__GPIO1_26
-206 MX35_PAD_CSI_D15__IPU_CSI_D_15
-207 MX35_PAD_CSI_D15__KPP_ROW_3
-208 MX35_PAD_CSI_D15__GPIO1_27
-209 MX35_PAD_CSI_MCLK__IPU_CSI_MCLK
-210 MX35_PAD_CSI_MCLK__GPIO1_28
-211 MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC
-212 MX35_PAD_CSI_VSYNC__GPIO1_29
-213 MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC
-214 MX35_PAD_CSI_HSYNC__GPIO1_30
-215 MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK
-216 MX35_PAD_CSI_PIXCLK__GPIO1_31
-217 MX35_PAD_I2C1_CLK__I2C1_SCL
-218 MX35_PAD_I2C1_CLK__GPIO2_24
-219 MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK
-220 MX35_PAD_I2C1_DAT__I2C1_SDA
-221 MX35_PAD_I2C1_DAT__GPIO2_25
-222 MX35_PAD_I2C2_CLK__I2C2_SCL
-223 MX35_PAD_I2C2_CLK__CAN1_TXCAN
-224 MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR
-225 MX35_PAD_I2C2_CLK__GPIO2_26
-226 MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2
-227 MX35_PAD_I2C2_DAT__I2C2_SDA
-228 MX35_PAD_I2C2_DAT__CAN1_RXCAN
-229 MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC
-230 MX35_PAD_I2C2_DAT__GPIO2_27
-231 MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3
-232 MX35_PAD_STXD4__AUDMUX_AUD4_TXD
-233 MX35_PAD_STXD4__GPIO2_28
-234 MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0
-235 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD
-236 MX35_PAD_SRXD4__GPIO2_29
-237 MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1
-238 MX35_PAD_SCK4__AUDMUX_AUD4_TXC
-239 MX35_PAD_SCK4__GPIO2_30
-240 MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2
-241 MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS
-242 MX35_PAD_STXFS4__GPIO2_31
-243 MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3
-244 MX35_PAD_STXD5__AUDMUX_AUD5_TXD
-245 MX35_PAD_STXD5__SPDIF_SPDIF_OUT1
-246 MX35_PAD_STXD5__CSPI2_MOSI
-247 MX35_PAD_STXD5__GPIO1_0
-248 MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4
-249 MX35_PAD_SRXD5__AUDMUX_AUD5_RXD
-250 MX35_PAD_SRXD5__SPDIF_SPDIF_IN1
-251 MX35_PAD_SRXD5__CSPI2_MISO
-252 MX35_PAD_SRXD5__GPIO1_1
-253 MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5
-254 MX35_PAD_SCK5__AUDMUX_AUD5_TXC
-255 MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK
-256 MX35_PAD_SCK5__CSPI2_SCLK
-257 MX35_PAD_SCK5__GPIO1_2
-258 MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6
-259 MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS
-260 MX35_PAD_STXFS5__CSPI2_RDY
-261 MX35_PAD_STXFS5__GPIO1_3
-262 MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7
-263 MX35_PAD_SCKR__ESAI_SCKR
-264 MX35_PAD_SCKR__GPIO1_4
-265 MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10
-266 MX35_PAD_FSR__ESAI_FSR
-267 MX35_PAD_FSR__GPIO1_5
-268 MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11
-269 MX35_PAD_HCKR__ESAI_HCKR
-270 MX35_PAD_HCKR__AUDMUX_AUD5_RXFS
-271 MX35_PAD_HCKR__CSPI2_SS0
-272 MX35_PAD_HCKR__IPU_FLASH_STROBE
-273 MX35_PAD_HCKR__GPIO1_6
-274 MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12
-275 MX35_PAD_SCKT__ESAI_SCKT
-276 MX35_PAD_SCKT__GPIO1_7
-277 MX35_PAD_SCKT__IPU_CSI_D_0
-278 MX35_PAD_SCKT__KPP_ROW_2
-279 MX35_PAD_FST__ESAI_FST
-280 MX35_PAD_FST__GPIO1_8
-281 MX35_PAD_FST__IPU_CSI_D_1
-282 MX35_PAD_FST__KPP_ROW_3
-283 MX35_PAD_HCKT__ESAI_HCKT
-284 MX35_PAD_HCKT__AUDMUX_AUD5_RXC
-285 MX35_PAD_HCKT__GPIO1_9
-286 MX35_PAD_HCKT__IPU_CSI_D_2
-287 MX35_PAD_HCKT__KPP_COL_3
-288 MX35_PAD_TX5_RX0__ESAI_TX5_RX0
-289 MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC
-290 MX35_PAD_TX5_RX0__CSPI2_SS2
-291 MX35_PAD_TX5_RX0__CAN2_TXCAN
-292 MX35_PAD_TX5_RX0__UART2_DTR
-293 MX35_PAD_TX5_RX0__GPIO1_10
-294 MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0
-295 MX35_PAD_TX4_RX1__ESAI_TX4_RX1
-296 MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS
-297 MX35_PAD_TX4_RX1__CSPI2_SS3
-298 MX35_PAD_TX4_RX1__CAN2_RXCAN
-299 MX35_PAD_TX4_RX1__UART2_DSR
-300 MX35_PAD_TX4_RX1__GPIO1_11
-301 MX35_PAD_TX4_RX1__IPU_CSI_D_3
-302 MX35_PAD_TX4_RX1__KPP_ROW_0
-303 MX35_PAD_TX3_RX2__ESAI_TX3_RX2
-304 MX35_PAD_TX3_RX2__I2C3_SCL
-305 MX35_PAD_TX3_RX2__EMI_NANDF_CE1
-306 MX35_PAD_TX3_RX2__GPIO1_12
-307 MX35_PAD_TX3_RX2__IPU_CSI_D_4
-308 MX35_PAD_TX3_RX2__KPP_ROW_1
-309 MX35_PAD_TX2_RX3__ESAI_TX2_RX3
-310 MX35_PAD_TX2_RX3__I2C3_SDA
-311 MX35_PAD_TX2_RX3__EMI_NANDF_CE2
-312 MX35_PAD_TX2_RX3__GPIO1_13
-313 MX35_PAD_TX2_RX3__IPU_CSI_D_5
-314 MX35_PAD_TX2_RX3__KPP_COL_0
-315 MX35_PAD_TX1__ESAI_TX1
-316 MX35_PAD_TX1__CCM_PMIC_RDY
-317 MX35_PAD_TX1__CSPI1_SS2
-318 MX35_PAD_TX1__EMI_NANDF_CE3
-319 MX35_PAD_TX1__UART2_RI
-320 MX35_PAD_TX1__GPIO1_14
-321 MX35_PAD_TX1__IPU_CSI_D_6
-322 MX35_PAD_TX1__KPP_COL_1
-323 MX35_PAD_TX0__ESAI_TX0
-324 MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK
-325 MX35_PAD_TX0__CSPI1_SS3
-326 MX35_PAD_TX0__EMI_DTACK_B
-327 MX35_PAD_TX0__UART2_DCD
-328 MX35_PAD_TX0__GPIO1_15
-329 MX35_PAD_TX0__IPU_CSI_D_7
-330 MX35_PAD_TX0__KPP_COL_2
-331 MX35_PAD_CSPI1_MOSI__CSPI1_MOSI
-332 MX35_PAD_CSPI1_MOSI__GPIO1_16
-333 MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2
-334 MX35_PAD_CSPI1_MISO__CSPI1_MISO
-335 MX35_PAD_CSPI1_MISO__GPIO1_17
-336 MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3
-337 MX35_PAD_CSPI1_SS0__CSPI1_SS0
-338 MX35_PAD_CSPI1_SS0__OWIRE_LINE
-339 MX35_PAD_CSPI1_SS0__CSPI2_SS3
-340 MX35_PAD_CSPI1_SS0__GPIO1_18
-341 MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4
-342 MX35_PAD_CSPI1_SS1__CSPI1_SS1
-343 MX35_PAD_CSPI1_SS1__PWM_PWMO
-344 MX35_PAD_CSPI1_SS1__CCM_CLK32K
-345 MX35_PAD_CSPI1_SS1__GPIO1_19
-346 MX35_PAD_CSPI1_SS1__IPU_DIAGB_29
-347 MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5
-348 MX35_PAD_CSPI1_SCLK__CSPI1_SCLK
-349 MX35_PAD_CSPI1_SCLK__GPIO3_4
-350 MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30
-351 MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1
-352 MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY
-353 MX35_PAD_CSPI1_SPI_RDY__GPIO3_5
-354 MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31
-355 MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2
-356 MX35_PAD_RXD1__UART1_RXD_MUX
-357 MX35_PAD_RXD1__CSPI2_MOSI
-358 MX35_PAD_RXD1__KPP_COL_4
-359 MX35_PAD_RXD1__GPIO3_6
-360 MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16
-361 MX35_PAD_TXD1__UART1_TXD_MUX
-362 MX35_PAD_TXD1__CSPI2_MISO
-363 MX35_PAD_TXD1__KPP_COL_5
-364 MX35_PAD_TXD1__GPIO3_7
-365 MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17
-366 MX35_PAD_RTS1__UART1_RTS
-367 MX35_PAD_RTS1__CSPI2_SCLK
-368 MX35_PAD_RTS1__I2C3_SCL
-369 MX35_PAD_RTS1__IPU_CSI_D_0
-370 MX35_PAD_RTS1__KPP_COL_6
-371 MX35_PAD_RTS1__GPIO3_8
-372 MX35_PAD_RTS1__EMI_NANDF_CE1
-373 MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18
-374 MX35_PAD_CTS1__UART1_CTS
-375 MX35_PAD_CTS1__CSPI2_RDY
-376 MX35_PAD_CTS1__I2C3_SDA
-377 MX35_PAD_CTS1__IPU_CSI_D_1
-378 MX35_PAD_CTS1__KPP_COL_7
-379 MX35_PAD_CTS1__GPIO3_9
-380 MX35_PAD_CTS1__EMI_NANDF_CE2
-381 MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19
-382 MX35_PAD_RXD2__UART2_RXD_MUX
-383 MX35_PAD_RXD2__KPP_ROW_4
-384 MX35_PAD_RXD2__GPIO3_10
-385 MX35_PAD_TXD2__UART2_TXD_MUX
-386 MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK
-387 MX35_PAD_TXD2__KPP_ROW_5
-388 MX35_PAD_TXD2__GPIO3_11
-389 MX35_PAD_RTS2__UART2_RTS
-390 MX35_PAD_RTS2__SPDIF_SPDIF_IN1
-391 MX35_PAD_RTS2__CAN2_RXCAN
-392 MX35_PAD_RTS2__IPU_CSI_D_2
-393 MX35_PAD_RTS2__KPP_ROW_6
-394 MX35_PAD_RTS2__GPIO3_12
-395 MX35_PAD_RTS2__AUDMUX_AUD5_RXC
-396 MX35_PAD_RTS2__UART3_RXD_MUX
-397 MX35_PAD_CTS2__UART2_CTS
-398 MX35_PAD_CTS2__SPDIF_SPDIF_OUT1
-399 MX35_PAD_CTS2__CAN2_TXCAN
-400 MX35_PAD_CTS2__IPU_CSI_D_3
-401 MX35_PAD_CTS2__KPP_ROW_7
-402 MX35_PAD_CTS2__GPIO3_13
-403 MX35_PAD_CTS2__AUDMUX_AUD5_RXFS
-404 MX35_PAD_CTS2__UART3_TXD_MUX
-405 MX35_PAD_RTCK__ARM11P_TOP_RTCK
-406 MX35_PAD_TCK__SJC_TCK
-407 MX35_PAD_TMS__SJC_TMS
-408 MX35_PAD_TDI__SJC_TDI
-409 MX35_PAD_TDO__SJC_TDO
-410 MX35_PAD_TRSTB__SJC_TRSTB
-411 MX35_PAD_DE_B__SJC_DE_B
-412 MX35_PAD_SJC_MOD__SJC_MOD
-413 MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR
-414 MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR
-415 MX35_PAD_USBOTG_PWR__GPIO3_14
-416 MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC
-417 MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC
-418 MX35_PAD_USBOTG_OC__GPIO3_15
-419 MX35_PAD_LD0__IPU_DISPB_DAT_0
-420 MX35_PAD_LD0__GPIO2_0
-421 MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0
-422 MX35_PAD_LD1__IPU_DISPB_DAT_1
-423 MX35_PAD_LD1__GPIO2_1
-424 MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1
-425 MX35_PAD_LD2__IPU_DISPB_DAT_2
-426 MX35_PAD_LD2__GPIO2_2
-427 MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2
-428 MX35_PAD_LD3__IPU_DISPB_DAT_3
-429 MX35_PAD_LD3__GPIO2_3
-430 MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3
-431 MX35_PAD_LD4__IPU_DISPB_DAT_4
-432 MX35_PAD_LD4__GPIO2_4
-433 MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4
-434 MX35_PAD_LD5__IPU_DISPB_DAT_5
-435 MX35_PAD_LD5__GPIO2_5
-436 MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5
-437 MX35_PAD_LD6__IPU_DISPB_DAT_6
-438 MX35_PAD_LD6__GPIO2_6
-439 MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6
-440 MX35_PAD_LD7__IPU_DISPB_DAT_7
-441 MX35_PAD_LD7__GPIO2_7
-442 MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7
-443 MX35_PAD_LD8__IPU_DISPB_DAT_8
-444 MX35_PAD_LD8__GPIO2_8
-445 MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8
-446 MX35_PAD_LD9__IPU_DISPB_DAT_9
-447 MX35_PAD_LD9__GPIO2_9
-448 MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9
-449 MX35_PAD_LD10__IPU_DISPB_DAT_10
-450 MX35_PAD_LD10__GPIO2_10
-451 MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10
-452 MX35_PAD_LD11__IPU_DISPB_DAT_11
-453 MX35_PAD_LD11__GPIO2_11
-454 MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11
-455 MX35_PAD_LD11__ARM11P_TOP_TRACE_4
-456 MX35_PAD_LD12__IPU_DISPB_DAT_12
-457 MX35_PAD_LD12__GPIO2_12
-458 MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12
-459 MX35_PAD_LD12__ARM11P_TOP_TRACE_5
-460 MX35_PAD_LD13__IPU_DISPB_DAT_13
-461 MX35_PAD_LD13__GPIO2_13
-462 MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13
-463 MX35_PAD_LD13__ARM11P_TOP_TRACE_6
-464 MX35_PAD_LD14__IPU_DISPB_DAT_14
-465 MX35_PAD_LD14__GPIO2_14
-466 MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0
-467 MX35_PAD_LD14__ARM11P_TOP_TRACE_7
-468 MX35_PAD_LD15__IPU_DISPB_DAT_15
-469 MX35_PAD_LD15__GPIO2_15
-470 MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1
-471 MX35_PAD_LD15__ARM11P_TOP_TRACE_8
-472 MX35_PAD_LD16__IPU_DISPB_DAT_16
-473 MX35_PAD_LD16__IPU_DISPB_D12_VSYNC
-474 MX35_PAD_LD16__GPIO2_16
-475 MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2
-476 MX35_PAD_LD16__ARM11P_TOP_TRACE_9
-477 MX35_PAD_LD17__IPU_DISPB_DAT_17
-478 MX35_PAD_LD17__IPU_DISPB_CS2
-479 MX35_PAD_LD17__GPIO2_17
-480 MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3
-481 MX35_PAD_LD17__ARM11P_TOP_TRACE_10
-482 MX35_PAD_LD18__IPU_DISPB_DAT_18
-483 MX35_PAD_LD18__IPU_DISPB_D0_VSYNC
-484 MX35_PAD_LD18__IPU_DISPB_D12_VSYNC
-485 MX35_PAD_LD18__ESDHC3_CMD
-486 MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3
-487 MX35_PAD_LD18__GPIO3_24
-488 MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4
-489 MX35_PAD_LD18__ARM11P_TOP_TRACE_11
-490 MX35_PAD_LD19__IPU_DISPB_DAT_19
-491 MX35_PAD_LD19__IPU_DISPB_BCLK
-492 MX35_PAD_LD19__IPU_DISPB_CS1
-493 MX35_PAD_LD19__ESDHC3_CLK
-494 MX35_PAD_LD19__USB_TOP_USBOTG_DIR
-495 MX35_PAD_LD19__GPIO3_25
-496 MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5
-497 MX35_PAD_LD19__ARM11P_TOP_TRACE_12
-498 MX35_PAD_LD20__IPU_DISPB_DAT_20
-499 MX35_PAD_LD20__IPU_DISPB_CS0
-500 MX35_PAD_LD20__IPU_DISPB_SD_CLK
-501 MX35_PAD_LD20__ESDHC3_DAT0
-502 MX35_PAD_LD20__GPIO3_26
-503 MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3
-504 MX35_PAD_LD20__ARM11P_TOP_TRACE_13
-505 MX35_PAD_LD21__IPU_DISPB_DAT_21
-506 MX35_PAD_LD21__IPU_DISPB_PAR_RS
-507 MX35_PAD_LD21__IPU_DISPB_SER_RS
-508 MX35_PAD_LD21__ESDHC3_DAT1
-509 MX35_PAD_LD21__USB_TOP_USBOTG_STP
-510 MX35_PAD_LD21__GPIO3_27
-511 MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL
-512 MX35_PAD_LD21__ARM11P_TOP_TRACE_14
-513 MX35_PAD_LD22__IPU_DISPB_DAT_22
-514 MX35_PAD_LD22__IPU_DISPB_WR
-515 MX35_PAD_LD22__IPU_DISPB_SD_D_I
-516 MX35_PAD_LD22__ESDHC3_DAT2
-517 MX35_PAD_LD22__USB_TOP_USBOTG_NXT
-518 MX35_PAD_LD22__GPIO3_28
-519 MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR
-520 MX35_PAD_LD22__ARM11P_TOP_TRCTL
-521 MX35_PAD_LD23__IPU_DISPB_DAT_23
-522 MX35_PAD_LD23__IPU_DISPB_RD
-523 MX35_PAD_LD23__IPU_DISPB_SD_D_IO
-524 MX35_PAD_LD23__ESDHC3_DAT3
-525 MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7
-526 MX35_PAD_LD23__GPIO3_29
-527 MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS
-528 MX35_PAD_LD23__ARM11P_TOP_TRCLK
-529 MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC
-530 MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO
-531 MX35_PAD_D3_HSYNC__GPIO3_30
-532 MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE
-533 MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15
-534 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK
-535 MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK
-536 MX35_PAD_D3_FPSHIFT__GPIO3_31
-537 MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0
-538 MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16
-539 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY
-540 MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O
-541 MX35_PAD_D3_DRDY__GPIO1_0
-542 MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1
-543 MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17
-544 MX35_PAD_CONTRAST__IPU_DISPB_CONTR
-545 MX35_PAD_CONTRAST__GPIO1_1
-546 MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2
-547 MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18
-548 MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC
-549 MX35_PAD_D3_VSYNC__IPU_DISPB_CS1
-550 MX35_PAD_D3_VSYNC__GPIO1_2
-551 MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD
-552 MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19
-553 MX35_PAD_D3_REV__IPU_DISPB_D3_REV
-554 MX35_PAD_D3_REV__IPU_DISPB_SER_RS
-555 MX35_PAD_D3_REV__GPIO1_3
-556 MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB
-557 MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20
-558 MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS
-559 MX35_PAD_D3_CLS__IPU_DISPB_CS2
-560 MX35_PAD_D3_CLS__GPIO1_4
-561 MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0
-562 MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21
-563 MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL
-564 MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC
-565 MX35_PAD_D3_SPL__GPIO1_5
-566 MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1
-567 MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22
-568 MX35_PAD_SD1_CMD__ESDHC1_CMD
-569 MX35_PAD_SD1_CMD__MSHC_SCLK
-570 MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC
-571 MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4
-572 MX35_PAD_SD1_CMD__GPIO1_6
-573 MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL
-574 MX35_PAD_SD1_CLK__ESDHC1_CLK
-575 MX35_PAD_SD1_CLK__MSHC_BS
-576 MX35_PAD_SD1_CLK__IPU_DISPB_BCLK
-577 MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5
-578 MX35_PAD_SD1_CLK__GPIO1_7
-579 MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK
-580 MX35_PAD_SD1_DATA0__ESDHC1_DAT0
-581 MX35_PAD_SD1_DATA0__MSHC_DATA_0
-582 MX35_PAD_SD1_DATA0__IPU_DISPB_CS0
-583 MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6
-584 MX35_PAD_SD1_DATA0__GPIO1_8
-585 MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23
-586 MX35_PAD_SD1_DATA1__ESDHC1_DAT1
-587 MX35_PAD_SD1_DATA1__MSHC_DATA_1
-588 MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS
-589 MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0
-590 MX35_PAD_SD1_DATA1__GPIO1_9
-591 MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24
-592 MX35_PAD_SD1_DATA2__ESDHC1_DAT2
-593 MX35_PAD_SD1_DATA2__MSHC_DATA_2
-594 MX35_PAD_SD1_DATA2__IPU_DISPB_WR
-595 MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1
-596 MX35_PAD_SD1_DATA2__GPIO1_10
-597 MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25
-598 MX35_PAD_SD1_DATA3__ESDHC1_DAT3
-599 MX35_PAD_SD1_DATA3__MSHC_DATA_3
-600 MX35_PAD_SD1_DATA3__IPU_DISPB_RD
-601 MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2
-602 MX35_PAD_SD1_DATA3__GPIO1_11
-603 MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26
-604 MX35_PAD_SD2_CMD__ESDHC2_CMD
-605 MX35_PAD_SD2_CMD__I2C3_SCL
-606 MX35_PAD_SD2_CMD__ESDHC1_DAT4
-607 MX35_PAD_SD2_CMD__IPU_CSI_D_2
-608 MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4
-609 MX35_PAD_SD2_CMD__GPIO2_0
-610 MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1
-611 MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC
-612 MX35_PAD_SD2_CLK__ESDHC2_CLK
-613 MX35_PAD_SD2_CLK__I2C3_SDA
-614 MX35_PAD_SD2_CLK__ESDHC1_DAT5
-615 MX35_PAD_SD2_CLK__IPU_CSI_D_3
-616 MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5
-617 MX35_PAD_SD2_CLK__GPIO2_1
-618 MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1
-619 MX35_PAD_SD2_CLK__IPU_DISPB_CS2
-620 MX35_PAD_SD2_DATA0__ESDHC2_DAT0
-621 MX35_PAD_SD2_DATA0__UART3_RXD_MUX
-622 MX35_PAD_SD2_DATA0__ESDHC1_DAT6
-623 MX35_PAD_SD2_DATA0__IPU_CSI_D_4
-624 MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6
-625 MX35_PAD_SD2_DATA0__GPIO2_2
-626 MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK
-627 MX35_PAD_SD2_DATA1__ESDHC2_DAT1
-628 MX35_PAD_SD2_DATA1__UART3_TXD_MUX
-629 MX35_PAD_SD2_DATA1__ESDHC1_DAT7
-630 MX35_PAD_SD2_DATA1__IPU_CSI_D_5
-631 MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0
-632 MX35_PAD_SD2_DATA1__GPIO2_3
-633 MX35_PAD_SD2_DATA2__ESDHC2_DAT2
-634 MX35_PAD_SD2_DATA2__UART3_RTS
-635 MX35_PAD_SD2_DATA2__CAN1_RXCAN
-636 MX35_PAD_SD2_DATA2__IPU_CSI_D_6
-637 MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1
-638 MX35_PAD_SD2_DATA2__GPIO2_4
-639 MX35_PAD_SD2_DATA3__ESDHC2_DAT3
-640 MX35_PAD_SD2_DATA3__UART3_CTS
-641 MX35_PAD_SD2_DATA3__CAN1_TXCAN
-642 MX35_PAD_SD2_DATA3__IPU_CSI_D_7
-643 MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2
-644 MX35_PAD_SD2_DATA3__GPIO2_5
-645 MX35_PAD_ATA_CS0__ATA_CS0
-646 MX35_PAD_ATA_CS0__CSPI1_SS3
-647 MX35_PAD_ATA_CS0__IPU_DISPB_CS1
-648 MX35_PAD_ATA_CS0__GPIO2_6
-649 MX35_PAD_ATA_CS0__IPU_DIAGB_0
-650 MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0
-651 MX35_PAD_ATA_CS1__ATA_CS1
-652 MX35_PAD_ATA_CS1__IPU_DISPB_CS2
-653 MX35_PAD_ATA_CS1__CSPI2_SS0
-654 MX35_PAD_ATA_CS1__GPIO2_7
-655 MX35_PAD_ATA_CS1__IPU_DIAGB_1
-656 MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1
-657 MX35_PAD_ATA_DIOR__ATA_DIOR
-658 MX35_PAD_ATA_DIOR__ESDHC3_DAT0
-659 MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR
-660 MX35_PAD_ATA_DIOR__IPU_DISPB_BE0
-661 MX35_PAD_ATA_DIOR__CSPI2_SS1
-662 MX35_PAD_ATA_DIOR__GPIO2_8
-663 MX35_PAD_ATA_DIOR__IPU_DIAGB_2
-664 MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2
-665 MX35_PAD_ATA_DIOW__ATA_DIOW
-666 MX35_PAD_ATA_DIOW__ESDHC3_DAT1
-667 MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP
-668 MX35_PAD_ATA_DIOW__IPU_DISPB_BE1
-669 MX35_PAD_ATA_DIOW__CSPI2_MOSI
-670 MX35_PAD_ATA_DIOW__GPIO2_9
-671 MX35_PAD_ATA_DIOW__IPU_DIAGB_3
-672 MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3
-673 MX35_PAD_ATA_DMACK__ATA_DMACK
-674 MX35_PAD_ATA_DMACK__ESDHC3_DAT2
-675 MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT
-676 MX35_PAD_ATA_DMACK__CSPI2_MISO
-677 MX35_PAD_ATA_DMACK__GPIO2_10
-678 MX35_PAD_ATA_DMACK__IPU_DIAGB_4
-679 MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0
-680 MX35_PAD_ATA_RESET_B__ATA_RESET_B
-681 MX35_PAD_ATA_RESET_B__ESDHC3_DAT3
-682 MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0
-683 MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O
-684 MX35_PAD_ATA_RESET_B__CSPI2_RDY
-685 MX35_PAD_ATA_RESET_B__GPIO2_11
-686 MX35_PAD_ATA_RESET_B__IPU_DIAGB_5
-687 MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1
-688 MX35_PAD_ATA_IORDY__ATA_IORDY
-689 MX35_PAD_ATA_IORDY__ESDHC3_DAT4
-690 MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1
-691 MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO
-692 MX35_PAD_ATA_IORDY__ESDHC2_DAT4
-693 MX35_PAD_ATA_IORDY__GPIO2_12
-694 MX35_PAD_ATA_IORDY__IPU_DIAGB_6
-695 MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2
-696 MX35_PAD_ATA_DATA0__ATA_DATA_0
-697 MX35_PAD_ATA_DATA0__ESDHC3_DAT5
-698 MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2
-699 MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC
-700 MX35_PAD_ATA_DATA0__ESDHC2_DAT5
-701 MX35_PAD_ATA_DATA0__GPIO2_13
-702 MX35_PAD_ATA_DATA0__IPU_DIAGB_7
-703 MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3
-704 MX35_PAD_ATA_DATA1__ATA_DATA_1
-705 MX35_PAD_ATA_DATA1__ESDHC3_DAT6
-706 MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3
-707 MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK
-708 MX35_PAD_ATA_DATA1__ESDHC2_DAT6
-709 MX35_PAD_ATA_DATA1__GPIO2_14
-710 MX35_PAD_ATA_DATA1__IPU_DIAGB_8
-711 MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27
-712 MX35_PAD_ATA_DATA2__ATA_DATA_2
-713 MX35_PAD_ATA_DATA2__ESDHC3_DAT7
-714 MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4
-715 MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS
-716 MX35_PAD_ATA_DATA2__ESDHC2_DAT7
-717 MX35_PAD_ATA_DATA2__GPIO2_15
-718 MX35_PAD_ATA_DATA2__IPU_DIAGB_9
-719 MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28
-720 MX35_PAD_ATA_DATA3__ATA_DATA_3
-721 MX35_PAD_ATA_DATA3__ESDHC3_CLK
-722 MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5
-723 MX35_PAD_ATA_DATA3__CSPI2_SCLK
-724 MX35_PAD_ATA_DATA3__GPIO2_16
-725 MX35_PAD_ATA_DATA3__IPU_DIAGB_10
-726 MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29
-727 MX35_PAD_ATA_DATA4__ATA_DATA_4
-728 MX35_PAD_ATA_DATA4__ESDHC3_CMD
-729 MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6
-730 MX35_PAD_ATA_DATA4__GPIO2_17
-731 MX35_PAD_ATA_DATA4__IPU_DIAGB_11
-732 MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30
-733 MX35_PAD_ATA_DATA5__ATA_DATA_5
-734 MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7
-735 MX35_PAD_ATA_DATA5__GPIO2_18
-736 MX35_PAD_ATA_DATA5__IPU_DIAGB_12
-737 MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31
-738 MX35_PAD_ATA_DATA6__ATA_DATA_6
-739 MX35_PAD_ATA_DATA6__CAN1_TXCAN
-740 MX35_PAD_ATA_DATA6__UART1_DTR
-741 MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD
-742 MX35_PAD_ATA_DATA6__GPIO2_19
-743 MX35_PAD_ATA_DATA6__IPU_DIAGB_13
-744 MX35_PAD_ATA_DATA7__ATA_DATA_7
-745 MX35_PAD_ATA_DATA7__CAN1_RXCAN
-746 MX35_PAD_ATA_DATA7__UART1_DSR
-747 MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD
-748 MX35_PAD_ATA_DATA7__GPIO2_20
-749 MX35_PAD_ATA_DATA7__IPU_DIAGB_14
-750 MX35_PAD_ATA_DATA8__ATA_DATA_8
-751 MX35_PAD_ATA_DATA8__UART3_RTS
-752 MX35_PAD_ATA_DATA8__UART1_RI
-753 MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC
-754 MX35_PAD_ATA_DATA8__GPIO2_21
-755 MX35_PAD_ATA_DATA8__IPU_DIAGB_15
-756 MX35_PAD_ATA_DATA9__ATA_DATA_9
-757 MX35_PAD_ATA_DATA9__UART3_CTS
-758 MX35_PAD_ATA_DATA9__UART1_DCD
-759 MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS
-760 MX35_PAD_ATA_DATA9__GPIO2_22
-761 MX35_PAD_ATA_DATA9__IPU_DIAGB_16
-762 MX35_PAD_ATA_DATA10__ATA_DATA_10
-763 MX35_PAD_ATA_DATA10__UART3_RXD_MUX
-764 MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC
-765 MX35_PAD_ATA_DATA10__GPIO2_23
-766 MX35_PAD_ATA_DATA10__IPU_DIAGB_17
-767 MX35_PAD_ATA_DATA11__ATA_DATA_11
-768 MX35_PAD_ATA_DATA11__UART3_TXD_MUX
-769 MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS
-770 MX35_PAD_ATA_DATA11__GPIO2_24
-771 MX35_PAD_ATA_DATA11__IPU_DIAGB_18
-772 MX35_PAD_ATA_DATA12__ATA_DATA_12
-773 MX35_PAD_ATA_DATA12__I2C3_SCL
-774 MX35_PAD_ATA_DATA12__GPIO2_25
-775 MX35_PAD_ATA_DATA12__IPU_DIAGB_19
-776 MX35_PAD_ATA_DATA13__ATA_DATA_13
-777 MX35_PAD_ATA_DATA13__I2C3_SDA
-778 MX35_PAD_ATA_DATA13__GPIO2_26
-779 MX35_PAD_ATA_DATA13__IPU_DIAGB_20
-780 MX35_PAD_ATA_DATA14__ATA_DATA_14
-781 MX35_PAD_ATA_DATA14__IPU_CSI_D_0
-782 MX35_PAD_ATA_DATA14__KPP_ROW_0
-783 MX35_PAD_ATA_DATA14__GPIO2_27
-784 MX35_PAD_ATA_DATA14__IPU_DIAGB_21
-785 MX35_PAD_ATA_DATA15__ATA_DATA_15
-786 MX35_PAD_ATA_DATA15__IPU_CSI_D_1
-787 MX35_PAD_ATA_DATA15__KPP_ROW_1
-788 MX35_PAD_ATA_DATA15__GPIO2_28
-789 MX35_PAD_ATA_DATA15__IPU_DIAGB_22
-790 MX35_PAD_ATA_INTRQ__ATA_INTRQ
-791 MX35_PAD_ATA_INTRQ__IPU_CSI_D_2
-792 MX35_PAD_ATA_INTRQ__KPP_ROW_2
-793 MX35_PAD_ATA_INTRQ__GPIO2_29
-794 MX35_PAD_ATA_INTRQ__IPU_DIAGB_23
-795 MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN
-796 MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3
-797 MX35_PAD_ATA_BUFF_EN__KPP_ROW_3
-798 MX35_PAD_ATA_BUFF_EN__GPIO2_30
-799 MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24
-800 MX35_PAD_ATA_DMARQ__ATA_DMARQ
-801 MX35_PAD_ATA_DMARQ__IPU_CSI_D_4
-802 MX35_PAD_ATA_DMARQ__KPP_COL_0
-803 MX35_PAD_ATA_DMARQ__GPIO2_31
-804 MX35_PAD_ATA_DMARQ__IPU_DIAGB_25
-805 MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4
-806 MX35_PAD_ATA_DA0__ATA_DA_0
-807 MX35_PAD_ATA_DA0__IPU_CSI_D_5
-808 MX35_PAD_ATA_DA0__KPP_COL_1
-809 MX35_PAD_ATA_DA0__GPIO3_0
-810 MX35_PAD_ATA_DA0__IPU_DIAGB_26
-811 MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5
-812 MX35_PAD_ATA_DA1__ATA_DA_1
-813 MX35_PAD_ATA_DA1__IPU_CSI_D_6
-814 MX35_PAD_ATA_DA1__KPP_COL_2
-815 MX35_PAD_ATA_DA1__GPIO3_1
-816 MX35_PAD_ATA_DA1__IPU_DIAGB_27
-817 MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6
-818 MX35_PAD_ATA_DA2__ATA_DA_2
-819 MX35_PAD_ATA_DA2__IPU_CSI_D_7
-820 MX35_PAD_ATA_DA2__KPP_COL_3
-821 MX35_PAD_ATA_DA2__GPIO3_2
-822 MX35_PAD_ATA_DA2__IPU_DIAGB_28
-823 MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7
-824 MX35_PAD_MLB_CLK__MLB_MLBCLK
-825 MX35_PAD_MLB_CLK__GPIO3_3
-826 MX35_PAD_MLB_DAT__MLB_MLBDAT
-827 MX35_PAD_MLB_DAT__GPIO3_4
-828 MX35_PAD_MLB_SIG__MLB_MLBSIG
-829 MX35_PAD_MLB_SIG__GPIO3_5
-830 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK
-831 MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4
-832 MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX
-833 MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR
-834 MX35_PAD_FEC_TX_CLK__CSPI2_MOSI
-835 MX35_PAD_FEC_TX_CLK__GPIO3_6
-836 MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC
-837 MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0
-838 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK
-839 MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5
-840 MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX
-841 MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP
-842 MX35_PAD_FEC_RX_CLK__CSPI2_MISO
-843 MX35_PAD_FEC_RX_CLK__GPIO3_7
-844 MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I
-845 MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1
-846 MX35_PAD_FEC_RX_DV__FEC_RX_DV
-847 MX35_PAD_FEC_RX_DV__ESDHC1_DAT6
-848 MX35_PAD_FEC_RX_DV__UART3_RTS
-849 MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT
-850 MX35_PAD_FEC_RX_DV__CSPI2_SCLK
-851 MX35_PAD_FEC_RX_DV__GPIO3_8
-852 MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK
-853 MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2
-854 MX35_PAD_FEC_COL__FEC_COL
-855 MX35_PAD_FEC_COL__ESDHC1_DAT7
-856 MX35_PAD_FEC_COL__UART3_CTS
-857 MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0
-858 MX35_PAD_FEC_COL__CSPI2_RDY
-859 MX35_PAD_FEC_COL__GPIO3_9
-860 MX35_PAD_FEC_COL__IPU_DISPB_SER_RS
-861 MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3
-862 MX35_PAD_FEC_RDATA0__FEC_RDATA_0
-863 MX35_PAD_FEC_RDATA0__PWM_PWMO
-864 MX35_PAD_FEC_RDATA0__UART3_DTR
-865 MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1
-866 MX35_PAD_FEC_RDATA0__CSPI2_SS0
-867 MX35_PAD_FEC_RDATA0__GPIO3_10
-868 MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1
-869 MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4
-870 MX35_PAD_FEC_TDATA0__FEC_TDATA_0
-871 MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1
-872 MX35_PAD_FEC_TDATA0__UART3_DSR
-873 MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2
-874 MX35_PAD_FEC_TDATA0__CSPI2_SS1
-875 MX35_PAD_FEC_TDATA0__GPIO3_11
-876 MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0
-877 MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5
-878 MX35_PAD_FEC_TX_EN__FEC_TX_EN
-879 MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1
-880 MX35_PAD_FEC_TX_EN__UART3_RI
-881 MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3
-882 MX35_PAD_FEC_TX_EN__GPIO3_12
-883 MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS
-884 MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6
-885 MX35_PAD_FEC_MDC__FEC_MDC
-886 MX35_PAD_FEC_MDC__CAN2_TXCAN
-887 MX35_PAD_FEC_MDC__UART3_DCD
-888 MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4
-889 MX35_PAD_FEC_MDC__GPIO3_13
-890 MX35_PAD_FEC_MDC__IPU_DISPB_WR
-891 MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7
-892 MX35_PAD_FEC_MDIO__FEC_MDIO
-893 MX35_PAD_FEC_MDIO__CAN2_RXCAN
-894 MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5
-895 MX35_PAD_FEC_MDIO__GPIO3_14
-896 MX35_PAD_FEC_MDIO__IPU_DISPB_RD
-897 MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8
-898 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR
-899 MX35_PAD_FEC_TX_ERR__OWIRE_LINE
-900 MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK
-901 MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6
-902 MX35_PAD_FEC_TX_ERR__GPIO3_15
-903 MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC
-904 MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9
-905 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR
-906 MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0
-907 MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7
-908 MX35_PAD_FEC_RX_ERR__KPP_COL_4
-909 MX35_PAD_FEC_RX_ERR__GPIO3_16
-910 MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO
-911 MX35_PAD_FEC_CRS__FEC_CRS
-912 MX35_PAD_FEC_CRS__IPU_CSI_D_1
-913 MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR
-914 MX35_PAD_FEC_CRS__KPP_COL_5
-915 MX35_PAD_FEC_CRS__GPIO3_17
-916 MX35_PAD_FEC_CRS__IPU_FLASH_STROBE
-917 MX35_PAD_FEC_RDATA1__FEC_RDATA_1
-918 MX35_PAD_FEC_RDATA1__IPU_CSI_D_2
-919 MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC
-920 MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC
-921 MX35_PAD_FEC_RDATA1__KPP_COL_6
-922 MX35_PAD_FEC_RDATA1__GPIO3_18
-923 MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0
-924 MX35_PAD_FEC_TDATA1__FEC_TDATA_1
-925 MX35_PAD_FEC_TDATA1__IPU_CSI_D_3
-926 MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS
-927 MX35_PAD_FEC_TDATA1__KPP_COL_7
-928 MX35_PAD_FEC_TDATA1__GPIO3_19
-929 MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1
-930 MX35_PAD_FEC_RDATA2__FEC_RDATA_2
-931 MX35_PAD_FEC_RDATA2__IPU_CSI_D_4
-932 MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD
-933 MX35_PAD_FEC_RDATA2__KPP_ROW_4
-934 MX35_PAD_FEC_RDATA2__GPIO3_20
-935 MX35_PAD_FEC_TDATA2__FEC_TDATA_2
-936 MX35_PAD_FEC_TDATA2__IPU_CSI_D_5
-937 MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD
-938 MX35_PAD_FEC_TDATA2__KPP_ROW_5
-939 MX35_PAD_FEC_TDATA2__GPIO3_21
-940 MX35_PAD_FEC_RDATA3__FEC_RDATA_3
-941 MX35_PAD_FEC_RDATA3__IPU_CSI_D_6
-942 MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC
-943 MX35_PAD_FEC_RDATA3__KPP_ROW_6
-944 MX35_PAD_FEC_RDATA3__GPIO3_22
-945 MX35_PAD_FEC_TDATA3__FEC_TDATA_3
-946 MX35_PAD_FEC_TDATA3__IPU_CSI_D_7
-947 MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS
-948 MX35_PAD_FEC_TDATA3__KPP_ROW_7
-949 MX35_PAD_FEC_TDATA3__GPIO3_23
-950 MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK
-951 MX35_PAD_TEST_MODE__TCU_TEST_MODE
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt
deleted file mode 100644
index b96fa4c3174..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt
+++ /dev/null
@@ -1,787 +0,0 @@
-* Freescale IMX51 IOMUX Controller
-
-Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
-and usage.
-
-Required properties:
-- compatible: "fsl,imx51-iomuxc"
-- fsl,pins: two integers array, represents a group of pins mux and config
-  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
-  pin working on a specific function, CONFIG is the pad setting value like
-  pull-up for this pin. Please refer to imx51 datasheet for the valid pad
-  config settings.
-
-CONFIG bits definition:
-PAD_CTL_HVE                     (1 << 13)
-PAD_CTL_HYS                     (1 << 8)
-PAD_CTL_PKE                     (1 << 7)
-PAD_CTL_PUE                     (1 << 6)
-PAD_CTL_PUS_100K_DOWN           (0 << 4)
-PAD_CTL_PUS_47K_UP              (1 << 4)
-PAD_CTL_PUS_100K_UP             (2 << 4)
-PAD_CTL_PUS_22K_UP              (3 << 4)
-PAD_CTL_ODE                     (1 << 3)
-PAD_CTL_DSE_LOW                 (0 << 1)
-PAD_CTL_DSE_MED                 (1 << 1)
-PAD_CTL_DSE_HIGH                (2 << 1)
-PAD_CTL_DSE_MAX                 (3 << 1)
-PAD_CTL_SRE_FAST                (1 << 0)
-PAD_CTL_SRE_SLOW                (0 << 0)
-
-See below for available PIN_FUNC_ID for imx51:
-MX51_PAD_EIM_D16__AUD4_RXFS                     0
-MX51_PAD_EIM_D16__AUD5_TXD                      1
-MX51_PAD_EIM_D16__EIM_D16                       2
-MX51_PAD_EIM_D16__GPIO2_0                       3
-MX51_PAD_EIM_D16__I2C1_SDA                      4
-MX51_PAD_EIM_D16__UART2_CTS                     5
-MX51_PAD_EIM_D16__USBH2_DATA0                   6
-MX51_PAD_EIM_D17__AUD5_RXD                      7
-MX51_PAD_EIM_D17__EIM_D17                       8
-MX51_PAD_EIM_D17__GPIO2_1                       9
-MX51_PAD_EIM_D17__UART2_RXD                     10
-MX51_PAD_EIM_D17__UART3_CTS                     11
-MX51_PAD_EIM_D17__USBH2_DATA1                   12
-MX51_PAD_EIM_D18__AUD5_TXC                      13
-MX51_PAD_EIM_D18__EIM_D18                       14
-MX51_PAD_EIM_D18__GPIO2_2                       15
-MX51_PAD_EIM_D18__UART2_TXD                     16
-MX51_PAD_EIM_D18__UART3_RTS                     17
-MX51_PAD_EIM_D18__USBH2_DATA2                   18
-MX51_PAD_EIM_D19__AUD4_RXC                      19
-MX51_PAD_EIM_D19__AUD5_TXFS                     20
-MX51_PAD_EIM_D19__EIM_D19                       21
-MX51_PAD_EIM_D19__GPIO2_3                       22
-MX51_PAD_EIM_D19__I2C1_SCL                      23
-MX51_PAD_EIM_D19__UART2_RTS                     24
-MX51_PAD_EIM_D19__USBH2_DATA3                   25
-MX51_PAD_EIM_D20__AUD4_TXD                      26
-MX51_PAD_EIM_D20__EIM_D20                       27
-MX51_PAD_EIM_D20__GPIO2_4                       28
-MX51_PAD_EIM_D20__SRTC_ALARM_DEB                29
-MX51_PAD_EIM_D20__USBH2_DATA4                   30
-MX51_PAD_EIM_D21__AUD4_RXD                      31
-MX51_PAD_EIM_D21__EIM_D21                       32
-MX51_PAD_EIM_D21__GPIO2_5                       33
-MX51_PAD_EIM_D21__SRTC_ALARM_DEB                34
-MX51_PAD_EIM_D21__USBH2_DATA5                   35
-MX51_PAD_EIM_D22__AUD4_TXC                      36
-MX51_PAD_EIM_D22__EIM_D22                       37
-MX51_PAD_EIM_D22__GPIO2_6                       38
-MX51_PAD_EIM_D22__USBH2_DATA6                   39
-MX51_PAD_EIM_D23__AUD4_TXFS                     40
-MX51_PAD_EIM_D23__EIM_D23                       41
-MX51_PAD_EIM_D23__GPIO2_7                       42
-MX51_PAD_EIM_D23__SPDIF_OUT1                    43
-MX51_PAD_EIM_D23__USBH2_DATA7                   44
-MX51_PAD_EIM_D24__AUD6_RXFS                     45
-MX51_PAD_EIM_D24__EIM_D24                       46
-MX51_PAD_EIM_D24__GPIO2_8                       47
-MX51_PAD_EIM_D24__I2C2_SDA                      48
-MX51_PAD_EIM_D24__UART3_CTS                     49
-MX51_PAD_EIM_D24__USBOTG_DATA0                  50
-MX51_PAD_EIM_D25__EIM_D25                       51
-MX51_PAD_EIM_D25__KEY_COL6                      52
-MX51_PAD_EIM_D25__UART2_CTS                     53
-MX51_PAD_EIM_D25__UART3_RXD                     54
-MX51_PAD_EIM_D25__USBOTG_DATA1                  55
-MX51_PAD_EIM_D26__EIM_D26                       56
-MX51_PAD_EIM_D26__KEY_COL7                      57
-MX51_PAD_EIM_D26__UART2_RTS                     58
-MX51_PAD_EIM_D26__UART3_TXD                     59
-MX51_PAD_EIM_D26__USBOTG_DATA2                  60
-MX51_PAD_EIM_D27__AUD6_RXC                      61
-MX51_PAD_EIM_D27__EIM_D27                       62
-MX51_PAD_EIM_D27__GPIO2_9                       63
-MX51_PAD_EIM_D27__I2C2_SCL                      64
-MX51_PAD_EIM_D27__UART3_RTS                     65
-MX51_PAD_EIM_D27__USBOTG_DATA3                  66
-MX51_PAD_EIM_D28__AUD6_TXD                      67
-MX51_PAD_EIM_D28__EIM_D28                       68
-MX51_PAD_EIM_D28__KEY_ROW4                      69
-MX51_PAD_EIM_D28__USBOTG_DATA4                  70
-MX51_PAD_EIM_D29__AUD6_RXD                      71
-MX51_PAD_EIM_D29__EIM_D29                       72
-MX51_PAD_EIM_D29__KEY_ROW5                      73
-MX51_PAD_EIM_D29__USBOTG_DATA5                  74
-MX51_PAD_EIM_D30__AUD6_TXC                      75
-MX51_PAD_EIM_D30__EIM_D30                       76
-MX51_PAD_EIM_D30__KEY_ROW6                      77
-MX51_PAD_EIM_D30__USBOTG_DATA6                  78
-MX51_PAD_EIM_D31__AUD6_TXFS                     79
-MX51_PAD_EIM_D31__EIM_D31                       80
-MX51_PAD_EIM_D31__KEY_ROW7                      81
-MX51_PAD_EIM_D31__USBOTG_DATA7                  82
-MX51_PAD_EIM_A16__EIM_A16                       83
-MX51_PAD_EIM_A16__GPIO2_10                      84
-MX51_PAD_EIM_A16__OSC_FREQ_SEL0                 85
-MX51_PAD_EIM_A17__EIM_A17                       86
-MX51_PAD_EIM_A17__GPIO2_11                      87
-MX51_PAD_EIM_A17__OSC_FREQ_SEL1                 88
-MX51_PAD_EIM_A18__BOOT_LPB0                     89
-MX51_PAD_EIM_A18__EIM_A18                       90
-MX51_PAD_EIM_A18__GPIO2_12                      91
-MX51_PAD_EIM_A19__BOOT_LPB1                     92
-MX51_PAD_EIM_A19__EIM_A19                       93
-MX51_PAD_EIM_A19__GPIO2_13                      94
-MX51_PAD_EIM_A20__BOOT_UART_SRC0                95
-MX51_PAD_EIM_A20__EIM_A20                       96
-MX51_PAD_EIM_A20__GPIO2_14                      97
-MX51_PAD_EIM_A21__BOOT_UART_SRC1                98
-MX51_PAD_EIM_A21__EIM_A21                       99
-MX51_PAD_EIM_A21__GPIO2_15                      100
-MX51_PAD_EIM_A22__EIM_A22                       101
-MX51_PAD_EIM_A22__GPIO2_16                      102
-MX51_PAD_EIM_A23__BOOT_HPN_EN                   103
-MX51_PAD_EIM_A23__EIM_A23                       104
-MX51_PAD_EIM_A23__GPIO2_17                      105
-MX51_PAD_EIM_A24__EIM_A24                       106
-MX51_PAD_EIM_A24__GPIO2_18                      107
-MX51_PAD_EIM_A24__USBH2_CLK                     108
-MX51_PAD_EIM_A25__DISP1_PIN4                    109
-MX51_PAD_EIM_A25__EIM_A25                       110
-MX51_PAD_EIM_A25__GPIO2_19                      111
-MX51_PAD_EIM_A25__USBH2_DIR                     112
-MX51_PAD_EIM_A26__CSI1_DATA_EN                  113
-MX51_PAD_EIM_A26__DISP2_EXT_CLK                 114
-MX51_PAD_EIM_A26__EIM_A26                       115
-MX51_PAD_EIM_A26__GPIO2_20                      116
-MX51_PAD_EIM_A26__USBH2_STP                     117
-MX51_PAD_EIM_A27__CSI2_DATA_EN                  118
-MX51_PAD_EIM_A27__DISP1_PIN1                    119
-MX51_PAD_EIM_A27__EIM_A27                       120
-MX51_PAD_EIM_A27__GPIO2_21                      121
-MX51_PAD_EIM_A27__USBH2_NXT                     122
-MX51_PAD_EIM_EB0__EIM_EB0                       123
-MX51_PAD_EIM_EB1__EIM_EB1                       124
-MX51_PAD_EIM_EB2__AUD5_RXFS                     125
-MX51_PAD_EIM_EB2__CSI1_D2                       126
-MX51_PAD_EIM_EB2__EIM_EB2                       127
-MX51_PAD_EIM_EB2__FEC_MDIO                      128
-MX51_PAD_EIM_EB2__GPIO2_22                      129
-MX51_PAD_EIM_EB2__GPT_CMPOUT1                   130
-MX51_PAD_EIM_EB3__AUD5_RXC                      131
-MX51_PAD_EIM_EB3__CSI1_D3                       132
-MX51_PAD_EIM_EB3__EIM_EB3                       133
-MX51_PAD_EIM_EB3__FEC_RDATA1                    134
-MX51_PAD_EIM_EB3__GPIO2_23                      135
-MX51_PAD_EIM_EB3__GPT_CMPOUT2                   136
-MX51_PAD_EIM_OE__EIM_OE                         137
-MX51_PAD_EIM_OE__GPIO2_24                       138
-MX51_PAD_EIM_CS0__EIM_CS0                       139
-MX51_PAD_EIM_CS0__GPIO2_25                      140
-MX51_PAD_EIM_CS1__EIM_CS1                       141
-MX51_PAD_EIM_CS1__GPIO2_26                      142
-MX51_PAD_EIM_CS2__AUD5_TXD                      143
-MX51_PAD_EIM_CS2__CSI1_D4                       144
-MX51_PAD_EIM_CS2__EIM_CS2                       145
-MX51_PAD_EIM_CS2__FEC_RDATA2                    146
-MX51_PAD_EIM_CS2__GPIO2_27                      147
-MX51_PAD_EIM_CS2__USBOTG_STP                    148
-MX51_PAD_EIM_CS3__AUD5_RXD                      149
-MX51_PAD_EIM_CS3__CSI1_D5                       150
-MX51_PAD_EIM_CS3__EIM_CS3                       151
-MX51_PAD_EIM_CS3__FEC_RDATA3                    152
-MX51_PAD_EIM_CS3__GPIO2_28                      153
-MX51_PAD_EIM_CS3__USBOTG_NXT                    154
-MX51_PAD_EIM_CS4__AUD5_TXC                      155
-MX51_PAD_EIM_CS4__CSI1_D6                       156
-MX51_PAD_EIM_CS4__EIM_CS4                       157
-MX51_PAD_EIM_CS4__FEC_RX_ER                     158
-MX51_PAD_EIM_CS4__GPIO2_29                      159
-MX51_PAD_EIM_CS4__USBOTG_CLK                    160
-MX51_PAD_EIM_CS5__AUD5_TXFS                     161
-MX51_PAD_EIM_CS5__CSI1_D7                       162
-MX51_PAD_EIM_CS5__DISP1_EXT_CLK                 163
-MX51_PAD_EIM_CS5__EIM_CS5                       164
-MX51_PAD_EIM_CS5__FEC_CRS                       165
-MX51_PAD_EIM_CS5__GPIO2_30                      166
-MX51_PAD_EIM_CS5__USBOTG_DIR                    167
-MX51_PAD_EIM_DTACK__EIM_DTACK                   168
-MX51_PAD_EIM_DTACK__GPIO2_31                    169
-MX51_PAD_EIM_LBA__EIM_LBA                       170
-MX51_PAD_EIM_LBA__GPIO3_1                       171
-MX51_PAD_EIM_CRE__EIM_CRE                       172
-MX51_PAD_EIM_CRE__GPIO3_2                       173
-MX51_PAD_DRAM_CS1__DRAM_CS1                     174
-MX51_PAD_NANDF_WE_B__GPIO3_3                    175
-MX51_PAD_NANDF_WE_B__NANDF_WE_B                 176
-MX51_PAD_NANDF_WE_B__PATA_DIOW                  177
-MX51_PAD_NANDF_WE_B__SD3_DATA0                  178
-MX51_PAD_NANDF_RE_B__GPIO3_4                    179
-MX51_PAD_NANDF_RE_B__NANDF_RE_B                 180
-MX51_PAD_NANDF_RE_B__PATA_DIOR                  181
-MX51_PAD_NANDF_RE_B__SD3_DATA1                  182
-MX51_PAD_NANDF_ALE__GPIO3_5                     183
-MX51_PAD_NANDF_ALE__NANDF_ALE                   184
-MX51_PAD_NANDF_ALE__PATA_BUFFER_EN              185
-MX51_PAD_NANDF_CLE__GPIO3_6                     186
-MX51_PAD_NANDF_CLE__NANDF_CLE                   187
-MX51_PAD_NANDF_CLE__PATA_RESET_B                188
-MX51_PAD_NANDF_WP_B__GPIO3_7                    189
-MX51_PAD_NANDF_WP_B__NANDF_WP_B                 190
-MX51_PAD_NANDF_WP_B__PATA_DMACK                 191
-MX51_PAD_NANDF_WP_B__SD3_DATA2                  192
-MX51_PAD_NANDF_RB0__ECSPI2_SS1                  193
-MX51_PAD_NANDF_RB0__GPIO3_8                     194
-MX51_PAD_NANDF_RB0__NANDF_RB0                   195
-MX51_PAD_NANDF_RB0__PATA_DMARQ                  196
-MX51_PAD_NANDF_RB0__SD3_DATA3                   197
-MX51_PAD_NANDF_RB1__CSPI_MOSI                   198
-MX51_PAD_NANDF_RB1__ECSPI2_RDY                  199
-MX51_PAD_NANDF_RB1__GPIO3_9                     200
-MX51_PAD_NANDF_RB1__NANDF_RB1                   201
-MX51_PAD_NANDF_RB1__PATA_IORDY                  202
-MX51_PAD_NANDF_RB1__SD4_CMD                     203
-MX51_PAD_NANDF_RB2__DISP2_WAIT                  204
-MX51_PAD_NANDF_RB2__ECSPI2_SCLK                 205
-MX51_PAD_NANDF_RB2__FEC_COL                     206
-MX51_PAD_NANDF_RB2__GPIO3_10                    207
-MX51_PAD_NANDF_RB2__NANDF_RB2                   208
-MX51_PAD_NANDF_RB2__USBH3_H3_DP                 209
-MX51_PAD_NANDF_RB2__USBH3_NXT                   210
-MX51_PAD_NANDF_RB3__DISP1_WAIT                  211
-MX51_PAD_NANDF_RB3__ECSPI2_MISO                 212
-MX51_PAD_NANDF_RB3__FEC_RX_CLK                  213
-MX51_PAD_NANDF_RB3__GPIO3_11                    214
-MX51_PAD_NANDF_RB3__NANDF_RB3                   215
-MX51_PAD_NANDF_RB3__USBH3_CLK                   216
-MX51_PAD_NANDF_RB3__USBH3_H3_DM                 217
-MX51_PAD_GPIO_NAND__GPIO_NAND                   218
-MX51_PAD_GPIO_NAND__PATA_INTRQ                  219
-MX51_PAD_NANDF_CS0__GPIO3_16                    220
-MX51_PAD_NANDF_CS0__NANDF_CS0                   221
-MX51_PAD_NANDF_CS1__GPIO3_17                    222
-MX51_PAD_NANDF_CS1__NANDF_CS1                   223
-MX51_PAD_NANDF_CS2__CSPI_SCLK                   224
-MX51_PAD_NANDF_CS2__FEC_TX_ER                   225
-MX51_PAD_NANDF_CS2__GPIO3_18                    226
-MX51_PAD_NANDF_CS2__NANDF_CS2                   227
-MX51_PAD_NANDF_CS2__PATA_CS_0                   228
-MX51_PAD_NANDF_CS2__SD4_CLK                     229
-MX51_PAD_NANDF_CS2__USBH3_H1_DP                 230
-MX51_PAD_NANDF_CS3__FEC_MDC                     231
-MX51_PAD_NANDF_CS3__GPIO3_19                    232
-MX51_PAD_NANDF_CS3__NANDF_CS3                   233
-MX51_PAD_NANDF_CS3__PATA_CS_1                   234
-MX51_PAD_NANDF_CS3__SD4_DAT0                    235
-MX51_PAD_NANDF_CS3__USBH3_H1_DM                 236
-MX51_PAD_NANDF_CS4__FEC_TDATA1                  237
-MX51_PAD_NANDF_CS4__GPIO3_20                    238
-MX51_PAD_NANDF_CS4__NANDF_CS4                   239
-MX51_PAD_NANDF_CS4__PATA_DA_0                   240
-MX51_PAD_NANDF_CS4__SD4_DAT1                    241
-MX51_PAD_NANDF_CS4__USBH3_STP                   242
-MX51_PAD_NANDF_CS5__FEC_TDATA2                  243
-MX51_PAD_NANDF_CS5__GPIO3_21                    244
-MX51_PAD_NANDF_CS5__NANDF_CS5                   245
-MX51_PAD_NANDF_CS5__PATA_DA_1                   246
-MX51_PAD_NANDF_CS5__SD4_DAT2                    247
-MX51_PAD_NANDF_CS5__USBH3_DIR                   248
-MX51_PAD_NANDF_CS6__CSPI_SS3                    249
-MX51_PAD_NANDF_CS6__FEC_TDATA3                  250
-MX51_PAD_NANDF_CS6__GPIO3_22                    251
-MX51_PAD_NANDF_CS6__NANDF_CS6                   252
-MX51_PAD_NANDF_CS6__PATA_DA_2                   253
-MX51_PAD_NANDF_CS6__SD4_DAT3                    254
-MX51_PAD_NANDF_CS7__FEC_TX_EN                   255
-MX51_PAD_NANDF_CS7__GPIO3_23                    256
-MX51_PAD_NANDF_CS7__NANDF_CS7                   257
-MX51_PAD_NANDF_CS7__SD3_CLK                     258
-MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0              259
-MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK              260
-MX51_PAD_NANDF_RDY_INT__GPIO3_24                261
-MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT           262
-MX51_PAD_NANDF_RDY_INT__SD3_CMD                 263
-MX51_PAD_NANDF_D15__ECSPI2_MOSI                 264
-MX51_PAD_NANDF_D15__GPIO3_25                    265
-MX51_PAD_NANDF_D15__NANDF_D15                   266
-MX51_PAD_NANDF_D15__PATA_DATA15                 267
-MX51_PAD_NANDF_D15__SD3_DAT7                    268
-MX51_PAD_NANDF_D14__ECSPI2_SS3                  269
-MX51_PAD_NANDF_D14__GPIO3_26                    270
-MX51_PAD_NANDF_D14__NANDF_D14                   271
-MX51_PAD_NANDF_D14__PATA_DATA14                 272
-MX51_PAD_NANDF_D14__SD3_DAT6                    273
-MX51_PAD_NANDF_D13__ECSPI2_SS2                  274
-MX51_PAD_NANDF_D13__GPIO3_27                    275
-MX51_PAD_NANDF_D13__NANDF_D13                   276
-MX51_PAD_NANDF_D13__PATA_DATA13                 277
-MX51_PAD_NANDF_D13__SD3_DAT5                    278
-MX51_PAD_NANDF_D12__ECSPI2_SS1                  279
-MX51_PAD_NANDF_D12__GPIO3_28                    280
-MX51_PAD_NANDF_D12__NANDF_D12                   281
-MX51_PAD_NANDF_D12__PATA_DATA12                 282
-MX51_PAD_NANDF_D12__SD3_DAT4                    283
-MX51_PAD_NANDF_D11__FEC_RX_DV                   284
-MX51_PAD_NANDF_D11__GPIO3_29                    285
-MX51_PAD_NANDF_D11__NANDF_D11                   286
-MX51_PAD_NANDF_D11__PATA_DATA11                 287
-MX51_PAD_NANDF_D11__SD3_DATA3                   288
-MX51_PAD_NANDF_D10__GPIO3_30                    289
-MX51_PAD_NANDF_D10__NANDF_D10                   290
-MX51_PAD_NANDF_D10__PATA_DATA10                 291
-MX51_PAD_NANDF_D10__SD3_DATA2                   292
-MX51_PAD_NANDF_D9__FEC_RDATA0                   293
-MX51_PAD_NANDF_D9__GPIO3_31                     294
-MX51_PAD_NANDF_D9__NANDF_D9                     295
-MX51_PAD_NANDF_D9__PATA_DATA9                   296
-MX51_PAD_NANDF_D9__SD3_DATA1                    297
-MX51_PAD_NANDF_D8__FEC_TDATA0                   298
-MX51_PAD_NANDF_D8__GPIO4_0                      299
-MX51_PAD_NANDF_D8__NANDF_D8                     300
-MX51_PAD_NANDF_D8__PATA_DATA8                   301
-MX51_PAD_NANDF_D8__SD3_DATA0                    302
-MX51_PAD_NANDF_D7__GPIO4_1                      303
-MX51_PAD_NANDF_D7__NANDF_D7                     304
-MX51_PAD_NANDF_D7__PATA_DATA7                   305
-MX51_PAD_NANDF_D7__USBH3_DATA0                  306
-MX51_PAD_NANDF_D6__GPIO4_2                      307
-MX51_PAD_NANDF_D6__NANDF_D6                     308
-MX51_PAD_NANDF_D6__PATA_DATA6                   309
-MX51_PAD_NANDF_D6__SD4_LCTL                     310
-MX51_PAD_NANDF_D6__USBH3_DATA1                  311
-MX51_PAD_NANDF_D5__GPIO4_3                      312
-MX51_PAD_NANDF_D5__NANDF_D5                     313
-MX51_PAD_NANDF_D5__PATA_DATA5                   314
-MX51_PAD_NANDF_D5__SD4_WP                       315
-MX51_PAD_NANDF_D5__USBH3_DATA2                  316
-MX51_PAD_NANDF_D4__GPIO4_4                      317
-MX51_PAD_NANDF_D4__NANDF_D4                     318
-MX51_PAD_NANDF_D4__PATA_DATA4                   319
-MX51_PAD_NANDF_D4__SD4_CD                       320
-MX51_PAD_NANDF_D4__USBH3_DATA3                  321
-MX51_PAD_NANDF_D3__GPIO4_5                      322
-MX51_PAD_NANDF_D3__NANDF_D3                     323
-MX51_PAD_NANDF_D3__PATA_DATA3                   324
-MX51_PAD_NANDF_D3__SD4_DAT4                     325
-MX51_PAD_NANDF_D3__USBH3_DATA4                  326
-MX51_PAD_NANDF_D2__GPIO4_6                      327
-MX51_PAD_NANDF_D2__NANDF_D2                     328
-MX51_PAD_NANDF_D2__PATA_DATA2                   329
-MX51_PAD_NANDF_D2__SD4_DAT5                     330
-MX51_PAD_NANDF_D2__USBH3_DATA5                  331
-MX51_PAD_NANDF_D1__GPIO4_7                      332
-MX51_PAD_NANDF_D1__NANDF_D1                     333
-MX51_PAD_NANDF_D1__PATA_DATA1                   334
-MX51_PAD_NANDF_D1__SD4_DAT6                     335
-MX51_PAD_NANDF_D1__USBH3_DATA6                  336
-MX51_PAD_NANDF_D0__GPIO4_8                      337
-MX51_PAD_NANDF_D0__NANDF_D0                     338
-MX51_PAD_NANDF_D0__PATA_DATA0                   339
-MX51_PAD_NANDF_D0__SD4_DAT7                     340
-MX51_PAD_NANDF_D0__USBH3_DATA7                  341
-MX51_PAD_CSI1_D8__CSI1_D8                       342
-MX51_PAD_CSI1_D8__GPIO3_12                      343
-MX51_PAD_CSI1_D9__CSI1_D9                       344
-MX51_PAD_CSI1_D9__GPIO3_13                      345
-MX51_PAD_CSI1_D10__CSI1_D10                     346
-MX51_PAD_CSI1_D11__CSI1_D11                     347
-MX51_PAD_CSI1_D12__CSI1_D12                     348
-MX51_PAD_CSI1_D13__CSI1_D13                     349
-MX51_PAD_CSI1_D14__CSI1_D14                     350
-MX51_PAD_CSI1_D15__CSI1_D15                     351
-MX51_PAD_CSI1_D16__CSI1_D16                     352
-MX51_PAD_CSI1_D17__CSI1_D17                     353
-MX51_PAD_CSI1_D18__CSI1_D18                     354
-MX51_PAD_CSI1_D19__CSI1_D19                     355
-MX51_PAD_CSI1_VSYNC__CSI1_VSYNC                 356
-MX51_PAD_CSI1_VSYNC__GPIO3_14                   357
-MX51_PAD_CSI1_HSYNC__CSI1_HSYNC                 358
-MX51_PAD_CSI1_HSYNC__GPIO3_15                   359
-MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK               360
-MX51_PAD_CSI1_MCLK__CSI1_MCLK                   361
-MX51_PAD_CSI2_D12__CSI2_D12                     362
-MX51_PAD_CSI2_D12__GPIO4_9                      363
-MX51_PAD_CSI2_D13__CSI2_D13                     364
-MX51_PAD_CSI2_D13__GPIO4_10                     365
-MX51_PAD_CSI2_D14__CSI2_D14                     366
-MX51_PAD_CSI2_D15__CSI2_D15                     367
-MX51_PAD_CSI2_D16__CSI2_D16                     368
-MX51_PAD_CSI2_D17__CSI2_D17                     369
-MX51_PAD_CSI2_D18__CSI2_D18                     370
-MX51_PAD_CSI2_D18__GPIO4_11                     371
-MX51_PAD_CSI2_D19__CSI2_D19                     372
-MX51_PAD_CSI2_D19__GPIO4_12                     373
-MX51_PAD_CSI2_VSYNC__CSI2_VSYNC                 374
-MX51_PAD_CSI2_VSYNC__GPIO4_13                   375
-MX51_PAD_CSI2_HSYNC__CSI2_HSYNC                 376
-MX51_PAD_CSI2_HSYNC__GPIO4_14                   377
-MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK               378
-MX51_PAD_CSI2_PIXCLK__GPIO4_15                  379
-MX51_PAD_I2C1_CLK__GPIO4_16                     380
-MX51_PAD_I2C1_CLK__I2C1_CLK                     381
-MX51_PAD_I2C1_DAT__GPIO4_17                     382
-MX51_PAD_I2C1_DAT__I2C1_DAT                     383
-MX51_PAD_AUD3_BB_TXD__AUD3_TXD                  384
-MX51_PAD_AUD3_BB_TXD__GPIO4_18                  385
-MX51_PAD_AUD3_BB_RXD__AUD3_RXD                  386
-MX51_PAD_AUD3_BB_RXD__GPIO4_19                  387
-MX51_PAD_AUD3_BB_RXD__UART3_RXD                 388
-MX51_PAD_AUD3_BB_CK__AUD3_TXC                   389
-MX51_PAD_AUD3_BB_CK__GPIO4_20                   390
-MX51_PAD_AUD3_BB_FS__AUD3_TXFS                  391
-MX51_PAD_AUD3_BB_FS__GPIO4_21                   392
-MX51_PAD_AUD3_BB_FS__UART3_TXD                  393
-MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI                394
-MX51_PAD_CSPI1_MOSI__GPIO4_22                   395
-MX51_PAD_CSPI1_MOSI__I2C1_SDA                   396
-MX51_PAD_CSPI1_MISO__AUD4_RXD                   397
-MX51_PAD_CSPI1_MISO__ECSPI1_MISO                398
-MX51_PAD_CSPI1_MISO__GPIO4_23                   399
-MX51_PAD_CSPI1_SS0__AUD4_TXC                    400
-MX51_PAD_CSPI1_SS0__ECSPI1_SS0                  401
-MX51_PAD_CSPI1_SS0__GPIO4_24                    402
-MX51_PAD_CSPI1_SS1__AUD4_TXD                    403
-MX51_PAD_CSPI1_SS1__ECSPI1_SS1                  404
-MX51_PAD_CSPI1_SS1__GPIO4_25                    405
-MX51_PAD_CSPI1_RDY__AUD4_TXFS                   406
-MX51_PAD_CSPI1_RDY__ECSPI1_RDY                  407
-MX51_PAD_CSPI1_RDY__GPIO4_26                    408
-MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK                409
-MX51_PAD_CSPI1_SCLK__GPIO4_27                   410
-MX51_PAD_CSPI1_SCLK__I2C1_SCL                   411
-MX51_PAD_UART1_RXD__GPIO4_28                    412
-MX51_PAD_UART1_RXD__UART1_RXD                   413
-MX51_PAD_UART1_TXD__GPIO4_29                    414
-MX51_PAD_UART1_TXD__PWM2_PWMO                   415
-MX51_PAD_UART1_TXD__UART1_TXD                   416
-MX51_PAD_UART1_RTS__GPIO4_30                    417
-MX51_PAD_UART1_RTS__UART1_RTS                   418
-MX51_PAD_UART1_CTS__GPIO4_31                    419
-MX51_PAD_UART1_CTS__UART1_CTS                   420
-MX51_PAD_UART2_RXD__FIRI_TXD                    421
-MX51_PAD_UART2_RXD__GPIO1_20                    422
-MX51_PAD_UART2_RXD__UART2_RXD                   423
-MX51_PAD_UART2_TXD__FIRI_RXD                    424
-MX51_PAD_UART2_TXD__GPIO1_21                    425
-MX51_PAD_UART2_TXD__UART2_TXD                   426
-MX51_PAD_UART3_RXD__CSI1_D0                     427
-MX51_PAD_UART3_RXD__GPIO1_22                    428
-MX51_PAD_UART3_RXD__UART1_DTR                   429
-MX51_PAD_UART3_RXD__UART3_RXD                   430
-MX51_PAD_UART3_TXD__CSI1_D1                     431
-MX51_PAD_UART3_TXD__GPIO1_23                    432
-MX51_PAD_UART3_TXD__UART1_DSR                   433
-MX51_PAD_UART3_TXD__UART3_TXD                   434
-MX51_PAD_OWIRE_LINE__GPIO1_24                   435
-MX51_PAD_OWIRE_LINE__OWIRE_LINE                 436
-MX51_PAD_OWIRE_LINE__SPDIF_OUT                  437
-MX51_PAD_KEY_ROW0__KEY_ROW0                     438
-MX51_PAD_KEY_ROW1__KEY_ROW1                     439
-MX51_PAD_KEY_ROW2__KEY_ROW2                     440
-MX51_PAD_KEY_ROW3__KEY_ROW3                     441
-MX51_PAD_KEY_COL0__KEY_COL0                     442
-MX51_PAD_KEY_COL0__PLL1_BYP                     443
-MX51_PAD_KEY_COL1__KEY_COL1                     444
-MX51_PAD_KEY_COL1__PLL2_BYP                     445
-MX51_PAD_KEY_COL2__KEY_COL2                     446
-MX51_PAD_KEY_COL2__PLL3_BYP                     447
-MX51_PAD_KEY_COL3__KEY_COL3                     448
-MX51_PAD_KEY_COL4__I2C2_SCL                     449
-MX51_PAD_KEY_COL4__KEY_COL4                     450
-MX51_PAD_KEY_COL4__SPDIF_OUT1                   451
-MX51_PAD_KEY_COL4__UART1_RI                     452
-MX51_PAD_KEY_COL4__UART3_RTS                    453
-MX51_PAD_KEY_COL5__I2C2_SDA                     454
-MX51_PAD_KEY_COL5__KEY_COL5                     455
-MX51_PAD_KEY_COL5__UART1_DCD                    456
-MX51_PAD_KEY_COL5__UART3_CTS                    457
-MX51_PAD_USBH1_CLK__CSPI_SCLK                   458
-MX51_PAD_USBH1_CLK__GPIO1_25                    459
-MX51_PAD_USBH1_CLK__I2C2_SCL                    460
-MX51_PAD_USBH1_CLK__USBH1_CLK                   461
-MX51_PAD_USBH1_DIR__CSPI_MOSI                   462
-MX51_PAD_USBH1_DIR__GPIO1_26                    463
-MX51_PAD_USBH1_DIR__I2C2_SDA                    464
-MX51_PAD_USBH1_DIR__USBH1_DIR                   465
-MX51_PAD_USBH1_STP__CSPI_RDY                    466
-MX51_PAD_USBH1_STP__GPIO1_27                    467
-MX51_PAD_USBH1_STP__UART3_RXD                   468
-MX51_PAD_USBH1_STP__USBH1_STP                   469
-MX51_PAD_USBH1_NXT__CSPI_MISO                   470
-MX51_PAD_USBH1_NXT__GPIO1_28                    471
-MX51_PAD_USBH1_NXT__UART3_TXD                   472
-MX51_PAD_USBH1_NXT__USBH1_NXT                   473
-MX51_PAD_USBH1_DATA0__GPIO1_11                  474
-MX51_PAD_USBH1_DATA0__UART2_CTS                 475
-MX51_PAD_USBH1_DATA0__USBH1_DATA0               476
-MX51_PAD_USBH1_DATA1__GPIO1_12                  477
-MX51_PAD_USBH1_DATA1__UART2_RXD                 478
-MX51_PAD_USBH1_DATA1__USBH1_DATA1               479
-MX51_PAD_USBH1_DATA2__GPIO1_13                  480
-MX51_PAD_USBH1_DATA2__UART2_TXD                 481
-MX51_PAD_USBH1_DATA2__USBH1_DATA2               482
-MX51_PAD_USBH1_DATA3__GPIO1_14                  483
-MX51_PAD_USBH1_DATA3__UART2_RTS                 484
-MX51_PAD_USBH1_DATA3__USBH1_DATA3               485
-MX51_PAD_USBH1_DATA4__CSPI_SS0                  486
-MX51_PAD_USBH1_DATA4__GPIO1_15                  487
-MX51_PAD_USBH1_DATA4__USBH1_DATA4               488
-MX51_PAD_USBH1_DATA5__CSPI_SS1                  489
-MX51_PAD_USBH1_DATA5__GPIO1_16                  490
-MX51_PAD_USBH1_DATA5__USBH1_DATA5               491
-MX51_PAD_USBH1_DATA6__CSPI_SS3                  492
-MX51_PAD_USBH1_DATA6__GPIO1_17                  493
-MX51_PAD_USBH1_DATA6__USBH1_DATA6               494
-MX51_PAD_USBH1_DATA7__ECSPI1_SS3                495
-MX51_PAD_USBH1_DATA7__ECSPI2_SS3                496
-MX51_PAD_USBH1_DATA7__GPIO1_18                  497
-MX51_PAD_USBH1_DATA7__USBH1_DATA7               498
-MX51_PAD_DI1_PIN11__DI1_PIN11                   499
-MX51_PAD_DI1_PIN11__ECSPI1_SS2                  500
-MX51_PAD_DI1_PIN11__GPIO3_0                     501
-MX51_PAD_DI1_PIN12__DI1_PIN12                   502
-MX51_PAD_DI1_PIN12__GPIO3_1                     503
-MX51_PAD_DI1_PIN13__DI1_PIN13                   504
-MX51_PAD_DI1_PIN13__GPIO3_2                     505
-MX51_PAD_DI1_D0_CS__DI1_D0_CS                   506
-MX51_PAD_DI1_D0_CS__GPIO3_3                     507
-MX51_PAD_DI1_D1_CS__DI1_D1_CS                   508
-MX51_PAD_DI1_D1_CS__DISP1_PIN14                 509
-MX51_PAD_DI1_D1_CS__DISP1_PIN5                  510
-MX51_PAD_DI1_D1_CS__GPIO3_4                     511
-MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1             512
-MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN         513
-MX51_PAD_DISPB2_SER_DIN__GPIO3_5                514
-MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6             515
-MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO         516
-MX51_PAD_DISPB2_SER_DIO__GPIO3_6                517
-MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17            518
-MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7             519
-MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK         520
-MX51_PAD_DISPB2_SER_CLK__GPIO3_7                521
-MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK           522
-MX51_PAD_DISPB2_SER_RS__DISP1_PIN16             523
-MX51_PAD_DISPB2_SER_RS__DISP1_PIN8              524
-MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS           525
-MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS           526
-MX51_PAD_DISPB2_SER_RS__GPIO3_8                 527
-MX51_PAD_DISP1_DAT0__DISP1_DAT0                 528
-MX51_PAD_DISP1_DAT1__DISP1_DAT1                 529
-MX51_PAD_DISP1_DAT2__DISP1_DAT2                 530
-MX51_PAD_DISP1_DAT3__DISP1_DAT3                 531
-MX51_PAD_DISP1_DAT4__DISP1_DAT4                 532
-MX51_PAD_DISP1_DAT5__DISP1_DAT5                 533
-MX51_PAD_DISP1_DAT6__BOOT_USB_SRC               534
-MX51_PAD_DISP1_DAT6__DISP1_DAT6                 535
-MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG            536
-MX51_PAD_DISP1_DAT7__DISP1_DAT7                 537
-MX51_PAD_DISP1_DAT8__BOOT_SRC0                  538
-MX51_PAD_DISP1_DAT8__DISP1_DAT8                 539
-MX51_PAD_DISP1_DAT9__BOOT_SRC1                  540
-MX51_PAD_DISP1_DAT9__DISP1_DAT9                 541
-MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE           542
-MX51_PAD_DISP1_DAT10__DISP1_DAT10               543
-MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2            544
-MX51_PAD_DISP1_DAT11__DISP1_DAT11               545
-MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL              546
-MX51_PAD_DISP1_DAT12__DISP1_DAT12               547
-MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0             548
-MX51_PAD_DISP1_DAT13__DISP1_DAT13               549
-MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1             550
-MX51_PAD_DISP1_DAT14__DISP1_DAT14               551
-MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH            552
-MX51_PAD_DISP1_DAT15__DISP1_DAT15               553
-MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0           554
-MX51_PAD_DISP1_DAT16__DISP1_DAT16               555
-MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1           556
-MX51_PAD_DISP1_DAT17__DISP1_DAT17               557
-MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0          558
-MX51_PAD_DISP1_DAT18__DISP1_DAT18               559
-MX51_PAD_DISP1_DAT18__DISP2_PIN11               560
-MX51_PAD_DISP1_DAT18__DISP2_PIN5                561
-MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1          562
-MX51_PAD_DISP1_DAT19__DISP1_DAT19               563
-MX51_PAD_DISP1_DAT19__DISP2_PIN12               564
-MX51_PAD_DISP1_DAT19__DISP2_PIN6                565
-MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0            566
-MX51_PAD_DISP1_DAT20__DISP1_DAT20               567
-MX51_PAD_DISP1_DAT20__DISP2_PIN13               568
-MX51_PAD_DISP1_DAT20__DISP2_PIN7                569
-MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1            570
-MX51_PAD_DISP1_DAT21__DISP1_DAT21               571
-MX51_PAD_DISP1_DAT21__DISP2_PIN14               572
-MX51_PAD_DISP1_DAT21__DISP2_PIN8                573
-MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0            574
-MX51_PAD_DISP1_DAT22__DISP1_DAT22               575
-MX51_PAD_DISP1_DAT22__DISP2_D0_CS               576
-MX51_PAD_DISP1_DAT22__DISP2_DAT16               577
-MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1            578
-MX51_PAD_DISP1_DAT23__DISP1_DAT23               579
-MX51_PAD_DISP1_DAT23__DISP2_D1_CS               580
-MX51_PAD_DISP1_DAT23__DISP2_DAT17               581
-MX51_PAD_DISP1_DAT23__DISP2_SER_CS              582
-MX51_PAD_DI1_PIN3__DI1_PIN3                     583
-MX51_PAD_DI1_PIN2__DI1_PIN2                     584
-MX51_PAD_DI_GP2__DISP1_SER_CLK                  585
-MX51_PAD_DI_GP2__DISP2_WAIT                     586
-MX51_PAD_DI_GP3__CSI1_DATA_EN                   587
-MX51_PAD_DI_GP3__DISP1_SER_DIO                  588
-MX51_PAD_DI_GP3__FEC_TX_ER                      589
-MX51_PAD_DI2_PIN4__CSI2_DATA_EN                 590
-MX51_PAD_DI2_PIN4__DI2_PIN4                     591
-MX51_PAD_DI2_PIN4__FEC_CRS                      592
-MX51_PAD_DI2_PIN2__DI2_PIN2                     593
-MX51_PAD_DI2_PIN2__FEC_MDC                      594
-MX51_PAD_DI2_PIN3__DI2_PIN3                     595
-MX51_PAD_DI2_PIN3__FEC_MDIO                     596
-MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK             597
-MX51_PAD_DI2_DISP_CLK__FEC_RDATA1               598
-MX51_PAD_DI_GP4__DI2_PIN15                      599
-MX51_PAD_DI_GP4__DISP1_SER_DIN                  600
-MX51_PAD_DI_GP4__DISP2_PIN1                     601
-MX51_PAD_DI_GP4__FEC_RDATA2                     602
-MX51_PAD_DISP2_DAT0__DISP2_DAT0                 603
-MX51_PAD_DISP2_DAT0__FEC_RDATA3                 604
-MX51_PAD_DISP2_DAT0__KEY_COL6                   605
-MX51_PAD_DISP2_DAT0__UART3_RXD                  606
-MX51_PAD_DISP2_DAT0__USBH3_CLK                  607
-MX51_PAD_DISP2_DAT1__DISP2_DAT1                 608
-MX51_PAD_DISP2_DAT1__FEC_RX_ER                  609
-MX51_PAD_DISP2_DAT1__KEY_COL7                   610
-MX51_PAD_DISP2_DAT1__UART3_TXD                  611
-MX51_PAD_DISP2_DAT1__USBH3_DIR                  612
-MX51_PAD_DISP2_DAT2__DISP2_DAT2                 613
-MX51_PAD_DISP2_DAT3__DISP2_DAT3                 614
-MX51_PAD_DISP2_DAT4__DISP2_DAT4                 615
-MX51_PAD_DISP2_DAT5__DISP2_DAT5                 616
-MX51_PAD_DISP2_DAT6__DISP2_DAT6                 617
-MX51_PAD_DISP2_DAT6__FEC_TDATA1                 618
-MX51_PAD_DISP2_DAT6__GPIO1_19                   619
-MX51_PAD_DISP2_DAT6__KEY_ROW4                   620
-MX51_PAD_DISP2_DAT6__USBH3_STP                  621
-MX51_PAD_DISP2_DAT7__DISP2_DAT7                 622
-MX51_PAD_DISP2_DAT7__FEC_TDATA2                 623
-MX51_PAD_DISP2_DAT7__GPIO1_29                   624
-MX51_PAD_DISP2_DAT7__KEY_ROW5                   625
-MX51_PAD_DISP2_DAT7__USBH3_NXT                  626
-MX51_PAD_DISP2_DAT8__DISP2_DAT8                 627
-MX51_PAD_DISP2_DAT8__FEC_TDATA3                 628
-MX51_PAD_DISP2_DAT8__GPIO1_30                   629
-MX51_PAD_DISP2_DAT8__KEY_ROW6                   630
-MX51_PAD_DISP2_DAT8__USBH3_DATA0                631
-MX51_PAD_DISP2_DAT9__AUD6_RXC                   632
-MX51_PAD_DISP2_DAT9__DISP2_DAT9                 633
-MX51_PAD_DISP2_DAT9__FEC_TX_EN                  634
-MX51_PAD_DISP2_DAT9__GPIO1_31                   635
-MX51_PAD_DISP2_DAT9__USBH3_DATA1                636
-MX51_PAD_DISP2_DAT10__DISP2_DAT10               637
-MX51_PAD_DISP2_DAT10__DISP2_SER_CS              638
-MX51_PAD_DISP2_DAT10__FEC_COL                   639
-MX51_PAD_DISP2_DAT10__KEY_ROW7                  640
-MX51_PAD_DISP2_DAT10__USBH3_DATA2               641
-MX51_PAD_DISP2_DAT11__AUD6_TXD                  642
-MX51_PAD_DISP2_DAT11__DISP2_DAT11               643
-MX51_PAD_DISP2_DAT11__FEC_RX_CLK                644
-MX51_PAD_DISP2_DAT11__GPIO1_10                  645
-MX51_PAD_DISP2_DAT11__USBH3_DATA3               646
-MX51_PAD_DISP2_DAT12__AUD6_RXD                  647
-MX51_PAD_DISP2_DAT12__DISP2_DAT12               648
-MX51_PAD_DISP2_DAT12__FEC_RX_DV                 649
-MX51_PAD_DISP2_DAT12__USBH3_DATA4               650
-MX51_PAD_DISP2_DAT13__AUD6_TXC                  651
-MX51_PAD_DISP2_DAT13__DISP2_DAT13               652
-MX51_PAD_DISP2_DAT13__FEC_TX_CLK                653
-MX51_PAD_DISP2_DAT13__USBH3_DATA5               654
-MX51_PAD_DISP2_DAT14__AUD6_TXFS                 655
-MX51_PAD_DISP2_DAT14__DISP2_DAT14               656
-MX51_PAD_DISP2_DAT14__FEC_RDATA0                657
-MX51_PAD_DISP2_DAT14__USBH3_DATA6               658
-MX51_PAD_DISP2_DAT15__AUD6_RXFS                 659
-MX51_PAD_DISP2_DAT15__DISP1_SER_CS              660
-MX51_PAD_DISP2_DAT15__DISP2_DAT15               661
-MX51_PAD_DISP2_DAT15__FEC_TDATA0                662
-MX51_PAD_DISP2_DAT15__USBH3_DATA7               663
-MX51_PAD_SD1_CMD__AUD5_RXFS                     664
-MX51_PAD_SD1_CMD__CSPI_MOSI                     665
-MX51_PAD_SD1_CMD__SD1_CMD                       666
-MX51_PAD_SD1_CLK__AUD5_RXC                      667
-MX51_PAD_SD1_CLK__CSPI_SCLK                     668
-MX51_PAD_SD1_CLK__SD1_CLK                       669
-MX51_PAD_SD1_DATA0__AUD5_TXD                    670
-MX51_PAD_SD1_DATA0__CSPI_MISO                   671
-MX51_PAD_SD1_DATA0__SD1_DATA0                   672
-MX51_PAD_EIM_DA0__EIM_DA0                       673
-MX51_PAD_EIM_DA1__EIM_DA1                       674
-MX51_PAD_EIM_DA2__EIM_DA2                       675
-MX51_PAD_EIM_DA3__EIM_DA3                       676
-MX51_PAD_SD1_DATA1__AUD5_RXD                    677
-MX51_PAD_SD1_DATA1__SD1_DATA1                   678
-MX51_PAD_EIM_DA4__EIM_DA4                       679
-MX51_PAD_EIM_DA5__EIM_DA5                       680
-MX51_PAD_EIM_DA6__EIM_DA6                       681
-MX51_PAD_EIM_DA7__EIM_DA7                       682
-MX51_PAD_SD1_DATA2__AUD5_TXC                    683
-MX51_PAD_SD1_DATA2__SD1_DATA2                   684
-MX51_PAD_EIM_DA10__EIM_DA10                     685
-MX51_PAD_EIM_DA11__EIM_DA11                     686
-MX51_PAD_EIM_DA8__EIM_DA8                       687
-MX51_PAD_EIM_DA9__EIM_DA9                       688
-MX51_PAD_SD1_DATA3__AUD5_TXFS                   689
-MX51_PAD_SD1_DATA3__CSPI_SS1                    690
-MX51_PAD_SD1_DATA3__SD1_DATA3                   691
-MX51_PAD_GPIO1_0__CSPI_SS2                      692
-MX51_PAD_GPIO1_0__GPIO1_0                       693
-MX51_PAD_GPIO1_0__SD1_CD                        694
-MX51_PAD_GPIO1_1__CSPI_MISO                     695
-MX51_PAD_GPIO1_1__GPIO1_1                       696
-MX51_PAD_GPIO1_1__SD1_WP                        697
-MX51_PAD_EIM_DA12__EIM_DA12                     698
-MX51_PAD_EIM_DA13__EIM_DA13                     699
-MX51_PAD_EIM_DA14__EIM_DA14                     700
-MX51_PAD_EIM_DA15__EIM_DA15                     701
-MX51_PAD_SD2_CMD__CSPI_MOSI                     702
-MX51_PAD_SD2_CMD__I2C1_SCL                      703
-MX51_PAD_SD2_CMD__SD2_CMD                       704
-MX51_PAD_SD2_CLK__CSPI_SCLK                     705
-MX51_PAD_SD2_CLK__I2C1_SDA                      706
-MX51_PAD_SD2_CLK__SD2_CLK                       707
-MX51_PAD_SD2_DATA0__CSPI_MISO                   708
-MX51_PAD_SD2_DATA0__SD1_DAT4                    709
-MX51_PAD_SD2_DATA0__SD2_DATA0                   710
-MX51_PAD_SD2_DATA1__SD1_DAT5                    711
-MX51_PAD_SD2_DATA1__SD2_DATA1                   712
-MX51_PAD_SD2_DATA1__USBH3_H2_DP                 713
-MX51_PAD_SD2_DATA2__SD1_DAT6                    714
-MX51_PAD_SD2_DATA2__SD2_DATA2                   715
-MX51_PAD_SD2_DATA2__USBH3_H2_DM                 716
-MX51_PAD_SD2_DATA3__CSPI_SS2                    717
-MX51_PAD_SD2_DATA3__SD1_DAT7                    718
-MX51_PAD_SD2_DATA3__SD2_DATA3                   719
-MX51_PAD_GPIO1_2__CCM_OUT_2                     720
-MX51_PAD_GPIO1_2__GPIO1_2                       721
-MX51_PAD_GPIO1_2__I2C2_SCL                      722
-MX51_PAD_GPIO1_2__PLL1_BYP                      723
-MX51_PAD_GPIO1_2__PWM1_PWMO                     724
-MX51_PAD_GPIO1_3__GPIO1_3                       725
-MX51_PAD_GPIO1_3__I2C2_SDA                      726
-MX51_PAD_GPIO1_3__PLL2_BYP                      727
-MX51_PAD_GPIO1_3__PWM2_PWMO                     728
-MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ             729
-MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B           730
-MX51_PAD_GPIO1_4__DISP2_EXT_CLK                 731
-MX51_PAD_GPIO1_4__EIM_RDY                       732
-MX51_PAD_GPIO1_4__GPIO1_4                       733
-MX51_PAD_GPIO1_4__WDOG1_WDOG_B                  734
-MX51_PAD_GPIO1_5__CSI2_MCLK                     735
-MX51_PAD_GPIO1_5__DISP2_PIN16                   736
-MX51_PAD_GPIO1_5__GPIO1_5                       737
-MX51_PAD_GPIO1_5__WDOG2_WDOG_B                  738
-MX51_PAD_GPIO1_6__DISP2_PIN17                   739
-MX51_PAD_GPIO1_6__GPIO1_6                       740
-MX51_PAD_GPIO1_6__REF_EN_B                      741
-MX51_PAD_GPIO1_7__CCM_OUT_0                     742
-MX51_PAD_GPIO1_7__GPIO1_7                       743
-MX51_PAD_GPIO1_7__SD2_WP                        744
-MX51_PAD_GPIO1_7__SPDIF_OUT1                    745
-MX51_PAD_GPIO1_8__CSI2_DATA_EN                  746
-MX51_PAD_GPIO1_8__GPIO1_8                       747
-MX51_PAD_GPIO1_8__SD2_CD                        748
-MX51_PAD_GPIO1_8__USBH3_PWR                     749
-MX51_PAD_GPIO1_9__CCM_OUT_1                     750
-MX51_PAD_GPIO1_9__DISP2_D1_CS                   751
-MX51_PAD_GPIO1_9__DISP2_SER_CS                  752
-MX51_PAD_GPIO1_9__GPIO1_9                       753
-MX51_PAD_GPIO1_9__SD2_LCTL                      754
-MX51_PAD_GPIO1_9__USBH3_OC                      755
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt
deleted file mode 100644
index ca85ca432ef..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt
+++ /dev/null
@@ -1,1202 +0,0 @@
-* Freescale IMX53 IOMUX Controller
-
-Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
-and usage.
-
-Required properties:
-- compatible: "fsl,imx53-iomuxc"
-- fsl,pins: two integers array, represents a group of pins mux and config
-  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
-  pin working on a specific function, CONFIG is the pad setting value like
-  pull-up for this pin. Please refer to imx53 datasheet for the valid pad
-  config settings.
-
-CONFIG bits definition:
-PAD_CTL_HVE                     (1 << 13)
-PAD_CTL_HYS                     (1 << 8)
-PAD_CTL_PKE                     (1 << 7)
-PAD_CTL_PUE                     (1 << 6)
-PAD_CTL_PUS_100K_DOWN           (0 << 4)
-PAD_CTL_PUS_47K_UP              (1 << 4)
-PAD_CTL_PUS_100K_UP             (2 << 4)
-PAD_CTL_PUS_22K_UP              (3 << 4)
-PAD_CTL_ODE                     (1 << 3)
-PAD_CTL_DSE_LOW                 (0 << 1)
-PAD_CTL_DSE_MED                 (1 << 1)
-PAD_CTL_DSE_HIGH                (2 << 1)
-PAD_CTL_DSE_MAX                 (3 << 1)
-PAD_CTL_SRE_FAST                (1 << 0)
-PAD_CTL_SRE_SLOW                (0 << 0)
-
-See below for available PIN_FUNC_ID for imx53:
-MX53_PAD_GPIO_19__KPP_COL_5                             0
-MX53_PAD_GPIO_19__GPIO4_5                               1
-MX53_PAD_GPIO_19__CCM_CLKO                              2
-MX53_PAD_GPIO_19__SPDIF_OUT1                            3
-MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2                  4
-MX53_PAD_GPIO_19__ECSPI1_RDY                            5
-MX53_PAD_GPIO_19__FEC_TDATA_3                           6
-MX53_PAD_GPIO_19__SRC_INT_BOOT                          7
-MX53_PAD_KEY_COL0__KPP_COL_0                            8
-MX53_PAD_KEY_COL0__GPIO4_6                              9
-MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC                      10
-MX53_PAD_KEY_COL0__UART4_TXD_MUX                        11
-MX53_PAD_KEY_COL0__ECSPI1_SCLK                          12
-MX53_PAD_KEY_COL0__FEC_RDATA_3                          13
-MX53_PAD_KEY_COL0__SRC_ANY_PU_RST                       14
-MX53_PAD_KEY_ROW0__KPP_ROW_0                            15
-MX53_PAD_KEY_ROW0__GPIO4_7                              16
-MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD                      17
-MX53_PAD_KEY_ROW0__UART4_RXD_MUX                        18
-MX53_PAD_KEY_ROW0__ECSPI1_MOSI                          19
-MX53_PAD_KEY_ROW0__FEC_TX_ER                            20
-MX53_PAD_KEY_COL1__KPP_COL_1                            21
-MX53_PAD_KEY_COL1__GPIO4_8                              22
-MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS                     23
-MX53_PAD_KEY_COL1__UART5_TXD_MUX                        24
-MX53_PAD_KEY_COL1__ECSPI1_MISO                          25
-MX53_PAD_KEY_COL1__FEC_RX_CLK                           26
-MX53_PAD_KEY_COL1__USBPHY1_TXREADY                      27
-MX53_PAD_KEY_ROW1__KPP_ROW_1                            28
-MX53_PAD_KEY_ROW1__GPIO4_9                              29
-MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD                      30
-MX53_PAD_KEY_ROW1__UART5_RXD_MUX                        31
-MX53_PAD_KEY_ROW1__ECSPI1_SS0                           32
-MX53_PAD_KEY_ROW1__FEC_COL                              33
-MX53_PAD_KEY_ROW1__USBPHY1_RXVALID                      34
-MX53_PAD_KEY_COL2__KPP_COL_2                            35
-MX53_PAD_KEY_COL2__GPIO4_10                             36
-MX53_PAD_KEY_COL2__CAN1_TXCAN                           37
-MX53_PAD_KEY_COL2__FEC_MDIO                             38
-MX53_PAD_KEY_COL2__ECSPI1_SS1                           39
-MX53_PAD_KEY_COL2__FEC_RDATA_2                          40
-MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE                     41
-MX53_PAD_KEY_ROW2__KPP_ROW_2                            42
-MX53_PAD_KEY_ROW2__GPIO4_11                             43
-MX53_PAD_KEY_ROW2__CAN1_RXCAN                           44
-MX53_PAD_KEY_ROW2__FEC_MDC                              45
-MX53_PAD_KEY_ROW2__ECSPI1_SS2                           46
-MX53_PAD_KEY_ROW2__FEC_TDATA_2                          47
-MX53_PAD_KEY_ROW2__USBPHY1_RXERROR                      48
-MX53_PAD_KEY_COL3__KPP_COL_3                            49
-MX53_PAD_KEY_COL3__GPIO4_12                             50
-MX53_PAD_KEY_COL3__USBOH3_H2_DP                         51
-MX53_PAD_KEY_COL3__SPDIF_IN1                            52
-MX53_PAD_KEY_COL3__I2C2_SCL                             53
-MX53_PAD_KEY_COL3__ECSPI1_SS3                           54
-MX53_PAD_KEY_COL3__FEC_CRS                              55
-MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK                     56
-MX53_PAD_KEY_ROW3__KPP_ROW_3                            57
-MX53_PAD_KEY_ROW3__GPIO4_13                             58
-MX53_PAD_KEY_ROW3__USBOH3_H2_DM                         59
-MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK                     60
-MX53_PAD_KEY_ROW3__I2C2_SDA                             61
-MX53_PAD_KEY_ROW3__OSC32K_32K_OUT                       62
-MX53_PAD_KEY_ROW3__CCM_PLL4_BYP                         63
-MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0                  64
-MX53_PAD_KEY_COL4__KPP_COL_4                            65
-MX53_PAD_KEY_COL4__GPIO4_14                             66
-MX53_PAD_KEY_COL4__CAN2_TXCAN                           67
-MX53_PAD_KEY_COL4__IPU_SISG_4                           68
-MX53_PAD_KEY_COL4__UART5_RTS                            69
-MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC                     70
-MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1                  71
-MX53_PAD_KEY_ROW4__KPP_ROW_4                            72
-MX53_PAD_KEY_ROW4__GPIO4_15                             73
-MX53_PAD_KEY_ROW4__CAN2_RXCAN                           74
-MX53_PAD_KEY_ROW4__IPU_SISG_5                           75
-MX53_PAD_KEY_ROW4__UART5_CTS                            76
-MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR                    77
-MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID                    78
-MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK                 79
-MX53_PAD_DI0_DISP_CLK__GPIO4_16                         80
-MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR                 81
-MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0          82
-MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0                  83
-MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID                   84
-MX53_PAD_DI0_PIN15__IPU_DI0_PIN15                       85
-MX53_PAD_DI0_PIN15__GPIO4_17                            86
-MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC                     87
-MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1             88
-MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1                     89
-MX53_PAD_DI0_PIN15__USBPHY1_BVALID                      90
-MX53_PAD_DI0_PIN2__IPU_DI0_PIN2                         91
-MX53_PAD_DI0_PIN2__GPIO4_18                             92
-MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD                      93
-MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2              94
-MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2                      95
-MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION                   96
-MX53_PAD_DI0_PIN3__IPU_DI0_PIN3                         97
-MX53_PAD_DI0_PIN3__GPIO4_19                             98
-MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS                     99
-MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3              100
-MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3                      101
-MX53_PAD_DI0_PIN3__USBPHY1_IDDIG                        102
-MX53_PAD_DI0_PIN4__IPU_DI0_PIN4                         103
-MX53_PAD_DI0_PIN4__GPIO4_20                             104
-MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD                      105
-MX53_PAD_DI0_PIN4__ESDHC1_WP                            106
-MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD                     107
-MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4                      108
-MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT               109
-MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0                    110
-MX53_PAD_DISP0_DAT0__GPIO4_21                           111
-MX53_PAD_DISP0_DAT0__CSPI_SCLK                          112
-MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0                113
-MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN                114
-MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5                    115
-MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY                    116
-MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1                    117
-MX53_PAD_DISP0_DAT1__GPIO4_22                           118
-MX53_PAD_DISP0_DAT1__CSPI_MOSI                          119
-MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1                120
-MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL       121
-MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6                    122
-MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID                    123
-MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2                    124
-MX53_PAD_DISP0_DAT2__GPIO4_23                           125
-MX53_PAD_DISP0_DAT2__CSPI_MISO                          126
-MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2                127
-MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE                    128
-MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7                    129
-MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE                   130
-MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3                    131
-MX53_PAD_DISP0_DAT3__GPIO4_24                           132
-MX53_PAD_DISP0_DAT3__CSPI_SS0                           133
-MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3                134
-MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR               135
-MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8                    136
-MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR                    137
-MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4                    138
-MX53_PAD_DISP0_DAT4__GPIO4_25                           139
-MX53_PAD_DISP0_DAT4__CSPI_SS1                           140
-MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4                141
-MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB                 142
-MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9                    143
-MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK                   144
-MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5                    145
-MX53_PAD_DISP0_DAT5__GPIO4_26                           146
-MX53_PAD_DISP0_DAT5__CSPI_SS2                           147
-MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5                148
-MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS           149
-MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10                   150
-MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0                151
-MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6                    152
-MX53_PAD_DISP0_DAT6__GPIO4_27                           153
-MX53_PAD_DISP0_DAT6__CSPI_SS3                           154
-MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6                155
-MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE          156
-MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11                   157
-MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1                158
-MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7                    159
-MX53_PAD_DISP0_DAT7__GPIO4_28                           160
-MX53_PAD_DISP0_DAT7__CSPI_RDY                           161
-MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7                162
-MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0         163
-MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12                   164
-MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID                  165
-MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8                    166
-MX53_PAD_DISP0_DAT8__GPIO4_29                           167
-MX53_PAD_DISP0_DAT8__PWM1_PWMO                          168
-MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B                       169
-MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1         170
-MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13                   171
-MX53_PAD_DISP0_DAT8__USBPHY2_AVALID                     172
-MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9                    173
-MX53_PAD_DISP0_DAT9__GPIO4_30                           174
-MX53_PAD_DISP0_DAT9__PWM2_PWMO                          175
-MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B                       176
-MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2         177
-MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14                   178
-MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0                  179
-MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10                  180
-MX53_PAD_DISP0_DAT10__GPIO4_31                          181
-MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP                  182
-MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3        183
-MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15                  184
-MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1                 185
-MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11                  186
-MX53_PAD_DISP0_DAT11__GPIO5_5                           187
-MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT                  188
-MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4        189
-MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16                  190
-MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2                 191
-MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12                  192
-MX53_PAD_DISP0_DAT12__GPIO5_6                           193
-MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK                  194
-MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5        195
-MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17                  196
-MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3                 197
-MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13                  198
-MX53_PAD_DISP0_DAT13__GPIO5_7                           199
-MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS                  200
-MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0        201
-MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18                  202
-MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4                 203
-MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14                  204
-MX53_PAD_DISP0_DAT14__GPIO5_8                           205
-MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC                   206
-MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1        207
-MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19                  208
-MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5                 209
-MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15                  210
-MX53_PAD_DISP0_DAT15__GPIO5_9                           211
-MX53_PAD_DISP0_DAT15__ECSPI1_SS1                        212
-MX53_PAD_DISP0_DAT15__ECSPI2_SS1                        213
-MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2        214
-MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20                  215
-MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6                 216
-MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16                  217
-MX53_PAD_DISP0_DAT16__GPIO5_10                          218
-MX53_PAD_DISP0_DAT16__ECSPI2_MOSI                       219
-MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC                   220
-MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0                  221
-MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3        222
-MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21                  223
-MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7                 224
-MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17                  225
-MX53_PAD_DISP0_DAT17__GPIO5_11                          226
-MX53_PAD_DISP0_DAT17__ECSPI2_MISO                       227
-MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD                   228
-MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1                  229
-MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4        230
-MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22                  231
-MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18                  232
-MX53_PAD_DISP0_DAT18__GPIO5_12                          233
-MX53_PAD_DISP0_DAT18__ECSPI2_SS0                        234
-MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS                  235
-MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS                  236
-MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5        237
-MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23                  238
-MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2                     239
-MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19                  240
-MX53_PAD_DISP0_DAT19__GPIO5_13                          241
-MX53_PAD_DISP0_DAT19__ECSPI2_SCLK                       242
-MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD                   243
-MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC                   244
-MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6        245
-MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24                  246
-MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3                     247
-MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20                  248
-MX53_PAD_DISP0_DAT20__GPIO5_14                          249
-MX53_PAD_DISP0_DAT20__ECSPI1_SCLK                       250
-MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC                   251
-MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7        252
-MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25                  253
-MX53_PAD_DISP0_DAT20__SATA_PHY_TDI                      254
-MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21                  255
-MX53_PAD_DISP0_DAT21__GPIO5_15                          256
-MX53_PAD_DISP0_DAT21__ECSPI1_MOSI                       257
-MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD                   258
-MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0           259
-MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26                  260
-MX53_PAD_DISP0_DAT21__SATA_PHY_TDO                      261
-MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22                  262
-MX53_PAD_DISP0_DAT22__GPIO5_16                          263
-MX53_PAD_DISP0_DAT22__ECSPI1_MISO                       264
-MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS                  265
-MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1           266
-MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27                  267
-MX53_PAD_DISP0_DAT22__SATA_PHY_TCK                      268
-MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23                  269
-MX53_PAD_DISP0_DAT23__GPIO5_17                          270
-MX53_PAD_DISP0_DAT23__ECSPI1_SS0                        271
-MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD                   272
-MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2           273
-MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28                  274
-MX53_PAD_DISP0_DAT23__SATA_PHY_TMS                      275
-MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK                   276
-MX53_PAD_CSI0_PIXCLK__GPIO5_18                          277
-MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0                   278
-MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29                  279
-MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC                      280
-MX53_PAD_CSI0_MCLK__GPIO5_19                            281
-MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK                       282
-MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1                     283
-MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30                    284
-MX53_PAD_CSI0_MCLK__TPIU_TRCTL                          285
-MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN                 286
-MX53_PAD_CSI0_DATA_EN__GPIO5_20                         287
-MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2                  288
-MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31                 289
-MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK                       290
-MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC                     291
-MX53_PAD_CSI0_VSYNC__GPIO5_21                           292
-MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3                    293
-MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32                   294
-MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0                       295
-MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4                        296
-MX53_PAD_CSI0_DAT4__GPIO5_22                            297
-MX53_PAD_CSI0_DAT4__KPP_COL_5                           298
-MX53_PAD_CSI0_DAT4__ECSPI1_SCLK                         299
-MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP                    300
-MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC                     301
-MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33                    302
-MX53_PAD_CSI0_DAT4__TPIU_TRACE_1                        303
-MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5                        304
-MX53_PAD_CSI0_DAT5__GPIO5_23                            305
-MX53_PAD_CSI0_DAT5__KPP_ROW_5                           306
-MX53_PAD_CSI0_DAT5__ECSPI1_MOSI                         307
-MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT                    308
-MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD                     309
-MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34                    310
-MX53_PAD_CSI0_DAT5__TPIU_TRACE_2                        311
-MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6                        312
-MX53_PAD_CSI0_DAT6__GPIO5_24                            313
-MX53_PAD_CSI0_DAT6__KPP_COL_6                           314
-MX53_PAD_CSI0_DAT6__ECSPI1_MISO                         315
-MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK                    316
-MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS                    317
-MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35                    318
-MX53_PAD_CSI0_DAT6__TPIU_TRACE_3                        319
-MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7                        320
-MX53_PAD_CSI0_DAT7__GPIO5_25                            321
-MX53_PAD_CSI0_DAT7__KPP_ROW_6                           322
-MX53_PAD_CSI0_DAT7__ECSPI1_SS0                          323
-MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR                    324
-MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD                     325
-MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36                    326
-MX53_PAD_CSI0_DAT7__TPIU_TRACE_4                        327
-MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8                        328
-MX53_PAD_CSI0_DAT8__GPIO5_26                            329
-MX53_PAD_CSI0_DAT8__KPP_COL_7                           330
-MX53_PAD_CSI0_DAT8__ECSPI2_SCLK                         331
-MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC                     332
-MX53_PAD_CSI0_DAT8__I2C1_SDA                            333
-MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37                    334
-MX53_PAD_CSI0_DAT8__TPIU_TRACE_5                        335
-MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9                        336
-MX53_PAD_CSI0_DAT9__GPIO5_27                            337
-MX53_PAD_CSI0_DAT9__KPP_ROW_7                           338
-MX53_PAD_CSI0_DAT9__ECSPI2_MOSI                         339
-MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR                    340
-MX53_PAD_CSI0_DAT9__I2C1_SCL                            341
-MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38                    342
-MX53_PAD_CSI0_DAT9__TPIU_TRACE_6                        343
-MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10                      344
-MX53_PAD_CSI0_DAT10__GPIO5_28                           345
-MX53_PAD_CSI0_DAT10__UART1_TXD_MUX                      346
-MX53_PAD_CSI0_DAT10__ECSPI2_MISO                        347
-MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC                    348
-MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4                    349
-MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39                   350
-MX53_PAD_CSI0_DAT10__TPIU_TRACE_7                       351
-MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11                      352
-MX53_PAD_CSI0_DAT11__GPIO5_29                           353
-MX53_PAD_CSI0_DAT11__UART1_RXD_MUX                      354
-MX53_PAD_CSI0_DAT11__ECSPI2_SS0                         355
-MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS                   356
-MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5                    357
-MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40                   358
-MX53_PAD_CSI0_DAT11__TPIU_TRACE_8                       359
-MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12                      360
-MX53_PAD_CSI0_DAT12__GPIO5_30                           361
-MX53_PAD_CSI0_DAT12__UART4_TXD_MUX                      362
-MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0                363
-MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6                    364
-MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41                   365
-MX53_PAD_CSI0_DAT12__TPIU_TRACE_9                       366
-MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13                      367
-MX53_PAD_CSI0_DAT13__GPIO5_31                           368
-MX53_PAD_CSI0_DAT13__UART4_RXD_MUX                      369
-MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1                370
-MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7                    371
-MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42                   372
-MX53_PAD_CSI0_DAT13__TPIU_TRACE_10                      373
-MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14                      374
-MX53_PAD_CSI0_DAT14__GPIO6_0                            375
-MX53_PAD_CSI0_DAT14__UART5_TXD_MUX                      376
-MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2                377
-MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8                    378
-MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43                   379
-MX53_PAD_CSI0_DAT14__TPIU_TRACE_11                      380
-MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15                      381
-MX53_PAD_CSI0_DAT15__GPIO6_1                            382
-MX53_PAD_CSI0_DAT15__UART5_RXD_MUX                      383
-MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3                384
-MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9                    385
-MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44                   386
-MX53_PAD_CSI0_DAT15__TPIU_TRACE_12                      387
-MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16                      388
-MX53_PAD_CSI0_DAT16__GPIO6_2                            389
-MX53_PAD_CSI0_DAT16__UART4_RTS                          390
-MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4                391
-MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10                   392
-MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45                   393
-MX53_PAD_CSI0_DAT16__TPIU_TRACE_13                      394
-MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17                      395
-MX53_PAD_CSI0_DAT17__GPIO6_3                            396
-MX53_PAD_CSI0_DAT17__UART4_CTS                          397
-MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5                398
-MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11                   399
-MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46                   400
-MX53_PAD_CSI0_DAT17__TPIU_TRACE_14                      401
-MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18                      402
-MX53_PAD_CSI0_DAT18__GPIO6_4                            403
-MX53_PAD_CSI0_DAT18__UART5_RTS                          404
-MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6                405
-MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12                   406
-MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47                   407
-MX53_PAD_CSI0_DAT18__TPIU_TRACE_15                      408
-MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19                      409
-MX53_PAD_CSI0_DAT19__GPIO6_5                            410
-MX53_PAD_CSI0_DAT19__UART5_CTS                          411
-MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7                412
-MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13                   413
-MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48                   414
-MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK                     415
-MX53_PAD_EIM_A25__EMI_WEIM_A_25                         416
-MX53_PAD_EIM_A25__GPIO5_2                               417
-MX53_PAD_EIM_A25__ECSPI2_RDY                            418
-MX53_PAD_EIM_A25__IPU_DI1_PIN12                         419
-MX53_PAD_EIM_A25__CSPI_SS1                              420
-MX53_PAD_EIM_A25__IPU_DI0_D1_CS                         421
-MX53_PAD_EIM_A25__USBPHY1_BISTOK                        422
-MX53_PAD_EIM_EB2__EMI_WEIM_EB_2                         423
-MX53_PAD_EIM_EB2__GPIO2_30                              424
-MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK                       425
-MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS                      426
-MX53_PAD_EIM_EB2__ECSPI1_SS0                            427
-MX53_PAD_EIM_EB2__I2C2_SCL                              428
-MX53_PAD_EIM_D16__EMI_WEIM_D_16                         429
-MX53_PAD_EIM_D16__GPIO3_16                              430
-MX53_PAD_EIM_D16__IPU_DI0_PIN5                          431
-MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK                    432
-MX53_PAD_EIM_D16__ECSPI1_SCLK                           433
-MX53_PAD_EIM_D16__I2C2_SDA                              434
-MX53_PAD_EIM_D17__EMI_WEIM_D_17                         435
-MX53_PAD_EIM_D17__GPIO3_17                              436
-MX53_PAD_EIM_D17__IPU_DI0_PIN6                          437
-MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN                    438
-MX53_PAD_EIM_D17__ECSPI1_MISO                           439
-MX53_PAD_EIM_D17__I2C3_SCL                              440
-MX53_PAD_EIM_D18__EMI_WEIM_D_18                         441
-MX53_PAD_EIM_D18__GPIO3_18                              442
-MX53_PAD_EIM_D18__IPU_DI0_PIN7                          443
-MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO                    444
-MX53_PAD_EIM_D18__ECSPI1_MOSI                           445
-MX53_PAD_EIM_D18__I2C3_SDA                              446
-MX53_PAD_EIM_D18__IPU_DI1_D0_CS                         447
-MX53_PAD_EIM_D19__EMI_WEIM_D_19                         448
-MX53_PAD_EIM_D19__GPIO3_19                              449
-MX53_PAD_EIM_D19__IPU_DI0_PIN8                          450
-MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS                     451
-MX53_PAD_EIM_D19__ECSPI1_SS1                            452
-MX53_PAD_EIM_D19__EPIT1_EPITO                           453
-MX53_PAD_EIM_D19__UART1_CTS                             454
-MX53_PAD_EIM_D19__USBOH3_USBH2_OC                       455
-MX53_PAD_EIM_D20__EMI_WEIM_D_20                         456
-MX53_PAD_EIM_D20__GPIO3_20                              457
-MX53_PAD_EIM_D20__IPU_DI0_PIN16                         458
-MX53_PAD_EIM_D20__IPU_SER_DISP0_CS                      459
-MX53_PAD_EIM_D20__CSPI_SS0                              460
-MX53_PAD_EIM_D20__EPIT2_EPITO                           461
-MX53_PAD_EIM_D20__UART1_RTS                             462
-MX53_PAD_EIM_D20__USBOH3_USBH2_PWR                      463
-MX53_PAD_EIM_D21__EMI_WEIM_D_21                         464
-MX53_PAD_EIM_D21__GPIO3_21                              465
-MX53_PAD_EIM_D21__IPU_DI0_PIN17                         466
-MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK                    467
-MX53_PAD_EIM_D21__CSPI_SCLK                             468
-MX53_PAD_EIM_D21__I2C1_SCL                              469
-MX53_PAD_EIM_D21__USBOH3_USBOTG_OC                      470
-MX53_PAD_EIM_D22__EMI_WEIM_D_22                         471
-MX53_PAD_EIM_D22__GPIO3_22                              472
-MX53_PAD_EIM_D22__IPU_DI0_PIN1                          473
-MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN                    474
-MX53_PAD_EIM_D22__CSPI_MISO                             475
-MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR                     476
-MX53_PAD_EIM_D23__EMI_WEIM_D_23                         477
-MX53_PAD_EIM_D23__GPIO3_23                              478
-MX53_PAD_EIM_D23__UART3_CTS                             479
-MX53_PAD_EIM_D23__UART1_DCD                             480
-MX53_PAD_EIM_D23__IPU_DI0_D0_CS                         481
-MX53_PAD_EIM_D23__IPU_DI1_PIN2                          482
-MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN                      483
-MX53_PAD_EIM_D23__IPU_DI1_PIN14                         484
-MX53_PAD_EIM_EB3__EMI_WEIM_EB_3                         485
-MX53_PAD_EIM_EB3__GPIO2_31                              486
-MX53_PAD_EIM_EB3__UART3_RTS                             487
-MX53_PAD_EIM_EB3__UART1_RI                              488
-MX53_PAD_EIM_EB3__IPU_DI1_PIN3                          489
-MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC                        490
-MX53_PAD_EIM_EB3__IPU_DI1_PIN16                         491
-MX53_PAD_EIM_D24__EMI_WEIM_D_24                         492
-MX53_PAD_EIM_D24__GPIO3_24                              493
-MX53_PAD_EIM_D24__UART3_TXD_MUX                         494
-MX53_PAD_EIM_D24__ECSPI1_SS2                            495
-MX53_PAD_EIM_D24__CSPI_SS2                              496
-MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS                      497
-MX53_PAD_EIM_D24__ECSPI2_SS2                            498
-MX53_PAD_EIM_D24__UART1_DTR                             499
-MX53_PAD_EIM_D25__EMI_WEIM_D_25                         500
-MX53_PAD_EIM_D25__GPIO3_25                              501
-MX53_PAD_EIM_D25__UART3_RXD_MUX                         502
-MX53_PAD_EIM_D25__ECSPI1_SS3                            503
-MX53_PAD_EIM_D25__CSPI_SS3                              504
-MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC                       505
-MX53_PAD_EIM_D25__ECSPI2_SS3                            506
-MX53_PAD_EIM_D25__UART1_DSR                             507
-MX53_PAD_EIM_D26__EMI_WEIM_D_26                         508
-MX53_PAD_EIM_D26__GPIO3_26                              509
-MX53_PAD_EIM_D26__UART2_TXD_MUX                         510
-MX53_PAD_EIM_D26__FIRI_RXD                              511
-MX53_PAD_EIM_D26__IPU_CSI0_D_1                          512
-MX53_PAD_EIM_D26__IPU_DI1_PIN11                         513
-MX53_PAD_EIM_D26__IPU_SISG_2                            514
-MX53_PAD_EIM_D26__IPU_DISP1_DAT_22                      515
-MX53_PAD_EIM_D27__EMI_WEIM_D_27                         516
-MX53_PAD_EIM_D27__GPIO3_27                              517
-MX53_PAD_EIM_D27__UART2_RXD_MUX                         518
-MX53_PAD_EIM_D27__FIRI_TXD                              519
-MX53_PAD_EIM_D27__IPU_CSI0_D_0                          520
-MX53_PAD_EIM_D27__IPU_DI1_PIN13                         521
-MX53_PAD_EIM_D27__IPU_SISG_3                            522
-MX53_PAD_EIM_D27__IPU_DISP1_DAT_23                      523
-MX53_PAD_EIM_D28__EMI_WEIM_D_28                         524
-MX53_PAD_EIM_D28__GPIO3_28                              525
-MX53_PAD_EIM_D28__UART2_CTS                             526
-MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO                    527
-MX53_PAD_EIM_D28__CSPI_MOSI                             528
-MX53_PAD_EIM_D28__I2C1_SDA                              529
-MX53_PAD_EIM_D28__IPU_EXT_TRIG                          530
-MX53_PAD_EIM_D28__IPU_DI0_PIN13                         531
-MX53_PAD_EIM_D29__EMI_WEIM_D_29                         532
-MX53_PAD_EIM_D29__GPIO3_29                              533
-MX53_PAD_EIM_D29__UART2_RTS                             534
-MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS                     535
-MX53_PAD_EIM_D29__CSPI_SS0                              536
-MX53_PAD_EIM_D29__IPU_DI1_PIN15                         537
-MX53_PAD_EIM_D29__IPU_CSI1_VSYNC                        538
-MX53_PAD_EIM_D29__IPU_DI0_PIN14                         539
-MX53_PAD_EIM_D30__EMI_WEIM_D_30                         540
-MX53_PAD_EIM_D30__GPIO3_30                              541
-MX53_PAD_EIM_D30__UART3_CTS                             542
-MX53_PAD_EIM_D30__IPU_CSI0_D_3                          543
-MX53_PAD_EIM_D30__IPU_DI0_PIN11                         544
-MX53_PAD_EIM_D30__IPU_DISP1_DAT_21                      545
-MX53_PAD_EIM_D30__USBOH3_USBH1_OC                       546
-MX53_PAD_EIM_D30__USBOH3_USBH2_OC                       547
-MX53_PAD_EIM_D31__EMI_WEIM_D_31                         548
-MX53_PAD_EIM_D31__GPIO3_31                              549
-MX53_PAD_EIM_D31__UART3_RTS                             550
-MX53_PAD_EIM_D31__IPU_CSI0_D_2                          551
-MX53_PAD_EIM_D31__IPU_DI0_PIN12                         552
-MX53_PAD_EIM_D31__IPU_DISP1_DAT_20                      553
-MX53_PAD_EIM_D31__USBOH3_USBH1_PWR                      554
-MX53_PAD_EIM_D31__USBOH3_USBH2_PWR                      555
-MX53_PAD_EIM_A24__EMI_WEIM_A_24                         556
-MX53_PAD_EIM_A24__GPIO5_4                               557
-MX53_PAD_EIM_A24__IPU_DISP1_DAT_19                      558
-MX53_PAD_EIM_A24__IPU_CSI1_D_19                         559
-MX53_PAD_EIM_A24__IPU_SISG_2                            560
-MX53_PAD_EIM_A24__USBPHY2_BVALID                        561
-MX53_PAD_EIM_A23__EMI_WEIM_A_23                         562
-MX53_PAD_EIM_A23__GPIO6_6                               563
-MX53_PAD_EIM_A23__IPU_DISP1_DAT_18                      564
-MX53_PAD_EIM_A23__IPU_CSI1_D_18                         565
-MX53_PAD_EIM_A23__IPU_SISG_3                            566
-MX53_PAD_EIM_A23__USBPHY2_ENDSESSION                    567
-MX53_PAD_EIM_A22__EMI_WEIM_A_22                         568
-MX53_PAD_EIM_A22__GPIO2_16                              569
-MX53_PAD_EIM_A22__IPU_DISP1_DAT_17                      570
-MX53_PAD_EIM_A22__IPU_CSI1_D_17                         571
-MX53_PAD_EIM_A22__SRC_BT_CFG1_7                         572
-MX53_PAD_EIM_A21__EMI_WEIM_A_21                         573
-MX53_PAD_EIM_A21__GPIO2_17                              574
-MX53_PAD_EIM_A21__IPU_DISP1_DAT_16                      575
-MX53_PAD_EIM_A21__IPU_CSI1_D_16                         576
-MX53_PAD_EIM_A21__SRC_BT_CFG1_6                         577
-MX53_PAD_EIM_A20__EMI_WEIM_A_20                         578
-MX53_PAD_EIM_A20__GPIO2_18                              579
-MX53_PAD_EIM_A20__IPU_DISP1_DAT_15                      580
-MX53_PAD_EIM_A20__IPU_CSI1_D_15                         581
-MX53_PAD_EIM_A20__SRC_BT_CFG1_5                         582
-MX53_PAD_EIM_A19__EMI_WEIM_A_19                         583
-MX53_PAD_EIM_A19__GPIO2_19                              584
-MX53_PAD_EIM_A19__IPU_DISP1_DAT_14                      585
-MX53_PAD_EIM_A19__IPU_CSI1_D_14                         586
-MX53_PAD_EIM_A19__SRC_BT_CFG1_4                         587
-MX53_PAD_EIM_A18__EMI_WEIM_A_18                         588
-MX53_PAD_EIM_A18__GPIO2_20                              589
-MX53_PAD_EIM_A18__IPU_DISP1_DAT_13                      590
-MX53_PAD_EIM_A18__IPU_CSI1_D_13                         591
-MX53_PAD_EIM_A18__SRC_BT_CFG1_3                         592
-MX53_PAD_EIM_A17__EMI_WEIM_A_17                         593
-MX53_PAD_EIM_A17__GPIO2_21                              594
-MX53_PAD_EIM_A17__IPU_DISP1_DAT_12                      595
-MX53_PAD_EIM_A17__IPU_CSI1_D_12                         596
-MX53_PAD_EIM_A17__SRC_BT_CFG1_2                         597
-MX53_PAD_EIM_A16__EMI_WEIM_A_16                         598
-MX53_PAD_EIM_A16__GPIO2_22                              599
-MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK                      600
-MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK                       601
-MX53_PAD_EIM_A16__SRC_BT_CFG1_1                         602
-MX53_PAD_EIM_CS0__EMI_WEIM_CS_0                         603
-MX53_PAD_EIM_CS0__GPIO2_23                              604
-MX53_PAD_EIM_CS0__ECSPI2_SCLK                           605
-MX53_PAD_EIM_CS0__IPU_DI1_PIN5                          606
-MX53_PAD_EIM_CS1__EMI_WEIM_CS_1                         607
-MX53_PAD_EIM_CS1__GPIO2_24                              608
-MX53_PAD_EIM_CS1__ECSPI2_MOSI                           609
-MX53_PAD_EIM_CS1__IPU_DI1_PIN6                          610
-MX53_PAD_EIM_OE__EMI_WEIM_OE                            611
-MX53_PAD_EIM_OE__GPIO2_25                               612
-MX53_PAD_EIM_OE__ECSPI2_MISO                            613
-MX53_PAD_EIM_OE__IPU_DI1_PIN7                           614
-MX53_PAD_EIM_OE__USBPHY2_IDDIG                          615
-MX53_PAD_EIM_RW__EMI_WEIM_RW                            616
-MX53_PAD_EIM_RW__GPIO2_26                               617
-MX53_PAD_EIM_RW__ECSPI2_SS0                             618
-MX53_PAD_EIM_RW__IPU_DI1_PIN8                           619
-MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT                 620
-MX53_PAD_EIM_LBA__EMI_WEIM_LBA                          621
-MX53_PAD_EIM_LBA__GPIO2_27                              622
-MX53_PAD_EIM_LBA__ECSPI2_SS1                            623
-MX53_PAD_EIM_LBA__IPU_DI1_PIN17                         624
-MX53_PAD_EIM_LBA__SRC_BT_CFG1_0                         625
-MX53_PAD_EIM_EB0__EMI_WEIM_EB_0                         626
-MX53_PAD_EIM_EB0__GPIO2_28                              627
-MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11                      628
-MX53_PAD_EIM_EB0__IPU_CSI1_D_11                         629
-MX53_PAD_EIM_EB0__GPC_PMIC_RDY                          630
-MX53_PAD_EIM_EB0__SRC_BT_CFG2_7                         631
-MX53_PAD_EIM_EB1__EMI_WEIM_EB_1                         632
-MX53_PAD_EIM_EB1__GPIO2_29                              633
-MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10                      634
-MX53_PAD_EIM_EB1__IPU_CSI1_D_10                         635
-MX53_PAD_EIM_EB1__SRC_BT_CFG2_6                         636
-MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0                    637
-MX53_PAD_EIM_DA0__GPIO3_0                               638
-MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9                       639
-MX53_PAD_EIM_DA0__IPU_CSI1_D_9                          640
-MX53_PAD_EIM_DA0__SRC_BT_CFG2_5                         641
-MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1                    642
-MX53_PAD_EIM_DA1__GPIO3_1                               643
-MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8                       644
-MX53_PAD_EIM_DA1__IPU_CSI1_D_8                          645
-MX53_PAD_EIM_DA1__SRC_BT_CFG2_4                         646
-MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2                    647
-MX53_PAD_EIM_DA2__GPIO3_2                               648
-MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7                       649
-MX53_PAD_EIM_DA2__IPU_CSI1_D_7                          650
-MX53_PAD_EIM_DA2__SRC_BT_CFG2_3                         651
-MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3                    652
-MX53_PAD_EIM_DA3__GPIO3_3                               653
-MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6                       654
-MX53_PAD_EIM_DA3__IPU_CSI1_D_6                          655
-MX53_PAD_EIM_DA3__SRC_BT_CFG2_2                         656
-MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4                    657
-MX53_PAD_EIM_DA4__GPIO3_4                               658
-MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5                       659
-MX53_PAD_EIM_DA4__IPU_CSI1_D_5                          660
-MX53_PAD_EIM_DA4__SRC_BT_CFG3_7                         661
-MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5                    662
-MX53_PAD_EIM_DA5__GPIO3_5                               663
-MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4                       664
-MX53_PAD_EIM_DA5__IPU_CSI1_D_4                          665
-MX53_PAD_EIM_DA5__SRC_BT_CFG3_6                         666
-MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6                    667
-MX53_PAD_EIM_DA6__GPIO3_6                               668
-MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3                       669
-MX53_PAD_EIM_DA6__IPU_CSI1_D_3                          670
-MX53_PAD_EIM_DA6__SRC_BT_CFG3_5                         671
-MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7                    672
-MX53_PAD_EIM_DA7__GPIO3_7                               673
-MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2                       674
-MX53_PAD_EIM_DA7__IPU_CSI1_D_2                          675
-MX53_PAD_EIM_DA7__SRC_BT_CFG3_4                         676
-MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8                    677
-MX53_PAD_EIM_DA8__GPIO3_8                               678
-MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1                       679
-MX53_PAD_EIM_DA8__IPU_CSI1_D_1                          680
-MX53_PAD_EIM_DA8__SRC_BT_CFG3_3                         681
-MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9                    682
-MX53_PAD_EIM_DA9__GPIO3_9                               683
-MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0                       684
-MX53_PAD_EIM_DA9__IPU_CSI1_D_0                          685
-MX53_PAD_EIM_DA9__SRC_BT_CFG3_2                         686
-MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10                  687
-MX53_PAD_EIM_DA10__GPIO3_10                             688
-MX53_PAD_EIM_DA10__IPU_DI1_PIN15                        689
-MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN                     690
-MX53_PAD_EIM_DA10__SRC_BT_CFG3_1                        691
-MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11                  692
-MX53_PAD_EIM_DA11__GPIO3_11                             693
-MX53_PAD_EIM_DA11__IPU_DI1_PIN2                         694
-MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC                       695
-MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12                  696
-MX53_PAD_EIM_DA12__GPIO3_12                             697
-MX53_PAD_EIM_DA12__IPU_DI1_PIN3                         698
-MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC                       699
-MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13                  700
-MX53_PAD_EIM_DA13__GPIO3_13                             701
-MX53_PAD_EIM_DA13__IPU_DI1_D0_CS                        702
-MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK                      703
-MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14                  704
-MX53_PAD_EIM_DA14__GPIO3_14                             705
-MX53_PAD_EIM_DA14__IPU_DI1_D1_CS                        706
-MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK                      707
-MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15                  708
-MX53_PAD_EIM_DA15__GPIO3_15                             709
-MX53_PAD_EIM_DA15__IPU_DI1_PIN1                         710
-MX53_PAD_EIM_DA15__IPU_DI1_PIN4                         711
-MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B                     712
-MX53_PAD_NANDF_WE_B__GPIO6_12                           713
-MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B                     714
-MX53_PAD_NANDF_RE_B__GPIO6_13                           715
-MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT                        716
-MX53_PAD_EIM_WAIT__GPIO5_0                              717
-MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B                     718
-MX53_PAD_LVDS1_TX3_P__GPIO6_22                          719
-MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3                     720
-MX53_PAD_LVDS1_TX2_P__GPIO6_24                          721
-MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2                     722
-MX53_PAD_LVDS1_CLK_P__GPIO6_26                          723
-MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK                     724
-MX53_PAD_LVDS1_TX1_P__GPIO6_28                          725
-MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1                     726
-MX53_PAD_LVDS1_TX0_P__GPIO6_30                          727
-MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0                     728
-MX53_PAD_LVDS0_TX3_P__GPIO7_22                          729
-MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3                     730
-MX53_PAD_LVDS0_CLK_P__GPIO7_24                          731
-MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK                     732
-MX53_PAD_LVDS0_TX2_P__GPIO7_26                          733
-MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2                     734
-MX53_PAD_LVDS0_TX1_P__GPIO7_28                          735
-MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1                     736
-MX53_PAD_LVDS0_TX0_P__GPIO7_30                          737
-MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0                     738
-MX53_PAD_GPIO_10__GPIO4_0                               739
-MX53_PAD_GPIO_10__OSC32k_32K_OUT                        740
-MX53_PAD_GPIO_11__GPIO4_1                               741
-MX53_PAD_GPIO_12__GPIO4_2                               742
-MX53_PAD_GPIO_13__GPIO4_3                               743
-MX53_PAD_GPIO_14__GPIO4_4                               744
-MX53_PAD_NANDF_CLE__EMI_NANDF_CLE                       745
-MX53_PAD_NANDF_CLE__GPIO6_7                             746
-MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0                   747
-MX53_PAD_NANDF_ALE__EMI_NANDF_ALE                       748
-MX53_PAD_NANDF_ALE__GPIO6_8                             749
-MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1                   750
-MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B                     751
-MX53_PAD_NANDF_WP_B__GPIO6_9                            752
-MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2                  753
-MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0                      754
-MX53_PAD_NANDF_RB0__GPIO6_10                            755
-MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3                   756
-MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0                      757
-MX53_PAD_NANDF_CS0__GPIO6_11                            758
-MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4                   759
-MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1                      760
-MX53_PAD_NANDF_CS1__GPIO6_14                            761
-MX53_PAD_NANDF_CS1__MLB_MLBCLK                          762
-MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5                   763
-MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2                      764
-MX53_PAD_NANDF_CS2__GPIO6_15                            765
-MX53_PAD_NANDF_CS2__IPU_SISG_0                          766
-MX53_PAD_NANDF_CS2__ESAI1_TX0                           767
-MX53_PAD_NANDF_CS2__EMI_WEIM_CRE                        768
-MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK                       769
-MX53_PAD_NANDF_CS2__MLB_MLBSIG                          770
-MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6                   771
-MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3                      772
-MX53_PAD_NANDF_CS3__GPIO6_16                            773
-MX53_PAD_NANDF_CS3__IPU_SISG_1                          774
-MX53_PAD_NANDF_CS3__ESAI1_TX1                           775
-MX53_PAD_NANDF_CS3__EMI_WEIM_A_26                       776
-MX53_PAD_NANDF_CS3__MLB_MLBDAT                          777
-MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7                   778
-MX53_PAD_FEC_MDIO__FEC_MDIO                             779
-MX53_PAD_FEC_MDIO__GPIO1_22                             780
-MX53_PAD_FEC_MDIO__ESAI1_SCKR                           781
-MX53_PAD_FEC_MDIO__FEC_COL                              782
-MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2                       783
-MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3              784
-MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49                     785
-MX53_PAD_FEC_REF_CLK__FEC_TX_CLK                        786
-MX53_PAD_FEC_REF_CLK__GPIO1_23                          787
-MX53_PAD_FEC_REF_CLK__ESAI1_FSR                         788
-MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4           789
-MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50                  790
-MX53_PAD_FEC_RX_ER__FEC_RX_ER                           791
-MX53_PAD_FEC_RX_ER__GPIO1_24                            792
-MX53_PAD_FEC_RX_ER__ESAI1_HCKR                          793
-MX53_PAD_FEC_RX_ER__FEC_RX_CLK                          794
-MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3                      795
-MX53_PAD_FEC_CRS_DV__FEC_RX_DV                          796
-MX53_PAD_FEC_CRS_DV__GPIO1_25                           797
-MX53_PAD_FEC_CRS_DV__ESAI1_SCKT                         798
-MX53_PAD_FEC_RXD1__FEC_RDATA_1                          799
-MX53_PAD_FEC_RXD1__GPIO1_26                             800
-MX53_PAD_FEC_RXD1__ESAI1_FST                            801
-MX53_PAD_FEC_RXD1__MLB_MLBSIG                           802
-MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1                       803
-MX53_PAD_FEC_RXD0__FEC_RDATA_0                          804
-MX53_PAD_FEC_RXD0__GPIO1_27                             805
-MX53_PAD_FEC_RXD0__ESAI1_HCKT                           806
-MX53_PAD_FEC_RXD0__OSC32k_32K_OUT                       807
-MX53_PAD_FEC_TX_EN__FEC_TX_EN                           808
-MX53_PAD_FEC_TX_EN__GPIO1_28                            809
-MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2                       810
-MX53_PAD_FEC_TXD1__FEC_TDATA_1                          811
-MX53_PAD_FEC_TXD1__GPIO1_29                             812
-MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3                        813
-MX53_PAD_FEC_TXD1__MLB_MLBCLK                           814
-MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK                  815
-MX53_PAD_FEC_TXD0__FEC_TDATA_0                          816
-MX53_PAD_FEC_TXD0__GPIO1_30                             817
-MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1                        818
-MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0                    819
-MX53_PAD_FEC_MDC__FEC_MDC                               820
-MX53_PAD_FEC_MDC__GPIO1_31                              821
-MX53_PAD_FEC_MDC__ESAI1_TX5_RX0                         822
-MX53_PAD_FEC_MDC__MLB_MLBDAT                            823
-MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG                824
-MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1                     825
-MX53_PAD_PATA_DIOW__PATA_DIOW                           826
-MX53_PAD_PATA_DIOW__GPIO6_17                            827
-MX53_PAD_PATA_DIOW__UART1_TXD_MUX                       828
-MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2                   829
-MX53_PAD_PATA_DMACK__PATA_DMACK                         830
-MX53_PAD_PATA_DMACK__GPIO6_18                           831
-MX53_PAD_PATA_DMACK__UART1_RXD_MUX                      832
-MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3                  833
-MX53_PAD_PATA_DMARQ__PATA_DMARQ                         834
-MX53_PAD_PATA_DMARQ__GPIO7_0                            835
-MX53_PAD_PATA_DMARQ__UART2_TXD_MUX                      836
-MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0                      837
-MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4                  838
-MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN                 839
-MX53_PAD_PATA_BUFFER_EN__GPIO7_1                        840
-MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX                  841
-MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1                  842
-MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5              843
-MX53_PAD_PATA_INTRQ__PATA_INTRQ                         844
-MX53_PAD_PATA_INTRQ__GPIO7_2                            845
-MX53_PAD_PATA_INTRQ__UART2_CTS                          846
-MX53_PAD_PATA_INTRQ__CAN1_TXCAN                         847
-MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2                      848
-MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6                  849
-MX53_PAD_PATA_DIOR__PATA_DIOR                           850
-MX53_PAD_PATA_DIOR__GPIO7_3                             851
-MX53_PAD_PATA_DIOR__UART2_RTS                           852
-MX53_PAD_PATA_DIOR__CAN1_RXCAN                          853
-MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7                   854
-MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B                855
-MX53_PAD_PATA_RESET_B__GPIO7_4                          856
-MX53_PAD_PATA_RESET_B__ESDHC3_CMD                       857
-MX53_PAD_PATA_RESET_B__UART1_CTS                        858
-MX53_PAD_PATA_RESET_B__CAN2_TXCAN                       859
-MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0                860
-MX53_PAD_PATA_IORDY__PATA_IORDY                         861
-MX53_PAD_PATA_IORDY__GPIO7_5                            862
-MX53_PAD_PATA_IORDY__ESDHC3_CLK                         863
-MX53_PAD_PATA_IORDY__UART1_RTS                          864
-MX53_PAD_PATA_IORDY__CAN2_RXCAN                         865
-MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1                  866
-MX53_PAD_PATA_DA_0__PATA_DA_0                           867
-MX53_PAD_PATA_DA_0__GPIO7_6                             868
-MX53_PAD_PATA_DA_0__ESDHC3_RST                          869
-MX53_PAD_PATA_DA_0__OWIRE_LINE                          870
-MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2                   871
-MX53_PAD_PATA_DA_1__PATA_DA_1                           872
-MX53_PAD_PATA_DA_1__GPIO7_7                             873
-MX53_PAD_PATA_DA_1__ESDHC4_CMD                          874
-MX53_PAD_PATA_DA_1__UART3_CTS                           875
-MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3                   876
-MX53_PAD_PATA_DA_2__PATA_DA_2                           877
-MX53_PAD_PATA_DA_2__GPIO7_8                             878
-MX53_PAD_PATA_DA_2__ESDHC4_CLK                          879
-MX53_PAD_PATA_DA_2__UART3_RTS                           880
-MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4                   881
-MX53_PAD_PATA_CS_0__PATA_CS_0                           882
-MX53_PAD_PATA_CS_0__GPIO7_9                             883
-MX53_PAD_PATA_CS_0__UART3_TXD_MUX                       884
-MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5                   885
-MX53_PAD_PATA_CS_1__PATA_CS_1                           886
-MX53_PAD_PATA_CS_1__GPIO7_10                            887
-MX53_PAD_PATA_CS_1__UART3_RXD_MUX                       888
-MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6                   889
-MX53_PAD_PATA_DATA0__PATA_DATA_0                        890
-MX53_PAD_PATA_DATA0__GPIO2_0                            891
-MX53_PAD_PATA_DATA0__EMI_NANDF_D_0                      892
-MX53_PAD_PATA_DATA0__ESDHC3_DAT4                        893
-MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0              894
-MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0                     895
-MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7                  896
-MX53_PAD_PATA_DATA1__PATA_DATA_1                        897
-MX53_PAD_PATA_DATA1__GPIO2_1                            898
-MX53_PAD_PATA_DATA1__EMI_NANDF_D_1                      899
-MX53_PAD_PATA_DATA1__ESDHC3_DAT5                        900
-MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1              901
-MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1                     902
-MX53_PAD_PATA_DATA2__PATA_DATA_2                        903
-MX53_PAD_PATA_DATA2__GPIO2_2                            904
-MX53_PAD_PATA_DATA2__EMI_NANDF_D_2                      905
-MX53_PAD_PATA_DATA2__ESDHC3_DAT6                        906
-MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2              907
-MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2                     908
-MX53_PAD_PATA_DATA3__PATA_DATA_3                        909
-MX53_PAD_PATA_DATA3__GPIO2_3                            910
-MX53_PAD_PATA_DATA3__EMI_NANDF_D_3                      911
-MX53_PAD_PATA_DATA3__ESDHC3_DAT7                        912
-MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3              913
-MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3                     914
-MX53_PAD_PATA_DATA4__PATA_DATA_4                        915
-MX53_PAD_PATA_DATA4__GPIO2_4                            916
-MX53_PAD_PATA_DATA4__EMI_NANDF_D_4                      917
-MX53_PAD_PATA_DATA4__ESDHC4_DAT4                        918
-MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4              919
-MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4                     920
-MX53_PAD_PATA_DATA5__PATA_DATA_5                        921
-MX53_PAD_PATA_DATA5__GPIO2_5                            922
-MX53_PAD_PATA_DATA5__EMI_NANDF_D_5                      923
-MX53_PAD_PATA_DATA5__ESDHC4_DAT5                        924
-MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5              925
-MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5                     926
-MX53_PAD_PATA_DATA6__PATA_DATA_6                        927
-MX53_PAD_PATA_DATA6__GPIO2_6                            928
-MX53_PAD_PATA_DATA6__EMI_NANDF_D_6                      929
-MX53_PAD_PATA_DATA6__ESDHC4_DAT6                        930
-MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6              931
-MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6                     932
-MX53_PAD_PATA_DATA7__PATA_DATA_7                        933
-MX53_PAD_PATA_DATA7__GPIO2_7                            934
-MX53_PAD_PATA_DATA7__EMI_NANDF_D_7                      935
-MX53_PAD_PATA_DATA7__ESDHC4_DAT7                        936
-MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7              937
-MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7                     938
-MX53_PAD_PATA_DATA8__PATA_DATA_8                        939
-MX53_PAD_PATA_DATA8__GPIO2_8                            940
-MX53_PAD_PATA_DATA8__ESDHC1_DAT4                        941
-MX53_PAD_PATA_DATA8__EMI_NANDF_D_8                      942
-MX53_PAD_PATA_DATA8__ESDHC3_DAT0                        943
-MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8              944
-MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8                     945
-MX53_PAD_PATA_DATA9__PATA_DATA_9                        946
-MX53_PAD_PATA_DATA9__GPIO2_9                            947
-MX53_PAD_PATA_DATA9__ESDHC1_DAT5                        948
-MX53_PAD_PATA_DATA9__EMI_NANDF_D_9                      949
-MX53_PAD_PATA_DATA9__ESDHC3_DAT1                        950
-MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9              951
-MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9                     952
-MX53_PAD_PATA_DATA10__PATA_DATA_10                      953
-MX53_PAD_PATA_DATA10__GPIO2_10                          954
-MX53_PAD_PATA_DATA10__ESDHC1_DAT6                       955
-MX53_PAD_PATA_DATA10__EMI_NANDF_D_10                    956
-MX53_PAD_PATA_DATA10__ESDHC3_DAT2                       957
-MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10            958
-MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10                   959
-MX53_PAD_PATA_DATA11__PATA_DATA_11                      960
-MX53_PAD_PATA_DATA11__GPIO2_11                          961
-MX53_PAD_PATA_DATA11__ESDHC1_DAT7                       962
-MX53_PAD_PATA_DATA11__EMI_NANDF_D_11                    963
-MX53_PAD_PATA_DATA11__ESDHC3_DAT3                       964
-MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11            965
-MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11                   966
-MX53_PAD_PATA_DATA12__PATA_DATA_12                      967
-MX53_PAD_PATA_DATA12__GPIO2_12                          968
-MX53_PAD_PATA_DATA12__ESDHC2_DAT4                       969
-MX53_PAD_PATA_DATA12__EMI_NANDF_D_12                    970
-MX53_PAD_PATA_DATA12__ESDHC4_DAT0                       971
-MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12            972
-MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12                   973
-MX53_PAD_PATA_DATA13__PATA_DATA_13                      974
-MX53_PAD_PATA_DATA13__GPIO2_13                          975
-MX53_PAD_PATA_DATA13__ESDHC2_DAT5                       976
-MX53_PAD_PATA_DATA13__EMI_NANDF_D_13                    977
-MX53_PAD_PATA_DATA13__ESDHC4_DAT1                       978
-MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13            979
-MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13                   980
-MX53_PAD_PATA_DATA14__PATA_DATA_14                      981
-MX53_PAD_PATA_DATA14__GPIO2_14                          982
-MX53_PAD_PATA_DATA14__ESDHC2_DAT6                       983
-MX53_PAD_PATA_DATA14__EMI_NANDF_D_14                    984
-MX53_PAD_PATA_DATA14__ESDHC4_DAT2                       985
-MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14            986
-MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14                   987
-MX53_PAD_PATA_DATA15__PATA_DATA_15                      988
-MX53_PAD_PATA_DATA15__GPIO2_15                          989
-MX53_PAD_PATA_DATA15__ESDHC2_DAT7                       990
-MX53_PAD_PATA_DATA15__EMI_NANDF_D_15                    991
-MX53_PAD_PATA_DATA15__ESDHC4_DAT3                       992
-MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15            993
-MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15                   994
-MX53_PAD_SD1_DATA0__ESDHC1_DAT0                         995
-MX53_PAD_SD1_DATA0__GPIO1_16                            996
-MX53_PAD_SD1_DATA0__GPT_CAPIN1                          997
-MX53_PAD_SD1_DATA0__CSPI_MISO                           998
-MX53_PAD_SD1_DATA0__CCM_PLL3_BYP                        999
-MX53_PAD_SD1_DATA1__ESDHC1_DAT1                         1000
-MX53_PAD_SD1_DATA1__GPIO1_17                            1001
-MX53_PAD_SD1_DATA1__GPT_CAPIN2                          1002
-MX53_PAD_SD1_DATA1__CSPI_SS0                            1003
-MX53_PAD_SD1_DATA1__CCM_PLL4_BYP                        1004
-MX53_PAD_SD1_CMD__ESDHC1_CMD                            1005
-MX53_PAD_SD1_CMD__GPIO1_18                              1006
-MX53_PAD_SD1_CMD__GPT_CMPOUT1                           1007
-MX53_PAD_SD1_CMD__CSPI_MOSI                             1008
-MX53_PAD_SD1_CMD__CCM_PLL1_BYP                          1009
-MX53_PAD_SD1_DATA2__ESDHC1_DAT2                         1010
-MX53_PAD_SD1_DATA2__GPIO1_19                            1011
-MX53_PAD_SD1_DATA2__GPT_CMPOUT2                         1012
-MX53_PAD_SD1_DATA2__PWM2_PWMO                           1013
-MX53_PAD_SD1_DATA2__WDOG1_WDOG_B                        1014
-MX53_PAD_SD1_DATA2__CSPI_SS1                            1015
-MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB                1016
-MX53_PAD_SD1_DATA2__CCM_PLL2_BYP                        1017
-MX53_PAD_SD1_CLK__ESDHC1_CLK                            1018
-MX53_PAD_SD1_CLK__GPIO1_20                              1019
-MX53_PAD_SD1_CLK__OSC32k_32K_OUT                        1020
-MX53_PAD_SD1_CLK__GPT_CLKIN                             1021
-MX53_PAD_SD1_CLK__CSPI_SCLK                             1022
-MX53_PAD_SD1_CLK__SATA_PHY_DTB_0                        1023
-MX53_PAD_SD1_DATA3__ESDHC1_DAT3                         1024
-MX53_PAD_SD1_DATA3__GPIO1_21                            1025
-MX53_PAD_SD1_DATA3__GPT_CMPOUT3                         1026
-MX53_PAD_SD1_DATA3__PWM1_PWMO                           1027
-MX53_PAD_SD1_DATA3__WDOG2_WDOG_B                        1028
-MX53_PAD_SD1_DATA3__CSPI_SS2                            1029
-MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB                1030
-MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1                      1031
-MX53_PAD_SD2_CLK__ESDHC2_CLK                            1032
-MX53_PAD_SD2_CLK__GPIO1_10                              1033
-MX53_PAD_SD2_CLK__KPP_COL_5                             1034
-MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS                      1035
-MX53_PAD_SD2_CLK__CSPI_SCLK                             1036
-MX53_PAD_SD2_CLK__SCC_RANDOM_V                          1037
-MX53_PAD_SD2_CMD__ESDHC2_CMD                            1038
-MX53_PAD_SD2_CMD__GPIO1_11                              1039
-MX53_PAD_SD2_CMD__KPP_ROW_5                             1040
-MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC                       1041
-MX53_PAD_SD2_CMD__CSPI_MOSI                             1042
-MX53_PAD_SD2_CMD__SCC_RANDOM                            1043
-MX53_PAD_SD2_DATA3__ESDHC2_DAT3                         1044
-MX53_PAD_SD2_DATA3__GPIO1_12                            1045
-MX53_PAD_SD2_DATA3__KPP_COL_6                           1046
-MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC                     1047
-MX53_PAD_SD2_DATA3__CSPI_SS2                            1048
-MX53_PAD_SD2_DATA3__SJC_DONE                            1049
-MX53_PAD_SD2_DATA2__ESDHC2_DAT2                         1050
-MX53_PAD_SD2_DATA2__GPIO1_13                            1051
-MX53_PAD_SD2_DATA2__KPP_ROW_6                           1052
-MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD                     1053
-MX53_PAD_SD2_DATA2__CSPI_SS1                            1054
-MX53_PAD_SD2_DATA2__SJC_FAIL                            1055
-MX53_PAD_SD2_DATA1__ESDHC2_DAT1                         1056
-MX53_PAD_SD2_DATA1__GPIO1_14                            1057
-MX53_PAD_SD2_DATA1__KPP_COL_7                           1058
-MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS                    1059
-MX53_PAD_SD2_DATA1__CSPI_SS0                            1060
-MX53_PAD_SD2_DATA1__RTIC_SEC_VIO                        1061
-MX53_PAD_SD2_DATA0__ESDHC2_DAT0                         1062
-MX53_PAD_SD2_DATA0__GPIO1_15                            1063
-MX53_PAD_SD2_DATA0__KPP_ROW_7                           1064
-MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD                     1065
-MX53_PAD_SD2_DATA0__CSPI_MISO                           1066
-MX53_PAD_SD2_DATA0__RTIC_DONE_INT                       1067
-MX53_PAD_GPIO_0__CCM_CLKO                               1068
-MX53_PAD_GPIO_0__GPIO1_0                                1069
-MX53_PAD_GPIO_0__KPP_COL_5                              1070
-MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK                       1071
-MX53_PAD_GPIO_0__EPIT1_EPITO                            1072
-MX53_PAD_GPIO_0__SRTC_ALARM_DEB                         1073
-MX53_PAD_GPIO_0__USBOH3_USBH1_PWR                       1074
-MX53_PAD_GPIO_0__CSU_TD                                 1075
-MX53_PAD_GPIO_1__ESAI1_SCKR                             1076
-MX53_PAD_GPIO_1__GPIO1_1                                1077
-MX53_PAD_GPIO_1__KPP_ROW_5                              1078
-MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK                       1079
-MX53_PAD_GPIO_1__PWM2_PWMO                              1080
-MX53_PAD_GPIO_1__WDOG2_WDOG_B                           1081
-MX53_PAD_GPIO_1__ESDHC1_CD                              1082
-MX53_PAD_GPIO_1__SRC_TESTER_ACK                         1083
-MX53_PAD_GPIO_9__ESAI1_FSR                              1084
-MX53_PAD_GPIO_9__GPIO1_9                                1085
-MX53_PAD_GPIO_9__KPP_COL_6                              1086
-MX53_PAD_GPIO_9__CCM_REF_EN_B                           1087
-MX53_PAD_GPIO_9__PWM1_PWMO                              1088
-MX53_PAD_GPIO_9__WDOG1_WDOG_B                           1089
-MX53_PAD_GPIO_9__ESDHC1_WP                              1090
-MX53_PAD_GPIO_9__SCC_FAIL_STATE                         1091
-MX53_PAD_GPIO_3__ESAI1_HCKR                             1092
-MX53_PAD_GPIO_3__GPIO1_3                                1093
-MX53_PAD_GPIO_3__I2C3_SCL                               1094
-MX53_PAD_GPIO_3__DPLLIP1_TOG_EN                         1095
-MX53_PAD_GPIO_3__CCM_CLKO2                              1096
-MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0             1097
-MX53_PAD_GPIO_3__USBOH3_USBH1_OC                        1098
-MX53_PAD_GPIO_3__MLB_MLBCLK                             1099
-MX53_PAD_GPIO_6__ESAI1_SCKT                             1100
-MX53_PAD_GPIO_6__GPIO1_6                                1101
-MX53_PAD_GPIO_6__I2C3_SDA                               1102
-MX53_PAD_GPIO_6__CCM_CCM_OUT_0                          1103
-MX53_PAD_GPIO_6__CSU_CSU_INT_DEB                        1104
-MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1             1105
-MX53_PAD_GPIO_6__ESDHC2_LCTL                            1106
-MX53_PAD_GPIO_6__MLB_MLBSIG                             1107
-MX53_PAD_GPIO_2__ESAI1_FST                              1108
-MX53_PAD_GPIO_2__GPIO1_2                                1109
-MX53_PAD_GPIO_2__KPP_ROW_6                              1110
-MX53_PAD_GPIO_2__CCM_CCM_OUT_1                          1111
-MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0                    1112
-MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2             1113
-MX53_PAD_GPIO_2__ESDHC2_WP                              1114
-MX53_PAD_GPIO_2__MLB_MLBDAT                             1115
-MX53_PAD_GPIO_4__ESAI1_HCKT                             1116
-MX53_PAD_GPIO_4__GPIO1_4                                1117
-MX53_PAD_GPIO_4__KPP_COL_7                              1118
-MX53_PAD_GPIO_4__CCM_CCM_OUT_2                          1119
-MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1                    1120
-MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3             1121
-MX53_PAD_GPIO_4__ESDHC2_CD                              1122
-MX53_PAD_GPIO_4__SCC_SEC_STATE                          1123
-MX53_PAD_GPIO_5__ESAI1_TX2_RX3                          1124
-MX53_PAD_GPIO_5__GPIO1_5                                1125
-MX53_PAD_GPIO_5__KPP_ROW_7                              1126
-MX53_PAD_GPIO_5__CCM_CLKO                               1127
-MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2                    1128
-MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4             1129
-MX53_PAD_GPIO_5__I2C3_SCL                               1130
-MX53_PAD_GPIO_5__CCM_PLL1_BYP                           1131
-MX53_PAD_GPIO_7__ESAI1_TX4_RX1                          1132
-MX53_PAD_GPIO_7__GPIO1_7                                1133
-MX53_PAD_GPIO_7__EPIT1_EPITO                            1134
-MX53_PAD_GPIO_7__CAN1_TXCAN                             1135
-MX53_PAD_GPIO_7__UART2_TXD_MUX                          1136
-MX53_PAD_GPIO_7__FIRI_RXD                               1137
-MX53_PAD_GPIO_7__SPDIF_PLOCK                            1138
-MX53_PAD_GPIO_7__CCM_PLL2_BYP                           1139
-MX53_PAD_GPIO_8__ESAI1_TX5_RX0                          1140
-MX53_PAD_GPIO_8__GPIO1_8                                1141
-MX53_PAD_GPIO_8__EPIT2_EPITO                            1142
-MX53_PAD_GPIO_8__CAN1_RXCAN                             1143
-MX53_PAD_GPIO_8__UART2_RXD_MUX                          1144
-MX53_PAD_GPIO_8__FIRI_TXD                               1145
-MX53_PAD_GPIO_8__SPDIF_SRCLK                            1146
-MX53_PAD_GPIO_8__CCM_PLL3_BYP                           1147
-MX53_PAD_GPIO_16__ESAI1_TX3_RX2                         1148
-MX53_PAD_GPIO_16__GPIO7_11                              1149
-MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT                      1150
-MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1                  1151
-MX53_PAD_GPIO_16__SPDIF_IN1                             1152
-MX53_PAD_GPIO_16__I2C3_SDA                              1153
-MX53_PAD_GPIO_16__SJC_DE_B                              1154
-MX53_PAD_GPIO_17__ESAI1_TX0                             1155
-MX53_PAD_GPIO_17__GPIO7_12                              1156
-MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0                      1157
-MX53_PAD_GPIO_17__GPC_PMIC_RDY                          1158
-MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG                   1159
-MX53_PAD_GPIO_17__SPDIF_OUT1                            1160
-MX53_PAD_GPIO_17__IPU_SNOOP2                            1161
-MX53_PAD_GPIO_17__SJC_JTAG_ACT                          1162
-MX53_PAD_GPIO_18__ESAI1_TX1                             1163
-MX53_PAD_GPIO_18__GPIO7_13                              1164
-MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1                      1165
-MX53_PAD_GPIO_18__OWIRE_LINE                            1166
-MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG                1167
-MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK                      1168
-MX53_PAD_GPIO_18__ESDHC1_LCTL                           1169
-MX53_PAD_GPIO_18__SRC_SYSTEM_RST                        1170
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
deleted file mode 100644
index a4119f6422d..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
+++ /dev/null
@@ -1,1630 +0,0 @@
-* Freescale IMX6Q IOMUX Controller
-
-Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
-and usage.
-
-Required properties:
-- compatible: "fsl,imx6q-iomuxc"
-- fsl,pins: two integers array, represents a group of pins mux and config
-  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
-  pin working on a specific function, CONFIG is the pad setting value like
-  pull-up for this pin. Please refer to imx6q datasheet for the valid pad
-  config settings.
-
-CONFIG bits definition:
-PAD_CTL_HYS                     (1 << 16)
-PAD_CTL_PUS_100K_DOWN           (0 << 14)
-PAD_CTL_PUS_47K_UP              (1 << 14)
-PAD_CTL_PUS_100K_UP             (2 << 14)
-PAD_CTL_PUS_22K_UP              (3 << 14)
-PAD_CTL_PUE                     (1 << 13)
-PAD_CTL_PKE                     (1 << 12)
-PAD_CTL_ODE                     (1 << 11)
-PAD_CTL_SPEED_LOW               (1 << 6)
-PAD_CTL_SPEED_MED               (2 << 6)
-PAD_CTL_SPEED_HIGH              (3 << 6)
-PAD_CTL_DSE_DISABLE             (0 << 3)
-PAD_CTL_DSE_240ohm              (1 << 3)
-PAD_CTL_DSE_120ohm              (2 << 3)
-PAD_CTL_DSE_80ohm               (3 << 3)
-PAD_CTL_DSE_60ohm               (4 << 3)
-PAD_CTL_DSE_48ohm               (5 << 3)
-PAD_CTL_DSE_40ohm               (6 << 3)
-PAD_CTL_DSE_34ohm               (7 << 3)
-PAD_CTL_SRE_FAST                (1 << 0)
-PAD_CTL_SRE_SLOW                (0 << 0)
-
-See below for available PIN_FUNC_ID for imx6q:
-MX6Q_PAD_SD2_DAT1__USDHC2_DAT1                  0
-MX6Q_PAD_SD2_DAT1__ECSPI5_SS0                   1
-MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2               2
-MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS             3
-MX6Q_PAD_SD2_DAT1__KPP_COL_7                    4
-MX6Q_PAD_SD2_DAT1__GPIO_1_14                    5
-MX6Q_PAD_SD2_DAT1__CCM_WAIT                     6
-MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0               7
-MX6Q_PAD_SD2_DAT2__USDHC2_DAT2                  8
-MX6Q_PAD_SD2_DAT2__ECSPI5_SS1                   9
-MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3               10
-MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD              11
-MX6Q_PAD_SD2_DAT2__KPP_ROW_6                    12
-MX6Q_PAD_SD2_DAT2__GPIO_1_13                    13
-MX6Q_PAD_SD2_DAT2__CCM_STOP                     14
-MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1               15
-MX6Q_PAD_SD2_DAT0__USDHC2_DAT0                  16
-MX6Q_PAD_SD2_DAT0__ECSPI5_MISO                  17
-MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD              18
-MX6Q_PAD_SD2_DAT0__KPP_ROW_7                    19
-MX6Q_PAD_SD2_DAT0__GPIO_1_15                    20
-MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT               21
-MX6Q_PAD_SD2_DAT0__TESTO_2                      22
-MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA              23
-MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC              24
-MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK          25
-MX6Q_PAD_RGMII_TXC__GPIO_6_19                   26
-MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0         27
-MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT              28
-MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY         29
-MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0              30
-MX6Q_PAD_RGMII_TD0__GPIO_6_20                   31
-MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1         32
-MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG         33
-MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1              34
-MX6Q_PAD_RGMII_TD1__GPIO_6_21                   35
-MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2         36
-MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP                37
-MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA         38
-MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2              39
-MX6Q_PAD_RGMII_TD2__GPIO_6_22                   40
-MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3         41
-MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP                42
-MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK         43
-MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3              44
-MX6Q_PAD_RGMII_TD3__GPIO_6_23                   45
-MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4         46
-MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA           47
-MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL             48
-MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24                49
-MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5           50
-MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY         51
-MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0              52
-MX6Q_PAD_RGMII_RD0__GPIO_6_25                   53
-MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6         54
-MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE         55
-MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL             56
-MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26                57
-MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7           58
-MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT           59
-MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL         60
-MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1              61
-MX6Q_PAD_RGMII_RD1__GPIO_6_27                   62
-MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8         63
-MX6Q_PAD_RGMII_RD1__SJC_FAIL                    64
-MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA         65
-MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2              66
-MX6Q_PAD_RGMII_RD2__GPIO_6_28                   67
-MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9         68
-MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK         69
-MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3              70
-MX6Q_PAD_RGMII_RD3__GPIO_6_29                   71
-MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10         72
-MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE            73
-MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC              74
-MX6Q_PAD_RGMII_RXC__GPIO_6_30                   75
-MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11         76
-MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25                77
-MX6Q_PAD_EIM_A25__ECSPI4_SS1                    78
-MX6Q_PAD_EIM_A25__ECSPI2_RDY                    79
-MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12                80
-MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS                81
-MX6Q_PAD_EIM_A25__GPIO_5_2                      82
-MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE              83
-MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0           84
-MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2                85
-MX6Q_PAD_EIM_EB2__ECSPI1_SS0                    86
-MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK               87
-MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19                88
-MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL               89
-MX6Q_PAD_EIM_EB2__GPIO_2_30                     90
-MX6Q_PAD_EIM_EB2__I2C2_SCL                      91
-MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30                 92
-MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16                93
-MX6Q_PAD_EIM_D16__ECSPI1_SCLK                   94
-MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5                 95
-MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18                96
-MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA               97
-MX6Q_PAD_EIM_D16__GPIO_3_16                     98
-MX6Q_PAD_EIM_D16__I2C2_SDA                      99
-MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17                100
-MX6Q_PAD_EIM_D17__ECSPI1_MISO                   101
-MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6                 102
-MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK              103
-MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT                104
-MX6Q_PAD_EIM_D17__GPIO_3_17                     105
-MX6Q_PAD_EIM_D17__I2C3_SCL                      106
-MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1           107
-MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18                108
-MX6Q_PAD_EIM_D18__ECSPI1_MOSI                   109
-MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7                 110
-MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17                111
-MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS                112
-MX6Q_PAD_EIM_D18__GPIO_3_18                     113
-MX6Q_PAD_EIM_D18__I2C3_SDA                      114
-MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2           115
-MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19                116
-MX6Q_PAD_EIM_D19__ECSPI1_SS1                    117
-MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8                 118
-MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16                119
-MX6Q_PAD_EIM_D19__UART1_CTS                     120
-MX6Q_PAD_EIM_D19__GPIO_3_19                     121
-MX6Q_PAD_EIM_D19__EPIT1_EPITO                   122
-MX6Q_PAD_EIM_D19__PL301_PER1_HRESP              123
-MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20                124
-MX6Q_PAD_EIM_D20__ECSPI4_SS0                    125
-MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16                126
-MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15                127
-MX6Q_PAD_EIM_D20__UART1_RTS                     128
-MX6Q_PAD_EIM_D20__GPIO_3_20                     129
-MX6Q_PAD_EIM_D20__EPIT2_EPITO                   130
-MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21                131
-MX6Q_PAD_EIM_D21__ECSPI4_SCLK                   132
-MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17                133
-MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11                134
-MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC              135
-MX6Q_PAD_EIM_D21__GPIO_3_21                     136
-MX6Q_PAD_EIM_D21__I2C1_SCL                      137
-MX6Q_PAD_EIM_D21__SPDIF_IN1                     138
-MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22                139
-MX6Q_PAD_EIM_D22__ECSPI4_MISO                   140
-MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1                 141
-MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10                142
-MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR             143
-MX6Q_PAD_EIM_D22__GPIO_3_22                     144
-MX6Q_PAD_EIM_D22__SPDIF_OUT1                    145
-MX6Q_PAD_EIM_D22__PL301_PER1_HWRITE             146
-MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23                147
-MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS                148
-MX6Q_PAD_EIM_D23__UART3_CTS                     149
-MX6Q_PAD_EIM_D23__UART1_DCD                     150
-MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN             151
-MX6Q_PAD_EIM_D23__GPIO_3_23                     152
-MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2                 153
-MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14                154
-MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3                155
-MX6Q_PAD_EIM_EB3__ECSPI4_RDY                    156
-MX6Q_PAD_EIM_EB3__UART3_RTS                     157
-MX6Q_PAD_EIM_EB3__UART1_RI                      158
-MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC               159
-MX6Q_PAD_EIM_EB3__GPIO_2_31                     160
-MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3                 161
-MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31                 162
-MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24                163
-MX6Q_PAD_EIM_D24__ECSPI4_SS2                    164
-MX6Q_PAD_EIM_D24__UART3_TXD                     165
-MX6Q_PAD_EIM_D24__ECSPI1_SS2                    166
-MX6Q_PAD_EIM_D24__ECSPI2_SS2                    167
-MX6Q_PAD_EIM_D24__GPIO_3_24                     168
-MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS              169
-MX6Q_PAD_EIM_D24__UART1_DTR                     170
-MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25                171
-MX6Q_PAD_EIM_D25__ECSPI4_SS3                    172
-MX6Q_PAD_EIM_D25__UART3_RXD                     173
-MX6Q_PAD_EIM_D25__ECSPI1_SS3                    174
-MX6Q_PAD_EIM_D25__ECSPI2_SS3                    175
-MX6Q_PAD_EIM_D25__GPIO_3_25                     176
-MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC               177
-MX6Q_PAD_EIM_D25__UART1_DSR                     178
-MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26                179
-MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11                180
-MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1                 181
-MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14                182
-MX6Q_PAD_EIM_D26__UART2_TXD                     183
-MX6Q_PAD_EIM_D26__GPIO_3_26                     184
-MX6Q_PAD_EIM_D26__IPU1_SISG_2                   185
-MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22             186
-MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27                187
-MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13                188
-MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0                 189
-MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13                190
-MX6Q_PAD_EIM_D27__UART2_RXD                     191
-MX6Q_PAD_EIM_D27__GPIO_3_27                     192
-MX6Q_PAD_EIM_D27__IPU1_SISG_3                   193
-MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23             194
-MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28                195
-MX6Q_PAD_EIM_D28__I2C1_SDA                      196
-MX6Q_PAD_EIM_D28__ECSPI4_MOSI                   197
-MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12                198
-MX6Q_PAD_EIM_D28__UART2_CTS                     199
-MX6Q_PAD_EIM_D28__GPIO_3_28                     200
-MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG                 201
-MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13                202
-MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29                203
-MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15                204
-MX6Q_PAD_EIM_D29__ECSPI4_SS0                    205
-MX6Q_PAD_EIM_D29__UART2_RTS                     206
-MX6Q_PAD_EIM_D29__GPIO_3_29                     207
-MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC               208
-MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14                209
-MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30                210
-MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21             211
-MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11                212
-MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3                 213
-MX6Q_PAD_EIM_D30__UART3_CTS                     214
-MX6Q_PAD_EIM_D30__GPIO_3_30                     215
-MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC               216
-MX6Q_PAD_EIM_D30__PL301_PER1_HPROT_0            217
-MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31                218
-MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20             219
-MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12                220
-MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2                 221
-MX6Q_PAD_EIM_D31__UART3_RTS                     222
-MX6Q_PAD_EIM_D31__GPIO_3_31                     223
-MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR              224
-MX6Q_PAD_EIM_D31__PL301_PER1_HPROT_1            225
-MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24                226
-MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19             227
-MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19                228
-MX6Q_PAD_EIM_A24__IPU2_SISG_2                   229
-MX6Q_PAD_EIM_A24__IPU1_SISG_2                   230
-MX6Q_PAD_EIM_A24__GPIO_5_4                      231
-MX6Q_PAD_EIM_A24__PL301_PER1_HPROT_2            232
-MX6Q_PAD_EIM_A24__SRC_BT_CFG_24                 233
-MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23                234
-MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18             235
-MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18                236
-MX6Q_PAD_EIM_A23__IPU2_SISG_3                   237
-MX6Q_PAD_EIM_A23__IPU1_SISG_3                   238
-MX6Q_PAD_EIM_A23__GPIO_6_6                      239
-MX6Q_PAD_EIM_A23__PL301_PER1_HPROT_3            240
-MX6Q_PAD_EIM_A23__SRC_BT_CFG_23                 241
-MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22                242
-MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17             243
-MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17                244
-MX6Q_PAD_EIM_A22__GPIO_2_16                     245
-MX6Q_PAD_EIM_A22__TPSMP_HDATA_0                 246
-MX6Q_PAD_EIM_A22__SRC_BT_CFG_22                 247
-MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21                248
-MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16             249
-MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16                250
-MX6Q_PAD_EIM_A21__RESERVED_RESERVED             251
-MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18         252
-MX6Q_PAD_EIM_A21__GPIO_2_17                     253
-MX6Q_PAD_EIM_A21__TPSMP_HDATA_1                 254
-MX6Q_PAD_EIM_A21__SRC_BT_CFG_21                 255
-MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20                256
-MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15             257
-MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15                258
-MX6Q_PAD_EIM_A20__RESERVED_RESERVED             259
-MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19         260
-MX6Q_PAD_EIM_A20__GPIO_2_18                     261
-MX6Q_PAD_EIM_A20__TPSMP_HDATA_2                 262
-MX6Q_PAD_EIM_A20__SRC_BT_CFG_20                 263
-MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19                264
-MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14             265
-MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14                266
-MX6Q_PAD_EIM_A19__RESERVED_RESERVED             267
-MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20         268
-MX6Q_PAD_EIM_A19__GPIO_2_19                     269
-MX6Q_PAD_EIM_A19__TPSMP_HDATA_3                 270
-MX6Q_PAD_EIM_A19__SRC_BT_CFG_19                 271
-MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18                272
-MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13             273
-MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13                274
-MX6Q_PAD_EIM_A18__RESERVED_RESERVED             275
-MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21         276
-MX6Q_PAD_EIM_A18__GPIO_2_20                     277
-MX6Q_PAD_EIM_A18__TPSMP_HDATA_4                 278
-MX6Q_PAD_EIM_A18__SRC_BT_CFG_18                 279
-MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17                280
-MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12             281
-MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12                282
-MX6Q_PAD_EIM_A17__RESERVED_RESERVED             283
-MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22         284
-MX6Q_PAD_EIM_A17__GPIO_2_21                     285
-MX6Q_PAD_EIM_A17__TPSMP_HDATA_5                 286
-MX6Q_PAD_EIM_A17__SRC_BT_CFG_17                 287
-MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16                288
-MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK             289
-MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK              290
-MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23         291
-MX6Q_PAD_EIM_A16__GPIO_2_22                     292
-MX6Q_PAD_EIM_A16__TPSMP_HDATA_6                 293
-MX6Q_PAD_EIM_A16__SRC_BT_CFG_16                 294
-MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0                295
-MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5                 296
-MX6Q_PAD_EIM_CS0__ECSPI2_SCLK                   297
-MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24         298
-MX6Q_PAD_EIM_CS0__GPIO_2_23                     299
-MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7                 300
-MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1                301
-MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6                 302
-MX6Q_PAD_EIM_CS1__ECSPI2_MOSI                   303
-MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25         304
-MX6Q_PAD_EIM_CS1__GPIO_2_24                     305
-MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8                 306
-MX6Q_PAD_EIM_OE__WEIM_WEIM_OE                   307
-MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7                  308
-MX6Q_PAD_EIM_OE__ECSPI2_MISO                    309
-MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26          310
-MX6Q_PAD_EIM_OE__GPIO_2_25                      311
-MX6Q_PAD_EIM_OE__TPSMP_HDATA_9                  312
-MX6Q_PAD_EIM_RW__WEIM_WEIM_RW                   313
-MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8                  314
-MX6Q_PAD_EIM_RW__ECSPI2_SS0                     315
-MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27          316
-MX6Q_PAD_EIM_RW__GPIO_2_26                      317
-MX6Q_PAD_EIM_RW__TPSMP_HDATA_10                 318
-MX6Q_PAD_EIM_RW__SRC_BT_CFG_29                  319
-MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA                 320
-MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17                321
-MX6Q_PAD_EIM_LBA__ECSPI2_SS1                    322
-MX6Q_PAD_EIM_LBA__GPIO_2_27                     323
-MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11                324
-MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26                 325
-MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0                326
-MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11             327
-MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11                328
-MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0          329
-MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY                  330
-MX6Q_PAD_EIM_EB0__GPIO_2_28                     331
-MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12                332
-MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27                 333
-MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1                334
-MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10             335
-MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10                336
-MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1         337
-MX6Q_PAD_EIM_EB1__GPIO_2_29                     338
-MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13                339
-MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28                 340
-MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0              341
-MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9              342
-MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9                 343
-MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2         344
-MX6Q_PAD_EIM_DA0__GPIO_3_0                      345
-MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14                346
-MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0                  347
-MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1              348
-MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8              349
-MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8                 350
-MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3          351
-MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE            352
-MX6Q_PAD_EIM_DA1__GPIO_3_1                      353
-MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15                354
-MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1                  355
-MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2              356
-MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7              357
-MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7                 358
-MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4          359
-MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE            360
-MX6Q_PAD_EIM_DA2__GPIO_3_2                      361
-MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16                362
-MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2                  363
-MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3              364
-MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6              365
-MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6                 366
-MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5          367
-MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ                368
-MX6Q_PAD_EIM_DA3__GPIO_3_3                      369
-MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17                370
-MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3                  371
-MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4              372
-MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5              373
-MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5                 374
-MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6          375
-MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN          376
-MX6Q_PAD_EIM_DA4__GPIO_3_4                      377
-MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18                378
-MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4                  379
-MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5              380
-MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4              381
-MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4                 382
-MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7          383
-MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP          384
-MX6Q_PAD_EIM_DA5__GPIO_3_5                      385
-MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19                386
-MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5                  387
-MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6              388
-MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3              389
-MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3                 390
-MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8          391
-MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN          392
-MX6Q_PAD_EIM_DA6__GPIO_3_6                      393
-MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20                394
-MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6                  395
-MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7              396
-MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2              397
-MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2                 398
-MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9          399
-MX6Q_PAD_EIM_DA7__GPIO_3_7                      400
-MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21                401
-MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7                  402
-MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8              403
-MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1              404
-MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1                 405
-MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10         406
-MX6Q_PAD_EIM_DA8__GPIO_3_8                      407
-MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22                408
-MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8                  409
-MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9              410
-MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0              411
-MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0                 412
-MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11         413
-MX6Q_PAD_EIM_DA9__GPIO_3_9                      414
-MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23                415
-MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9                  416
-MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10            417
-MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15               418
-MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN            419
-MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12         420
-MX6Q_PAD_EIM_DA10__GPIO_3_10                    421
-MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24               422
-MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10                423
-MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11            424
-MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2                425
-MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC              426
-MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13         427
-MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6           428
-MX6Q_PAD_EIM_DA11__GPIO_3_11                    429
-MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25               430
-MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11                431
-MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12            432
-MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3                433
-MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC              434
-MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14         435
-MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3         436
-MX6Q_PAD_EIM_DA12__GPIO_3_12                    437
-MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26               438
-MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12                439
-MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13            440
-MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS               441
-MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK              442
-MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15         443
-MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4         444
-MX6Q_PAD_EIM_DA13__GPIO_3_13                    445
-MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27               446
-MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13                447
-MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14            448
-MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS               449
-MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK              450
-MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16         451
-MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5         452
-MX6Q_PAD_EIM_DA14__GPIO_3_14                    453
-MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28               454
-MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14                455
-MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15            456
-MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1                457
-MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4                458
-MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17         459
-MX6Q_PAD_EIM_DA15__GPIO_3_15                    460
-MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29               461
-MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15                462
-MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT               463
-MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B            464
-MX6Q_PAD_EIM_WAIT__GPIO_5_0                     465
-MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30               466
-MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25                467
-MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK               468
-MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16               469
-MX6Q_PAD_EIM_BCLK__GPIO_6_31                    470
-MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31               471
-MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK         472
-MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK         473
-MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28         474
-MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0         475
-MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16                476
-MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0             477
-MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15              478
-MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15              479
-MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC             480
-MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29         481
-MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1         482
-MX6Q_PAD_DI0_PIN15__GPIO_4_17                   483
-MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1           484
-MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2                485
-MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2                486
-MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD              487
-MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30          488
-MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2          489
-MX6Q_PAD_DI0_PIN2__GPIO_4_18                    490
-MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2                 491
-MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9           492
-MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3                493
-MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3                494
-MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS             495
-MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31         496
-MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3          497
-MX6Q_PAD_DI0_PIN3__GPIO_4_19                    498
-MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3            499
-MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10          500
-MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4                501
-MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4                502
-MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD              503
-MX6Q_PAD_DI0_PIN4__USDHC1_WP                    504
-MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD             505
-MX6Q_PAD_DI0_PIN4__GPIO_4_20                    506
-MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4            507
-MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11          508
-MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0           509
-MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0           510
-MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK                511
-MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0         512
-MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN          513
-MX6Q_PAD_DISP0_DAT0__GPIO_4_21                  514
-MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5          515
-MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1           516
-MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1           517
-MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI                518
-MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1         519
-MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL         520
-MX6Q_PAD_DISP0_DAT1__GPIO_4_22                  521
-MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6               522
-MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12         523
-MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2           524
-MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2           525
-MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO                526
-MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2         527
-MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE            528
-MX6Q_PAD_DISP0_DAT2__GPIO_4_23                  529
-MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7               530
-MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13         531
-MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3           532
-MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3           533
-MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0                 534
-MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3         535
-MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR         536
-MX6Q_PAD_DISP0_DAT3__GPIO_4_24                  537
-MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8            538
-MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14         539
-MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4           540
-MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4           541
-MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1                 542
-MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4         543
-MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB         544
-MX6Q_PAD_DISP0_DAT4__GPIO_4_25                  545
-MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9          546
-MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15         547
-MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5           548
-MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5           549
-MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2                 550
-MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS           551
-MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS         552
-MX6Q_PAD_DISP0_DAT5__GPIO_4_26                  553
-MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10              554
-MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16         555
-MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6           556
-MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6           557
-MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3                 558
-MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC            559
-MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT         560
-MX6Q_PAD_DISP0_DAT6__GPIO_4_27                  561
-MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11              562
-MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17         563
-MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7           564
-MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7           565
-MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY                 566
-MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5         567
-MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0         568
-MX6Q_PAD_DISP0_DAT7__GPIO_4_28                  569
-MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12              570
-MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18         571
-MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8           572
-MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8           573
-MX6Q_PAD_DISP0_DAT8__PWM1_PWMO                  574
-MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B               575
-MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1         576
-MX6Q_PAD_DISP0_DAT8__GPIO_4_29                  577
-MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13              578
-MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19         579
-MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9           580
-MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9           581
-MX6Q_PAD_DISP0_DAT9__PWM2_PWMO                  582
-MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B               583
-MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2         584
-MX6Q_PAD_DISP0_DAT9__GPIO_4_30                  585
-MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14              586
-MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20         587
-MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10         588
-MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10         589
-MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6              590
-MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3         591
-MX6Q_PAD_DISP0_DAT10__GPIO_4_31                 592
-MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15             593
-MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21         594
-MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11         595
-MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11         596
-MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7         597
-MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4         598
-MX6Q_PAD_DISP0_DAT11__GPIO_5_5                  599
-MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16             600
-MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22         601
-MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12         602
-MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12         603
-MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED         604
-MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5         605
-MX6Q_PAD_DISP0_DAT12__GPIO_5_6                  606
-MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17             607
-MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23         608
-MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13         609
-MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13         610
-MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS          611
-MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0         612
-MX6Q_PAD_DISP0_DAT13__GPIO_5_7                  613
-MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18             614
-MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24         615
-MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14         616
-MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14         617
-MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC           618
-MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1         619
-MX6Q_PAD_DISP0_DAT14__GPIO_5_8                  620
-MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19             621
-MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15         622
-MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15         623
-MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1                624
-MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1                625
-MX6Q_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2         626
-MX6Q_PAD_DISP0_DAT15__GPIO_5_9                  627
-MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20             628
-MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25         629
-MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16         630
-MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16         631
-MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI               632
-MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC           633
-MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0          634
-MX6Q_PAD_DISP0_DAT16__GPIO_5_10                 635
-MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21             636
-MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26         637
-MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17         638
-MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17         639
-MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO               640
-MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD           641
-MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1          642
-MX6Q_PAD_DISP0_DAT17__GPIO_5_11                 643
-MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22             644
-MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27         645
-MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18         646
-MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18         647
-MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0                648
-MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS          649
-MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS          650
-MX6Q_PAD_DISP0_DAT18__GPIO_5_12                 651
-MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23             652
-MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2            653
-MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19         654
-MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19         655
-MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK               656
-MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD           657
-MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC           658
-MX6Q_PAD_DISP0_DAT19__GPIO_5_13                 659
-MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24             660
-MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3            661
-MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20         662
-MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20         663
-MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK               664
-MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC           665
-MX6Q_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7         666
-MX6Q_PAD_DISP0_DAT20__GPIO_5_14                 667
-MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25             668
-MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28         669
-MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21         670
-MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21         671
-MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI               672
-MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD           673
-MX6Q_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0         674
-MX6Q_PAD_DISP0_DAT21__GPIO_5_15                 675
-MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26             676
-MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29         677
-MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22         678
-MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22         679
-MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO               680
-MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS          681
-MX6Q_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1         682
-MX6Q_PAD_DISP0_DAT22__GPIO_5_16                 683
-MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27             684
-MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30         685
-MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23         686
-MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23         687
-MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0                688
-MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD           689
-MX6Q_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2         690
-MX6Q_PAD_DISP0_DAT23__GPIO_5_17                 691
-MX6Q_PAD_DISP0_DAT23__MMDC_DEBUG_28             692
-MX6Q_PAD_DISP0_DAT23__PL301_PER1_HADR31         693
-MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED           694
-MX6Q_PAD_ENET_MDIO__ENET_MDIO                   695
-MX6Q_PAD_ENET_MDIO__ESAI1_SCKR                  696
-MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3         697
-MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT          698
-MX6Q_PAD_ENET_MDIO__GPIO_1_22                   699
-MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK                 700
-MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED          701
-MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK              702
-MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR                703
-MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4         704
-MX6Q_PAD_ENET_REF_CLK__GPIO_1_23                705
-MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK              706
-MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH           707
-MX6Q_PAD_ENET_RX_ER__ENET_RX_ER                 708
-MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR                 709
-MX6Q_PAD_ENET_RX_ER__SPDIF_IN1                  710
-MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT         711
-MX6Q_PAD_ENET_RX_ER__GPIO_1_24                  712
-MX6Q_PAD_ENET_RX_ER__PHY_TDI                    713
-MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD          714
-MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED           715
-MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN                716
-MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT                717
-MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK              718
-MX6Q_PAD_ENET_CRS_DV__GPIO_1_25                 719
-MX6Q_PAD_ENET_CRS_DV__PHY_TDO                   720
-MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD         721
-MX6Q_PAD_ENET_RXD1__MLB_MLBSIG                  722
-MX6Q_PAD_ENET_RXD1__ENET_RDATA_1                723
-MX6Q_PAD_ENET_RXD1__ESAI1_FST                   724
-MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT          725
-MX6Q_PAD_ENET_RXD1__GPIO_1_26                   726
-MX6Q_PAD_ENET_RXD1__PHY_TCK                     727
-MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON           728
-MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT              729
-MX6Q_PAD_ENET_RXD0__ENET_RDATA_0                730
-MX6Q_PAD_ENET_RXD0__ESAI1_HCKT                  731
-MX6Q_PAD_ENET_RXD0__SPDIF_OUT1                  732
-MX6Q_PAD_ENET_RXD0__GPIO_1_27                   733
-MX6Q_PAD_ENET_RXD0__PHY_TMS                     734
-MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV         735
-MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED            736
-MX6Q_PAD_ENET_TX_EN__ENET_TX_EN                 737
-MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2              738
-MX6Q_PAD_ENET_TX_EN__GPIO_1_28                  739
-MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI               740
-MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH             741
-MX6Q_PAD_ENET_TXD1__MLB_MLBCLK                  742
-MX6Q_PAD_ENET_TXD1__ENET_TDATA_1                743
-MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3               744
-MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN         745
-MX6Q_PAD_ENET_TXD1__GPIO_1_29                   746
-MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO                747
-MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD           748
-MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED             749
-MX6Q_PAD_ENET_TXD0__ENET_TDATA_0                750
-MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1               751
-MX6Q_PAD_ENET_TXD0__GPIO_1_30                   752
-MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK                753
-MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD           754
-MX6Q_PAD_ENET_MDC__MLB_MLBDAT                   755
-MX6Q_PAD_ENET_MDC__ENET_MDC                     756
-MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0                757
-MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN          758
-MX6Q_PAD_ENET_MDC__GPIO_1_31                    759
-MX6Q_PAD_ENET_MDC__SATA_PHY_TMS                 760
-MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON            761
-MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40               762
-MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41               763
-MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42               764
-MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43               765
-MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44               766
-MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45               767
-MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46               768
-MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47               769
-MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5           770
-MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5             771
-MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32               772
-MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33               773
-MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34               774
-MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35               775
-MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36               776
-MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37               777
-MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38               778
-MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39               779
-MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4             780
-MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4           781
-MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24               782
-MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25               783
-MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26               784
-MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27               785
-MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28               786
-MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29               787
-MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3           788
-MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30               789
-MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31               790
-MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3             791
-MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16               792
-MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17               793
-MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18               794
-MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19               795
-MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20               796
-MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21               797
-MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22               798
-MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2           799
-MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23               800
-MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2             801
-MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0                 802
-MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1                 803
-MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2                 804
-MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3                 805
-MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4                 806
-MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5                 807
-MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6                 808
-MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7                 809
-MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8                 810
-MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9                 811
-MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10               812
-MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11               813
-MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12               814
-MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13               815
-MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14               816
-MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15               817
-MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS                818
-MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0               819
-MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1               820
-MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS                821
-MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET            822
-MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0           823
-MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1           824
-MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0         825
-MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2           826
-MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0         827
-MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1         828
-MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1         829
-MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0           830
-MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1           831
-MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE              832
-MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0                 833
-MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1                 834
-MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2                 835
-MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3                 836
-MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4                 837
-MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5                 838
-MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0           839
-MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6                 840
-MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7                 841
-MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0             842
-MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8                 843
-MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9                 844
-MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10               845
-MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11               846
-MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12               847
-MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13               848
-MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14               849
-MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1           850
-MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15               851
-MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1             852
-MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48               853
-MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49               854
-MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50               855
-MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51               856
-MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52               857
-MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53               858
-MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54               859
-MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55               860
-MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6           861
-MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6             862
-MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56               863
-MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7           864
-MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57               865
-MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58               866
-MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59               867
-MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60               868
-MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7             869
-MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61               870
-MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62               871
-MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63               872
-MX6Q_PAD_KEY_COL0__ECSPI1_SCLK                  873
-MX6Q_PAD_KEY_COL0__ENET_RDATA_3                 874
-MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC              875
-MX6Q_PAD_KEY_COL0__KPP_COL_0                    876
-MX6Q_PAD_KEY_COL0__UART4_TXD                    877
-MX6Q_PAD_KEY_COL0__GPIO_4_6                     878
-MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT               879
-MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST               880
-MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI                  881
-MX6Q_PAD_KEY_ROW0__ENET_TDATA_3                 882
-MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD              883
-MX6Q_PAD_KEY_ROW0__KPP_ROW_0                    884
-MX6Q_PAD_KEY_ROW0__UART4_RXD                    885
-MX6Q_PAD_KEY_ROW0__GPIO_4_7                     886
-MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT               887
-MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0            888
-MX6Q_PAD_KEY_COL1__ECSPI1_MISO                  889
-MX6Q_PAD_KEY_COL1__ENET_MDIO                    890
-MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS             891
-MX6Q_PAD_KEY_COL1__KPP_COL_1                    892
-MX6Q_PAD_KEY_COL1__UART5_TXD                    893
-MX6Q_PAD_KEY_COL1__GPIO_4_8                     894
-MX6Q_PAD_KEY_COL1__USDHC1_VSELECT               895
-MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1          896
-MX6Q_PAD_KEY_ROW1__ECSPI1_SS0                   897
-MX6Q_PAD_KEY_ROW1__ENET_COL                     898
-MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD              899
-MX6Q_PAD_KEY_ROW1__KPP_ROW_1                    900
-MX6Q_PAD_KEY_ROW1__UART5_RXD                    901
-MX6Q_PAD_KEY_ROW1__GPIO_4_9                     902
-MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT               903
-MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2           904
-MX6Q_PAD_KEY_COL2__ECSPI1_SS1                   905
-MX6Q_PAD_KEY_COL2__ENET_RDATA_2                 906
-MX6Q_PAD_KEY_COL2__CAN1_TXCAN                   907
-MX6Q_PAD_KEY_COL2__KPP_COL_2                    908
-MX6Q_PAD_KEY_COL2__ENET_MDC                     909
-MX6Q_PAD_KEY_COL2__GPIO_4_10                    910
-MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP         911
-MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3           912
-MX6Q_PAD_KEY_ROW2__ECSPI1_SS2                   913
-MX6Q_PAD_KEY_ROW2__ENET_TDATA_2                 914
-MX6Q_PAD_KEY_ROW2__CAN1_RXCAN                   915
-MX6Q_PAD_KEY_ROW2__KPP_ROW_2                    916
-MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT               917
-MX6Q_PAD_KEY_ROW2__GPIO_4_11                    918
-MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE             919
-MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4            920
-MX6Q_PAD_KEY_COL3__ECSPI1_SS3                   921
-MX6Q_PAD_KEY_COL3__ENET_CRS                     922
-MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL              923
-MX6Q_PAD_KEY_COL3__KPP_COL_3                    924
-MX6Q_PAD_KEY_COL3__I2C2_SCL                     925
-MX6Q_PAD_KEY_COL3__GPIO_4_12                    926
-MX6Q_PAD_KEY_COL3__SPDIF_IN1                    927
-MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5            928
-MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT               929
-MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK            930
-MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA              931
-MX6Q_PAD_KEY_ROW3__KPP_ROW_3                    932
-MX6Q_PAD_KEY_ROW3__I2C2_SDA                     933
-MX6Q_PAD_KEY_ROW3__GPIO_4_13                    934
-MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT               935
-MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6            936
-MX6Q_PAD_KEY_COL4__CAN2_TXCAN                   937
-MX6Q_PAD_KEY_COL4__IPU1_SISG_4                  938
-MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC             939
-MX6Q_PAD_KEY_COL4__KPP_COL_4                    940
-MX6Q_PAD_KEY_COL4__UART5_RTS                    941
-MX6Q_PAD_KEY_COL4__GPIO_4_14                    942
-MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49                943
-MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7           944
-MX6Q_PAD_KEY_ROW4__CAN2_RXCAN                   945
-MX6Q_PAD_KEY_ROW4__IPU1_SISG_5                  946
-MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR            947
-MX6Q_PAD_KEY_ROW4__KPP_ROW_4                    948
-MX6Q_PAD_KEY_ROW4__UART5_CTS                    949
-MX6Q_PAD_KEY_ROW4__GPIO_4_15                    950
-MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50                951
-MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8            952
-MX6Q_PAD_GPIO_0__CCM_CLKO                       953
-MX6Q_PAD_GPIO_0__KPP_COL_5                      954
-MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK              955
-MX6Q_PAD_GPIO_0__EPIT1_EPITO                    956
-MX6Q_PAD_GPIO_0__GPIO_1_0                       957
-MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR               958
-MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5         959
-MX6Q_PAD_GPIO_1__ESAI1_SCKR                     960
-MX6Q_PAD_GPIO_1__WDOG2_WDOG_B                   961
-MX6Q_PAD_GPIO_1__KPP_ROW_5                      962
-MX6Q_PAD_GPIO_1__PWM2_PWMO                      963
-MX6Q_PAD_GPIO_1__GPIO_1_1                       964
-MX6Q_PAD_GPIO_1__USDHC1_CD                      965
-MX6Q_PAD_GPIO_1__SRC_TESTER_ACK                 966
-MX6Q_PAD_GPIO_9__ESAI1_FSR                      967
-MX6Q_PAD_GPIO_9__WDOG1_WDOG_B                   968
-MX6Q_PAD_GPIO_9__KPP_COL_6                      969
-MX6Q_PAD_GPIO_9__CCM_REF_EN_B                   970
-MX6Q_PAD_GPIO_9__PWM1_PWMO                      971
-MX6Q_PAD_GPIO_9__GPIO_1_9                       972
-MX6Q_PAD_GPIO_9__USDHC1_WP                      973
-MX6Q_PAD_GPIO_9__SRC_EARLY_RST                  974
-MX6Q_PAD_GPIO_3__ESAI1_HCKR                     975
-MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0           976
-MX6Q_PAD_GPIO_3__I2C3_SCL                       977
-MX6Q_PAD_GPIO_3__ANATOP_24M_OUT                 978
-MX6Q_PAD_GPIO_3__CCM_CLKO2                      979
-MX6Q_PAD_GPIO_3__GPIO_1_3                       980
-MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC                981
-MX6Q_PAD_GPIO_3__MLB_MLBCLK                     982
-MX6Q_PAD_GPIO_6__ESAI1_SCKT                     983
-MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1           984
-MX6Q_PAD_GPIO_6__I2C3_SDA                       985
-MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0                  986
-MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB                987
-MX6Q_PAD_GPIO_6__GPIO_1_6                       988
-MX6Q_PAD_GPIO_6__USDHC2_LCTL                    989
-MX6Q_PAD_GPIO_6__MLB_MLBSIG                     990
-MX6Q_PAD_GPIO_2__ESAI1_FST                      991
-MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2           992
-MX6Q_PAD_GPIO_2__KPP_ROW_6                      993
-MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1                  994
-MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0            995
-MX6Q_PAD_GPIO_2__GPIO_1_2                       996
-MX6Q_PAD_GPIO_2__USDHC2_WP                      997
-MX6Q_PAD_GPIO_2__MLB_MLBDAT                     998
-MX6Q_PAD_GPIO_4__ESAI1_HCKT                     999
-MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3           1000
-MX6Q_PAD_GPIO_4__KPP_COL_7                      1001
-MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2                  1002
-MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1            1003
-MX6Q_PAD_GPIO_4__GPIO_1_4                       1004
-MX6Q_PAD_GPIO_4__USDHC2_CD                      1005
-MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA         1006
-MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3                  1007
-MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4           1008
-MX6Q_PAD_GPIO_5__KPP_ROW_7                      1009
-MX6Q_PAD_GPIO_5__CCM_CLKO                       1010
-MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2            1011
-MX6Q_PAD_GPIO_5__GPIO_1_5                       1012
-MX6Q_PAD_GPIO_5__I2C3_SCL                       1013
-MX6Q_PAD_GPIO_5__CHEETAH_EVENTI                 1014
-MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1                  1015
-MX6Q_PAD_GPIO_7__ECSPI5_RDY                     1016
-MX6Q_PAD_GPIO_7__EPIT1_EPITO                    1017
-MX6Q_PAD_GPIO_7__CAN1_TXCAN                     1018
-MX6Q_PAD_GPIO_7__UART2_TXD                      1019
-MX6Q_PAD_GPIO_7__GPIO_1_7                       1020
-MX6Q_PAD_GPIO_7__SPDIF_PLOCK                    1021
-MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE         1022
-MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0                  1023
-MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT          1024
-MX6Q_PAD_GPIO_8__EPIT2_EPITO                    1025
-MX6Q_PAD_GPIO_8__CAN1_RXCAN                     1026
-MX6Q_PAD_GPIO_8__UART2_RXD                      1027
-MX6Q_PAD_GPIO_8__GPIO_1_8                       1028
-MX6Q_PAD_GPIO_8__SPDIF_SRCLK                    1029
-MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK          1030
-MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2                 1031
-MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN           1032
-MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT         1033
-MX6Q_PAD_GPIO_16__USDHC1_LCTL                   1034
-MX6Q_PAD_GPIO_16__SPDIF_IN1                     1035
-MX6Q_PAD_GPIO_16__GPIO_7_11                     1036
-MX6Q_PAD_GPIO_16__I2C3_SDA                      1037
-MX6Q_PAD_GPIO_16__SJC_DE_B                      1038
-MX6Q_PAD_GPIO_17__ESAI1_TX0                     1039
-MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN           1040
-MX6Q_PAD_GPIO_17__CCM_PMIC_RDY                  1041
-MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0         1042
-MX6Q_PAD_GPIO_17__SPDIF_OUT1                    1043
-MX6Q_PAD_GPIO_17__GPIO_7_12                     1044
-MX6Q_PAD_GPIO_17__SJC_JTAG_ACT                  1045
-MX6Q_PAD_GPIO_18__ESAI1_TX1                     1046
-MX6Q_PAD_GPIO_18__ENET_RX_CLK                   1047
-MX6Q_PAD_GPIO_18__USDHC3_VSELECT                1048
-MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1         1049
-MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK             1050
-MX6Q_PAD_GPIO_18__GPIO_7_13                     1051
-MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5         1052
-MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST                1053
-MX6Q_PAD_GPIO_19__KPP_COL_5                     1054
-MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT          1055
-MX6Q_PAD_GPIO_19__SPDIF_OUT1                    1056
-MX6Q_PAD_GPIO_19__CCM_CLKO                      1057
-MX6Q_PAD_GPIO_19__ECSPI1_RDY                    1058
-MX6Q_PAD_GPIO_19__GPIO_4_5                      1059
-MX6Q_PAD_GPIO_19__ENET_TX_ER                    1060
-MX6Q_PAD_GPIO_19__SRC_INT_BOOT                  1061
-MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK          1062
-MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12          1063
-MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0           1064
-MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18                 1065
-MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29            1066
-MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO            1067
-MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC             1068
-MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13            1069
-MX6Q_PAD_CSI0_MCLK__CCM_CLKO                    1070
-MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1             1071
-MX6Q_PAD_CSI0_MCLK__GPIO_5_19                   1072
-MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30          1073
-MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL               1074
-MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN          1075
-MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0            1076
-MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14         1077
-MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2          1078
-MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20                1079
-MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31            1080
-MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK            1081
-MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC            1082
-MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1              1083
-MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15           1084
-MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3            1085
-MX6Q_PAD_CSI0_VSYNC__GPIO_5_21                  1086
-MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32              1087
-MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0            1088
-MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4               1089
-MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2               1090
-MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK                 1091
-MX6Q_PAD_CSI0_DAT4__KPP_COL_5                   1092
-MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC             1093
-MX6Q_PAD_CSI0_DAT4__GPIO_5_22                   1094
-MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43               1095
-MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1             1096
-MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5               1097
-MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3               1098
-MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI                 1099
-MX6Q_PAD_CSI0_DAT5__KPP_ROW_5                   1100
-MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD             1101
-MX6Q_PAD_CSI0_DAT5__GPIO_5_23                   1102
-MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44          1103
-MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2             1104
-MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6               1105
-MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4               1106
-MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO                 1107
-MX6Q_PAD_CSI0_DAT6__KPP_COL_6                   1108
-MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS            1109
-MX6Q_PAD_CSI0_DAT6__GPIO_5_24                   1110
-MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45          1111
-MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3             1112
-MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7               1113
-MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5               1114
-MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0                  1115
-MX6Q_PAD_CSI0_DAT7__KPP_ROW_6                   1116
-MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD             1117
-MX6Q_PAD_CSI0_DAT7__GPIO_5_25                   1118
-MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46          1119
-MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4             1120
-MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8               1121
-MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6               1122
-MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK                 1123
-MX6Q_PAD_CSI0_DAT8__KPP_COL_7                   1124
-MX6Q_PAD_CSI0_DAT8__I2C1_SDA                    1125
-MX6Q_PAD_CSI0_DAT8__GPIO_5_26                   1126
-MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47          1127
-MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5             1128
-MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9               1129
-MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7               1130
-MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI                 1131
-MX6Q_PAD_CSI0_DAT9__KPP_ROW_7                   1132
-MX6Q_PAD_CSI0_DAT9__I2C1_SCL                    1133
-MX6Q_PAD_CSI0_DAT9__GPIO_5_27                   1134
-MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48          1135
-MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6             1136
-MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10             1137
-MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC            1138
-MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO                1139
-MX6Q_PAD_CSI0_DAT10__UART1_TXD                  1140
-MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4            1141
-MX6Q_PAD_CSI0_DAT10__GPIO_5_28                  1142
-MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33         1143
-MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7            1144
-MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11             1145
-MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS           1146
-MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0                 1147
-MX6Q_PAD_CSI0_DAT11__UART1_RXD                  1148
-MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5            1149
-MX6Q_PAD_CSI0_DAT11__GPIO_5_29                  1150
-MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34         1151
-MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8            1152
-MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12             1153
-MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8              1154
-MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16           1155
-MX6Q_PAD_CSI0_DAT12__UART4_TXD                  1156
-MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6            1157
-MX6Q_PAD_CSI0_DAT12__GPIO_5_30                  1158
-MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35         1159
-MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9            1160
-MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13             1161
-MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9              1162
-MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17           1163
-MX6Q_PAD_CSI0_DAT13__UART4_RXD                  1164
-MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7            1165
-MX6Q_PAD_CSI0_DAT13__GPIO_5_31                  1166
-MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36         1167
-MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10           1168
-MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14             1169
-MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10             1170
-MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18           1171
-MX6Q_PAD_CSI0_DAT14__UART5_TXD                  1172
-MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8            1173
-MX6Q_PAD_CSI0_DAT14__GPIO_6_0                   1174
-MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37         1175
-MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11           1176
-MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15             1177
-MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11             1178
-MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19           1179
-MX6Q_PAD_CSI0_DAT15__UART5_RXD                  1180
-MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9            1181
-MX6Q_PAD_CSI0_DAT15__GPIO_6_1                   1182
-MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38         1183
-MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12           1184
-MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16             1185
-MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12             1186
-MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20           1187
-MX6Q_PAD_CSI0_DAT16__UART4_RTS                  1188
-MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10           1189
-MX6Q_PAD_CSI0_DAT16__GPIO_6_2                   1190
-MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39         1191
-MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13           1192
-MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17             1193
-MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13             1194
-MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21           1195
-MX6Q_PAD_CSI0_DAT17__UART4_CTS                  1196
-MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11           1197
-MX6Q_PAD_CSI0_DAT17__GPIO_6_3                   1198
-MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40         1199
-MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14           1200
-MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18             1201
-MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14             1202
-MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22           1203
-MX6Q_PAD_CSI0_DAT18__UART5_RTS                  1204
-MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12           1205
-MX6Q_PAD_CSI0_DAT18__GPIO_6_4                   1206
-MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41         1207
-MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15           1208
-MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19             1209
-MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15             1210
-MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23           1211
-MX6Q_PAD_CSI0_DAT19__UART5_CTS                  1212
-MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13           1213
-MX6Q_PAD_CSI0_DAT19__GPIO_6_5                   1214
-MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42         1215
-MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9             1216
-MX6Q_PAD_JTAG_TMS__SJC_TMS                      1217
-MX6Q_PAD_JTAG_MOD__SJC_MOD                      1218
-MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB                  1219
-MX6Q_PAD_JTAG_TDI__SJC_TDI                      1220
-MX6Q_PAD_JTAG_TCK__SJC_TCK                      1221
-MX6Q_PAD_JTAG_TDO__SJC_TDO                      1222
-MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3             1223
-MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2             1224
-MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK             1225
-MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1             1226
-MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0             1227
-MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3             1228
-MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK             1229
-MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2             1230
-MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1             1231
-MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0             1232
-MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1          1233
-MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM         1234
-MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ         1235
-MX6Q_PAD_POR_B__SRC_POR_B                       1236
-MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1            1237
-MX6Q_PAD_RESET_IN_B__SRC_RESET_B                1238
-MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0            1239
-MX6Q_PAD_TEST_MODE__TCU_TEST_MODE               1240
-MX6Q_PAD_SD3_DAT7__USDHC3_DAT7                  1241
-MX6Q_PAD_SD3_DAT7__UART1_TXD                    1242
-MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24             1243
-MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0         1244
-MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0         1245
-MX6Q_PAD_SD3_DAT7__GPIO_6_17                    1246
-MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12         1247
-MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV             1248
-MX6Q_PAD_SD3_DAT6__USDHC3_DAT6                  1249
-MX6Q_PAD_SD3_DAT6__UART1_RXD                    1250
-MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25             1251
-MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1         1252
-MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1         1253
-MX6Q_PAD_SD3_DAT6__GPIO_6_18                    1254
-MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13         1255
-MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10              1256
-MX6Q_PAD_SD3_DAT5__USDHC3_DAT5                  1257
-MX6Q_PAD_SD3_DAT5__UART2_TXD                    1258
-MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26             1259
-MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2         1260
-MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2         1261
-MX6Q_PAD_SD3_DAT5__GPIO_7_0                     1262
-MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14         1263
-MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11              1264
-MX6Q_PAD_SD3_DAT4__USDHC3_DAT4                  1265
-MX6Q_PAD_SD3_DAT4__UART2_RXD                    1266
-MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27             1267
-MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3         1268
-MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3         1269
-MX6Q_PAD_SD3_DAT4__GPIO_7_1                     1270
-MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15         1271
-MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12              1272
-MX6Q_PAD_SD3_CMD__USDHC3_CMD                    1273
-MX6Q_PAD_SD3_CMD__UART2_CTS                     1274
-MX6Q_PAD_SD3_CMD__CAN1_TXCAN                    1275
-MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4          1276
-MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4          1277
-MX6Q_PAD_SD3_CMD__GPIO_7_2                      1278
-MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16          1279
-MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13               1280
-MX6Q_PAD_SD3_CLK__USDHC3_CLK                    1281
-MX6Q_PAD_SD3_CLK__UART2_RTS                     1282
-MX6Q_PAD_SD3_CLK__CAN1_RXCAN                    1283
-MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5          1284
-MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5          1285
-MX6Q_PAD_SD3_CLK__GPIO_7_3                      1286
-MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17          1287
-MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14               1288
-MX6Q_PAD_SD3_DAT0__USDHC3_DAT0                  1289
-MX6Q_PAD_SD3_DAT0__UART1_CTS                    1290
-MX6Q_PAD_SD3_DAT0__CAN2_TXCAN                   1291
-MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6         1292
-MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6         1293
-MX6Q_PAD_SD3_DAT0__GPIO_7_4                     1294
-MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18         1295
-MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15              1296
-MX6Q_PAD_SD3_DAT1__USDHC3_DAT1                  1297
-MX6Q_PAD_SD3_DAT1__UART1_RTS                    1298
-MX6Q_PAD_SD3_DAT1__CAN2_RXCAN                   1299
-MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7         1300
-MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7         1301
-MX6Q_PAD_SD3_DAT1__GPIO_7_5                     1302
-MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19         1303
-MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0               1304
-MX6Q_PAD_SD3_DAT2__USDHC3_DAT2                  1305
-MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28             1306
-MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8         1307
-MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8         1308
-MX6Q_PAD_SD3_DAT2__GPIO_7_6                     1309
-MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20         1310
-MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1               1311
-MX6Q_PAD_SD3_DAT3__USDHC3_DAT3                  1312
-MX6Q_PAD_SD3_DAT3__UART3_CTS                    1313
-MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29             1314
-MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9         1315
-MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9         1316
-MX6Q_PAD_SD3_DAT3__GPIO_7_7                     1317
-MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21         1318
-MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2               1319
-MX6Q_PAD_SD3_RST__USDHC3_RST                    1320
-MX6Q_PAD_SD3_RST__UART3_RTS                     1321
-MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30              1322
-MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10         1323
-MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10         1324
-MX6Q_PAD_SD3_RST__GPIO_7_8                      1325
-MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22          1326
-MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3         1327
-MX6Q_PAD_NANDF_CLE__RAWNAND_CLE                 1328
-MX6Q_PAD_NANDF_CLE__IPU2_SISG_4                 1329
-MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31            1330
-MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11         1331
-MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11         1332
-MX6Q_PAD_NANDF_CLE__GPIO_6_7                    1333
-MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23         1334
-MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0              1335
-MX6Q_PAD_NANDF_ALE__RAWNAND_ALE                 1336
-MX6Q_PAD_NANDF_ALE__USDHC4_RST                  1337
-MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0             1338
-MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12         1339
-MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12         1340
-MX6Q_PAD_NANDF_ALE__GPIO_6_8                    1341
-MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24          1342
-MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1              1343
-MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN             1344
-MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5                1345
-MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1           1346
-MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13         1347
-MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13         1348
-MX6Q_PAD_NANDF_WP_B__GPIO_6_9                   1349
-MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32         1350
-MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0         1351
-MX6Q_PAD_NANDF_RB0__RAWNAND_READY0              1352
-MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1               1353
-MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2             1354
-MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14         1355
-MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14         1356
-MX6Q_PAD_NANDF_RB0__GPIO_6_10                   1357
-MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33         1358
-MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1          1359
-MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N                1360
-MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15         1361
-MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15         1362
-MX6Q_PAD_NANDF_CS0__GPIO_6_11                   1363
-MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2          1364
-MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N                1365
-MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT              1366
-MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT              1367
-MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3             1368
-MX6Q_PAD_NANDF_CS1__GPIO_6_14                   1369
-MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT          1370
-MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N                1371
-MX6Q_PAD_NANDF_CS2__IPU1_SISG_0                 1372
-MX6Q_PAD_NANDF_CS2__ESAI1_TX0                   1373
-MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE               1374
-MX6Q_PAD_NANDF_CS2__CCM_CLKO2                   1375
-MX6Q_PAD_NANDF_CS2__GPIO_6_15                   1376
-MX6Q_PAD_NANDF_CS2__IPU2_SISG_0                 1377
-MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N                1378
-MX6Q_PAD_NANDF_CS3__IPU1_SISG_1                 1379
-MX6Q_PAD_NANDF_CS3__ESAI1_TX1                   1380
-MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26              1381
-MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4             1382
-MX6Q_PAD_NANDF_CS3__GPIO_6_16                   1383
-MX6Q_PAD_NANDF_CS3__IPU2_SISG_1                 1384
-MX6Q_PAD_NANDF_CS3__TPSMP_CLK                   1385
-MX6Q_PAD_SD4_CMD__USDHC4_CMD                    1386
-MX6Q_PAD_SD4_CMD__RAWNAND_RDN                   1387
-MX6Q_PAD_SD4_CMD__UART3_TXD                     1388
-MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5               1389
-MX6Q_PAD_SD4_CMD__GPIO_7_9                      1390
-MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR               1391
-MX6Q_PAD_SD4_CLK__USDHC4_CLK                    1392
-MX6Q_PAD_SD4_CLK__RAWNAND_WRN                   1393
-MX6Q_PAD_SD4_CLK__UART3_RXD                     1394
-MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6               1395
-MX6Q_PAD_SD4_CLK__GPIO_7_10                     1396
-MX6Q_PAD_NANDF_D0__RAWNAND_D0                   1397
-MX6Q_PAD_NANDF_D0__USDHC1_DAT4                  1398
-MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0          1399
-MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16         1400
-MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16         1401
-MX6Q_PAD_NANDF_D0__GPIO_2_0                     1402
-MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0          1403
-MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0          1404
-MX6Q_PAD_NANDF_D1__RAWNAND_D1                   1405
-MX6Q_PAD_NANDF_D1__USDHC1_DAT5                  1406
-MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1         1407
-MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17         1408
-MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17         1409
-MX6Q_PAD_NANDF_D1__GPIO_2_1                     1410
-MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1          1411
-MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1          1412
-MX6Q_PAD_NANDF_D2__RAWNAND_D2                   1413
-MX6Q_PAD_NANDF_D2__USDHC1_DAT6                  1414
-MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2          1415
-MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18         1416
-MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18         1417
-MX6Q_PAD_NANDF_D2__GPIO_2_2                     1418
-MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2          1419
-MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2          1420
-MX6Q_PAD_NANDF_D3__RAWNAND_D3                   1421
-MX6Q_PAD_NANDF_D3__USDHC1_DAT7                  1422
-MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3          1423
-MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19         1424
-MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19         1425
-MX6Q_PAD_NANDF_D3__GPIO_2_3                     1426
-MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3          1427
-MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3          1428
-MX6Q_PAD_NANDF_D4__RAWNAND_D4                   1429
-MX6Q_PAD_NANDF_D4__USDHC2_DAT4                  1430
-MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4          1431
-MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20         1432
-MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20         1433
-MX6Q_PAD_NANDF_D4__GPIO_2_4                     1434
-MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4          1435
-MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4          1436
-MX6Q_PAD_NANDF_D5__RAWNAND_D5                   1437
-MX6Q_PAD_NANDF_D5__USDHC2_DAT5                  1438
-MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5          1439
-MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21         1440
-MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21         1441
-MX6Q_PAD_NANDF_D5__GPIO_2_5                     1442
-MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5          1443
-MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5          1444
-MX6Q_PAD_NANDF_D6__RAWNAND_D6                   1445
-MX6Q_PAD_NANDF_D6__USDHC2_DAT6                  1446
-MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6          1447
-MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22         1448
-MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22         1449
-MX6Q_PAD_NANDF_D6__GPIO_2_6                     1450
-MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6          1451
-MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6          1452
-MX6Q_PAD_NANDF_D7__RAWNAND_D7                   1453
-MX6Q_PAD_NANDF_D7__USDHC2_DAT7                  1454
-MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7          1455
-MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23         1456
-MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23         1457
-MX6Q_PAD_NANDF_D7__GPIO_2_7                     1458
-MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7          1459
-MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7          1460
-MX6Q_PAD_SD4_DAT0__RAWNAND_D8                   1461
-MX6Q_PAD_SD4_DAT0__USDHC4_DAT0                  1462
-MX6Q_PAD_SD4_DAT0__RAWNAND_DQS                  1463
-MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24         1464
-MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24         1465
-MX6Q_PAD_SD4_DAT0__GPIO_2_8                     1466
-MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8          1467
-MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8          1468
-MX6Q_PAD_SD4_DAT1__RAWNAND_D9                   1469
-MX6Q_PAD_SD4_DAT1__USDHC4_DAT1                  1470
-MX6Q_PAD_SD4_DAT1__PWM3_PWMO                    1471
-MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25         1472
-MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25         1473
-MX6Q_PAD_SD4_DAT1__GPIO_2_9                     1474
-MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9          1475
-MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9          1476
-MX6Q_PAD_SD4_DAT2__RAWNAND_D10                  1477
-MX6Q_PAD_SD4_DAT2__USDHC4_DAT2                  1478
-MX6Q_PAD_SD4_DAT2__PWM4_PWMO                    1479
-MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26         1480
-MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26         1481
-MX6Q_PAD_SD4_DAT2__GPIO_2_10                    1482
-MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10         1483
-MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10         1484
-MX6Q_PAD_SD4_DAT3__RAWNAND_D11                  1485
-MX6Q_PAD_SD4_DAT3__USDHC4_DAT3                  1486
-MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27         1487
-MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27         1488
-MX6Q_PAD_SD4_DAT3__GPIO_2_11                    1489
-MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11         1490
-MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11         1491
-MX6Q_PAD_SD4_DAT4__RAWNAND_D12                  1492
-MX6Q_PAD_SD4_DAT4__USDHC4_DAT4                  1493
-MX6Q_PAD_SD4_DAT4__UART2_RXD                    1494
-MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28         1495
-MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28         1496
-MX6Q_PAD_SD4_DAT4__GPIO_2_12                    1497
-MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12         1498
-MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12         1499
-MX6Q_PAD_SD4_DAT5__RAWNAND_D13                  1500
-MX6Q_PAD_SD4_DAT5__USDHC4_DAT5                  1501
-MX6Q_PAD_SD4_DAT5__UART2_RTS                    1502
-MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29         1503
-MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29         1504
-MX6Q_PAD_SD4_DAT5__GPIO_2_13                    1505
-MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13         1506
-MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13         1507
-MX6Q_PAD_SD4_DAT6__RAWNAND_D14                  1508
-MX6Q_PAD_SD4_DAT6__USDHC4_DAT6                  1509
-MX6Q_PAD_SD4_DAT6__UART2_CTS                    1510
-MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30         1511
-MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30         1512
-MX6Q_PAD_SD4_DAT6__GPIO_2_14                    1513
-MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14         1514
-MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14         1515
-MX6Q_PAD_SD4_DAT7__RAWNAND_D15                  1516
-MX6Q_PAD_SD4_DAT7__USDHC4_DAT7                  1517
-MX6Q_PAD_SD4_DAT7__UART2_TXD                    1518
-MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31         1519
-MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31         1520
-MX6Q_PAD_SD4_DAT7__GPIO_2_15                    1521
-MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15         1522
-MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15         1523
-MX6Q_PAD_SD1_DAT1__USDHC1_DAT1                  1524
-MX6Q_PAD_SD1_DAT1__ECSPI5_SS0                   1525
-MX6Q_PAD_SD1_DAT1__PWM3_PWMO                    1526
-MX6Q_PAD_SD1_DAT1__GPT_CAPIN2                   1527
-MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7              1528
-MX6Q_PAD_SD1_DAT1__GPIO_1_17                    1529
-MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0            1530
-MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8               1531
-MX6Q_PAD_SD1_DAT0__USDHC1_DAT0                  1532
-MX6Q_PAD_SD1_DAT0__ECSPI5_MISO                  1533
-MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS         1534
-MX6Q_PAD_SD1_DAT0__GPT_CAPIN1                   1535
-MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8              1536
-MX6Q_PAD_SD1_DAT0__GPIO_1_16                    1537
-MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1            1538
-MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7               1539
-MX6Q_PAD_SD1_DAT3__USDHC1_DAT3                  1540
-MX6Q_PAD_SD1_DAT3__ECSPI5_SS2                   1541
-MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3                  1542
-MX6Q_PAD_SD1_DAT3__PWM1_PWMO                    1543
-MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B                 1544
-MX6Q_PAD_SD1_DAT3__GPIO_1_21                    1545
-MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB         1546
-MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6               1547
-MX6Q_PAD_SD1_CMD__USDHC1_CMD                    1548
-MX6Q_PAD_SD1_CMD__ECSPI5_MOSI                   1549
-MX6Q_PAD_SD1_CMD__PWM4_PWMO                     1550
-MX6Q_PAD_SD1_CMD__GPT_CMPOUT1                   1551
-MX6Q_PAD_SD1_CMD__GPIO_1_18                     1552
-MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5                1553
-MX6Q_PAD_SD1_DAT2__USDHC1_DAT2                  1554
-MX6Q_PAD_SD1_DAT2__ECSPI5_SS1                   1555
-MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2                  1556
-MX6Q_PAD_SD1_DAT2__PWM2_PWMO                    1557
-MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B                 1558
-MX6Q_PAD_SD1_DAT2__GPIO_1_19                    1559
-MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB         1560
-MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4               1561
-MX6Q_PAD_SD1_CLK__USDHC1_CLK                    1562
-MX6Q_PAD_SD1_CLK__ECSPI5_SCLK                   1563
-MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT                1564
-MX6Q_PAD_SD1_CLK__GPT_CLKIN                     1565
-MX6Q_PAD_SD1_CLK__GPIO_1_20                     1566
-MX6Q_PAD_SD1_CLK__PHY_DTB_0                     1567
-MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0                1568
-MX6Q_PAD_SD2_CLK__USDHC2_CLK                    1569
-MX6Q_PAD_SD2_CLK__ECSPI5_SCLK                   1570
-MX6Q_PAD_SD2_CLK__KPP_COL_5                     1571
-MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS              1572
-MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9               1573
-MX6Q_PAD_SD2_CLK__GPIO_1_10                     1574
-MX6Q_PAD_SD2_CLK__PHY_DTB_1                     1575
-MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1                1576
-MX6Q_PAD_SD2_CMD__USDHC2_CMD                    1577
-MX6Q_PAD_SD2_CMD__ECSPI5_MOSI                   1578
-MX6Q_PAD_SD2_CMD__KPP_ROW_5                     1579
-MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC               1580
-MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10              1581
-MX6Q_PAD_SD2_CMD__GPIO_1_11                     1582
-MX6Q_PAD_SD2_DAT3__USDHC2_DAT3                  1583
-MX6Q_PAD_SD2_DAT3__ECSPI5_SS3                   1584
-MX6Q_PAD_SD2_DAT3__KPP_COL_6                    1585
-MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC              1586
-MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11             1587
-MX6Q_PAD_SD2_DAT3__GPIO_1_12                    1588
-MX6Q_PAD_SD2_DAT3__SJC_DONE                     1589
-MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3               1590
-MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID           1591
-MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID               1592
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt
deleted file mode 100644
index f7e8e8f4d9a..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt
+++ /dev/null
@@ -1,918 +0,0 @@
-* Freescale MXS Pin Controller
-
-The pins controlled by mxs pin controller are organized in banks, each bank
-has 32 pins.  Each pin has 4 multiplexing functions, and generally, the 4th
-function is GPIO.  The configuration on the pins includes drive strength,
-voltage and pull-up.
-
-Required properties:
-- compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
-- reg: Should contain the register physical address and length for the
-  pin controller.
-
-Please refer to pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices.
-
-The node of mxs pin controller acts as a container for an arbitrary number of
-subnodes.  Each of these subnodes represents some desired configuration for
-a group of pins, and only affects those parameters that are explicitly listed.
-In other words, a subnode that describes a drive strength parameter implies no
-information about pull-up. For this reason, even seemingly boolean values are
-actually tristates in this binding: unspecified, off, or on. Unspecified is
-represented as an absent property, and off/on are represented as integer
-values 0 and 1.
-
-Those subnodes under mxs pin controller node will fall into two categories.
-One is to set up a group of pins for a function, both mux selection and pin
-configurations, and it's called group node in the binding document.   The other
-one is to adjust the pin configuration for some particular pins that need a
-different configuration than what is defined in group node.  The binding
-document calls this type of node config node.
-
-On mxs, there is no hardware pin group. The pin group in this binding only
-means a group of pins put together for particular peripheral to work in
-particular function, like SSP0 functioning as mmc0-8bit.  That said, the
-group node should include all the pins needed for one function rather than
-having these pins defined in several group nodes.  It also means each of
-"pinctrl-*" phandle in client device node should only have one group node
-pointed in there, while the phandle can have multiple config node referenced
-there to adjust configurations for some pins in the group.
-
-Required subnode-properties:
-- fsl,pinmux-ids: An integer array.  Each integer in the array specify a pin
-  with given mux function, with bank, pin and mux packed as below.
-
-    [15..12] : bank number
-    [11..4]  : pin number
-    [3..0]   : mux selection
-
-  This integer with mux selection packed is used as an entity by both group
-  and config nodes to identify a pin.  The mux selection in the integer takes
-  effects only on group node, and will get ignored by driver with config node,
-  since config node is only meant to set up pin configurations.
-
-  Valid values for these integers are listed below.
-
-- reg: Should be the index of the group nodes for same function.  This property
-  is required only for group nodes, and should not be present in any config
-  nodes.
-
-Optional subnode-properties:
-- fsl,drive-strength: Integer.
-    0: 4 mA
-    1: 8 mA
-    2: 12 mA
-    3: 16 mA
-- fsl,voltage: Integer.
-    0: 1.8 V
-    1: 3.3 V
-- fsl,pull-up: Integer.
-    0: Disable the internal pull-up
-    1: Enable the internal pull-up
-
-Examples:
-
-pinctrl@80018000 {
-        #address-cells = <1>;
-        #size-cells = <0>;
-        compatible = "fsl,imx28-pinctrl";
-        reg = <0x80018000 2000>;
-
-        mmc0_8bit_pins_a: mmc0-8bit@0 {
-                reg = <0>;
-                fsl,pinmux-ids = <
-                        0x2000 0x2010 0x2020 0x2030
-                        0x2040 0x2050 0x2060 0x2070
-                        0x2080 0x2090 0x20a0>;
-                fsl,drive-strength = <1>;
-                fsl,voltage = <1>;
-                fsl,pull-up = <1>;
-        };
-
-        mmc_cd_cfg: mmc-cd-cfg {
-                fsl,pinmux-ids = <0x2090>;
-                fsl,pull-up = <0>;
-        };
-
-        mmc_sck_cfg: mmc-sck-cfg {
-                fsl,pinmux-ids = <0x20a0>;
-                fsl,drive-strength = <2>;
-                fsl,pull-up = <0>;
-        };
-};
-
-In this example, group node mmc0-8bit defines a group of pins for mxs SSP0
-to function as a 8-bit mmc device, with 8mA, 3.3V and pull-up configurations
-applied on all these pins.  And config nodes mmc-cd-cfg and mmc-sck-cfg are
-adjusting the configuration for pins card-detection and clock from what group
-node mmc0-8bit defines.  Only the configuration properties to be adjusted need
-to be listed in the config nodes.
-
-Valid values for i.MX28 pinmux-id:
-
-pinmux                                          id
-------                                          --
-MX28_PAD_GPMI_D00__GPMI_D0                      0x0000
-MX28_PAD_GPMI_D01__GPMI_D1                      0x0010
-MX28_PAD_GPMI_D02__GPMI_D2                      0x0020
-MX28_PAD_GPMI_D03__GPMI_D3                      0x0030
-MX28_PAD_GPMI_D04__GPMI_D4                      0x0040
-MX28_PAD_GPMI_D05__GPMI_D5                      0x0050
-MX28_PAD_GPMI_D06__GPMI_D6                      0x0060
-MX28_PAD_GPMI_D07__GPMI_D7                      0x0070
-MX28_PAD_GPMI_CE0N__GPMI_CE0N                   0x0100
-MX28_PAD_GPMI_CE1N__GPMI_CE1N                   0x0110
-MX28_PAD_GPMI_CE2N__GPMI_CE2N                   0x0120
-MX28_PAD_GPMI_CE3N__GPMI_CE3N                   0x0130
-MX28_PAD_GPMI_RDY0__GPMI_READY0                 0x0140
-MX28_PAD_GPMI_RDY1__GPMI_READY1                 0x0150
-MX28_PAD_GPMI_RDY2__GPMI_READY2                 0x0160
-MX28_PAD_GPMI_RDY3__GPMI_READY3                 0x0170
-MX28_PAD_GPMI_RDN__GPMI_RDN                     0x0180
-MX28_PAD_GPMI_WRN__GPMI_WRN                     0x0190
-MX28_PAD_GPMI_ALE__GPMI_ALE                     0x01a0
-MX28_PAD_GPMI_CLE__GPMI_CLE                     0x01b0
-MX28_PAD_GPMI_RESETN__GPMI_RESETN               0x01c0
-MX28_PAD_LCD_D00__LCD_D0                        0x1000
-MX28_PAD_LCD_D01__LCD_D1                        0x1010
-MX28_PAD_LCD_D02__LCD_D2                        0x1020
-MX28_PAD_LCD_D03__LCD_D3                        0x1030
-MX28_PAD_LCD_D04__LCD_D4                        0x1040
-MX28_PAD_LCD_D05__LCD_D5                        0x1050
-MX28_PAD_LCD_D06__LCD_D6                        0x1060
-MX28_PAD_LCD_D07__LCD_D7                        0x1070
-MX28_PAD_LCD_D08__LCD_D8                        0x1080
-MX28_PAD_LCD_D09__LCD_D9                        0x1090
-MX28_PAD_LCD_D10__LCD_D10                       0x10a0
-MX28_PAD_LCD_D11__LCD_D11                       0x10b0
-MX28_PAD_LCD_D12__LCD_D12                       0x10c0
-MX28_PAD_LCD_D13__LCD_D13                       0x10d0
-MX28_PAD_LCD_D14__LCD_D14                       0x10e0
-MX28_PAD_LCD_D15__LCD_D15                       0x10f0
-MX28_PAD_LCD_D16__LCD_D16                       0x1100
-MX28_PAD_LCD_D17__LCD_D17                       0x1110
-MX28_PAD_LCD_D18__LCD_D18                       0x1120
-MX28_PAD_LCD_D19__LCD_D19                       0x1130
-MX28_PAD_LCD_D20__LCD_D20                       0x1140
-MX28_PAD_LCD_D21__LCD_D21                       0x1150
-MX28_PAD_LCD_D22__LCD_D22                       0x1160
-MX28_PAD_LCD_D23__LCD_D23                       0x1170
-MX28_PAD_LCD_RD_E__LCD_RD_E                     0x1180
-MX28_PAD_LCD_WR_RWN__LCD_WR_RWN                 0x1190
-MX28_PAD_LCD_RS__LCD_RS                         0x11a0
-MX28_PAD_LCD_CS__LCD_CS                         0x11b0
-MX28_PAD_LCD_VSYNC__LCD_VSYNC                   0x11c0
-MX28_PAD_LCD_HSYNC__LCD_HSYNC                   0x11d0
-MX28_PAD_LCD_DOTCLK__LCD_DOTCLK                 0x11e0
-MX28_PAD_LCD_ENABLE__LCD_ENABLE                 0x11f0
-MX28_PAD_SSP0_DATA0__SSP0_D0                    0x2000
-MX28_PAD_SSP0_DATA1__SSP0_D1                    0x2010
-MX28_PAD_SSP0_DATA2__SSP0_D2                    0x2020
-MX28_PAD_SSP0_DATA3__SSP0_D3                    0x2030
-MX28_PAD_SSP0_DATA4__SSP0_D4                    0x2040
-MX28_PAD_SSP0_DATA5__SSP0_D5                    0x2050
-MX28_PAD_SSP0_DATA6__SSP0_D6                    0x2060
-MX28_PAD_SSP0_DATA7__SSP0_D7                    0x2070
-MX28_PAD_SSP0_CMD__SSP0_CMD                     0x2080
-MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT          0x2090
-MX28_PAD_SSP0_SCK__SSP0_SCK                     0x20a0
-MX28_PAD_SSP1_SCK__SSP1_SCK                     0x20c0
-MX28_PAD_SSP1_CMD__SSP1_CMD                     0x20d0
-MX28_PAD_SSP1_DATA0__SSP1_D0                    0x20e0
-MX28_PAD_SSP1_DATA3__SSP1_D3                    0x20f0
-MX28_PAD_SSP2_SCK__SSP2_SCK                     0x2100
-MX28_PAD_SSP2_MOSI__SSP2_CMD                    0x2110
-MX28_PAD_SSP2_MISO__SSP2_D0                     0x2120
-MX28_PAD_SSP2_SS0__SSP2_D3                      0x2130
-MX28_PAD_SSP2_SS1__SSP2_D4                      0x2140
-MX28_PAD_SSP2_SS2__SSP2_D5                      0x2150
-MX28_PAD_SSP3_SCK__SSP3_SCK                     0x2180
-MX28_PAD_SSP3_MOSI__SSP3_CMD                    0x2190
-MX28_PAD_SSP3_MISO__SSP3_D0                     0x21a0
-MX28_PAD_SSP3_SS0__SSP3_D3                      0x21b0
-MX28_PAD_AUART0_RX__AUART0_RX                   0x3000
-MX28_PAD_AUART0_TX__AUART0_TX                   0x3010
-MX28_PAD_AUART0_CTS__AUART0_CTS                 0x3020
-MX28_PAD_AUART0_RTS__AUART0_RTS                 0x3030
-MX28_PAD_AUART1_RX__AUART1_RX                   0x3040
-MX28_PAD_AUART1_TX__AUART1_TX                   0x3050
-MX28_PAD_AUART1_CTS__AUART1_CTS                 0x3060
-MX28_PAD_AUART1_RTS__AUART1_RTS                 0x3070
-MX28_PAD_AUART2_RX__AUART2_RX                   0x3080
-MX28_PAD_AUART2_TX__AUART2_TX                   0x3090
-MX28_PAD_AUART2_CTS__AUART2_CTS                 0x30a0
-MX28_PAD_AUART2_RTS__AUART2_RTS                 0x30b0
-MX28_PAD_AUART3_RX__AUART3_RX                   0x30c0
-MX28_PAD_AUART3_TX__AUART3_TX                   0x30d0
-MX28_PAD_AUART3_CTS__AUART3_CTS                 0x30e0
-MX28_PAD_AUART3_RTS__AUART3_RTS                 0x30f0
-MX28_PAD_PWM0__PWM_0                            0x3100
-MX28_PAD_PWM1__PWM_1                            0x3110
-MX28_PAD_PWM2__PWM_2                            0x3120
-MX28_PAD_SAIF0_MCLK__SAIF0_MCLK                 0x3140
-MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK               0x3150
-MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK             0x3160
-MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0             0x3170
-MX28_PAD_I2C0_SCL__I2C0_SCL                     0x3180
-MX28_PAD_I2C0_SDA__I2C0_SDA                     0x3190
-MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0             0x31a0
-MX28_PAD_SPDIF__SPDIF_TX                        0x31b0
-MX28_PAD_PWM3__PWM_3                            0x31c0
-MX28_PAD_PWM4__PWM_4                            0x31d0
-MX28_PAD_LCD_RESET__LCD_RESET                   0x31e0
-MX28_PAD_ENET0_MDC__ENET0_MDC                   0x4000
-MX28_PAD_ENET0_MDIO__ENET0_MDIO                 0x4010
-MX28_PAD_ENET0_RX_EN__ENET0_RX_EN               0x4020
-MX28_PAD_ENET0_RXD0__ENET0_RXD0                 0x4030
-MX28_PAD_ENET0_RXD1__ENET0_RXD1                 0x4040
-MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK             0x4050
-MX28_PAD_ENET0_TX_EN__ENET0_TX_EN               0x4060
-MX28_PAD_ENET0_TXD0__ENET0_TXD0                 0x4070
-MX28_PAD_ENET0_TXD1__ENET0_TXD1                 0x4080
-MX28_PAD_ENET0_RXD2__ENET0_RXD2                 0x4090
-MX28_PAD_ENET0_RXD3__ENET0_RXD3                 0x40a0
-MX28_PAD_ENET0_TXD2__ENET0_TXD2                 0x40b0
-MX28_PAD_ENET0_TXD3__ENET0_TXD3                 0x40c0
-MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK             0x40d0
-MX28_PAD_ENET0_COL__ENET0_COL                   0x40e0
-MX28_PAD_ENET0_CRS__ENET0_CRS                   0x40f0
-MX28_PAD_ENET_CLK__CLKCTRL_ENET                 0x4100
-MX28_PAD_JTAG_RTCK__JTAG_RTCK                   0x4140
-MX28_PAD_EMI_D00__EMI_DATA0                     0x5000
-MX28_PAD_EMI_D01__EMI_DATA1                     0x5010
-MX28_PAD_EMI_D02__EMI_DATA2                     0x5020
-MX28_PAD_EMI_D03__EMI_DATA3                     0x5030
-MX28_PAD_EMI_D04__EMI_DATA4                     0x5040
-MX28_PAD_EMI_D05__EMI_DATA5                     0x5050
-MX28_PAD_EMI_D06__EMI_DATA6                     0x5060
-MX28_PAD_EMI_D07__EMI_DATA7                     0x5070
-MX28_PAD_EMI_D08__EMI_DATA8                     0x5080
-MX28_PAD_EMI_D09__EMI_DATA9                     0x5090
-MX28_PAD_EMI_D10__EMI_DATA10                    0x50a0
-MX28_PAD_EMI_D11__EMI_DATA11                    0x50b0
-MX28_PAD_EMI_D12__EMI_DATA12                    0x50c0
-MX28_PAD_EMI_D13__EMI_DATA13                    0x50d0
-MX28_PAD_EMI_D14__EMI_DATA14                    0x50e0
-MX28_PAD_EMI_D15__EMI_DATA15                    0x50f0
-MX28_PAD_EMI_ODT0__EMI_ODT0                     0x5100
-MX28_PAD_EMI_DQM0__EMI_DQM0                     0x5110
-MX28_PAD_EMI_ODT1__EMI_ODT1                     0x5120
-MX28_PAD_EMI_DQM1__EMI_DQM1                     0x5130
-MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK 0x5140
-MX28_PAD_EMI_CLK__EMI_CLK                       0x5150
-MX28_PAD_EMI_DQS0__EMI_DQS0                     0x5160
-MX28_PAD_EMI_DQS1__EMI_DQS1                     0x5170
-MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN             0x51a0
-MX28_PAD_EMI_A00__EMI_ADDR0                     0x6000
-MX28_PAD_EMI_A01__EMI_ADDR1                     0x6010
-MX28_PAD_EMI_A02__EMI_ADDR2                     0x6020
-MX28_PAD_EMI_A03__EMI_ADDR3                     0x6030
-MX28_PAD_EMI_A04__EMI_ADDR4                     0x6040
-MX28_PAD_EMI_A05__EMI_ADDR5                     0x6050
-MX28_PAD_EMI_A06__EMI_ADDR6                     0x6060
-MX28_PAD_EMI_A07__EMI_ADDR7                     0x6070
-MX28_PAD_EMI_A08__EMI_ADDR8                     0x6080
-MX28_PAD_EMI_A09__EMI_ADDR9                     0x6090
-MX28_PAD_EMI_A10__EMI_ADDR10                    0x60a0
-MX28_PAD_EMI_A11__EMI_ADDR11                    0x60b0
-MX28_PAD_EMI_A12__EMI_ADDR12                    0x60c0
-MX28_PAD_EMI_A13__EMI_ADDR13                    0x60d0
-MX28_PAD_EMI_A14__EMI_ADDR14                    0x60e0
-MX28_PAD_EMI_BA0__EMI_BA0                       0x6100
-MX28_PAD_EMI_BA1__EMI_BA1                       0x6110
-MX28_PAD_EMI_BA2__EMI_BA2                       0x6120
-MX28_PAD_EMI_CASN__EMI_CASN                     0x6130
-MX28_PAD_EMI_RASN__EMI_RASN                     0x6140
-MX28_PAD_EMI_WEN__EMI_WEN                       0x6150
-MX28_PAD_EMI_CE0N__EMI_CE0N                     0x6160
-MX28_PAD_EMI_CE1N__EMI_CE1N                     0x6170
-MX28_PAD_EMI_CKE__EMI_CKE                       0x6180
-MX28_PAD_GPMI_D00__SSP1_D0                      0x0001
-MX28_PAD_GPMI_D01__SSP1_D1                      0x0011
-MX28_PAD_GPMI_D02__SSP1_D2                      0x0021
-MX28_PAD_GPMI_D03__SSP1_D3                      0x0031
-MX28_PAD_GPMI_D04__SSP1_D4                      0x0041
-MX28_PAD_GPMI_D05__SSP1_D5                      0x0051
-MX28_PAD_GPMI_D06__SSP1_D6                      0x0061
-MX28_PAD_GPMI_D07__SSP1_D7                      0x0071
-MX28_PAD_GPMI_CE0N__SSP3_D0                     0x0101
-MX28_PAD_GPMI_CE1N__SSP3_D3                     0x0111
-MX28_PAD_GPMI_CE2N__CAN1_TX                     0x0121
-MX28_PAD_GPMI_CE3N__CAN1_RX                     0x0131
-MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT            0x0141
-MX28_PAD_GPMI_RDY1__SSP1_CMD                    0x0151
-MX28_PAD_GPMI_RDY2__CAN0_TX                     0x0161
-MX28_PAD_GPMI_RDY3__CAN0_RX                     0x0171
-MX28_PAD_GPMI_RDN__SSP3_SCK                     0x0181
-MX28_PAD_GPMI_WRN__SSP1_SCK                     0x0191
-MX28_PAD_GPMI_ALE__SSP3_D1                      0x01a1
-MX28_PAD_GPMI_CLE__SSP3_D2                      0x01b1
-MX28_PAD_GPMI_RESETN__SSP3_CMD                  0x01c1
-MX28_PAD_LCD_D03__ETM_DA8                       0x1031
-MX28_PAD_LCD_D04__ETM_DA9                       0x1041
-MX28_PAD_LCD_D08__ETM_DA3                       0x1081
-MX28_PAD_LCD_D09__ETM_DA4                       0x1091
-MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT         0x1141
-MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN          0x1151
-MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT         0x1161
-MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN          0x1171
-MX28_PAD_LCD_RD_E__LCD_VSYNC                    0x1181
-MX28_PAD_LCD_WR_RWN__LCD_HSYNC                  0x1191
-MX28_PAD_LCD_RS__LCD_DOTCLK                     0x11a1
-MX28_PAD_LCD_CS__LCD_ENABLE                     0x11b1
-MX28_PAD_LCD_VSYNC__SAIF1_SDATA0                0x11c1
-MX28_PAD_LCD_HSYNC__SAIF1_SDATA1                0x11d1
-MX28_PAD_LCD_DOTCLK__SAIF1_MCLK                 0x11e1
-MX28_PAD_SSP0_DATA4__SSP2_D0                    0x2041
-MX28_PAD_SSP0_DATA5__SSP2_D3                    0x2051
-MX28_PAD_SSP0_DATA6__SSP2_CMD                   0x2061
-MX28_PAD_SSP0_DATA7__SSP2_SCK                   0x2071
-MX28_PAD_SSP1_SCK__SSP2_D1                      0x20c1
-MX28_PAD_SSP1_CMD__SSP2_D2                      0x20d1
-MX28_PAD_SSP1_DATA0__SSP2_D6                    0x20e1
-MX28_PAD_SSP1_DATA3__SSP2_D7                    0x20f1
-MX28_PAD_SSP2_SCK__AUART2_RX                    0x2101
-MX28_PAD_SSP2_MOSI__AUART2_TX                   0x2111
-MX28_PAD_SSP2_MISO__AUART3_RX                   0x2121
-MX28_PAD_SSP2_SS0__AUART3_TX                    0x2131
-MX28_PAD_SSP2_SS1__SSP2_D1                      0x2141
-MX28_PAD_SSP2_SS2__SSP2_D2                      0x2151
-MX28_PAD_SSP3_SCK__AUART4_TX                    0x2181
-MX28_PAD_SSP3_MOSI__AUART4_RX                   0x2191
-MX28_PAD_SSP3_MISO__AUART4_RTS                  0x21a1
-MX28_PAD_SSP3_SS0__AUART4_CTS                   0x21b1
-MX28_PAD_AUART0_RX__I2C0_SCL                    0x3001
-MX28_PAD_AUART0_TX__I2C0_SDA                    0x3011
-MX28_PAD_AUART0_CTS__AUART4_RX                  0x3021
-MX28_PAD_AUART0_RTS__AUART4_TX                  0x3031
-MX28_PAD_AUART1_RX__SSP2_CARD_DETECT            0x3041
-MX28_PAD_AUART1_TX__SSP3_CARD_DETECT            0x3051
-MX28_PAD_AUART1_CTS__USB0_OVERCURRENT           0x3061
-MX28_PAD_AUART1_RTS__USB0_ID                    0x3071
-MX28_PAD_AUART2_RX__SSP3_D1                     0x3081
-MX28_PAD_AUART2_TX__SSP3_D2                     0x3091
-MX28_PAD_AUART2_CTS__I2C1_SCL                   0x30a1
-MX28_PAD_AUART2_RTS__I2C1_SDA                   0x30b1
-MX28_PAD_AUART3_RX__CAN0_TX                     0x30c1
-MX28_PAD_AUART3_TX__CAN0_RX                     0x30d1
-MX28_PAD_AUART3_CTS__CAN1_TX                    0x30e1
-MX28_PAD_AUART3_RTS__CAN1_RX                    0x30f1
-MX28_PAD_PWM0__I2C1_SCL                         0x3101
-MX28_PAD_PWM1__I2C1_SDA                         0x3111
-MX28_PAD_PWM2__USB0_ID                          0x3121
-MX28_PAD_SAIF0_MCLK__PWM_3                      0x3141
-MX28_PAD_SAIF0_LRCLK__PWM_4                     0x3151
-MX28_PAD_SAIF0_BITCLK__PWM_5                    0x3161
-MX28_PAD_SAIF0_SDATA0__PWM_6                    0x3171
-MX28_PAD_I2C0_SCL__TIMROT_ROTARYA               0x3181
-MX28_PAD_I2C0_SDA__TIMROT_ROTARYB               0x3191
-MX28_PAD_SAIF1_SDATA0__PWM_7                    0x31a1
-MX28_PAD_LCD_RESET__LCD_VSYNC                   0x31e1
-MX28_PAD_ENET0_MDC__GPMI_CE4N                   0x4001
-MX28_PAD_ENET0_MDIO__GPMI_CE5N                  0x4011
-MX28_PAD_ENET0_RX_EN__GPMI_CE6N                 0x4021
-MX28_PAD_ENET0_RXD0__GPMI_CE7N                  0x4031
-MX28_PAD_ENET0_RXD1__GPMI_READY4                0x4041
-MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER            0x4051
-MX28_PAD_ENET0_TX_EN__GPMI_READY5               0x4061
-MX28_PAD_ENET0_TXD0__GPMI_READY6                0x4071
-MX28_PAD_ENET0_TXD1__GPMI_READY7                0x4081
-MX28_PAD_ENET0_RXD2__ENET1_RXD0                 0x4091
-MX28_PAD_ENET0_RXD3__ENET1_RXD1                 0x40a1
-MX28_PAD_ENET0_TXD2__ENET1_TXD0                 0x40b1
-MX28_PAD_ENET0_TXD3__ENET1_TXD1                 0x40c1
-MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER              0x40d1
-MX28_PAD_ENET0_COL__ENET1_TX_EN                 0x40e1
-MX28_PAD_ENET0_CRS__ENET1_RX_EN                 0x40f1
-MX28_PAD_GPMI_CE2N__ENET0_RX_ER                 0x0122
-MX28_PAD_GPMI_CE3N__SAIF1_MCLK                  0x0132
-MX28_PAD_GPMI_RDY0__USB0_ID                     0x0142
-MX28_PAD_GPMI_RDY2__ENET0_TX_ER                 0x0162
-MX28_PAD_GPMI_RDY3__HSADC_TRIGGER               0x0172
-MX28_PAD_GPMI_ALE__SSP3_D4                      0x01a2
-MX28_PAD_GPMI_CLE__SSP3_D5                      0x01b2
-MX28_PAD_LCD_D00__ETM_DA0                       0x1002
-MX28_PAD_LCD_D01__ETM_DA1                       0x1012
-MX28_PAD_LCD_D02__ETM_DA2                       0x1022
-MX28_PAD_LCD_D03__ETM_DA3                       0x1032
-MX28_PAD_LCD_D04__ETM_DA4                       0x1042
-MX28_PAD_LCD_D05__ETM_DA5                       0x1052
-MX28_PAD_LCD_D06__ETM_DA6                       0x1062
-MX28_PAD_LCD_D07__ETM_DA7                       0x1072
-MX28_PAD_LCD_D08__ETM_DA8                       0x1082
-MX28_PAD_LCD_D09__ETM_DA9                       0x1092
-MX28_PAD_LCD_D10__ETM_DA10                      0x10a2
-MX28_PAD_LCD_D11__ETM_DA11                      0x10b2
-MX28_PAD_LCD_D12__ETM_DA12                      0x10c2
-MX28_PAD_LCD_D13__ETM_DA13                      0x10d2
-MX28_PAD_LCD_D14__ETM_DA14                      0x10e2
-MX28_PAD_LCD_D15__ETM_DA15                      0x10f2
-MX28_PAD_LCD_D16__ETM_DA7                       0x1102
-MX28_PAD_LCD_D17__ETM_DA6                       0x1112
-MX28_PAD_LCD_D18__ETM_DA5                       0x1122
-MX28_PAD_LCD_D19__ETM_DA4                       0x1132
-MX28_PAD_LCD_D20__ETM_DA3                       0x1142
-MX28_PAD_LCD_D21__ETM_DA2                       0x1152
-MX28_PAD_LCD_D22__ETM_DA1                       0x1162
-MX28_PAD_LCD_D23__ETM_DA0                       0x1172
-MX28_PAD_LCD_RD_E__ETM_TCTL                     0x1182
-MX28_PAD_LCD_WR_RWN__ETM_TCLK                   0x1192
-MX28_PAD_LCD_HSYNC__ETM_TCTL                    0x11d2
-MX28_PAD_LCD_DOTCLK__ETM_TCLK                   0x11e2
-MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT        0x20c2
-MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN         0x20d2
-MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT      0x20e2
-MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN       0x20f2
-MX28_PAD_SSP2_SCK__SAIF0_SDATA1                 0x2102
-MX28_PAD_SSP2_MOSI__SAIF0_SDATA2                0x2112
-MX28_PAD_SSP2_MISO__SAIF1_SDATA1                0x2122
-MX28_PAD_SSP2_SS0__SAIF1_SDATA2                 0x2132
-MX28_PAD_SSP2_SS1__USB1_OVERCURRENT             0x2142
-MX28_PAD_SSP2_SS2__USB0_OVERCURRENT             0x2152
-MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT        0x2182
-MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN        0x2192
-MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT       0x21a2
-MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN         0x21b2
-MX28_PAD_AUART0_RX__DUART_CTS                   0x3002
-MX28_PAD_AUART0_TX__DUART_RTS                   0x3012
-MX28_PAD_AUART0_CTS__DUART_RX                   0x3022
-MX28_PAD_AUART0_RTS__DUART_TX                   0x3032
-MX28_PAD_AUART1_RX__PWM_0                       0x3042
-MX28_PAD_AUART1_TX__PWM_1                       0x3052
-MX28_PAD_AUART1_CTS__TIMROT_ROTARYA             0x3062
-MX28_PAD_AUART1_RTS__TIMROT_ROTARYB             0x3072
-MX28_PAD_AUART2_RX__SSP3_D4                     0x3082
-MX28_PAD_AUART2_TX__SSP3_D5                     0x3092
-MX28_PAD_AUART2_CTS__SAIF1_BITCLK               0x30a2
-MX28_PAD_AUART2_RTS__SAIF1_LRCLK                0x30b2
-MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT       0x30c2
-MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN        0x30d2
-MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT      0x30e2
-MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN       0x30f2
-MX28_PAD_PWM0__DUART_RX                         0x3102
-MX28_PAD_PWM1__DUART_TX                         0x3112
-MX28_PAD_PWM2__USB1_OVERCURRENT                 0x3122
-MX28_PAD_SAIF0_MCLK__AUART4_CTS                 0x3142
-MX28_PAD_SAIF0_LRCLK__AUART4_RTS                0x3152
-MX28_PAD_SAIF0_BITCLK__AUART4_RX                0x3162
-MX28_PAD_SAIF0_SDATA0__AUART4_TX                0x3172
-MX28_PAD_I2C0_SCL__DUART_RX                     0x3182
-MX28_PAD_I2C0_SDA__DUART_TX                     0x3192
-MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1             0x31a2
-MX28_PAD_SPDIF__ENET1_RX_ER                     0x31b2
-MX28_PAD_ENET0_MDC__SAIF0_SDATA1                0x4002
-MX28_PAD_ENET0_MDIO__SAIF0_SDATA2               0x4012
-MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1              0x4022
-MX28_PAD_ENET0_RXD0__SAIF1_SDATA2               0x4032
-MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT    0x4052
-MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT      0x4092
-MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN       0x40a2
-MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT      0x40b2
-MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN       0x40c2
-MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN     0x40d2
-MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT       0x40e2
-MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN        0x40f2
-MX28_PAD_GPMI_D00__GPIO_0_0                     0x0003
-MX28_PAD_GPMI_D01__GPIO_0_1                     0x0013
-MX28_PAD_GPMI_D02__GPIO_0_2                     0x0023
-MX28_PAD_GPMI_D03__GPIO_0_3                     0x0033
-MX28_PAD_GPMI_D04__GPIO_0_4                     0x0043
-MX28_PAD_GPMI_D05__GPIO_0_5                     0x0053
-MX28_PAD_GPMI_D06__GPIO_0_6                     0x0063
-MX28_PAD_GPMI_D07__GPIO_0_7                     0x0073
-MX28_PAD_GPMI_CE0N__GPIO_0_16                   0x0103
-MX28_PAD_GPMI_CE1N__GPIO_0_17                   0x0113
-MX28_PAD_GPMI_CE2N__GPIO_0_18                   0x0123
-MX28_PAD_GPMI_CE3N__GPIO_0_19                   0x0133
-MX28_PAD_GPMI_RDY0__GPIO_0_20                   0x0143
-MX28_PAD_GPMI_RDY1__GPIO_0_21                   0x0153
-MX28_PAD_GPMI_RDY2__GPIO_0_22                   0x0163
-MX28_PAD_GPMI_RDY3__GPIO_0_23                   0x0173
-MX28_PAD_GPMI_RDN__GPIO_0_24                    0x0183
-MX28_PAD_GPMI_WRN__GPIO_0_25                    0x0193
-MX28_PAD_GPMI_ALE__GPIO_0_26                    0x01a3
-MX28_PAD_GPMI_CLE__GPIO_0_27                    0x01b3
-MX28_PAD_GPMI_RESETN__GPIO_0_28                 0x01c3
-MX28_PAD_LCD_D00__GPIO_1_0                      0x1003
-MX28_PAD_LCD_D01__GPIO_1_1                      0x1013
-MX28_PAD_LCD_D02__GPIO_1_2                      0x1023
-MX28_PAD_LCD_D03__GPIO_1_3                      0x1033
-MX28_PAD_LCD_D04__GPIO_1_4                      0x1043
-MX28_PAD_LCD_D05__GPIO_1_5                      0x1053
-MX28_PAD_LCD_D06__GPIO_1_6                      0x1063
-MX28_PAD_LCD_D07__GPIO_1_7                      0x1073
-MX28_PAD_LCD_D08__GPIO_1_8                      0x1083
-MX28_PAD_LCD_D09__GPIO_1_9                      0x1093
-MX28_PAD_LCD_D10__GPIO_1_10                     0x10a3
-MX28_PAD_LCD_D11__GPIO_1_11                     0x10b3
-MX28_PAD_LCD_D12__GPIO_1_12                     0x10c3
-MX28_PAD_LCD_D13__GPIO_1_13                     0x10d3
-MX28_PAD_LCD_D14__GPIO_1_14                     0x10e3
-MX28_PAD_LCD_D15__GPIO_1_15                     0x10f3
-MX28_PAD_LCD_D16__GPIO_1_16                     0x1103
-MX28_PAD_LCD_D17__GPIO_1_17                     0x1113
-MX28_PAD_LCD_D18__GPIO_1_18                     0x1123
-MX28_PAD_LCD_D19__GPIO_1_19                     0x1133
-MX28_PAD_LCD_D20__GPIO_1_20                     0x1143
-MX28_PAD_LCD_D21__GPIO_1_21                     0x1153
-MX28_PAD_LCD_D22__GPIO_1_22                     0x1163
-MX28_PAD_LCD_D23__GPIO_1_23                     0x1173
-MX28_PAD_LCD_RD_E__GPIO_1_24                    0x1183
-MX28_PAD_LCD_WR_RWN__GPIO_1_25                  0x1193
-MX28_PAD_LCD_RS__GPIO_1_26                      0x11a3
-MX28_PAD_LCD_CS__GPIO_1_27                      0x11b3
-MX28_PAD_LCD_VSYNC__GPIO_1_28                   0x11c3
-MX28_PAD_LCD_HSYNC__GPIO_1_29                   0x11d3
-MX28_PAD_LCD_DOTCLK__GPIO_1_30                  0x11e3
-MX28_PAD_LCD_ENABLE__GPIO_1_31                  0x11f3
-MX28_PAD_SSP0_DATA0__GPIO_2_0                   0x2003
-MX28_PAD_SSP0_DATA1__GPIO_2_1                   0x2013
-MX28_PAD_SSP0_DATA2__GPIO_2_2                   0x2023
-MX28_PAD_SSP0_DATA3__GPIO_2_3                   0x2033
-MX28_PAD_SSP0_DATA4__GPIO_2_4                   0x2043
-MX28_PAD_SSP0_DATA5__GPIO_2_5                   0x2053
-MX28_PAD_SSP0_DATA6__GPIO_2_6                   0x2063
-MX28_PAD_SSP0_DATA7__GPIO_2_7                   0x2073
-MX28_PAD_SSP0_CMD__GPIO_2_8                     0x2083
-MX28_PAD_SSP0_DETECT__GPIO_2_9                  0x2093
-MX28_PAD_SSP0_SCK__GPIO_2_10                    0x20a3
-MX28_PAD_SSP1_SCK__GPIO_2_12                    0x20c3
-MX28_PAD_SSP1_CMD__GPIO_2_13                    0x20d3
-MX28_PAD_SSP1_DATA0__GPIO_2_14                  0x20e3
-MX28_PAD_SSP1_DATA3__GPIO_2_15                  0x20f3
-MX28_PAD_SSP2_SCK__GPIO_2_16                    0x2103
-MX28_PAD_SSP2_MOSI__GPIO_2_17                   0x2113
-MX28_PAD_SSP2_MISO__GPIO_2_18                   0x2123
-MX28_PAD_SSP2_SS0__GPIO_2_19                    0x2133
-MX28_PAD_SSP2_SS1__GPIO_2_20                    0x2143
-MX28_PAD_SSP2_SS2__GPIO_2_21                    0x2153
-MX28_PAD_SSP3_SCK__GPIO_2_24                    0x2183
-MX28_PAD_SSP3_MOSI__GPIO_2_25                   0x2193
-MX28_PAD_SSP3_MISO__GPIO_2_26                   0x21a3
-MX28_PAD_SSP3_SS0__GPIO_2_27                    0x21b3
-MX28_PAD_AUART0_RX__GPIO_3_0                    0x3003
-MX28_PAD_AUART0_TX__GPIO_3_1                    0x3013
-MX28_PAD_AUART0_CTS__GPIO_3_2                   0x3023
-MX28_PAD_AUART0_RTS__GPIO_3_3                   0x3033
-MX28_PAD_AUART1_RX__GPIO_3_4                    0x3043
-MX28_PAD_AUART1_TX__GPIO_3_5                    0x3053
-MX28_PAD_AUART1_CTS__GPIO_3_6                   0x3063
-MX28_PAD_AUART1_RTS__GPIO_3_7                   0x3073
-MX28_PAD_AUART2_RX__GPIO_3_8                    0x3083
-MX28_PAD_AUART2_TX__GPIO_3_9                    0x3093
-MX28_PAD_AUART2_CTS__GPIO_3_10                  0x30a3
-MX28_PAD_AUART2_RTS__GPIO_3_11                  0x30b3
-MX28_PAD_AUART3_RX__GPIO_3_12                   0x30c3
-MX28_PAD_AUART3_TX__GPIO_3_13                   0x30d3
-MX28_PAD_AUART3_CTS__GPIO_3_14                  0x30e3
-MX28_PAD_AUART3_RTS__GPIO_3_15                  0x30f3
-MX28_PAD_PWM0__GPIO_3_16                        0x3103
-MX28_PAD_PWM1__GPIO_3_17                        0x3113
-MX28_PAD_PWM2__GPIO_3_18                        0x3123
-MX28_PAD_SAIF0_MCLK__GPIO_3_20                  0x3143
-MX28_PAD_SAIF0_LRCLK__GPIO_3_21                 0x3153
-MX28_PAD_SAIF0_BITCLK__GPIO_3_22                0x3163
-MX28_PAD_SAIF0_SDATA0__GPIO_3_23                0x3173
-MX28_PAD_I2C0_SCL__GPIO_3_24                    0x3183
-MX28_PAD_I2C0_SDA__GPIO_3_25                    0x3193
-MX28_PAD_SAIF1_SDATA0__GPIO_3_26                0x31a3
-MX28_PAD_SPDIF__GPIO_3_27                       0x31b3
-MX28_PAD_PWM3__GPIO_3_28                        0x31c3
-MX28_PAD_PWM4__GPIO_3_29                        0x31d3
-MX28_PAD_LCD_RESET__GPIO_3_30                   0x31e3
-MX28_PAD_ENET0_MDC__GPIO_4_0                    0x4003
-MX28_PAD_ENET0_MDIO__GPIO_4_1                   0x4013
-MX28_PAD_ENET0_RX_EN__GPIO_4_2                  0x4023
-MX28_PAD_ENET0_RXD0__GPIO_4_3                   0x4033
-MX28_PAD_ENET0_RXD1__GPIO_4_4                   0x4043
-MX28_PAD_ENET0_TX_CLK__GPIO_4_5                 0x4053
-MX28_PAD_ENET0_TX_EN__GPIO_4_6                  0x4063
-MX28_PAD_ENET0_TXD0__GPIO_4_7                   0x4073
-MX28_PAD_ENET0_TXD1__GPIO_4_8                   0x4083
-MX28_PAD_ENET0_RXD2__GPIO_4_9                   0x4093
-MX28_PAD_ENET0_RXD3__GPIO_4_10                  0x40a3
-MX28_PAD_ENET0_TXD2__GPIO_4_11                  0x40b3
-MX28_PAD_ENET0_TXD3__GPIO_4_12                  0x40c3
-MX28_PAD_ENET0_RX_CLK__GPIO_4_13                0x40d3
-MX28_PAD_ENET0_COL__GPIO_4_14                   0x40e3
-MX28_PAD_ENET0_CRS__GPIO_4_15                   0x40f3
-MX28_PAD_ENET_CLK__GPIO_4_16                    0x4103
-MX28_PAD_JTAG_RTCK__GPIO_4_20                   0x4143
-
-Valid values for i.MX23 pinmux-id:
-
-pinmux                                          id
-------                                          --
-MX23_PAD_GPMI_D00__GPMI_D00                     0x0000
-MX23_PAD_GPMI_D01__GPMI_D01                     0x0010
-MX23_PAD_GPMI_D02__GPMI_D02                     0x0020
-MX23_PAD_GPMI_D03__GPMI_D03                     0x0030
-MX23_PAD_GPMI_D04__GPMI_D04                     0x0040
-MX23_PAD_GPMI_D05__GPMI_D05                     0x0050
-MX23_PAD_GPMI_D06__GPMI_D06                     0x0060
-MX23_PAD_GPMI_D07__GPMI_D07                     0x0070
-MX23_PAD_GPMI_D08__GPMI_D08                     0x0080
-MX23_PAD_GPMI_D09__GPMI_D09                     0x0090
-MX23_PAD_GPMI_D10__GPMI_D10                     0x00a0
-MX23_PAD_GPMI_D11__GPMI_D11                     0x00b0
-MX23_PAD_GPMI_D12__GPMI_D12                     0x00c0
-MX23_PAD_GPMI_D13__GPMI_D13                     0x00d0
-MX23_PAD_GPMI_D14__GPMI_D14                     0x00e0
-MX23_PAD_GPMI_D15__GPMI_D15                     0x00f0
-MX23_PAD_GPMI_CLE__GPMI_CLE                     0x0100
-MX23_PAD_GPMI_ALE__GPMI_ALE                     0x0110
-MX23_PAD_GPMI_CE2N__GPMI_CE2N                   0x0120
-MX23_PAD_GPMI_RDY0__GPMI_RDY0                   0x0130
-MX23_PAD_GPMI_RDY1__GPMI_RDY1                   0x0140
-MX23_PAD_GPMI_RDY2__GPMI_RDY2                   0x0150
-MX23_PAD_GPMI_RDY3__GPMI_RDY3                   0x0160
-MX23_PAD_GPMI_WPN__GPMI_WPN                     0x0170
-MX23_PAD_GPMI_WRN__GPMI_WRN                     0x0180
-MX23_PAD_GPMI_RDN__GPMI_RDN                     0x0190
-MX23_PAD_AUART1_CTS__AUART1_CTS                 0x01a0
-MX23_PAD_AUART1_RTS__AUART1_RTS                 0x01b0
-MX23_PAD_AUART1_RX__AUART1_RX                   0x01c0
-MX23_PAD_AUART1_TX__AUART1_TX                   0x01d0
-MX23_PAD_I2C_SCL__I2C_SCL                       0x01e0
-MX23_PAD_I2C_SDA__I2C_SDA                       0x01f0
-MX23_PAD_LCD_D00__LCD_D00                       0x1000
-MX23_PAD_LCD_D01__LCD_D01                       0x1010
-MX23_PAD_LCD_D02__LCD_D02                       0x1020
-MX23_PAD_LCD_D03__LCD_D03                       0x1030
-MX23_PAD_LCD_D04__LCD_D04                       0x1040
-MX23_PAD_LCD_D05__LCD_D05                       0x1050
-MX23_PAD_LCD_D06__LCD_D06                       0x1060
-MX23_PAD_LCD_D07__LCD_D07                       0x1070
-MX23_PAD_LCD_D08__LCD_D08                       0x1080
-MX23_PAD_LCD_D09__LCD_D09                       0x1090
-MX23_PAD_LCD_D10__LCD_D10                       0x10a0
-MX23_PAD_LCD_D11__LCD_D11                       0x10b0
-MX23_PAD_LCD_D12__LCD_D12                       0x10c0
-MX23_PAD_LCD_D13__LCD_D13                       0x10d0
-MX23_PAD_LCD_D14__LCD_D14                       0x10e0
-MX23_PAD_LCD_D15__LCD_D15                       0x10f0
-MX23_PAD_LCD_D16__LCD_D16                       0x1100
-MX23_PAD_LCD_D17__LCD_D17                       0x1110
-MX23_PAD_LCD_RESET__LCD_RESET                   0x1120
-MX23_PAD_LCD_RS__LCD_RS                         0x1130
-MX23_PAD_LCD_WR__LCD_WR                         0x1140
-MX23_PAD_LCD_CS__LCD_CS                         0x1150
-MX23_PAD_LCD_DOTCK__LCD_DOTCK                   0x1160
-MX23_PAD_LCD_ENABLE__LCD_ENABLE                 0x1170
-MX23_PAD_LCD_HSYNC__LCD_HSYNC                   0x1180
-MX23_PAD_LCD_VSYNC__LCD_VSYNC                   0x1190
-MX23_PAD_PWM0__PWM0                             0x11a0
-MX23_PAD_PWM1__PWM1                             0x11b0
-MX23_PAD_PWM2__PWM2                             0x11c0
-MX23_PAD_PWM3__PWM3                             0x11d0
-MX23_PAD_PWM4__PWM4                             0x11e0
-MX23_PAD_SSP1_CMD__SSP1_CMD                     0x2000
-MX23_PAD_SSP1_DETECT__SSP1_DETECT               0x2010
-MX23_PAD_SSP1_DATA0__SSP1_DATA0                 0x2020
-MX23_PAD_SSP1_DATA1__SSP1_DATA1                 0x2030
-MX23_PAD_SSP1_DATA2__SSP1_DATA2                 0x2040
-MX23_PAD_SSP1_DATA3__SSP1_DATA3                 0x2050
-MX23_PAD_SSP1_SCK__SSP1_SCK                     0x2060
-MX23_PAD_ROTARYA__ROTARYA                       0x2070
-MX23_PAD_ROTARYB__ROTARYB                       0x2080
-MX23_PAD_EMI_A00__EMI_A00                       0x2090
-MX23_PAD_EMI_A01__EMI_A01                       0x20a0
-MX23_PAD_EMI_A02__EMI_A02                       0x20b0
-MX23_PAD_EMI_A03__EMI_A03                       0x20c0
-MX23_PAD_EMI_A04__EMI_A04                       0x20d0
-MX23_PAD_EMI_A05__EMI_A05                       0x20e0
-MX23_PAD_EMI_A06__EMI_A06                       0x20f0
-MX23_PAD_EMI_A07__EMI_A07                       0x2100
-MX23_PAD_EMI_A08__EMI_A08                       0x2110
-MX23_PAD_EMI_A09__EMI_A09                       0x2120
-MX23_PAD_EMI_A10__EMI_A10                       0x2130
-MX23_PAD_EMI_A11__EMI_A11                       0x2140
-MX23_PAD_EMI_A12__EMI_A12                       0x2150
-MX23_PAD_EMI_BA0__EMI_BA0                       0x2160
-MX23_PAD_EMI_BA1__EMI_BA1                       0x2170
-MX23_PAD_EMI_CASN__EMI_CASN                     0x2180
-MX23_PAD_EMI_CE0N__EMI_CE0N                     0x2190
-MX23_PAD_EMI_CE1N__EMI_CE1N                     0x21a0
-MX23_PAD_GPMI_CE1N__GPMI_CE1N                   0x21b0
-MX23_PAD_GPMI_CE0N__GPMI_CE0N                   0x21c0
-MX23_PAD_EMI_CKE__EMI_CKE                       0x21d0
-MX23_PAD_EMI_RASN__EMI_RASN                     0x21e0
-MX23_PAD_EMI_WEN__EMI_WEN                       0x21f0
-MX23_PAD_EMI_D00__EMI_D00                       0x3000
-MX23_PAD_EMI_D01__EMI_D01                       0x3010
-MX23_PAD_EMI_D02__EMI_D02                       0x3020
-MX23_PAD_EMI_D03__EMI_D03                       0x3030
-MX23_PAD_EMI_D04__EMI_D04                       0x3040
-MX23_PAD_EMI_D05__EMI_D05                       0x3050
-MX23_PAD_EMI_D06__EMI_D06                       0x3060
-MX23_PAD_EMI_D07__EMI_D07                       0x3070
-MX23_PAD_EMI_D08__EMI_D08                       0x3080
-MX23_PAD_EMI_D09__EMI_D09                       0x3090
-MX23_PAD_EMI_D10__EMI_D10                       0x30a0
-MX23_PAD_EMI_D11__EMI_D11                       0x30b0
-MX23_PAD_EMI_D12__EMI_D12                       0x30c0
-MX23_PAD_EMI_D13__EMI_D13                       0x30d0
-MX23_PAD_EMI_D14__EMI_D14                       0x30e0
-MX23_PAD_EMI_D15__EMI_D15                       0x30f0
-MX23_PAD_EMI_DQM0__EMI_DQM0                     0x3100
-MX23_PAD_EMI_DQM1__EMI_DQM1                     0x3110
-MX23_PAD_EMI_DQS0__EMI_DQS0                     0x3120
-MX23_PAD_EMI_DQS1__EMI_DQS1                     0x3130
-MX23_PAD_EMI_CLK__EMI_CLK                       0x3140
-MX23_PAD_EMI_CLKN__EMI_CLKN                     0x3150
-MX23_PAD_GPMI_D00__LCD_D8                       0x0001
-MX23_PAD_GPMI_D01__LCD_D9                       0x0011
-MX23_PAD_GPMI_D02__LCD_D10                      0x0021
-MX23_PAD_GPMI_D03__LCD_D11                      0x0031
-MX23_PAD_GPMI_D04__LCD_D12                      0x0041
-MX23_PAD_GPMI_D05__LCD_D13                      0x0051
-MX23_PAD_GPMI_D06__LCD_D14                      0x0061
-MX23_PAD_GPMI_D07__LCD_D15                      0x0071
-MX23_PAD_GPMI_D08__LCD_D18                      0x0081
-MX23_PAD_GPMI_D09__LCD_D19                      0x0091
-MX23_PAD_GPMI_D10__LCD_D20                      0x00a1
-MX23_PAD_GPMI_D11__LCD_D21                      0x00b1
-MX23_PAD_GPMI_D12__LCD_D22                      0x00c1
-MX23_PAD_GPMI_D13__LCD_D23                      0x00d1
-MX23_PAD_GPMI_D14__AUART2_RX                    0x00e1
-MX23_PAD_GPMI_D15__AUART2_TX                    0x00f1
-MX23_PAD_GPMI_CLE__LCD_D16                      0x0101
-MX23_PAD_GPMI_ALE__LCD_D17                      0x0111
-MX23_PAD_GPMI_CE2N__ATA_A2                      0x0121
-MX23_PAD_AUART1_RTS__IR_CLK                     0x01b1
-MX23_PAD_AUART1_RX__IR_RX                       0x01c1
-MX23_PAD_AUART1_TX__IR_TX                       0x01d1
-MX23_PAD_I2C_SCL__GPMI_RDY2                     0x01e1
-MX23_PAD_I2C_SDA__GPMI_CE2N                     0x01f1
-MX23_PAD_LCD_D00__ETM_DA8                       0x1001
-MX23_PAD_LCD_D01__ETM_DA9                       0x1011
-MX23_PAD_LCD_D02__ETM_DA10                      0x1021
-MX23_PAD_LCD_D03__ETM_DA11                      0x1031
-MX23_PAD_LCD_D04__ETM_DA12                      0x1041
-MX23_PAD_LCD_D05__ETM_DA13                      0x1051
-MX23_PAD_LCD_D06__ETM_DA14                      0x1061
-MX23_PAD_LCD_D07__ETM_DA15                      0x1071
-MX23_PAD_LCD_D08__ETM_DA0                       0x1081
-MX23_PAD_LCD_D09__ETM_DA1                       0x1091
-MX23_PAD_LCD_D10__ETM_DA2                       0x10a1
-MX23_PAD_LCD_D11__ETM_DA3                       0x10b1
-MX23_PAD_LCD_D12__ETM_DA4                       0x10c1
-MX23_PAD_LCD_D13__ETM_DA5                       0x10d1
-MX23_PAD_LCD_D14__ETM_DA6                       0x10e1
-MX23_PAD_LCD_D15__ETM_DA7                       0x10f1
-MX23_PAD_LCD_RESET__ETM_TCTL                    0x1121
-MX23_PAD_LCD_RS__ETM_TCLK                       0x1131
-MX23_PAD_LCD_DOTCK__GPMI_RDY3                   0x1161
-MX23_PAD_LCD_ENABLE__I2C_SCL                    0x1171
-MX23_PAD_LCD_HSYNC__I2C_SDA                     0x1181
-MX23_PAD_LCD_VSYNC__LCD_BUSY                    0x1191
-MX23_PAD_PWM0__ROTARYA                          0x11a1
-MX23_PAD_PWM1__ROTARYB                          0x11b1
-MX23_PAD_PWM2__GPMI_RDY3                        0x11c1
-MX23_PAD_PWM3__ETM_TCTL                         0x11d1
-MX23_PAD_PWM4__ETM_TCLK                         0x11e1
-MX23_PAD_SSP1_DETECT__GPMI_CE3N                 0x2011
-MX23_PAD_SSP1_DATA1__I2C_SCL                    0x2031
-MX23_PAD_SSP1_DATA2__I2C_SDA                    0x2041
-MX23_PAD_ROTARYA__AUART2_RTS                    0x2071
-MX23_PAD_ROTARYB__AUART2_CTS                    0x2081
-MX23_PAD_GPMI_D00__SSP2_DATA0                   0x0002
-MX23_PAD_GPMI_D01__SSP2_DATA1                   0x0012
-MX23_PAD_GPMI_D02__SSP2_DATA2                   0x0022
-MX23_PAD_GPMI_D03__SSP2_DATA3                   0x0032
-MX23_PAD_GPMI_D04__SSP2_DATA4                   0x0042
-MX23_PAD_GPMI_D05__SSP2_DATA5                   0x0052
-MX23_PAD_GPMI_D06__SSP2_DATA6                   0x0062
-MX23_PAD_GPMI_D07__SSP2_DATA7                   0x0072
-MX23_PAD_GPMI_D08__SSP1_DATA4                   0x0082
-MX23_PAD_GPMI_D09__SSP1_DATA5                   0x0092
-MX23_PAD_GPMI_D10__SSP1_DATA6                   0x00a2
-MX23_PAD_GPMI_D11__SSP1_DATA7                   0x00b2
-MX23_PAD_GPMI_D15__GPMI_CE3N                    0x00f2
-MX23_PAD_GPMI_RDY0__SSP2_DETECT                 0x0132
-MX23_PAD_GPMI_RDY1__SSP2_CMD                    0x0142
-MX23_PAD_GPMI_WRN__SSP2_SCK                     0x0182
-MX23_PAD_AUART1_CTS__SSP1_DATA4                 0x01a2
-MX23_PAD_AUART1_RTS__SSP1_DATA5                 0x01b2
-MX23_PAD_AUART1_RX__SSP1_DATA6                  0x01c2
-MX23_PAD_AUART1_TX__SSP1_DATA7                  0x01d2
-MX23_PAD_I2C_SCL__AUART1_TX                     0x01e2
-MX23_PAD_I2C_SDA__AUART1_RX                     0x01f2
-MX23_PAD_LCD_D08__SAIF2_SDATA0                  0x1082
-MX23_PAD_LCD_D09__SAIF1_SDATA0                  0x1092
-MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK              0x10a2
-MX23_PAD_LCD_D11__SAIF_LRCLK                    0x10b2
-MX23_PAD_LCD_D12__SAIF2_SDATA1                  0x10c2
-MX23_PAD_LCD_D13__SAIF2_SDATA2                  0x10d2
-MX23_PAD_LCD_D14__SAIF1_SDATA2                  0x10e2
-MX23_PAD_LCD_D15__SAIF1_SDATA1                  0x10f2
-MX23_PAD_LCD_D16__SAIF_ALT_BITCLK               0x1102
-MX23_PAD_LCD_RESET__GPMI_CE3N                   0x1122
-MX23_PAD_PWM0__DUART_RX                         0x11a2
-MX23_PAD_PWM1__DUART_TX                         0x11b2
-MX23_PAD_PWM3__AUART1_CTS                       0x11d2
-MX23_PAD_PWM4__AUART1_RTS                       0x11e2
-MX23_PAD_SSP1_CMD__JTAG_TDO                     0x2002
-MX23_PAD_SSP1_DETECT__USB_OTG_ID                0x2012
-MX23_PAD_SSP1_DATA0__JTAG_TDI                   0x2022
-MX23_PAD_SSP1_DATA1__JTAG_TCLK                  0x2032
-MX23_PAD_SSP1_DATA2__JTAG_RTCK                  0x2042
-MX23_PAD_SSP1_DATA3__JTAG_TMS                   0x2052
-MX23_PAD_SSP1_SCK__JTAG_TRST                    0x2062
-MX23_PAD_ROTARYA__SPDIF                         0x2072
-MX23_PAD_ROTARYB__GPMI_CE3N                     0x2082
-MX23_PAD_GPMI_D00__GPIO_0_0                     0x0003
-MX23_PAD_GPMI_D01__GPIO_0_1                     0x0013
-MX23_PAD_GPMI_D02__GPIO_0_2                     0x0023
-MX23_PAD_GPMI_D03__GPIO_0_3                     0x0033
-MX23_PAD_GPMI_D04__GPIO_0_4                     0x0043
-MX23_PAD_GPMI_D05__GPIO_0_5                     0x0053
-MX23_PAD_GPMI_D06__GPIO_0_6                     0x0063
-MX23_PAD_GPMI_D07__GPIO_0_7                     0x0073
-MX23_PAD_GPMI_D08__GPIO_0_8                     0x0083
-MX23_PAD_GPMI_D09__GPIO_0_9                     0x0093
-MX23_PAD_GPMI_D10__GPIO_0_10                    0x00a3
-MX23_PAD_GPMI_D11__GPIO_0_11                    0x00b3
-MX23_PAD_GPMI_D12__GPIO_0_12                    0x00c3
-MX23_PAD_GPMI_D13__GPIO_0_13                    0x00d3
-MX23_PAD_GPMI_D14__GPIO_0_14                    0x00e3
-MX23_PAD_GPMI_D15__GPIO_0_15                    0x00f3
-MX23_PAD_GPMI_CLE__GPIO_0_16                    0x0103
-MX23_PAD_GPMI_ALE__GPIO_0_17                    0x0113
-MX23_PAD_GPMI_CE2N__GPIO_0_18                   0x0123
-MX23_PAD_GPMI_RDY0__GPIO_0_19                   0x0133
-MX23_PAD_GPMI_RDY1__GPIO_0_20                   0x0143
-MX23_PAD_GPMI_RDY2__GPIO_0_21                   0x0153
-MX23_PAD_GPMI_RDY3__GPIO_0_22                   0x0163
-MX23_PAD_GPMI_WPN__GPIO_0_23                    0x0173
-MX23_PAD_GPMI_WRN__GPIO_0_24                    0x0183
-MX23_PAD_GPMI_RDN__GPIO_0_25                    0x0193
-MX23_PAD_AUART1_CTS__GPIO_0_26                  0x01a3
-MX23_PAD_AUART1_RTS__GPIO_0_27                  0x01b3
-MX23_PAD_AUART1_RX__GPIO_0_28                   0x01c3
-MX23_PAD_AUART1_TX__GPIO_0_29                   0x01d3
-MX23_PAD_I2C_SCL__GPIO_0_30                     0x01e3
-MX23_PAD_I2C_SDA__GPIO_0_31                     0x01f3
-MX23_PAD_LCD_D00__GPIO_1_0                      0x1003
-MX23_PAD_LCD_D01__GPIO_1_1                      0x1013
-MX23_PAD_LCD_D02__GPIO_1_2                      0x1023
-MX23_PAD_LCD_D03__GPIO_1_3                      0x1033
-MX23_PAD_LCD_D04__GPIO_1_4                      0x1043
-MX23_PAD_LCD_D05__GPIO_1_5                      0x1053
-MX23_PAD_LCD_D06__GPIO_1_6                      0x1063
-MX23_PAD_LCD_D07__GPIO_1_7                      0x1073
-MX23_PAD_LCD_D08__GPIO_1_8                      0x1083
-MX23_PAD_LCD_D09__GPIO_1_9                      0x1093
-MX23_PAD_LCD_D10__GPIO_1_10                     0x10a3
-MX23_PAD_LCD_D11__GPIO_1_11                     0x10b3
-MX23_PAD_LCD_D12__GPIO_1_12                     0x10c3
-MX23_PAD_LCD_D13__GPIO_1_13                     0x10d3
-MX23_PAD_LCD_D14__GPIO_1_14                     0x10e3
-MX23_PAD_LCD_D15__GPIO_1_15                     0x10f3
-MX23_PAD_LCD_D16__GPIO_1_16                     0x1103
-MX23_PAD_LCD_D17__GPIO_1_17                     0x1113
-MX23_PAD_LCD_RESET__GPIO_1_18                   0x1123
-MX23_PAD_LCD_RS__GPIO_1_19                      0x1133
-MX23_PAD_LCD_WR__GPIO_1_20                      0x1143
-MX23_PAD_LCD_CS__GPIO_1_21                      0x1153
-MX23_PAD_LCD_DOTCK__GPIO_1_22                   0x1163
-MX23_PAD_LCD_ENABLE__GPIO_1_23                  0x1173
-MX23_PAD_LCD_HSYNC__GPIO_1_24                   0x1183
-MX23_PAD_LCD_VSYNC__GPIO_1_25                   0x1193
-MX23_PAD_PWM0__GPIO_1_26                        0x11a3
-MX23_PAD_PWM1__GPIO_1_27                        0x11b3
-MX23_PAD_PWM2__GPIO_1_28                        0x11c3
-MX23_PAD_PWM3__GPIO_1_29                        0x11d3
-MX23_PAD_PWM4__GPIO_1_30                        0x11e3
-MX23_PAD_SSP1_CMD__GPIO_2_0                     0x2003
-MX23_PAD_SSP1_DETECT__GPIO_2_1                  0x2013
-MX23_PAD_SSP1_DATA0__GPIO_2_2                   0x2023
-MX23_PAD_SSP1_DATA1__GPIO_2_3                   0x2033
-MX23_PAD_SSP1_DATA2__GPIO_2_4                   0x2043
-MX23_PAD_SSP1_DATA3__GPIO_2_5                   0x2053
-MX23_PAD_SSP1_SCK__GPIO_2_6                     0x2063
-MX23_PAD_ROTARYA__GPIO_2_7                      0x2073
-MX23_PAD_ROTARYB__GPIO_2_8                      0x2083
-MX23_PAD_EMI_A00__GPIO_2_9                      0x2093
-MX23_PAD_EMI_A01__GPIO_2_10                     0x20a3
-MX23_PAD_EMI_A02__GPIO_2_11                     0x20b3
-MX23_PAD_EMI_A03__GPIO_2_12                     0x20c3
-MX23_PAD_EMI_A04__GPIO_2_13                     0x20d3
-MX23_PAD_EMI_A05__GPIO_2_14                     0x20e3
-MX23_PAD_EMI_A06__GPIO_2_15                     0x20f3
-MX23_PAD_EMI_A07__GPIO_2_16                     0x2103
-MX23_PAD_EMI_A08__GPIO_2_17                     0x2113
-MX23_PAD_EMI_A09__GPIO_2_18                     0x2123
-MX23_PAD_EMI_A10__GPIO_2_19                     0x2133
-MX23_PAD_EMI_A11__GPIO_2_20                     0x2143
-MX23_PAD_EMI_A12__GPIO_2_21                     0x2153
-MX23_PAD_EMI_BA0__GPIO_2_22                     0x2163
-MX23_PAD_EMI_BA1__GPIO_2_23                     0x2173
-MX23_PAD_EMI_CASN__GPIO_2_24                    0x2183
-MX23_PAD_EMI_CE0N__GPIO_2_25                    0x2193
-MX23_PAD_EMI_CE1N__GPIO_2_26                    0x21a3
-MX23_PAD_GPMI_CE1N__GPIO_2_27                   0x21b3
-MX23_PAD_GPMI_CE0N__GPIO_2_28                   0x21c3
-MX23_PAD_EMI_CKE__GPIO_2_29                     0x21d3
-MX23_PAD_EMI_RASN__GPIO_2_30                    0x21e3
-MX23_PAD_EMI_WEN__GPIO_2_31                     0x21f3
diff --git a/Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt b/Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt
deleted file mode 100644
index daa76895606..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt
+++ /dev/null
@@ -1,83 +0,0 @@
-Lantiq FALCON pinmux controller
-
-Required properties:
-- compatible: "lantiq,pinctrl-falcon"
-- reg: Should contain the physical address and length of the gpio/pinmux
-  register range
-
-Please refer to pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices, including the meaning of the
-phrase "pin configuration node".
-
-Lantiq's pin configuration nodes act as a container for an abitrary number of
-subnodes. Each of these subnodes represents some desired configuration for a
-pin, a group, or a list of pins or groups. This configuration can include the
-mux function to select on those group(s), and two pin configuration parameters:
-pull-up and open-drain
-
-The name of each subnode is not important as long as it is unique; all subnodes
-should be enumerated and processed purely based on their content.
-
-Each subnode only affects those parameters that are explicitly listed. In
-other words, a subnode that lists a mux function but no pin configuration
-parameters implies no information about any pin configuration parameters.
-Similarly, a pin subnode that describes a pullup parameter implies no
-information about e.g. the mux function.
-
-We support 2 types of nodes.
-
-Definition of mux function groups:
-
-Required subnode-properties:
-- lantiq,groups : An array of strings. Each string contains the name of a group.
-  Valid values for these names are listed below.
-- lantiq,function: A string containing the name of the function to mux to the
-  group. Valid values for function names are listed below.
-
-Valid values for group and function names:
-
-  mux groups:
-    por, ntr, ntr8k, hrst, mdio, bootled, asc0, spi, spi cs0, spi cs1, i2c,
-    jtag, slic, pcm, asc1
-
-  functions:
-    rst, ntr, mdio, led, asc, spi, i2c, jtag, slic, pcm
-
-
-Definition of pin configurations:
-
-Required subnode-properties:
-- lantiq,pins : An array of strings. Each string contains the name of a pin.
-  Valid values for these names are listed below.
-
-Optional subnode-properties:
-- lantiq,pull: Integer, representing the pull-down/up to apply to the pin.
-    0: none, 1: down
-- lantiq,drive-current: Boolean, enables drive-current
-- lantiq,slew-rate: Boolean, enables slew-rate
-
-Example:
-        pinmux0 {
-                compatible = "lantiq,pinctrl-falcon";
-                pinctrl-names = "default";
-                pinctrl-0 = <&state_default>;
-
-                state_default: pinmux {
-                        asc0 {
-                                lantiq,groups = "asc0";
-                                lantiq,function = "asc";
-                        };
-                        ntr {
-                                lantiq,groups = "ntr8k";
-                                lantiq,function = "ntr";
-                        };
-                        i2c {
-                                lantiq,groups = "i2c";
-                                lantiq,function = "i2c";
-                        };
-                        hrst {
-                                lantiq,groups = "hrst";
-                                lantiq,function = "rst";
-                        };
-                };
-        };
diff --git a/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt b/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt
deleted file mode 100644
index b5469db1d7a..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt
+++ /dev/null
@@ -1,97 +0,0 @@
-Lantiq XWAY pinmux controller
-
-Required properties:
-- compatible: "lantiq,pinctrl-xway" or "lantiq,pinctrl-xr9"
-- reg: Should contain the physical address and length of the gpio/pinmux
-  register range
-
-Please refer to pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices, including the meaning of the
-phrase "pin configuration node".
-
-Lantiq's pin configuration nodes act as a container for an abitrary number of
-subnodes. Each of these subnodes represents some desired configuration for a
-pin, a group, or a list of pins or groups. This configuration can include the
-mux function to select on those group(s), and two pin configuration parameters:
-pull-up and open-drain
-
-The name of each subnode is not important as long as it is unique; all subnodes
-should be enumerated and processed purely based on their content.
-
-Each subnode only affects those parameters that are explicitly listed. In
-other words, a subnode that lists a mux function but no pin configuration
-parameters implies no information about any pin configuration parameters.
-Similarly, a pin subnode that describes a pullup parameter implies no
-information about e.g. the mux function.
-
-We support 2 types of nodes.
-
-Definition of mux function groups:
-
-Required subnode-properties:
-- lantiq,groups : An array of strings. Each string contains the name of a group.
-  Valid values for these names are listed below.
-- lantiq,function: A string containing the name of the function to mux to the
-  group. Valid values for function names are listed below.
-
-Valid values for group and function names:
-
-  mux groups:
-    exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1,
-    ebu wait, nand ale, nand cs1, nand cle, spi, spi_cs1, spi_cs2, spi_cs3,
-    spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi , gpt1, gpt2,
-    gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3, req1, req2,
-    req3
-
-  additional mux groups (XR9 only):
-    mdio, nand rdy, nand rd, exin3, exin4, gnt4, req4
-
-  functions:
-    spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio
-
-
-
-Definition of pin configurations:
-
-Required subnode-properties:
-- lantiq,pins : An array of strings. Each string contains the name of a pin.
-  Valid values for these names are listed below.
-
-Optional subnode-properties:
-- lantiq,pull: Integer, representing the pull-down/up to apply to the pin.
-    0: none, 1: down, 2: up.
-- lantiq,open-drain: Boolean, enables open-drain on the defined pin.
-
-Valid values for XWAY pin names:
-  Pinconf pins can be referenced via the names io0-io31.
-
-Valid values for XR9 pin names:
-  Pinconf pins can be referenced via the names io0-io55.
-
-Example:
-        gpio: pinmux@E100B10 {
-                compatible = "lantiq,pinctrl-xway";
-                pinctrl-names = "default";
-                pinctrl-0 = <&state_default>;
-
-                #gpio-cells = <2>;
-                gpio-controller;
-                reg = <0xE100B10 0xA0>;
-
-                state_default: pinmux {
-                        stp {
-                                lantiq,groups = "stp";
-                                lantiq,function = "stp";
-                        };
-                        pci {
-                                lantiq,groups = "gnt1";
-                                lantiq,function = "pci";
-                        };
-                        conf_out {
-                                lantiq,pins = "io4", "io5", "io6"; /* stp */
-                                lantiq,open-drain;
-                                lantiq,pull = <0>;
-                        };
-                };
-        };
-
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
deleted file mode 100644
index 01ef408e205..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
+++ /dev/null
@@ -1,95 +0,0 @@
-* Marvell Armada 370 SoC pinctrl driver for mpp
-
-Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
-part and usage.
-
-Required properties:
-- compatible: "marvell,88f6710-pinctrl"
-
-Available mpp pins/groups and functions:
-Note: brackets (x) are not part of the mpp name for marvell,function and given
-only for more detailed description in this document.
-
-name          pins     functions
-================================================================================
-mpp0          0        gpio, uart0(rxd)
-mpp1          1        gpo, uart0(txd)
-mpp2          2        gpio, i2c0(sck), uart0(txd)
-mpp3          3        gpio, i2c0(sda), uart0(rxd)
-mpp4          4        gpio, cpu_pd(vdd)
-mpp5          5        gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk)
-mpp6          6        gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo)
-mpp7          7        gpo, ge0(txd1), tdm(tdx), audio(lrclk)
-mpp8          8        gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
-mpp9          9        gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo)
-mpp10         10       gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi)
-mpp11         11       gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1),
-                       sata1(prsnt), spi1(cs1)
-mpp12         12       gpio, ge0(rxd1), i2c1(sda), sd0(d0), spi1(cs0),
-                       audio(spdifi)
-mpp13         13       gpio, ge0(rxd2), i2c1(sck), sd0(d1), tdm(pclk),
-                       audio(rmclk)
-mpp14         14       gpio, ge0(rxd3), pcie(clkreq0), sd0(d2), spi1(mosi),
-                       spi0(cs2)
-mpp15         15       gpio, ge0(rxctl), pcie(clkreq1), sd0(d3), spi1(miso),
-                       spi0(cs3)
-mpp16         16       gpio, ge0(rxclk), uart1(rxd), tdm(int), audio(extclk)
-mpp17         17       gpo, ge(mdc)
-mpp18         18       gpio, ge(mdio)
-mpp19         19       gpio, ge0(txclk), ge1(txclkout), tdm(pclk)
-mpp20         20       gpo, ge0(txd4), ge1(txd0)
-mpp21         21       gpo, ge0(txd5), ge1(txd1), uart1(txd)
-mpp22         22       gpo, ge0(txd6), ge1(txd2), uart0(rts)
-mpp23         23       gpo, ge0(txd7), ge1(txd3), spi1(mosi)
-mpp24         24       gpio, ge0(col), ge1(txctl), spi1(cs0)
-mpp25         25       gpio, ge0(rxerr), ge1(rxd0), uart1(rxd)
-mpp26         26       gpio, ge0(crs), ge1(rxd1), spi1(miso)
-mpp27         27       gpio, ge0(rxd4), ge1(rxd2), uart0(cts)
-mpp28         28       gpio, ge0(rxd5), ge1(rxd3)
-mpp29         29       gpio, ge0(rxd6), ge1(rxctl), i2c1(sda)
-mpp30         30       gpio, ge0(rxd7), ge1(rxclk), i2c1(sck)
-mpp31         31       gpio, tclk, ge0(txerr)
-mpp32         32       gpio, spi0(cs0)
-mpp33         33       gpio, dev(bootcs), spi0(cs0)
-mpp34         34       gpo, dev(wen0), spi0(mosi)
-mpp35         35       gpo, dev(oen), spi0(sck)
-mpp36         36       gpo, dev(a1), spi0(miso)
-mpp37         37       gpo, dev(a0), sata0(prsnt)
-mpp38         38       gpio, dev(ready), uart1(cts), uart0(cts)
-mpp39         39       gpo, dev(ad0), audio(spdifo)
-mpp40         40       gpio, dev(ad1), uart1(rts), uart0(rts)
-mpp41         41       gpio, dev(ad2), uart1(rxd)
-mpp42         42       gpo, dev(ad3), uart1(txd)
-mpp43         43       gpo, dev(ad4), audio(bclk)
-mpp44         44       gpo, dev(ad5), audio(mclk)
-mpp45         45       gpo, dev(ad6), audio(lrclk)
-mpp46         46       gpo, dev(ad7), audio(sdo)
-mpp47         47       gpo, dev(ad8), sd0(clk), audio(spdifo)
-mpp48         48       gpio, dev(ad9), uart0(rts), sd0(cmd), sata1(prsnt),
-                       spi0(cs1)
-mpp49         49       gpio, dev(ad10), pcie(clkreq1), sd0(d0), spi1(cs0),
-                       audio(spdifi)
-mpp50         50       gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso),
-                       audio(rmclk)
-mpp51         51       gpio, dev(ad12), i2c1(sda), sd0(d2), spi1(mosi)
-mpp52         52       gpio, dev(ad13), i2c1(sck), sd0(d3), spi1(sck)
-mpp53         53       gpio, dev(ad14), sd0(clk), tdm(pclk), spi0(cs2),
-                       pcie(clkreq1)
-mpp54         54       gpo, dev(ad15), tdm(dtx)
-mpp55         55       gpio, dev(cs1), uart1(txd), tdm(rst), sata1(prsnt),
-                       sata0(prsnt)
-mpp56         56       gpio, dev(cs2), uart1(cts), uart0(cts), spi0(cs3),
-                       pcie(clkreq0), spi1(cs1)
-mpp57         57       gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt),
-                       audio(sdo)
-mpp58         58       gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk),
-                       uart0(rts)
-mpp59         59       gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk)
-mpp60         60       gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out),
-                       audio(sdi)
-mpp61         61       gpo, dev(wen1), uart1(txd), audio(rclk)
-mpp62         62       gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0),
-                       audio(mclk), uart0(cts)
-mpp63         63       gpo, spi0(sck), tclk
-mpp64         64       gpio, spi0(miso), spi0-1(cs1)
-mpp65         65       gpio, spi0(mosi), spi0-1(cs2)
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
deleted file mode 100644
index bfa0a2e5e0c..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
+++ /dev/null
@@ -1,100 +0,0 @@
-* Marvell Armada XP SoC pinctrl driver for mpp
-
-Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
-part and usage.
-
-Required properties:
-- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
-              "marvell,mv78460-pinctrl"
-
-This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460.
-
-Available mpp pins/groups and functions:
-Note: brackets (x) are not part of the mpp name for marvell,function and given
-only for more detailed description in this document.
-
-* Marvell Armada XP (all variants)
-
-name          pins     functions
-================================================================================
-mpp0          0        gpio, ge0(txclko), lcd(d0)
-mpp1          1        gpio, ge0(txd0), lcd(d1)
-mpp2          2        gpio, ge0(txd1), lcd(d2)
-mpp3          3        gpio, ge0(txd2), lcd(d3)
-mpp4          4        gpio, ge0(txd3), lcd(d4)
-mpp5          5        gpio, ge0(txctl), lcd(d5)
-mpp6          6        gpio, ge0(rxd0), lcd(d6)
-mpp7          7        gpio, ge0(rxd1), lcd(d7)
-mpp8          8        gpio, ge0(rxd2), lcd(d8)
-mpp9          9        gpio, ge0(rxd3), lcd(d9)
-mpp10         10       gpio, ge0(rxctl), lcd(d10)
-mpp11         11       gpio, ge0(rxclk), lcd(d11)
-mpp12         12       gpio, ge0(txd4), ge1(txd0), lcd(d12)
-mpp13         13       gpio, ge0(txd5), ge1(txd1), lcd(d13)
-mpp14         14       gpio, ge0(txd6), ge1(txd2), lcd(d15)
-mpp15         15       gpio, ge0(txd7), ge1(txd3), lcd(d16)
-mpp16         16       gpio, ge0(txd7), ge1(txd3), lcd(d16)
-mpp17         17       gpio, ge0(col), ge1(txctl), lcd(d17)
-mpp18         18       gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig)
-mpp19         19       gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq)
-mpp20         20       gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk)
-mpp21         21       gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat)
-mpp22         22       gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt)
-mpp23         23       gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt)
-mpp24         24       gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst)
-mpp25         25       gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk)
-mpp26         26       gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd)
-mpp27         27       gpio, lcd(e), tdm(dtx), ptp(trig)
-mpp28         28       gpio, lcd(pwm), tdm(drx), ptp(evreq)
-mpp29         29       gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd)
-mpp30         30       gpio, tdm(int1), sd0(clk)
-mpp31         31       gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd)
-mpp32         32       gpio, tdm(int3), sd0(d0), vdd(cpu1-pd)
-mpp33         33       gpio, tdm(int4), sd0(d1), mem(bat)
-mpp34         34       gpio, tdm(int5), sd0(d2), sata0(prsnt)
-mpp35         35       gpio, tdm(int6), sd0(d3), sata1(prsnt)
-mpp36         36       gpio, spi(mosi)
-mpp37         37       gpio, spi(miso)
-mpp38         38       gpio, spi(sck)
-mpp39         39       gpio, spi(cs0)
-mpp40         40       gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd),
-                       pcie(clkreq0)
-mpp41         41       gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
-                       pcie(clkreq1)
-mpp42         42       gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer),
-                       vdd(cpu0-pd)
-mpp43         43       gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout),
-                       vdd(cpu2-3-pd){1}
-mpp44         44       gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2),
-                       mem(bat)
-mpp45         45       gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt)
-mpp46         46       gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt)
-mpp47         47       gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3),
-                       ref(clkout)
-mpp48         48       gpio, tclk, dev(burst/last)
-
-* Marvell Armada XP (mv78260 and mv78460 only)
-
-name          pins     functions
-================================================================================
-mpp49         49       gpio, dev(we3)
-mpp50         50       gpio, dev(we2)
-mpp51         51       gpio, dev(ad16)
-mpp52         52       gpio, dev(ad17)
-mpp53         53       gpio, dev(ad18)
-mpp54         54       gpio, dev(ad19)
-mpp55         55       gpio, dev(ad20), vdd(cpu0-pd)
-mpp56         56       gpio, dev(ad21), vdd(cpu1-pd)
-mpp57         57       gpio, dev(ad22), vdd(cpu2-3-pd){1}
-mpp58         58       gpio, dev(ad23)
-mpp59         59       gpio, dev(ad24)
-mpp60         60       gpio, dev(ad25)
-mpp61         61       gpio, dev(ad26)
-mpp62         62       gpio, dev(ad27)
-mpp63         63       gpio, dev(ad28)
-mpp64         64       gpio, dev(ad29)
-mpp65         65       gpio, dev(ad30)
-mpp66         66       gpio, dev(ad31)
-
-Notes:
-* {1} vdd(cpu2-3-pd) only available on mv78460.
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
deleted file mode 100644
index a648aaad611..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
+++ /dev/null
@@ -1,72 +0,0 @@
-* Marvell Dove SoC pinctrl driver for mpp
-
-Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
-part and usage.
-
-Required properties:
-- compatible: "marvell,dove-pinctrl"
-- clocks: (optional) phandle of pdma clock
-
-Available mpp pins/groups and functions:
-Note: brackets (x) are not part of the mpp name for marvell,function and given
-only for more detailed description in this document.
-
-name          pins     functions
-================================================================================
-mpp0          0        gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm)
-mpp1          1        gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm)
-mpp2          2        gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
-                       uart1(rts)
-mpp3          3        gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
-                       uart1(cts), lcd-spi(cs1)
-mpp4          4        gpio, pmu, uart3(rts), sdio1(cd), spi1(miso)
-mpp5          5        gpio, pmu, uart3(cts), sdio1(wp), spi1(cs)
-mpp6          6        gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi)
-mpp7          7        gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck)
-mpp8          8        gpio, pmu, watchdog(rstout)
-mpp9          9        gpio, pmu, pex1(clkreq)
-mpp10         10       gpio, pmu, ssp(sclk)
-mpp11         11       gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
-                       sdio1(ledctrl), pex0(clkreq)
-mpp12         12       gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd), sata(act)
-mpp13         13       gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
-                       ssp(extclk)
-mpp14         14       gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd)
-mpp15         15       gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm)
-mpp16         16       gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
-mpp17         17       gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda),
-                       ac97-1(sysclko)
-mpp18         18       gpio, uart3(txd), sdio0(buspwr), ac97(sdi3), lcd0(pwm)
-mpp19         19       gpio, uart3(rxd), sdio0(ledctrl), twsi(sck)
-mpp20         20       gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso),
-                       ac97(sysclko)
-mpp21         21       gpio, sdio0(wp), sdio1(wp), spi1(cs), lcd-spi(cs0),
-                       uart1(cts), ssp(sfrm)
-mpp22         22       gpio, sdio0(buspwr), sdio1(buspwr), spi1(mosi),
-                       lcd-spi(mosi), uart1(cts), ssp(txd)
-mpp23         23       gpio, sdio0(ledctrl), sdio1(ledctrl), spi1(sck),
-                       lcd-spi(sck), ssp(sclk)
-mpp_camera    24-39    gpio, camera
-mpp_sdio0     40-45    gpio, sdio0
-mpp_sdio1     46-51    gpio, sdio1
-mpp_audio1    52-57    gpio, i2s1/spdifo, i2s1, spdifo, twsi, ssp/spdifo, ssp,
-                       ssp/twsi
-mpp_spi0      58-61    gpio, spi0
-mpp_uart1     62-63    gpio, uart1
-mpp_nand      64-71    gpo, nand
-audio0        -        i2s, ac97
-twsi          -        none, opt1, opt2, opt3
-
-Notes:
-* group "mpp_audio1" allows the following functions and gpio pins:
-  - gpio          : gpio on pins 52-57
-  - i2s1/spdifo   : audio1 i2s on pins 52-55 and spdifo on 57, no gpios
-  - i2s1          : audio1 i2s on pins 52-55, gpio on pins 56,57
-  - spdifo        : spdifo on pin 57, gpio on pins 52-55
-  - twsi          : twsi on pins 56,57, gpio on pins 52-55
-  - ssp/spdifo    : ssp on pins 52-55, spdifo on pin 57, no gpios
-  - ssp           : ssp on pins 52-55, gpio on pins 56,57
-  - ssp/twsi      : ssp on pins 52-55, twsi on pins 56,57, no gpios
-* group "audio0" internally muxes i2s0 or ac97 controller to the dedicated
-  audio0 pins.
-* group "twsi" internally muxes twsi controller to the dedicated or option pins.
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
deleted file mode 100644
index 95daf6335c3..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
+++ /dev/null
@@ -1,318 +0,0 @@
-* Marvell Kirkwood SoC pinctrl driver for mpp
-
-Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
-part and usage.
-
-Required properties:
-- compatible: "marvell,88f6180-pinctrl",
-              "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
-              "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
-              "marvell,98dx4122-pinctrl"
-
-This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
-It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
-
-Available mpp pins/groups and functions:
-Note: brackets (x) are not part of the mpp name for marvell,function and given
-only for more detailed description in this document.
-
-* Marvell Kirkwood 88f6180
-
-name          pins     functions
-================================================================================
-mpp0          0        gpio, nand(io2), spi(cs)
-mpp1          1        gpo, nand(io3), spi(mosi)
-mpp2          2        gpo, nand(io4), spi(sck)
-mpp3          3        gpo, nand(io5), spi(miso)
-mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk)
-mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig)
-mpp6          6        sysrst(out), spi(mosi), ptp(trig)
-mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
-mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
-                       mii(col)
-mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
-                       mii(crs)
-mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig)
-mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
-                       ptp-2(trig)
-mpp12         12       gpo, sdio(clk)
-mpp13         13       gpio, sdio(cmd), uart1(txd)
-mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col)
-mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd)
-mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
-mpp17         17       gpio, sdio(d3)
-mpp18         18       gpo, nand(io0)
-mpp19         19       gpo, nand(io1)
-mpp20         20       gpio, mii(rxerr)
-mpp21         21       gpio, audio(spdifi)
-mpp22         22       gpio, audio(spdifo)
-mpp23         23       gpio, audio(rmclk)
-mpp24         24       gpio, audio(bclk)
-mpp25         25       gpio, audio(sdo)
-mpp26         26       gpio, audio(lrclk)
-mpp27         27       gpio, audio(mclk)
-mpp28         28       gpio, audio(sdi)
-mpp29         29       gpio, audio(extclk)
-
-* Marvell Kirkwood 88f6190
-
-name          pins     functions
-================================================================================
-mpp0          0        gpio, nand(io2), spi(cs)
-mpp1          1        gpo, nand(io3), spi(mosi)
-mpp2          2        gpo, nand(io4), spi(sck)
-mpp3          3        gpo, nand(io5), spi(miso)
-mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk)
-mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
-mpp6          6        sysrst(out), spi(mosi), ptp(trig)
-mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
-mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
-                       mii(col), mii-1(rxerr)
-mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
-                       mii(crs), sata0(prsnt)
-mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig)
-mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
-                       ptp-2(trig), sata0(act)
-mpp12         12       gpo, sdio(clk)
-mpp13         13       gpio, sdio(cmd), uart1(txd)
-mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col)
-mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
-mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
-mpp17         17       gpio, sdio(d3), sata0(prsnt)
-mpp18         18       gpo, nand(io0)
-mpp19         19       gpo, nand(io1)
-mpp20         20       gpio, ge1(txd0)
-mpp21         21       gpio, ge1(txd1), sata0(act)
-mpp22         22       gpio, ge1(txd2)
-mpp23         23       gpio, ge1(txd3), sata0(prsnt)
-mpp24         24       gpio, ge1(rxd0)
-mpp25         25       gpio, ge1(rxd1)
-mpp26         26       gpio, ge1(rxd2)
-mpp27         27       gpio, ge1(rxd3)
-mpp28         28       gpio, ge1(col)
-mpp29         29       gpio, ge1(txclk)
-mpp30         30       gpio, ge1(rxclk)
-mpp31         31       gpio, ge1(rxclk)
-mpp32         32       gpio, ge1(txclko)
-mpp33         33       gpo, ge1(txclk)
-mpp34         34       gpio, ge1(txen)
-mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr)
-
-* Marvell Kirkwood 88f6192
-
-name          pins     functions
-================================================================================
-mpp0          0        gpio, nand(io2), spi(cs)
-mpp1          1        gpo, nand(io3), spi(mosi)
-mpp2          2        gpo, nand(io4), spi(sck)
-mpp3          3        gpo, nand(io5), spi(miso)
-mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
-mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
-mpp6          6        sysrst(out), spi(mosi), ptp(trig)
-mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
-mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
-                       mii(col), mii-1(rxerr), sata1(prsnt)
-mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
-                       mii(crs), sata0(prsnt)
-mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
-mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
-                       ptp-2(trig), sata0(act)
-mpp12         12       gpo, sdio(clk)
-mpp13         13       gpio, sdio(cmd), uart1(txd)
-mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
-mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
-mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
-                       sata1(act)
-mpp17         17       gpio, sdio(d3), sata0(prsnt)
-mpp18         18       gpo, nand(io0)
-mpp19         19       gpo, nand(io1)
-mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
-                       sata1(act)
-mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
-                       audio(spdifo)
-mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
-                       sata1(prsnt)
-mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
-                       audio(bclk)
-mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
-mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
-mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
-mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
-mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
-mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst)
-mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk)
-mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs)
-mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx)
-mpp33         33       gpo, ge1(txclk), tdm(drx)
-mpp34         34       gpio, ge1(txen), tdm(spi-cs1)
-mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
-
-* Marvell Kirkwood 88f6281
-
-name          pins     functions
-================================================================================
-mpp0          0        gpio, nand(io2), spi(cs)
-mpp1          1        gpo, nand(io3), spi(mosi)
-mpp2          2        gpo, nand(io4), spi(sck)
-mpp3          3        gpo, nand(io5), spi(miso)
-mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
-mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
-mpp6          6        sysrst(out), spi(mosi), ptp(trig)
-mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
-mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
-                       mii(col), mii-1(rxerr), sata1(prsnt)
-mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
-                       mii(crs), sata0(prsnt)
-mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
-mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
-                       ptp-2(trig), sata0(act)
-mpp12         12       gpio, sdio(clk)
-mpp13         13       gpio, sdio(cmd), uart1(txd)
-mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
-mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
-mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
-                       sata1(act)
-mpp17         17       gpio, sdio(d3), sata0(prsnt)
-mpp18         18       gpo, nand(io0)
-mpp19         19       gpo, nand(io1)
-mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
-                       sata1(act)
-mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
-                       audio(spdifo)
-mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
-                       sata1(prsnt)
-mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
-                       audio(bclk)
-mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
-mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
-mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
-mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
-mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
-mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst)
-mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk)
-mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs)
-mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx)
-mpp33         33       gpo, ge1(txclk), tdm(drx)
-mpp34         34       gpio, ge1(txen), tdm(spi-cs1), sata1(act)
-mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
-mpp36         36       gpio, ts(mp0), tdm(spi-cs1), audio(spdifi)
-mpp37         37       gpio, ts(mp1), tdm(tx2ql), audio(spdifo)
-mpp38         38       gpio, ts(mp2), tdm(rx2ql), audio(rmclk)
-mpp39         39       gpio, ts(mp3), tdm(spi-cs0), audio(bclk)
-mpp40         40       gpio, ts(mp4), tdm(spi-sck), audio(sdo)
-mpp41         41       gpio, ts(mp5), tdm(spi-miso), audio(lrclk)
-mpp42         42       gpio, ts(mp6), tdm(spi-mosi), audio(mclk)
-mpp43         43       gpio, ts(mp7), tdm(int), audio(sdi)
-mpp44         44       gpio, ts(mp8), tdm(rst), audio(extclk)
-mpp45         45       gpio, ts(mp9), tdm(pclk)
-mpp46         46       gpio, ts(mp10), tdm(fs)
-mpp47         47       gpio, ts(mp11), tdm(drx)
-mpp48         48       gpio, ts(mp12), tdm(dtx)
-mpp49         49       gpio, ts(mp9), tdm(rx0ql), ptp(clk)
-
-* Marvell Kirkwood 88f6282
-
-name          pins     functions
-================================================================================
-mpp0          0        gpio, nand(io2), spi(cs)
-mpp1          1        gpo, nand(io3), spi(mosi)
-mpp2          2        gpo, nand(io4), spi(sck)
-mpp3          3        gpo, nand(io5), spi(miso)
-mpp4          4        gpio, nand(io6), uart0(rxd), sata1(act), lcd(hsync)
-mpp5          5        gpo, nand(io7), uart0(txd), sata0(act), lcd(vsync)
-mpp6          6        sysrst(out), spi(mosi)
-mpp7          7        gpo, spi(cs), lcd(pwm)
-mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), mii(col),
-                       mii-1(rxerr), sata1(prsnt)
-mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), mii(crs),
-                       sata0(prsnt)
-mpp10         10       gpo, spi(sck), uart0(txd), sata1(act)
-mpp11         11       gpio, spi(miso), uart0(rxd), sata0(act)
-mpp12         12       gpo, sdio(clk), audio(spdifo), spi(mosi), twsi(sda)
-mpp13         13       gpio, sdio(cmd), uart1(txd), audio(rmclk), lcd(pwm)
-mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt),
-                       audio(spdifi), audio-1(sdi)
-mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act),
-                       spi(cs)
-mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
-                       sata1(act), lcd(extclk)
-mpp17         17       gpio, sdio(d3), sata0(prsnt), sata1(act), twsi1(sck)
-mpp18         18       gpo, nand(io0), pex(clkreq)
-mpp19         19       gpo, nand(io1)
-mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
-                       sata1(act), lcd(d0)
-mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
-                       audio(spdifo), lcd(d1)
-mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
-                       sata1(prsnt), lcd(d2)
-mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
-                       audio(bclk), lcd(d3)
-mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo),
-                       lcd(d4)
-mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk),
-                       lcd(d5)
-mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk),
-                       lcd(d6)
-mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi),
-                       lcd(d7)
-mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk),
-                       lcd(d8)
-mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst), lcd(d9)
-mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk), lcd(d10)
-mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs), lcd(d11)
-mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx), lcd(d12)
-mpp33         33       gpo, ge1(txclk), tdm(drx), lcd(d13)
-mpp34         34       gpio, ge1(txen), tdm(spi-cs1), sata1(act), lcd(d14)
-mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql),
-                       lcd(d15)
-mpp36         36       gpio, ts(mp0), tdm(spi-cs1), audio(spdifi), twsi1(sda)
-mpp37         37       gpio, ts(mp1), tdm(tx2ql), audio(spdifo), twsi1(sck)
-mpp38         38       gpio, ts(mp2), tdm(rx2ql), audio(rmclk), lcd(d18)
-mpp39         39       gpio, ts(mp3), tdm(spi-cs0), audio(bclk), lcd(d19)
-mpp40         40       gpio, ts(mp4), tdm(spi-sck), audio(sdo), lcd(d20)
-mpp41         41       gpio, ts(mp5), tdm(spi-miso), audio(lrclk), lcd(d21)
-mpp42         42       gpio, ts(mp6), tdm(spi-mosi), audio(mclk), lcd(d22)
-mpp43         43       gpio, ts(mp7), tdm(int), audio(sdi), lcd(d23)
-mpp44         44       gpio, ts(mp8), tdm(rst), audio(extclk), lcd(clk)
-mpp45         45       gpio, ts(mp9), tdm(pclk), lcd(e)
-mpp46         46       gpio, ts(mp10), tdm(fs), lcd(hsync)
-mpp47         47       gpio, ts(mp11), tdm(drx), lcd(vsync)
-mpp48         48       gpio, ts(mp12), tdm(dtx), lcd(d16)
-mpp49         49       gpo, tdm(rx0ql), pex(clkreq), lcd(d17)
-
-* Marvell Bobcat 98dx4122
-
-name          pins     functions
-================================================================================
-mpp0          0        gpio, nand(io2), spi(cs)
-mpp1          1        gpo, nand(io3), spi(mosi)
-mpp2          2        gpo, nand(io4), spi(sck)
-mpp3          3        gpo, nand(io5), spi(miso)
-mpp4          4        gpio, nand(io6), uart0(rxd)
-mpp5          5        gpo, nand(io7), uart0(txd)
-mpp6          6        sysrst(out), spi(mosi)
-mpp7          7        gpo, pex(rsto), spi(cs)
-mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts)
-mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts)
-mpp10         10       gpo, spi(sck), uart0(txd)
-mpp11         11       gpio, spi(miso), uart0(rxd)
-mpp13         13       gpio, uart1(txd)
-mpp14         14       gpio, uart1(rxd)
-mpp15         15       gpio, uart0(rts)
-mpp16         16       gpio, uart0(cts)
-mpp18         18       gpo, nand(io0)
-mpp19         19       gpo, nand(io1)
-mpp34         34       gpio
-mpp35         35       gpio
-mpp36         36       gpio
-mpp37         37       gpio
-mpp38         38       gpio
-mpp39         39       gpio
-mpp40         40       gpio
-mpp41         41       gpio
-mpp42         42       gpio
-mpp43         43       gpio
-mpp44         44       gpio
-mpp45         45       gpio
-mpp49         49       gpio
-
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
deleted file mode 100644
index 0a26c3aa4e6..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-* Marvell SoC pinctrl core driver for mpp
-
-The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
-(mpp) to a specific function. For each SoC family there is a SoC specific
-driver using this core driver.
-
-Please refer to pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices, including the meaning of the
-phrase "pin configuration node".
-
-A Marvell SoC pin configuration node is a node of a group of pins which can
-be used for a specific device or function. Each node requires one or more
-mpp pins or group of pins and a mpp function common to all pins.
-
-Required properties for pinctrl driver:
-- compatible: "marvell,<soc>-pinctrl"
-  Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
-
-Required properties for pin configuration node:
-- marvell,pins: string array of mpp pins or group of pins to be muxed.
-- marvell,function: string representing a function to mux to for all
-    marvell,pins given in this pin configuration node. The function has to be
-    common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for
-    valid pin/pin group names and available function names for each SoC.
-
-Examples:
-
-uart1: serial@12100 {
-        compatible = "ns16550a";
-        reg = <0x12100 0x100>;
-        reg-shift = <2>;
-        interrupts = <7>;
-
-        pinctrl-0 = <&pmx_uart1_sw>;
-        pinctrl-names = "default";
-};
-
-pinctrl: pinctrl@d0200 {
-        compatible = "marvell,dove-pinctrl";
-        reg = <0xd0200 0x20>;
-
-        pmx_uart1_sw: pmx-uart1-sw {
-                marvell,pins = "mpp_uart1";
-                marvell,function = "uart1";
-        };
-};
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
deleted file mode 100644
index 683fde93c4f..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
+++ /dev/null
@@ -1,132 +0,0 @@
-NVIDIA Tegra20 pinmux controller
-
-Required properties:
-- compatible: "nvidia,tegra20-pinmux"
-- reg: Should contain the register physical address and length for each of
-  the tri-state, mux, pull-up/down, and pad control register sets.
-
-Please refer to pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices, including the meaning of the
-phrase "pin configuration node".
-
-Tegra's pin configuration nodes act as a container for an abitrary number of
-subnodes. Each of these subnodes represents some desired configuration for a
-pin, a group, or a list of pins or groups. This configuration can include the
-mux function to select on those pin(s)/group(s), and various pin configuration
-parameters, such as pull-up, tristate, drive strength, etc.
-
-The name of each subnode is not important; all subnodes should be enumerated
-and processed purely based on their content.
-
-Each subnode only affects those parameters that are explicitly listed. In
-other words, a subnode that lists a mux function but no pin configuration
-parameters implies no information about any pin configuration parameters.
-Similarly, a pin subnode that describes a pullup parameter implies no
-information about e.g. the mux function or tristate parameter. For this
-reason, even seemingly boolean values are actually tristates in this binding:
-unspecified, off, or on. Unspecified is represented as an absent property,
-and off/on are represented as integer values 0 and 1.
-
-Required subnode-properties:
-- nvidia,pins : An array of strings. Each string contains the name of a pin or
-    group. Valid values for these names are listed below.
-
-Optional subnode-properties:
-- nvidia,function: A string containing the name of the function to mux to the
-  pin or group. Valid values for function names are listed below. See the Tegra
-  TRM to determine which are valid for each pin or group.
-- nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
-    0: none, 1: down, 2: up.
-- nvidia,tristate: Integer.
-    0: drive, 1: tristate.
-- nvidia,high-speed-mode: Integer. Enable high speed mode the pins.
-    0: no, 1: yes.
-- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.
-    0: no, 1: yes.
-- nvidia,low-power-mode: Integer. Valid values 0-3. 0 is least power, 3 is
-    most power. Controls the drive power or current. See "Low Power Mode"
-    or "LPMD1" and "LPMD0" in the Tegra TRM.
-- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
-    The range of valid values depends on the pingroup. See "CAL_DRVDN" in the
-    Tegra TRM.
-- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
-    The range of valid values depends on the pingroup. See "CAL_DRVUP" in the
-    Tegra TRM.
-- nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is
-    fastest. The range of valid values depends on the pingroup. See
-    "DRVDN_SLWR" in the Tegra TRM.
-- nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is
-    fastest. The range of valid values depends on the pingroup. See
-    "DRVUP_SLWF" in the Tegra TRM.
-
-Note that many of these properties are only valid for certain specific pins
-or groups. See the Tegra TRM and various pinmux spreadsheets for complete
-details regarding which groups support which functionality. The Linux pinctrl
-driver may also be a useful reference, since it consolidates, disambiguates,
-and corrects data from all those sources.
-
-Valid values for pin and group names are:
-
-  mux groups:
-
-    These all support nvidia,function, nvidia,tristate, and many support
-    nvidia,pull.
-
-    ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1, dap2, dap3, dap4,
-    ddc, dta, dtb, dtc, dtd, dte, dtf, gma, gmb, gmc, gmd, gme, gpu, gpu7,
-    gpv, hdint, i2cp, irrx, irtx, kbca, kbcb, kbcc, kbcd, kbce, kbcf, lcsn,
-    ld0, ld1, ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12, ld13,
-    ld14, ld15, ld16, ld17, ldc, ldi, lhp0, lhp1, lhp2, lhs, lm0, lm1, lpp,
-    lpw0, lpw1, lpw2, lsc0, lsc1, lsck, lsda, lsdi, lspi, lvp0, lvp1, lvs,
-    owc, pmc, pta, rm, sdb, sdc, sdd, sdio1, slxa, slxc, slxd, slxk, spdi,
-    spdo, spia, spib, spic, spid, spie, spif, spig, spih, uaa, uab, uac, uad,
-    uca, ucb, uda.
-
-  tristate groups:
-
-    These only support nvidia,pull.
-
-    ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls, lc, ld17_0,
-    ld19_18, ld21_20, ld23_22.
-
-  drive groups:
-
-    With some exceptions, these support nvidia,high-speed-mode,
-    nvidia,schmitt, nvidia,low-power-mode, nvidia,pull-down-strength,
-    nvidia,pull-up-strength, nvidia,slew-rate-rising, nvidia,slew-rate-falling.
-
-    drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1, drive_cdev2,
-    drive_csus, drive_dap1, drive_dap2, drive_dap3, drive_dap4, drive_dbg,
-    drive_lcd1, drive_lcd2, drive_sdmmc2, drive_sdmmc3, drive_spi, drive_uaa,
-    drive_uab, drive_uart2, drive_uart3, drive_vi1, drive_vi2, drive_xm2a,
-    drive_xm2c, drive_xm2d, drive_xm2clk, drive_sdio1, drive_crt, drive_ddc,
-    drive_gma, drive_gmb, drive_gmc, drive_gmd, drive_gme, drive_owr,
-    drive_uda.
-
-Example:
-
-        pinctrl@70000000 {
-                compatible = "nvidia,tegra20-pinmux";
-                reg = < 0x70000014 0x10    /* Tri-state registers */
-                        0x70000080 0x20    /* Mux registers */
-                        0x700000a0 0x14    /* Pull-up/down registers */
-                        0x70000868 0xa8 >; /* Pad control registers */
-        };
-
-Example board file extract:
-
-        pinctrl@70000000 {
-                sdio4_default: sdio4_default {
-                        atb {
-                                nvidia,pins = "atb", "gma", "gme";
-                                nvidia,function = "sdio4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                        };
-                };
-        };
-
-        sdhci@c8000600 {
-                pinctrl-names = "default";
-                pinctrl-0 = <&sdio4_default>;
-        };
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
deleted file mode 100644
index 6f426ed7009..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
+++ /dev/null
@@ -1,132 +0,0 @@
-NVIDIA Tegra30 pinmux controller
-
-The Tegra30 pinctrl binding is very similar to the Tegra20 pinctrl binding,
-as described in nvidia,tegra20-pinmux.txt. In fact, this document assumes
-that binding as a baseline, and only documents the differences between the
-two bindings.
-
-Required properties:
-- compatible: "nvidia,tegra30-pinmux"
-- reg: Should contain the register physical address and length for each of
-  the pad control and mux registers.
-
-Tegra30 adds the following optional properties for pin configuration subnodes:
-- nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
-- nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
-- nvidia,lock: Integer. Lock the pin configuration against further changes
-    until reset. 0: no, 1: yes.
-- nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
-
-As with Tegra20, see the Tegra TRM for complete details regarding which groups
-support which functionality.
-
-Valid values for pin and group names are:
-
-  per-pin mux groups:
-
-    These all support nvidia,function, nvidia,tristate, nvidia,pull,
-    nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain,
-    nvidia,io-reset.
-
-    clk_32k_out_pa0, uart3_cts_n_pa1, dap2_fs_pa2, dap2_sclk_pa3,
-    dap2_din_pa4, dap2_dout_pa5, sdmmc3_clk_pa6, sdmmc3_cmd_pa7, gmi_a17_pb0,
-    gmi_a18_pb1, lcd_pwr0_pb2, lcd_pclk_pb3, sdmmc3_dat3_pb4, sdmmc3_dat2_pb5,
-    sdmmc3_dat1_pb6, sdmmc3_dat0_pb7, uart3_rts_n_pc0, lcd_pwr1_pc1,
-    uart2_txd_pc2, uart2_rxd_pc3, gen1_i2c_scl_pc4, gen1_i2c_sda_pc5,
-    lcd_pwr2_pc6, gmi_wp_n_pc7, sdmmc3_dat5_pd0, sdmmc3_dat4_pd1, lcd_dc1_pd2,
-    sdmmc3_dat6_pd3, sdmmc3_dat7_pd4, vi_d1_pd5, vi_vsync_pd6, vi_hsync_pd7,
-    lcd_d0_pe0, lcd_d1_pe1, lcd_d2_pe2, lcd_d3_pe3, lcd_d4_pe4, lcd_d5_pe5,
-    lcd_d6_pe6, lcd_d7_pe7, lcd_d8_pf0, lcd_d9_pf1, lcd_d10_pf2, lcd_d11_pf3,
-    lcd_d12_pf4, lcd_d13_pf5, lcd_d14_pf6, lcd_d15_pf7, gmi_ad0_pg0,
-    gmi_ad1_pg1, gmi_ad2_pg2, gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5,
-    gmi_ad6_pg6, gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
-    gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, gmi_ad15_ph7,
-    gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_pi2, gmi_cs6_n_pi3, gmi_rst_n_pi4,
-    gmi_iordy_pi5, gmi_cs7_n_pi6, gmi_wait_pi7, gmi_cs0_n_pj0, lcd_de_pj1,
-    gmi_cs1_n_pj2, lcd_hsync_pj3, lcd_vsync_pj4, uart2_cts_n_pj5,
-    uart2_rts_n_pj6, gmi_a16_pj7, gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs4_n_pk2,
-    gmi_cs2_n_pk3, gmi_cs3_n_pk4, spdif_out_pk5, spdif_in_pk6, gmi_a19_pk7,
-    vi_d2_pl0, vi_d3_pl1, vi_d4_pl2, vi_d5_pl3, vi_d6_pl4, vi_d7_pl5,
-    vi_d8_pl6, vi_d9_pl7, lcd_d16_pm0, lcd_d17_pm1, lcd_d18_pm2, lcd_d19_pm3,
-    lcd_d20_pm4, lcd_d21_pm5, lcd_d22_pm6, lcd_d23_pm7, dap1_fs_pn0,
-    dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3, lcd_cs0_n_pn4, lcd_sdout_pn5,
-    lcd_dc0_pn6, hdmi_int_pn7, ulpi_data7_po0, ulpi_data0_po1, ulpi_data1_po2,
-    ulpi_data2_po3, ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6,
-    ulpi_data6_po7, dap3_fs_pp0, dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3,
-    dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, kb_col0_pq0,
-    kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
-    kb_col6_pq6, kb_col7_pq7, kb_row0_pr0, kb_row1_pr1, kb_row2_pr2,
-    kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7,
-    kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, kb_row12_ps4,
-    kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, vi_pclk_pt0, vi_mclk_pt1,
-    vi_d10_pt2, vi_d11_pt3, vi_d0_pt4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6,
-    sdmmc4_cmd_pt7, pu0, pu1, pu2, pu3, pu4, pu5, pu6, jtag_rtck_pu7, pv0,
-    pv1, pv2, pv3, ddc_scl_pv4, ddc_sda_pv5, crt_hsync_pv6, crt_vsync_pv7,
-    lcd_cs1_n_pw0, lcd_m1_pw1, spi2_cs1_n_pw2, spi2_cs2_n_pw3, clk1_out_pw4,
-    clk2_out_pw5, uart3_txd_pw6, uart3_rxd_pw7, spi2_mosi_px0, spi2_miso_px1,
-    spi2_sck_px2, spi2_cs0_n_px3, spi1_mosi_px4, spi1_sck_px5, spi1_cs0_n_px6,
-    spi1_miso_px7, ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3,
-    sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6, sdmmc1_dat0_py7,
-    sdmmc1_clk_pz0, sdmmc1_cmd_pz1, lcd_sdin_pz2, lcd_wr_n_pz3, lcd_sck_pz4,
-    sys_clk_req_pz5, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, sdmmc4_dat0_paa0,
-    sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4,
-    sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, pbb0,
-    cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, pbb7,
-    cam_mclk_pcc0, pcc1, pcc2, sdmmc4_rst_n_pcc3, sdmmc4_clk_pcc4,
-    clk2_req_pcc5, pex_l2_rst_n_pcc6, pex_l2_clkreq_n_pcc7,
-    pex_l0_prsnt_n_pdd0, pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2,
-    pex_wake_n_pdd3, pex_l1_prsnt_n_pdd4, pex_l1_rst_n_pdd5,
-    pex_l1_clkreq_n_pdd6, pex_l2_prsnt_n_pdd7, clk3_out_pee0, clk3_req_pee1,
-    clk1_req_pee2, hdmi_cec_pee3, clk_32k_in, core_pwr_req, cpu_pwr_req, owr,
-    pwr_int_n.
-
-  drive groups:
-
-    These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
-    nvidia,slew-rate-rising, nvidia,slew-rate-falling. Most but not all
-    support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode.
-
-    ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, cec, crt, csus, dap1,
-    dap2, dap3, dap4, dbg, ddc, dev3, gma, gmb, gmc, gmd, gme, gmf, gmg,
-    gmh, gpv, lcd1, lcd2, owr, sdio1, sdio2, sdio3, spi, uaa, uab, uart2,
-    uart3, uda, vi1.
-
-Example:
-
-        pinctrl@70000000 {
-                compatible = "nvidia,tegra30-pinmux";
-                reg = < 0x70000868 0xd0     /* Pad control registers */
-                        0x70003000 0x3e0 >; /* Mux registers */
-        };
-
-Example board file extract:
-
-        pinctrl@70000000 {
-                sdmmc4_default: pinmux {
-                        sdmmc4_clk_pcc4 {
-                                nvidia,pins =   "sdmmc4_clk_pcc4",
-                                                "sdmmc4_rst_n_pcc3";
-                                nvidia,function = "sdmmc4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                        };
-                        sdmmc4_dat0_paa0 {
-                                nvidia,pins =   "sdmmc4_dat0_paa0",
-                                                "sdmmc4_dat1_paa1",
-                                                "sdmmc4_dat2_paa2",
-                                                "sdmmc4_dat3_paa3",
-                                                "sdmmc4_dat4_paa4",
-                                                "sdmmc4_dat5_paa5",
-                                                "sdmmc4_dat6_paa6",
-                                                "sdmmc4_dat7_paa7";
-                                nvidia,function = "sdmmc4";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                        };
-                };
-        };
-
-        sdhci@78000400 {
-                pinctrl-names = "default";
-                pinctrl-0 = <&sdmmc4_default>;
-        };
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
deleted file mode 100644
index c95ea8278f8..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+++ /dev/null
@@ -1,128 +0,0 @@
-== Introduction ==
-
-Hardware modules that control pin multiplexing or configuration parameters
-such as pull-up/down, tri-state, drive-strength etc are designated as pin
-controllers. Each pin controller must be represented as a node in device tree,
-just like any other hardware module.
-
-Hardware modules whose signals are affected by pin configuration are
-designated client devices. Again, each client device must be represented as a
-node in device tree, just like any other hardware module.
-
-For a client device to operate correctly, certain pin controllers must
-set up certain specific pin configurations. Some client devices need a
-single static pin configuration, e.g. set up during initialization. Others
-need to reconfigure pins at run-time, for example to tri-state pins when the
-device is inactive. Hence, each client device can define a set of named
-states. The number and names of those states is defined by the client device's
-own binding.
-
-The common pinctrl bindings defined in this file provide an infrastructure
-for client device device tree nodes to map those state names to the pin
-configuration used by those states.
-
-Note that pin controllers themselves may also be client devices of themselves.
-For example, a pin controller may set up its own "active" state when the
-driver loads. This would allow representing a board's static pin configuration
-in a single place, rather than splitting it across multiple client device
-nodes. The decision to do this or not somewhat rests with the author of
-individual board device tree files, and any requirements imposed by the
-bindings for the individual client devices in use by that board, i.e. whether
-they require certain specific named states for dynamic pin configuration.
-
-== Pinctrl client devices ==
-
-For each client device individually, every pin state is assigned an integer
-ID. These numbers start at 0, and are contiguous. For each state ID, a unique
-property exists to define the pin configuration. Each state may also be
-assigned a name. When names are used, another property exists to map from
-those names to the integer IDs.
-
-Each client device's own binding determines the set of states the must be
-defined in its device tree node, and whether to define the set of state
-IDs that must be provided, or whether to define the set of state names that
-must be provided.
-
-Required properties:
-pinctrl-0:      List of phandles, each pointing at a pin configuration
-                node. These referenced pin configuration nodes must be child
-                nodes of the pin controller that they configure. Multiple
-                entries may exist in this list so that multiple pin
-                controllers may be configured, or so that a state may be built
-                from multiple nodes for a single pin controller, each
-                contributing part of the overall configuration. See the next
-                section of this document for details of the format of these
-                pin configuration nodes.
-
-                In some cases, it may be useful to define a state, but for it
-                to be empty. This may be required when a common IP block is
-                used in an SoC either without a pin controller, or where the
-                pin controller does not affect the HW module in question. If
-                the binding for that IP block requires certain pin states to
-                exist, they must still be defined, but may be left empty.
-
-Optional properties:
-pinctrl-1:      List of phandles, each pointing at a pin configuration
-                node within a pin controller.
-...
-pinctrl-n:      List of phandles, each pointing at a pin configuration
-                node within a pin controller.
-pinctrl-names:  The list of names to assign states. List entry 0 defines the
-                name for integer state ID 0, list entry 1 for state ID 1, and
-                so on.
-
-For example:
-
-        /* For a client device requiring named states */
-        device {
-                pinctrl-names = "active", "idle";
-                pinctrl-0 = <&state_0_node_a>;
-                pinctrl-1 = <&state_1_node_a &state_1_node_b>;
-        };
-
-        /* For the same device if using state IDs */
-        device {
-                pinctrl-0 = <&state_0_node_a>;
-                pinctrl-1 = <&state_1_node_a &state_1_node_b>;
-        };
-
-        /*
-         * For an IP block whose binding supports pin configuration,
-         * but in use on an SoC that doesn't have any pin control hardware
-         */
-        device {
-                pinctrl-names = "active", "idle";
-                pinctrl-0 = <>;
-                pinctrl-1 = <>;
-        };
-
-== Pin controller devices ==
-
-Pin controller devices should contain the pin configuration nodes that client
-devices reference.
-
-For example:
-
-        pincontroller {
-                ... /* Standard DT properties for the device itself elided */
-
-                state_0_node_a {
-                        ...
-                };
-                state_1_node_a {
-                        ...
-                };
-                state_1_node_b {
-                        ...
-                };
-        }
-
-The contents of each of those pin configuration child nodes is defined
-entirely by the binding for the individual pin controller device. There
-exists no common standard for this content.
-
-The pin configuration nodes need not be direct children of the pin controller
-device; they may be grandchildren, for example. Whether this is legal, and
-whether there is any interaction between the child and intermediate parent
-nodes, is again defined entirely by the binding for the individual pin
-controller device.
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
deleted file mode 100644
index 2c81e45f137..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
+++ /dev/null
@@ -1,128 +0,0 @@
-One-register-per-pin type device tree based pinctrl driver
-
-Required properties:
-- compatible : "pinctrl-single"
-
-- reg : offset and length of the register set for the mux registers
-
-- pinctrl-single,register-width : pinmux register access width in bits
-
-- pinctrl-single,function-mask : mask of allowed pinmux function bits
-  in the pinmux register
-
-Optional properties:
-- pinctrl-single,function-off : function off mode for disabled state if
-  available and same for all registers; if not specified, disabling of
-  pin functions is ignored
-- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
-  more than one pin
-
-This driver assumes that there is only one register for each pin (unless the
-pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
-specified in the pinctrl-bindings.txt document in this directory.
-
-The pin configuration nodes for pinctrl-single are specified as pinctrl
-register offset and value pairs using pinctrl-single,pins. Only the bits
-specified in pinctrl-single,function-mask are updated. For example, setting
-a pin for a device could be done with:
-
-        pinctrl-single,pins = <0xdc 0x118>;
-
-Where 0xdc is the offset from the pinctrl register base address for the
-device pinctrl register, and 0x118 contains the desired value of the
-pinctrl register. See the device example and static board pins example
-below for more information.
-
-In case when one register changes more than one pin's mux the
-pinctrl-single,bits need to be used which takes three parameters:
-
-        pinctrl-single,bits = <0xdc 0x18, 0xff>;
-
-Where 0xdc is the offset from the pinctrl register base address for the
-device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
-be used when applying this change to the register.
-
-Example:
-
-/* SoC common file */
-
-/* first controller instance for pins in core domain */
-pmx_core: pinmux@4a100040 {
-        compatible = "pinctrl-single";
-        reg = <0x4a100040 0x0196>;
-        #address-cells = <1>;
-        #size-cells = <0>;
-        pinctrl-single,register-width = <16>;
-        pinctrl-single,function-mask = <0xffff>;
-};
-
-/* second controller instance for pins in wkup domain */
-pmx_wkup: pinmux@4a31e040 {
-        compatible = "pinctrl-single;
-        reg = <0x4a31e040 0x0038>;
-        #address-cells = <1>;
-        #size-cells = <0>;
-        pinctrl-single,register-width = <16>;
-        pinctrl-single,function-mask = <0xffff>;
-};
-
-control_devconf0: pinmux@48002274 {
-        compatible = "pinctrl-single";
-        reg = <0x48002274 4>;   /* Single register */
-        #address-cells = <1>;
-        #size-cells = <0>;
-        pinctrl-single,bit-per-mux;
-        pinctrl-single,register-width = <32>;
-        pinctrl-single,function-mask = <0x5F>;
-};
-
-/* board specific .dts file */
-
-&pmx_core {
-
-        /*
-         * map all board specific static pins enabled by the pinctrl driver
-         * itself during the boot (or just set them up in the bootloader)
-         */
-        pinctrl-names = "default";
-        pinctrl-0 = <&board_pins>;
-
-        board_pins: pinmux_board_pins {
-                pinctrl-single,pins = <
-                        0x6c 0xf
-                        0x6e 0xf
-                        0x70 0xf
-                        0x72 0xf
-                >;
-        };
-
-        /* map uart2 pins */
-        uart2_pins: pinmux_uart2_pins {
-                pinctrl-single,pins = <
-                        0xd8 0x118
-                        0xda 0
-                        0xdc 0x118
-                        0xde 0
-                >;
-        };
-};
-
-&control_devconf0 {
-        mcbsp1_pins: pinmux_mcbsp1_pins {
-                pinctrl-single,bits = <
-                        0x00 0x18 0x18 /* FSR/CLKR signal from FSX/CLKX pin */
-                >;
-        };
-
-        mcbsp2_clks_pins: pinmux_mcbsp2_clks_pins {
-                pinctrl-single,bits = <
-                        0x00 0x40 0x40 /* McBSP2 CLKS from McBSP_CLKS pin */
-                >;
-        };
-
-};
-
-&uart2 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&uart2_pins>;
-};
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt
deleted file mode 100644
index c596a6ad328..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt
+++ /dev/null
@@ -1,47 +0,0 @@
-CSR SiRFprimaII pinmux controller
-
-Required properties:
-- compatible    : "sirf,prima2-pinctrl"
-- reg           : Address range of the pinctrl registers
-- interrupts    : Interrupts used by every GPIO group
-- gpio-controller : Indicates this device is a GPIO controller
-- interrupt-controller  : Marks the device node as an interrupt controller
-Optional properties:
-- sirf,pullups : if n-th bit of m-th bank is set, set a pullup on GPIO-n of bank m
-- sirf,pulldowns : if n-th bit of m-th bank is set, set a pulldown on GPIO-n of bank m
-
-Please refer to pinctrl-bindings.txt in this directory for details of the common
-pinctrl bindings used by client devices.
-
-SiRFprimaII's pinmux nodes act as a container for an abitrary number of subnodes.
-Each of these subnodes represents some desired configuration for a group of pins.
-
-Required subnode-properties:
-- sirf,pins : An array of strings. Each string contains the name of a group.
-- sirf,function: A string containing the name of the function to mux to the
-  group.
-
-  Valid values for group and function names can be found from looking at the
-  group and function arrays in driver files:
-  drivers/pinctrl/pinctrl-sirf.c
-
-For example, pinctrl might have subnodes like the following:
- uart2_pins_a: uart2@0 {
-         uart {
-                 sirf,pins = "uart2grp";
-                 sirf,function = "uart2";
-         };
- };
- uart2_noflow_pins_a: uart2@1 {
-         uart {
-                 sirf,pins = "uart2_nostreamctrlgrp";
-                 sirf,function = "uart2_nostreamctrl";
-         };
- };
-
-For a specific board, if it wants to use uart2 without hardware flow control,
-it can add the following to its board-specific .dts file.
-uart2: uart@0xb0070000 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&uart2_noflow_pins_a>;
-}
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
deleted file mode 100644
index b4480d5c3ac..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
+++ /dev/null
@@ -1,155 +0,0 @@
-ST Microelectronics, SPEAr pinmux controller
-
-Required properties:
-- compatible    : "st,spear300-pinmux"
-                : "st,spear310-pinmux"
-                : "st,spear320-pinmux"
-                : "st,spear1310-pinmux"
-                : "st,spear1340-pinmux"
-- reg           : Address range of the pinctrl registers
-- st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
-        - Its values for SPEAr300:
-                - NAND_MODE             : <0>
-                - NOR_MODE              : <1>
-                - PHOTO_FRAME_MODE      : <2>
-                - LEND_IP_PHONE_MODE    : <3>
-                - HEND_IP_PHONE_MODE    : <4>
-                - LEND_WIFI_PHONE_MODE  : <5>
-                - HEND_WIFI_PHONE_MODE  : <6>
-                - ATA_PABX_WI2S_MODE    : <7>
-                - ATA_PABX_I2S_MODE     : <8>
-                - CAML_LCDW_MODE        : <9>
-                - CAMU_LCD_MODE         : <10>
-                - CAMU_WLCD_MODE        : <11>
-                - CAML_LCD_MODE         : <12>
-        - Its values for SPEAr320:
-                - AUTO_NET_SMII_MODE    : <0>
-                - AUTO_NET_MII_MODE     : <1>
-                - AUTO_EXP_MODE         : <2>
-                - SMALL_PRINTERS_MODE   : <3>
-                - EXTENDED_MODE         : <4>
-
-Please refer to pinctrl-bindings.txt in this directory for details of the common
-pinctrl bindings used by client devices.
-
-SPEAr's pinmux nodes act as a container for an abitrary number of subnodes. Each
-of these subnodes represents muxing for a pin, a group, or a list of pins or
-groups.
-
-The name of each subnode is not important; all subnodes should be enumerated
-and processed purely based on their content.
-
-Required subnode-properties:
-- st,pins : An array of strings. Each string contains the name of a pin or
-  group.
-- st,function: A string containing the name of the function to mux to the pin or
-  group. See the SPEAr's TRM to determine which are valid for each pin or group.
-
-  Valid values for group and function names can be found from looking at the
-  group and function arrays in driver files:
-  drivers/pinctrl/spear/pinctrl-spear3*0.c
-
-Valid values for group names are:
-For All SPEAr3xx machines:
-        "firda_grp", "i2c0_grp", "ssp_cs_grp", "ssp0_grp", "mii0_grp",
-        "gpio0_pin0_grp", "gpio0_pin1_grp", "gpio0_pin2_grp", "gpio0_pin3_grp",
-        "gpio0_pin4_grp", "gpio0_pin5_grp", "uart0_ext_grp", "uart0_grp",
-        "timer_0_1_grp", timer_0_1_pins, "timer_2_3_grp"
-
-For SPEAr300 machines:
-        "fsmc_2chips_grp", "fsmc_4chips_grp", "clcd_lcdmode_grp",
-        "clcd_pfmode_grp", "tdm_grp", "i2c_clk_grp_grp", "caml_grp", "camu_grp",
-        "dac_grp", "i2s_grp", "sdhci_4bit_grp", "sdhci_8bit_grp",
-        "gpio1_0_to_3_grp", "gpio1_4_to_7_grp"
-
-For SPEAr310 machines:
-        "emi_cs_0_to_5_grp", "uart1_grp", "uart2_grp", "uart3_grp", "uart4_grp",
-        "uart5_grp", "fsmc_grp", "rs485_0_grp", "rs485_1_grp", "tdm_grp"
-
-For SPEAr320 machines:
-        "clcd_grp", "emi_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "spp_grp",
-        "sdhci_led_grp", "sdhci_cd_12_grp", "sdhci_cd_51_grp", "i2s_grp",
-        "uart1_grp", "uart1_modem_2_to_7_grp", "uart1_modem_31_to_36_grp",
-        "uart1_modem_34_to_45_grp", "uart1_modem_80_to_85_grp", "uart2_grp",
-        "uart3_8_9_grp", "uart3_15_16_grp", "uart3_41_42_grp",
-        "uart3_52_53_grp", "uart3_73_74_grp", "uart3_94_95_grp",
-        "uart3_98_99_grp", "uart4_6_7_grp", "uart4_13_14_grp",
-        "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
-        "uart4_100_101_grp", "uart5_4_5_grp", "uart5_37_38_grp",
-        "uart5_69_70_grp", "uart5_90_91_grp", "uart6_2_3_grp",
-        "uart6_88_89_grp", "rs485_grp", "touchscreen_grp", "can0_grp",
-        "can1_grp", "pwm0_1_pin_8_9_grp", "pwm0_1_pin_14_15_grp",
-        "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp", "pwm0_1_pin_42_43_grp",
-        "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp", "pwm2_pin_7_grp",
-        "pwm2_pin_13_grp", "pwm2_pin_29_grp", "pwm2_pin_34_grp",
-        "pwm2_pin_41_grp", "pwm2_pin_58_grp", "pwm2_pin_87_grp",
-        "pwm3_pin_6_grp", "pwm3_pin_12_grp", "pwm3_pin_28_grp",
-        "pwm3_pin_40_grp", "pwm3_pin_57_grp", "pwm3_pin_86_grp",
-        "ssp1_17_20_grp", "ssp1_36_39_grp", "ssp1_48_51_grp", "ssp1_65_68_grp",
-        "ssp1_94_97_grp", "ssp2_13_16_grp", "ssp2_32_35_grp", "ssp2_44_47_grp",
-        "ssp2_61_64_grp", "ssp2_90_93_grp", "mii2_grp", "smii0_1_grp",
-        "rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp",
-        "i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp"
-
-For SPEAr1310 machines:
-        "i2c0_grp", "ssp0_grp", "ssp0_cs0_grp", "ssp0_cs1_2_grp", "i2s0_grp",
-        "i2s1_grp", "clcd_grp", "clcd_high_res_grp", "arm_gpio_grp",
-        "smi_2_chips_grp", "smi_4_chips_grp", "gmii_grp", "rgmii_grp",
-        "smii_0_1_2_grp", "ras_mii_txclk_grp", "nand_8bit_grp",
-        "nand_16bit_grp", "nand_4_chips_grp", "keyboard_6x6_grp",
-        "keyboard_rowcol6_8_grp", "uart0_grp", "uart0_modem_grp",
-        "gpt0_tmr0_grp", "gpt0_tmr1_grp", "gpt1_tmr0_grp", "gpt1_tmr1_grp",
-        "sdhci_grp", "cf_grp", "xd_grp", "touch_xy_grp",
-        "uart1_disable_i2c_grp", "uart1_disable_sd_grp", "uart2_3_grp",
-        "uart4_grp", "uart5_grp", "rs485_0_1_tdm_0_1_grp", "i2c_1_2_grp",
-        "i2c3_dis_smi_clcd_grp", "i2c3_dis_sd_i2s0_grp", "i2c_4_5_dis_smi_grp",
-        "i2c4_dis_sd_grp", "i2c5_dis_sd_grp", "i2c_6_7_dis_kbd_grp",
-        "i2c6_dis_sd_grp", "i2c7_dis_sd_grp", "can0_dis_nor_grp",
-        "can0_dis_sd_grp", "can1_dis_sd_grp", "can1_dis_kbd_grp", "pcie0_grp",
-        "pcie1_grp", "pcie2_grp", "sata0_grp", "sata1_grp", "sata2_grp",
-        "ssp1_dis_kbd_grp", "ssp1_dis_sd_grp", "gpt64_grp"
-
-For SPEAr1340 machines:
-        "pads_as_gpio_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "fsmc_pnor_grp",
-        "keyboard_row_col_grp", "keyboard_col5_grp", "spdif_in_grp",
-        "spdif_out_grp", "gpt_0_1_grp", "pwm0_grp", "pwm1_grp", "pwm2_grp",
-        "pwm3_grp", "vip_mux_grp", "vip_mux_cam0_grp", "vip_mux_cam1_grp",
-        "vip_mux_cam2_grp", "vip_mux_cam3_grp", "cam0_grp", "cam1_grp",
-        "cam2_grp", "cam3_grp", "smi_grp", "ssp0_grp", "ssp0_cs1_grp",
-        "ssp0_cs2_grp", "ssp0_cs3_grp", "uart0_grp", "uart0_enh_grp",
-        "uart1_grp", "i2s_in_grp", "i2s_out_grp", "gmii_grp", "rgmii_grp",
-        "rmii_grp", "sgmii_grp", "i2c0_grp", "i2c1_grp", "cec0_grp", "cec1_grp",
-        "sdhci_grp", "cf_grp", "xd_grp", "clcd_grp", "arm_trace_grp",
-        "miphy_dbg_grp", "pcie_grp", "sata_grp"
-
-Valid values for function names are:
-For All SPEAr3xx machines:
-        "firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext",
-        "uart0", "timer_0_1", "timer_2_3"
-
-For SPEAr300 machines:
-        "fsmc", "clcd", "tdm", "i2c1", "cam", "dac", "i2s", "sdhci", "gpio1"
-
-For SPEAr310 machines:
-        "emi", "uart1", "uart2", "uart3", "uart4", "uart5", "fsmc", "rs485_0",
-        "rs485_1", "tdm"
-
-For SPEAr320 machines:
-        "clcd", "emi", "fsmc", "spp", "sdhci", "i2s", "uart1", "uart1_modem",
-        "uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen",
-        "can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2",
-        "mii0_1", "i2c1", "i2c2"
-
-
-For SPEAr1310 machines:
-        "i2c0", "ssp0", "i2s0", "i2s1", "clcd", "arm_gpio", "smi", "gmii",
-        "rgmii", "smii_0_1_2", "ras_mii_txclk", "nand", "keyboard", "uart0",
-        "gpt0", "gpt1", "sdhci", "cf", "xd", "touchscreen", "uart1", "uart2_3",
-        "uart4", "uart5", "rs485_0_1_tdm_0_1", "i2c_1_2", "i2c3_i2s1",
-        "i2c_4_5", "i2c_6_7", "can0", "can1", "pci", "sata", "ssp1", "gpt64"
-
-For SPEAr1340 machines:
-        "pads_as_gpio", "fsmc", "keyboard", "spdif_in", "spdif_out", "gpt_0_1",
-        "pwm", "vip", "cam0", "cam1", "cam2", "cam3", "smi", "ssp0", "uart0",
-        "uart1", "i2s", "gmac", "i2c0", "i2c1", "cec0", "cec1", "sdhci", "cf",
-        "xd", "clcd", "arm_trace", "miphy_dbg", "pcie", "sata"
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
deleted file mode 100644
index e97a27856b2..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ /dev/null
@@ -1,265 +0,0 @@
-Samsung GPIO and Pin Mux/Config controller
-
-Samsung's ARM based SoC's integrates a GPIO and Pin mux/config hardware
-controller. It controls the input/output settings on the available pads/pins
-and also provides ability to multiplex and configure the output of various
-on-chip controllers onto these pads.
-
-Required Properties:
-- compatible: should be one of the following.
-  - "samsung,pinctrl-exynos4210": for Exynos4210 compatible pin-controller.
-  - "samsung,pinctrl-exynos4x12": for Exynos4x12 compatible pin-controller.
-  - "samsung,pinctrl-exynos5250": for Exynos5250 compatible pin-controller.
-
-- reg: Base address of the pin controller hardware module and length of
-  the address space it occupies.
-
-- Pin banks as child nodes: Pin banks of the controller are represented by child
-  nodes of the controller node. Bank name is taken from name of the node. Each
-  bank node must contain following properties:
-
-  - gpio-controller: identifies the node as a gpio controller and pin bank.
-  - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
-    binding is used, the amount of cells must be specified as 2. See generic
-    GPIO binding documentation for description of particular cells.
-
-- Pin mux/config groups as child nodes: The pin mux (selecting pin function
-  mode) and pin config (pull up/down, driver strength) settings are represented
-  as child nodes of the pin-controller node. There should be atleast one
-  child node and there is no limit on the count of these child nodes.
-
-  The child node should contain a list of pin(s) on which a particular pin
-  function selection or pin configuration (or both) have to applied. This
-  list of pins is specified using the property name "samsung,pins". There
-  should be atleast one pin specfied for this property and there is no upper
-  limit on the count of pins that can be specified. The pins are specified
-  using pin names which are derived from the hardware manual of the SoC. As
-  an example, the pins in GPA0 bank of the pin controller can be represented
-  as "gpa0-0", "gpa0-1", "gpa0-2" and so on. The names should be in lower case.
-  The format of the pin names should be (as per the hardware manual)
-  "[pin bank name]-[pin number within the bank]".
-
-  The pin function selection that should be applied on the pins listed in the
-  child node is specified using the "samsung,pin-function" property. The value
-  of this property that should be applied to each of the pins listed in the
-  "samsung,pins" property should be picked from the hardware manual of the SoC
-  for the specified pin group. This property is optional in the child node if
-  no specific function selection is desired for the pins listed in the child
-  node. The value of this property is used as-is to program the pin-controller
-  function selector register of the pin-bank.
-
-  The child node can also optionally specify one or more of the pin
-  configuration that should be applied on all the pins listed in the
-  "samsung,pins" property of the child node. The following pin configuration
-  properties are supported.
-
-  - samsung,pin-pud: Pull up/down configuration.
-  - samsung,pin-drv: Drive strength configuration.
-  - samsung,pin-pud-pdn: Pull up/down configuration in power down mode.
-  - samsung,pin-drv-pdn: Drive strength configuration in power down mode.
-
-  The values specified by these config properties should be derived from the
-  hardware manual and these values are programmed as-is into the pin
-  pull up/down and driver strength register of the pin-controller.
-
-  Note: A child should include atleast a pin function selection property or
-  pin configuration property (one or more) or both.
-
-  The client nodes that require a particular pin function selection and/or
-  pin configuration should use the bindings listed in the "pinctrl-bindings.txt"
-  file.
-
-External GPIO and Wakeup Interrupts:
-
-The controller supports two types of external interrupts over gpio. The first
-is the external gpio interrupt and second is the external wakeup interrupts.
-The difference between the two is that the external wakeup interrupts can be
-used as system wakeup events.
-
-A. External GPIO Interrupts: For supporting external gpio interrupts, the
-   following properties should be specified in the pin-controller device node.
-
-   - interrupt-parent: phandle of the interrupt parent to which the external
-     GPIO interrupts are forwarded to.
-   - interrupts: interrupt specifier for the controller. The format and value of
-     the interrupt specifier depends on the interrupt parent for the controller.
-
-   In addition, following properties must be present in node of every bank
-   of pins supporting GPIO interrupts:
-
-   - interrupt-controller: identifies the controller node as interrupt-parent.
-   - #interrupt-cells: the value of this property should be 2.
-     - First Cell: represents the external gpio interrupt number local to the
-       external gpio interrupt space of the controller.
-     - Second Cell: flags to identify the type of the interrupt
-       - 1 = rising edge triggered
-       - 2 = falling edge triggered
-       - 3 = rising and falling edge triggered
-       - 4 = high level triggered
-       - 8 = low level triggered
-
-B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
-   child node representing the external wakeup interrupt controller should be
-   included in the pin-controller device node. This child node should include
-   the following properties.
-
-   - compatible: identifies the type of the external wakeup interrupt controller
-     The possible values are:
-     - samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller
-       found on Samsung Exynos4210 SoC.
-   - interrupt-parent: phandle of the interrupt parent to which the external
-     wakeup interrupts are forwarded to.
-   - interrupts: interrupt used by multiplexed wakeup interrupts.
-
-   In addition, following properties must be present in node of every bank
-   of pins supporting wake-up interrupts:
-
-   - interrupt-controller: identifies the node as interrupt-parent.
-   - #interrupt-cells: the value of this property should be 2
-     - First Cell: represents the external wakeup interrupt number local to
-       the external wakeup interrupt space of the controller.
-     - Second Cell: flags to identify the type of the interrupt
-       - 1 = rising edge triggered
-       - 2 = falling edge triggered
-       - 3 = rising and falling edge triggered
-       - 4 = high level triggered
-       - 8 = low level triggered
-
-   Node of every bank of pins supporting direct wake-up interrupts (without
-   multiplexing) must contain following properties:
-
-   - interrupt-parent: phandle of the interrupt parent to which the external
-     wakeup interrupts are forwarded to.
-   - interrupts: interrupts of the interrupt parent which are used for external
-     wakeup interrupts from pins of the bank, must contain interrupts for all
-     pins of the bank.
-
-Aliases:
-
-All the pin controller nodes should be represented in the aliases node using
-the following format 'pinctrl{n}' where n is a unique number for the alias.
-
-Example: A pin-controller node with pin banks:
-
-        pinctrl_0: pinctrl@11400000 {
-                compatible = "samsung,pinctrl-exynos4210";
-                reg = <0x11400000 0x1000>;
-                interrupts = <0 47 0>;
-
-                /* ... */
-
-                /* Pin bank without external interrupts */
-                gpy0: gpy0 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                };
-
-                /* ... */
-
-                /* Pin bank with external GPIO or muxed wake-up interrupts */
-                gpj0: gpj0 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                /* ... */
-
-                /* Pin bank with external direct wake-up interrupts */
-                gpx0: gpx0 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        interrupt-parent = <&gic>;
-                        interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
-                                     <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
-                        #interrupt-cells = <2>;
-                };
-
-                /* ... */
-        };
-
-Example 1: A pin-controller node with pin groups.
-
-        pinctrl_0: pinctrl@11400000 {
-                compatible = "samsung,pinctrl-exynos4210";
-                reg = <0x11400000 0x1000>;
-                interrupts = <0 47 0>;
-
-                /* ... */
-
-                uart0_data: uart0-data {
-                        samsung,pins = "gpa0-0", "gpa0-1";
-                        samsung,pin-function = <2>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-
-                uart0_fctl: uart0-fctl {
-                        samsung,pins = "gpa0-2", "gpa0-3";
-                        samsung,pin-function = <2>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-
-                uart1_data: uart1-data {
-                        samsung,pins = "gpa0-4", "gpa0-5";
-                        samsung,pin-function = <2>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-
-                uart1_fctl: uart1-fctl {
-                        samsung,pins = "gpa0-6", "gpa0-7";
-                        samsung,pin-function = <2>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-
-                i2c2_bus: i2c2-bus {
-                        samsung,pins = "gpa0-6", "gpa0-7";
-                        samsung,pin-function = <3>;
-                        samsung,pin-pud = <3>;
-                        samsung,pin-drv = <0>;
-                };
-        };
-
-Example 2: A pin-controller node with external wakeup interrupt controller node.
-
-        pinctrl_1: pinctrl@11000000 {
-                compatible = "samsung,pinctrl-exynos4210";
-                reg = <0x11000000 0x1000>;
-                interrupts = <0 46 0>
-
-                /* ... */
-
-                wakeup-interrupt-controller {
-                        compatible = "samsung,exynos4210-wakeup-eint";
-                        interrupt-parent = <&gic>;
-                        interrupts = <0 32 0>;
-                };
-        };
-
-Example 3: A uart client node that supports 'default' and 'flow-control' states.
-
-        uart@13800000 {
-                compatible = "samsung,exynos4210-uart";
-                reg = <0x13800000 0x100>;
-                interrupts = <0 52 0>;
-                pinctrl-names = "default", "flow-control;
-                pinctrl-0 = <&uart0_data>;
-                pinctrl-1 = <&uart0_data &uart0_fctl>;
-        };
-
-Example 4: Set up the default pin state for uart controller.
-
-        static int s3c24xx_serial_probe(struct platform_device *pdev) {
-                struct pinctrl *pinctrl;
-
-                /* ... */
-
-                pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
-        }
diff --git a/Documentation/devicetree/bindings/power/opp.txt b/Documentation/devicetree/bindings/power/opp.txt
deleted file mode 100644
index 74499e5033f..00000000000
--- a/Documentation/devicetree/bindings/power/opp.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-* Generic OPP Interface
-
-SoCs have a standard set of tuples consisting of frequency and
-voltage pairs that the device will support per voltage domain. These
-are called Operating Performance Points or OPPs.
-
-Properties:
-- operating-points: An array of 2-tuples items, and each item consists
-  of frequency and voltage like <freq-kHz vol-uV>.
-        freq: clock frequency in kHz
-        vol: voltage in microvolt
-
-Examples:
-
-cpu@0 {
-        compatible = "arm,cortex-a9";
-        reg = <0>;
-        next-level-cache = <&L2>;
-        operating-points = <
-                /* kHz    uV */
-                792000  1100000
-                396000  950000
-                198000  850000
-        >;
-};
diff --git a/Documentation/devicetree/bindings/power_supply/ab8500/btemp.txt b/Documentation/devicetree/bindings/power_supply/ab8500/btemp.txt
deleted file mode 100644
index 0ba1bcc7f33..00000000000
--- a/Documentation/devicetree/bindings/power_supply/ab8500/btemp.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-=== AB8500 Battery Temperature Monitor Driver ===
-
-The properties below describes the node for btemp driver.
-
-Required Properties:
-- compatible = Shall be: "stericsson,ab8500-btemp"
-- battery = Shall be battery specific information
-
-        Example:
-        ab8500_btemp {
-                compatible = "stericsson,ab8500-btemp";
-                battery    = <&ab8500_battery>;
-        };
-
-For information on battery specific node, Ref:
-Documentation/devicetree/bindings/power_supply/ab8500/fg.txt
diff --git a/Documentation/devicetree/bindings/power_supply/ab8500/chargalg.txt b/Documentation/devicetree/bindings/power_supply/ab8500/chargalg.txt
deleted file mode 100644
index ef532837112..00000000000
--- a/Documentation/devicetree/bindings/power_supply/ab8500/chargalg.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-=== AB8500 Charging Algorithm Driver ===
-
-The properties below describes the node for chargalg driver.
-
-Required Properties:
-- compatible = Shall be: "stericsson,ab8500-chargalg"
-- battery = Shall be battery specific information
-
-Example:
-ab8500_chargalg {
-        compatible = "stericsson,ab8500-chargalg";
-        battery    = <&ab8500_battery>;
-};
-
-For information on battery specific node, Ref:
-Documentation/devicetree/bindings/power_supply/ab8500/fg.txt
diff --git a/Documentation/devicetree/bindings/power_supply/ab8500/charger.txt b/Documentation/devicetree/bindings/power_supply/ab8500/charger.txt
deleted file mode 100644
index 6bdbb08ea9e..00000000000
--- a/Documentation/devicetree/bindings/power_supply/ab8500/charger.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-=== AB8500 Charger Driver ===
-
-Required Properties:
-- compatible = Shall be "stericsson,ab8500-charger"
-- battery = Shall be battery specific information
-        Example:
-        ab8500_charger {
-                compatible = "stericsson,ab8500-charger";
-                battery    = <&ab8500_battery>;
-        };
-
-- vddadc-supply: Supply for USB and Main charger
-        Example:
-        ab8500-charger {
-                vddadc-supply   = <&ab8500_ldo_tvout_reg>;
-        }
-- autopower_cfg:
-        Boolean value depicting the presence of 'automatic poweron after powerloss'
-        Example:
-        ab8500-charger {
-                autopower_cfg;
-        };
-
-For information on battery specific node, Ref:
-Documentation/devicetree/bindings/power_supply/ab8500/fg.txt
diff --git a/Documentation/devicetree/bindings/power_supply/ab8500/fg.txt b/Documentation/devicetree/bindings/power_supply/ab8500/fg.txt
deleted file mode 100644
index ccafcb9112f..00000000000
--- a/Documentation/devicetree/bindings/power_supply/ab8500/fg.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-=== AB8500 Fuel Gauge Driver ===
-
-AB8500 is a mixed signal multimedia and power management
-device comprising: power and energy-management-module,
-wall-charger, usb-charger, audio codec, general purpose adc,
-tvout, clock management and sim card interface.
-
-Fuelgauge support is part of energy-management-modules, other
-components of this module are:
-main-charger, usb-combo-charger and battery-temperature-monitoring.
-
-The properties below describes the node for fuelgauge driver.
-
-Required Properties:
-- compatible = This shall be: "stericsson,ab8500-fg"
-- battery = Shall be battery specific information
-        Example:
-        ab8500_fg {
-                compatible = "stericsson,ab8500-fg";
-                battery    = <&ab8500_battery>;
-        };
-
-dependent node:
-        ab8500_battery: ab8500_battery {
-        };
-        This node will provide information on 'thermistor interface' and
-        'battery technology type' used.
-
-Properties of this node are:
-thermistor-on-batctrl:
-        A boolean value indicating thermistor interface to battery
-
-        Note:
-        'btemp' and 'batctrl' are the pins interfaced for battery temperature
-        measurement, 'btemp' signal is used when NTC(negative temperature
-        coefficient) resister is interfaced external to battery whereas
-        'batctrl' pin is used when NTC resister is internal to battery.
-
-        Example:
-        ab8500_battery: ab8500_battery {
-                thermistor-on-batctrl;
-        };
-        indicates: NTC resister is internal to battery, 'batctrl' is used
-                for thermal measurement.
-
-        The absence of property 'thermal-on-batctrl' indicates
-        NTC resister is external to battery and  'btemp' signal is used
-        for thermal measurement.
-
-battery-type:
-        This shall be the battery manufacturing technology type,
-        allowed types are:
-                "UNKNOWN" "NiMH" "LION" "LIPO" "LiFe" "NiCd" "LiMn"
-        Example:
-        ab8500_battery: ab8500_battery {
-                stericsson,battery-type = "LIPO";
-        }
-
diff --git a/Documentation/devicetree/bindings/power_supply/max17042_battery.txt b/Documentation/devicetree/bindings/power_supply/max17042_battery.txt
deleted file mode 100644
index 5bc9b685cf8..00000000000
--- a/Documentation/devicetree/bindings/power_supply/max17042_battery.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-max17042_battery
-~~~~~~~~~~~~~~~~
-
-Required properties :
- - compatible : "maxim,max17042"
-
-Optional properties :
- - maxim,rsns-microohm : Resistance of rsns resistor in micro Ohms
-                         (datasheet-recommended value is 10000).
-   Defining this property enables current-sense functionality.
-
-Example:
-
-        battery-charger@36 {
-                compatible = "maxim,max17042";
-                reg = <0x36>;
-                maxim,rsns-microohm = <10000>;
-        };
diff --git a/Documentation/devicetree/bindings/power_supply/olpc_battery.txt b/Documentation/devicetree/bindings/power_supply/olpc_battery.txt
deleted file mode 100644
index c8901b3992d..00000000000
--- a/Documentation/devicetree/bindings/power_supply/olpc_battery.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-OLPC battery
-~~~~~~~~~~~~
-
-Required properties:
-  - compatible : "olpc,xo1-battery"
diff --git a/Documentation/devicetree/bindings/power_supply/sbs_sbs-battery.txt b/Documentation/devicetree/bindings/power_supply/sbs_sbs-battery.txt
deleted file mode 100644
index c40e8926fac..00000000000
--- a/Documentation/devicetree/bindings/power_supply/sbs_sbs-battery.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-SBS sbs-battery
-~~~~~~~~~~
-
-Required properties :
- - compatible : "sbs,sbs-battery"
-
-Optional properties :
- - sbs,i2c-retry-count : The number of times to retry i2c transactions on i2c
-   IO failure.
- - sbs,poll-retry-count : The number of times to try looking for new status
-   after an external change notification.
- - sbs,battery-detect-gpios : The gpio which signals battery detection and
-   a flag specifying its polarity.
-
-Example:
-
-        bq20z75@b {
-                compatible = "sbs,sbs-battery";
-                reg = < 0xb >;
-                sbs,i2c-retry-count = <2>;
-                sbs,poll-retry-count = <10>;
-                sbs,battery-detect-gpios = <&gpio-controller 122 1>;
-        }
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/board.txt b/Documentation/devicetree/bindings/powerpc/fsl/board.txt
index 380914e965e..39e941515a3 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/board.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/board.txt
@@ -1,8 +1,3 @@
-Freescale Reference Board Bindings
-
-This document describes device tree bindings for various devices that
-exist on some Freescale reference boards.
-
 * Board Control and Status (BCSR)
 
 Required properties:
@@ -17,26 +12,25 @@ Example:
                 reg = <f8000000 8000>;
         };
 
-* Freescale on-board FPGA
+* Freescale on board FPGA
 
 This is the memory-mapped registers for on board FPGA.
 
 Required properities:
-- compatible: should be a board-specific string followed by a string
-  indicating the type of FPGA.  Example:
-        "fsl,<board>-fpga", "fsl,fpga-pixis"
-- reg: should contain the address and the length of the FPGA register set.
+- compatible : should be "fsl,fpga-pixis".
+- reg : should contain the address and the length of the FPPGA register
+  set.
 - interrupt-parent: should specify phandle for the interrupt controller.
-- interrupts: should specify event (wakeup) IRQ.
+- interrupts : should specify event (wakeup) IRQ.
 
-Example (P1022DS):
+Example (MPC8610HPCD):
 
-         board-control@3,0 {
-                 compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
-                 reg = <3 0 0x30>;
-                 interrupt-parent = <&mpic>;
-                 interrupts = <8 8 0 0>;
-         };
+        board-control@e8000000 {
+                compatible = "fsl,fpga-pixis";
+                reg = <0xe8000000 32>;
+                interrupt-parent = <&mpic>;
+                interrupts = <8 8>;
+        };
 
 * Freescale BCSR GPIO banks
 
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt b/Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt
deleted file mode 100644
index 9d54eb5a295..00000000000
--- a/Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt
+++ /dev/null
@@ -1,395 +0,0 @@
-===================================================================
-Debug Control and Status Register (DCSR) Binding
-Copyright 2011 Freescale Semiconductor Inc.
-
-NOTE: The bindings described in this document are preliminary and subject
-to change.  Some of the compatible strings that contain only generic names
-may turn out to be inappropriate, or need additional properties to describe
-the integration of the block with the rest of the chip.
-
-=====================================================================
-Debug Control and Status Register Memory Map
-
-Description
-
-This node defines the base address and range for the
-defined DCSR Memory Map. Child nodes will describe the individual
-debug blocks defined within this memory space.
-
-PROPERTIES
-
-        - compatible
-        Usage: required
-        Value type: <string>
-        Definition: Must include "fsl,dcsr" and "simple-bus".
-        The DCSR space exists in the memory-mapped bus.
-
-        - #address-cells
-        Usage: required
-        Value type: <u32>
-        Definition: A standard property.  Defines the number of cells
-        or representing physical addresses in child nodes.
-
-        - #size-cells
-        Usage: required
-        Value type: <u32>
-        Definition: A standard property.  Defines the number of cells
-        or representing the size of physical addresses in
-        child nodes.
-
-        - ranges
-        Usage: required
-        Value type: <prop-encoded-array>
-        Definition: A standard property. Specifies the physical address
-        range of the DCSR space.
-
-EXAMPLE
-        dcsr: dcsr@f00000000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "fsl,dcsr", "simple-bus";
-                ranges = <0x00000000 0xf 0x00000000 0x01008000>;
-        };
-
-=====================================================================
-Event Processing Unit
-
-This node represents the region of DCSR space allocated to the EPU
-
-PROPERTIES
-
-        - compatible
-        Usage: required
-        Value type: <string>
-        Definition: Must include "fsl,dcsr-epu"
-
-        - interrupts
-        Usage: required
-        Value type: <prop_encoded-array>
-        Definition:  Specifies the interrupts generated by the EPU.
-        The value of the interrupts property consists of three
-        interrupt specifiers. The format of the specifier is defined
-        by the binding document describing the node's interrupt parent.
-
-        The EPU counters can be configured to assert the performance
-        monitor interrupt signal based on either counter overflow or value
-        match. Which counter asserted the interrupt is captured in an EPU
-        Counter Interrupt Status Register (EPCPUISR).
-
-        The EPU unit can also be configured to assert either or both of
-        two interrupt signals based on debug event sources within the SoC.
-        The interrupt signals are epu_xt_int0 and epu_xt_int1.
-        Which event source asserted the interrupt is captured in an EPU
-        Interrupt Status Register (EPISR0,EPISR1).
-
-        Interrupt numbers are lised in order (perfmon, event0, event1).
-
-        - interrupt-parent
-        Usage: required
-        Value type: <phandle>
-        Definition: A single <phandle> value that points
-        to the interrupt parent to which the child domain
-        is being mapped. Value must be "&mpic"
-
-        - reg
-        Usage: required
-        Value type: <prop-encoded-array>
-        Definition: A standard property.  Specifies the physical address
-        offset and length of the DCSR space registers of the device
-        configuration block.
-
-EXAMPLE
-        dcsr-epu@0 {
-                compatible = "fsl,dcsr-epu";
-                interrupts = <52 2 0 0
-                              84 2 0 0
-                              85 2 0 0>;
-                interrupt-parent = <&mpic>;
-                reg = <0x0 0x1000>;
-        };
-
-=======================================================================
-Nexus Port Controller
-
-This node represents the region of DCSR space allocated to the NPC
-
-PROPERTIES
-
-        - compatible
-        Usage: required
-        Value type: <string>
-        Definition: Must include "fsl,dcsr-npc"
-
-        - reg
-        Usage: required
-        Value type: <prop-encoded-array>
-        Definition: A standard property.  Specifies the physical address
-        offset and length of the DCSR space registers of the device
-        configuration block.
-        The Nexus Port controller occupies two regions in the DCSR space
-        with distinct functionality.
-
-        The first register range describes the Nexus Port Controller
-        control and status registers.
-
-        The second register range describes the Nexus Port Controller
-        internal trace buffer. The NPC trace buffer is a small memory buffer
-        which stages the nexus trace data for transmission via the Aurora port
-        or to a DDR based trace buffer. In some configurations the NPC trace
-        buffer can be the only trace buffer used.
-
-
-EXAMPLE
-                dcsr-npc {
-                        compatible = "fsl,dcsr-npc";
-                        reg = <0x1000 0x1000 0x1000000 0x8000>;
-                };
-
-=======================================================================
-Nexus Concentrator
-
-This node represents the region of DCSR space allocated to the NXC
-
-PROPERTIES
-
-        - compatible
-        Usage: required
-        Value type: <string>
-        Definition: Must include "fsl,dcsr-nxc"
-
-        - reg
-        Usage: required
-        Value type: <prop-encoded-array>
-        Definition: A standard property.  Specifies the physical address
-        offset and length of the DCSR space registers of the device
-        configuration block.
-
-EXAMPLE
-                dcsr-nxc@2000 {
-                        compatible = "fsl,dcsr-nxc";
-                        reg = <0x2000 0x1000>;
-                };
-=======================================================================
-CoreNet Debug Controller
-
-This node represents the region of DCSR space allocated to
-the CoreNet Debug controller.
-
-PROPERTIES
-
-        - compatible
-        Usage: required
-        Value type: <string>
-        Definition: Must include "fsl,dcsr-corenet"
-
-        - reg
-        Usage: required
-        Value type: <prop-encoded-array>
-        Definition: A standard property.  Specifies the physical address
-        offset and length of the DCSR space registers of the device
-        configuration block.
-        The CoreNet Debug controller occupies two regions in the DCSR space
-        with distinct functionality.
-
-        The first register range describes the CoreNet Debug Controller
-        functionalty to perform transaction and transaction attribute matches.
-
-        The second register range describes the CoreNet Debug Controller
-        functionalty to trigger event notifications and debug traces.
-
-EXAMPLE
-                dcsr-corenet {
-                        compatible = "fsl,dcsr-corenet";
-                        reg = <0x8000 0x1000 0xB0000 0x1000>;
-                };
-
-=======================================================================
-Data Path Debug controller
-
-This node represents the region of DCSR space allocated to
-the DPAA Debug Controller. This controller controls debug configuration
-for the QMAN and FMAN blocks.
-
-PROPERTIES
-
-        - compatible
-        Usage: required
-        Value type: <string>
-        Definition: Must include both an identifier specific to the SoC
-        or Debug IP of the form "fsl,<soc>-dcsr-dpaa" in addition to the
-        generic compatible string "fsl,dcsr-dpaa".
-
-        - reg
-        Usage: required
-        Value type: <prop-encoded-array>
-        Definition: A standard property.  Specifies the physical address
-        offset and length of the DCSR space registers of the device
-        configuration block.
-
-EXAMPLE
-                dcsr-dpaa@9000 {
-                        compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
-                        reg = <0x9000 0x1000>;
-                };
-
-=======================================================================
-OCeaN Debug controller
-
-This node represents the region of DCSR space allocated to
-the OCN Debug Controller.
-
-PROPERTIES
-
-        - compatible
-        Usage: required
-        Value type: <string>
-        Definition: Must include both an identifier specific to the SoC
-        or Debug IP of the form "fsl,<soc>-dcsr-ocn" in addition to the
-        generic compatible string "fsl,dcsr-ocn".
-
-        - reg
-        Usage: required
-        Value type: <prop-encoded-array>
-        Definition: A standard property.  Specifies the physical address
-        offset and length of the DCSR space registers of the device
-        configuration block.
-
-EXAMPLE
-                dcsr-ocn@11000 {
-                        compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
-                        reg = <0x11000 0x1000>;
-                };
-
-=======================================================================
-DDR Controller Debug controller
-
-This node represents the region of DCSR space allocated to
-the OCN Debug Controller.
-
-PROPERTIES
-
-        - compatible
-        Usage: required
-        Value type: <string>
-        Definition: Must include "fsl,dcsr-ddr"
-
-        - dev-handle
-        Usage: required
-        Definition: A phandle to associate this debug node with its
-        component controller.
-
-        - reg
-        Usage: required
-        Value type: <prop-encoded-array>
-        Definition: A standard property.  Specifies the physical address
-        offset and length of the DCSR space registers of the device
-        configuration block.
-
-EXAMPLE
-                dcsr-ddr@12000 {
-                        compatible = "fsl,dcsr-ddr";
-                        dev-handle = <&ddr1>;
-                        reg = <0x12000 0x1000>;
-                };
-
-=======================================================================
-Nexus Aurora Link Controller
-
-This node represents the region of DCSR space allocated to
-the NAL Controller.
-
-PROPERTIES
-
-        - compatible
-        Usage: required
-        Value type: <string>
-        Definition: Must include both an identifier specific to the SoC
-        or Debug IP of the form "fsl,<soc>-dcsr-nal" in addition to the
-        generic compatible string "fsl,dcsr-nal".
-
-        - reg
-        Usage: required
-        Value type: <prop-encoded-array>
-        Definition: A standard property.  Specifies the physical address
-        offset and length of the DCSR space registers of the device
-        configuration block.
-
-EXAMPLE
-                dcsr-nal@18000 {
-                        compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
-                        reg = <0x18000 0x1000>;
-                };
-
-
-=======================================================================
-Run Control and Power Management
-
-This node represents the region of DCSR space allocated to
-the RCPM Debug Controller. This functionlity is limited to the
-control the debug operations of the SoC and cores.
-
-PROPERTIES
-
-        - compatible
-        Usage: required
-        Value type: <string>
-        Definition: Must include both an identifier specific to the SoC
-        or Debug IP of the form "fsl,<soc>-dcsr-rcpm" in addition to the
-        generic compatible string "fsl,dcsr-rcpm".
-
-        - reg
-        Usage: required
-        Value type: <prop-encoded-array>
-        Definition: A standard property.  Specifies the physical address
-        offset and length of the DCSR space registers of the device
-        configuration block.
-
-EXAMPLE
-                dcsr-rcpm@22000 {
-                        compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
-                        reg = <0x22000 0x1000>;
-                };
-
-=======================================================================
-Core Service Bridge Proxy
-
-This node represents the region of DCSR space allocated to
-the Core Service Bridge Proxies.
-There is one Core Service Bridge Proxy device for each CPU in the system.
-This functionlity provides access to the debug operations of the CPU.
-
-PROPERTIES
-
-        - compatible
-        Usage: required
-        Value type: <string>
-        Definition: Must include both an identifier specific to the cpu
-        of the form "fsl,dcsr-<cpu>-sb-proxy" in addition to the
-        generic compatible string "fsl,dcsr-cpu-sb-proxy".
-
-        - cpu-handle
-        Usage: required
-        Definition: A phandle to associate this debug node with its cpu.
-
-        - reg
-        Usage: required
-        Value type: <prop-encoded-array>
-        Definition: A standard property.  Specifies the physical address
-        offset and length of the DCSR space registers of the device
-        configuration block.
-
-EXAMPLE
-                dcsr-cpu-sb-proxy@40000 {
-                        compatible = "fsl,dcsr-e500mc-sb-proxy",
-                                     "fsl,dcsr-cpu-sb-proxy";
-                        cpu-handle = <&cpu0>;
-                        reg = <0x40000 0x1000>;
-                };
-                dcsr-cpu-sb-proxy@41000 {
-                        compatible = "fsl,dcsr-e500mc-sb-proxy",
-                                     "fsl,dcsr-cpu-sb-proxy";
-                        cpu-handle = <&cpu1>;
-                        reg = <0x41000 0x1000>;
-                };
-
-=======================================================================
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt b/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
index d5e370450ac..939a26d541f 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
@@ -12,12 +12,9 @@ Properties:
 - #size-cells : Either one or two, depending on how large each chipselect
                 can be.
 - reg : Offset and length of the register set for the device
-- interrupts: IFC may have one or two interrupts.  If two interrupt
-              specifiers are present, the first is the "common"
-              interrupt (CM_EVTER_STAT), and the second is the NAND
-              interrupt (NAND_EVTER_STAT).  If there is only one,
-              that interrupt reports both types of event.
-
+- interrupts : IFC has two interrupts. The first one is the "common"
+               interrupt(CM_EVTER_STAT), and second is the NAND interrupt
+               (NAND_EVTER_STAT).
 
 - ranges : Each range corresponds to a single chipselect, and covers
            the entire access window as configured.
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt b/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt
deleted file mode 100644
index bc8ded641ab..00000000000
--- a/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt
+++ /dev/null
@@ -1,63 +0,0 @@
-* FSL MPIC Message Registers
-
-This binding specifies what properties must be available in the device tree
-representation of the message register blocks found in some FSL MPIC
-implementations.
-
-Required properties:
-
-    - compatible: Specifies the compatibility list for the message register
-      block.  The type shall be <string-list> and the value shall be of the form
-      "fsl,mpic-v<version>-msgr", where <version> is the version number of
-      the MPIC containing the message registers.
-
-    - reg: Specifies the base physical address(s) and size(s) of the
-      message register block's addressable register space.  The type shall be
-      <prop-encoded-array>.
-
-    - interrupts: Specifies a list of interrupt-specifiers which are available
-      for receiving interrupts. Interrupt-specifier consists of two cells: first
-      cell is interrupt-number and second cell is level-sense. The type shall be
-      <prop-encoded-array>.
-
-Optional properties:
-
-    - mpic-msgr-receive-mask: Specifies what registers in the containing block
-      are allowed to receive interrupts. The value is a bit mask where a set
-      bit at bit 'n' indicates that message register 'n' can receive interrupts.
-      Note that "bit 'n'" is numbered from LSB for PPC hardware. The type shall
-      be <u32>. If not present, then all of the message registers in the block
-      are available.
-
-Aliases:
-
-    An alias should be created for every message register block.  They are not
-    required, though.  However, a particular implementation of this binding
-    may require aliases to be present.  Aliases are of the form
-    'mpic-msgr-block<n>', where <n> is an integer specifying the block's number.
-    Numbers shall start at 0.
-
-Example:
-
-        aliases {
-                mpic-msgr-block0 = &mpic_msgr_block0;
-                mpic-msgr-block1 = &mpic_msgr_block1;
-        };
-
-        mpic_msgr_block0: mpic-msgr-block@41400 {
-                compatible = "fsl,mpic-v3.1-msgr";
-                reg = <0x41400 0x200>;
-                // Message registers 0 and 2 in this block can receive interrupts on
-                // sources 0xb0 and 0xb2, respectively.
-                interrupts = <0xb0 2 0xb2 2>;
-                mpic-msgr-receive-mask = <0x5>;
-        };
-
-        mpic_msgr_block1: mpic-msgr-block@42400 {
-                compatible = "fsl,mpic-v3.1-msgr";
-                reg = <0x42400 0x200>;
-                // Message registers 0 and 2 in this block can receive interrupts on
-                // sources 0xb4 and 0xb6, respectively.
-                interrupts = <0xb4 2 0xb6 2>;
-                mpic-msgr-receive-mask = <0x5>;
-        };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
index dc5744636a5..2cf38bd841f 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
@@ -56,27 +56,7 @@ PROPERTIES
           to the client.  The presence of this property also mandates
           that any initialization related to interrupt sources shall
           be limited to sources explicitly referenced in the device tree.
-
-  - big-endian
-      Usage: optional
-      Value type: <empty>
-          If present the MPIC will be assumed to be big-endian.  Some
-          device-trees omit this property on MPIC nodes even when the MPIC is
-          in fact big-endian, so certain boards override this property.
-
-  - single-cpu-affinity
-      Usage: optional
-      Value type: <empty>
-          If present the MPIC will be assumed to only be able to route
-          non-IPI interrupts to a single CPU at a time (EG: Freescale MPIC).
-
-  - last-interrupt-source
-      Usage: optional
-      Value type: <u32>
-          Some MPICs do not correctly report the number of hardware sources
-          in the global feature registers.  If specified, this field will
-          override the value read from MPIC_GREG_FEATURE_LAST_SRC.
-
+       
 INTERRUPT SPECIFIER DEFINITION
 
   Interrupt specifiers consists of 4 cells encoded as
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
index 5693877ab37..70558c3f368 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
@@ -6,10 +6,8 @@ Required properties:
   etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on
   the parent type.
 
-- reg : It may contain one or two regions. The first region should contain
-  the address and the length of the shared message interrupt register set.
-  The second region should contain the address of aliased MSIIR register for
-  platforms that have such an alias.
+- reg : should contain the address and the length of the shared message
+  interrupt register set.
 
 - msi-available-ranges: use <start count> style section to define which
   msi interrupt can be used in the 256 msi interrupts. This property is
@@ -27,16 +25,6 @@ Required properties:
   are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed
   to MPIC.
 
-Optional properties:
-- msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register
-  is used for MSI messaging.  The address of MSIIR in PCI address space is
-  the MSI message address.
-
-  This property may be used in virtualized environments where the hypervisor
-  has created an alternate mapping for the MSIR block.  See below for an
-  explanation.
-
-
 Example:
         msi@41600 {
                 compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
@@ -53,35 +41,3 @@ Example:
                         0xe7 0>;
                 interrupt-parent = <&mpic>;
         };
-
-The Freescale hypervisor and msi-address-64
--------------------------------------------
-Normally, PCI devices have access to all of CCSR via an ATMU mapping.  The
-Freescale MSI driver calculates the address of MSIIR (in the MSI register
-block) and sets that address as the MSI message address.
-
-In a virtualized environment, the hypervisor may need to create an IOMMU
-mapping for MSIIR.  The Freescale ePAPR hypervisor has this requirement
-because of hardware limitations of the Peripheral Access Management Unit
-(PAMU), which is currently the only IOMMU that the hypervisor supports.
-The ATMU is programmed with the guest physical address, and the PAMU
-intercepts transactions and reroutes them to the true physical address.
-
-In the PAMU, each PCI controller is given only one primary window.  The
-PAMU restricts DMA operations so that they can only occur within a window.
-Because PCI devices must be able to DMA to memory, the primary window must
-be used to cover all of the guest's memory space.
-
-PAMU primary windows can be divided into 256 subwindows, and each
-subwindow can have its own address mapping ("guest physical" to "true
-physical").  However, each subwindow has to have the same alignment, which
-means they cannot be located at just any address.  Because of these
-restrictions, it is usually impossible to create a 4KB subwindow that
-covers MSIIR where it's normally located.
-
-Therefore, the hypervisor has to create a subwindow inside the same
-primary window used for memory, but mapped to the MSIR block (where MSIIR
-lives).  The first subwindow after the end of guest memory is used for
-this.  The address specified in the msi-address-64 property is the PCI
-address of MSIIR.  The hypervisor configures the PAMU to map that address to
-the true physical address of MSIIR.
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/raideng.txt b/Documentation/devicetree/bindings/powerpc/fsl/raideng.txt
deleted file mode 100644
index 4ad29b9ac2a..00000000000
--- a/Documentation/devicetree/bindings/powerpc/fsl/raideng.txt
+++ /dev/null
@@ -1,81 +0,0 @@
-* Freescale 85xx RAID Engine nodes
-
-RAID Engine nodes are defined to describe on-chip RAID accelerators.  Each RAID
-Engine should have a separate node.
-
-Supported chips:
-P5020, P5040
-
-Required properties:
-
-- compatible:   Should contain "fsl,raideng-v1.0" as the value
-                This identifies RAID Engine block. 1 in 1.0 represents
-                major number whereas 0 represents minor number. The
-                version matches the hardware IP version.
-- reg:          offset and length of the register set for the device
-- ranges:       standard ranges property specifying the translation
-                between child address space and parent address space
-
-Example:
-        /* P5020 */
-        raideng: raideng@320000 {
-                compatible = "fsl,raideng-v1.0";
-                #address-cells = <1>;
-                #size-cells = <1>;
-                reg     = <0x320000 0x10000>;
-                ranges  = <0 0x320000 0x10000>;
-        };
-
-
-There must be a sub-node for each job queue present in RAID Engine
-This node must be a sub-node of the main RAID Engine node
-
-- compatible:   Should contain "fsl,raideng-v1.0-job-queue" as the value
-                This identifies the job queue interface
-- reg:          offset and length of the register set for job queue
-- ranges:       standard ranges property specifying the translation
-                between child address space and parent address space
-
-Example:
-        /* P5020 */
-        raideng_jq0@1000 {
-                compatible = "fsl,raideng-v1.0-job-queue";
-                reg        = <0x1000 0x1000>;
-                ranges     = <0x0 0x1000 0x1000>;
-        };
-
-
-There must be a sub-node for each job ring present in RAID Engine
-This node must be a sub-node of job queue node
-
-- compatible:   Must contain "fsl,raideng-v1.0-job-ring" as the value
-                This identifies job ring. Should contain either
-                "fsl,raideng-v1.0-hp-ring" or "fsl,raideng-v1.0-lp-ring"
-                depending upon whether ring has high or low priority
-- reg:          offset and length of the register set for job ring
-- interrupts:   interrupt mapping for job ring IRQ
-
-Optional property:
-
-- fsl,liodn:    Specifies the LIODN to be used for Job Ring. This
-                property is normally set by firmware. Value
-                is of 12-bits which is the LIODN number for this JR.
-                This property is used by the IOMMU (PAMU) to distinquish
-                transactions from this JR and than be able to do address
-                translation & protection accordingly.
-
-Example:
-        /* P5020 */
-        raideng_jq0@1000 {
-                compatible = "fsl,raideng-v1.0-job-queue";
-                reg        = <0x1000 0x1000>;
-                ranges     = <0x0 0x1000 0x1000>;
-
-                raideng_jr0: jr@0 {
-                        compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-hp-ring";
-                        reg        = <0x0 0x400>;
-                        interrupts = <139 2 0 0>;
-                        interrupt-parent = <&mpic>;
-                        fsl,liodn = <0x41>;
-                };
-        };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/srio-rmu.txt b/Documentation/devicetree/bindings/powerpc/fsl/srio-rmu.txt
deleted file mode 100644
index b9a8a2bcfae..00000000000
--- a/Documentation/devicetree/bindings/powerpc/fsl/srio-rmu.txt
+++ /dev/null
@@ -1,163 +0,0 @@
-Message unit node:
-
-For SRIO controllers that implement the message unit as part of the controller
-this node is required.  For devices with RMAN this node should NOT exist.  The
-node is composed of three types of sub-nodes ("fsl-srio-msg-unit",
-"fsl-srio-dbell-unit" and "fsl-srio-port-write-unit").
-
-See srio.txt for more details about generic SRIO controller details.
-
-   - compatible
-        Usage: required
-        Value type: <string>
-        Definition: Must include "fsl,srio-rmu-vX.Y", "fsl,srio-rmu".
-
-        The version X.Y should match the general SRIO controller's IP Block
-        revision register's Major(X) and Minor (Y) value.
-
-   - reg
-        Usage: required
-        Value type: <prop-encoded-array>
-        Definition: A standard property.  Specifies the physical address and
-                length of the SRIO configuration registers for message units
-                and doorbell units.
-
-   - fsl,liodn
-        Usage: optional-but-recommended (for devices with PAMU)
-        Value type: <prop-encoded-array>
-        Definition: The logical I/O device number for the PAMU (IOMMU) to be
-                correctly configured for SRIO accesses.  The property should
-                not exist on devices that do not support PAMU.
-
-                The LIODN value is associated with all RMU transactions
-                (msg-unit, doorbell, port-write).
-
-Sub-Nodes for RMU:  The RMU node is composed of multiple sub-nodes that
-correspond to the actual sub-controllers in the RMU.  The manual for a given
-SoC will detail which and how many of these sub-controllers are implemented.
-
-Message Unit:
-
-   - compatible
-        Usage: required
-        Value type: <string>
-        Definition: Must include "fsl,srio-msg-unit-vX.Y", "fsl,srio-msg-unit".
-
-        The version X.Y should match the general SRIO controller's IP Block
-        revision register's Major(X) and Minor (Y) value.
-
-   - reg
-        Usage: required
-        Value type: <prop-encoded-array>
-        Definition: A standard property.  Specifies the physical address and
-                length of the SRIO configuration registers for message units
-                and doorbell units.
-
-   - interrupts
-        Usage: required
-        Value type: <prop_encoded-array>
-        Definition:  Specifies the interrupts generated by this device.  The
-                value of the interrupts property consists of one interrupt
-                specifier. The format of the specifier is defined by the
-                binding document describing the node's interrupt parent.
-
-                A pair of IRQs are specified in this property.  The first
-                element is associated with the transmit (TX) interrupt and the
-                second element is associated with the receive (RX) interrupt.
-
-Doorbell Unit:
-
-   - compatible
-        Usage: required
-        Value type: <string>
-        Definition: Must include:
-                "fsl,srio-dbell-unit-vX.Y", "fsl,srio-dbell-unit"
-
-        The version X.Y should match the general SRIO controller's IP Block
-        revision register's Major(X) and Minor (Y) value.
-
-   - reg
-        Usage: required
-        Value type: <prop-encoded-array>
-        Definition: A standard property.  Specifies the physical address and
-                length of the SRIO configuration registers for message units
-                and doorbell units.
-
-   - interrupts
-        Usage: required
-        Value type: <prop_encoded-array>
-        Definition:  Specifies the interrupts generated by this device.  The
-                value of the interrupts property consists of one interrupt
-                specifier. The format of the specifier is defined by the
-                binding document describing the node's interrupt parent.
-
-                A pair of IRQs are specified in this property.  The first
-                element is associated with the transmit (TX) interrupt and the
-                second element is associated with the receive (RX) interrupt.
-
-Port-Write Unit:
-
-   - compatible
-        Usage: required
-        Value type: <string>
-        Definition: Must include:
-                 "fsl,srio-port-write-unit-vX.Y", "fsl,srio-port-write-unit"
-
-        The version X.Y should match the general SRIO controller's IP Block
-        revision register's Major(X) and Minor (Y) value.
-
-   - reg
-        Usage: required
-        Value type: <prop-encoded-array>
-        Definition: A standard property.  Specifies the physical address and
-                length of the SRIO configuration registers for message units
-                and doorbell units.
-
-   - interrupts
-        Usage: required
-        Value type: <prop_encoded-array>
-        Definition:  Specifies the interrupts generated by this device.  The
-                value of the interrupts property consists of one interrupt
-                specifier. The format of the specifier is defined by the
-                binding document describing the node's interrupt parent.
-
-                A single IRQ that handles port-write conditions is
-                specified by this property.  (Typically shared with error).
-
-   Note: All other standard properties (see the ePAPR) are allowed
-   but are optional.
-
-Example:
-        rmu: rmu@d3000 {
-                compatible = "fsl,srio-rmu";
-                reg = <0xd3000 0x400>;
-                ranges = <0x0 0xd3000 0x400>;
-                fsl,liodn = <0xc8>;
-
-                message-unit@0 {
-                        compatible = "fsl,srio-msg-unit";
-                        reg = <0x0 0x100>;
-                        interrupts = <
-                                60 2 0 0  /* msg1_tx_irq */
-                                61 2 0 0>;/* msg1_rx_irq */
-                };
-                message-unit@100 {
-                        compatible = "fsl,srio-msg-unit";
-                        reg = <0x100 0x100>;
-                        interrupts = <
-                                62 2 0 0  /* msg2_tx_irq */
-                                63 2 0 0>;/* msg2_rx_irq */
-                };
-                doorbell-unit@400 {
-                        compatible = "fsl,srio-dbell-unit";
-                        reg = <0x400 0x80>;
-                        interrupts = <
-                                56 2 0 0  /* bell_outb_irq */
-                                57 2 0 0>;/* bell_inb_irq */
-                };
-                port-write-unit@4e0 {
-                        compatible = "fsl,srio-port-write-unit";
-                        reg = <0x4e0 0x20>;
-                        interrupts = <16 2 1 11>;
-                };
-        };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/srio.txt b/Documentation/devicetree/bindings/powerpc/fsl/srio.txt
deleted file mode 100644
index b039bcbee13..00000000000
--- a/Documentation/devicetree/bindings/powerpc/fsl/srio.txt
+++ /dev/null
@@ -1,103 +0,0 @@
-* Freescale Serial RapidIO (SRIO) Controller
-
-RapidIO port node:
-Properties:
-   - compatible
-        Usage: required
-        Value type: <string>
-        Definition: Must include "fsl,srio" for IP blocks with IP Block
-        Revision Register (SRIO IPBRR1) Major ID equal to 0x01c0.
-
-        Optionally, a compatiable string of "fsl,srio-vX.Y" where X is Major
-        version in IP Block Revision Register and Y is Minor version.  If this
-        compatiable is provided it should be ordered before "fsl,srio".
-
-   - reg
-        Usage: required
-        Value type: <prop-encoded-array>
-        Definition: A standard property.  Specifies the physical address and
-                length of the SRIO configuration registers.  The size should
-                be set to 0x11000.
-
-   - interrupts
-        Usage: required
-        Value type: <prop_encoded-array>
-        Definition:  Specifies the interrupts generated by this device.  The
-                value of the interrupts property consists of one interrupt
-                specifier. The format of the specifier is defined by the
-                binding document describing the node's interrupt parent.
-
-                A single IRQ that handles error conditions is specified by this
-                property.  (Typically shared with port-write).
-
-   - fsl,srio-rmu-handle:
-        Usage: required if rmu node is defined
-        Value type: <phandle>
-        Definition: A single <phandle> value that points to the RMU.
-        (See srio-rmu.txt for more details on RMU node binding)
-
-Port Child Nodes:  There should a port child node for each port that exists in
-the controller.  The ports are numbered starting at one (1) and should have
-the following properties:
-
-   - cell-index
-        Usage: required
-        Value type: <u32>
-        Definition: A standard property.  Matches the port id.
-
-   - ranges
-        Usage: required if local access windows preset
-        Value type: <prop-encoded-array>
-        Definition: A standard property. Utilized to describe the memory mapped
-                IO space utilized by the controller.  This corresponds to the
-                setting of the local access windows that are targeted to this
-                SRIO port.
-
-   - fsl,liodn
-        Usage: optional-but-recommended (for devices with PAMU)
-        Value type: <prop-encoded-array>
-        Definition: The logical I/O device number for the PAMU (IOMMU) to be
-                correctly configured for SRIO accesses.  The property should
-                not exist on devices that do not support PAMU.
-
-                For HW (ie, the P4080) that only supports a LIODN for both
-                memory and maintenance transactions then a single LIODN is
-                represented in the property for both transactions.
-
-                For HW (ie, the P304x/P5020, etc) that supports an LIODN for
-                memory transactions and a unique LIODN for maintenance
-                transactions then a pair of LIODNs are represented in the
-                property.  Within the pair, the first element represents the
-                LIODN associated with memory transactions and the second element
-                represents the LIODN associated with maintenance transactions
-                for the port.
-
-Note: All other standard properties (see ePAPR) are allowed but are optional.
-
-Example:
-
-        rapidio: rapidio@ffe0c0000 {
-                #address-cells = <2>;
-                #size-cells = <2>;
-                reg = <0xf 0xfe0c0000 0 0x11000>;
-                compatible = "fsl,srio";
-                interrupts = <16 2 1 11>; /* err_irq */
-                fsl,srio-rmu-handle = <&rmu>;
-                ranges;
-
-                port1 {
-                        cell-index = <1>;
-                        #address-cells = <2>;
-                        #size-cells = <2>;
-                        fsl,liodn = <34>;
-                        ranges = <0 0 0xc 0x20000000 0 0x10000000>;
-                };
-
-                port2 {
-                        cell-index = <2>;
-                        #address-cells = <2>;
-                        #size-cells = <2>;
-                        fsl,liodn = <48>;
-                        ranges = <0 0 0xc 0x30000000 0 0x10000000>;
-                };
-        };
diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.txt b/Documentation/devicetree/bindings/pwm/imx-pwm.txt
deleted file mode 100644
index 8522bfbccfd..00000000000
--- a/Documentation/devicetree/bindings/pwm/imx-pwm.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-Freescale i.MX PWM controller
-
-Required properties:
-- compatible: should be "fsl,<soc>-pwm"
-- reg: physical base address and length of the controller's registers
-- #pwm-cells: should be 2.  The first cell specifies the per-chip index
-  of the PWM to use and the second cell is the period in nanoseconds.
-- interrupts: The interrupt for the pwm controller
-
-Example:
-
-pwm1: pwm@53fb4000 {
-        #pwm-cells = <2>;
-        compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
-        reg = <0x53fb4000 0x4000>;
-        interrupts = <61>;
-};
diff --git a/Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt b/Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt
deleted file mode 100644
index cfe1db3bb6e..00000000000
--- a/Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-LPC32XX PWM controller
-
-Required properties:
-- compatible: should be "nxp,lpc3220-pwm"
-- reg: physical base address and length of the controller's registers
-
-Examples:
-
-pwm@0x4005C000 {
-        compatible = "nxp,lpc3220-pwm";
-        reg = <0x4005C000 0x8>;
-};
diff --git a/Documentation/devicetree/bindings/pwm/mxs-pwm.txt b/Documentation/devicetree/bindings/pwm/mxs-pwm.txt
deleted file mode 100644
index 9e3f8f1d46a..00000000000
--- a/Documentation/devicetree/bindings/pwm/mxs-pwm.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-Freescale MXS PWM controller
-
-Required properties:
-- compatible: should be "fsl,imx23-pwm"
-- reg: physical base address and length of the controller's registers
-- #pwm-cells: should be 2.  The first cell specifies the per-chip index
-  of the PWM to use and the second cell is the period in nanoseconds.
-- fsl,pwm-number: the number of PWM devices
-
-Example:
-
-pwm: pwm@80064000 {
-        compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
-        reg = <0x80064000 0x2000>;
-        #pwm-cells = <2>;
-        fsl,pwm-number = <8>;
-};
diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
deleted file mode 100644
index 01438ecd662..00000000000
--- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-Tegra SoC PWFM controller
-
-Required properties:
-- compatible: should be one of:
-  - "nvidia,tegra20-pwm"
-  - "nvidia,tegra30-pwm"
-- reg: physical base address and length of the controller's registers
-- #pwm-cells: On Tegra the number of cells used to specify a PWM is 2. The
-  first cell specifies the per-chip index of the PWM to use and the second
-  cell is the period in nanoseconds.
-
-Example:
-
-        pwm: pwm@7000a000 {
-                compatible = "nvidia,tegra20-pwm";
-                reg = <0x7000a000 0x100>;
-                #pwm-cells = <2>;
-        };
diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt
deleted file mode 100644
index 131e8c11d26..00000000000
--- a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-TI SOC ECAP based APWM controller
-
-Required properties:
-- compatible: Must be "ti,am33xx-ecap"
-- #pwm-cells: Should be 3. Number of cells being used to specify PWM property.
-  First cell specifies the per-chip index of the PWM to use, the second
-  cell is the period in nanoseconds and bit 0 in the third cell is used to
-  encode the polarity of PWM output. Set bit 0 of the third in PWM specifier
-  to 1 for inverse polarity & set to 0 for normal polarity.
-- reg: physical base address and size of the registers map.
-
-Optional properties:
-- ti,hwmods: Name of the hwmod associated to the ECAP:
-  "ecap<x>", <x> being the 0-based instance number from the HW spec
-
-Example:
-
-ecap0: ecap@0 {
-        compatible = "ti,am33xx-ecap";
-        #pwm-cells = <3>;
-        reg = <0x48300100 0x80>;
-        ti,hwmods = "ecap0";
-};
diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
deleted file mode 100644
index 4fc7079d822..00000000000
--- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-TI SOC EHRPWM based PWM controller
-
-Required properties:
-- compatible : Must be "ti,am33xx-ehrpwm"
-- #pwm-cells: Should be 3. Number of cells being used to specify PWM property.
-  First cell specifies the per-chip index of the PWM to use, the second
-  cell is the period in nanoseconds and bit 0 in the third cell is used to
-  encode the polarity of PWM output. Set bit 0 of the third in PWM specifier
-  to 1 for inverse polarity & set to 0 for normal polarity.
-- reg: physical base address and size of the registers map.
-
-Optional properties:
-- ti,hwmods: Name of the hwmod associated to the EHRPWM:
-  "ehrpwm<x>", <x> being the 0-based instance number from the HW spec
-
-Example:
-
-ehrpwm0: ehrpwm@0 {
-        compatible = "ti,am33xx-ehrpwm";
-        #pwm-cells = <3>;
-        reg = <0x48300200 0x100>;
-        ti,hwmods = "ehrpwm0";
-};
diff --git a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt
deleted file mode 100644
index f7eae77f835..00000000000
--- a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-TI SOC based PWM Subsystem
-
-Required properties:
-- compatible: Must be "ti,am33xx-pwmss";
-- reg: physical base address and size of the registers map.
-- address-cells: Specify the number of u32 entries needed in child nodes.
-                  Should set to 1.
-- size-cells: specify number of u32 entries needed to specify child nodes size
-                in reg property. Should set to 1.
-- ranges: describes the address mapping of a memory-mapped bus. Should set to
-           physical address map of child's base address, physical address within
-           parent's address  space and length of the address map. For am33xx,
-           3 set of child register maps present, ECAP register space, EQEP
-           register space, EHRPWM register space.
-
-Also child nodes should also populated under PWMSS DT node.
-
-Example:
-pwmss0: pwmss@48300000 {
-        compatible = "ti,am33xx-pwmss";
-        reg = <0x48300000 0x10>;
-        ti,hwmods = "epwmss0";
-        #address-cells = <1>;
-        #size-cells = <1>;
-        status = "disabled";
-        ranges = <0x48300100 0x48300100 0x80   /* ECAP */
-                  0x48300180 0x48300180 0x80   /* EQEP */
-                  0x48300200 0x48300200 0x80>; /* EHRPWM */
-
-        /* child nodes go here */
-};
diff --git a/Documentation/devicetree/bindings/pwm/pwm.txt b/Documentation/devicetree/bindings/pwm/pwm.txt
deleted file mode 100644
index 06e67247859..00000000000
--- a/Documentation/devicetree/bindings/pwm/pwm.txt
+++ /dev/null
@@ -1,68 +0,0 @@
-Specifying PWM information for devices
-======================================
-
-1) PWM user nodes
------------------
-
-PWM users should specify a list of PWM devices that they want to use
-with a property containing a 'pwm-list':
-
-        pwm-list ::= <single-pwm> [pwm-list]
-        single-pwm ::= <pwm-phandle> <pwm-specifier>
-        pwm-phandle : phandle to PWM controller node
-        pwm-specifier : array of #pwm-cells specifying the given PWM
-                        (controller specific)
-
-PWM properties should be named "pwms". The exact meaning of each pwms
-property must be documented in the device tree binding for each device.
-An optional property "pwm-names" may contain a list of strings to label
-each of the PWM devices listed in the "pwms" property. If no "pwm-names"
-property is given, the name of the user node will be used as fallback.
-
-Drivers for devices that use more than a single PWM device can use the
-"pwm-names" property to map the name of the PWM device requested by the
-pwm_get() call to an index into the list given by the "pwms" property.
-
-The following example could be used to describe a PWM-based backlight
-device:
-
-        pwm: pwm {
-                #pwm-cells = <2>;
-        };
-
-        [...]
-
-        bl: backlight {
-                pwms = <&pwm 0 5000000>;
-                pwm-names = "backlight";
-        };
-
-Note that in the example above, specifying the "pwm-names" is redundant
-because the name "backlight" would be used as fallback anyway.
-
-pwm-specifier typically encodes the chip-relative PWM number and the PWM
-period in nanoseconds.
-
-Optionally, the pwm-specifier can encode a number of flags in a third cell:
-- bit 0: PWM signal polarity (0: normal polarity, 1: inverse polarity)
-
-Example with optional PWM specifier for inverse polarity
-
-        bl: backlight {
-                pwms = <&pwm 0 5000000 1>;
-                pwm-names = "backlight";
-        };
-
-2) PWM controller nodes
------------------------
-
-PWM controller nodes must specify the number of cells used for the
-specifier using the '#pwm-cells' property.
-
-An example PWM controller might look like this:
-
-        pwm: pwm@7000a000 {
-                compatible = "nvidia,tegra20-pwm";
-                reg = <0x7000a000 0x100>;
-                #pwm-cells = <2>;
-        };
diff --git a/Documentation/devicetree/bindings/pwm/spear-pwm.txt b/Documentation/devicetree/bindings/pwm/spear-pwm.txt
deleted file mode 100644
index 3ac779d8338..00000000000
--- a/Documentation/devicetree/bindings/pwm/spear-pwm.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-== ST SPEAr SoC PWM controller ==
-
-Required properties:
-- compatible: should be one of:
-  - "st,spear320-pwm"
-  - "st,spear1340-pwm"
-- reg: physical base address and length of the controller's registers
-- #pwm-cells: number of cells used to specify PWM which is fixed to 2 on
-  SPEAr. The first cell specifies the per-chip index of the PWM to use and
-  the second cell is the period in nanoseconds.
-
-Example:
-
-        pwm: pwm@a8000000 {
-            compatible ="st,spear320-pwm";
-            reg = <0xa8000000 0x1000>;
-            #pwm-cells = <2>;
-        };
diff --git a/Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt b/Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt
deleted file mode 100644
index 2943ee5fce0..00000000000
--- a/Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-Texas Instruments TWL series PWM drivers
-
-Supported PWMs:
-On TWL4030 series: PWM1 and PWM2
-On TWL6030 series: PWM0 and PWM1
-
-Required properties:
-- compatible: "ti,twl4030-pwm" or "ti,twl6030-pwm"
-- #pwm-cells: should be 2.  The first cell specifies the per-chip index
-  of the PWM to use and the second cell is the period in nanoseconds.
-
-Example:
-
-twl_pwm: pwm {
-        compatible = "ti,twl6030-pwm";
-        #pwm-cells = <2>;
-};
diff --git a/Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt b/Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt
deleted file mode 100644
index cb64f3acc10..00000000000
--- a/Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-Texas Instruments TWL series PWM drivers connected to LED terminals
-
-Supported PWMs:
-On TWL4030 series: PWMA and PWMB (connected to LEDA and LEDB terminals)
-On TWL6030 series: LED PWM (mainly used as charging indicator LED)
-
-Required properties:
-- compatible: "ti,twl4030-pwmled" or "ti,twl6030-pwmled"
-- #pwm-cells: should be 2.  The first cell specifies the per-chip index
-  of the PWM to use and the second cell is the period in nanoseconds.
-
-Example:
-
-twl_pwmled: pwmled {
-        compatible = "ti,twl6030-pwmled";
-        #pwm-cells = <2>;
-};
diff --git a/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt b/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt
deleted file mode 100644
index bcc63678a9a..00000000000
--- a/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-VIA/Wondermedia VT8500/WM8xxx series SoC PWM controller
-
-Required properties:
-- compatible: should be "via,vt8500-pwm"
-- reg: physical base address and length of the controller's registers
-- #pwm-cells: should be 2.  The first cell specifies the per-chip index
-  of the PWM to use and the second cell is the period in nanoseconds.
-- clocks: phandle to the PWM source clock
-
-Example:
-
-pwm1: pwm@d8220000 {
-        #pwm-cells = <2>;
-        compatible = "via,vt8500-pwm";
-        reg = <0xd8220000 0x1000>;
-        clocks = <&clkpwm>;
-};
diff --git a/Documentation/devicetree/bindings/regulator/88pm860x.txt b/Documentation/devicetree/bindings/regulator/88pm860x.txt
deleted file mode 100644
index 1267b3e1a2c..00000000000
--- a/Documentation/devicetree/bindings/regulator/88pm860x.txt
+++ /dev/null
@@ -1,30 +0,0 @@
-Marvell 88PM860x regulator
-
-Required properties:
-- compatible: "marvell,88pm860x"
-- reg: I2C slave address
-- regulators: A node that houses a sub-node for each regulator within the
-  device. Each sub-node is identified using the regulator-compatible
-  property, with valid values listed below.
-
-Example:
-
-        pmic: 88pm860x@34 {
-                compatible = "marvell,88pm860x";
-                reg = <0x34>;
-
-                regulators {
-                        BUCK1 {
-                                regulator-min-microvolt = <1000000>;
-                                regulator-max-microvolt = <1500000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-                        BUCK3 {
-                                regulator-min-microvolt = <1000000>;
-                                regulator-max-microvolt = <3000000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-                };
-        };
diff --git a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
deleted file mode 100644
index 357758cb6e9..00000000000
--- a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-Anatop Voltage regulators
-
-Required properties:
-- compatible: Must be "fsl,anatop-regulator"
-- anatop-reg-offset: Anatop MFD register offset
-- anatop-vol-bit-shift: Bit shift for the register
-- anatop-vol-bit-width: Number of bits used in the register
-- anatop-min-bit-val: Minimum value of this register
-- anatop-min-voltage: Minimum voltage of this regulator
-- anatop-max-voltage: Maximum voltage of this regulator
-
-Any property defined as part of the core regulator
-binding, defined in regulator.txt, can also be used.
-
-Example:
-
-        regulator-vddpu {
-                compatible = "fsl,anatop-regulator";
-                regulator-name = "vddpu";
-                regulator-min-microvolt = <725000>;
-                regulator-max-microvolt = <1300000>;
-                regulator-always-on;
-                anatop-reg-offset = <0x140>;
-                anatop-vol-bit-shift = <9>;
-                anatop-vol-bit-width = <5>;
-                anatop-min-bit-val = <1>;
-                anatop-min-voltage = <725000>;
-                anatop-max-voltage = <1300000>;
-        };
diff --git a/Documentation/devicetree/bindings/regulator/fixed-regulator.txt b/Documentation/devicetree/bindings/regulator/fixed-regulator.txt
deleted file mode 100644
index 4fae41d5479..00000000000
--- a/Documentation/devicetree/bindings/regulator/fixed-regulator.txt
+++ /dev/null
@@ -1,34 +0,0 @@
-Fixed Voltage regulators
-
-Required properties:
-- compatible: Must be "regulator-fixed";
-
-Optional properties:
-- gpio: gpio to use for enable control
-- startup-delay-us: startup time in microseconds
-- enable-active-high: Polarity of GPIO is Active high
-If this property is missing, the default assumed is Active low.
-- gpio-open-drain: GPIO is open drain type.
-  If this property is missing then default assumption is false.
--vin-supply: Input supply name.
-
-Any property defined as part of the core regulator
-binding, defined in regulator.txt, can also be used.
-However a fixed voltage regulator is expected to have the
-regulator-min-microvolt and regulator-max-microvolt
-to be the same.
-
-Example:
-
-        abc: fixedregulator@0 {
-                compatible = "regulator-fixed";
-                regulator-name = "fixed-supply";
-                regulator-min-microvolt = <1800000>;
-                regulator-max-microvolt = <1800000>;
-                gpio = <&gpio1 16 0>;
-                startup-delay-us = <70000>;
-                enable-active-high;
-                regulator-boot-on;
-                gpio-open-drain;
-                vin-supply = <&parent_reg>;
-        };
diff --git a/Documentation/devicetree/bindings/regulator/gpio-regulator.txt b/Documentation/devicetree/bindings/regulator/gpio-regulator.txt
deleted file mode 100644
index 63c659800c0..00000000000
--- a/Documentation/devicetree/bindings/regulator/gpio-regulator.txt
+++ /dev/null
@@ -1,37 +0,0 @@
-GPIO controlled regulators
-
-Required properties:
-- compatible            : Must be "regulator-gpio".
-- states                : Selection of available voltages and GPIO configs.
-                          if there are no states, then use a fixed regulator
-
-Optional properties:
-- enable-gpio           : GPIO to use to enable/disable the regulator.
-- gpios                 : GPIO group used to control voltage.
-- startup-delay-us      : Startup time in microseconds.
-- enable-active-high    : Polarity of GPIO is active high (default is low).
-
-Any property defined as part of the core regulator binding defined in
-regulator.txt can also be used.
-
-Example:
-
-        mmciv: gpio-regulator {
-                compatible = "regulator-gpio";
-
-                regulator-name = "mmci-gpio-supply";
-                regulator-min-microvolt = <1800000>;
-                regulator-max-microvolt = <2600000>;
-                regulator-boot-on;
-
-                enable-gpio = <&gpio0 23 0x4>;
-                gpios = <&gpio0 24 0x4
-                         &gpio0 25 0x4>;
-                states = <1800000 0x3
-                          2200000 0x2
-                          2600000 0x1
-                          2900000 0x0>;
-
-                startup-delay-us = <100000>;
-                enable-active-high;
-        };
diff --git a/Documentation/devicetree/bindings/regulator/max8907.txt b/Documentation/devicetree/bindings/regulator/max8907.txt
deleted file mode 100644
index 371eccd1cd6..00000000000
--- a/Documentation/devicetree/bindings/regulator/max8907.txt
+++ /dev/null
@@ -1,69 +0,0 @@
-MAX8907 regulator
-
-Required properties:
-- compatible: "maxim,max8907"
-- reg: I2C slave address
-- interrupts: The interrupt output of the controller
-- mbatt-supply: The input supply for MBATT, BBAT, SDBY, VRTC.
-- in-v1-supply: The input supply for SD1.
-- in-v2-supply: The input supply for SD2.
-- in-v3-supply: The input supply for SD3.
-- in1-supply: The input supply for LDO1.
-...
-- in20-supply: The input supply for LDO20.
-- regulators: A node that houses a sub-node for each regulator within the
-  device. Each sub-node is identified using the node's name (or the deprecated
-  regulator-compatible property if present), with valid values listed below.
-  The content of each sub-node is defined by the standard binding for
-  regulators; see regulator.txt.
-
-Optional properties:
-- maxim,system-power-controller: Boolean property indicating that the PMIC
-  controls the overall system power.
-
-The valid names for regulators are:
-
-  sd1, sd2, sd3, ldo1, ldo2, ldo3, ldo4, ldo5, ldo6, ldo7, ldo8, ldo9, ldo10,
-  ldo11, ldo12, ldo13, ldo14, ldo15, ldo16, ldo17, ldo18, ldo19, ldo20, out5v,
-  out33v, bbat, sdby, vrtc.
-
-Example:
-
-                max8907@3c {
-                        compatible = "maxim,max8907";
-                        reg = <0x3c>;
-                        interrupts = <0 86 0x4>;
-
-                        maxim,system-power-controller;
-
-                        mbatt-supply = <&some_reg>;
-                        in-v1-supply = <&mbatt_reg>;
-                        ...
-                        in1-supply = <&mbatt_reg>;
-                        ...
-
-                        regulators {
-                                mbatt_reg: mbatt {
-                                        regulator-name = "vbat_pmu";
-                                        regulator-min-microvolt = <5000000>;
-                                        regulator-max-microvolt = <5000000>;
-                                        regulator-always-on;
-                                };
-
-                                sd1 {
-                                        regulator-name = "nvvdd_sv1,vdd_cpu_pmu";
-                                        regulator-min-microvolt = <1000000>;
-                                        regulator-max-microvolt = <1000000>;
-                                        regulator-always-on;
-                                };
-
-                                sd2 {
-                                        regulator-name = "nvvdd_sv2,vdd_core";
-                                        regulator-min-microvolt = <1200000>;
-                                        regulator-max-microvolt = <1200000>;
-                                        regulator-always-on;
-                                };
-...
-                        };
-                };
-        };
diff --git a/Documentation/devicetree/bindings/regulator/max8925-regulator.txt b/Documentation/devicetree/bindings/regulator/max8925-regulator.txt
deleted file mode 100644
index 0057695aae8..00000000000
--- a/Documentation/devicetree/bindings/regulator/max8925-regulator.txt
+++ /dev/null
@@ -1,40 +0,0 @@
-Max8925 Voltage regulators
-
-Required nodes:
--nodes:
-  - SDV1 for SDV SDV1
-  - SDV2 for SDV SDV2
-  - SDV3 for SDV SDV3
-  - LDO1 for LDO LDO1
-  - LDO2 for LDO LDO2
-  - LDO3 for LDO LDO3
-  - LDO4 for LDO LDO4
-  - LDO5 for LDO LDO5
-  - LDO6 for LDO LDO6
-  - LDO7 for LDO LDO7
-  - LDO8 for LDO LDO8
-  - LDO9 for LDO LDO9
-  - LDO10 for LDO LDO10
-  - LDO11 for LDO LDO11
-  - LDO12 for LDO LDO12
-  - LDO13 for LDO LDO13
-  - LDO14 for LDO LDO14
-  - LDO15 for LDO LDO15
-  - LDO16 for LDO LDO16
-  - LDO17 for LDO LDO17
-  - LDO18 for LDO LDO18
-  - LDO19 for LDO LDO19
-  - LDO20 for LDO LDO20
-
-Optional properties:
-- Any optional property defined in bindings/regulator/regulator.txt
-
-Example:
-
-        SDV1 {
-                regulator-min-microvolt = <637500>;
-                regulator-max-microvolt = <1425000>;
-                regulator-boot-on;
-                regulator-always-on;
-        };
-
diff --git a/Documentation/devicetree/bindings/regulator/max8997-regulator.txt b/Documentation/devicetree/bindings/regulator/max8997-regulator.txt
deleted file mode 100644
index 9fd69a18b0b..00000000000
--- a/Documentation/devicetree/bindings/regulator/max8997-regulator.txt
+++ /dev/null
@@ -1,146 +0,0 @@
-* Maxim MAX8997 Voltage and Current Regulator
-
-The Maxim MAX8997 is a multi-function device which includes volatage and
-current regulators, rtc, charger controller and other sub-blocks. It is
-interfaced to the host controller using a i2c interface. Each sub-block is
-addressed by the host system using different i2c slave address. This document
-describes the bindings for 'pmic' sub-block of max8997.
-
-Required properties:
-- compatible: Should be "maxim,max8997-pmic".
-- reg: Specifies the i2c slave address of the pmic block. It should be 0x66.
-
-- max8997,pmic-buck1-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
-  units for buck1 when changing voltage using gpio dvs. Refer to [1] below
-  for additional information.
-
-- max8997,pmic-buck2-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
-  units for buck2 when changing voltage using gpio dvs. Refer to [1] below
-  for additional information.
-
-- max8997,pmic-buck5-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
-  units for buck5 when changing voltage using gpio dvs. Refer to [1] below
-  for additional information.
-
-[1] If none of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional
-    property is specified, the 'max8997,pmic-buck[1/2/5]-dvs-voltage'
-    property should specify atleast one voltage level (which would be a
-    safe operating voltage).
-
-    If either of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional
-    property is specified, then all the eigth voltage values for the
-    'max8997,pmic-buck[1/2/5]-dvs-voltage' should be specified.
-
-Optional properties:
-- interrupt-parent: Specifies the phandle of the interrupt controller to which
-  the interrupts from max8997 are delivered to.
-- interrupts: Interrupt specifiers for two interrupt sources.
-  - First interrupt specifier is for 'irq1' interrupt.
-  - Second interrupt specifier is for 'alert' interrupt.
-- max8997,pmic-buck1-uses-gpio-dvs: 'buck1' can be controlled by gpio dvs.
-- max8997,pmic-buck2-uses-gpio-dvs: 'buck2' can be controlled by gpio dvs.
-- max8997,pmic-buck5-uses-gpio-dvs: 'buck5' can be controlled by gpio dvs.
-
-Additional properties required if either of the optional properties are used:
-- max8997,pmic-ignore-gpiodvs-side-effect: When GPIO-DVS mode is used for
-  multiple bucks, changing the voltage value of one of the bucks may affect
-  that of another buck, which is the side effect of the change (set_voltage).
-  Use this property to ignore such side effects and change the voltage.
-
-- max8997,pmic-buck125-default-dvs-idx: Default voltage setting selected from
-  the possible 8 options selectable by the dvs gpios. The value of this
-  property should be between 0 and 7. If not specified or if out of range, the
-  default value of this property is set to 0.
-
-- max8997,pmic-buck125-dvs-gpios: GPIO specifiers for three host gpio's used
-  for dvs. The format of the gpio specifier depends in the gpio controller.
-
-Regulators: The regulators of max8997 that have to be instantiated should be
-included in a sub-node named 'regulators'. Regulator nodes included in this
-sub-node should be of the format as listed below.
-
-        regulator_name {
-                standard regulator bindings here
-        };
-
-The following are the names of the regulators that the max8997 pmic block
-supports. Note: The 'n' in LDOn and BUCKn represents the LDO or BUCK number
-as per the datasheet of max8997.
-
-        - LDOn
-                  - valid values for n are 1 to 18 and 21
-                  - Example: LDO0, LD01, LDO2, LDO21
-        - BUCKn
-                  - valid values for n are 1 to 7.
-                  - Example: BUCK1, BUCK2, BUCK3, BUCK7
-
-        - ENVICHG: Battery Charging Current Monitor Output. This is a fixed
-                   voltage type regulator
-
-        - ESAFEOUT1: (ldo19)
-        - ESAFEOUT2: (ld020)
-
-        - CHARGER_CV: main battery charger voltage control
-        - CHARGER: main battery charger current control
-        - CHARGER_TOPOFF: end of charge current threshold level
-
-The bindings inside the regulator nodes use the standard regulator bindings
-which are documented elsewhere.
-
-Example:
-
-        max8997_pmic@66 {
-                compatible = "maxim,max8997-pmic";
-                interrupt-parent = <&wakeup_eint>;
-                reg = <0x66>;
-                interrupts = <4 0>, <3 0>;
-
-                max8997,pmic-buck1-uses-gpio-dvs;
-                max8997,pmic-buck2-uses-gpio-dvs;
-                max8997,pmic-buck5-uses-gpio-dvs;
-
-                max8997,pmic-ignore-gpiodvs-side-effect;
-                max8997,pmic-buck125-default-dvs-idx = <0>;
-
-                max8997,pmic-buck125-dvs-gpios = <&gpx0 0 1 0 0>, /* SET1 */
-                                                 <&gpx0 1 1 0 0>, /* SET2 */
-                                                 <&gpx0 2 1 0 0>; /* SET3 */
-
-                max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>,
-                                                 <1250000>, <1200000>,
-                                                 <1150000>, <1100000>,
-                                                 <1000000>, <950000>;
-
-                max8997,pmic-buck2-dvs-voltage = <1100000>, <1100000>,
-                                                 <1100000>, <1100000>,
-                                                 <1000000>, <1000000>,
-                                                 <1000000>, <1000000>;
-
-                max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>,
-                                                 <1200000>, <1200000>,
-                                                 <1200000>, <1200000>,
-                                                 <1200000>, <1200000>;
-
-                regulators {
-                        ldo1_reg: LDO1 {
-                                regulator-name = "VDD_ABB_3.3V";
-                                regulator-min-microvolt = <3300000>;
-                                regulator-max-microvolt = <3300000>;
-                        };
-
-                        ldo2_reg: LDO2 {
-                                regulator-name = "VDD_ALIVE_1.1V";
-                                regulator-min-microvolt = <1100000>;
-                                regulator-max-microvolt = <1100000>;
-                                regulator-always-on;
-                        };
-
-                        buck1_reg: BUCK1 {
-                                regulator-name = "VDD_ARM_1.2V";
-                                regulator-min-microvolt = <950000>;
-                                regulator-max-microvolt = <1350000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                        };
-                };
-        };
diff --git a/Documentation/devicetree/bindings/regulator/regulator.txt b/Documentation/devicetree/bindings/regulator/regulator.txt
deleted file mode 100644
index ecfc6ccd67e..00000000000
--- a/Documentation/devicetree/bindings/regulator/regulator.txt
+++ /dev/null
@@ -1,62 +0,0 @@
-Voltage/Current Regulators
-
-Optional properties:
-- regulator-name: A string used as a descriptive name for regulator outputs
-- regulator-min-microvolt: smallest voltage consumers may set
-- regulator-max-microvolt: largest voltage consumers may set
-- regulator-microvolt-offset: Offset applied to voltages to compensate for voltage drops
-- regulator-min-microamp: smallest current consumers may set
-- regulator-max-microamp: largest current consumers may set
-- regulator-always-on: boolean, regulator should never be disabled
-- regulator-boot-on: bootloader/firmware enabled regulator
-- <name>-supply: phandle to the parent supply/regulator node
-- regulator-ramp-delay: ramp delay for regulator(in uV/uS)
-
-Deprecated properties:
-- regulator-compatible: If a regulator chip contains multiple
-  regulators, and if the chip's binding contains a child node that
-  describes each regulator, then this property indicates which regulator
-  this child node is intended to configure. If this property is missing,
-  the node's name will be used instead.
-
-Example:
-
-        xyzreg: regulator@0 {
-                regulator-min-microvolt = <1000000>;
-                regulator-max-microvolt = <2500000>;
-                regulator-always-on;
-                vin-supply = <&vin>;
-        };
-
-Regulator Consumers:
-Consumer nodes can reference one or more of its supplies/
-regulators using the below bindings.
-
-- <name>-supply: phandle to the regulator node
-
-These are the same bindings that a regulator in the above
-example used to reference its own supply, in which case
-its just seen as a special case of a regulator being a
-consumer itself.
-
-Example of a consumer device node (mmc) referencing two
-regulators (twl_reg1 and twl_reg2),
-
-        twl_reg1: regulator@0 {
-                ...
-                ...
-                ...
-        };
-
-        twl_reg2: regulator@1 {
-                ...
-                ...
-                ...
-        };
-
-        mmc: mmc@0x0 {
-                ...
-                ...
-                vmmc-supply = <&twl_reg1>;
-                vmmcaux-supply = <&twl_reg2>;
-        };
diff --git a/Documentation/devicetree/bindings/regulator/tps62360-regulator.txt b/Documentation/devicetree/bindings/regulator/tps62360-regulator.txt
deleted file mode 100644
index c8ca6b8f658..00000000000
--- a/Documentation/devicetree/bindings/regulator/tps62360-regulator.txt
+++ /dev/null
@@ -1,44 +0,0 @@
-TPS62360 Voltage regulators
-
-Required properties:
-- compatible: Must be one of the following.
-        "ti,tps62360"
-        "ti,tps62361",
-        "ti,tps62362",
-        "ti,tps62363",
-- reg: I2C slave address
-
-Optional properties:
-- ti,enable-vout-discharge: Enable output discharge. This is boolean value.
-- ti,enable-pull-down: Enable pull down. This is boolean value.
-- ti,vsel0-gpio: GPIO for controlling VSEL0 line.
-  If this property is missing, then assume that there is no GPIO
-  for vsel0 control.
-- ti,vsel1-gpio: Gpio for controlling VSEL1 line.
-  If this property is missing, then assume that there is no GPIO
-  for vsel1 control.
-- ti,vsel0-state-high: Inital state of vsel0 input is high.
-  If this property is missing, then assume the state as low (0).
-- ti,vsel1-state-high: Inital state of vsel1 input is high.
-  If this property is missing, then assume the state as low (0).
-
-Any property defined as part of the core regulator binding, defined in
-regulator.txt, can also be used.
-
-Example:
-
-        abc: tps62360 {
-                compatible = "ti,tps62361";
-                reg =  <0x60>;
-                regulator-name = "tps62361-vout";
-                regulator-min-microvolt = <500000>;
-                regulator-max-microvolt = <1500000>;
-                regulator-boot-on
-                ti,vsel0-gpio = <&gpio1 16 0>;
-                ti,vsel1-gpio = <&gpio1 17 0>;
-                ti,vsel0-state-high;
-                ti,vsel1-state-high;
-                ti,enable-pull-down;
-                ti,enable-force-pwm;
-                ti,enable-vout-discharge;
-        };
diff --git a/Documentation/devicetree/bindings/regulator/tps65217.txt b/Documentation/devicetree/bindings/regulator/tps65217.txt
deleted file mode 100644
index 4f05d208c95..00000000000
--- a/Documentation/devicetree/bindings/regulator/tps65217.txt
+++ /dev/null
@@ -1,78 +0,0 @@
-TPS65217 family of regulators
-
-Required properties:
-- compatible: "ti,tps65217"
-- reg: I2C slave address
-- regulators: list of regulators provided by this controller, must be named
-  after their hardware counterparts: dcdc[1-3] and ldo[1-4]
-- regulators: This is the list of child nodes that specify the regulator
-  initialization data for defined regulators. Not all regulators for the given
-  device need to be present. The definition for each of these nodes is defined
-  using the standard binding for regulators found at
-  Documentation/devicetree/bindings/regulator/regulator.txt.
-
-Optional properties:
-- ti,pmic-shutdown-controller: Telling the PMIC to shutdown on PWR_EN toggle.
-
-  The valid names for regulators are:
-  tps65217: dcdc1, dcdc2, dcdc3, ldo1, ldo2, ldo3 and ldo4
-
-Each regulator is defined using the standard binding for regulators.
-
-Example:
-
-        tps: tps@24 {
-                compatible = "ti,tps65217";
-                ti,pmic-shutdown-controller;
-
-                regulators {
-                        dcdc1_reg: dcdc1 {
-                                regulator-min-microvolt = <900000>;
-                                regulator-max-microvolt = <1800000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-
-                        dcdc2_reg: dcdc2 {
-                                regulator-min-microvolt = <900000>;
-                                regulator-max-microvolt = <3300000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-
-                        dcdc3_reg: dcc3 {
-                                regulator-min-microvolt = <900000>;
-                                regulator-max-microvolt = <1500000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-
-                        ldo1_reg: ldo1 {
-                                regulator-min-microvolt = <1000000>;
-                                regulator-max-microvolt = <3300000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-
-                        ldo2_reg: ldo2 {
-                                regulator-min-microvolt = <900000>;
-                                regulator-max-microvolt = <3300000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-
-                        ldo3_reg: ldo3 {
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <3300000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-
-                        ldo4_reg: ldo4 {
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <3300000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-                };
-        };
diff --git a/Documentation/devicetree/bindings/regulator/tps6586x.txt b/Documentation/devicetree/bindings/regulator/tps6586x.txt
deleted file mode 100644
index 8b40cac24d9..00000000000
--- a/Documentation/devicetree/bindings/regulator/tps6586x.txt
+++ /dev/null
@@ -1,135 +0,0 @@
-TPS6586x family of regulators
-
-Required properties:
-- compatible: "ti,tps6586x"
-- reg: I2C slave address
-- interrupts: the interrupt outputs of the controller
-- #gpio-cells: number of cells to describe a GPIO
-- gpio-controller: mark the device as a GPIO controller
-- regulators: A node that houses a sub-node for each regulator within the
-  device. Each sub-node is identified using the node's name (or the deprecated
-  regulator-compatible property if present), with valid values listed below.
-  The content of each sub-node is defined by the standard binding for
-  regulators; see regulator.txt.
-  sys, sm[0-2], ldo[0-9] and ldo_rtc
-- sys-supply: The input supply for SYS.
-- vin-sm0-supply: The input supply for the SM0.
-- vin-sm1-supply: The input supply for the SM1.
-- vin-sm2-supply: The input supply for the SM2.
-- vinldo01-supply: The input supply for the LDO1 and LDO2
-- vinldo23-supply: The input supply for the LDO2 and LDO3
-- vinldo4-supply: The input supply for the LDO4
-- vinldo678-supply: The input supply for the LDO6, LDO7 and LDO8
-- vinldo9-supply: The input supply for the LDO9
-
-Optional properties:
-- ti,system-power-controller: Telling whether or not this pmic is controlling
-  the system power.
-
-Each regulator is defined using the standard binding for regulators.
-
-Note: LDO5 and LDO_RTC is supplied by SYS regulator internally and driver
-      take care of making proper parent child relationship.
-
-Example:
-
-        pmu: tps6586x@34 {
-                compatible = "ti,tps6586x";
-                reg = <0x34>;
-                interrupts = <0 88 0x4>;
-
-                #gpio-cells = <2>;
-                gpio-controller;
-
-                ti,system-power-controller;
-
-                sys-supply = <&some_reg>;
-                vin-sm0-supply = <&some_reg>;
-                vin-sm1-supply = <&some_reg>;
-                vin-sm2-supply = <&some_reg>;
-                vinldo01-supply = <...>;
-                vinldo23-supply = <...>;
-                vinldo4-supply = <...>;
-                vinldo678-supply = <...>;
-                vinldo9-supply = <...>;
-
-                regulators {
-                        sys_reg: sys {
-                                regulator-name = "vdd_sys";
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-
-                        sm0_reg: sm0 {
-                                regulator-min-microvolt = < 725000>;
-                                regulator-max-microvolt = <1500000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-
-                        sm1_reg: sm1 {
-                                regulator-min-microvolt = < 725000>;
-                                regulator-max-microvolt = <1500000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-
-                        sm2_reg: sm2 {
-                                regulator-min-microvolt = <3000000>;
-                                regulator-max-microvolt = <4550000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-
-                        ldo0_reg: ldo0 {
-                                regulator-name = "PCIE CLK";
-                                regulator-min-microvolt = <3300000>;
-                                regulator-max-microvolt = <3300000>;
-                        };
-
-                        ldo1_reg: ldo1 {
-                                regulator-min-microvolt = < 725000>;
-                                regulator-max-microvolt = <1500000>;
-                        };
-
-                        ldo2_reg: ldo2 {
-                                regulator-min-microvolt = < 725000>;
-                                regulator-max-microvolt = <1500000>;
-                        };
-
-                        ldo3_reg: ldo3 {
-                                regulator-min-microvolt = <1250000>;
-                                regulator-max-microvolt = <3300000>;
-                        };
-
-                        ldo4_reg: ldo4 {
-                                regulator-min-microvolt = <1700000>;
-                                regulator-max-microvolt = <2475000>;
-                        };
-
-                        ldo5_reg: ldo5 {
-                                regulator-min-microvolt = <1250000>;
-                                regulator-max-microvolt = <3300000>;
-                        };
-
-                        ldo6_reg: ldo6 {
-                                regulator-min-microvolt = <1250000>;
-                                regulator-max-microvolt = <3300000>;
-                        };
-
-                        ldo7_reg: ldo7 {
-                                regulator-min-microvolt = <1250000>;
-                                regulator-max-microvolt = <3300000>;
-                        };
-
-                        ldo8_reg: ldo8 {
-                                regulator-min-microvolt = <1250000>;
-                                regulator-max-microvolt = <3300000>;
-                        };
-
-                        ldo9_reg: ldo9 {
-                                regulator-min-microvolt = <1250000>;
-                                regulator-max-microvolt = <3300000>;
-                        };
-                };
-        };
diff --git a/Documentation/devicetree/bindings/regulator/twl-regulator.txt b/Documentation/devicetree/bindings/regulator/twl-regulator.txt
deleted file mode 100644
index 658749b90b9..00000000000
--- a/Documentation/devicetree/bindings/regulator/twl-regulator.txt
+++ /dev/null
@@ -1,67 +0,0 @@
-TWL family of regulators
-
-Required properties:
-For twl6030 regulators/LDOs
-- compatible:
-  - "ti,twl6030-vaux1" for VAUX1 LDO
-  - "ti,twl6030-vaux2" for VAUX2 LDO
-  - "ti,twl6030-vaux3" for VAUX3 LDO
-  - "ti,twl6030-vmmc" for VMMC LDO
-  - "ti,twl6030-vpp" for VPP LDO
-  - "ti,twl6030-vusim" for VUSIM LDO
-  - "ti,twl6030-vana" for VANA LDO
-  - "ti,twl6030-vcxio" for VCXIO LDO
-  - "ti,twl6030-vdac" for VDAC LDO
-  - "ti,twl6030-vusb" for VUSB LDO
-  - "ti,twl6030-v1v8" for V1V8 LDO
-  - "ti,twl6030-v2v1" for V2V1 LDO
-  - "ti,twl6030-vdd1" for VDD1 SMPS
-  - "ti,twl6030-vdd2" for VDD2 SMPS
-  - "ti,twl6030-vdd3" for VDD3 SMPS
-For twl6025 regulators/LDOs
-- compatible:
-  - "ti,twl6025-ldo1" for LDO1 LDO
-  - "ti,twl6025-ldo2" for LDO2 LDO
-  - "ti,twl6025-ldo3" for LDO3 LDO
-  - "ti,twl6025-ldo4" for LDO4 LDO
-  - "ti,twl6025-ldo5" for LDO5 LDO
-  - "ti,twl6025-ldo6" for LDO6 LDO
-  - "ti,twl6025-ldo7" for LDO7 LDO
-  - "ti,twl6025-ldoln" for LDOLN LDO
-  - "ti,twl6025-ldousb" for LDOUSB LDO
-  - "ti,twl6025-smps3" for SMPS3 SMPS
-  - "ti,twl6025-smps4" for SMPS4 SMPS
-  - "ti,twl6025-vio" for VIO SMPS
-For twl4030 regulators/LDOs
-- compatible:
-  - "ti,twl4030-vaux1" for VAUX1 LDO
-  - "ti,twl4030-vaux2" for VAUX2 LDO
-  - "ti,twl5030-vaux2" for VAUX2 LDO
-  - "ti,twl4030-vaux3" for VAUX3 LDO
-  - "ti,twl4030-vaux4" for VAUX4 LDO
-  - "ti,twl4030-vmmc1" for VMMC1 LDO
-  - "ti,twl4030-vmmc2" for VMMC2 LDO
-  - "ti,twl4030-vpll1" for VPLL1 LDO
-  - "ti,twl4030-vpll2" for VPLL2 LDO
-  - "ti,twl4030-vsim" for VSIM LDO
-  - "ti,twl4030-vdac" for VDAC LDO
-  - "ti,twl4030-vintana2" for VINTANA2 LDO
-  - "ti,twl4030-vio" for VIO LDO
-  - "ti,twl4030-vdd1" for VDD1 SMPS
-  - "ti,twl4030-vdd2" for VDD2 SMPS
-  - "ti,twl4030-vintana1" for VINTANA1 LDO
-  - "ti,twl4030-vintdig" for VINTDIG LDO
-  - "ti,twl4030-vusb1v5" for VUSB1V5 LDO
-  - "ti,twl4030-vusb1v8" for VUSB1V8 LDO
-  - "ti,twl4030-vusb3v1" for VUSB3V1 LDO
-
-Optional properties:
-- Any optional property defined in bindings/regulator/regulator.txt
-
-Example:
-
-        xyz: regulator@0 {
-                compatible = "ti,twl6030-vaux1";
-                regulator-min-microvolt  = <1000000>;
-                regulator-max-microvolt  = <3000000>;
-        };
diff --git a/Documentation/devicetree/bindings/regulator/vexpress.txt b/Documentation/devicetree/bindings/regulator/vexpress.txt
deleted file mode 100644
index d775f72487a..00000000000
--- a/Documentation/devicetree/bindings/regulator/vexpress.txt
+++ /dev/null
@@ -1,32 +0,0 @@
-Versatile Express voltage regulators
-------------------------------------
-
-Requires node properties:
-- "compatible" value: "arm,vexpress-volt"
-- "arm,vexpress-sysreg,func" when controlled via vexpress-sysreg
-  (see Documentation/devicetree/bindings/arm/vexpress-sysreg.txt
-  for more details)
-
-Required regulator properties:
-- "regulator-name"
-- "regulator-always-on"
-
-Optional regulator properties:
-- "regulator-min-microvolt"
-- "regulator-max-microvolt"
-
-See Documentation/devicetree/bindings/regulator/regulator.txt
-for more details about the regulator properties.
-
-When no "regulator-[min|max]-microvolt" properties are defined,
-the device is treated as fixed (or rather "read-only") regulator.
-
-Example:
-        volt@0 {
-                compatible = "arm,vexpress-volt";
-                arm,vexpress-sysreg,func = <2 0>;
-                regulator-name = "Cores";
-                regulator-min-microvolt = <800000>;
-                regulator-max-microvolt = <1050000>;
-                regulator-always-on;
-        };
diff --git a/Documentation/devicetree/bindings/resource-names.txt b/Documentation/devicetree/bindings/resource-names.txt
deleted file mode 100644
index e280fef6f26..00000000000
--- a/Documentation/devicetree/bindings/resource-names.txt
+++ /dev/null
@@ -1,54 +0,0 @@
-Some properties contain an ordered list of 1 or more datum which are
-normally accessed by index.  However, some devices will have multiple
-values which are more naturally accessed by name.  Device nodes can
-include a supplemental property for assigning names to each of the list
-items.  The names property consists of a list of strings in the same
-order as the data in the resource property.
-
-The following supplemental names properties are defined.
-
-Resource Property       Supplemental Names Property
------------------       ---------------------------
-reg                     reg-names
-clocks                  clock-names
-interrupts              interrupt-names
-
-Usage:
-
-The -names property must be used in conjunction with the normal resource
-property. If not it will be ignored.
-
-Examples:
-
-l4-abe {
-        compatible = "simple-bus";
-        #address-cells = <2>;
-        #size-cells = <1>;
-        ranges = <0 0 0x48000000 0x00001000>, /* MPU path */
-                 <1 0 0x49000000 0x00001000>; /* L3 path */
-        mcasp {
-                compatible = "ti,mcasp";
-                reg = <0 0x10 0x10>, <0 0x20 0x10>,
-                      <1 0x10 0x10>, <1 0x20 0x10>;
-                reg-names = "mpu", "dat",
-                            "dma", "dma_dat";
-                interrupts = <11>, <12>;
-                interrupt-names = "rx", "tx";
-        };
-
-        timer {
-                compatible = "ti,timer";
-                reg = <0 0x40 0x10>, <1 0x40 0x10>;
-                reg-names = "mpu", "dma";
-        };
-};
-
-
-usb {
-        compatible = "ti,usb-host";
-        reg = <0x4a064000 0x800>, <0x4a064800 0x200>,
-              <0x4a064c00 0x200>;
-        reg-names = "config", "ohci", "ehci";
-        interrupts = <14>, <15>;
-        interrupt-names = "ohci", "ehci";
-};
diff --git a/Documentation/devicetree/bindings/rtc/dw-apb.txt b/Documentation/devicetree/bindings/rtc/dw-apb.txt
deleted file mode 100644
index 93e2b0f048e..00000000000
--- a/Documentation/devicetree/bindings/rtc/dw-apb.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-* Designware APB timer
-
-Required properties:
-- compatible: "snps,dw-apb-timer-sp" or "snps,dw-apb-timer-osc"
-- reg: physical base address of the controller and length of memory mapped
-  region.
-- interrupts: IRQ line for the timer.
-- clock-frequency: The frequency in HZ of the timer.
-- clock-freq: For backwards compatibility with picoxcell
-
-Example:
-
-                timer1: timer@ffc09000 {
-                                compatible = "snps,dw-apb-timer-sp";
-                                interrupts = <0 168 4>;
-                                clock-frequency = <200000000>;
-                                reg = <0xffc09000 0x1000>;
-                        };
-
-                timer2: timer@ffd00000 {
-                                compatible = "snps,dw-apb-timer-osc";
-                                interrupts = <0 169 4>;
-                                clock-frequency = <200000000>;
-                                reg = <0xffd00000 0x1000>;
-                        };
diff --git a/Documentation/devicetree/bindings/rtc/imxdi-rtc.txt b/Documentation/devicetree/bindings/rtc/imxdi-rtc.txt
deleted file mode 100644
index c9d80d7da14..00000000000
--- a/Documentation/devicetree/bindings/rtc/imxdi-rtc.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-* i.MX25 Real Time Clock controller
-
-This binding supports the following chips: i.MX25, i.MX53
-
-Required properties:
-- compatible: should be: "fsl,imx25-rtc"
-- reg: physical base address of the controller and length of memory mapped
-  region.
-- interrupts: rtc alarm interrupt
-
-Example:
-
-rtc@80056000 {
-        compatible = "fsl,imx53-rtc", "fsl,imx25-rtc";
-        reg = <0x80056000 2000>;
-        interrupts = <29>;
-};
diff --git a/Documentation/devicetree/bindings/rtc/lpc32xx-rtc.txt b/Documentation/devicetree/bindings/rtc/lpc32xx-rtc.txt
deleted file mode 100644
index a87a1e9bc06..00000000000
--- a/Documentation/devicetree/bindings/rtc/lpc32xx-rtc.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-* NXP LPC32xx SoC Real Time Clock controller
-
-Required properties:
-- compatible: must be "nxp,lpc3220-rtc"
-- reg: physical base address of the controller and length of memory mapped
-  region.
-- interrupts: The RTC interrupt
-
-Example:
-
-        rtc@40024000 {
-                compatible = "nxp,lpc3220-rtc";
-                reg = <0x40024000 0x1000>;
-                interrupts = <52 0>;
-        };
diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
deleted file mode 100644
index 93f45e9dce7..00000000000
--- a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-NVIDIA Tegra20 real-time clock
-
-The Tegra RTC maintains seconds and milliseconds counters, and five alarm
-registers. The alarms and other interrupts may wake the system from low-power
-state.
-
-Required properties:
-
-- compatible : should be "nvidia,tegra20-rtc".
-- reg : Specifies base physical address and size of the registers.
-- interrupts : A single interrupt specifier.
-
-Example:
-
-timer {
-        compatible = "nvidia,tegra20-rtc";
-        reg = <0x7000e000 0x100>;
-        interrupts = <0 2 0x04>;
-};
diff --git a/Documentation/devicetree/bindings/rtc/orion-rtc.txt b/Documentation/devicetree/bindings/rtc/orion-rtc.txt
deleted file mode 100644
index 3bf63ffa516..00000000000
--- a/Documentation/devicetree/bindings/rtc/orion-rtc.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-* Mvebu Real Time Clock
-
-RTC controller for the Kirkwood, the Dove, the Armada 370 and the
-Armada XP SoCs
-
-Required properties:
-- compatible : Should be "marvell,orion-rtc"
-- reg: physical base address of the controller and length of memory mapped
-  region.
-- interrupts: IRQ line for the RTC.
-
-Example:
-
-rtc@10300 {
-        compatible = "marvell,orion-rtc";
-        reg = <0xd0010300 0x20>;
-        interrupts = <50>;
-};
diff --git a/Documentation/devicetree/bindings/rtc/pxa-rtc.txt b/Documentation/devicetree/bindings/rtc/pxa-rtc.txt
deleted file mode 100644
index 8c6672a1b7d..00000000000
--- a/Documentation/devicetree/bindings/rtc/pxa-rtc.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-* PXA RTC
-
-PXA specific RTC driver.
-
-Required properties:
-- compatible : Should be "marvell,pxa-rtc"
-
-Examples:
-
-rtc@40900000 {
-        compatible = "marvell,pxa-rtc";
-        reg = <0x40900000 0x3c>;
-        interrupts = <30 31>;
-};
diff --git a/Documentation/devicetree/bindings/rtc/rtc-omap.txt b/Documentation/devicetree/bindings/rtc/rtc-omap.txt
deleted file mode 100644
index b47aa415c82..00000000000
--- a/Documentation/devicetree/bindings/rtc/rtc-omap.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-TI Real Time Clock
-
-Required properties:
-- compatible: "ti,da830-rtc"
-- reg: Address range of rtc register set
-- interrupts: rtc timer, alarm interrupts in order
-- interrupt-parent: phandle for the interrupt controller
-
-Example:
-
-rtc@1c23000 {
-        compatible = "ti,da830-rtc";
-        reg = <0x23000 0x1000>;
-        interrupts = <19
-                      19>;
-        interrupt-parent = <&intc>;
-};
diff --git a/Documentation/devicetree/bindings/rtc/s3c-rtc.txt b/Documentation/devicetree/bindings/rtc/s3c-rtc.txt
deleted file mode 100644
index 90ec45fd33e..00000000000
--- a/Documentation/devicetree/bindings/rtc/s3c-rtc.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-* Samsung's S3C Real Time Clock controller
-
-Required properties:
-- compatible: should be one of the following.
-    * "samsung,s3c2410-rtc" - for controllers compatible with s3c2410 rtc.
-    * "samsung,s3c6410-rtc" - for controllers compatible with s3c6410 rtc.
-- reg: physical base address of the controller and length of memory mapped
-  region.
-- interrupts: Two interrupt numbers to the cpu should be specified. First
-  interrupt number is the rtc alarm interupt and second interrupt number
-  is the rtc tick interrupt. The number of cells representing a interrupt
-  depends on the parent interrupt controller.
-
-Example:
-
-        rtc@10070000 {
-                compatible = "samsung,s3c6410-rtc";
-                reg = <0x10070000 0x100>;
-                interrupts = <44 0 45 0>;
-        };
diff --git a/Documentation/devicetree/bindings/rtc/sa1100-rtc.txt b/Documentation/devicetree/bindings/rtc/sa1100-rtc.txt
deleted file mode 100644
index 0cda19ad485..00000000000
--- a/Documentation/devicetree/bindings/rtc/sa1100-rtc.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-* Marvell Real Time Clock controller
-
-Required properties:
-- compatible: should be "mrvl,sa1100-rtc"
-- reg: physical base address of the controller and length of memory mapped
-  region.
-- interrupts: Should be two. The first interrupt number is the rtc alarm
-  interrupt and the second interrupt number is the rtc hz interrupt.
-- interrupt-names: Assign name of irq resource.
-
-Example:
-        rtc: rtc@d4010000 {
-                compatible = "mrvl,mmp-rtc";
-                reg = <0xd4010000 0x1000>;
-                interrupts = <5>, <6>;
-                interrupt-name = "rtc 1Hz", "rtc alarm";
-        };
diff --git a/Documentation/devicetree/bindings/rtc/snvs-rtc.txt b/Documentation/devicetree/bindings/rtc/snvs-rtc.txt
deleted file mode 100644
index fb61ed77ada..00000000000
--- a/Documentation/devicetree/bindings/rtc/snvs-rtc.txt
+++ /dev/null
@@ -1 +0,0 @@
-See Documentation/devicetree/bindings/crypto/fsl-sec4.txt for details.
diff --git a/Documentation/devicetree/bindings/rtc/spear-rtc.txt b/Documentation/devicetree/bindings/rtc/spear-rtc.txt
deleted file mode 100644
index ca67ac62108..00000000000
--- a/Documentation/devicetree/bindings/rtc/spear-rtc.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-* SPEAr RTC
-
-Required properties:
-- compatible : "st,spear600-rtc"
-- reg : Address range of the rtc registers
-- interrupt-parent: Should be the phandle for the interrupt controller
-  that services interrupts for this device
-- interrupt: Should contain the rtc interrupt number
-
-Example:
-
-        rtc@fc000000 {
-                compatible = "st,spear600-rtc";
-                reg = <0xfc000000 0x1000>;
-                interrupt-parent = <&vic1>;
-                interrupts = <12>;
-        };
diff --git a/Documentation/devicetree/bindings/rtc/stmp3xxx-rtc.txt b/Documentation/devicetree/bindings/rtc/stmp3xxx-rtc.txt
deleted file mode 100644
index b800070fe6e..00000000000
--- a/Documentation/devicetree/bindings/rtc/stmp3xxx-rtc.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-* STMP3xxx/i.MX28 Time Clock controller
-
-Required properties:
-- compatible: should be one of the following.
-    * "fsl,stmp3xxx-rtc"
-- reg: physical base address of the controller and length of memory mapped
-  region.
-- interrupts: rtc alarm interrupt
-
-Example:
-
-rtc@80056000 {
-        compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
-        reg = <0x80056000 2000>;
-        interrupts = <29>;
-};
diff --git a/Documentation/devicetree/bindings/rtc/twl-rtc.txt b/Documentation/devicetree/bindings/rtc/twl-rtc.txt
deleted file mode 100644
index 596e0c97be7..00000000000
--- a/Documentation/devicetree/bindings/rtc/twl-rtc.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-* TI twl RTC
-
-The TWL family (twl4030/6030) contains a RTC.
-
-Required properties:
-- compatible : Should be twl4030-rtc
-
-Examples:
-
-rtc@0 {
-    compatible = "ti,twl4030-rtc";
-};
diff --git a/Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt b/Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt
deleted file mode 100644
index 3c0484c4958..00000000000
--- a/Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-VIA/Wondermedia VT8500 Realtime Clock Controller
------------------------------------------------------
-
-Required properties:
-- compatible : "via,vt8500-rtc"
-- reg : Should contain 1 register ranges(address and length)
-- interrupts : alarm interrupt
-
-Example:
-
-        rtc@d8100000 {
-                compatible = "via,vt8500-rtc";
-                reg = <0xd8100000 0x10000>;
-                interrupts = <48>;
-        };
diff --git a/Documentation/devicetree/bindings/serial/cavium-uart.txt b/Documentation/devicetree/bindings/serial/cavium-uart.txt
deleted file mode 100644
index 87a6c375cd4..00000000000
--- a/Documentation/devicetree/bindings/serial/cavium-uart.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-* Universal Asynchronous Receiver/Transmitter (UART)
-
-- compatible: "cavium,octeon-3860-uart"
-
-  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
-
-- reg: The base address of the UART register bank.
-
-- interrupts: A single interrupt specifier.
-
-- current-speed: Optional, the current bit rate in bits per second.
-
-Example:
-        uart1: serial@1180000000c00 {
-                compatible = "cavium,octeon-3860-uart","ns16550";
-                reg = <0x11800 0x00000c00 0x0 0x400>;
-                current-speed = <115200>;
-                interrupts = <0 35>;
-        };
diff --git a/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt b/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt
deleted file mode 100644
index c58573b5b1a..00000000000
--- a/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-* Freescale i.MX UART controller
-
-Required properties:
-- compatible : should be "fsl,imx21-uart"
-- reg : Address and length of the register set for the device
-- interrupts : Should contain UART interrupt number
-
-Optional properties:
-- fsl,uart-has-rtscts: indicate that RTS/CTS signals are used
-
-Note: Each uart controller should have an alias correctly numbered
-in "aliases" node.
-
-Example:
-
-- From imx51.dtsi:
-aliases {
-        serial0 = &uart1;
-        serial1 = &uart2;
-        serial2 = &uart3;
-};
-
-uart1: serial@73fbc000 {
-        compatible = "fsl,imx51-uart", "fsl,imx21-uart";
-        reg = <0x73fbc000 0x4000>;
-        interrupts = <31>;
-        status = "disabled";
-}
-
-- From imx51-babbage.dts:
-uart1: serial@73fbc000 {
-        fsl,uart-has-rtscts;
-        status = "okay";
-};
-
diff --git a/Documentation/devicetree/bindings/serial/mrvl-serial.txt b/Documentation/devicetree/bindings/serial/mrvl-serial.txt
deleted file mode 100644
index d744340de88..00000000000
--- a/Documentation/devicetree/bindings/serial/mrvl-serial.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-PXA UART controller
-
-Required properties:
-- compatible : should be "mrvl,mmp-uart" or "mrvl,pxa-uart".
diff --git a/Documentation/devicetree/bindings/serial/omap_serial.txt b/Documentation/devicetree/bindings/serial/omap_serial.txt
deleted file mode 100644
index 342eedd1005..00000000000
--- a/Documentation/devicetree/bindings/serial/omap_serial.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-OMAP UART controller
-
-Required properties:
-- compatible : should be "ti,omap2-uart" for OMAP2 controllers
-- compatible : should be "ti,omap3-uart" for OMAP3 controllers
-- compatible : should be "ti,omap4-uart" for OMAP4 controllers
-- ti,hwmods : Must be "uart<n>", n being the instance number (1-based)
-
-Optional properties:
-- clock-frequency : frequency of the clock input to the UART
diff --git a/Documentation/devicetree/bindings/serial/rs485.txt b/Documentation/devicetree/bindings/serial/rs485.txt
deleted file mode 100644
index 1e753c69fc8..00000000000
--- a/Documentation/devicetree/bindings/serial/rs485.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-* RS485 serial communications
-
-The RTS signal is capable of automatically controlling line direction for
-the built-in half-duplex mode.
-The properties described hereafter shall be given to a half-duplex capable
-UART node.
-
-Required properties:
-- rs485-rts-delay: prop-encoded-array <a b> where:
-  * a is the delay beteween rts signal and beginning of data sent in milliseconds.
-      it corresponds to the delay before sending data.
-  * b is the delay between end of data sent and rts signal in milliseconds
-      it corresponds to the delay after sending data and actual release of the line.
-
-Optional properties:
-- linux,rs485-enabled-at-boot-time: empty property telling to enable the rs485
-  feature at boot time. It can be disabled later with proper ioctl.
-- rs485-rx-during-tx: empty property that enables the receiving of data even
-  whilst sending data.
-
-RS485 example for Atmel USART:
-        usart0: serial@fff8c000 {
-                compatible = "atmel,at91sam9260-usart";
-                reg = <0xfff8c000 0x4000>;
-                interrupts = <7>;
-                atmel,use-dma-rx;
-                atmel,use-dma-tx;
-                linux,rs485-enabled-at-boot-time;
-                rs485-rts-delay = <0 200>;              // in milliseconds
-        };
-
diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.txt b/Documentation/devicetree/bindings/serial/samsung_uart.txt
deleted file mode 100644
index 2c8a17cf5cb..00000000000
--- a/Documentation/devicetree/bindings/serial/samsung_uart.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-* Samsung's UART Controller
-
-The Samsung's UART controller is used for interfacing SoC with serial communicaion
-devices.
-
-Required properties:
-- compatible: should be
-  - "samsung,exynos4210-uart", for UART's compatible with Exynos4210 uart ports.
-
-- reg: base physical address of the controller and length of memory mapped
-  region.
-
-- interrupts: interrupt number to the cpu. The interrupt specifier format depends
-  on the interrupt controller parent.
diff --git a/Documentation/devicetree/bindings/sound/ak4104.txt b/Documentation/devicetree/bindings/sound/ak4104.txt
deleted file mode 100644
index b902ee39cf8..00000000000
--- a/Documentation/devicetree/bindings/sound/ak4104.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-AK4104 S/PDIF transmitter
-
-This device supports SPI mode only.
-
-Required properties:
-
-  - compatible : "asahi-kasei,ak4104"
-
-  - reg : The chip select number on the SPI bus
-
-Optional properties:
-
-  - reset-gpio : a GPIO spec for the reset pin. If specified, it will be
-                 deasserted before communication to the device starts.
-
-Example:
-
-spdif: ak4104@0 {
-        compatible = "asahi-kasei,ak4104";
-        reg = <0>;
-        spi-max-frequency = <5000000>;
-};
diff --git a/Documentation/devicetree/bindings/sound/alc5632.txt b/Documentation/devicetree/bindings/sound/alc5632.txt
deleted file mode 100644
index 8608f747dcf..00000000000
--- a/Documentation/devicetree/bindings/sound/alc5632.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-ALC5632 audio CODEC
-
-This device supports I2C only.
-
-Required properties:
-
-  - compatible : "realtek,alc5632"
-
-  - reg : the I2C address of the device.
-
-  - gpio-controller : Indicates this device is a GPIO controller.
-
-  - #gpio-cells : Should be two. The first cell is the pin number and the
-    second cell is used to specify optional parameters (currently unused).
-
-Example:
-
-alc5632: alc5632@1e {
-        compatible = "realtek,alc5632";
-        reg = <0x1a>;
-
-        gpio-controller;
-        #gpio-cells = <2>;
-};
diff --git a/Documentation/devicetree/bindings/sound/atmel-at91sam9g20ek-wm8731-audio.txt b/Documentation/devicetree/bindings/sound/atmel-at91sam9g20ek-wm8731-audio.txt
deleted file mode 100644
index 9c5a9947b64..00000000000
--- a/Documentation/devicetree/bindings/sound/atmel-at91sam9g20ek-wm8731-audio.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-* Atmel at91sam9g20ek wm8731 audio complex
-
-Required properties:
-  - compatible: "atmel,at91sam9g20ek-wm8731-audio"
-  - atmel,model: The user-visible name of this sound complex.
-  - atmel,audio-routing: A list of the connections between audio components.
-  - atmel,ssc-controller: The phandle of the SSC controller
-  - atmel,audio-codec: The phandle of the WM8731 audio codec
-Optional properties:
-  - pinctrl-names, pinctrl-0: Please refer to pinctrl-bindings.txt
-
-Example:
-sound {
-        compatible = "atmel,at91sam9g20ek-wm8731-audio";
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_pck0_as_mck>;
-
-        atmel,model = "wm8731 @ AT91SAMG20EK";
-
-        atmel,audio-routing =
-                "Ext Spk", "LHPOUT",
-                "Int MIC", "MICIN";
-
-        atmel,ssc-controller = <&ssc0>;
-        atmel,audio-codec = <&wm8731>;
-};
diff --git a/Documentation/devicetree/bindings/sound/cs4270.txt b/Documentation/devicetree/bindings/sound/cs4270.txt
deleted file mode 100644
index 6b222f9b8ef..00000000000
--- a/Documentation/devicetree/bindings/sound/cs4270.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-CS4270 audio CODEC
-
-The driver for this device currently only supports I2C.
-
-Required properties:
-
-  - compatible : "cirrus,cs4270"
-
-  - reg : the I2C address of the device for I2C
-
-Optional properties:
-
-  - reset-gpio : a GPIO spec for the reset pin. If specified, it will be
-                 deasserted before communication to the codec starts.
-
-Example:
-
-codec: cs4270@48 {
-        compatible = "cirrus,cs4270";
-        reg = <0x48>;
-};
diff --git a/Documentation/devicetree/bindings/sound/cs4271.txt b/Documentation/devicetree/bindings/sound/cs4271.txt
deleted file mode 100644
index a850fb9c88e..00000000000
--- a/Documentation/devicetree/bindings/sound/cs4271.txt
+++ /dev/null
@@ -1,38 +0,0 @@
-Cirrus Logic CS4271 DT bindings
-
-This driver supports both the I2C and the SPI bus.
-
-Required properties:
-
- - compatible: "cirrus,cs4271"
-
-For required properties on SPI, please consult
-Documentation/devicetree/bindings/spi/spi-bus.txt
-
-Required properties on I2C:
-
- - reg: the i2c address
-
-
-Optional properties:
-
- - reset-gpio:  a GPIO spec to define which pin is connected to the chip's
-                !RESET pin
- - cirrus,amuteb-eq-bmutec:     When given, the Codec's AMUTEB=BMUTEC flag
-                                is enabled.
-
-Examples:
-
-        codec_i2c: cs4271@10 {
-                compatible = "cirrus,cs4271";
-                reg = <0x10>;
-                reset-gpio = <&gpio 23 0>;
-        };
-
-        codec_spi: cs4271@0 {
-                compatible = "cirrus,cs4271";
-                reg = <0x0>;
-                reset-gpio = <&gpio 23 0>;
-                spi-max-frequency = <6000000>;
-        };
-
diff --git a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
deleted file mode 100644
index 374e145c2ef..00000000000
--- a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
+++ /dev/null
@@ -1,45 +0,0 @@
-Texas Instruments McASP controller
-
-Required properties:
-- compatible :
-        "ti,dm646x-mcasp-audio" : for DM646x platforms
-        "ti,da830-mcasp-audio"  : for both DA830 & DA850 platforms
-        "ti,omap2-mcasp-audio"  : for OMAP2 platforms (TI81xx, AM33xx)
-
-- reg : Should contain McASP registers offset and length
-- interrupts : Interrupt number for McASP
-- op-mode : I2S/DIT ops mode.
-- tdm-slots : Slots for TDM operation.
-- num-serializer : Serializers used by McASP.
-- serial-dir : A list of serializer pin mode. The list number should be equal
-                to "num-serializer" parameter. Each entry is a number indication
-                serializer pin direction. (0 - INACTIVE, 1 - TX, 2 - RX)
-
-
-Optional properties:
-
-- ti,hwmods : Must be "mcasp<n>", n is controller instance starting 0
-- tx-num-evt : FIFO levels.
-- rx-num-evt : FIFO levels.
-- sram-size-playback : size of sram to be allocated during playback
-- sram-size-capture  : size of sram to be allocated during capture
-
-Example:
-
-mcasp0: mcasp0@1d00000 {
-        compatible = "ti,da830-mcasp-audio";
-        #address-cells = <1>;
-        #size-cells = <0>;
-        reg = <0x100000 0x3000>;
-        interrupts = <82 83>;
-        op-mode = <0>;          /* MCASP_IIS_MODE */
-        tdm-slots = <2>;
-        num-serializer = <16>;
-        serial-dir = <
-                        0 0 0 0 /* 0: INACTIVE, 1: TX, 2: RX */
-                        0 0 0 0
-                        0 0 0 1
-                        2 0 0 0 >;
-        tx-num-evt = <1>;
-        rx-num-evt = <1>;
-};
diff --git a/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt b/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt
deleted file mode 100644
index e4acdd891e4..00000000000
--- a/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt
+++ /dev/null
@@ -1,49 +0,0 @@
-Freescale i.MX audio complex with SGTL5000 codec
-
-Required properties:
-- compatible : "fsl,imx-audio-sgtl5000"
-- model : The user-visible name of this sound complex
-- ssi-controller : The phandle of the i.MX SSI controller
-- audio-codec : The phandle of the SGTL5000 audio codec
-- audio-routing : A list of the connections between audio components.
-  Each entry is a pair of strings, the first being the connection's sink,
-  the second being the connection's source. Valid names could be power
-  supplies, SGTL5000 pins, and the jacks on the board:
-
-  Power supplies:
-   * Mic Bias
-
-  SGTL5000 pins:
-   * MIC_IN
-   * LINE_IN
-   * HP_OUT
-   * LINE_OUT
-
-  Board connectors:
-   * Mic Jack
-   * Line In Jack
-   * Headphone Jack
-   * Line Out Jack
-   * Ext Spk
-
-- mux-int-port : The internal port of the i.MX audio muxer (AUDMUX)
-- mux-ext-port : The external port of the i.MX audio muxer
-
-Note: The AUDMUX port numbering should start at 1, which is consistent with
-hardware manual.
-
-Example:
-
-sound {
-        compatible = "fsl,imx51-babbage-sgtl5000",
-                     "fsl,imx-audio-sgtl5000";
-        model = "imx51-babbage-sgtl5000";
-        ssi-controller = <&ssi1>;
-        audio-codec = <&sgtl5000>;
-        audio-routing =
-                "MIC_IN", "Mic Jack",
-                "Mic Jack", "Mic Bias",
-                "Headphone Jack", "HP_OUT";
-        mux-int-port = <1>;
-        mux-ext-port = <3>;
-};
diff --git a/Documentation/devicetree/bindings/sound/imx-audmux.txt b/Documentation/devicetree/bindings/sound/imx-audmux.txt
deleted file mode 100644
index 215aa981721..00000000000
--- a/Documentation/devicetree/bindings/sound/imx-audmux.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-Freescale Digital Audio Mux (AUDMUX) device
-
-Required properties:
-- compatible : "fsl,imx21-audmux" for AUDMUX version firstly used on i.MX21,
-  or "fsl,imx31-audmux" for the version firstly used on i.MX31.
-- reg : Should contain AUDMUX registers location and length
-
-Example:
-
-audmux@021d8000 {
-        compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
-        reg = <0x021d8000 0x4000>;
-};
diff --git a/Documentation/devicetree/bindings/sound/mxs-audio-sgtl5000.txt b/Documentation/devicetree/bindings/sound/mxs-audio-sgtl5000.txt
deleted file mode 100644
index 601c518edda..00000000000
--- a/Documentation/devicetree/bindings/sound/mxs-audio-sgtl5000.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-* Freescale MXS audio complex with SGTL5000 codec
-
-Required properties:
-- compatible: "fsl,mxs-audio-sgtl5000"
-- model: The user-visible name of this sound complex
-- saif-controllers: The phandle list of the MXS SAIF controller
-- audio-codec: The phandle of the SGTL5000 audio codec
-
-Example:
-
-sound {
-        compatible = "fsl,imx28-evk-sgtl5000",
-                     "fsl,mxs-audio-sgtl5000";
-        model = "imx28-evk-sgtl5000";
-        saif-controllers = <&saif0 &saif1>;
-        audio-codec = <&sgtl5000>;
-};
diff --git a/Documentation/devicetree/bindings/sound/mxs-saif.txt b/Documentation/devicetree/bindings/sound/mxs-saif.txt
deleted file mode 100644
index c37ba6143d9..00000000000
--- a/Documentation/devicetree/bindings/sound/mxs-saif.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-* Freescale MXS Serial Audio Interface (SAIF)
-
-Required properties:
-- compatible: Should be "fsl,<chip>-saif"
-- reg: Should contain registers location and length
-- interrupts: Should contain ERROR and DMA interrupts
-- fsl,saif-dma-channel: APBX DMA channel for the SAIF
-
-Optional properties:
-- fsl,saif-master: phandle to the master SAIF.  It's only required for
-  the slave SAIF.
-
-Note: Each SAIF controller should have an alias correctly numbered
-in "aliases" node.
-
-Example:
-
-aliases {
-        saif0 = &saif0;
-        saif1 = &saif1;
-};
-
-saif0: saif@80042000 {
-        compatible = "fsl,imx28-saif";
-        reg = <0x80042000 2000>;
-        interrupts = <59 80>;
-        fsl,saif-dma-channel = <4>;
-};
-
-saif1: saif@80046000 {
-        compatible = "fsl,imx28-saif";
-        reg = <0x80046000 2000>;
-        interrupts = <58 81>;
-        fsl,saif-dma-channel = <5>;
-        fsl,saif-master = <&saif0>;
-};
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt
deleted file mode 100644
index b77a97c9101..00000000000
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt
+++ /dev/null
@@ -1,59 +0,0 @@
-NVIDIA Tegra audio complex
-
-Required properties:
-- compatible : "nvidia,tegra-audio-alc5632"
-- nvidia,model : The user-visible name of this sound complex.
-- nvidia,audio-routing : A list of the connections between audio components.
-  Each entry is a pair of strings, the first being the connection's sink,
-  the second being the connection's source. Valid names for sources and
-  sinks are the ALC5632's pins:
-
-  ALC5632 pins:
-
-  * SPK_OUTP
-  * SPK_OUTN
-  * HP_OUT_L
-  * HP_OUT_R
-  * AUX_OUT_P
-  * AUX_OUT_N
-  * LINE_IN_L
-  * LINE_IN_R
-  * PHONE_P
-  * PHONE_N
-  * MIC1_P
-  * MIC1_N
-  * MIC2_P
-  * MIC2_N
-  * MICBIAS1
-  * DMICDAT
-
-  Board connectors:
-
-  * Headset Stereophone
-  * Int Spk
-  * Headset Mic
-  * Digital Mic
-
-- nvidia,i2s-controller : The phandle of the Tegra I2S controller
-- nvidia,audio-codec : The phandle of the ALC5632 audio codec
-
-Example:
-
-sound {
-        compatible = "nvidia,tegra-audio-alc5632-paz00",
-                                 "nvidia,tegra-audio-alc5632";
-
-        nvidia,model = "Compal PAZ00";
-
-        nvidia,audio-routing =
-                                "Int Spk", "SPK_OUTP",
-                                "Int Spk", "SPK_OUTN",
-                                "Headset Mic","MICBIAS1",
-                                "MIC1_N", "Headset Mic",
-                                "MIC1_P", "Headset Mic",
-                                "Headset Stereophone", "HP_OUT_R",
-                                "Headset Stereophone", "HP_OUT_L";
-
-        nvidia,i2s-controller = <&tegra_i2s1>;
-        nvidia,audio-codec = <&alc5632>;
-};
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-trimslice.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-trimslice.txt
deleted file mode 100644
index 04b14cfb1f1..00000000000
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-trimslice.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-NVIDIA Tegra audio complex for TrimSlice
-
-Required properties:
-- compatible : "nvidia,tegra-audio-trimslice"
-- nvidia,i2s-controller : The phandle of the Tegra I2S1 controller
-- nvidia,audio-codec : The phandle of the WM8903 audio codec
-
-Example:
-
-sound {
-        compatible = "nvidia,tegra-audio-trimslice";
-        nvidia,i2s-controller = <&tegra_i2s1>;
-        nvidia,audio-codec = <&codec>;
-};
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
deleted file mode 100644
index c4dd39ce616..00000000000
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
+++ /dev/null
@@ -1,54 +0,0 @@
-NVIDIA Tegra audio complex
-
-Required properties:
-- compatible : "nvidia,tegra-audio-wm8753"
-- nvidia,model : The user-visible name of this sound complex.
-- nvidia,audio-routing : A list of the connections between audio components.
-  Each entry is a pair of strings, the first being the connection's sink,
-  the second being the connection's source. Valid names for sources and
-  sinks are the WM8753's pins, and the jacks on the board:
-
-  WM8753 pins:
-
-  * LOUT1
-  * LOUT2
-  * ROUT1
-  * ROUT2
-  * MONO1
-  * MONO2
-  * OUT3
-  * OUT4
-  * LINE1
-  * LINE2
-  * RXP
-  * RXN
-  * ACIN
-  * ACOP
-  * MIC1N
-  * MIC1
-  * MIC2N
-  * MIC2
-  * Mic Bias
-
-  Board connectors:
-
-  * Headphone Jack
-  * Mic Jack
-
-- nvidia,i2s-controller : The phandle of the Tegra I2S1 controller
-- nvidia,audio-codec : The phandle of the WM8753 audio codec
-Example:
-
-sound {
-        compatible = "nvidia,tegra-audio-wm8753-whistler",
-                     "nvidia,tegra-audio-wm8753"
-        nvidia,model = "tegra-wm8753-harmony";
-
-        nvidia,audio-routing =
-                "Headphone Jack", "LOUT1",
-                "Headphone Jack", "ROUT1";
-
-        nvidia,i2s-controller = <&i2s1>;
-        nvidia,audio-codec = <&wm8753>;
-};
-
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
deleted file mode 100644
index d5b0da8bf1d..00000000000
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
+++ /dev/null
@@ -1,71 +0,0 @@
-NVIDIA Tegra audio complex
-
-Required properties:
-- compatible : "nvidia,tegra-audio-wm8903"
-- nvidia,model : The user-visible name of this sound complex.
-- nvidia,audio-routing : A list of the connections between audio components.
-  Each entry is a pair of strings, the first being the connection's sink,
-  the second being the connection's source. Valid names for sources and
-  sinks are the WM8903's pins, and the jacks on the board:
-
-  WM8903 pins:
-
-  * IN1L
-  * IN1R
-  * IN2L
-  * IN2R
-  * IN3L
-  * IN3R
-  * DMICDAT
-  * HPOUTL
-  * HPOUTR
-  * LINEOUTL
-  * LINEOUTR
-  * LOP
-  * LON
-  * ROP
-  * RON
-  * MICBIAS
-
-  Board connectors:
-
-  * Headphone Jack
-  * Int Spk
-  * Mic Jack
-
-- nvidia,i2s-controller : The phandle of the Tegra I2S1 controller
-- nvidia,audio-codec : The phandle of the WM8903 audio codec
-
-Optional properties:
-- nvidia,spkr-en-gpios : The GPIO that enables the speakers
-- nvidia,hp-mute-gpios : The GPIO that mutes the headphones
-- nvidia,hp-det-gpios : The GPIO that detect headphones are plugged in
-- nvidia,int-mic-en-gpios : The GPIO that enables the internal microphone
-- nvidia,ext-mic-en-gpios : The GPIO that enables the external microphone
-
-Example:
-
-sound {
-        compatible = "nvidia,tegra-audio-wm8903-harmony",
-                     "nvidia,tegra-audio-wm8903"
-        nvidia,model = "tegra-wm8903-harmony";
-
-        nvidia,audio-routing =
-                "Headphone Jack", "HPOUTR",
-                "Headphone Jack", "HPOUTL",
-                "Int Spk", "ROP",
-                "Int Spk", "RON",
-                "Int Spk", "LOP",
-                "Int Spk", "LON",
-                "Mic Jack", "MICBIAS",
-                "IN1L", "Mic Jack";
-
-        nvidia,i2s-controller = <&i2s1>;
-        nvidia,audio-codec = <&wm8903>;
-
-        nvidia,spkr-en-gpios = <&codec 2 0>;
-        nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
-        nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
-        nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
-};
-
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-das.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-das.txt
deleted file mode 100644
index 6de3a7ee4ef..00000000000
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-das.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-NVIDIA Tegra 20 DAS (Digital Audio Switch) controller
-
-Required properties:
-- compatible : "nvidia,tegra20-das"
-- reg : Should contain DAS registers location and length
-
-Example:
-
-das@70000c00 {
-        compatible = "nvidia,tegra20-das";
-        reg = <0x70000c00 0x80>;
-};
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
deleted file mode 100644
index 0df2b5c816e..00000000000
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-NVIDIA Tegra 20 I2S controller
-
-Required properties:
-- compatible : "nvidia,tegra20-i2s"
-- reg : Should contain I2S registers location and length
-- interrupts : Should contain I2S interrupt
-- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
-  request selector for this I2S controller
-
-Example:
-
-i2s@70002800 {
-        compatible = "nvidia,tegra20-i2s";
-        reg = <0x70002800 0x200>;
-        interrupts = < 45 >;
-        nvidia,dma-request-selector = < &apbdma 2 >;
-};
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
deleted file mode 100644
index 1ac7b164218..00000000000
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
+++ /dev/null
@@ -1,32 +0,0 @@
-NVIDIA Tegra30 AHUB (Audio Hub)
-
-Required properties:
-- compatible : "nvidia,tegra30-ahub"
-- reg : Should contain the register physical address and length for each of
-  the AHUB's APBIF registers and the AHUB's own registers.
-- interrupts : Should contain AHUB interrupt
-- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
-  request selector for the first APBIF channel.
-- ranges : The bus address mapping for the configlink register bus.
-  Can be empty since the mapping is 1:1.
-- #address-cells : For the configlink bus. Should be <1>;
-- #size-cells : For the configlink bus. Should be <1>.
-
-AHUB client modules need to specify the IDs of their CIFs (Client InterFaces).
-For RX CIFs, the numbers indicate the register number within AHUB routing
-register space (APBIF 0..3 RX, I2S 0..5 RX, DAM 0..2 RX 0..1, SPDIF RX 0..1).
-For TX CIFs, the numbers indicate the bit position within the AHUB routing
-registers (APBIF 0..3 TX, I2S 0..5 TX, DAM 0..2 TX, SPDIF TX 0..1).
-
-Example:
-
-ahub@70080000 {
-        compatible = "nvidia,tegra30-ahub";
-        reg = <0x70080000 0x200 0x70080200 0x100>;
-        interrupts = < 0 103 0x04 >;
-        nvidia,dma-request-selector = <&apbdma 1>;
-
-        ranges;
-        #address-cells = <1>;
-        #size-cells = <1>;
-};
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
deleted file mode 100644
index dfa6c037124..00000000000
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-NVIDIA Tegra30 I2S controller
-
-Required properties:
-- compatible : "nvidia,tegra30-i2s"
-- reg : Should contain I2S registers location and length
-- nvidia,ahub-cif-ids : The list of AHUB CIF IDs for this port, rx (playback)
-  first, tx (capture) second. See nvidia,tegra30-ahub.txt for values.
-
-Example:
-
-i2s@70002800 {
-        compatible = "nvidia,tegra30-i2s";
-        reg = <0x70080300 0x100>;
-        nvidia,ahub-cif-ids = <4 4>;
-};
diff --git a/Documentation/devicetree/bindings/sound/omap-abe-twl6040.txt b/Documentation/devicetree/bindings/sound/omap-abe-twl6040.txt
deleted file mode 100644
index fd40c852d7c..00000000000
--- a/Documentation/devicetree/bindings/sound/omap-abe-twl6040.txt
+++ /dev/null
@@ -1,91 +0,0 @@
-* Texas Instruments OMAP4+ and twl6040 based audio setups
-
-Required properties:
-- compatible: "ti,abe-twl6040"
-- ti,model: Name of the sound card ( for example "SDP4430")
-- ti,mclk-freq: MCLK frequency for HPPLL operation
-- ti,mcpdm: phandle for the McPDM node
-- ti,twl6040: phandle for the twl6040 core node
-- ti,audio-routing: List of connections between audio components.
-  Each entry is a pair of strings, the first being the connection's sink,
-  the second being the connection's source.
-
-Optional properties:
-- ti,dmic: phandle for the OMAP dmic node if the machine have it connected
-- ti,jack_detection: Need to be present if the board capable to detect jack
-  insertion, removal.
-
-Available audio endpoints for the audio-routing table:
-
-Board connectors:
- * Headset Stereophone
- * Earphone Spk
- * Ext Spk
- * Line Out
- * Vibrator
- * Headset Mic
- * Main Handset Mic
- * Sub Handset Mic
- * Line In
- * Digital Mic
-
-twl6040 pins:
- * HSOL
- * HSOR
- * EP
- * HFL
- * HFR
- * AUXL
- * AUXR
- * VIBRAL
- * VIBRAR
- * HSMIC
- * MAINMIC
- * SUBMIC
- * AFML
- * AFMR
-
- * Headset Mic Bias
- * Main Mic Bias
- * Digital Mic1 Bias
- * Digital Mic2 Bias
-
-Digital mic pins:
- * DMic
-
-Example:
-
-sound {
-        compatible = "ti,abe-twl6040";
-        ti,model = "SDP4430";
-
-        ti,jack-detection;
-        ti,mclk-freq = <38400000>;
-
-        ti,mcpdm = <&mcpdm>;
-        ti,dmic = <&dmic>;
-
-        ti,twl6040 = <&twl6040>;
-
-        /* Audio routing */
-        ti,audio-routing =
-                "Headset Stereophone", "HSOL",
-                "Headset Stereophone", "HSOR",
-                "Earphone Spk", "EP",
-                "Ext Spk", "HFL",
-                "Ext Spk", "HFR",
-                "Line Out", "AUXL",
-                "Line Out", "AUXR",
-                "Vibrator", "VIBRAL",
-                "Vibrator", "VIBRAR",
-                "HSMIC", "Headset Mic",
-                "Headset Mic", "Headset Mic Bias",
-                "MAINMIC", "Main Handset Mic",
-                "Main Handset Mic", "Main Mic Bias",
-                "SUBMIC", "Sub Handset Mic",
-                "Sub Handset Mic", "Main Mic Bias",
-                "AFML", "Line In",
-                "AFMR", "Line In",
-                "DMic", "Digital Mic",
-                "Digital Mic", "Digital Mic1 Bias";
-};
diff --git a/Documentation/devicetree/bindings/sound/omap-dmic.txt b/Documentation/devicetree/bindings/sound/omap-dmic.txt
deleted file mode 100644
index fd8105f1897..00000000000
--- a/Documentation/devicetree/bindings/sound/omap-dmic.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-* Texas Instruments OMAP4+ Digital Microphone Module
-
-Required properties:
-- compatible: "ti,omap4-dmic"
-- reg: Register location and size as an array:
-       <MPU access base address, size>,
-       <L3 interconnect address, size>;
-- interrupts: Interrupt number for DMIC
-- interrupt-parent: The parent interrupt controller
-- ti,hwmods: Name of the hwmod associated with OMAP dmic IP
-
-Example:
-
-dmic: dmic@4012e000 {
-        compatible = "ti,omap4-dmic";
-        reg = <0x4012e000 0x7f>, /* MPU private access */
-              <0x4902e000 0x7f>; /* L3 Interconnect */
-        interrupts = <0 114 0x4>;
-        interrupt-parent = <&gic>;
-        ti,hwmods = "dmic";
-};
diff --git a/Documentation/devicetree/bindings/sound/omap-mcbsp.txt b/Documentation/devicetree/bindings/sound/omap-mcbsp.txt
deleted file mode 100644
index 17cce449045..00000000000
--- a/Documentation/devicetree/bindings/sound/omap-mcbsp.txt
+++ /dev/null
@@ -1,37 +0,0 @@
-* Texas Instruments OMAP2+ McBSP module
-
-Required properties:
-- compatible: "ti,omap2420-mcbsp" for McBSP on OMAP2420
-              "ti,omap2430-mcbsp" for McBSP on OMAP2430
-              "ti,omap3-mcbsp" for McBSP on OMAP3
-              "ti,omap4-mcbsp" for McBSP on OMAP4 and newer SoC
-- reg: Register location and size, for OMAP4+ as an array:
-       <MPU access base address, size>,
-       <L3 interconnect address, size>;
-- reg-names: Array of strings associated with the address space
-- interrupts: Interrupt numbers for the McBSP port, as an array in case the
-              McBSP IP have more interrupt lines:
-        <OCP compliant irq>,
-        <TX irq>,
-        <RX irq>;
-- interrupt-names: Array of strings associated with the interrupt numbers
-- interrupt-parent: The parent interrupt controller
-- ti,buffer-size: Size of the FIFO on the port (OMAP2430 and newer SoC)
-- ti,hwmods: Name of the hwmod associated to the McBSP port
-
-Example:
-
-mcbsp2: mcbsp@49022000 {
-        compatible = "ti,omap3-mcbsp";
-        reg = <0x49022000 0xff>,
-              <0x49028000 0xff>;
-        reg-names = "mpu", "sidetone";
-        interrupts = <0 17 0x4>, /* OCP compliant interrupt */
-                     <0 62 0x4>, /* TX interrupt */
-                     <0 63 0x4>, /* RX interrupt */
-                     <0 4 0x4>;  /* Sidetone */
-        interrupt-names = "common", "tx", "rx", "sidetone";
-        interrupt-parent = <&intc>;
-        ti,buffer-size = <1280>;
-        ti,hwmods = "mcbsp2";
-};
diff --git a/Documentation/devicetree/bindings/sound/omap-mcpdm.txt b/Documentation/devicetree/bindings/sound/omap-mcpdm.txt
deleted file mode 100644
index 0741dff048d..00000000000
--- a/Documentation/devicetree/bindings/sound/omap-mcpdm.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-* Texas Instruments OMAP4+ McPDM
-
-Required properties:
-- compatible: "ti,omap4-mcpdm"
-- reg: Register location and size as an array:
-       <MPU access base address, size>,
-       <L3 interconnect address, size>;
-- interrupts: Interrupt number for McPDM
-- interrupt-parent: The parent interrupt controller
-- ti,hwmods: Name of the hwmod associated to the McPDM
-
-Example:
-
-mcpdm: mcpdm@40132000 {
-        compatible = "ti,omap4-mcpdm";
-        reg = <0x40132000 0x7f>, /* MPU private access */
-              <0x49032000 0x7f>; /* L3 Interconnect */
-        interrupts = <0 112 0x4>;
-        interrupt-parent = <&gic>;
-        ti,hwmods = "mcpdm";
-};
diff --git a/Documentation/devicetree/bindings/sound/omap-twl4030.txt b/Documentation/devicetree/bindings/sound/omap-twl4030.txt
deleted file mode 100644
index 6fae51c7f76..00000000000
--- a/Documentation/devicetree/bindings/sound/omap-twl4030.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-* Texas Instruments SoC with twl4030 based audio setups
-
-Required properties:
-- compatible: "ti,omap-twl4030"
-- ti,model: Name of the sound card (for example "omap3beagle")
-- ti,mcbsp: phandle for the McBSP node
-- ti,codec: phandle for the twl4030 audio node
-
-Example:
-
-sound {
-        compatible = "ti,omap-twl4030";
-        ti,model = "omap3beagle";
-
-        ti,mcbsp = <&mcbsp2>;
-        ti,codec = <&twl_audio>;
-};
diff --git a/Documentation/devicetree/bindings/sound/sgtl5000.txt b/Documentation/devicetree/bindings/sound/sgtl5000.txt
deleted file mode 100644
index 9cc44449508..00000000000
--- a/Documentation/devicetree/bindings/sound/sgtl5000.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-* Freescale SGTL5000 Stereo Codec
-
-Required properties:
-- compatible : "fsl,sgtl5000".
-
-- reg : the I2C address of the device
-
-Example:
-
-codec: sgtl5000@0a {
-        compatible = "fsl,sgtl5000";
-        reg = <0x0a>;
-};
diff --git a/Documentation/devicetree/bindings/sound/tlv320aic3x.txt b/Documentation/devicetree/bindings/sound/tlv320aic3x.txt
deleted file mode 100644
index e7b98f41fa5..00000000000
--- a/Documentation/devicetree/bindings/sound/tlv320aic3x.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-Texas Instruments - tlv320aic3x Codec module
-
-The tlv320aic3x serial control bus communicates through I2C protocols
-
-Required properties:
-- compatible - "string" -  "ti,tlv320aic3x"
-- reg - <int> -  I2C slave address
-
-
-Optional properties:
-
-- gpio-reset - gpio pin number used for codec reset
-- ai3x-gpio-func - <array of 2 int> - AIC3X_GPIO1 & AIC3X_GPIO2 Functionality
-
-Example:
-
-tlv320aic3x: tlv320aic3x@1b {
-        compatible = "ti,tlv320aic3x";
-        reg = <0x1b>;
-};
diff --git a/Documentation/devicetree/bindings/sound/ux500-mop500.txt b/Documentation/devicetree/bindings/sound/ux500-mop500.txt
deleted file mode 100644
index 48e071c96b4..00000000000
--- a/Documentation/devicetree/bindings/sound/ux500-mop500.txt
+++ /dev/null
@@ -1,39 +0,0 @@
-* MOP500 Audio Machine Driver
-
-This node is responsible for linking together all ux500 Audio Driver components.
-
-Required properties:
- - compatible              : "stericsson,snd-soc-mop500"
-
-Non-standard properties:
- - stericsson,cpu-dai      : Phandle to the CPU-side DAI
- - stericsson,audio-codec  : Phandle to the Audio CODEC
- - stericsson,card-name    : Over-ride default card name
-
-Example:
-
-        sound {
-                compatible = "stericsson,snd-soc-mop500";
-
-                stericsson,cpu-dai = <&msp1 &msp3>;
-                stericsson,audio-codec = <&codec>;
-        };
-
-        msp1: msp@80124000 {
-                compatible = "stericsson,ux500-msp-i2s";
-                reg = <0x80124000 0x1000>;
-                interrupts = <0 62 0x4>;
-                v-ape-supply = <&db8500_vape_reg>;
-        };
-
-        msp3: msp@80125000 {
-                compatible = "stericsson,ux500-msp-i2s";
-                reg = <0x80125000 0x1000>;
-                interrupts = <0 62 0x4>;
-                v-ape-supply = <&db8500_vape_reg>;
-        };
-
-        codec: ab8500-codec {
-                compatible = "stericsson,ab8500-codec";
-                stericsson,earpeice-cmv = <950>; /* Units in mV. */
-        };
diff --git a/Documentation/devicetree/bindings/sound/ux500-msp.txt b/Documentation/devicetree/bindings/sound/ux500-msp.txt
deleted file mode 100644
index 99acd9c774e..00000000000
--- a/Documentation/devicetree/bindings/sound/ux500-msp.txt
+++ /dev/null
@@ -1,43 +0,0 @@
-* ux500 MSP (CPU-side Digital Audio Interface)
-
-Required properties:
- - compatible       :"stericsson,ux500-msp-i2s"
- - reg              : Physical base address and length of the device's registers.
-
-Optional properties:
- - interrupts       : The interrupt output from the device.
- - interrupt-parent : The parent interrupt controller.
- - <name>-supply    : Phandle to the regulator <name> supply
-
-Example:
-
-        sound {
-                compatible = "stericsson,snd-soc-mop500";
-
-                stericsson,platform-pcm-dma = <&pcm>;
-                stericsson,cpu-dai = <&msp1 &msp3>;
-                stericsson,audio-codec = <&codec>;
-        };
-
-        pcm: ux500-pcm {
-                compatible = "stericsson,ux500-pcm";
-        };
-
-        msp1: msp@80124000 {
-                compatible = "stericsson,ux500-msp-i2s";
-                reg = <0x80124000 0x1000>;
-                interrupts = <0 62 0x4>;
-                v-ape-supply = <&db8500_vape_reg>;
-        };
-
-        msp3: msp@80125000 {
-                compatible = "stericsson,ux500-msp-i2s";
-                reg = <0x80125000 0x1000>;
-                interrupts = <0 62 0x4>;
-                v-ape-supply = <&db8500_vape_reg>;
-        };
-
-        codec: ab8500-codec {
-                compatible = "stericsson,ab8500-codec";
-                stericsson,earpeice-cmv = <950>; /* Units in mV. */
-        };
diff --git a/Documentation/devicetree/bindings/sound/wm8510.txt b/Documentation/devicetree/bindings/sound/wm8510.txt
deleted file mode 100644
index fa1a32b8557..00000000000
--- a/Documentation/devicetree/bindings/sound/wm8510.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-WM8510 audio CODEC
-
-This device supports both I2C and SPI (configured with pin strapping
-on the board).
-
-Required properties:
-
-  - compatible : "wlf,wm8510"
-
-  - reg : the I2C address of the device for I2C, the chip select
-          number for SPI.
-
-Example:
-
-codec: wm8510@1a {
-        compatible = "wlf,wm8510";
-        reg = <0x1a>;
-};
diff --git a/Documentation/devicetree/bindings/sound/wm8523.txt b/Documentation/devicetree/bindings/sound/wm8523.txt
deleted file mode 100644
index 04746186b28..00000000000
--- a/Documentation/devicetree/bindings/sound/wm8523.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-WM8523 audio CODEC
-
-This device supports I2C only.
-
-Required properties:
-
-  - compatible : "wlf,wm8523"
-
-  - reg : the I2C address of the device.
-
-Example:
-
-codec: wm8523@1a {
-        compatible = "wlf,wm8523";
-        reg = <0x1a>;
-};
diff --git a/Documentation/devicetree/bindings/sound/wm8580.txt b/Documentation/devicetree/bindings/sound/wm8580.txt
deleted file mode 100644
index 7d9821f348d..00000000000
--- a/Documentation/devicetree/bindings/sound/wm8580.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-WM8580 audio CODEC
-
-This device supports I2C only.
-
-Required properties:
-
-  - compatible : "wlf,wm8580"
-
-  - reg : the I2C address of the device.
-
-Example:
-
-codec: wm8580@1a {
-        compatible = "wlf,wm8580";
-        reg = <0x1a>;
-};
diff --git a/Documentation/devicetree/bindings/sound/wm8711.txt b/Documentation/devicetree/bindings/sound/wm8711.txt
deleted file mode 100644
index 8ed9998cd23..00000000000
--- a/Documentation/devicetree/bindings/sound/wm8711.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-WM8711 audio CODEC
-
-This device supports both I2C and SPI (configured with pin strapping
-on the board).
-
-Required properties:
-
-  - compatible : "wlf,wm8711"
-
-  - reg : the I2C address of the device for I2C, the chip select
-          number for SPI.
-
-Example:
-
-codec: wm8711@1a {
-        compatible = "wlf,wm8711";
-        reg = <0x1a>;
-};
diff --git a/Documentation/devicetree/bindings/sound/wm8728.txt b/Documentation/devicetree/bindings/sound/wm8728.txt
deleted file mode 100644
index a8b5c3668e6..00000000000
--- a/Documentation/devicetree/bindings/sound/wm8728.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-WM8728 audio CODEC
-
-This device supports both I2C and SPI (configured with pin strapping
-on the board).
-
-Required properties:
-
-  - compatible : "wlf,wm8728"
-
-  - reg : the I2C address of the device for I2C, the chip select
-          number for SPI.
-
-Example:
-
-codec: wm8728@1a {
-        compatible = "wlf,wm8728";
-        reg = <0x1a>;
-};
diff --git a/Documentation/devicetree/bindings/sound/wm8731.txt b/Documentation/devicetree/bindings/sound/wm8731.txt
deleted file mode 100644
index 15f70048469..00000000000
--- a/Documentation/devicetree/bindings/sound/wm8731.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-WM8731 audio CODEC
-
-This device supports both I2C and SPI (configured with pin strapping
-on the board).
-
-Required properties:
-
-  - compatible : "wlf,wm8731"
-
-  - reg : the I2C address of the device for I2C, the chip select
-          number for SPI.
-
-Example:
-
-codec: wm8731@1a {
-        compatible = "wlf,wm8731";
-        reg = <0x1a>;
-};
diff --git a/Documentation/devicetree/bindings/sound/wm8737.txt b/Documentation/devicetree/bindings/sound/wm8737.txt
deleted file mode 100644
index 4bc2cea3b14..00000000000
--- a/Documentation/devicetree/bindings/sound/wm8737.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-WM8737 audio CODEC
-
-This device supports both I2C and SPI (configured with pin strapping
-on the board).
-
-Required properties:
-
-  - compatible : "wlf,wm8737"
-
-  - reg : the I2C address of the device for I2C, the chip select
-          number for SPI.
-
-Example:
-
-codec: wm8737@1a {
-        compatible = "wlf,wm8737";
-        reg = <0x1a>;
-};
diff --git a/Documentation/devicetree/bindings/sound/wm8741.txt b/Documentation/devicetree/bindings/sound/wm8741.txt
deleted file mode 100644
index 74bda58c1bc..00000000000
--- a/Documentation/devicetree/bindings/sound/wm8741.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-WM8741 audio CODEC
-
-This device supports both I2C and SPI (configured with pin strapping
-on the board).
-
-Required properties:
-
-  - compatible : "wlf,wm8741"
-
-  - reg : the I2C address of the device for I2C, the chip select
-          number for SPI.
-
-Example:
-
-codec: wm8741@1a {
-        compatible = "wlf,wm8741";
-        reg = <0x1a>;
-};
diff --git a/Documentation/devicetree/bindings/sound/wm8750.txt b/Documentation/devicetree/bindings/sound/wm8750.txt
deleted file mode 100644
index 8db239fd5ec..00000000000
--- a/Documentation/devicetree/bindings/sound/wm8750.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-WM8750 and WM8987 audio CODECs
-
-These devices support both I2C and SPI (configured with pin strapping
-on the board).
-
-Required properties:
-
-  - compatible : "wlf,wm8750" or "wlf,wm8987"
-
-  - reg : the I2C address of the device for I2C, the chip select
-          number for SPI.
-
-Example:
-
-codec: wm8750@1a {
-        compatible = "wlf,wm8750";
-        reg = <0x1a>;
-};
diff --git a/Documentation/devicetree/bindings/sound/wm8753.txt b/Documentation/devicetree/bindings/sound/wm8753.txt
deleted file mode 100644
index e65277a0fb6..00000000000
--- a/Documentation/devicetree/bindings/sound/wm8753.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-WM8753 audio CODEC
-
-This device supports both I2C and SPI (configured with pin strapping
-on the board).
-
-Required properties:
-
-  - compatible : "wlf,wm8753"
-
-  - reg : the I2C address of the device for I2C, the chip select
-          number for SPI.
-
-Example:
-
-codec: wm8737@1a {
-        compatible = "wlf,wm8753";
-        reg = <0x1a>;
-};
diff --git a/Documentation/devicetree/bindings/sound/wm8770.txt b/Documentation/devicetree/bindings/sound/wm8770.txt
deleted file mode 100644
index 866e00ca150..00000000000
--- a/Documentation/devicetree/bindings/sound/wm8770.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-WM8770 audio CODEC
-
-This device supports SPI.
-
-Required properties:
-
-  - compatible : "wlf,wm8770"
-
-  - reg : the chip select number.
-
-Example:
-
-codec: wm8770@1 {
-        compatible = "wlf,wm8770";
-        reg = <1>;
-};
diff --git a/Documentation/devicetree/bindings/sound/wm8776.txt b/Documentation/devicetree/bindings/sound/wm8776.txt
deleted file mode 100644
index 3b9ca49abc2..00000000000
--- a/Documentation/devicetree/bindings/sound/wm8776.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-WM8776 audio CODEC
-
-This device supports both I2C and SPI (configured with pin strapping
-on the board).
-
-Required properties:
-
-  - compatible : "wlf,wm8776"
-
-  - reg : the I2C address of the device for I2C, the chip select
-          number for SPI.
-
-Example:
-
-codec: wm8776@1a {
-        compatible = "wlf,wm8776";
-        reg = <0x1a>;
-};
diff --git a/Documentation/devicetree/bindings/sound/wm8804.txt b/Documentation/devicetree/bindings/sound/wm8804.txt
deleted file mode 100644
index 4d3a56f38ad..00000000000
--- a/Documentation/devicetree/bindings/sound/wm8804.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-WM8804 audio CODEC
-
-This device supports both I2C and SPI (configured with pin strapping
-on the board).
-
-Required properties:
-
-  - compatible : "wlf,wm8804"
-
-  - reg : the I2C address of the device for I2C, the chip select
-          number for SPI.
-
-Example:
-
-codec: wm8804@1a {
-        compatible = "wlf,wm8804";
-        reg = <0x1a>;
-};
diff --git a/Documentation/devicetree/bindings/sound/wm8903.txt b/Documentation/devicetree/bindings/sound/wm8903.txt
deleted file mode 100644
index f102cbc4269..00000000000
--- a/Documentation/devicetree/bindings/sound/wm8903.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-WM8903 audio CODEC
-
-This device supports I2C only.
-
-Required properties:
-
-  - compatible : "wlf,wm8903"
-
-  - reg : the I2C address of the device.
-
-  - gpio-controller : Indicates this device is a GPIO controller.
-
-  - #gpio-cells : Should be two. The first cell is the pin number and the
-    second cell is used to specify optional parameters (currently unused).
-
-Optional properties:
-
-  - interrupts : The interrupt line the codec is connected to.
-
-  - micdet-cfg : Default register value for R6 (Mic Bias). If absent, the
-    default is 0.
-
-  - micdet-delay : The debounce delay for microphone detection in mS. If
-    absent, the default is 100.
-
-  - gpio-cfg : A list of GPIO configuration register values. The list must
-    be 5 entries long. If absent, no configuration of these registers is
-    performed. If any entry has the value 0xffffffff, that GPIO's
-    configuration will not be modified.
-
-Example:
-
-codec: wm8903@1a {
-        compatible = "wlf,wm8903";
-        reg = <0x1a>;
-        interrupts = < 347 >;
-
-        gpio-controller;
-        #gpio-cells = <2>;
-
-        micdet-cfg = <0>;
-        micdet-delay = <100>;
-        gpio-cfg = <
-                0x0600 /* DMIC_LR, output */
-                0x0680 /* DMIC_DAT, input */
-                0x0000 /* GPIO, output, low */
-                0x0200 /* Interrupt, output */
-                0x01a0 /* BCLK, input, active high */
-        >;
-};
diff --git a/Documentation/devicetree/bindings/sound/wm8994.txt b/Documentation/devicetree/bindings/sound/wm8994.txt
deleted file mode 100644
index 7a7eb1e7bda..00000000000
--- a/Documentation/devicetree/bindings/sound/wm8994.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-WM1811/WM8994/WM8958 audio CODEC
-
-These devices support both I2C and SPI (configured with pin strapping
-on the board).
-
-Required properties:
-
-  - compatible : "wlf,wm1811", "wlf,wm8994", "wlf,wm8958"
-
-  - reg : the I2C address of the device for I2C, the chip select
-          number for SPI.
-
-Example:
-
-codec: wm8994@1a {
-        compatible = "wlf,wm8994";
-        reg = <0x1a>;
-};
diff --git a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt
index 4256a6df9b7..9841057d112 100644
--- a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt
+++ b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt
@@ -17,6 +17,6 @@ ecspi@70010000 {
         reg = <0x70010000 0x4000>;
         interrupts = <36>;
         fsl,spi-num-chipselects = <2>;
-        cs-gpios = <&gpio3 24 0>, /* GPIO3_24 */
-                   <&gpio3 25 0>; /* GPIO3_25 */
+        cs-gpios = <&gpio3 24 0>, /* GPIO4_24 */
+                   <&gpio3 25 0>; /* GPIO4_25 */
 };
diff --git a/Documentation/devicetree/bindings/spi/mxs-spi.txt b/Documentation/devicetree/bindings/spi/mxs-spi.txt
deleted file mode 100644
index e2e13957c2a..00000000000
--- a/Documentation/devicetree/bindings/spi/mxs-spi.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-* Freescale MX233/MX28 SSP/SPI
-
-Required properties:
-- compatible: Should be "fsl,<soc>-spi", where soc is "imx23" or "imx28"
-- reg: Offset and length of the register set for the device
-- interrupts: Should contain SSP interrupts (error irq first, dma irq second)
-- fsl,ssp-dma-channel: APBX DMA channel for the SSP
-
-Optional properties:
-- clock-frequency : Input clock frequency to the SPI block in Hz.
-                    Default is 160000000 Hz.
-
-Example:
-
-ssp0: ssp@80010000 {
-        #address-cells = <1>;
-        #size-cells = <0>;
-        compatible = "fsl,imx28-spi";
-        reg = <0x80010000 0x2000>;
-        interrupts = <96 82>;
-        fsl,ssp-dma-channel = <0>;
-};
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
deleted file mode 100644
index 7b53da5cb75..00000000000
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-NVIDIA Tegra20 SFLASH controller.
-
-Required properties:
-- compatible : should be "nvidia,tegra20-sflash".
-- reg: Should contain SFLASH registers location and length.
-- interrupts: Should contain SFLASH interrupts.
-- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
-  request selector for this SFLASH controller.
-
-Recommended properties:
-- spi-max-frequency: Definition as per
-                     Documentation/devicetree/bindings/spi/spi-bus.txt
-
-Example:
-
-spi@7000c380 {
-        compatible = "nvidia,tegra20-sflash";
-        reg = <0x7000c380 0x80>;
-        interrupts = <0 39 0x04>;
-        nvidia,dma-request-selector = <&apbdma 16>;
-        spi-max-frequency = <25000000>;
-        #address-cells = <1>;
-        #size-cells = <0>;
-        status = "disabled";
-};
-
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
deleted file mode 100644
index eefe15e3d95..00000000000
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-NVIDIA Tegra20/Tegra30 SLINK controller.
-
-Required properties:
-- compatible : should be "nvidia,tegra20-slink", "nvidia,tegra30-slink".
-- reg: Should contain SLINK registers location and length.
-- interrupts: Should contain SLINK interrupts.
-- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
-  request selector for this SLINK controller.
-
-Recommended properties:
-- spi-max-frequency: Definition as per
-                     Documentation/devicetree/bindings/spi/spi-bus.txt
-
-Example:
-
-spi@7000d600 {
-        compatible = "nvidia,tegra20-slink";
-        reg = <0x7000d600 0x200>;
-        interrupts = <0 82 0x04>;
-        nvidia,dma-request-selector = <&apbdma 16>;
-        spi-max-frequency = <25000000>;
-        #address-cells = <1>;
-        #size-cells = <0>;
-        status = "disabled";
-};
-
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-spi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-spi.txt
deleted file mode 100644
index 6b9e5189669..00000000000
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-spi.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-NVIDIA Tegra 2 SPI device
-
-Required properties:
-- compatible : should be "nvidia,tegra20-spi".
-- gpios : should specify GPIOs used for chipselect.
diff --git a/Documentation/devicetree/bindings/spi/omap-spi.txt b/Documentation/devicetree/bindings/spi/omap-spi.txt
deleted file mode 100644
index 938809c6829..00000000000
--- a/Documentation/devicetree/bindings/spi/omap-spi.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-OMAP2+ McSPI device
-
-Required properties:
-- compatible :
-  - "ti,omap2-spi" for OMAP2 & OMAP3.
-  - "ti,omap4-spi" for OMAP4+.
-- ti,spi-num-cs : Number of chipselect supported  by the instance.
-- ti,hwmods: Name of the hwmod associated to the McSPI
-- ti,pindir-d0-out-d1-in: Select the D0 pin as output and D1 as
-                          input. The default is D0 as input and
-                          D1 as output.
-
-Example:
-
-mcspi1: mcspi@1 {
-    #address-cells = <1>;
-    #size-cells = <0>;
-    compatible = "ti,omap4-mcspi";
-    ti,hwmods = "mcspi1";
-    ti,spi-num-cs = <4>;
-};
-
diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt
index 296015e3c63..e782add2e45 100644
--- a/Documentation/devicetree/bindings/spi/spi-bus.txt
+++ b/Documentation/devicetree/bindings/spi/spi-bus.txt
@@ -12,7 +12,6 @@ The SPI master node requires the following properties:
 - #size-cells     - should be zero.
 - compatible      - name of SPI bus controller following generic names
                 recommended practice.
-- cs-gpios        - (optional) gpios chip select.
 No other properties are required in the SPI bus node.  It is assumed
 that a driver for an SPI bus device will understand that it is an SPI bus.
 However, the binding does not attempt to define the specific method for
@@ -22,25 +21,6 @@ assumption that board specific platform code will be used to manage
 chip selects.  Individual drivers can define additional properties to
 support describing the chip select layout.
 
-Optional property:
-- num-cs : total number of chipselects
-
-If cs-gpios is used the number of chip select will automatically increased
-with max(cs-gpios > hw cs)
-
-So if for example the controller has 2 CS lines, and the cs-gpios
-property looks like this:
-
-cs-gpios = <&gpio1 0 0> <0> <&gpio1 1 0> <&gpio1 2 0>;
-
-Then it should be configured so that num_chipselect = 4 with the
-following mapping:
-
-cs0 : &gpio1 0 0
-cs1 : native
-cs2 : &gpio1 1 0
-cs3 : &gpio1 2 0
-
 SPI slave nodes must be children of the SPI master node and can
 contain the following properties.
 - reg             - (required) chip select address of device.
@@ -53,11 +33,6 @@ contain the following properties.
                 shifted clock phase (CPHA) mode
 - spi-cs-high     - (optional) Empty property indicating device requires
                 chip select active high
-- spi-3wire       - (optional) Empty property indicating device requires
-                    3-wire mode.
-
-If a gpio chipselect is used for the SPI slave the gpio number will be passed
-via the cs_gpio
 
 SPI example for an MPC5200 SPI bus:
         spi@f00 {
diff --git a/Documentation/devicetree/bindings/spi/spi-gpio.txt b/Documentation/devicetree/bindings/spi/spi-gpio.txt
deleted file mode 100644
index 8a824be1575..00000000000
--- a/Documentation/devicetree/bindings/spi/spi-gpio.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-SPI-GPIO devicetree bindings
-
-Required properties:
-
- - compatible: should be set to "spi-gpio"
- - #address-cells: should be set to <0x1>
- - ranges
- - gpio-sck: GPIO spec for the SCK line to use
- - gpio-miso: GPIO spec for the MISO line to use
- - gpio-mosi: GPIO spec for the MOSI line to use
- - cs-gpios: GPIOs to use for chipselect lines
- - num-chipselects: number of chipselect lines
-
-Example:
-
-        spi {
-                compatible = "spi-gpio";
-                #address-cells = <0x1>;
-                ranges;
-
-                gpio-sck = <&gpio 95 0>;
-                gpio-miso = <&gpio 98 0>;
-                gpio-mosi = <&gpio 97 0>;
-                cs-gpios = <&gpio 125 0>;
-                num-chipselects = <1>;
-
-                /* clients */
-        };
-
diff --git a/Documentation/devicetree/bindings/spi/spi-octeon.txt b/Documentation/devicetree/bindings/spi/spi-octeon.txt
deleted file mode 100644
index 431add19234..00000000000
--- a/Documentation/devicetree/bindings/spi/spi-octeon.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-Cavium, Inc. OCTEON SOC SPI master controller.
-
-Required properties:
-- compatible : "cavium,octeon-3010-spi"
-- reg : The register base for the controller.
-- interrupts : One interrupt, used by the controller.
-- #address-cells : <1>, as required by generic SPI binding.
-- #size-cells : <0>, also as required by generic SPI binding.
-
-Child nodes as per the generic SPI binding.
-
-Example:
-
-        spi@1070000001000 {
-                compatible = "cavium,octeon-3010-spi";
-                reg = <0x10700 0x00001000 0x0 0x100>;
-                interrupts = <0 58>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                eeprom@0 {
-                        compatible = "st,m95256", "atmel,at25";
-                        reg = <0>;
-                        spi-max-frequency = <5000000>;
-                        spi-cpha;
-                        spi-cpol;
-
-                        pagesize = <64>;
-                        size = <32768>;
-                        address-width = <16>;
-                };
-        };
-
diff --git a/Documentation/devicetree/bindings/spi/spi-orion.txt b/Documentation/devicetree/bindings/spi/spi-orion.txt
deleted file mode 100644
index a3ff50fc76f..00000000000
--- a/Documentation/devicetree/bindings/spi/spi-orion.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-Marvell Orion SPI device
-
-Required properties:
-- compatible : should be "marvell,orion-spi".
-- reg : offset and length of the register set for the device
-- cell-index : Which of multiple SPI controllers is this.
-Optional properties:
-- interrupts : Is currently not used.
-
-Example:
-       spi@10600 {
-               compatible = "marvell,orion-spi";
-               #address-cells = <1>;
-               #size-cells = <0>;
-               cell-index = <0>;
-               reg = <0x10600 0x28>;
-               interrupts = <23>;
-               status = "disabled";
-       };
diff --git a/Documentation/devicetree/bindings/spi/spi-samsung.txt b/Documentation/devicetree/bindings/spi/spi-samsung.txt
deleted file mode 100644
index a15ffeddfba..00000000000
--- a/Documentation/devicetree/bindings/spi/spi-samsung.txt
+++ /dev/null
@@ -1,116 +0,0 @@
-* Samsung SPI Controller
-
-The Samsung SPI controller is used to interface with various devices such as flash
-and display controllers using the SPI communication interface.
-
-Required SoC Specific Properties:
-
-- compatible: should be one of the following.
-    - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms
-    - samsung,s3c6410-spi: for s3c6410 platforms
-    - samsung,s5p6440-spi: for s5p6440 and s5p6450 platforms
-    - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
-    - samsung,exynos4210-spi: for exynos4 and exynos5 platforms
-
-- reg: physical base address of the controller and length of memory mapped
-  region.
-
-- interrupts: The interrupt number to the cpu. The interrupt specifier format
-  depends on the interrupt controller.
-
-[PRELIMINARY: the dma channel allocation will change once there are
-official DMA bindings]
-
-- tx-dma-channel: The dma channel specifier for tx operations. The format of
-  the dma specifier depends on the dma controller.
-
-- rx-dma-channel: The dma channel specifier for rx operations. The format of
-  the dma specifier depends on the dma controller.
-
-Required Board Specific Properties:
-
-- #address-cells: should be 1.
-- #size-cells: should be 0.
-- gpios: The gpio specifier for clock, mosi and miso interface lines (in the
-  order specified). The format of the gpio specifier depends on the gpio
-  controller.
-
-Optional Board Specific Properties:
-
-- samsung,spi-src-clk: If the spi controller includes a internal clock mux to
-  select the clock source for the spi bus clock, this property can be used to
-  indicate the clock to be used for driving the spi bus clock. If not specified,
-  the clock number 0 is used as default.
-
-- num-cs: Specifies the number of chip select lines supported. If
-  not specified, the default number of chip select lines is set to 1.
-
-SPI Controller specific data in SPI slave nodes:
-
-- The spi slave nodes should provide the following information which is required
-  by the spi controller.
-
-  - cs-gpio: A gpio specifier that specifies the gpio line used as
-    the slave select line by the spi controller. The format of the gpio
-    specifier depends on the gpio controller.
-
-  - samsung,spi-feedback-delay: The sampling phase shift to be applied on the
-    miso line (to account for any lag in the miso line). The following are the
-    valid values.
-
-      - 0: No phase shift.
-      - 1: 90 degree phase shift sampling.
-      - 2: 180 degree phase shift sampling.
-      - 3: 270 degree phase shift sampling.
-
-Aliases:
-
-- All the SPI controller nodes should be represented in the aliases node using
-  the following format 'spi{n}' where n is a unique number for the alias.
-
-
-Example:
-
-- SoC Specific Portion:
-
-        spi_0: spi@12d20000 {
-                compatible = "samsung,exynos4210-spi";
-                reg = <0x12d20000 0x100>;
-                interrupts = <0 66 0>;
-                tx-dma-channel = <&pdma0 5>;
-                rx-dma-channel = <&pdma0 4>;
-        };
-
-- Board Specific Portion:
-
-        spi_0: spi@12d20000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                gpios = <&gpa2 4 2 3 0>,
-                        <&gpa2 6 2 3 0>,
-                        <&gpa2 7 2 3 0>;
-
-                w25q80bw@0 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "w25x80";
-                        reg = <0>;
-                        spi-max-frequency = <10000>;
-
-                        controller-data {
-                                cs-gpio = <&gpa2 5 1 0 3>;
-                                samsung,spi-feedback-delay = <0>;
-                        };
-
-                        partition@0 {
-                                label = "U-Boot";
-                                reg = <0x0 0x40000>;
-                                read-only;
-                        };
-
-                        partition@40000 {
-                                label = "Kernel";
-                                reg = <0x40000 0xc0000>;
-                        };
-                };
-        };
diff --git a/Documentation/devicetree/bindings/spi/spi-sc18is602.txt b/Documentation/devicetree/bindings/spi/spi-sc18is602.txt
deleted file mode 100644
index 02f9033270a..00000000000
--- a/Documentation/devicetree/bindings/spi/spi-sc18is602.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-NXP SC18IS602/SCIS603
-
-Required properties:
-        - compatible : Should be one of
-                "nxp,sc18is602"
-                "nxp,sc18is602b"
-                "nxp,sc18is603"
-        - reg: I2C bus address
-
-Optional properties:
-        - clock-frequency : external oscillator clock frequency. If not
-          specified, the SC18IS602 default frequency (7372000) will be used.
-
-The clock-frequency property is relevant and needed only if the chip has an
-external oscillator (SC18IS603).
-
-Example:
-
-        sc18is603@28 {
-                compatible = "nxp,sc18is603";
-                reg = <0x28>;
-                clock-frequency = <14744000>;
-        }
diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt b/Documentation/devicetree/bindings/spi/spi_atmel.txt
deleted file mode 100644
index 07e04cdc0c9..00000000000
--- a/Documentation/devicetree/bindings/spi/spi_atmel.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-Atmel SPI device
-
-Required properties:
-- compatible : should be "atmel,at91rm9200-spi".
-- reg: Address and length of the register set for the device
-- interrupts: Should contain spi interrupt
-- cs-gpios: chipselects
-
-Example:
-
-spi1: spi@fffcc000 {
-        compatible = "atmel,at91rm9200-spi";
-        reg = <0xfffcc000 0x4000>;
-        interrupts = <13 4 5>;
-        #address-cells = <1>;
-        #size-cells = <0>;
-        cs-gpios = <&pioB 3 0>;
-        status = "okay";
-
-        mmc-slot@0 {
-                compatible = "mmc-spi-slot";
-                reg = <0>;
-                gpios = <&pioC 4 0>;    /* CD */
-                spi-max-frequency = <25000000>;
-        };
-};
diff --git a/Documentation/devicetree/bindings/spi/spi_pl022.txt b/Documentation/devicetree/bindings/spi/spi_pl022.txt
deleted file mode 100644
index f158fd31cfd..00000000000
--- a/Documentation/devicetree/bindings/spi/spi_pl022.txt
+++ /dev/null
@@ -1,34 +0,0 @@
-ARM PL022 SPI controller
-
-Required properties:
-- compatible : "arm,pl022", "arm,primecell"
-- reg : Offset and length of the register set for the device
-- interrupts : Should contain SPI controller interrupt
-
-Optional properties:
-- num-cs : total number of chipselects
-- cs-gpios : should specify GPIOs used for chipselects.
-  The gpios will be referred to as reg = <index> in the SPI child nodes.
-  If unspecified, a single SPI device without a chip select can be used.
-- pl022,autosuspend-delay : delay in ms following transfer completion before
-                            the runtime power management system suspends the
-                            device. A setting of 0 indicates no delay and the
-                            device will be suspended immediately
-- pl022,rt : indicates the controller should run the message pump with realtime
-             priority to minimise the transfer latency on the bus (boolean)
-
-
-SPI slave nodes must be children of the SPI master node and can
-contain the following properties.
-
-- pl022,interface : interface type:
-        0: SPI
-        1: Texas Instruments Synchronous Serial Frame Format
-        2: Microwire (Half Duplex)
-- pl022,com-mode : polling, interrupt or dma
-- pl022,rx-level-trig : Rx FIFO watermark level
-- pl022,tx-level-trig : Tx FIFO watermark level
-- pl022,ctrl-len : Microwire interface: Control length
-- pl022,wait-state : Microwire interface: Wait state
-- pl022,duplex : Microwire interface: Full/Half duplex
-
diff --git a/Documentation/devicetree/bindings/staging/iio/adc/lpc32xx-adc.txt b/Documentation/devicetree/bindings/staging/iio/adc/lpc32xx-adc.txt
deleted file mode 100644
index b3629d3a9ad..00000000000
--- a/Documentation/devicetree/bindings/staging/iio/adc/lpc32xx-adc.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-* NXP LPC32xx SoC ADC controller
-
-Required properties:
-- compatible: must be "nxp,lpc3220-adc"
-- reg: physical base address of the controller and length of memory mapped
-  region.
-- interrupts: The ADC interrupt
-
-Example:
-
-        adc@40048000 {
-                compatible = "nxp,lpc3220-adc";
-                reg = <0x40048000 0x1000>;
-                interrupt-parent = <&mic>;
-                interrupts = <39 0>;
-        };
diff --git a/Documentation/devicetree/bindings/staging/iio/adc/mxs-lradc.txt b/Documentation/devicetree/bindings/staging/iio/adc/mxs-lradc.txt
deleted file mode 100644
index 801d58cb6d4..00000000000
--- a/Documentation/devicetree/bindings/staging/iio/adc/mxs-lradc.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-* Freescale i.MX28 LRADC device driver
-
-Required properties:
-- compatible: Should be "fsl,imx28-lradc"
-- reg: Address and length of the register set for the device
-- interrupts: Should contain the LRADC interrupts
-
-Examples:
-
-        lradc@80050000 {
-                compatible = "fsl,imx28-lradc";
-                reg = <0x80050000 0x2000>;
-                interrupts = <10 14 15 16 17 18 19
-                                20 21 22 23 24 25>;
-        };
diff --git a/Documentation/devicetree/bindings/staging/iio/adc/spear-adc.txt b/Documentation/devicetree/bindings/staging/iio/adc/spear-adc.txt
deleted file mode 100644
index 02ea23a63f2..00000000000
--- a/Documentation/devicetree/bindings/staging/iio/adc/spear-adc.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-* ST SPEAr ADC device driver
-
-Required properties:
-- compatible: Should be "st,spear600-adc"
-- reg: Address and length of the register set for the device
-- interrupt-parent: Should be the phandle for the interrupt controller
-  that services interrupts for this device
-- interrupts: Should contain the ADC interrupt
-- sampling-frequency: Default sampling frequency
-
-Optional properties:
-- vref-external: External voltage reference in milli-volts. If omitted
-  the internal voltage reference will be used.
-- average-samples: Number of samples to generate an average value. If
-  omitted, single data conversion will be used.
-
-Examples:
-
-        adc: adc@d8200000 {
-                compatible = "st,spear600-adc";
-                reg = <0xd8200000 0x1000>;
-                interrupt-parent = <&vic1>;
-                interrupts = <6>;
-                sampling-frequency = <5000000>;
-                vref-external = <2500>; /* 2.5V VRef */
-        };
diff --git a/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt b/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt
deleted file mode 100644
index 07654f0338b..00000000000
--- a/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-Freescale i.MX IPUv3
-====================
-
-Required properties:
-- compatible: Should be "fsl,<chip>-ipu"
-- reg: should be register base and length as documented in the
-  datasheet
-- interrupts: Should contain sync interrupt and error interrupt,
-  in this order.
-- #crtc-cells: 1, See below
-
-example:
-
-ipu: ipu@18000000 {
-        #crtc-cells = <1>;
-        compatible = "fsl,imx53-ipu";
-        reg = <0x18000000 0x080000000>;
-        interrupts = <11 10>;
-};
-
-Parallel display support
-========================
-
-Required properties:
-- compatible: Should be "fsl,imx-parallel-display"
-- crtc: the crtc this display is connected to, see below
-Optional properties:
-- interface_pix_fmt: How this display is connected to the
-  crtc. Currently supported types: "rgb24", "rgb565"
-- edid: verbatim EDID data block describing attached display.
-- ddc: phandle describing the i2c bus handling the display data
-  channel
-
-example:
-
-display@di0 {
-        compatible = "fsl,imx-parallel-display";
-        edid = [edid-data];
-        crtc = <&ipu 0>;
-        interface-pix-fmt = "rgb24";
-};
diff --git a/Documentation/devicetree/bindings/thermal/db8500-thermal.txt b/Documentation/devicetree/bindings/thermal/db8500-thermal.txt
deleted file mode 100644
index 2e1c06fad81..00000000000
--- a/Documentation/devicetree/bindings/thermal/db8500-thermal.txt
+++ /dev/null
@@ -1,44 +0,0 @@
-* ST-Ericsson DB8500 Thermal
-
-** Thermal node properties:
-
-- compatible : "stericsson,db8500-thermal";
-- reg : address range of the thermal sensor registers;
-- interrupts : interrupts generated from PRCMU;
-- interrupt-names : "IRQ_HOTMON_LOW" and "IRQ_HOTMON_HIGH";
-- num-trips : number of total trip points, this is required, set it 0 if none,
-  if greater than 0, the following properties must be defined;
-- tripN-temp : temperature of trip point N, should be in ascending order;
-- tripN-type : type of trip point N, should be one of "active" "passive" "hot"
-  "critical";
-- tripN-cdev-num : number of the cooling devices which can be bound to trip
-  point N, this is required if trip point N is defined, set it 0 if none,
-  otherwise the following cooling device names must be defined;
-- tripN-cdev-nameM : name of the No. M cooling device of trip point N;
-
-Usually the num-trips and tripN-*** are separated in board related dts files.
-
-Example:
-thermal@801573c0 {
-        compatible = "stericsson,db8500-thermal";
-        reg = <0x801573c0 0x40>;
-        interrupts = <21 0x4>, <22 0x4>;
-        interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
-
-        num-trips = <3>;
-
-        trip0-temp = <75000>;
-        trip0-type = "active";
-        trip0-cdev-num = <1>;
-        trip0-cdev-name0 = "thermal-cpufreq-0";
-
-        trip1-temp = <80000>;
-        trip1-type = "active";
-        trip1-cdev-num = <2>;
-        trip1-cdev-name0 = "thermal-cpufreq-0";
-        trip1-cdev-name1 = "thermal-fan";
-
-        trip2-temp = <85000>;
-        trip2-type = "critical";
-        trip2-cdev-num = <0>;
-}
diff --git a/Documentation/devicetree/bindings/thermal/spear-thermal.txt b/Documentation/devicetree/bindings/thermal/spear-thermal.txt
deleted file mode 100644
index 93e3b67c102..00000000000
--- a/Documentation/devicetree/bindings/thermal/spear-thermal.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-* SPEAr Thermal
-
-Required properties:
-- compatible : "st,thermal-spear1340"
-- reg : Address range of the thermal registers
-- st,thermal-flags: flags used to enable thermal sensor
-
-Example:
-
-        thermal@fc000000 {
-                compatible = "st,thermal-spear1340";
-                reg = <0xfc000000 0x1000>;
-                st,thermal-flags = <0x7000>;
-        };
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt b/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt
deleted file mode 100644
index 0c7b64e95a6..00000000000
--- a/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-Allwinner A1X SoCs Timer Controller
-
-Required properties:
-
-- compatible : should be "allwinner,sunxi-timer"
-- reg : Specifies base physical address and size of the registers.
-- interrupts : The interrupt of the first timer
-- clocks: phandle to the source clock (usually a 24 MHz fixed clock)
-
-Example:
-
-timer {
-        compatible = "allwinner,sunxi-timer";
-        reg = <0x01c20c00 0x400>;
-        interrupts = <22>;
-        clocks = <&osc>;
-};
diff --git a/Documentation/devicetree/bindings/timer/brcm,bcm2835-system-timer.txt b/Documentation/devicetree/bindings/timer/brcm,bcm2835-system-timer.txt
deleted file mode 100644
index 844bd5fbd04..00000000000
--- a/Documentation/devicetree/bindings/timer/brcm,bcm2835-system-timer.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-BCM2835 System Timer
-
-The System Timer peripheral provides four 32-bit timer channels and a
-single 64-bit free running counter. Each channel has an output compare
-register, which is compared against the 32 least significant bits of the
-free running counter values, and generates an interrupt.
-
-Required properties:
-
-- compatible : should be "brcm,bcm2835-system-timer"
-- reg : Specifies base physical address and size of the registers.
-- interrupts : A list of 4 interrupt sinks; one per timer channel.
-- clock-frequency : The frequency of the clock that drives the counter, in Hz.
-
-Example:
-
-timer {
-        compatible = "brcm,bcm2835-system-timer";
-        reg = <0x7e003000 0x1000>;
-        interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
-        clock-frequency = <1000000>;
-};
diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
deleted file mode 100644
index e019fdc3877..00000000000
--- a/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-NVIDIA Tegra20 timer
-
-The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free
-running counter. The first two channels may also trigger a watchdog reset.
-
-Required properties:
-
-- compatible : should be "nvidia,tegra20-timer".
-- reg : Specifies base physical address and size of the registers.
-- interrupts : A list of 4 interrupts; one per timer channel.
-
-Example:
-
-timer {
-        compatible = "nvidia,tegra20-timer";
-        reg = <0x60005000 0x60>;
-        interrupts = <0 0 0x04
-                        0 1 0x04
-                        0 41 0x04
-                        0 42 0x04>;
-};
diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
deleted file mode 100644
index 906109d4c59..00000000000
--- a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-NVIDIA Tegra30 timer
-
-The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free
-running counter, and 5 watchdog modules. The first two channels may also
-trigger a legacy watchdog reset.
-
-Required properties:
-
-- compatible : should be "nvidia,tegra30-timer", "nvidia,tegra20-timer".
-- reg : Specifies base physical address and size of the registers.
-- interrupts : A list of 6 interrupts; one per each of timer channels 1
-    through 5, and one for the shared interrupt for the remaining channels.
-
-timer {
-        compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
-        reg = <0x60005000 0x400>;
-        interrupts = <0 0 0x04
-                      0 1 0x04
-                      0 41 0x04
-                      0 42 0x04
-                      0 121 0x04
-                      0 122 0x04>;
-};
diff --git a/Documentation/devicetree/bindings/tty/serial/atmel-usart.txt b/Documentation/devicetree/bindings/tty/serial/atmel-usart.txt
deleted file mode 100644
index a49d9a1d4cc..00000000000
--- a/Documentation/devicetree/bindings/tty/serial/atmel-usart.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-* Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART)
-
-Required properties:
-- compatible: Should be "atmel,<chip>-usart"
-  The compatible <chip> indicated will be the first SoC to support an
-  additional mode or an USART new feature.
-- reg: Should contain registers location and length
-- interrupts: Should contain interrupt
-
-Optional properties:
-- atmel,use-dma-rx: use of PDC or DMA for receiving data
-- atmel,use-dma-tx: use of PDC or DMA for transmitting data
-
-<chip> compatible description:
-- at91rm9200:  legacy USART support
-- at91sam9260: generic USART implementation for SAM9 SoCs
-
-Example:
-
-        usart0: serial@fff8c000 {
-                compatible = "atmel,at91sam9260-usart";
-                reg = <0xfff8c000 0x4000>;
-                interrupts = <7>;
-                atmel,use-dma-rx;
-                atmel,use-dma-tx;
-        };
-
diff --git a/Documentation/devicetree/bindings/tty/serial/efm32-uart.txt b/Documentation/devicetree/bindings/tty/serial/efm32-uart.txt
deleted file mode 100644
index 6588b6950a7..00000000000
--- a/Documentation/devicetree/bindings/tty/serial/efm32-uart.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-* Energymicro efm32 UART
-
-Required properties:
-- compatible : Should be "efm32,uart"
-- reg : Address and length of the register set
-- interrupts : Should contain uart interrupt
-
-Example:
-
-uart@0x4000c400 {
-        compatible = "efm32,uart";
-        reg = <0x4000c400 0x400>;
-        interrupts = <15>;
-};
diff --git a/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt b/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt
index b462d0c5482..a9c0406280e 100644
--- a/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt
+++ b/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt
@@ -11,7 +11,7 @@ Optional properties:
 
 Example:
 
-serial@73fbc000 {
+uart@73fbc000 {
         compatible = "fsl,imx51-uart", "fsl,imx21-uart";
         reg = <0x73fbc000 0x4000>;
         interrupts = <31>;
diff --git a/Documentation/devicetree/bindings/tty/serial/fsl-mxs-auart.txt b/Documentation/devicetree/bindings/tty/serial/fsl-mxs-auart.txt
deleted file mode 100644
index 273a8d5b330..00000000000
--- a/Documentation/devicetree/bindings/tty/serial/fsl-mxs-auart.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-* Freescale MXS Application UART (AUART)
-
-Required properties:
-- compatible : Should be "fsl,<soc>-auart". The supported SoCs include
-  imx23 and imx28.
-- reg : Address and length of the register set for the device
-- interrupts : Should contain the auart interrupt numbers
-
-Optional properties:
-- fsl,auart-dma-channel : The DMA channels, the first is for RX, the other
-                is for TX. If you add this property, it also means that you
-                will enable the DMA support for the auart.
-                Note: due to the hardware bug in imx23(see errata : 2836),
-                only the imx28 can enable the DMA support for the auart.
-
-Example:
-auart0: serial@8006a000 {
-        compatible = "fsl,imx28-auart", "fsl,imx23-auart";
-        reg = <0x8006a000 0x2000>;
-        interrupts = <112 70 71>;
-        fsl,auart-dma-channel = <8 9>;
-};
-
-Note: Each auart port should have an alias correctly numbered in "aliases"
-node.
-
-Example:
-
-aliases {
-        serial0 = &auart0;
-        serial1 = &auart1;
-        serial2 = &auart2;
-        serial3 = &auart3;
-        serial4 = &auart4;
-};
diff --git a/Documentation/devicetree/bindings/tty/serial/msm_serial.txt b/Documentation/devicetree/bindings/tty/serial/msm_serial.txt
deleted file mode 100644
index aef383eb887..00000000000
--- a/Documentation/devicetree/bindings/tty/serial/msm_serial.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-* Qualcomm MSM UART
-
-Required properties:
-- compatible :
-        - "qcom,msm-uart", and one of "qcom,msm-hsuart" or
-          "qcom,msm-lsuart".
-- reg : offset and length of the register set for the device
-        for the hsuart operating in compatible mode, there should be a
-        second pair describing the gsbi registers.
-- interrupts : should contain the uart interrupt.
-
-There are two different UART blocks used in MSM devices,
-"qcom,msm-hsuart" and "qcom,msm-lsuart".  The msm-serial driver is
-able to handle both of these, and matches against the "qcom,msm-uart"
-as the compatibility.
-
-The registers for the "qcom,msm-hsuart" device need to specify both
-register blocks, even for the common driver.
-
-Example:
-
-        uart@19c400000 {
-                compatible = "qcom,msm-hsuart", "qcom,msm-uart";
-                reg = <0x19c40000 0x1000>,
-                      <0x19c00000 0x1000>;
-                interrupts = <195>;
-        };
diff --git a/Documentation/devicetree/bindings/tty/serial/nxp-lpc32xx-hsuart.txt b/Documentation/devicetree/bindings/tty/serial/nxp-lpc32xx-hsuart.txt
deleted file mode 100644
index 0d439dfc1aa..00000000000
--- a/Documentation/devicetree/bindings/tty/serial/nxp-lpc32xx-hsuart.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-* NXP LPC32xx SoC High Speed UART
-
-Required properties:
-- compatible: Should be "nxp,lpc3220-hsuart"
-- reg: Should contain registers location and length
-- interrupts: Should contain interrupt
-
-Example:
-
-        uart1: serial@40014000 {
-                compatible = "nxp,lpc3220-hsuart";
-                reg = <0x40014000 0x1000>;
-                interrupts = <26 0>;
-        };
diff --git a/Documentation/devicetree/bindings/tty/serial/of-serial.txt b/Documentation/devicetree/bindings/tty/serial/of-serial.txt
index 1e1145ca4f3..b8b27b0aca1 100644
--- a/Documentation/devicetree/bindings/tty/serial/of-serial.txt
+++ b/Documentation/devicetree/bindings/tty/serial/of-serial.txt
@@ -9,15 +9,11 @@ Required properties:
         - "ns16750"
         - "ns16850"
         - "nvidia,tegra20-uart"
-        - "nxp,lpc3220-uart"
         - "ibm,qpace-nwp-serial"
         - "serial" if the port type is unknown.
 - reg : offset and length of the register set for the device.
 - interrupts : should contain uart interrupt.
-- clock-frequency : the input clock frequency for the UART
-         or
-  clocks phandle to refer to the clk used as per Documentation/devicetree
-  /bindings/clock/clock-bindings.txt
+- clock-frequency : the input clock frequency for the UART.
 
 Optional properties:
 - current-speed : the current active speed of the UART.
@@ -28,8 +24,6 @@ Optional properties:
   accesses to the UART (e.g. TI davinci).
 - used-by-rtas : set to indicate that the port is in use by the OpenFirmware
   RTAS and should not be registered.
-- no-loopback-test: set to indicate that the port does not implements loopback
-  test mode
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/tty/serial/snps-dw-apb-uart.txt b/Documentation/devicetree/bindings/tty/serial/snps-dw-apb-uart.txt
deleted file mode 100644
index f13f1c5be91..00000000000
--- a/Documentation/devicetree/bindings/tty/serial/snps-dw-apb-uart.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-* Synopsys DesignWare ABP UART
-
-Required properties:
-- compatible : "snps,dw-apb-uart"
-- reg : offset and length of the register set for the device.
-- interrupts : should contain uart interrupt.
-- clock-frequency : the input clock frequency for the UART.
-
-Optional properties:
-- reg-shift : quantity to shift the register offsets by.  If this property is
-  not present then the register offsets are not shifted.
-- reg-io-width : the size (in bytes) of the IO accesses that should be
-  performed on the device.  If this property is not present then single byte
-  accesses are used.
-
-Example:
-
-        uart@80230000 {
-                compatible = "snps,dw-apb-uart";
-                reg = <0x80230000 0x100>;
-                clock-frequency = <3686400>;
-                interrupts = <10>;
-                reg-shift = <2>;
-                reg-io-width = <4>;
-        };
diff --git a/Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt b/Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt
deleted file mode 100644
index 5feef1ef167..00000000000
--- a/Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-VIA/Wondermedia VT8500 UART Controller
------------------------------------------------------
-
-Required properties:
-- compatible : "via,vt8500-uart"
-- reg : Should contain 1 register ranges(address and length)
-- interrupts : UART interrupt
-- clocks : phandle to the uart source clock (usually a 24Mhz fixed clock)
-
-Example:
-
-        uart@d8210000 {
-                compatible = "via,vt8500-uart";
-                reg = <0xd8210000 0x1040>;
-                interrupts = <47>;
-                clocks = <&ref24>;
-        };
diff --git a/Documentation/devicetree/bindings/usb/am33xx-usb.txt b/Documentation/devicetree/bindings/usb/am33xx-usb.txt
deleted file mode 100644
index ea840f7f925..00000000000
--- a/Documentation/devicetree/bindings/usb/am33xx-usb.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-AM33XX MUSB GLUE
- - compatible : Should be "ti,musb-am33xx"
- - reg : offset and length of register sets, first usbss, then for musb instances
- - interrupts : usbss, musb instance interrupts in order
- - ti,hwmods : must be "usb_otg_hs"
- - multipoint : Should be "1" indicating the musb controller supports
-   multipoint. This is a MUSB configuration-specific setting.
- - num-eps : Specifies the number of endpoints. This is also a
-   MUSB configuration-specific setting. Should be set to "16"
- - ram-bits : Specifies the ram address size. Should be set to "12"
- - port0-mode : Should be "3" to represent OTG. "1" signifies HOST and "2"
-   represents PERIPHERAL.
- - port1-mode : Should be "1" to represent HOST. "3" signifies OTG and "2"
-   represents PERIPHERAL.
- - power : Should be "250". This signifies the controller can supply upto
-   500mA when operating in host mode.
-
-Example:
-
-usb@47400000  {
-        compatible = "ti,musb-am33xx";
-        reg = <0x47400000 0x1000        /* usbss */
-               0x47401000 0x800         /* musb instance 0 */
-               0x47401800 0x800>;       /* musb instance 1 */
-        interrupts = <17                /* usbss */
-                      18                /* musb instance 0 */
-                      19>;              /* musb instance 1 */
-        multipoint = <1>;
-        num-eps = <16>;
-        ram-bits = <12>;
-        port0-mode = <3>;
-        port1-mode = <3>;
-        power = <250>;
-        ti,hwmods = "usb_otg_hs";
-};
diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt
deleted file mode 100644
index 60bd2150a3e..00000000000
--- a/Documentation/devicetree/bindings/usb/atmel-usb.txt
+++ /dev/null
@@ -1,49 +0,0 @@
-Atmel SOC USB controllers
-
-OHCI
-
-Required properties:
- - compatible: Should be "atmel,at91rm9200-ohci" for USB controllers
-   used in host mode.
- - num-ports: Number of ports.
- - atmel,vbus-gpio: If present, specifies a gpio that needs to be
-   activated for the bus to be powered.
- - atmel,oc-gpio: If present, specifies a gpio that needs to be
-   activated for the overcurrent detection.
-
-usb0: ohci@00500000 {
-        compatible = "atmel,at91rm9200-ohci", "usb-ohci";
-        reg = <0x00500000 0x100000>;
-        interrupts = <20 4>;
-        num-ports = <2>;
-};
-
-EHCI
-
-Required properties:
- - compatible: Should be "atmel,at91sam9g45-ehci" for USB controllers
-   used in host mode.
-
-usb1: ehci@00800000 {
-        compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
-        reg = <0x00800000 0x100000>;
-        interrupts = <22 4>;
-};
-
-AT91 USB device controller
-
-Required properties:
- - compatible: Should be "atmel,at91rm9200-udc"
- - reg: Address and length of the register set for the device
- - interrupts: Should contain macb interrupt
-
-Optional properties:
- - atmel,vbus-gpio: If present, specifies a gpio that needs to be
-   activated for the bus to be powered.
-
-usb1: gadget@fffa4000 {
-        compatible = "atmel,at91rm9200-udc";
-        reg = <0xfffa4000 0x4000>;
-        interrupts = <10 4>;
-        atmel,vbus-gpio = <&pioC 5 0>;
-};
diff --git a/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt b/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
deleted file mode 100644
index 5778b9c83bd..00000000000
--- a/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-* Freescale i.MX ci13xxx usb controllers
-
-Required properties:
-- compatible: Should be "fsl,imx27-usb"
-- reg: Should contain registers location and length
-- interrupts: Should contain controller interrupt
-
-Optional properties:
-- fsl,usbphy: phandler of usb phy that connects to the only one port
-- fsl,usbmisc: phandler of non-core register device, with one argument
-  that indicate usb controller index
-- vbus-supply: regulator for vbus
-- disable-over-current: disable over current detect
-
-Examples:
-usb@02184000 { /* USB OTG */
-        compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
-        reg = <0x02184000 0x200>;
-        interrupts = <0 43 0x04>;
-        fsl,usbphy = <&usbphy1>;
-        fsl,usbmisc = <&usbmisc 0>;
-        disable-over-current;
-};
diff --git a/Documentation/devicetree/bindings/usb/ehci-orion.txt b/Documentation/devicetree/bindings/usb/ehci-orion.txt
deleted file mode 100644
index 6bc09ec14c4..00000000000
--- a/Documentation/devicetree/bindings/usb/ehci-orion.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-* EHCI controller, Orion Marvell variants
-
-Required properties:
-- compatible: must be "marvell,orion-ehci"
-- reg: physical base address of the controller and length of memory mapped
-  region.
-- interrupts: The EHCI interrupt
-
-Example:
-
-        ehci@50000 {
-                compatible = "marvell,orion-ehci";
-                reg = <0x50000 0x1000>;
-                interrupts = <19>;
-        };
diff --git a/Documentation/devicetree/bindings/usb/isp1301.txt b/Documentation/devicetree/bindings/usb/isp1301.txt
deleted file mode 100644
index 5405d99d9aa..00000000000
--- a/Documentation/devicetree/bindings/usb/isp1301.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-* NXP ISP1301 USB transceiver
-
-Required properties:
-- compatible: must be "nxp,isp1301"
-- reg: I2C address of the ISP1301 device
-
-Optional properties of devices using ISP1301:
-- transceiver: phandle of isp1301 - this helps the ISP1301 driver to find the
-               ISP1301 instance associated with the respective USB driver
-
-Example:
-
-        isp1301: usb-transceiver@2c {
-                compatible = "nxp,isp1301";
-                reg = <0x2c>;
-        };
-
-        usbd@31020000 {
-                compatible = "nxp,lpc3220-udc";
-                reg = <0x31020000 0x300>;
-                interrupt-parent = <&mic>;
-                interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
-                transceiver = <&isp1301>;
-                status = "okay";
-        };
diff --git a/Documentation/devicetree/bindings/usb/lpc32xx-udc.txt b/Documentation/devicetree/bindings/usb/lpc32xx-udc.txt
deleted file mode 100644
index 29f12a533f6..00000000000
--- a/Documentation/devicetree/bindings/usb/lpc32xx-udc.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-* NXP LPC32xx SoC USB Device Controller (UDC)
-
-Required properties:
-- compatible: Must be "nxp,lpc3220-udc"
-- reg: Physical base address of the controller and length of memory mapped
-  region.
-- interrupts: The USB interrupts:
-              * USB Device Low Priority Interrupt
-              * USB Device High Priority Interrupt
-              * USB Device DMA Interrupt
-              * External USB Transceiver Interrupt (OTG ATX)
-- transceiver: phandle of the associated ISP1301 device - this is necessary for
-               the UDC controller for connecting to the USB physical layer
-
-Example:
-
-        isp1301: usb-transceiver@2c {
-                compatible = "nxp,isp1301";
-                reg = <0x2c>;
-        };
-
-        usbd@31020000 {
-                compatible = "nxp,lpc3220-udc";
-                reg = <0x31020000 0x300>;
-                interrupt-parent = <&mic>;
-                interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
-                transceiver = <&isp1301>;
-        };
diff --git a/Documentation/devicetree/bindings/usb/mxs-phy.txt b/Documentation/devicetree/bindings/usb/mxs-phy.txt
deleted file mode 100644
index 5835b27146e..00000000000
--- a/Documentation/devicetree/bindings/usb/mxs-phy.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-* Freescale MXS USB Phy Device
-
-Required properties:
-- compatible: Should be "fsl,imx23-usbphy"
-- reg: Should contain registers location and length
-- interrupts: Should contain phy interrupt
-
-Example:
-usbphy1: usbphy@020c9000 {
-        compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
-        reg = <0x020c9000 0x1000>;
-        interrupts = <0 44 0x04>;
-};
diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
deleted file mode 100644
index e9b005dc762..00000000000
--- a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-Tegra SOC USB controllers
-
-The device node for a USB controller that is part of a Tegra
-SOC is as described in the document "Open Firmware Recommended
-Practice : Universal Serial Bus" with the following modifications
-and additions :
-
-Required properties :
- - compatible : Should be "nvidia,tegra20-ehci" for USB controllers
-   used in host mode.
- - phy_type : Should be one of "ulpi" or "utmi".
- - nvidia,vbus-gpio : If present, specifies a gpio that needs to be
-   activated for the bus to be powered.
-
-Required properties for phy_type == ulpi:
-  - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
-
-Optional properties:
-  - dr_mode : dual role mode. Indicates the working mode for
-   nvidia,tegra20-ehci compatible controllers.  Can be "host", "peripheral",
-   or "otg".  Default to "host" if not defined for backward compatibility.
-      host means this is a host controller
-      peripheral means it is device controller
-      otg means it can operate as either ("on the go")
-  - nvidia,has-legacy-mode : boolean indicates whether this controller can
-    operate in legacy mode (as APX 2500 / 2600). In legacy mode some
-    registers are accessed through the APB_MISC base address instead of
-    the USB controller. Since this is a legacy issue it probably does not
-    warrant a compatible string of its own.
diff --git a/Documentation/devicetree/bindings/usb/ohci-nxp.txt b/Documentation/devicetree/bindings/usb/ohci-nxp.txt
deleted file mode 100644
index 71e28c1017e..00000000000
--- a/Documentation/devicetree/bindings/usb/ohci-nxp.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-* OHCI controller, NXP ohci-nxp variant
-
-Required properties:
-- compatible: must be "nxp,ohci-nxp"
-- reg: physical base address of the controller and length of memory mapped
-  region.
-- interrupts: The OHCI interrupt
-- transceiver: phandle of the associated ISP1301 device - this is necessary for
-               the UDC controller for connecting to the USB physical layer
-
-Example (LPC32xx):
-
-        isp1301: usb-transceiver@2c {
-                compatible = "nxp,isp1301";
-                reg = <0x2c>;
-        };
-
-        ohci@31020000 {
-                compatible = "nxp,ohci-nxp";
-                reg = <0x31020000 0x300>;
-                interrupt-parent = <&mic>;
-                interrupts = <0x3b 0>;
-                transceiver = <&isp1301>;
-        };
diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt b/Documentation/devicetree/bindings/usb/omap-usb.txt
deleted file mode 100644
index 29a043ecda5..00000000000
--- a/Documentation/devicetree/bindings/usb/omap-usb.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-OMAP GLUE
-
-OMAP MUSB GLUE
- - compatible : Should be "ti,omap4-musb" or "ti,omap3-musb"
- - ti,hwmods : must be "usb_otg_hs"
- - multipoint : Should be "1" indicating the musb controller supports
-   multipoint. This is a MUSB configuration-specific setting.
- - num_eps : Specifies the number of endpoints. This is also a
-   MUSB configuration-specific setting. Should be set to "16"
- - ram_bits : Specifies the ram address size. Should be set to "12"
- - interface_type : This is a board specific setting to describe the type of
-   interface between the controller and the phy. It should be "0" or "1"
-   specifying ULPI and UTMI respectively.
- - mode : Should be "3" to represent OTG. "1" signifies HOST and "2"
-   represents PERIPHERAL.
- - power : Should be "50". This signifies the controller can supply upto
-   100mA when operating in host mode.
-
-SOC specific device node entry
-usb_otg_hs: usb_otg_hs@4a0ab000 {
-        compatible = "ti,omap4-musb";
-        ti,hwmods = "usb_otg_hs";
-        multipoint = <1>;
-        num_eps = <16>;
-        ram_bits = <12>;
-};
-
-Board specific device node entry
-&usb_otg_hs {
-        interface_type = <1>;
-        mode = <3>;
-        power = <50>;
-};
diff --git a/Documentation/devicetree/bindings/usb/platform-uhci.txt b/Documentation/devicetree/bindings/usb/platform-uhci.txt
deleted file mode 100644
index a4fb0719d15..00000000000
--- a/Documentation/devicetree/bindings/usb/platform-uhci.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-Generic Platform UHCI Controller
------------------------------------------------------
-
-Required properties:
-- compatible : "platform-uhci"
-- reg : Should contain 1 register ranges(address and length)
-- interrupts : UHCI controller interrupt
-
-Example:
-
-        uhci@d8007b00 {
-                compatible = "platform-uhci";
-                reg = <0xd8007b00 0x200>;
-                interrupts = <43>;
-        };
diff --git a/Documentation/devicetree/bindings/usb/pxa-usb.txt b/Documentation/devicetree/bindings/usb/pxa-usb.txt
deleted file mode 100644
index 79729a948d5..00000000000
--- a/Documentation/devicetree/bindings/usb/pxa-usb.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-PXA USB controllers
-
-OHCI
-
-Required properties:
- - compatible: Should be "marvell,pxa-ohci" for USB controllers
-   used in host mode.
-
-Optional properties:
- - "marvell,enable-port1", "marvell,enable-port2", "marvell,enable-port3"
-   If present, enables the appropriate USB port of the controller.
- - "marvell,port-mode" selects the mode of the ports:
-        1 = PMM_NPS_MODE
-        2 = PMM_GLOBAL_MODE
-        3 = PMM_PERPORT_MODE
- - "marvell,power-sense-low" - power sense pin is low-active.
- - "marvell,power-control-low" - power control pin is low-active.
- - "marvell,no-oc-protection" - disable over-current protection.
- - "marvell,oc-mode-perport" - enable per-port over-current protection.
- - "marvell,power_on_delay" Power On to Power Good time - in ms.
-
-Example:
-
-        usb0: ohci@4c000000 {
-                compatible = "marvell,pxa-ohci", "usb-ohci";
-                reg = <0x4c000000 0x100000>;
-                interrupts = <18>;
-                marvell,enable-port1;
-                marvell,port-mode = <2>; /* PMM_GLOBAL_MODE */
-        };
-
diff --git a/Documentation/devicetree/bindings/usb/spear-usb.txt b/Documentation/devicetree/bindings/usb/spear-usb.txt
deleted file mode 100644
index f8a464a2565..00000000000
--- a/Documentation/devicetree/bindings/usb/spear-usb.txt
+++ /dev/null
@@ -1,39 +0,0 @@
-ST SPEAr SoC USB controllers:
------------------------------
-
-EHCI:
------
-
-Required properties:
-- compatible: "st,spear600-ehci"
-- interrupt-parent: Should be the phandle for the interrupt controller
-  that services interrupts for this device
-- interrupts: Should contain the EHCI interrupt
-
-Example:
-
-        ehci@e1800000 {
-                compatible = "st,spear600-ehci", "usb-ehci";
-                reg = <0xe1800000 0x1000>;
-                interrupt-parent = <&vic1>;
-                interrupts = <27>;
-        };
-
-
-OHCI:
------
-
-Required properties:
-- compatible: "st,spear600-ohci"
-- interrupt-parent: Should be the phandle for the interrupt controller
-  that services interrupts for this device
-- interrupts: Should contain the OHCI interrupt
-
-Example:
-
-        ohci@e1900000 {
-                compatible = "st,spear600-ohci", "usb-ohci";
-                reg = <0xe1800000 0x1000>;
-                interrupt-parent = <&vic1>;
-                interrupts = <26>;
-        };
diff --git a/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt b/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt
deleted file mode 100644
index 36b9aede3f4..00000000000
--- a/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt
+++ /dev/null
@@ -1,40 +0,0 @@
-USB COMPARATOR OF TWL CHIPS
-
-TWL6030 USB COMPARATOR
- - compatible : Should be "ti,twl6030-usb"
- - interrupts : Two interrupt numbers to the cpu should be specified. First
-   interrupt number is the otg interrupt number that raises ID interrupts when
-   the controller has to act as host and the second interrupt number is the
-   usb interrupt number that raises VBUS interrupts when the controller has to
-   act as device
- - usb-supply : phandle to the regulator device tree node. It should be vusb
-   if it is twl6030 or ldousb if it is twl6025 subclass.
-
-twl6030-usb {
-        compatible = "ti,twl6030-usb";
-        interrupts = < 4 10 >;
-};
-
-Board specific device node entry
-&twl6030-usb {
-        usb-supply = <&vusb>;
-};
-
-TWL4030 USB PHY AND COMPARATOR
- - compatible : Should be "ti,twl4030-usb"
- - interrupts : The interrupt numbers to the cpu should be specified. First
-   interrupt number is the otg interrupt number that raises ID interrupts
-   and VBUS interrupts. The second interrupt number is optional.
- - <supply-name>-supply : phandle to the regulator device tree node.
-   <supply-name> should be vusb1v5, vusb1v8 and vusb3v1
- - usb_mode : The mode used by the phy to connect to the controller. "1"
-   specifies "ULPI" mode and "2" specifies "CEA2011_3PIN" mode.
-
-twl4030-usb {
-        compatible = "ti,twl4030-usb";
-        interrupts = < 10 4 >;
-        usb1v5-supply = <&vusb1v5>;
-        usb1v8-supply = <&vusb1v8>;
-        usb3v1-supply = <&vusb3v1>;
-        usb_mode = <1>;
-};
diff --git a/Documentation/devicetree/bindings/usb/usb-phy.txt b/Documentation/devicetree/bindings/usb/usb-phy.txt
deleted file mode 100644
index 80d4148cb66..00000000000
--- a/Documentation/devicetree/bindings/usb/usb-phy.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-USB PHY
-
-OMAP USB2 PHY
-
-Required properties:
- - compatible: Should be "ti,omap-usb2"
- - reg : Address and length of the register set for the device. Also
-add the address of control module dev conf register until a driver for
-control module is added
-
-This is usually a subnode of ocp2scp to which it is connected.
-
-usb2phy@4a0ad080 {
-        compatible = "ti,omap-usb2";
-        reg = <0x4a0ad080 0x58>,
-              <0x4a002300 0x4>;
-};
diff --git a/Documentation/devicetree/bindings/usb/usbmisc-imx.txt b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt
deleted file mode 100644
index 97ce94e1a6c..00000000000
--- a/Documentation/devicetree/bindings/usb/usbmisc-imx.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-* Freescale i.MX non-core registers
-
-Required properties:
-- #index-cells: Cells used to descibe usb controller index. Should be <1>
-- compatible: Should be one of below:
-        "fsl,imx6q-usbmisc" for imx6q
-- reg: Should contain registers location and length
-
-Examples:
-usbmisc@02184800 {
-        #index-cells = <1>;
-        compatible = "fsl,imx6q-usbmisc";
-        reg = <0x02184800 0x200>;
-};
diff --git a/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt b/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
deleted file mode 100644
index 17b3ad1d97e..00000000000
--- a/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-VIA/Wondermedia VT8500 EHCI Controller
------------------------------------------------------
-
-Required properties:
-- compatible : "via,vt8500-ehci"
-- reg : Should contain 1 register ranges(address and length)
-- interrupts : ehci controller interrupt
-
-Example:
-
-        ehci@d8007900 {
-                compatible = "via,vt8500-ehci";
-                reg = <0xd8007900 0x200>;
-                interrupts = <43>;
-        };
diff --git a/Documentation/devicetree/bindings/usb/vt8500-ehci.txt b/Documentation/devicetree/bindings/usb/vt8500-ehci.txt
deleted file mode 100644
index 5fb8fd6e250..00000000000
--- a/Documentation/devicetree/bindings/usb/vt8500-ehci.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-VIA VT8500 and Wondermedia WM8xxx SoC USB controllers.
-
-Required properties:
- - compatible: Should be "via,vt8500-ehci" or "wm,prizm-ehci".
- - reg: Address range of the ehci registers. size should be 0x200
- - interrupts: Should contain the ehci interrupt.
-
-usb: ehci@D8007100 {
-        compatible = "wm,prizm-ehci", "usb-ehci";
-        reg = <0xD8007100 0x200>;
-        interrupts = <1>;
-};
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
deleted file mode 100644
index 902b1b1f568..00000000000
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ /dev/null
@@ -1,59 +0,0 @@
-Device tree binding vendor prefix registry.  Keep list in alphabetical order.
-
-This isn't an exhaustive list, but you should add new prefixes to it before
-using them to avoid name-space collisions.
-
-ad      Avionic Design GmbH
-adi     Analog Devices, Inc.
-ak      Asahi Kasei Corp.
-amcc    Applied Micro Circuits Corporation (APM, formally AMCC)
-apm     Applied Micro Circuits Corporation (APM)
-arm     ARM Ltd.
-atmel   Atmel Corporation
-bosch   Bosch Sensortec GmbH
-brcm    Broadcom Corporation
-cavium  Cavium, Inc.
-chrp    Common Hardware Reference Platform
-cortina Cortina Systems, Inc.
-dallas  Maxim Integrated Products (formerly Dallas Semiconductor)
-denx    Denx Software Engineering
-emmicro EM Microelectronic
-epson   Seiko Epson Corp.
-est     ESTeem Wireless Modems
-fsl     Freescale Semiconductor
-GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc.
-gef     GE Fanuc Intelligent Platforms Embedded Systems, Inc.
-hp      Hewlett Packard
-ibm     International Business Machines (IBM)
-idt     Integrated Device Technologies, Inc.
-img     Imagination Technologies Ltd.
-intercontrol    Inter Control Group
-linux   Linux-specific binding
-marvell Marvell Technology Group Ltd.
-maxim   Maxim Integrated Products
-mosaixtech      Mosaix Technologies, Inc.
-national        National Semiconductor
-nintendo        Nintendo
-nvidia  NVIDIA
-nxp     NXP Semiconductors
-onnn    ON Semiconductor Corp.
-picochip        Picochip Ltd
-powervr PowerVR (deprecated, use img)
-qcom    Qualcomm, Inc.
-ramtron Ramtron International
-realtek Realtek Semiconductor Corp.
-samsung Samsung Semiconductor
-sbs     Smart Battery System
-schindler       Schindler
-sil     Silicon Image
-simtek
-sirf    SiRF Technology, Inc.
-snps    Synopsys, Inc.
-st      STMicroelectronics
-stericsson      ST-Ericsson
-ti      Texas Instruments
-via     VIA Technologies, Inc.
-wlf     Wolfson Microelectronics
-wm      Wondermedia Technologies, Inc.
-winbond Winbond Electronics corp.
-xlnx    Xilinx
diff --git a/Documentation/devicetree/bindings/video/backlight/88pm860x.txt b/Documentation/devicetree/bindings/video/backlight/88pm860x.txt
deleted file mode 100644
index 261df279931..00000000000
--- a/Documentation/devicetree/bindings/video/backlight/88pm860x.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-88pm860x-backlight bindings
-
-Optional properties:
-  - marvell,88pm860x-iset: Current supplies on backlight device.
-  - marvell,88pm860x-pwm: PWM frequency on backlight device.
-
-Example:
-
-        backlights {
-                backlight-0 {
-                        marvell,88pm860x-iset = <4>;
-                        marvell,88pm860x-pwm = <3>;
-                };
-                backlight-2 {
-                };
diff --git a/Documentation/devicetree/bindings/video/backlight/pwm-backlight.txt b/Documentation/devicetree/bindings/video/backlight/pwm-backlight.txt
deleted file mode 100644
index 1e4fc727f3b..00000000000
--- a/Documentation/devicetree/bindings/video/backlight/pwm-backlight.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-pwm-backlight bindings
-
-Required properties:
-  - compatible: "pwm-backlight"
-  - pwms: OF device-tree PWM specification (see PWM binding[0])
-  - brightness-levels: Array of distinct brightness levels. Typically these
-      are in the range from 0 to 255, but any range starting at 0 will do.
-      The actual brightness level (PWM duty cycle) will be interpolated
-      from these values. 0 means a 0% duty cycle (darkest/off), while the
-      last value in the array represents a 100% duty cycle (brightest).
-  - default-brightness-level: the default brightness level (index into the
-      array defined by the "brightness-levels" property)
-
-Optional properties:
-  - pwm-names: a list of names for the PWM devices specified in the
-               "pwms" property (see PWM binding[0])
-
-[0]: Documentation/devicetree/bindings/pwm/pwm.txt
-
-Example:
-
-        backlight {
-                compatible = "pwm-backlight";
-                pwms = <&pwm 0 5000000>;
-
-                brightness-levels = <0 4 8 16 32 64 128 255>;
-                default-brightness-level = <6>;
-        };
diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt b/Documentation/devicetree/bindings/video/exynos_dp.txt
deleted file mode 100644
index c60da67a5d7..00000000000
--- a/Documentation/devicetree/bindings/video/exynos_dp.txt
+++ /dev/null
@@ -1,80 +0,0 @@
-The Exynos display port interface should be configured based on
-the type of panel connected to it.
-
-We use two nodes:
-        -dp-controller node
-        -dptx-phy node(defined inside dp-controller node)
-
-For the DP-PHY initialization, we use the dptx-phy node.
-Required properties for dptx-phy:
-        -reg:
-                Base address of DP PHY register.
-        -samsung,enable-mask:
-                The bit-mask used to enable/disable DP PHY.
-
-For the Panel initialization, we read data from dp-controller node.
-Required properties for dp-controller:
-        -compatible:
-                should be "samsung,exynos5-dp".
-        -reg:
-                physical base address of the controller and length
-                of memory mapped region.
-        -interrupts:
-                interrupt combiner values.
-        -interrupt-parent:
-                phandle to Interrupt combiner node.
-        -samsung,color-space:
-                input video data format.
-                        COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
-        -samsung,dynamic-range:
-                dynamic range for input video data.
-                        VESA = 0, CEA = 1
-        -samsung,ycbcr-coeff:
-                YCbCr co-efficients for input video.
-                        COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
-        -samsung,color-depth:
-                number of bits per colour component.
-                        COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
-        -samsung,link-rate:
-                link rate supported by the panel.
-                        LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
-        -samsung,lane-count:
-                number of lanes supported by the panel.
-                        LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
-
-Optional properties for dp-controller:
-        -interlaced:
-                interlace scan mode.
-                        Progressive if defined, Interlaced if not defined
-        -vsync-active-high:
-                VSYNC polarity configuration.
-                        High if defined, Low if not defined
-        -hsync-active-high:
-                HSYNC polarity configuration.
-                        High if defined, Low if not defined
-
-Example:
-
-SOC specific portion:
-        dp-controller {
-                compatible = "samsung,exynos5-dp";
-                reg = <0x145b0000 0x10000>;
-                interrupts = <10 3>;
-                interrupt-parent = <&combiner>;
-
-                dptx-phy {
-                        reg = <0x10040720>;
-                        samsung,enable-mask = <1>;
-                };
-
-        };
-
-Board Specific portion:
-        dp-controller {
-                samsung,color-space = <0>;
-                samsung,dynamic-range = <0>;
-                samsung,ycbcr-coeff = <0>;
-                samsung,color-depth = <1>;
-                samsung,link-rate = <0x0a>;
-                samsung,lane-count = <4>;
-        };
diff --git a/Documentation/devicetree/bindings/video/ssd1307fb.txt b/Documentation/devicetree/bindings/video/ssd1307fb.txt
deleted file mode 100644
index 3d0060cff06..00000000000
--- a/Documentation/devicetree/bindings/video/ssd1307fb.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-* Solomon SSD1307 Framebuffer Driver
-
-Required properties:
-  - compatible: Should be "solomon,ssd1307fb-<bus>". The only supported bus for
-    now is i2c.
-  - reg: Should contain address of the controller on the I2C bus. Most likely
-         0x3c or 0x3d
-  - pwm: Should contain the pwm to use according to the OF device tree PWM
-         specification [0]
-  - reset-gpios: Should contain the GPIO used to reset the OLED display
-
-Optional properties:
-  - reset-active-low: Is the reset gpio is active on physical low?
-
-[0]: Documentation/devicetree/bindings/pwm/pwm.txt
-
-Examples:
-ssd1307: oled@3c {
-        compatible = "solomon,ssd1307fb-i2c";
-        reg = <0x3c>;
-        pwms = <&pwm 4 3000>;
-        reset-gpios = <&gpio2 7>;
-        reset-active-low;
-};
diff --git a/Documentation/devicetree/bindings/video/via,vt8500-fb.txt b/Documentation/devicetree/bindings/video/via,vt8500-fb.txt
deleted file mode 100644
index c870b6478ec..00000000000
--- a/Documentation/devicetree/bindings/video/via,vt8500-fb.txt
+++ /dev/null
@@ -1,62 +0,0 @@
-VIA VT8500 Framebuffer
------------------------------------------------------
-
-Required properties:
-- compatible : "via,vt8500-fb"
-- reg : Should contain 1 register ranges(address and length)
-- interrupts : framebuffer controller interrupt
-- display: a phandle pointing to the display node
-
-Required nodes:
-- display: a display node is required to initialize the lcd panel
-        This should be in the board dts.
-- default-mode: a videomode within the display with timing parameters
-        as specified below.
-
-Example:
-
-        fb@d800e400 {
-                compatible = "via,vt8500-fb";
-                reg = <0xd800e400 0x400>;
-                interrupts = <12>;
-                display = <&display>;
-                default-mode = <&mode0>;
-        };
-
-VIA VT8500 Display
------------------------------------------------------
-Required properties (as per of_videomode_helper):
-
- - hactive, vactive: Display resolution
- - hfront-porch, hback-porch, hsync-len: Horizontal Display timing parameters
-   in pixels
-   vfront-porch, vback-porch, vsync-len: Vertical display timing parameters in
-   lines
- - clock: displayclock in Hz
- - bpp: lcd panel bit-depth.
-        <16> for RGB565, <32> for RGB888
-
-Optional properties (as per of_videomode_helper):
- - width-mm, height-mm: Display dimensions in mm
- - hsync-active-high (bool): Hsync pulse is active high
- - vsync-active-high (bool): Vsync pulse is active high
- - interlaced (bool): This is an interlaced mode
- - doublescan (bool): This is a doublescan mode
-
-Example:
-        display: display@0 {
-                modes {
-                        mode0: mode@0 {
-                                hactive = <800>;
-                                vactive = <480>;
-                                hback-porch = <88>;
-                                hfront-porch = <40>;
-                                hsync-len = <0>;
-                                vback-porch = <32>;
-                                vfront-porch = <11>;
-                                vsync-len = <1>;
-                                clock = <0>;    /* unused but required */
-                                bpp = <16>;     /* non-standard but required */
-                        };
-                };
-        };
diff --git a/Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt b/Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt
deleted file mode 100644
index a850fa011f0..00000000000
--- a/Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-VIA/Wondermedia Graphics Engine Controller
------------------------------------------------------
-
-Required properties:
-- compatible : "wm,prizm-ge-rops"
-- reg : Should contain 1 register ranges(address and length)
-
-Example:
-
-        ge_rops@d8050400 {
-                compatible = "wm,prizm-ge-rops";
-                reg = <0xd8050400 0x100>;
-        };
diff --git a/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt b/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt
deleted file mode 100644
index 3d325e1d11e..00000000000
--- a/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-Wondermedia WM8505 Framebuffer
------------------------------------------------------
-
-Required properties:
-- compatible : "wm,wm8505-fb"
-- reg : Should contain 1 register ranges(address and length)
-- via,display: a phandle pointing to the display node
-
-Required nodes:
-- display: a display node is required to initialize the lcd panel
-        This should be in the board dts. See definition in
-        Documentation/devicetree/bindings/video/via,vt8500-fb.txt
-- default-mode: a videomode node as specified in
-        Documentation/devicetree/bindings/video/via,vt8500-fb.txt
-
-Example:
-
-        fb@d8050800 {
-                compatible = "wm,wm8505-fb";
-                reg = <0xd8050800 0x200>;
-                display = <&display>;
-                default-mode = <&mode0>;
-        };
diff --git a/Documentation/devicetree/bindings/virtio/mmio.txt b/Documentation/devicetree/bindings/virtio/mmio.txt
deleted file mode 100644
index 5069c1b8e19..00000000000
--- a/Documentation/devicetree/bindings/virtio/mmio.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-* virtio memory mapped device
-
-See http://ozlabs.org/~rusty/virtio-spec/ for more details.
-
-Required properties:
-
-- compatible:   "virtio,mmio" compatibility string
-- reg:          control registers base address and size including configuration space
-- interrupts:   interrupt generated by the device
-
-Example:
-
-        virtio_block@3000 {
-                compatible = "virtio,mmio";
-                reg = <0x3000 0x100>;
-                interrupts = <41>;
-        }
diff --git a/Documentation/devicetree/bindings/w1/w1-gpio.txt b/Documentation/devicetree/bindings/w1/w1-gpio.txt
deleted file mode 100644
index 6e09c35d9f1..00000000000
--- a/Documentation/devicetree/bindings/w1/w1-gpio.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-w1-gpio devicetree bindings
-
-Required properties:
-
- - compatible: "w1-gpio"
- - gpios: one or two GPIO specs:
-                - the first one is used as data I/O pin
-                - the second one is optional. If specified, it is used as
-                  enable pin for an external pin pullup.
-
-Optional properties:
-
- - linux,open-drain: if specified, the data pin is considered in
-                     open-drain mode.
-
-Examples:
-
-        onewire@0 {
-                compatible = "w1-gpio";
-                gpios = <&gpio 126 0>, <&gpio 105 0>;
-        };
-
diff --git a/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt b/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt
deleted file mode 100644
index 2957ebb5aa7..00000000000
--- a/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-* Atmel Watchdog Timers
-
-** at91sam9-wdt
-
-Required properties:
-- compatible: must be "atmel,at91sam9260-wdt".
-- reg: physical base address of the controller and length of memory mapped
-  region.
-
-Example:
-
-        watchdog@fffffd40 {
-                compatible = "atmel,at91sam9260-wdt";
-                reg = <0xfffffd40 0x10>;
-        };
diff --git a/Documentation/devicetree/bindings/watchdog/brcm,bcm2835-pm-wdog.txt b/Documentation/devicetree/bindings/watchdog/brcm,bcm2835-pm-wdog.txt
deleted file mode 100644
index d209366b4a6..00000000000
--- a/Documentation/devicetree/bindings/watchdog/brcm,bcm2835-pm-wdog.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-BCM2835 Watchdog timer
-
-Required properties:
-
-- compatible : should be "brcm,bcm2835-pm-wdt"
-- reg : Specifies base physical address and size of the registers.
-
-Example:
-
-watchdog {
-        compatible = "brcm,bcm2835-pm-wdt";
-        reg = <0x7e100000 0x28>;
-};
diff --git a/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt b/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
deleted file mode 100644
index 75558ccd9a0..00000000000
--- a/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-DaVinci Watchdog Timer (WDT) Controller
-
-Required properties:
-- compatible : Should be "ti,davinci-wdt"
-- reg : Should contain WDT registers location and length
-
-Examples:
-
-wdt: wdt@2320000 {
-        compatible = "ti,davinci-wdt";
-        reg = <0x02320000 0x80>;
-};
diff --git a/Documentation/devicetree/bindings/watchdog/marvel.txt b/Documentation/devicetree/bindings/watchdog/marvel.txt
deleted file mode 100644
index 0b2503ab0a0..00000000000
--- a/Documentation/devicetree/bindings/watchdog/marvel.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-* Marvell Orion Watchdog Time
-
-Required Properties:
-
-- Compatibility : "marvell,orion-wdt"
-- reg           : Address of the timer registers
-
-Example:
-
-        wdt@20300 {
-                compatible = "marvell,orion-wdt";
-                reg = <0x20300 0x28>;
-                status = "okay";
-        };
diff --git a/Documentation/devicetree/bindings/watchdog/omap-wdt.txt b/Documentation/devicetree/bindings/watchdog/omap-wdt.txt
deleted file mode 100644
index c227970671e..00000000000
--- a/Documentation/devicetree/bindings/watchdog/omap-wdt.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-TI Watchdog Timer (WDT) Controller for OMAP
-
-Required properties:
-compatible:
-- "ti,omap3-wdt" for OMAP3
-- "ti,omap4-wdt" for OMAP4
-- ti,hwmods: Name of the hwmod associated to the WDT
-
-Examples:
-
-wdt2: wdt@4a314000 {
-        compatible = "ti,omap4-wdt", "ti,omap3-wdt";
-        ti,hwmods = "wd_timer2";
-};
diff --git a/Documentation/devicetree/bindings/watchdog/pnx4008-wdt.txt b/Documentation/devicetree/bindings/watchdog/pnx4008-wdt.txt
deleted file mode 100644
index 7c7f6887c79..00000000000
--- a/Documentation/devicetree/bindings/watchdog/pnx4008-wdt.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-* NXP PNX watchdog timer
-
-Required properties:
-- compatible: must be "nxp,pnx4008-wdt"
-- reg: physical base address of the controller and length of memory mapped
-  region.
-
-Example:
-
-        watchdog@4003C000 {
-                compatible = "nxp,pnx4008-wdt";
-                reg = <0x4003C000 0x1000>;
-        };
diff --git a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
deleted file mode 100644
index 0b271777560..00000000000
--- a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-Allwinner sunXi Watchdog timer
-
-Required properties:
-
-- compatible : should be "allwinner,sunxi-wdt"
-- reg : Specifies base physical address and size of the registers.
-
-Example:
-
-wdt: watchdog@01c20c90 {
-        compatible = "allwinner,sunxi-wdt";
-        reg = <0x01c20c90 0x10>;
-};
diff --git a/Documentation/devicetree/bindings/watchdog/twl4030-wdt.txt b/Documentation/devicetree/bindings/watchdog/twl4030-wdt.txt
deleted file mode 100644
index 80a37193c0b..00000000000
--- a/Documentation/devicetree/bindings/watchdog/twl4030-wdt.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-Device tree bindings for twl4030-wdt driver (TWL4030 watchdog)
-
-Required properties:
-        compatible = "ti,twl4030-wdt";
-
-Example:
-
-watchdog {
-        compatible = "ti,twl4030-wdt";
-};
diff --git a/Documentation/devicetree/booting-without-of.txt b/Documentation/devicetree/booting-without-of.txt
index d4d66757354..7c1329de059 100644
--- a/Documentation/devicetree/booting-without-of.txt
+++ b/Documentation/devicetree/booting-without-of.txt
@@ -169,7 +169,7 @@ it with special cases.
 
         b) Entry with a flattened device-tree block.  Firmware loads the
         physical address of the flattened device tree block (dtb) into r2,
-        r1 is not used, but it is considered good practice to use a valid
+        r1 is not used, but it is considered good practise to use a valid
         machine number as described in Documentation/arm/Booting.
 
                 r0 : 0
@@ -551,13 +551,12 @@ Here is an example of a simple device-tree. In this example, an "o"
 designates a node followed by the node unit name. Properties are
 presented with their name followed by their content. "content"
 represents an ASCII string (zero terminated) value, while <content>
-represents a 32-bit value, specified in decimal or hexadecimal (the
-latter prefixed 0x). The various nodes in this example will be
-discussed in a later chapter. At this point, it is only meant to give
-you a idea of what a device-tree looks like. I have purposefully kept
-the "name" and "linux,phandle" properties which aren't necessary in
-order to give you a better idea of what the tree looks like in
-practice.
+represents a 32-bit hexadecimal value. The various nodes in this
+example will be discussed in a later chapter. At this point, it is
+only meant to give you a idea of what a device-tree looks like. I have
+purposefully kept the "name" and "linux,phandle" properties which
+aren't necessary in order to give you a better idea of what the tree
+looks like in practice.
 
   / o device-tree
       |- name = "device-tree"
@@ -577,14 +576,14 @@ practice.
       |   |- name = "PowerPC,970"
       |   |- device_type = "cpu"
       |   |- reg = <0>
-      |   |- clock-frequency = <0x5f5e1000>
+      |   |- clock-frequency = <5f5e1000>
       |   |- 64-bit
       |   |- linux,phandle = <2>
       |
       o memory@0
       | |- name = "memory"
       | |- device_type = "memory"
-      | |- reg = <0x00000000 0x00000000 0x00000000 0x20000000>
+      | |- reg = <00000000 00000000 00000000 20000000>
       | |- linux,phandle = <3>
       |
       o chosen
@@ -1011,8 +1010,8 @@ compatibility.
                 #size-cells = <1>;
                 #interrupt-cells = <2>;
                 device_type = "soc";
-                ranges = <0x00000000 0xe0000000 0x00100000>
-                reg = <0xe0000000 0x00003000>;
+                ranges = <00000000 e0000000 00100000>
+                reg = <e0000000 00003000>;
                 bus-frequency = <0>;
         }
 
@@ -1086,16 +1085,16 @@ supported currently at the toplevel.
                                  * terminated string
                                  */
 
-  property2 = <0x1234abcd>;     /* define a property containing a
+  property2 = <1234abcd>;       /* define a property containing a
                                  * numerical 32-bit value (hexadecimal)
                                  */
 
-  property3 = <0x12345678 0x12345678 0xdeadbeef>;
+  property3 = <12345678 12345678 deadbeef>;
                                 /* define a property containing 3
                                  * numerical 32-bit values (cells) in
                                  * hexadecimal
                                  */
-  property4 = [0x0a 0x0b 0x0c 0x0d 0xde 0xea 0xad 0xbe 0xef];
+  property4 = [0a 0b 0c 0d de ea ad be ef];
                                 /* define a property whose content is
                                  * an arbitrary array of bytes
                                  */
@@ -1351,10 +1350,10 @@ Appendix A - Sample SOC node for MPC8540
                         model = "TSEC";
                         compatible = "gianfar", "simple-bus";
                         reg = <0x24000 0x1000>;
-                        local-mac-address = [ 0x00 0xE0 0x0C 0x00 0x73 0x00 ];
-                        interrupts = <0x29 2 0x30 2 0x34 2>;
+                        local-mac-address = [ 00 E0 0C 00 73 00 ];
+                        interrupts = <29 2 30 2 34 2>;
                         phy-handle = <&phy0>;
-                        sleep = <&pmc 0x00000080>;
+                        sleep = <&pmc 00000080>;
                         ranges;
 
                         mdio@24520 {
@@ -1386,10 +1385,10 @@ Appendix A - Sample SOC node for MPC8540
                         model = "TSEC";
                         compatible = "gianfar";
                         reg = <0x25000 0x1000>;
-                        local-mac-address = [ 0x00 0xE0 0x0C 0x00 0x73 0x01 ];
-                        interrupts = <0x13 2 0x14 2 0x18 2>;
+                        local-mac-address = [ 00 E0 0C 00 73 01 ];
+                        interrupts = <13 2 14 2 18 2>;
                         phy-handle = <&phy1>;
-                        sleep = <&pmc 0x00000040>;
+                        sleep = <&pmc 00000040>;
                 };
 
                 ethernet@26000 {
@@ -1397,17 +1396,17 @@ Appendix A - Sample SOC node for MPC8540
                         model = "FEC";
                         compatible = "gianfar";
                         reg = <0x26000 0x1000>;
-                        local-mac-address = [ 0x00 0xE0 0x0C 0x00 0x73 0x02 ];
-                        interrupts = <0x41 2>;
+                        local-mac-address = [ 00 E0 0C 00 73 02 ];
+                        interrupts = <41 2>;
                         phy-handle = <&phy3>;
-                        sleep = <&pmc 0x00000020>;
+                        sleep = <&pmc 00000020>;
                 };
 
                 serial@4500 {
                         #address-cells = <1>;
                         #size-cells = <1>;
                         compatible = "fsl,mpc8540-duart", "simple-bus";
-                        sleep = <&pmc 0x00000002>;
+                        sleep = <&pmc 00000002>;
                         ranges;
 
                         serial@4500 {
@@ -1415,7 +1414,7 @@ Appendix A - Sample SOC node for MPC8540
                                 compatible = "ns16550";
                                 reg = <0x4500 0x100>;
                                 clock-frequency = <0>;
-                                interrupts = <0x42 2>;
+                                interrupts = <42 2>;
                         };
 
                         serial@4600 {
@@ -1423,7 +1422,7 @@ Appendix A - Sample SOC node for MPC8540
                                 compatible = "ns16550";
                                 reg = <0x4600 0x100>;
                                 clock-frequency = <0>;
-                                interrupts = <0x42 2>;
+                                interrupts = <42 2>;
                         };
                 };
 
@@ -1437,11 +1436,11 @@ Appendix A - Sample SOC node for MPC8540
                 };
 
                 i2c@3000 {
-                        interrupts = <0x43 2>;
+                        interrupts = <43 2>;
                         reg = <0x3000 0x100>;
                         compatible  = "fsl-i2c";
                         dfsrr;
-                        sleep = <&pmc 0x00000004>;
+                        sleep = <&pmc 00000004>;
                 };
 
                 pmc: power@e0070 {
diff --git a/Documentation/devicetree/usage-model.txt b/Documentation/devicetree/usage-model.txt
deleted file mode 100644
index ef9d06c9f8f..00000000000
--- a/Documentation/devicetree/usage-model.txt
+++ /dev/null
@@ -1,412 +0,0 @@
-Linux and the Device Tree
--------------------------
-The Linux usage model for device tree data
-
-Author: Grant Likely <grant.likely@secretlab.ca>
-
-This article describes how Linux uses the device tree.  An overview of
-the device tree data format can be found on the device tree usage page
-at devicetree.org[1].
-
-[1] http://devicetree.org/Device_Tree_Usage
-
-The "Open Firmware Device Tree", or simply Device Tree (DT), is a data
-structure and language for describing hardware.  More specifically, it
-is a description of hardware that is readable by an operating system
-so that the operating system doesn't need to hard code details of the
-machine.
-
-Structurally, the DT is a tree, or acyclic graph with named nodes, and
-nodes may have an arbitrary number of named properties encapsulating
-arbitrary data.  A mechanism also exists to create arbitrary
-links from one node to another outside of the natural tree structure.
-
-Conceptually, a common set of usage conventions, called 'bindings',
-is defined for how data should appear in the tree to describe typical
-hardware characteristics including data busses, interrupt lines, GPIO
-connections, and peripheral devices.
-
-As much as possible, hardware is described using existing bindings to
-maximize use of existing support code, but since property and node
-names are simply text strings, it is easy to extend existing bindings
-or create new ones by defining new nodes and properties.  Be wary,
-however, of creating a new binding without first doing some homework
-about what already exists.  There are currently two different,
-incompatible, bindings for i2c busses that came about because the new
-binding was created without first investigating how i2c devices were
-already being enumerated in existing systems.
-
-1. History
-----------
-The DT was originally created by Open Firmware as part of the
-communication method for passing data from Open Firmware to a client
-program (like to an operating system).  An operating system used the
-Device Tree to discover the topology of the hardware at runtime, and
-thereby support a majority of available hardware without hard coded
-information (assuming drivers were available for all devices).
-
-Since Open Firmware is commonly used on PowerPC and SPARC platforms,
-the Linux support for those architectures has for a long time used the
-Device Tree.
-
-In 2005, when PowerPC Linux began a major cleanup and to merge 32-bit
-and 64-bit support, the decision was made to require DT support on all
-powerpc platforms, regardless of whether or not they used Open
-Firmware.  To do this, a DT representation called the Flattened Device
-Tree (FDT) was created which could be passed to the kernel as a binary
-blob without requiring a real Open Firmware implementation.  U-Boot,
-kexec, and other bootloaders were modified to support both passing a
-Device Tree Binary (dtb) and to modify a dtb at boot time.  DT was
-also added to the PowerPC boot wrapper (arch/powerpc/boot/*) so that
-a dtb could be wrapped up with the kernel image to support booting
-existing non-DT aware firmware.
-
-Some time later, FDT infrastructure was generalized to be usable by
-all architectures.  At the time of this writing, 6 mainlined
-architectures (arm, microblaze, mips, powerpc, sparc, and x86) and 1
-out of mainline (nios) have some level of DT support.
-
-2. Data Model
--------------
-If you haven't already read the Device Tree Usage[1] page,
-then go read it now.  It's okay, I'll wait....
-
-2.1 High Level View
--------------------
-The most important thing to understand is that the DT is simply a data
-structure that describes the hardware.  There is nothing magical about
-it, and it doesn't magically make all hardware configuration problems
-go away.  What it does do is provide a language for decoupling the
-hardware configuration from the board and device driver support in the
-Linux kernel (or any other operating system for that matter).  Using
-it allows board and device support to become data driven; to make
-setup decisions based on data passed into the kernel instead of on
-per-machine hard coded selections.
-
-Ideally, data driven platform setup should result in less code
-duplication and make it easier to support a wide range of hardware
-with a single kernel image.
-
-Linux uses DT data for three major purposes:
-1) platform identification,
-2) runtime configuration, and
-3) device population.
-
-2.2 Platform Identification
----------------------------
-First and foremost, the kernel will use data in the DT to identify the
-specific machine.  In a perfect world, the specific platform shouldn't
-matter to the kernel because all platform details would be described
-perfectly by the device tree in a consistent and reliable manner.
-Hardware is not perfect though, and so the kernel must identify the
-machine during early boot so that it has the opportunity to run
-machine-specific fixups.
-
-In the majority of cases, the machine identity is irrelevant, and the
-kernel will instead select setup code based on the machine's core
-CPU or SoC.  On ARM for example, setup_arch() in
-arch/arm/kernel/setup.c will call setup_machine_fdt() in
-arch/arm/kernel/devicetree.c which searches through the machine_desc
-table and selects the machine_desc which best matches the device tree
-data.  It determines the best match by looking at the 'compatible'
-property in the root device tree node, and comparing it with the
-dt_compat list in struct machine_desc.
-
-The 'compatible' property contains a sorted list of strings starting
-with the exact name of the machine, followed by an optional list of
-boards it is compatible with sorted from most compatible to least.  For
-example, the root compatible properties for the TI BeagleBoard and its
-successor, the BeagleBoard xM board might look like:
-
-        compatible = "ti,omap3-beagleboard", "ti,omap3450", "ti,omap3";
-        compatible = "ti,omap3-beagleboard-xm", "ti,omap3450", "ti,omap3";
-
-Where "ti,omap3-beagleboard-xm" specifies the exact model, it also
-claims that it compatible with the OMAP 3450 SoC, and the omap3 family
-of SoCs in general.  You'll notice that the list is sorted from most
-specific (exact board) to least specific (SoC family).
-
-Astute readers might point out that the Beagle xM could also claim
-compatibility with the original Beagle board.  However, one should be
-cautioned about doing so at the board level since there is typically a
-high level of change from one board to another, even within the same
-product line, and it is hard to nail down exactly what is meant when one
-board claims to be compatible with another.  For the top level, it is
-better to err on the side of caution and not claim one board is
-compatible with another.  The notable exception would be when one
-board is a carrier for another, such as a CPU module attached to a
-carrier board.
-
-One more note on compatible values.  Any string used in a compatible
-property must be documented as to what it indicates.  Add
-documentation for compatible strings in Documentation/devicetree/bindings.
-
-Again on ARM, for each machine_desc, the kernel looks to see if
-any of the dt_compat list entries appear in the compatible property.
-If one does, then that machine_desc is a candidate for driving the
-machine.  After searching the entire table of machine_descs,
-setup_machine_fdt() returns the 'most compatible' machine_desc based
-on which entry in the compatible property each machine_desc matches
-against.  If no matching machine_desc is found, then it returns NULL.
-
-The reasoning behind this scheme is the observation that in the majority
-of cases, a single machine_desc can support a large number of boards
-if they all use the same SoC, or same family of SoCs.  However,
-invariably there will be some exceptions where a specific board will
-require special setup code that is not useful in the generic case.
-Special cases could be handled by explicitly checking for the
-troublesome board(s) in generic setup code, but doing so very quickly
-becomes ugly and/or unmaintainable if it is more than just a couple of
-cases.
-
-Instead, the compatible list allows a generic machine_desc to provide
-support for a wide common set of boards by specifying "less
-compatible" value in the dt_compat list.  In the example above,
-generic board support can claim compatibility with "ti,omap3" or
-"ti,omap3450".  If a bug was discovered on the original beagleboard
-that required special workaround code during early boot, then a new
-machine_desc could be added which implements the workarounds and only
-matches on "ti,omap3-beagleboard".
-
-PowerPC uses a slightly different scheme where it calls the .probe()
-hook from each machine_desc, and the first one returning TRUE is used.
-However, this approach does not take into account the priority of the
-compatible list, and probably should be avoided for new architecture
-support.
-
-2.3 Runtime configuration
--------------------------
-In most cases, a DT will be the sole method of communicating data from
-firmware to the kernel, so also gets used to pass in runtime and
-configuration data like the kernel parameters string and the location
-of an initrd image.
-
-Most of this data is contained in the /chosen node, and when booting
-Linux it will look something like this:
-
-        chosen {
-                bootargs = "console=ttyS0,115200 loglevel=8";
-                initrd-start = <0xc8000000>;
-                initrd-end = <0xc8200000>;
-        };
-
-The bootargs property contains the kernel arguments, and the initrd-*
-properties define the address and size of an initrd blob.  The
-chosen node may also optionally contain an arbitrary number of
-additional properties for platform-specific configuration data.
-
-During early boot, the architecture setup code calls of_scan_flat_dt()
-several times with different helper callbacks to parse device tree
-data before paging is setup.  The of_scan_flat_dt() code scans through
-the device tree and uses the helpers to extract information required
-during early boot.  Typically the early_init_dt_scan_chosen() helper
-is used to parse the chosen node including kernel parameters,
-early_init_dt_scan_root() to initialize the DT address space model,
-and early_init_dt_scan_memory() to determine the size and
-location of usable RAM.
-
-On ARM, the function setup_machine_fdt() is responsible for early
-scanning of the device tree after selecting the correct machine_desc
-that supports the board.
-
-2.4 Device population
----------------------
-After the board has been identified, and after the early configuration data
-has been parsed, then kernel initialization can proceed in the normal
-way.  At some point in this process, unflatten_device_tree() is called
-to convert the data into a more efficient runtime representation.
-This is also when machine-specific setup hooks will get called, like
-the machine_desc .init_early(), .init_irq() and .init_machine() hooks
-on ARM.  The remainder of this section uses examples from the ARM
-implementation, but all architectures will do pretty much the same
-thing when using a DT.
-
-As can be guessed by the names, .init_early() is used for any machine-
-specific setup that needs to be executed early in the boot process,
-and .init_irq() is used to set up interrupt handling.  Using a DT
-doesn't materially change the behaviour of either of these functions.
-If a DT is provided, then both .init_early() and .init_irq() are able
-to call any of the DT query functions (of_* in include/linux/of*.h) to
-get additional data about the platform.
-
-The most interesting hook in the DT context is .init_machine() which
-is primarily responsible for populating the Linux device model with
-data about the platform.  Historically this has been implemented on
-embedded platforms by defining a set of static clock structures,
-platform_devices, and other data in the board support .c file, and
-registering it en-masse in .init_machine().  When DT is used, then
-instead of hard coding static devices for each platform, the list of
-devices can be obtained by parsing the DT, and allocating device
-structures dynamically.
-
-The simplest case is when .init_machine() is only responsible for
-registering a block of platform_devices.  A platform_device is a concept
-used by Linux for memory or I/O mapped devices which cannot be detected
-by hardware, and for 'composite' or 'virtual' devices (more on those
-later).  While there is no 'platform device' terminology for the DT,
-platform devices roughly correspond to device nodes at the root of the
-tree and children of simple memory mapped bus nodes.
-
-About now is a good time to lay out an example.  Here is part of the
-device tree for the NVIDIA Tegra board.
-
-/{
-        compatible = "nvidia,harmony", "nvidia,tegra20";
-        #address-cells = <1>;
-        #size-cells = <1>;
-        interrupt-parent = <&intc>;
-
-        chosen { };
-        aliases { };
-
-        memory {
-                device_type = "memory";
-                reg = <0x00000000 0x40000000>;
-        };
-
-        soc {
-                compatible = "nvidia,tegra20-soc", "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-
-                intc: interrupt-controller@50041000 {
-                        compatible = "nvidia,tegra20-gic";
-                        interrupt-controller;
-                        #interrupt-cells = <1>;
-                        reg = <0x50041000 0x1000>, < 0x50040100 0x0100 >;
-                };
-
-                serial@70006300 {
-                        compatible = "nvidia,tegra20-uart";
-                        reg = <0x70006300 0x100>;
-                        interrupts = <122>;
-                };
-
-                i2s1: i2s@70002800 {
-                        compatible = "nvidia,tegra20-i2s";
-                        reg = <0x70002800 0x100>;
-                        interrupts = <77>;
-                        codec = <&wm8903>;
-                };
-
-                i2c@7000c000 {
-                        compatible = "nvidia,tegra20-i2c";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        reg = <0x7000c000 0x100>;
-                        interrupts = <70>;
-
-                        wm8903: codec@1a {
-                                compatible = "wlf,wm8903";
-                                reg = <0x1a>;
-                                interrupts = <347>;
-                        };
-                };
-        };
-
-        sound {
-                compatible = "nvidia,harmony-sound";
-                i2s-controller = <&i2s1>;
-                i2s-codec = <&wm8903>;
-        };
-};
-
-At .init_machine() time, Tegra board support code will need to look at
-this DT and decide which nodes to create platform_devices for.
-However, looking at the tree, it is not immediately obvious what kind
-of device each node represents, or even if a node represents a device
-at all.  The /chosen, /aliases, and /memory nodes are informational
-nodes that don't describe devices (although arguably memory could be
-considered a device).  The children of the /soc node are memory mapped
-devices, but the codec@1a is an i2c device, and the sound node
-represents not a device, but rather how other devices are connected
-together to create the audio subsystem.  I know what each device is
-because I'm familiar with the board design, but how does the kernel
-know what to do with each node?
-
-The trick is that the kernel starts at the root of the tree and looks
-for nodes that have a 'compatible' property.  First, it is generally
-assumed that any node with a 'compatible' property represents a device
-of some kind, and second, it can be assumed that any node at the root
-of the tree is either directly attached to the processor bus, or is a
-miscellaneous system device that cannot be described any other way.
-For each of these nodes, Linux allocates and registers a
-platform_device, which in turn may get bound to a platform_driver.
-
-Why is using a platform_device for these nodes a safe assumption?
-Well, for the way that Linux models devices, just about all bus_types
-assume that its devices are children of a bus controller.  For
-example, each i2c_client is a child of an i2c_master.  Each spi_device
-is a child of an SPI bus.  Similarly for USB, PCI, MDIO, etc.  The
-same hierarchy is also found in the DT, where I2C device nodes only
-ever appear as children of an I2C bus node.  Ditto for SPI, MDIO, USB,
-etc.  The only devices which do not require a specific type of parent
-device are platform_devices (and amba_devices, but more on that
-later), which will happily live at the base of the Linux /sys/devices
-tree.  Therefore, if a DT node is at the root of the tree, then it
-really probably is best registered as a platform_device.
-
-Linux board support code calls of_platform_populate(NULL, NULL, NULL, NULL)
-to kick off discovery of devices at the root of the tree.  The
-parameters are all NULL because when starting from the root of the
-tree, there is no need to provide a starting node (the first NULL), a
-parent struct device (the last NULL), and we're not using a match
-table (yet).  For a board that only needs to register devices,
-.init_machine() can be completely empty except for the
-of_platform_populate() call.
-
-In the Tegra example, this accounts for the /soc and /sound nodes, but
-what about the children of the SoC node?  Shouldn't they be registered
-as platform devices too?  For Linux DT support, the generic behaviour
-is for child devices to be registered by the parent's device driver at
-driver .probe() time.  So, an i2c bus device driver will register a
-i2c_client for each child node, an SPI bus driver will register
-its spi_device children, and similarly for other bus_types.
-According to that model, a driver could be written that binds to the
-SoC node and simply registers platform_devices for each of its
-children.  The board support code would allocate and register an SoC
-device, a (theoretical) SoC device driver could bind to the SoC device,
-and register platform_devices for /soc/interrupt-controller, /soc/serial,
-/soc/i2s, and /soc/i2c in its .probe() hook.  Easy, right?
-
-Actually, it turns out that registering children of some
-platform_devices as more platform_devices is a common pattern, and the
-device tree support code reflects that and makes the above example
-simpler.  The second argument to of_platform_populate() is an
-of_device_id table, and any node that matches an entry in that table
-will also get its child nodes registered.  In the tegra case, the code
-can look something like this:
-
-static void __init harmony_init_machine(void)
-{
-        /* ... */
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
-"simple-bus" is defined in the ePAPR 1.0 specification as a property
-meaning a simple memory mapped bus, so the of_platform_populate() code
-could be written to just assume simple-bus compatible nodes will
-always be traversed.  However, we pass it in as an argument so that
-board support code can always override the default behaviour.
-
-[Need to add discussion of adding i2c/spi/etc child devices]
-
-Appendix A: AMBA devices
-------------------------
-
-ARM Primecells are a certain kind of device attached to the ARM AMBA
-bus which include some support for hardware detection and power
-management.  In Linux, struct amba_device and the amba_bus_type is
-used to represent Primecell devices.  However, the fiddly bit is that
-not all devices on an AMBA bus are Primecells, and for Linux it is
-typical for both amba_device and platform_device instances to be
-siblings of the same bus segment.
-
-When using the DT, this creates problems for of_platform_populate()
-because it must decide whether to register each node as either a
-platform_device or an amba_device.  This unfortunately complicates the
-device creation model a little bit, but the solution turns out not to
-be too invasive.  If a node is compatible with "arm,amba-primecell", then
-of_platform_populate() will register it as an amba_device instead of a
-platform_device.