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1* ARM architected timer
2
3ARM Cortex-A7 and Cortex-A15 have a per-core architected timer, which
4provides per-cpu timers.
5
6The timer is attached to a GIC to deliver its per-processor interrupts.
7
8** Timer node properties:
9
10- compatible : Should at least contain "arm,armv7-timer".
11
12- interrupts : Interrupt list for secure, non-secure, virtual and
13 hypervisor timers, in that order.
14
15- clock-frequency : The frequency of the main counter, in Hz. Optional.
16
17Example:
18
19 timer {
20 compatible = "arm,cortex-a15-timer",
21 "arm,armv7-timer";
22 interrupts = <1 13 0xf08>,
23 <1 14 0xf08>,
24 <1 11 0xf08>,
25 <1 10 0xf08>;
26 clock-frequency = <100000000>;
27 };