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* ASoC: tegra: call pm_runtime APIs around register accessesStephen Warren2013-12-11
| | | | | | | | | | | | | | Call pm_runtime_get_sync() before all register accesses; the HW requires clocks to be running when accessing registers. This hasn't been needed to date, since all register IO was performed while playback was active, and hence the ASoC core had already called pm_runtime_get(). However, an imminent future commit will allocate and set up the FIFOs and routing during probe(), when that "protection" won't be in place. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Mark Brown <broonie@linaro.org>
* ASoC: tegra: use reset frameworkStephen Warren2013-12-11
| | | | | | | | | | | | | | | | | | | | | | Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. This change also renames "clock"/"clk" to "modules"/"mod" in symbols related to entries in configlink_clocks[], since: - We don't care about clock handles any more, but rather reset handles, so the old name isn't applicable. - It really is a list of modules on the bus, about which we currently only care about reset handles. If we start caring about any other aspect of the modules in the future, we won't have to rename all these symbols again. Note: The addition of "depends COMMON_CLOCK" is something that was missing before, not a new requirement. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Mark Brown <broonie@linaro.org> Reviewed-by: Thierry Reding <treding@nvidia.com>
* dma: tegra: register as an OF DMA controllerStephen Warren2013-12-11
| | | | | | | | | | | | | Call of_dma_controller_register() so that DMA clients can look up the Tegra DMA controller using standard APIs. This requires the of_xlate() function to save off the DMA slave ID, and for tegra_dma_slave_config() not to over-write this information; once DMA client drivers are converted to dma_request_slave_channel() and DT-based lookups, they won't set this field of struct dma_slave_config anymore. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Thierry Reding <treding@nvidia.com>
* dma: tegra: use reset frameworkStephen Warren2013-12-11
| | | | | | | | | | | Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-by: Dan Williams <dan.j.williams@intel.com> Acked-by: Vinod Koul <vinod.koul@intel.com>
* ARM: tegra: pass reset to tegra_powergate_sequence_power_up()Stephen Warren2013-12-11
| | | | | | | | | | | | Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Acked-By: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: use reset frameworkStephen Warren2013-12-11
| | | | | | | | | Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>
* pci: tegra: use reset frameworkStephen Warren2013-12-11
| | | | | | | | | | | | | | | | Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. The old Tegra-specific API used a struct clock to represent the module to reset. Some of the clocks retrieved during probe() were only used for reset purposes, and indeed aren't even true clocks. So, there's no need to get() them any more. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: implement a reset driverStephen Warren2013-12-11
| | | | | | | | | | | | | The Tegra CAR module implements both a clock and reset controller. So far, the driver exposes the clock feature via the common clock API and the reset feature using a custom API. This patch adds an implementation of the common reset framework API (include/linux/reset*.h). The legacy reset implementation will be removed once all drivers have been converted. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
* ARM: tegra: select the reset frameworkStephen Warren2013-12-11
| | | | | | | | | The Tegra clock driver is built unconditionally when Tegra support is enabled. In order to avoid having to ifdef the forthcoming reset driver implementation, have ARCH_TEGRA select RESET_CONTROLLER. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: update DT files to add DMA propertiesStephen Warren2013-12-11
| | | | | | | | | This patch switches the Tegra DT files to use the standard DMA DT bindings rather than custom properties. Note that the legacy properties are not yet removed; the drivers must be updated to use the new properties first. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: update DT files to add reset propertiesStephen Warren2013-12-11
| | | | | | | | | | | | An earlier patch updated the Tegra DT bindings to require resets and reset-names properties to be filled in. This patch updates the DT files to include those properties. Note that any legacy clocks and clock-names entries that are replaced by reset properties are not yet removed; the drivers must be updated to use the new resets and reset-names properties first. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: document use of standard DMA DT bindingsStephen Warren2013-12-11
| | | | | | | | | | | Update all the Tegra DT bindings to require the standard dmas/dma-names properties rather than non-standard nvidia,dma-request-selector property. This is a DT-ABI-incompatible change. It is the second of two changes required for me to consider the Tegra DT bindings as stable, the other being the previous conversion to the common reset bindings. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: document reset properties in DT bindingsStephen Warren2013-12-11
| | | | | | | | | | | | | | Update all the Tegra DT bindings to require resets/reset-names properties where the HW module has reset inputs. Remove any entries from clocks or clock-names that were only required to identify reset inputs, rather than referring to real clocks. This is a DT-ABI-incompatible change. It is the first of two changes required for me to consider the Tegra DT bindings as stable, the other being conversion to the common DMA DT bindings. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>
* ARM: tegra: add missing clock documentation to DT bindingsStephen Warren2013-12-11
| | | | | | | | | | | | | Many of the Tegra DT binding documents say nothing about the clocks or clock-names properties, yet those are present and required in DT files. This patch simply updates the documentation file to match the implicit definition of the binding, based on real-world DT content. All Tegra bindings that mention clocks are updated to have consistent wording and formatting of the clock-related properties. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>
* Merge tag 'clk-tegra-for-3.14' into for-3.14/dmas-resets-reworkStephen Warren2013-12-11
|\ | | | | | | Tegra clk branch for 3.14
| * clk: tegra: fix __clk_lookup() return value checksWei Yongjun2013-11-28
| | | | | | | | | | | | | | | | | | In case of error, the function __clk_lookup() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| * clk: tegra: Do not print errors for clk_round_rate()Thierry Reding2013-11-28
| | | | | | | | | | | | | | | | | | | | clk_round_rate() can be used by drivers to determine whether or not a frequency is supported by the clock. The current Tegra clock driver outputs an error message and a stacktrace when the requested rate isn't supported. That's fine for clk_set_rate(), but it's confusing when all the driver does is query whether or not a frequency is supported. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: Initialize DSI low-power clocksThierry Reding2013-11-26
| | | | | | | | | | | | | | | | The low-power DSI clocks are used during host-driven transactions on the DSI bus. Documentation recommends that they be children of PLLP and run at a frequency of at least 52 MHz. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: add FUSE clock deviceAlexandre Courbot2013-11-26
| | | | | | | | | | | | | | This clock is needed to ensure the FUSE registers can be accessed without freezing the system. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
| * clk: tegra: Properly setup PWM clock on Tegra30Thierry Reding2013-11-26
| | | | | | | | | | | | | | | | The clock for the PWM controller is slightly different from other peripheral clocks on Tegra30. The clock source mux field start at bit position 28 rather than 30. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: Initialize secondary gr3d clock on Tegra30Thierry Reding2013-11-26
| | | | | | | | | | | | | | | | There are two GPUs on Tegra30 and each of them uses a separate clock, so the secondary clock needs to be initialized in order for the gr3d module to work properly. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra114: Initialize clocks needed for HDMIMikko Perttunen2013-11-26
| | | | | | | | | | | | | | | | Add disp1 and disp2 clocks to the clock initialization table. These clocks are required for display and HDMI support. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra124: add suspend/resume function for tegra_cpu_car_opsJoseph Lo2013-11-26
| | | | | | | | | | | | | | | | | | | | Adding suspend/resume function for tegra_cpu_car_ops. We only save and restore the setting of the clock of CoreSight. Other clocks still need to be taken care by clock driver. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| * clk: tegra124: add wait_for_reset and disable_clock for tegra_cpu_car_opsJoseph Lo2013-11-26
| | | | | | | | | | | | | | | | | | Hook the functions for CPU hotplug support. After the CPU is hot unplugged, the flow controller will handle to clock gate the CPU clock. But still need to implement an empty function to avoid warning message. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Joseph Lo <josephl@nvidia.com>
| * clk: tegra124: Add support for Tegra124 clocksPeter De Schrijver2013-11-26
| | | | | | | | | | | | Implement clock support for Tegra124. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| * clk: tegra124: Add new peripheral clocksPeter De Schrijver2013-11-26
| | | | | | | | | | | | | | Tegra124 introduces a number of new peripheral clocks. This patch adds those to the common peripheral clock code. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| * clk: tegra124: Add common clk IDs to clk-id.hPeter De Schrijver2013-11-26
| | | | | | | | | | | | | | Tegra124 introduces a number of a new clocks. Introduce the corresponding the IDs for them. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| * clk: tegra: add TEGRA_PERIPH_NO_GATEPeter De Schrijver2013-11-26
| | | | | | | | | | | | | | | | Tegra124 has a clock which consists of a mux and a fractional divider. Add support for this. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: add locking to periph clksPeter De Schrijver2013-11-26
| | | | | | | | | | | | | | | | Tegra124 has periph clocks which share the hw register. Hence locking is required. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: Add periph regs bank XPeter De Schrijver2013-11-26
| | | | | | | | | | | | | | Tegra124 has an extra bank of peripheral clock registers. Add it to the generic peripheral clock code. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| * clk: tegra: Add support for PLLSSPeter De Schrijver2013-11-26
| | | | | | | | | | | | Tegra124 introduces a new PLL type, PLLSS. Add support for it. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| * clk: tegra: move tegra20 to common infraPeter De Schrijver2013-11-26
| | | | | | | | | | | | Move tegra20 to common tegra clock infrastructure. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| * clk: tegra: move tegra30 to common infraPeter De Schrijver2013-11-26
| | | | | | | | | | | | Move tegra30 to common tegra clock infrastructure. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| * clk: tegra: introduce common gen4 super clockPeter De Schrijver2013-11-26
| | | | | | | | | | | | | | Introduce a common function which performs super clock initialization for Tegra114 and beyond. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| * clk: tegra: move PMC, fixed clocks to common filesPeter De Schrijver2013-11-26
| | | | | | | | | | | | | | Introduce new files for fixed and PMC clocks common between several Tegra SoCs and move Tegra114 to this new infrastructure. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| * clk: tegra: move periph clocks to common filePeter De Schrijver2013-11-26
| | | | | | | | | | | | | | | | Introduce a new file for peripheral clocks common between several Tegra SoCs and move Tegra114 to this new infrastructure. Also PLLP and the PLLP_OUT clocks will be initialized here. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| * clk: tegra: move audio clk to common filePeter De Schrijver2013-11-26
| | | | | | | | | | | | | | | | | | Move audio clocks and PLLA initialization to a common file so it can be used by multiple Tegra SoCs. Also a new array tegra114_clks is introduced for Tegra114 which specifies which common clocks are available on Tegra114 and what their DT IDs are. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| * clk: tegra: add clkdev registration infraPeter De Schrijver2013-11-26
| | | | | | | | | | | | | | Add a common infra for registering clkdev. This allows decoupling clk registration from clkdev registration. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| * clk: tegra: add common infra for DT clocksPeter De Schrijver2013-11-26
| | | | | | | | | | | | | | Introduce a common infrastructure for sharing clock initialization between SoCs. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| * clk: tegra: add header for common tegra clock IDsPeter De Schrijver2013-11-26
| | | | | | | | | | | | | | | | | | Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| * clk: tegra: move fields to tegra_clk_pll_paramsPeter De Schrijver2013-11-26
| | | | | | | | | | | | | | Move some fields related to the PLL HW description to the tegra_clk_pll_params. This allows some PLL code to be moved to common files later. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| * clk: tegra: use pll_ref as the pll_e parentPeter De Schrijver2013-11-26
| | | | | | | | | | | | | | | | | | Use pll_ref instead of pll_re_vco as the pll_e parent on Tegra114. Also add a 12Mhz pll_ref table entry for pll_e for Tegra114. This prevents the system from crashing at bootup because of an unsupported pll_re_vco rate. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| * clk: tegra: move some PLLC and PLLXC init to clk-pll.cPeter De Schrijver2013-11-26
| | | | | | | | | | | | | | | | VCO min clipping, dynamic ramp setup and IDDQ init can be done in the respective PLL clk_register functions if the parent is already registered. This is done for other some PLLs already. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| * clk: tegra: Add TEGRA_PERIPH_NO_DIV flagPeter De Schrijver2013-11-26
| | | | | | | | | | | | | | This flag indicates the peripheral clock does not have a divider. It will simplify the initialization tables and avoids some very similar code. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| * clk: tegra: common periph_clk_enb_refcnt and clksPeter De Schrijver2013-11-26
| | | | | | | | | | | | | | | | | | | | This patch makes periph_clk_enb_refcnt a global array, dynamically allocated at boottime. It simplifies the macros somewhat and allows clocks common to several Tegra SoCs to be defined in a separate files. Also the clks array becomes global and dynamically allocated which allows the DT registration to be moved to a generic funcion. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| * clk: tegra: simplify periph clock dataPeter De Schrijver2013-11-26
| | | | | | | | | | | | | | | | | | | | This patch determines the register bank for clock enable/disable and reset based on the clock ID instead of hardcoding it in the tables describing the clocks. This results in less data to be maintained in the tables, making the code easier to understand. The full benefit of the change will be realized once also other clocktypes will be table based. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| * clk: tegra: Fix clock rate computationThierry Reding2013-11-26
| | | | | | | | | | | | | | | | | | | | The PLL output frequency is multiplied during the P-divider computation, so it needs to be divided by the P-divider again before returning. This fixes an issue where clk_round_rate() would return the multiplied frequency instead of the real one after the P-divider. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * ARM: tegra30: add missing CLK IDsPeter De Schrijver2013-11-26
| | | | | | | | | | | | The Tegra30 clock bindings lack few IDs for audio and clk_out muxes. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| * clk: tegra114: Rename gr_2d/gr_3d to gr2d/gr3dThierry Reding2013-11-26
| | | | | | | | | | | | | | | | These clocks were named gr2d and gr3d on Tegra20 and Tegra30, so use the same names on Tegra114 for consistency. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| * clk: tegra: PLLE spread spectrum controlPeter De Schrijver2013-11-26
| | | | | | | | | | | | Add spread spectrum control for PLLE in Tegra114. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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