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authorThierry Reding <thierry.reding@gmail.com>2013-10-29 11:51:11 -0400
committerPeter De Schrijver <pdeschrijver@nvidia.com>2013-11-26 11:46:56 -0500
commit43e36a9646ec7d0180d638c095cca36484cc6f82 (patch)
tree01f6f55047b3319920f54369d71d6afcddb585fe
parent77f71730341e9072766eabc5bbd001aa286e7a23 (diff)
clk: tegra: Initialize secondary gr3d clock on Tegra30
There are two GPUs on Tegra30 and each of them uses a separate clock, so the secondary clock needs to be initialized in order for the gr3d module to work properly. Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r--drivers/clk/tegra/clk-tegra30.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index f7ebf2bacdd9..153ae1acd2fa 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1368,6 +1368,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
1368 {TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1}, 1368 {TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1},
1369 {TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0}, 1369 {TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0},
1370 {TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0}, 1370 {TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0},
1371 {TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0},
1371 {TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry. */ 1372 {TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry. */
1372}; 1373};
1373 1374