diff options
author | Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-09-09 06:23:56 -0400 |
---|---|---|
committer | Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-11-26 11:46:54 -0500 |
commit | 76da314df603a08ebc463853030752251b260ab8 (patch) | |
tree | 81517c610e96d690189809204ca51e7913e56a58 | |
parent | 3b34d8214dce9bfeef9049de3fe1e8bfbbbb2709 (diff) |
clk: tegra124: Add support for Tegra124 clocks
Implement clock support for Tegra124.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
-rw-r--r-- | Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt | 59 | ||||
-rw-r--r-- | drivers/clk/tegra/Makefile | 1 | ||||
-rw-r--r-- | drivers/clk/tegra/clk-tegra124.c | 1370 | ||||
-rw-r--r-- | include/dt-bindings/clock/tegra124-car.h | 341 |
4 files changed, 1771 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt new file mode 100644 index 000000000000..1a91ec60dee5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt | |||
@@ -0,0 +1,59 @@ | |||
1 | NVIDIA Tegra124 Clock And Reset Controller | ||
2 | |||
3 | This binding uses the common clock binding: | ||
4 | Documentation/devicetree/bindings/clock/clock-bindings.txt | ||
5 | |||
6 | The CAR (Clock And Reset) Controller on Tegra is the HW module responsible | ||
7 | for muxing and gating Tegra's clocks, and setting their rates. | ||
8 | |||
9 | Required properties : | ||
10 | - compatible : Should be "nvidia,tegra124-car" | ||
11 | - reg : Should contain CAR registers location and length | ||
12 | - clocks : Should contain phandle and clock specifiers for two clocks: | ||
13 | the 32 KHz "32k_in", and the board-specific oscillator "osc". | ||
14 | - #clock-cells : Should be 1. | ||
15 | In clock consumers, this cell represents the clock ID exposed by the | ||
16 | CAR. The assignments may be found in header file | ||
17 | <dt-bindings/clock/tegra124-car.h>. | ||
18 | |||
19 | Example SoC include file: | ||
20 | |||
21 | / { | ||
22 | tegra_car: clock { | ||
23 | compatible = "nvidia,tegra124-car"; | ||
24 | reg = <0x60006000 0x1000>; | ||
25 | #clock-cells = <1>; | ||
26 | }; | ||
27 | |||
28 | usb@c5004000 { | ||
29 | clocks = <&tegra_car TEGRA124_CLK_USB2>; | ||
30 | }; | ||
31 | }; | ||
32 | |||
33 | Example board file: | ||
34 | |||
35 | / { | ||
36 | clocks { | ||
37 | compatible = "simple-bus"; | ||
38 | #address-cells = <1>; | ||
39 | #size-cells = <0>; | ||
40 | |||
41 | osc: clock@0 { | ||
42 | compatible = "fixed-clock"; | ||
43 | reg = <0>; | ||
44 | #clock-cells = <0>; | ||
45 | clock-frequency = <112400000>; | ||
46 | }; | ||
47 | |||
48 | clk_32k: clock@1 { | ||
49 | compatible = "fixed-clock"; | ||
50 | reg = <1>; | ||
51 | #clock-cells = <0>; | ||
52 | clock-frequency = <32768>; | ||
53 | }; | ||
54 | }; | ||
55 | |||
56 | &tegra_car { | ||
57 | clocks = <&clk_32k> <&osc>; | ||
58 | }; | ||
59 | }; | ||
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile index 2d837411dfed..f7dfb72884a4 100644 --- a/drivers/clk/tegra/Makefile +++ b/drivers/clk/tegra/Makefile | |||
@@ -14,3 +14,4 @@ obj-y += clk-tegra-super-gen4.o | |||
14 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o | 14 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o |
15 | obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o | 15 | obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o |
16 | obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o | 16 | obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o |
17 | obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o | ||
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c new file mode 100644 index 000000000000..f69367a14777 --- /dev/null +++ b/drivers/clk/tegra/clk-tegra124.c | |||
@@ -0,0 +1,1370 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include <linux/io.h> | ||
18 | #include <linux/clk.h> | ||
19 | #include <linux/clk-provider.h> | ||
20 | #include <linux/clkdev.h> | ||
21 | #include <linux/of.h> | ||
22 | #include <linux/of_address.h> | ||
23 | #include <linux/delay.h> | ||
24 | #include <linux/export.h> | ||
25 | #include <linux/clk/tegra.h> | ||
26 | #include <dt-bindings/clock/tegra124-car.h> | ||
27 | |||
28 | #include "clk.h" | ||
29 | #include "clk-id.h" | ||
30 | |||
31 | #define CLK_SOURCE_EMC 0x19c | ||
32 | #define CLK_SOURCE_XUSB_SS_SRC 0x610 | ||
33 | |||
34 | #define PLLC_BASE 0x80 | ||
35 | #define PLLC_OUT 0x84 | ||
36 | #define PLLC_MISC2 0x88 | ||
37 | #define PLLC_MISC 0x8c | ||
38 | #define PLLC2_BASE 0x4e8 | ||
39 | #define PLLC2_MISC 0x4ec | ||
40 | #define PLLC3_BASE 0x4fc | ||
41 | #define PLLC3_MISC 0x500 | ||
42 | #define PLLM_BASE 0x90 | ||
43 | #define PLLM_OUT 0x94 | ||
44 | #define PLLM_MISC 0x9c | ||
45 | #define PLLP_BASE 0xa0 | ||
46 | #define PLLP_MISC 0xac | ||
47 | #define PLLA_BASE 0xb0 | ||
48 | #define PLLA_MISC 0xbc | ||
49 | #define PLLD_BASE 0xd0 | ||
50 | #define PLLD_MISC 0xdc | ||
51 | #define PLLU_BASE 0xc0 | ||
52 | #define PLLU_MISC 0xcc | ||
53 | #define PLLX_BASE 0xe0 | ||
54 | #define PLLX_MISC 0xe4 | ||
55 | #define PLLX_MISC2 0x514 | ||
56 | #define PLLX_MISC3 0x518 | ||
57 | #define PLLE_BASE 0xe8 | ||
58 | #define PLLE_MISC 0xec | ||
59 | #define PLLD2_BASE 0x4b8 | ||
60 | #define PLLD2_MISC 0x4bc | ||
61 | #define PLLE_AUX 0x48c | ||
62 | #define PLLRE_BASE 0x4c4 | ||
63 | #define PLLRE_MISC 0x4c8 | ||
64 | #define PLLDP_BASE 0x590 | ||
65 | #define PLLDP_MISC 0x594 | ||
66 | #define PLLC4_BASE 0x5a4 | ||
67 | #define PLLC4_MISC 0x5a8 | ||
68 | |||
69 | #define PLLC_IDDQ_BIT 26 | ||
70 | #define PLLRE_IDDQ_BIT 16 | ||
71 | #define PLLSS_IDDQ_BIT 19 | ||
72 | |||
73 | #define PLL_BASE_LOCK BIT(27) | ||
74 | #define PLLE_MISC_LOCK BIT(11) | ||
75 | #define PLLRE_MISC_LOCK BIT(24) | ||
76 | |||
77 | #define PLL_MISC_LOCK_ENABLE 18 | ||
78 | #define PLLC_MISC_LOCK_ENABLE 24 | ||
79 | #define PLLDU_MISC_LOCK_ENABLE 22 | ||
80 | #define PLLE_MISC_LOCK_ENABLE 9 | ||
81 | #define PLLRE_MISC_LOCK_ENABLE 30 | ||
82 | #define PLLSS_MISC_LOCK_ENABLE 30 | ||
83 | |||
84 | #define PLLXC_SW_MAX_P 6 | ||
85 | |||
86 | #define PMC_PLLM_WB0_OVERRIDE 0x1dc | ||
87 | #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0 | ||
88 | |||
89 | #define UTMIP_PLL_CFG2 0x488 | ||
90 | #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6) | ||
91 | #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) | ||
92 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0) | ||
93 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2) | ||
94 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4) | ||
95 | |||
96 | #define UTMIP_PLL_CFG1 0x484 | ||
97 | #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) | ||
98 | #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) | ||
99 | #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17) | ||
100 | #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16) | ||
101 | #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15) | ||
102 | #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14) | ||
103 | #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12) | ||
104 | |||
105 | #define UTMIPLL_HW_PWRDN_CFG0 0x52c | ||
106 | #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25) | ||
107 | #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) | ||
108 | #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6) | ||
109 | #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5) | ||
110 | #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4) | ||
111 | #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2) | ||
112 | #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1) | ||
113 | #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0) | ||
114 | |||
115 | static void __iomem *clk_base; | ||
116 | static void __iomem *pmc_base; | ||
117 | |||
118 | static unsigned long osc_freq; | ||
119 | static unsigned long pll_ref_freq; | ||
120 | |||
121 | static DEFINE_SPINLOCK(pll_d_lock); | ||
122 | static DEFINE_SPINLOCK(pll_d2_lock); | ||
123 | static DEFINE_SPINLOCK(pll_e_lock); | ||
124 | static DEFINE_SPINLOCK(pll_re_lock); | ||
125 | static DEFINE_SPINLOCK(pll_u_lock); | ||
126 | |||
127 | /* possible OSC frequencies in Hz */ | ||
128 | static unsigned long tegra124_input_freq[] = { | ||
129 | [0] = 13000000, | ||
130 | [1] = 16800000, | ||
131 | [4] = 19200000, | ||
132 | [5] = 38400000, | ||
133 | [8] = 12000000, | ||
134 | [9] = 48000000, | ||
135 | [12] = 260000000, | ||
136 | }; | ||
137 | |||
138 | static const char *mux_plld_out0_plld2_out0[] = { | ||
139 | "pll_d_out0", "pll_d2_out0", | ||
140 | }; | ||
141 | #define mux_plld_out0_plld2_out0_idx NULL | ||
142 | |||
143 | static const char *mux_pllmcp_clkm[] = { | ||
144 | "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3", | ||
145 | }; | ||
146 | #define mux_pllmcp_clkm_idx NULL | ||
147 | |||
148 | static struct div_nmp pllxc_nmp = { | ||
149 | .divm_shift = 0, | ||
150 | .divm_width = 8, | ||
151 | .divn_shift = 8, | ||
152 | .divn_width = 8, | ||
153 | .divp_shift = 20, | ||
154 | .divp_width = 4, | ||
155 | }; | ||
156 | |||
157 | static struct pdiv_map pllxc_p[] = { | ||
158 | { .pdiv = 1, .hw_val = 0 }, | ||
159 | { .pdiv = 2, .hw_val = 1 }, | ||
160 | { .pdiv = 3, .hw_val = 2 }, | ||
161 | { .pdiv = 4, .hw_val = 3 }, | ||
162 | { .pdiv = 5, .hw_val = 4 }, | ||
163 | { .pdiv = 6, .hw_val = 5 }, | ||
164 | { .pdiv = 8, .hw_val = 6 }, | ||
165 | { .pdiv = 10, .hw_val = 7 }, | ||
166 | { .pdiv = 12, .hw_val = 8 }, | ||
167 | { .pdiv = 16, .hw_val = 9 }, | ||
168 | { .pdiv = 12, .hw_val = 10 }, | ||
169 | { .pdiv = 16, .hw_val = 11 }, | ||
170 | { .pdiv = 20, .hw_val = 12 }, | ||
171 | { .pdiv = 24, .hw_val = 13 }, | ||
172 | { .pdiv = 32, .hw_val = 14 }, | ||
173 | { .pdiv = 0, .hw_val = 0 }, | ||
174 | }; | ||
175 | |||
176 | static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { | ||
177 | /* 1 GHz */ | ||
178 | {12000000, 1000000000, 83, 0, 1}, /* actual: 996.0 MHz */ | ||
179 | {13000000, 1000000000, 76, 0, 1}, /* actual: 988.0 MHz */ | ||
180 | {16800000, 1000000000, 59, 0, 1}, /* actual: 991.2 MHz */ | ||
181 | {19200000, 1000000000, 52, 0, 1}, /* actual: 998.4 MHz */ | ||
182 | {26000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */ | ||
183 | {0, 0, 0, 0, 0, 0}, | ||
184 | }; | ||
185 | |||
186 | static struct tegra_clk_pll_params pll_x_params = { | ||
187 | .input_min = 12000000, | ||
188 | .input_max = 800000000, | ||
189 | .cf_min = 12000000, | ||
190 | .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ | ||
191 | .vco_min = 700000000, | ||
192 | .vco_max = 3000000000UL, | ||
193 | .base_reg = PLLX_BASE, | ||
194 | .misc_reg = PLLX_MISC, | ||
195 | .lock_mask = PLL_BASE_LOCK, | ||
196 | .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, | ||
197 | .lock_delay = 300, | ||
198 | .iddq_reg = PLLX_MISC3, | ||
199 | .iddq_bit_idx = 3, | ||
200 | .max_p = 6, | ||
201 | .dyn_ramp_reg = PLLX_MISC2, | ||
202 | .stepa_shift = 16, | ||
203 | .stepb_shift = 24, | ||
204 | .pdiv_tohw = pllxc_p, | ||
205 | .div_nmp = &pllxc_nmp, | ||
206 | .freq_table = pll_x_freq_table, | ||
207 | .flags = TEGRA_PLL_USE_LOCK, | ||
208 | }; | ||
209 | |||
210 | static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { | ||
211 | { 12000000, 624000000, 104, 1, 2}, | ||
212 | { 12000000, 600000000, 100, 1, 2}, | ||
213 | { 13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ | ||
214 | { 16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */ | ||
215 | { 19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */ | ||
216 | { 26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */ | ||
217 | { 0, 0, 0, 0, 0, 0 }, | ||
218 | }; | ||
219 | |||
220 | static struct tegra_clk_pll_params pll_c_params = { | ||
221 | .input_min = 12000000, | ||
222 | .input_max = 800000000, | ||
223 | .cf_min = 12000000, | ||
224 | .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ | ||
225 | .vco_min = 600000000, | ||
226 | .vco_max = 1400000000, | ||
227 | .base_reg = PLLC_BASE, | ||
228 | .misc_reg = PLLC_MISC, | ||
229 | .lock_mask = PLL_BASE_LOCK, | ||
230 | .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE, | ||
231 | .lock_delay = 300, | ||
232 | .iddq_reg = PLLC_MISC, | ||
233 | .iddq_bit_idx = PLLC_IDDQ_BIT, | ||
234 | .max_p = PLLXC_SW_MAX_P, | ||
235 | .dyn_ramp_reg = PLLC_MISC2, | ||
236 | .stepa_shift = 17, | ||
237 | .stepb_shift = 9, | ||
238 | .pdiv_tohw = pllxc_p, | ||
239 | .div_nmp = &pllxc_nmp, | ||
240 | .freq_table = pll_c_freq_table, | ||
241 | .flags = TEGRA_PLL_USE_LOCK, | ||
242 | }; | ||
243 | |||
244 | static struct div_nmp pllcx_nmp = { | ||
245 | .divm_shift = 0, | ||
246 | .divm_width = 2, | ||
247 | .divn_shift = 8, | ||
248 | .divn_width = 8, | ||
249 | .divp_shift = 20, | ||
250 | .divp_width = 3, | ||
251 | }; | ||
252 | |||
253 | static struct pdiv_map pllc_p[] = { | ||
254 | { .pdiv = 1, .hw_val = 0 }, | ||
255 | { .pdiv = 2, .hw_val = 1 }, | ||
256 | { .pdiv = 3, .hw_val = 2 }, | ||
257 | { .pdiv = 4, .hw_val = 3 }, | ||
258 | { .pdiv = 6, .hw_val = 4 }, | ||
259 | { .pdiv = 8, .hw_val = 5 }, | ||
260 | { .pdiv = 12, .hw_val = 6 }, | ||
261 | { .pdiv = 16, .hw_val = 7 }, | ||
262 | { .pdiv = 0, .hw_val = 0 }, | ||
263 | }; | ||
264 | |||
265 | static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = { | ||
266 | {12000000, 600000000, 100, 1, 2}, | ||
267 | {13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ | ||
268 | {16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */ | ||
269 | {19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */ | ||
270 | {26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */ | ||
271 | {0, 0, 0, 0, 0, 0}, | ||
272 | }; | ||
273 | |||
274 | static struct tegra_clk_pll_params pll_c2_params = { | ||
275 | .input_min = 12000000, | ||
276 | .input_max = 48000000, | ||
277 | .cf_min = 12000000, | ||
278 | .cf_max = 19200000, | ||
279 | .vco_min = 600000000, | ||
280 | .vco_max = 1200000000, | ||
281 | .base_reg = PLLC2_BASE, | ||
282 | .misc_reg = PLLC2_MISC, | ||
283 | .lock_mask = PLL_BASE_LOCK, | ||
284 | .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, | ||
285 | .lock_delay = 300, | ||
286 | .pdiv_tohw = pllc_p, | ||
287 | .div_nmp = &pllcx_nmp, | ||
288 | .max_p = 7, | ||
289 | .ext_misc_reg[0] = 0x4f0, | ||
290 | .ext_misc_reg[1] = 0x4f4, | ||
291 | .ext_misc_reg[2] = 0x4f8, | ||
292 | .freq_table = pll_cx_freq_table, | ||
293 | .flags = TEGRA_PLL_USE_LOCK, | ||
294 | }; | ||
295 | |||
296 | static struct tegra_clk_pll_params pll_c3_params = { | ||
297 | .input_min = 12000000, | ||
298 | .input_max = 48000000, | ||
299 | .cf_min = 12000000, | ||
300 | .cf_max = 19200000, | ||
301 | .vco_min = 600000000, | ||
302 | .vco_max = 1200000000, | ||
303 | .base_reg = PLLC3_BASE, | ||
304 | .misc_reg = PLLC3_MISC, | ||
305 | .lock_mask = PLL_BASE_LOCK, | ||
306 | .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, | ||
307 | .lock_delay = 300, | ||
308 | .pdiv_tohw = pllc_p, | ||
309 | .div_nmp = &pllcx_nmp, | ||
310 | .max_p = 7, | ||
311 | .ext_misc_reg[0] = 0x504, | ||
312 | .ext_misc_reg[1] = 0x508, | ||
313 | .ext_misc_reg[2] = 0x50c, | ||
314 | .freq_table = pll_cx_freq_table, | ||
315 | .flags = TEGRA_PLL_USE_LOCK, | ||
316 | }; | ||
317 | |||
318 | static struct div_nmp pllss_nmp = { | ||
319 | .divm_shift = 0, | ||
320 | .divm_width = 8, | ||
321 | .divn_shift = 8, | ||
322 | .divn_width = 8, | ||
323 | .divp_shift = 20, | ||
324 | .divp_width = 4, | ||
325 | }; | ||
326 | |||
327 | static struct pdiv_map pll12g_ssd_esd_p[] = { | ||
328 | { .pdiv = 1, .hw_val = 0 }, | ||
329 | { .pdiv = 2, .hw_val = 1 }, | ||
330 | { .pdiv = 3, .hw_val = 2 }, | ||
331 | { .pdiv = 4, .hw_val = 3 }, | ||
332 | { .pdiv = 5, .hw_val = 4 }, | ||
333 | { .pdiv = 6, .hw_val = 5 }, | ||
334 | { .pdiv = 8, .hw_val = 6 }, | ||
335 | { .pdiv = 10, .hw_val = 7 }, | ||
336 | { .pdiv = 12, .hw_val = 8 }, | ||
337 | { .pdiv = 16, .hw_val = 9 }, | ||
338 | { .pdiv = 12, .hw_val = 10 }, | ||
339 | { .pdiv = 16, .hw_val = 11 }, | ||
340 | { .pdiv = 20, .hw_val = 12 }, | ||
341 | { .pdiv = 24, .hw_val = 13 }, | ||
342 | { .pdiv = 32, .hw_val = 14 }, | ||
343 | { .pdiv = 0, .hw_val = 0 }, | ||
344 | }; | ||
345 | |||
346 | static struct tegra_clk_pll_freq_table pll_c4_freq_table[] = { | ||
347 | { 12000000, 600000000, 100, 1, 1}, | ||
348 | { 13000000, 600000000, 92, 1, 1}, /* actual: 598.0 MHz */ | ||
349 | { 16800000, 600000000, 71, 1, 1}, /* actual: 596.4 MHz */ | ||
350 | { 19200000, 600000000, 62, 1, 1}, /* actual: 595.2 MHz */ | ||
351 | { 26000000, 600000000, 92, 2, 1}, /* actual: 598.0 MHz */ | ||
352 | { 0, 0, 0, 0, 0, 0 }, | ||
353 | }; | ||
354 | |||
355 | static struct tegra_clk_pll_params pll_c4_params = { | ||
356 | .input_min = 12000000, | ||
357 | .input_max = 1000000000, | ||
358 | .cf_min = 12000000, | ||
359 | .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */ | ||
360 | .vco_min = 600000000, | ||
361 | .vco_max = 1200000000, | ||
362 | .base_reg = PLLC4_BASE, | ||
363 | .misc_reg = PLLC4_MISC, | ||
364 | .lock_mask = PLL_BASE_LOCK, | ||
365 | .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE, | ||
366 | .lock_delay = 300, | ||
367 | .iddq_reg = PLLC4_BASE, | ||
368 | .iddq_bit_idx = PLLSS_IDDQ_BIT, | ||
369 | .pdiv_tohw = pll12g_ssd_esd_p, | ||
370 | .div_nmp = &pllss_nmp, | ||
371 | .ext_misc_reg[0] = 0x5ac, | ||
372 | .ext_misc_reg[1] = 0x5b0, | ||
373 | .ext_misc_reg[2] = 0x5b4, | ||
374 | .freq_table = pll_c4_freq_table, | ||
375 | }; | ||
376 | |||
377 | static struct pdiv_map pllm_p[] = { | ||
378 | { .pdiv = 1, .hw_val = 0 }, | ||
379 | { .pdiv = 2, .hw_val = 1 }, | ||
380 | { .pdiv = 0, .hw_val = 0 }, | ||
381 | }; | ||
382 | |||
383 | static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { | ||
384 | {12000000, 800000000, 66, 1, 1}, /* actual: 792.0 MHz */ | ||
385 | {13000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */ | ||
386 | {16800000, 800000000, 47, 1, 1}, /* actual: 789.6 MHz */ | ||
387 | {19200000, 800000000, 41, 1, 1}, /* actual: 787.2 MHz */ | ||
388 | {26000000, 800000000, 61, 2, 1}, /* actual: 793.0 MHz */ | ||
389 | {0, 0, 0, 0, 0, 0}, | ||
390 | }; | ||
391 | |||
392 | static struct div_nmp pllm_nmp = { | ||
393 | .divm_shift = 0, | ||
394 | .divm_width = 8, | ||
395 | .override_divm_shift = 0, | ||
396 | .divn_shift = 8, | ||
397 | .divn_width = 8, | ||
398 | .override_divn_shift = 8, | ||
399 | .divp_shift = 20, | ||
400 | .divp_width = 1, | ||
401 | .override_divp_shift = 27, | ||
402 | }; | ||
403 | |||
404 | static struct tegra_clk_pll_params pll_m_params = { | ||
405 | .input_min = 12000000, | ||
406 | .input_max = 500000000, | ||
407 | .cf_min = 12000000, | ||
408 | .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ | ||
409 | .vco_min = 400000000, | ||
410 | .vco_max = 1066000000, | ||
411 | .base_reg = PLLM_BASE, | ||
412 | .misc_reg = PLLM_MISC, | ||
413 | .lock_mask = PLL_BASE_LOCK, | ||
414 | .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, | ||
415 | .lock_delay = 300, | ||
416 | .max_p = 2, | ||
417 | .pdiv_tohw = pllm_p, | ||
418 | .div_nmp = &pllm_nmp, | ||
419 | .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, | ||
420 | .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2, | ||
421 | .freq_table = pll_m_freq_table, | ||
422 | .flags = TEGRA_PLL_USE_LOCK, | ||
423 | }; | ||
424 | |||
425 | static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { | ||
426 | /* PLLE special case: use cpcon field to store cml divider value */ | ||
427 | {336000000, 100000000, 100, 21, 16, 11}, | ||
428 | {312000000, 100000000, 200, 26, 24, 13}, | ||
429 | {13000000, 100000000, 200, 1, 26, 13}, | ||
430 | {12000000, 100000000, 200, 1, 24, 13}, | ||
431 | {0, 0, 0, 0, 0, 0}, | ||
432 | }; | ||
433 | |||
434 | static struct div_nmp plle_nmp = { | ||
435 | .divm_shift = 0, | ||
436 | .divm_width = 8, | ||
437 | .divn_shift = 8, | ||
438 | .divn_width = 8, | ||
439 | .divp_shift = 24, | ||
440 | .divp_width = 4, | ||
441 | }; | ||
442 | |||
443 | static struct tegra_clk_pll_params pll_e_params = { | ||
444 | .input_min = 12000000, | ||
445 | .input_max = 1000000000, | ||
446 | .cf_min = 12000000, | ||
447 | .cf_max = 75000000, | ||
448 | .vco_min = 1600000000, | ||
449 | .vco_max = 2400000000U, | ||
450 | .base_reg = PLLE_BASE, | ||
451 | .misc_reg = PLLE_MISC, | ||
452 | .aux_reg = PLLE_AUX, | ||
453 | .lock_mask = PLLE_MISC_LOCK, | ||
454 | .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, | ||
455 | .lock_delay = 300, | ||
456 | .div_nmp = &plle_nmp, | ||
457 | .freq_table = pll_e_freq_table, | ||
458 | .flags = TEGRA_PLL_FIXED, | ||
459 | .fixed_rate = 100000000, | ||
460 | }; | ||
461 | |||
462 | static const struct clk_div_table pll_re_div_table[] = { | ||
463 | { .val = 0, .div = 1 }, | ||
464 | { .val = 1, .div = 2 }, | ||
465 | { .val = 2, .div = 3 }, | ||
466 | { .val = 3, .div = 4 }, | ||
467 | { .val = 4, .div = 5 }, | ||
468 | { .val = 5, .div = 6 }, | ||
469 | { .val = 0, .div = 0 }, | ||
470 | }; | ||
471 | |||
472 | static struct div_nmp pllre_nmp = { | ||
473 | .divm_shift = 0, | ||
474 | .divm_width = 8, | ||
475 | .divn_shift = 8, | ||
476 | .divn_width = 8, | ||
477 | .divp_shift = 16, | ||
478 | .divp_width = 4, | ||
479 | }; | ||
480 | |||
481 | static struct tegra_clk_pll_params pll_re_vco_params = { | ||
482 | .input_min = 12000000, | ||
483 | .input_max = 1000000000, | ||
484 | .cf_min = 12000000, | ||
485 | .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */ | ||
486 | .vco_min = 300000000, | ||
487 | .vco_max = 600000000, | ||
488 | .base_reg = PLLRE_BASE, | ||
489 | .misc_reg = PLLRE_MISC, | ||
490 | .lock_mask = PLLRE_MISC_LOCK, | ||
491 | .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE, | ||
492 | .lock_delay = 300, | ||
493 | .iddq_reg = PLLRE_MISC, | ||
494 | .iddq_bit_idx = PLLRE_IDDQ_BIT, | ||
495 | .div_nmp = &pllre_nmp, | ||
496 | .flags = TEGRA_PLL_USE_LOCK, | ||
497 | }; | ||
498 | |||
499 | static struct div_nmp pllp_nmp = { | ||
500 | .divm_shift = 0, | ||
501 | .divm_width = 5, | ||
502 | .divn_shift = 8, | ||
503 | .divn_width = 10, | ||
504 | .divp_shift = 20, | ||
505 | .divp_width = 3, | ||
506 | }; | ||
507 | |||
508 | static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { | ||
509 | {12000000, 216000000, 432, 12, 1, 8}, | ||
510 | {13000000, 216000000, 432, 13, 1, 8}, | ||
511 | {16800000, 216000000, 360, 14, 1, 8}, | ||
512 | {19200000, 216000000, 360, 16, 1, 8}, | ||
513 | {26000000, 216000000, 432, 26, 1, 8}, | ||
514 | {0, 0, 0, 0, 0, 0}, | ||
515 | }; | ||
516 | |||
517 | static struct tegra_clk_pll_params pll_p_params = { | ||
518 | .input_min = 2000000, | ||
519 | .input_max = 31000000, | ||
520 | .cf_min = 1000000, | ||
521 | .cf_max = 6000000, | ||
522 | .vco_min = 200000000, | ||
523 | .vco_max = 700000000, | ||
524 | .base_reg = PLLP_BASE, | ||
525 | .misc_reg = PLLP_MISC, | ||
526 | .lock_mask = PLL_BASE_LOCK, | ||
527 | .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, | ||
528 | .lock_delay = 300, | ||
529 | .div_nmp = &pllp_nmp, | ||
530 | .freq_table = pll_p_freq_table, | ||
531 | .fixed_rate = 408000000, | ||
532 | .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK, | ||
533 | }; | ||
534 | |||
535 | static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { | ||
536 | {9600000, 282240000, 147, 5, 0, 4}, | ||
537 | {9600000, 368640000, 192, 5, 0, 4}, | ||
538 | {9600000, 240000000, 200, 8, 0, 8}, | ||
539 | |||
540 | {28800000, 282240000, 245, 25, 0, 8}, | ||
541 | {28800000, 368640000, 320, 25, 0, 8}, | ||
542 | {28800000, 240000000, 200, 24, 0, 8}, | ||
543 | {0, 0, 0, 0, 0, 0}, | ||
544 | }; | ||
545 | |||
546 | static struct tegra_clk_pll_params pll_a_params = { | ||
547 | .input_min = 2000000, | ||
548 | .input_max = 31000000, | ||
549 | .cf_min = 1000000, | ||
550 | .cf_max = 6000000, | ||
551 | .vco_min = 200000000, | ||
552 | .vco_max = 700000000, | ||
553 | .base_reg = PLLA_BASE, | ||
554 | .misc_reg = PLLA_MISC, | ||
555 | .lock_mask = PLL_BASE_LOCK, | ||
556 | .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, | ||
557 | .lock_delay = 300, | ||
558 | .div_nmp = &pllp_nmp, | ||
559 | .freq_table = pll_a_freq_table, | ||
560 | .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK, | ||
561 | }; | ||
562 | |||
563 | static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { | ||
564 | {12000000, 216000000, 864, 12, 4, 12}, | ||
565 | {13000000, 216000000, 864, 13, 4, 12}, | ||
566 | {16800000, 216000000, 720, 14, 4, 12}, | ||
567 | {19200000, 216000000, 720, 16, 4, 12}, | ||
568 | {26000000, 216000000, 864, 26, 4, 12}, | ||
569 | |||
570 | {12000000, 594000000, 594, 12, 1, 12}, | ||
571 | {13000000, 594000000, 594, 13, 1, 12}, | ||
572 | {16800000, 594000000, 495, 14, 1, 12}, | ||
573 | {19200000, 594000000, 495, 16, 1, 12}, | ||
574 | {26000000, 594000000, 594, 26, 1, 12}, | ||
575 | |||
576 | {12000000, 1000000000, 1000, 12, 1, 12}, | ||
577 | {13000000, 1000000000, 1000, 13, 1, 12}, | ||
578 | {19200000, 1000000000, 625, 12, 1, 12}, | ||
579 | {26000000, 1000000000, 1000, 26, 1, 12}, | ||
580 | |||
581 | {0, 0, 0, 0, 0, 0}, | ||
582 | }; | ||
583 | |||
584 | static struct tegra_clk_pll_params pll_d_params = { | ||
585 | .input_min = 2000000, | ||
586 | .input_max = 40000000, | ||
587 | .cf_min = 1000000, | ||
588 | .cf_max = 6000000, | ||
589 | .vco_min = 500000000, | ||
590 | .vco_max = 1000000000, | ||
591 | .base_reg = PLLD_BASE, | ||
592 | .misc_reg = PLLD_MISC, | ||
593 | .lock_mask = PLL_BASE_LOCK, | ||
594 | .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, | ||
595 | .lock_delay = 1000, | ||
596 | .div_nmp = &pllp_nmp, | ||
597 | .freq_table = pll_d_freq_table, | ||
598 | .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | | ||
599 | TEGRA_PLL_USE_LOCK, | ||
600 | }; | ||
601 | |||
602 | static struct tegra_clk_pll_freq_table tegra124_pll_d2_freq_table[] = { | ||
603 | { 12000000, 148500000, 99, 1, 8}, | ||
604 | { 12000000, 594000000, 99, 1, 1}, | ||
605 | { 13000000, 594000000, 91, 1, 1}, /* actual: 591.5 MHz */ | ||
606 | { 16800000, 594000000, 71, 1, 1}, /* actual: 596.4 MHz */ | ||
607 | { 19200000, 594000000, 62, 1, 1}, /* actual: 595.2 MHz */ | ||
608 | { 26000000, 594000000, 91, 2, 1}, /* actual: 591.5 MHz */ | ||
609 | { 0, 0, 0, 0, 0, 0 }, | ||
610 | }; | ||
611 | |||
612 | static struct tegra_clk_pll_params tegra124_pll_d2_params = { | ||
613 | .input_min = 12000000, | ||
614 | .input_max = 1000000000, | ||
615 | .cf_min = 12000000, | ||
616 | .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */ | ||
617 | .vco_min = 600000000, | ||
618 | .vco_max = 1200000000, | ||
619 | .base_reg = PLLD2_BASE, | ||
620 | .misc_reg = PLLD2_MISC, | ||
621 | .lock_mask = PLL_BASE_LOCK, | ||
622 | .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE, | ||
623 | .lock_delay = 300, | ||
624 | .iddq_reg = PLLD2_BASE, | ||
625 | .iddq_bit_idx = PLLSS_IDDQ_BIT, | ||
626 | .pdiv_tohw = pll12g_ssd_esd_p, | ||
627 | .div_nmp = &pllss_nmp, | ||
628 | .ext_misc_reg[0] = 0x570, | ||
629 | .ext_misc_reg[1] = 0x574, | ||
630 | .ext_misc_reg[2] = 0x578, | ||
631 | .max_p = 15, | ||
632 | .freq_table = tegra124_pll_d2_freq_table, | ||
633 | }; | ||
634 | |||
635 | static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = { | ||
636 | { 12000000, 600000000, 100, 1, 1}, | ||
637 | { 13000000, 600000000, 92, 1, 1}, /* actual: 598.0 MHz */ | ||
638 | { 16800000, 600000000, 71, 1, 1}, /* actual: 596.4 MHz */ | ||
639 | { 19200000, 600000000, 62, 1, 1}, /* actual: 595.2 MHz */ | ||
640 | { 26000000, 600000000, 92, 2, 1}, /* actual: 598.0 MHz */ | ||
641 | { 0, 0, 0, 0, 0, 0 }, | ||
642 | }; | ||
643 | |||
644 | static struct tegra_clk_pll_params pll_dp_params = { | ||
645 | .input_min = 12000000, | ||
646 | .input_max = 1000000000, | ||
647 | .cf_min = 12000000, | ||
648 | .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */ | ||
649 | .vco_min = 600000000, | ||
650 | .vco_max = 1200000000, | ||
651 | .base_reg = PLLDP_BASE, | ||
652 | .misc_reg = PLLDP_MISC, | ||
653 | .lock_mask = PLL_BASE_LOCK, | ||
654 | .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE, | ||
655 | .lock_delay = 300, | ||
656 | .iddq_reg = PLLDP_BASE, | ||
657 | .iddq_bit_idx = PLLSS_IDDQ_BIT, | ||
658 | .pdiv_tohw = pll12g_ssd_esd_p, | ||
659 | .div_nmp = &pllss_nmp, | ||
660 | .ext_misc_reg[0] = 0x598, | ||
661 | .ext_misc_reg[1] = 0x59c, | ||
662 | .ext_misc_reg[2] = 0x5a0, | ||
663 | .max_p = 5, | ||
664 | .freq_table = pll_dp_freq_table, | ||
665 | }; | ||
666 | |||
667 | static struct pdiv_map pllu_p[] = { | ||
668 | { .pdiv = 1, .hw_val = 1 }, | ||
669 | { .pdiv = 2, .hw_val = 0 }, | ||
670 | { .pdiv = 0, .hw_val = 0 }, | ||
671 | }; | ||
672 | |||
673 | static struct div_nmp pllu_nmp = { | ||
674 | .divm_shift = 0, | ||
675 | .divm_width = 5, | ||
676 | .divn_shift = 8, | ||
677 | .divn_width = 10, | ||
678 | .divp_shift = 20, | ||
679 | .divp_width = 1, | ||
680 | }; | ||
681 | |||
682 | static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { | ||
683 | {12000000, 480000000, 960, 12, 2, 12}, | ||
684 | {13000000, 480000000, 960, 13, 2, 12}, | ||
685 | {16800000, 480000000, 400, 7, 2, 5}, | ||
686 | {19200000, 480000000, 200, 4, 2, 3}, | ||
687 | {26000000, 480000000, 960, 26, 2, 12}, | ||
688 | {0, 0, 0, 0, 0, 0}, | ||
689 | }; | ||
690 | |||
691 | static struct tegra_clk_pll_params pll_u_params = { | ||
692 | .input_min = 2000000, | ||
693 | .input_max = 40000000, | ||
694 | .cf_min = 1000000, | ||
695 | .cf_max = 6000000, | ||
696 | .vco_min = 480000000, | ||
697 | .vco_max = 960000000, | ||
698 | .base_reg = PLLU_BASE, | ||
699 | .misc_reg = PLLU_MISC, | ||
700 | .lock_mask = PLL_BASE_LOCK, | ||
701 | .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, | ||
702 | .lock_delay = 1000, | ||
703 | .pdiv_tohw = pllu_p, | ||
704 | .div_nmp = &pllu_nmp, | ||
705 | .freq_table = pll_u_freq_table, | ||
706 | .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | | ||
707 | TEGRA_PLL_USE_LOCK, | ||
708 | }; | ||
709 | |||
710 | struct utmi_clk_param { | ||
711 | /* Oscillator Frequency in KHz */ | ||
712 | u32 osc_frequency; | ||
713 | /* UTMIP PLL Enable Delay Count */ | ||
714 | u8 enable_delay_count; | ||
715 | /* UTMIP PLL Stable count */ | ||
716 | u8 stable_count; | ||
717 | /* UTMIP PLL Active delay count */ | ||
718 | u8 active_delay_count; | ||
719 | /* UTMIP PLL Xtal frequency count */ | ||
720 | u8 xtal_freq_count; | ||
721 | }; | ||
722 | |||
723 | static const struct utmi_clk_param utmi_parameters[] = { | ||
724 | {.osc_frequency = 13000000, .enable_delay_count = 0x02, | ||
725 | .stable_count = 0x33, .active_delay_count = 0x05, | ||
726 | .xtal_freq_count = 0x7F}, | ||
727 | {.osc_frequency = 19200000, .enable_delay_count = 0x03, | ||
728 | .stable_count = 0x4B, .active_delay_count = 0x06, | ||
729 | .xtal_freq_count = 0xBB}, | ||
730 | {.osc_frequency = 12000000, .enable_delay_count = 0x02, | ||
731 | .stable_count = 0x2F, .active_delay_count = 0x04, | ||
732 | .xtal_freq_count = 0x76}, | ||
733 | {.osc_frequency = 26000000, .enable_delay_count = 0x04, | ||
734 | .stable_count = 0x66, .active_delay_count = 0x09, | ||
735 | .xtal_freq_count = 0xFE}, | ||
736 | {.osc_frequency = 16800000, .enable_delay_count = 0x03, | ||
737 | .stable_count = 0x41, .active_delay_count = 0x0A, | ||
738 | .xtal_freq_count = 0xA4}, | ||
739 | }; | ||
740 | |||
741 | static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = { | ||
742 | [tegra_clk_ispb] = { .dt_id = TEGRA124_CLK_ISPB, .present = true }, | ||
743 | [tegra_clk_rtc] = { .dt_id = TEGRA124_CLK_RTC, .present = true }, | ||
744 | [tegra_clk_timer] = { .dt_id = TEGRA124_CLK_TIMER, .present = true }, | ||
745 | [tegra_clk_uarta] = { .dt_id = TEGRA124_CLK_UARTA, .present = true }, | ||
746 | [tegra_clk_sdmmc2] = { .dt_id = TEGRA124_CLK_SDMMC2, .present = true }, | ||
747 | [tegra_clk_i2s1] = { .dt_id = TEGRA124_CLK_I2S1, .present = true }, | ||
748 | [tegra_clk_i2c1] = { .dt_id = TEGRA124_CLK_I2C1, .present = true }, | ||
749 | [tegra_clk_ndflash] = { .dt_id = TEGRA124_CLK_NDFLASH, .present = true }, | ||
750 | [tegra_clk_sdmmc1] = { .dt_id = TEGRA124_CLK_SDMMC1, .present = true }, | ||
751 | [tegra_clk_sdmmc4] = { .dt_id = TEGRA124_CLK_SDMMC4, .present = true }, | ||
752 | [tegra_clk_pwm] = { .dt_id = TEGRA124_CLK_PWM, .present = true }, | ||
753 | [tegra_clk_i2s2] = { .dt_id = TEGRA124_CLK_I2S2, .present = true }, | ||
754 | [tegra_clk_gr2d] = { .dt_id = TEGRA124_CLK_GR_2D, .present = true }, | ||
755 | [tegra_clk_usbd] = { .dt_id = TEGRA124_CLK_USBD, .present = true }, | ||
756 | [tegra_clk_isp_8] = { .dt_id = TEGRA124_CLK_ISP, .present = true }, | ||
757 | [tegra_clk_gr3d] = { .dt_id = TEGRA124_CLK_GR_3D, .present = true }, | ||
758 | [tegra_clk_disp2] = { .dt_id = TEGRA124_CLK_DISP2, .present = true }, | ||
759 | [tegra_clk_disp1] = { .dt_id = TEGRA124_CLK_DISP1, .present = true }, | ||
760 | [tegra_clk_host1x] = { .dt_id = TEGRA124_CLK_HOST1X, .present = true }, | ||
761 | [tegra_clk_vcp] = { .dt_id = TEGRA124_CLK_VCP, .present = true }, | ||
762 | [tegra_clk_i2s0] = { .dt_id = TEGRA124_CLK_I2S0, .present = true }, | ||
763 | [tegra_clk_apbdma] = { .dt_id = TEGRA124_CLK_APBDMA, .present = true }, | ||
764 | [tegra_clk_kbc] = { .dt_id = TEGRA124_CLK_KBC, .present = true }, | ||
765 | [tegra_clk_kfuse] = { .dt_id = TEGRA124_CLK_KFUSE, .present = true }, | ||
766 | [tegra_clk_sbc1] = { .dt_id = TEGRA124_CLK_SBC1, .present = true }, | ||
767 | [tegra_clk_nor] = { .dt_id = TEGRA124_CLK_NOR, .present = true }, | ||
768 | [tegra_clk_sbc2] = { .dt_id = TEGRA124_CLK_SBC2, .present = true }, | ||
769 | [tegra_clk_sbc3] = { .dt_id = TEGRA124_CLK_SBC3, .present = true }, | ||
770 | [tegra_clk_i2c5] = { .dt_id = TEGRA124_CLK_I2C5, .present = true }, | ||
771 | [tegra_clk_dsia] = { .dt_id = TEGRA124_CLK_DSIA, .present = true }, | ||
772 | [tegra_clk_mipi] = { .dt_id = TEGRA124_CLK_MIPI, .present = true }, | ||
773 | [tegra_clk_hdmi] = { .dt_id = TEGRA124_CLK_HDMI, .present = true }, | ||
774 | [tegra_clk_csi] = { .dt_id = TEGRA124_CLK_CSI, .present = true }, | ||
775 | [tegra_clk_i2c2] = { .dt_id = TEGRA124_CLK_I2C2, .present = true }, | ||
776 | [tegra_clk_uartc] = { .dt_id = TEGRA124_CLK_UARTC, .present = true }, | ||
777 | [tegra_clk_mipi_cal] = { .dt_id = TEGRA124_CLK_MIPI_CAL, .present = true }, | ||
778 | [tegra_clk_emc] = { .dt_id = TEGRA124_CLK_EMC, .present = true }, | ||
779 | [tegra_clk_usb2] = { .dt_id = TEGRA124_CLK_USB2, .present = true }, | ||
780 | [tegra_clk_usb3] = { .dt_id = TEGRA124_CLK_USB3, .present = true }, | ||
781 | [tegra_clk_vde_8] = { .dt_id = TEGRA124_CLK_VDE, .present = true }, | ||
782 | [tegra_clk_bsea] = { .dt_id = TEGRA124_CLK_BSEA, .present = true }, | ||
783 | [tegra_clk_bsev] = { .dt_id = TEGRA124_CLK_BSEV, .present = true }, | ||
784 | [tegra_clk_uartd] = { .dt_id = TEGRA124_CLK_UARTD, .present = true }, | ||
785 | [tegra_clk_i2c3] = { .dt_id = TEGRA124_CLK_I2C3, .present = true }, | ||
786 | [tegra_clk_sbc4] = { .dt_id = TEGRA124_CLK_SBC4, .present = true }, | ||
787 | [tegra_clk_sdmmc3] = { .dt_id = TEGRA124_CLK_SDMMC3, .present = true }, | ||
788 | [tegra_clk_pcie] = { .dt_id = TEGRA124_CLK_PCIE, .present = true }, | ||
789 | [tegra_clk_owr] = { .dt_id = TEGRA124_CLK_OWR, .present = true }, | ||
790 | [tegra_clk_afi] = { .dt_id = TEGRA124_CLK_AFI, .present = true }, | ||
791 | [tegra_clk_csite] = { .dt_id = TEGRA124_CLK_CSITE, .present = true }, | ||
792 | [tegra_clk_la] = { .dt_id = TEGRA124_CLK_LA, .present = true }, | ||
793 | [tegra_clk_trace] = { .dt_id = TEGRA124_CLK_TRACE, .present = true }, | ||
794 | [tegra_clk_soc_therm] = { .dt_id = TEGRA124_CLK_SOC_THERM, .present = true }, | ||
795 | [tegra_clk_dtv] = { .dt_id = TEGRA124_CLK_DTV, .present = true }, | ||
796 | [tegra_clk_ndspeed] = { .dt_id = TEGRA124_CLK_NDSPEED, .present = true }, | ||
797 | [tegra_clk_i2cslow] = { .dt_id = TEGRA124_CLK_I2CSLOW, .present = true }, | ||
798 | [tegra_clk_dsib] = { .dt_id = TEGRA124_CLK_DSIB, .present = true }, | ||
799 | [tegra_clk_tsec] = { .dt_id = TEGRA124_CLK_TSEC, .present = true }, | ||
800 | [tegra_clk_xusb_host] = { .dt_id = TEGRA124_CLK_XUSB_HOST, .present = true }, | ||
801 | [tegra_clk_msenc] = { .dt_id = TEGRA124_CLK_MSENC, .present = true }, | ||
802 | [tegra_clk_csus] = { .dt_id = TEGRA124_CLK_CSUS, .present = true }, | ||
803 | [tegra_clk_mselect] = { .dt_id = TEGRA124_CLK_MSELECT, .present = true }, | ||
804 | [tegra_clk_tsensor] = { .dt_id = TEGRA124_CLK_TSENSOR, .present = true }, | ||
805 | [tegra_clk_i2s3] = { .dt_id = TEGRA124_CLK_I2S3, .present = true }, | ||
806 | [tegra_clk_i2s4] = { .dt_id = TEGRA124_CLK_I2S4, .present = true }, | ||
807 | [tegra_clk_i2c4] = { .dt_id = TEGRA124_CLK_I2C4, .present = true }, | ||
808 | [tegra_clk_sbc5] = { .dt_id = TEGRA124_CLK_SBC5, .present = true }, | ||
809 | [tegra_clk_sbc6] = { .dt_id = TEGRA124_CLK_SBC6, .present = true }, | ||
810 | [tegra_clk_d_audio] = { .dt_id = TEGRA124_CLK_D_AUDIO, .present = true }, | ||
811 | [tegra_clk_apbif] = { .dt_id = TEGRA124_CLK_APBIF, .present = true }, | ||
812 | [tegra_clk_dam0] = { .dt_id = TEGRA124_CLK_DAM0, .present = true }, | ||
813 | [tegra_clk_dam1] = { .dt_id = TEGRA124_CLK_DAM1, .present = true }, | ||
814 | [tegra_clk_dam2] = { .dt_id = TEGRA124_CLK_DAM2, .present = true }, | ||
815 | [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA124_CLK_HDA2CODEC_2X, .present = true }, | ||
816 | [tegra_clk_audio0_2x] = { .dt_id = TEGRA124_CLK_AUDIO0_2X, .present = true }, | ||
817 | [tegra_clk_audio1_2x] = { .dt_id = TEGRA124_CLK_AUDIO1_2X, .present = true }, | ||
818 | [tegra_clk_audio2_2x] = { .dt_id = TEGRA124_CLK_AUDIO2_2X, .present = true }, | ||
819 | [tegra_clk_audio3_2x] = { .dt_id = TEGRA124_CLK_AUDIO3_2X, .present = true }, | ||
820 | [tegra_clk_audio4_2x] = { .dt_id = TEGRA124_CLK_AUDIO4_2X, .present = true }, | ||
821 | [tegra_clk_spdif_2x] = { .dt_id = TEGRA124_CLK_SPDIF_2X, .present = true }, | ||
822 | [tegra_clk_actmon] = { .dt_id = TEGRA124_CLK_ACTMON, .present = true }, | ||
823 | [tegra_clk_extern1] = { .dt_id = TEGRA124_CLK_EXTERN1, .present = true }, | ||
824 | [tegra_clk_extern2] = { .dt_id = TEGRA124_CLK_EXTERN2, .present = true }, | ||
825 | [tegra_clk_extern3] = { .dt_id = TEGRA124_CLK_EXTERN3, .present = true }, | ||
826 | [tegra_clk_sata_oob] = { .dt_id = TEGRA124_CLK_SATA_OOB, .present = true }, | ||
827 | [tegra_clk_sata] = { .dt_id = TEGRA124_CLK_SATA, .present = true }, | ||
828 | [tegra_clk_hda] = { .dt_id = TEGRA124_CLK_HDA, .present = true }, | ||
829 | [tegra_clk_se] = { .dt_id = TEGRA124_CLK_SE, .present = true }, | ||
830 | [tegra_clk_hda2hdmi] = { .dt_id = TEGRA124_CLK_HDA2HDMI, .present = true }, | ||
831 | [tegra_clk_sata_cold] = { .dt_id = TEGRA124_CLK_SATA_COLD, .present = true }, | ||
832 | [tegra_clk_cilab] = { .dt_id = TEGRA124_CLK_CILAB, .present = true }, | ||
833 | [tegra_clk_cilcd] = { .dt_id = TEGRA124_CLK_CILCD, .present = true }, | ||
834 | [tegra_clk_cile] = { .dt_id = TEGRA124_CLK_CILE, .present = true }, | ||
835 | [tegra_clk_dsialp] = { .dt_id = TEGRA124_CLK_DSIALP, .present = true }, | ||
836 | [tegra_clk_dsiblp] = { .dt_id = TEGRA124_CLK_DSIBLP, .present = true }, | ||
837 | [tegra_clk_entropy] = { .dt_id = TEGRA124_CLK_ENTROPY, .present = true }, | ||
838 | [tegra_clk_dds] = { .dt_id = TEGRA124_CLK_DDS, .present = true }, | ||
839 | [tegra_clk_dp2] = { .dt_id = TEGRA124_CLK_DP2, .present = true }, | ||
840 | [tegra_clk_amx] = { .dt_id = TEGRA124_CLK_AMX, .present = true }, | ||
841 | [tegra_clk_adx] = { .dt_id = TEGRA124_CLK_ADX, .present = true }, | ||
842 | [tegra_clk_xusb_ss] = { .dt_id = TEGRA124_CLK_XUSB_SS, .present = true }, | ||
843 | [tegra_clk_i2c6] = { .dt_id = TEGRA124_CLK_I2C6, .present = true }, | ||
844 | [tegra_clk_vim2_clk] = { .dt_id = TEGRA124_CLK_VIM2_CLK, .present = true }, | ||
845 | [tegra_clk_hdmi_audio] = { .dt_id = TEGRA124_CLK_HDMI_AUDIO, .present = true }, | ||
846 | [tegra_clk_clk72Mhz] = { .dt_id = TEGRA124_CLK_CLK72MHZ, .present = true }, | ||
847 | [tegra_clk_vic03] = { .dt_id = TEGRA124_CLK_VIC03, .present = true }, | ||
848 | [tegra_clk_adx1] = { .dt_id = TEGRA124_CLK_ADX1, .present = true }, | ||
849 | [tegra_clk_dpaux] = { .dt_id = TEGRA124_CLK_DPAUX, .present = true }, | ||
850 | [tegra_clk_sor0] = { .dt_id = TEGRA124_CLK_SOR0, .present = true }, | ||
851 | [tegra_clk_sor0_lvds] = { .dt_id = TEGRA124_CLK_SOR0_LVDS, .present = true }, | ||
852 | [tegra_clk_gpu] = { .dt_id = TEGRA124_CLK_GPU, .present = true }, | ||
853 | [tegra_clk_amx1] = { .dt_id = TEGRA124_CLK_AMX1, .present = true }, | ||
854 | [tegra_clk_uartb] = { .dt_id = TEGRA124_CLK_UARTB, .present = true }, | ||
855 | [tegra_clk_vfir] = { .dt_id = TEGRA124_CLK_VFIR, .present = true }, | ||
856 | [tegra_clk_spdif_in] = { .dt_id = TEGRA124_CLK_SPDIF_IN, .present = true }, | ||
857 | [tegra_clk_spdif_out] = { .dt_id = TEGRA124_CLK_SPDIF_OUT, .present = true }, | ||
858 | [tegra_clk_vi_9] = { .dt_id = TEGRA124_CLK_VI, .present = true }, | ||
859 | [tegra_clk_vi_sensor] = { .dt_id = TEGRA124_CLK_VI_SENSOR, .present = true }, | ||
860 | [tegra_clk_fuse] = { .dt_id = TEGRA124_CLK_FUSE, .present = true }, | ||
861 | [tegra_clk_fuse_burn] = { .dt_id = TEGRA124_CLK_FUSE_BURN, .present = true }, | ||
862 | [tegra_clk_clk_32k] = { .dt_id = TEGRA124_CLK_CLK_32K, .present = true }, | ||
863 | [tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true }, | ||
864 | [tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true }, | ||
865 | [tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true }, | ||
866 | [tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true }, | ||
867 | [tegra_clk_pll_c] = { .dt_id = TEGRA124_CLK_PLL_C, .present = true }, | ||
868 | [tegra_clk_pll_c_out1] = { .dt_id = TEGRA124_CLK_PLL_C_OUT1, .present = true }, | ||
869 | [tegra_clk_pll_c2] = { .dt_id = TEGRA124_CLK_PLL_C2, .present = true }, | ||
870 | [tegra_clk_pll_c3] = { .dt_id = TEGRA124_CLK_PLL_C3, .present = true }, | ||
871 | [tegra_clk_pll_m] = { .dt_id = TEGRA124_CLK_PLL_M, .present = true }, | ||
872 | [tegra_clk_pll_m_out1] = { .dt_id = TEGRA124_CLK_PLL_M_OUT1, .present = true }, | ||
873 | [tegra_clk_pll_p] = { .dt_id = TEGRA124_CLK_PLL_P, .present = true }, | ||
874 | [tegra_clk_pll_p_out1] = { .dt_id = TEGRA124_CLK_PLL_P_OUT1, .present = true }, | ||
875 | [tegra_clk_pll_p_out2] = { .dt_id = TEGRA124_CLK_PLL_P_OUT2, .present = true }, | ||
876 | [tegra_clk_pll_p_out3] = { .dt_id = TEGRA124_CLK_PLL_P_OUT3, .present = true }, | ||
877 | [tegra_clk_pll_p_out4] = { .dt_id = TEGRA124_CLK_PLL_P_OUT4, .present = true }, | ||
878 | [tegra_clk_pll_a] = { .dt_id = TEGRA124_CLK_PLL_A, .present = true }, | ||
879 | [tegra_clk_pll_a_out0] = { .dt_id = TEGRA124_CLK_PLL_A_OUT0, .present = true }, | ||
880 | [tegra_clk_pll_d] = { .dt_id = TEGRA124_CLK_PLL_D, .present = true }, | ||
881 | [tegra_clk_pll_d_out0] = { .dt_id = TEGRA124_CLK_PLL_D_OUT0, .present = true }, | ||
882 | [tegra_clk_pll_d2] = { .dt_id = TEGRA124_CLK_PLL_D2, .present = true }, | ||
883 | [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA124_CLK_PLL_D2_OUT0, .present = true }, | ||
884 | [tegra_clk_pll_u] = { .dt_id = TEGRA124_CLK_PLL_U, .present = true }, | ||
885 | [tegra_clk_pll_u_480m] = { .dt_id = TEGRA124_CLK_PLL_U_480M, .present = true }, | ||
886 | [tegra_clk_pll_u_60m] = { .dt_id = TEGRA124_CLK_PLL_U_60M, .present = true }, | ||
887 | [tegra_clk_pll_u_48m] = { .dt_id = TEGRA124_CLK_PLL_U_48M, .present = true }, | ||
888 | [tegra_clk_pll_u_12m] = { .dt_id = TEGRA124_CLK_PLL_U_12M, .present = true }, | ||
889 | [tegra_clk_pll_x] = { .dt_id = TEGRA124_CLK_PLL_X, .present = true }, | ||
890 | [tegra_clk_pll_x_out0] = { .dt_id = TEGRA124_CLK_PLL_X_OUT0, .present = true }, | ||
891 | [tegra_clk_pll_re_vco] = { .dt_id = TEGRA124_CLK_PLL_RE_VCO, .present = true }, | ||
892 | [tegra_clk_pll_re_out] = { .dt_id = TEGRA124_CLK_PLL_RE_OUT, .present = true }, | ||
893 | [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC, .present = true }, | ||
894 | [tegra_clk_i2s0_sync] = { .dt_id = TEGRA124_CLK_I2S0_SYNC, .present = true }, | ||
895 | [tegra_clk_i2s1_sync] = { .dt_id = TEGRA124_CLK_I2S1_SYNC, .present = true }, | ||
896 | [tegra_clk_i2s2_sync] = { .dt_id = TEGRA124_CLK_I2S2_SYNC, .present = true }, | ||
897 | [tegra_clk_i2s3_sync] = { .dt_id = TEGRA124_CLK_I2S3_SYNC, .present = true }, | ||
898 | [tegra_clk_i2s4_sync] = { .dt_id = TEGRA124_CLK_I2S4_SYNC, .present = true }, | ||
899 | [tegra_clk_vimclk_sync] = { .dt_id = TEGRA124_CLK_VIMCLK_SYNC, .present = true }, | ||
900 | [tegra_clk_audio0] = { .dt_id = TEGRA124_CLK_AUDIO0, .present = true }, | ||
901 | [tegra_clk_audio1] = { .dt_id = TEGRA124_CLK_AUDIO1, .present = true }, | ||
902 | [tegra_clk_audio2] = { .dt_id = TEGRA124_CLK_AUDIO2, .present = true }, | ||
903 | [tegra_clk_audio3] = { .dt_id = TEGRA124_CLK_AUDIO3, .present = true }, | ||
904 | [tegra_clk_audio4] = { .dt_id = TEGRA124_CLK_AUDIO4, .present = true }, | ||
905 | [tegra_clk_spdif] = { .dt_id = TEGRA124_CLK_SPDIF, .present = true }, | ||
906 | [tegra_clk_clk_out_1] = { .dt_id = TEGRA124_CLK_CLK_OUT_1, .present = true }, | ||
907 | [tegra_clk_clk_out_2] = { .dt_id = TEGRA124_CLK_CLK_OUT_2, .present = true }, | ||
908 | [tegra_clk_clk_out_3] = { .dt_id = TEGRA124_CLK_CLK_OUT_3, .present = true }, | ||
909 | [tegra_clk_blink] = { .dt_id = TEGRA124_CLK_BLINK, .present = true }, | ||
910 | [tegra_clk_xusb_host_src] = { .dt_id = TEGRA124_CLK_XUSB_HOST_SRC, .present = true }, | ||
911 | [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA124_CLK_XUSB_FALCON_SRC, .present = true }, | ||
912 | [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA124_CLK_XUSB_FS_SRC, .present = true }, | ||
913 | [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA124_CLK_XUSB_SS_SRC, .present = true }, | ||
914 | [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA124_CLK_XUSB_DEV_SRC, .present = true }, | ||
915 | [tegra_clk_xusb_dev] = { .dt_id = TEGRA124_CLK_XUSB_DEV, .present = true }, | ||
916 | [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA124_CLK_XUSB_HS_SRC, .present = true }, | ||
917 | [tegra_clk_sclk] = { .dt_id = TEGRA124_CLK_SCLK, .present = true }, | ||
918 | [tegra_clk_hclk] = { .dt_id = TEGRA124_CLK_HCLK, .present = true }, | ||
919 | [tegra_clk_pclk] = { .dt_id = TEGRA124_CLK_PCLK, .present = true }, | ||
920 | [tegra_clk_cclk_g] = { .dt_id = TEGRA124_CLK_CCLK_G, .present = true }, | ||
921 | [tegra_clk_cclk_lp] = { .dt_id = TEGRA124_CLK_CCLK_LP, .present = true }, | ||
922 | [tegra_clk_dfll_ref] = { .dt_id = TEGRA124_CLK_DFLL_REF, .present = true }, | ||
923 | [tegra_clk_dfll_soc] = { .dt_id = TEGRA124_CLK_DFLL_SOC, .present = true }, | ||
924 | [tegra_clk_vi_sensor2] = { .dt_id = TEGRA124_CLK_VI_SENSOR2, .present = true }, | ||
925 | [tegra_clk_pll_p_out5] = { .dt_id = TEGRA124_CLK_PLL_P_OUT5, .present = true }, | ||
926 | [tegra_clk_pll_c4] = { .dt_id = TEGRA124_CLK_PLL_C4, .present = true }, | ||
927 | [tegra_clk_pll_dp] = { .dt_id = TEGRA124_CLK_PLL_DP, .present = true }, | ||
928 | [tegra_clk_audio0_mux] = { .dt_id = TEGRA124_CLK_AUDIO0_MUX, .present = true }, | ||
929 | [tegra_clk_audio1_mux] = { .dt_id = TEGRA124_CLK_AUDIO1_MUX, .present = true }, | ||
930 | [tegra_clk_audio2_mux] = { .dt_id = TEGRA124_CLK_AUDIO2_MUX, .present = true }, | ||
931 | [tegra_clk_audio3_mux] = { .dt_id = TEGRA124_CLK_AUDIO3_MUX, .present = true }, | ||
932 | [tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true }, | ||
933 | [tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true }, | ||
934 | [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true }, | ||
935 | [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true }, | ||
936 | [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true }, | ||
937 | [tegra_clk_dsia_mux] = { .dt_id = TEGRA124_CLK_DSIA_MUX, .present = true }, | ||
938 | [tegra_clk_dsib_mux] = { .dt_id = TEGRA124_CLK_DSIB_MUX, .present = true }, | ||
939 | [tegra_clk_uarte] = { .dt_id = TEGRA124_CLK_UARTE, .present = true }, | ||
940 | }; | ||
941 | |||
942 | static struct tegra_devclk devclks[] __initdata = { | ||
943 | { .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M }, | ||
944 | { .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF }, | ||
945 | { .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K }, | ||
946 | { .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 }, | ||
947 | { .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 }, | ||
948 | { .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C }, | ||
949 | { .con_id = "pll_c_out1", .dt_id = TEGRA124_CLK_PLL_C_OUT1 }, | ||
950 | { .con_id = "pll_c2", .dt_id = TEGRA124_CLK_PLL_C2 }, | ||
951 | { .con_id = "pll_c3", .dt_id = TEGRA124_CLK_PLL_C3 }, | ||
952 | { .con_id = "pll_p", .dt_id = TEGRA124_CLK_PLL_P }, | ||
953 | { .con_id = "pll_p_out1", .dt_id = TEGRA124_CLK_PLL_P_OUT1 }, | ||
954 | { .con_id = "pll_p_out2", .dt_id = TEGRA124_CLK_PLL_P_OUT2 }, | ||
955 | { .con_id = "pll_p_out3", .dt_id = TEGRA124_CLK_PLL_P_OUT3 }, | ||
956 | { .con_id = "pll_p_out4", .dt_id = TEGRA124_CLK_PLL_P_OUT4 }, | ||
957 | { .con_id = "pll_m", .dt_id = TEGRA124_CLK_PLL_M }, | ||
958 | { .con_id = "pll_m_out1", .dt_id = TEGRA124_CLK_PLL_M_OUT1 }, | ||
959 | { .con_id = "pll_x", .dt_id = TEGRA124_CLK_PLL_X }, | ||
960 | { .con_id = "pll_x_out0", .dt_id = TEGRA124_CLK_PLL_X_OUT0 }, | ||
961 | { .con_id = "pll_u", .dt_id = TEGRA124_CLK_PLL_U }, | ||
962 | { .con_id = "pll_u_480M", .dt_id = TEGRA124_CLK_PLL_U_480M }, | ||
963 | { .con_id = "pll_u_60M", .dt_id = TEGRA124_CLK_PLL_U_60M }, | ||
964 | { .con_id = "pll_u_48M", .dt_id = TEGRA124_CLK_PLL_U_48M }, | ||
965 | { .con_id = "pll_u_12M", .dt_id = TEGRA124_CLK_PLL_U_12M }, | ||
966 | { .con_id = "pll_d", .dt_id = TEGRA124_CLK_PLL_D }, | ||
967 | { .con_id = "pll_d_out0", .dt_id = TEGRA124_CLK_PLL_D_OUT0 }, | ||
968 | { .con_id = "pll_d2", .dt_id = TEGRA124_CLK_PLL_D2 }, | ||
969 | { .con_id = "pll_d2_out0", .dt_id = TEGRA124_CLK_PLL_D2_OUT0 }, | ||
970 | { .con_id = "pll_a", .dt_id = TEGRA124_CLK_PLL_A }, | ||
971 | { .con_id = "pll_a_out0", .dt_id = TEGRA124_CLK_PLL_A_OUT0 }, | ||
972 | { .con_id = "pll_re_vco", .dt_id = TEGRA124_CLK_PLL_RE_VCO }, | ||
973 | { .con_id = "pll_re_out", .dt_id = TEGRA124_CLK_PLL_RE_OUT }, | ||
974 | { .con_id = "spdif_in_sync", .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC }, | ||
975 | { .con_id = "i2s0_sync", .dt_id = TEGRA124_CLK_I2S0_SYNC }, | ||
976 | { .con_id = "i2s1_sync", .dt_id = TEGRA124_CLK_I2S1_SYNC }, | ||
977 | { .con_id = "i2s2_sync", .dt_id = TEGRA124_CLK_I2S2_SYNC }, | ||
978 | { .con_id = "i2s3_sync", .dt_id = TEGRA124_CLK_I2S3_SYNC }, | ||
979 | { .con_id = "i2s4_sync", .dt_id = TEGRA124_CLK_I2S4_SYNC }, | ||
980 | { .con_id = "vimclk_sync", .dt_id = TEGRA124_CLK_VIMCLK_SYNC }, | ||
981 | { .con_id = "audio0", .dt_id = TEGRA124_CLK_AUDIO0 }, | ||
982 | { .con_id = "audio1", .dt_id = TEGRA124_CLK_AUDIO1 }, | ||
983 | { .con_id = "audio2", .dt_id = TEGRA124_CLK_AUDIO2 }, | ||
984 | { .con_id = "audio3", .dt_id = TEGRA124_CLK_AUDIO3 }, | ||
985 | { .con_id = "audio4", .dt_id = TEGRA124_CLK_AUDIO4 }, | ||
986 | { .con_id = "spdif", .dt_id = TEGRA124_CLK_SPDIF }, | ||
987 | { .con_id = "audio0_2x", .dt_id = TEGRA124_CLK_AUDIO0_2X }, | ||
988 | { .con_id = "audio1_2x", .dt_id = TEGRA124_CLK_AUDIO1_2X }, | ||
989 | { .con_id = "audio2_2x", .dt_id = TEGRA124_CLK_AUDIO2_2X }, | ||
990 | { .con_id = "audio3_2x", .dt_id = TEGRA124_CLK_AUDIO3_2X }, | ||
991 | { .con_id = "audio4_2x", .dt_id = TEGRA124_CLK_AUDIO4_2X }, | ||
992 | { .con_id = "spdif_2x", .dt_id = TEGRA124_CLK_SPDIF_2X }, | ||
993 | { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA124_CLK_EXTERN1 }, | ||
994 | { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA124_CLK_EXTERN2 }, | ||
995 | { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA124_CLK_EXTERN3 }, | ||
996 | { .con_id = "blink", .dt_id = TEGRA124_CLK_BLINK }, | ||
997 | { .con_id = "cclk_g", .dt_id = TEGRA124_CLK_CCLK_G }, | ||
998 | { .con_id = "cclk_lp", .dt_id = TEGRA124_CLK_CCLK_LP }, | ||
999 | { .con_id = "sclk", .dt_id = TEGRA124_CLK_SCLK }, | ||
1000 | { .con_id = "hclk", .dt_id = TEGRA124_CLK_HCLK }, | ||
1001 | { .con_id = "pclk", .dt_id = TEGRA124_CLK_PCLK }, | ||
1002 | { .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC }, | ||
1003 | { .dev_id = "timer", .dt_id = TEGRA124_CLK_TIMER }, | ||
1004 | }; | ||
1005 | |||
1006 | static struct clk **clks; | ||
1007 | |||
1008 | static void tegra124_utmi_param_configure(void __iomem *clk_base) | ||
1009 | { | ||
1010 | u32 reg; | ||
1011 | int i; | ||
1012 | |||
1013 | for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { | ||
1014 | if (osc_freq == utmi_parameters[i].osc_frequency) | ||
1015 | break; | ||
1016 | } | ||
1017 | |||
1018 | if (i >= ARRAY_SIZE(utmi_parameters)) { | ||
1019 | pr_err("%s: Unexpected oscillator freq %lu\n", __func__, | ||
1020 | osc_freq); | ||
1021 | return; | ||
1022 | } | ||
1023 | |||
1024 | reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); | ||
1025 | |||
1026 | /* Program UTMIP PLL stable and active counts */ | ||
1027 | /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */ | ||
1028 | reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); | ||
1029 | reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count); | ||
1030 | |||
1031 | reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); | ||
1032 | |||
1033 | reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i]. | ||
1034 | active_delay_count); | ||
1035 | |||
1036 | /* Remove power downs from UTMIP PLL control bits */ | ||
1037 | reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; | ||
1038 | reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; | ||
1039 | reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; | ||
1040 | |||
1041 | writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); | ||
1042 | |||
1043 | /* Program UTMIP PLL delay and oscillator frequency counts */ | ||
1044 | reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); | ||
1045 | reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); | ||
1046 | |||
1047 | reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i]. | ||
1048 | enable_delay_count); | ||
1049 | |||
1050 | reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); | ||
1051 | reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i]. | ||
1052 | xtal_freq_count); | ||
1053 | |||
1054 | /* Remove power downs from UTMIP PLL control bits */ | ||
1055 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; | ||
1056 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; | ||
1057 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP; | ||
1058 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; | ||
1059 | writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); | ||
1060 | |||
1061 | /* Setup HW control of UTMIPLL */ | ||
1062 | reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); | ||
1063 | reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET; | ||
1064 | reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL; | ||
1065 | reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE; | ||
1066 | writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); | ||
1067 | |||
1068 | reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); | ||
1069 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; | ||
1070 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; | ||
1071 | writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); | ||
1072 | |||
1073 | udelay(1); | ||
1074 | |||
1075 | /* Setup SW override of UTMIPLL assuming USB2.0 | ||
1076 | ports are assigned to USB2 */ | ||
1077 | reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); | ||
1078 | reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL; | ||
1079 | reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; | ||
1080 | writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); | ||
1081 | |||
1082 | udelay(1); | ||
1083 | |||
1084 | /* Enable HW control UTMIPLL */ | ||
1085 | reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); | ||
1086 | reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; | ||
1087 | writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); | ||
1088 | } | ||
1089 | |||
1090 | static __init void tegra124_periph_clk_init(void __iomem *clk_base, | ||
1091 | void __iomem *pmc_base) | ||
1092 | { | ||
1093 | struct clk *clk; | ||
1094 | u32 val; | ||
1095 | |||
1096 | /* xusb_hs_src */ | ||
1097 | val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC); | ||
1098 | val |= BIT(25); /* always select PLLU_60M */ | ||
1099 | writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC); | ||
1100 | |||
1101 | clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0, | ||
1102 | 1, 1); | ||
1103 | clks[TEGRA124_CLK_XUSB_HS_SRC] = clk; | ||
1104 | |||
1105 | /* dsia mux */ | ||
1106 | clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0, | ||
1107 | ARRAY_SIZE(mux_plld_out0_plld2_out0), 0, | ||
1108 | clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock); | ||
1109 | clks[TEGRA124_CLK_DSIA_MUX] = clk; | ||
1110 | |||
1111 | /* dsib mux */ | ||
1112 | clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0, | ||
1113 | ARRAY_SIZE(mux_plld_out0_plld2_out0), 0, | ||
1114 | clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock); | ||
1115 | clks[TEGRA124_CLK_DSIB_MUX] = clk; | ||
1116 | |||
1117 | /* emc mux */ | ||
1118 | clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, | ||
1119 | ARRAY_SIZE(mux_pllmcp_clkm), 0, | ||
1120 | clk_base + CLK_SOURCE_EMC, | ||
1121 | 29, 3, 0, NULL); | ||
1122 | |||
1123 | /* cml0 */ | ||
1124 | clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, | ||
1125 | 0, 0, &pll_e_lock); | ||
1126 | clk_register_clkdev(clk, "cml0", NULL); | ||
1127 | clks[TEGRA124_CLK_CML0] = clk; | ||
1128 | |||
1129 | /* cml1 */ | ||
1130 | clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, | ||
1131 | 1, 0, &pll_e_lock); | ||
1132 | clk_register_clkdev(clk, "cml1", NULL); | ||
1133 | clks[TEGRA124_CLK_CML1] = clk; | ||
1134 | |||
1135 | tegra_periph_clk_init(clk_base, pmc_base, tegra124_clks, &pll_p_params); | ||
1136 | } | ||
1137 | |||
1138 | static void __init tegra124_pll_init(void __iomem *clk_base, | ||
1139 | void __iomem *pmc) | ||
1140 | { | ||
1141 | u32 val; | ||
1142 | struct clk *clk; | ||
1143 | |||
1144 | /* PLLC */ | ||
1145 | clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, | ||
1146 | pmc, 0, &pll_c_params, NULL); | ||
1147 | clk_register_clkdev(clk, "pll_c", NULL); | ||
1148 | clks[TEGRA124_CLK_PLL_C] = clk; | ||
1149 | |||
1150 | /* PLLC_OUT1 */ | ||
1151 | clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", | ||
1152 | clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, | ||
1153 | 8, 8, 1, NULL); | ||
1154 | clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", | ||
1155 | clk_base + PLLC_OUT, 1, 0, | ||
1156 | CLK_SET_RATE_PARENT, 0, NULL); | ||
1157 | clk_register_clkdev(clk, "pll_c_out1", NULL); | ||
1158 | clks[TEGRA124_CLK_PLL_C_OUT1] = clk; | ||
1159 | |||
1160 | /* PLLC2 */ | ||
1161 | clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, | ||
1162 | &pll_c2_params, NULL); | ||
1163 | clk_register_clkdev(clk, "pll_c2", NULL); | ||
1164 | clks[TEGRA124_CLK_PLL_C2] = clk; | ||
1165 | |||
1166 | /* PLLC3 */ | ||
1167 | clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, | ||
1168 | &pll_c3_params, NULL); | ||
1169 | clk_register_clkdev(clk, "pll_c3", NULL); | ||
1170 | clks[TEGRA124_CLK_PLL_C3] = clk; | ||
1171 | |||
1172 | /* PLLM */ | ||
1173 | clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc, | ||
1174 | CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, | ||
1175 | &pll_m_params, NULL); | ||
1176 | clk_register_clkdev(clk, "pll_m", NULL); | ||
1177 | clks[TEGRA124_CLK_PLL_M] = clk; | ||
1178 | |||
1179 | /* PLLM_OUT1 */ | ||
1180 | clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", | ||
1181 | clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, | ||
1182 | 8, 8, 1, NULL); | ||
1183 | clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", | ||
1184 | clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | | ||
1185 | CLK_SET_RATE_PARENT, 0, NULL); | ||
1186 | clk_register_clkdev(clk, "pll_m_out1", NULL); | ||
1187 | clks[TEGRA124_CLK_PLL_M_OUT1] = clk; | ||
1188 | |||
1189 | /* PLLM_UD */ | ||
1190 | clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m", | ||
1191 | CLK_SET_RATE_PARENT, 1, 1); | ||
1192 | |||
1193 | /* PLLU */ | ||
1194 | val = readl(clk_base + pll_u_params.base_reg); | ||
1195 | val &= ~BIT(24); /* disable PLLU_OVERRIDE */ | ||
1196 | writel(val, clk_base + pll_u_params.base_reg); | ||
1197 | |||
1198 | clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0, | ||
1199 | &pll_u_params, &pll_u_lock); | ||
1200 | clk_register_clkdev(clk, "pll_u", NULL); | ||
1201 | clks[TEGRA124_CLK_PLL_U] = clk; | ||
1202 | |||
1203 | tegra124_utmi_param_configure(clk_base); | ||
1204 | |||
1205 | /* PLLU_480M */ | ||
1206 | clk = clk_register_gate(NULL, "pll_u_480M", "pll_u", | ||
1207 | CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, | ||
1208 | 22, 0, &pll_u_lock); | ||
1209 | clk_register_clkdev(clk, "pll_u_480M", NULL); | ||
1210 | clks[TEGRA124_CLK_PLL_U_480M] = clk; | ||
1211 | |||
1212 | /* PLLU_60M */ | ||
1213 | clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u", | ||
1214 | CLK_SET_RATE_PARENT, 1, 8); | ||
1215 | clk_register_clkdev(clk, "pll_u_60M", NULL); | ||
1216 | clks[TEGRA124_CLK_PLL_U_60M] = clk; | ||
1217 | |||
1218 | /* PLLU_48M */ | ||
1219 | clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u", | ||
1220 | CLK_SET_RATE_PARENT, 1, 10); | ||
1221 | clk_register_clkdev(clk, "pll_u_48M", NULL); | ||
1222 | clks[TEGRA124_CLK_PLL_U_48M] = clk; | ||
1223 | |||
1224 | /* PLLU_12M */ | ||
1225 | clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u", | ||
1226 | CLK_SET_RATE_PARENT, 1, 40); | ||
1227 | clk_register_clkdev(clk, "pll_u_12M", NULL); | ||
1228 | clks[TEGRA124_CLK_PLL_U_12M] = clk; | ||
1229 | |||
1230 | /* PLLD */ | ||
1231 | clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, | ||
1232 | &pll_d_params, &pll_d_lock); | ||
1233 | clk_register_clkdev(clk, "pll_d", NULL); | ||
1234 | clks[TEGRA124_CLK_PLL_D] = clk; | ||
1235 | |||
1236 | /* PLLD_OUT0 */ | ||
1237 | clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", | ||
1238 | CLK_SET_RATE_PARENT, 1, 2); | ||
1239 | clk_register_clkdev(clk, "pll_d_out0", NULL); | ||
1240 | clks[TEGRA124_CLK_PLL_D_OUT0] = clk; | ||
1241 | |||
1242 | /* PLLRE */ | ||
1243 | clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc, | ||
1244 | 0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq); | ||
1245 | clk_register_clkdev(clk, "pll_re_vco", NULL); | ||
1246 | clks[TEGRA124_CLK_PLL_RE_VCO] = clk; | ||
1247 | |||
1248 | clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0, | ||
1249 | clk_base + PLLRE_BASE, 16, 4, 0, | ||
1250 | pll_re_div_table, &pll_re_lock); | ||
1251 | clk_register_clkdev(clk, "pll_re_out", NULL); | ||
1252 | clks[TEGRA124_CLK_PLL_RE_OUT] = clk; | ||
1253 | |||
1254 | /* PLLE */ | ||
1255 | clk = tegra_clk_register_plle_tegra114("pll_e", "pll_ref", | ||
1256 | clk_base, 0, &pll_e_params, NULL); | ||
1257 | clk_register_clkdev(clk, "pll_e", NULL); | ||
1258 | clks[TEGRA124_CLK_PLL_E] = clk; | ||
1259 | |||
1260 | /* PLLC4 */ | ||
1261 | clk = tegra_clk_register_pllss("pll_c4", "pll_ref", clk_base, 0, | ||
1262 | &pll_c4_params, NULL); | ||
1263 | clk_register_clkdev(clk, "pll_c4", NULL); | ||
1264 | clks[TEGRA124_CLK_PLL_C4] = clk; | ||
1265 | |||
1266 | /* PLLDP */ | ||
1267 | clk = tegra_clk_register_pllss("pll_dp", "pll_ref", clk_base, 0, | ||
1268 | &pll_dp_params, NULL); | ||
1269 | clk_register_clkdev(clk, "pll_dp", NULL); | ||
1270 | clks[TEGRA124_CLK_PLL_DP] = clk; | ||
1271 | |||
1272 | /* PLLD2 */ | ||
1273 | clk = tegra_clk_register_pllss("pll_d2", "pll_ref", clk_base, 0, | ||
1274 | &tegra124_pll_d2_params, NULL); | ||
1275 | clk_register_clkdev(clk, "pll_d2", NULL); | ||
1276 | clks[TEGRA124_CLK_PLL_D2] = clk; | ||
1277 | |||
1278 | /* PLLD2_OUT0 ?? */ | ||
1279 | clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", | ||
1280 | CLK_SET_RATE_PARENT, 1, 2); | ||
1281 | clk_register_clkdev(clk, "pll_d2_out0", NULL); | ||
1282 | clks[TEGRA124_CLK_PLL_D2_OUT0] = clk; | ||
1283 | |||
1284 | } | ||
1285 | |||
1286 | static const struct of_device_id pmc_match[] __initconst = { | ||
1287 | { .compatible = "nvidia,tegra124-pmc" }, | ||
1288 | {}, | ||
1289 | }; | ||
1290 | |||
1291 | static struct tegra_clk_init_table init_table[] __initdata = { | ||
1292 | {TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 408000000, 0}, | ||
1293 | {TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0}, | ||
1294 | {TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0}, | ||
1295 | {TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0}, | ||
1296 | {TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1}, | ||
1297 | {TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1}, | ||
1298 | {TEGRA124_CLK_EXTERN1, TEGRA124_CLK_PLL_A_OUT0, 0, 1}, | ||
1299 | {TEGRA124_CLK_CLK_OUT_1_MUX, TEGRA124_CLK_EXTERN1, 0, 1}, | ||
1300 | {TEGRA124_CLK_CLK_OUT_1, TEGRA124_CLK_CLK_MAX, 0, 1}, | ||
1301 | {TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0}, | ||
1302 | {TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0}, | ||
1303 | {TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0}, | ||
1304 | {TEGRA124_CLK_I2S3, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0}, | ||
1305 | {TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0}, | ||
1306 | {TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_P, 0, 0}, | ||
1307 | {TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1}, | ||
1308 | {TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 1}, | ||
1309 | {TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1}, | ||
1310 | {TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1}, | ||
1311 | {TEGRA124_CLK_PLL_C, TEGRA124_CLK_CLK_MAX, 768000000, 0}, | ||
1312 | {TEGRA124_CLK_PLL_C_OUT1, TEGRA124_CLK_CLK_MAX, 100000000, 0}, | ||
1313 | {TEGRA124_CLK_SBC4, TEGRA124_CLK_PLL_P, 12000000, 1}, | ||
1314 | {TEGRA124_CLK_TSEC, TEGRA124_CLK_PLL_C3, 0, 0}, | ||
1315 | {TEGRA124_CLK_MSENC, TEGRA124_CLK_PLL_C3, 0, 0}, | ||
1316 | /* This MUST be the last entry. */ | ||
1317 | {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0}, | ||
1318 | }; | ||
1319 | |||
1320 | static void __init tegra124_clock_apply_init_table(void) | ||
1321 | { | ||
1322 | tegra_init_from_table(init_table, clks, TEGRA124_CLK_CLK_MAX); | ||
1323 | } | ||
1324 | |||
1325 | static void __init tegra124_clock_init(struct device_node *np) | ||
1326 | { | ||
1327 | struct device_node *node; | ||
1328 | |||
1329 | clk_base = of_iomap(np, 0); | ||
1330 | if (!clk_base) { | ||
1331 | pr_err("ioremap tegra124 CAR failed\n"); | ||
1332 | return; | ||
1333 | } | ||
1334 | |||
1335 | node = of_find_matching_node(NULL, pmc_match); | ||
1336 | if (!node) { | ||
1337 | pr_err("Failed to find pmc node\n"); | ||
1338 | WARN_ON(1); | ||
1339 | return; | ||
1340 | } | ||
1341 | |||
1342 | pmc_base = of_iomap(node, 0); | ||
1343 | if (!pmc_base) { | ||
1344 | pr_err("Can't map pmc registers\n"); | ||
1345 | WARN_ON(1); | ||
1346 | return; | ||
1347 | } | ||
1348 | |||
1349 | clks = tegra_clk_init(TEGRA124_CLK_CLK_MAX, 6); | ||
1350 | if (!clks) | ||
1351 | return; | ||
1352 | |||
1353 | if (tegra_osc_clk_init(clk_base, tegra124_clks, tegra124_input_freq, | ||
1354 | ARRAY_SIZE(tegra124_input_freq), &osc_freq, &pll_ref_freq) < 0) | ||
1355 | return; | ||
1356 | |||
1357 | tegra_fixed_clk_init(tegra124_clks); | ||
1358 | tegra124_pll_init(clk_base, pmc_base); | ||
1359 | tegra124_periph_clk_init(clk_base, pmc_base); | ||
1360 | tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks, &pll_a_params); | ||
1361 | tegra_pmc_clk_init(pmc_base, tegra124_clks); | ||
1362 | |||
1363 | tegra_super_clk_gen4_init(clk_base, pmc_base, tegra124_clks, | ||
1364 | &pll_x_params); | ||
1365 | tegra_add_of_provider(np); | ||
1366 | tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); | ||
1367 | |||
1368 | tegra_clk_apply_init_table = tegra124_clock_apply_init_table; | ||
1369 | } | ||
1370 | CLK_OF_DECLARE(tegra124, "nvidia,tegra124-car", tegra124_clock_init); | ||
diff --git a/include/dt-bindings/clock/tegra124-car.h b/include/dt-bindings/clock/tegra124-car.h new file mode 100644 index 000000000000..a1116a3b54ef --- /dev/null +++ b/include/dt-bindings/clock/tegra124-car.h | |||
@@ -0,0 +1,341 @@ | |||
1 | /* | ||
2 | * This header provides constants for binding nvidia,tegra124-car. | ||
3 | * | ||
4 | * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB | ||
5 | * registers. These IDs often match those in the CAR's RST_DEVICES registers, | ||
6 | * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In | ||
7 | * this case, those clocks are assigned IDs above 185 in order to highlight | ||
8 | * this issue. Implementations that interpret these clock IDs as bit values | ||
9 | * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to | ||
10 | * explicitly handle these special cases. | ||
11 | * | ||
12 | * The balance of the clocks controlled by the CAR are assigned IDs of 185 and | ||
13 | * above. | ||
14 | */ | ||
15 | |||
16 | #ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_H | ||
17 | #define _DT_BINDINGS_CLOCK_TEGRA124_CAR_H | ||
18 | |||
19 | /* 0 */ | ||
20 | /* 1 */ | ||
21 | /* 2 */ | ||
22 | #define TEGRA124_CLK_ISPB 3 | ||
23 | #define TEGRA124_CLK_RTC 4 | ||
24 | #define TEGRA124_CLK_TIMER 5 | ||
25 | #define TEGRA124_CLK_UARTA 6 | ||
26 | /* 7 (register bit affects uartb and vfir) */ | ||
27 | /* 8 */ | ||
28 | #define TEGRA124_CLK_SDMMC2 9 | ||
29 | /* 10 (register bit affects spdif_in and spdif_out) */ | ||
30 | #define TEGRA124_CLK_I2S1 11 | ||
31 | #define TEGRA124_CLK_I2C1 12 | ||
32 | #define TEGRA124_CLK_NDFLASH 13 | ||
33 | #define TEGRA124_CLK_SDMMC1 14 | ||
34 | #define TEGRA124_CLK_SDMMC4 15 | ||
35 | /* 16 */ | ||
36 | #define TEGRA124_CLK_PWM 17 | ||
37 | #define TEGRA124_CLK_I2S2 18 | ||
38 | /* 20 (register bit affects vi and vi_sensor) */ | ||
39 | #define TEGRA124_CLK_GR_2D 21 | ||
40 | #define TEGRA124_CLK_USBD 22 | ||
41 | #define TEGRA124_CLK_ISP 23 | ||
42 | #define TEGRA124_CLK_GR_3D 24 | ||
43 | /* 25 */ | ||
44 | #define TEGRA124_CLK_DISP2 26 | ||
45 | #define TEGRA124_CLK_DISP1 27 | ||
46 | #define TEGRA124_CLK_HOST1X 28 | ||
47 | #define TEGRA124_CLK_VCP 29 | ||
48 | #define TEGRA124_CLK_I2S0 30 | ||
49 | /* 31 */ | ||
50 | |||
51 | /* 32 */ | ||
52 | /* 33 */ | ||
53 | #define TEGRA124_CLK_APBDMA 34 | ||
54 | /* 35 */ | ||
55 | #define TEGRA124_CLK_KBC 36 | ||
56 | /* 37 */ | ||
57 | /* 38 */ | ||
58 | /* 39 (register bit affects fuse and fuse_burn) */ | ||
59 | #define TEGRA124_CLK_KFUSE 40 | ||
60 | #define TEGRA124_CLK_SBC1 41 | ||
61 | #define TEGRA124_CLK_NOR 42 | ||
62 | /* 43 */ | ||
63 | #define TEGRA124_CLK_SBC2 44 | ||
64 | /* 45 */ | ||
65 | #define TEGRA124_CLK_SBC3 46 | ||
66 | #define TEGRA124_CLK_I2C5 47 | ||
67 | #define TEGRA124_CLK_DSIA 48 | ||
68 | /* 49 */ | ||
69 | #define TEGRA124_CLK_MIPI 50 | ||
70 | #define TEGRA124_CLK_HDMI 51 | ||
71 | #define TEGRA124_CLK_CSI 52 | ||
72 | /* 53 */ | ||
73 | #define TEGRA124_CLK_I2C2 54 | ||
74 | #define TEGRA124_CLK_UARTC 55 | ||
75 | #define TEGRA124_CLK_MIPI_CAL 56 | ||
76 | #define TEGRA124_CLK_EMC 57 | ||
77 | #define TEGRA124_CLK_USB2 58 | ||
78 | #define TEGRA124_CLK_USB3 59 | ||
79 | /* 60 */ | ||
80 | #define TEGRA124_CLK_VDE 61 | ||
81 | #define TEGRA124_CLK_BSEA 62 | ||
82 | #define TEGRA124_CLK_BSEV 63 | ||
83 | |||
84 | /* 64 */ | ||
85 | #define TEGRA124_CLK_UARTD 65 | ||
86 | #define TEGRA124_CLK_UARTE 66 | ||
87 | #define TEGRA124_CLK_I2C3 67 | ||
88 | #define TEGRA124_CLK_SBC4 68 | ||
89 | #define TEGRA124_CLK_SDMMC3 69 | ||
90 | #define TEGRA124_CLK_PCIE 70 | ||
91 | #define TEGRA124_CLK_OWR 71 | ||
92 | #define TEGRA124_CLK_AFI 72 | ||
93 | #define TEGRA124_CLK_CSITE 73 | ||
94 | /* 74 */ | ||
95 | /* 75 */ | ||
96 | #define TEGRA124_CLK_LA 76 | ||
97 | #define TEGRA124_CLK_TRACE 77 | ||
98 | #define TEGRA124_CLK_SOC_THERM 78 | ||
99 | #define TEGRA124_CLK_DTV 79 | ||
100 | #define TEGRA124_CLK_NDSPEED 80 | ||
101 | #define TEGRA124_CLK_I2CSLOW 81 | ||
102 | #define TEGRA124_CLK_DSIB 82 | ||
103 | #define TEGRA124_CLK_TSEC 83 | ||
104 | /* 84 */ | ||
105 | /* 85 */ | ||
106 | /* 86 */ | ||
107 | /* 87 */ | ||
108 | /* 88 */ | ||
109 | #define TEGRA124_CLK_XUSB_HOST 89 | ||
110 | /* 90 */ | ||
111 | #define TEGRA124_CLK_MSENC 91 | ||
112 | #define TEGRA124_CLK_CSUS 92 | ||
113 | /* 93 */ | ||
114 | /* 94 */ | ||
115 | /* 95 (bit affects xusb_dev and xusb_dev_src) */ | ||
116 | |||
117 | /* 96 */ | ||
118 | /* 97 */ | ||
119 | /* 98 */ | ||
120 | #define TEGRA124_CLK_MSELECT 99 | ||
121 | #define TEGRA124_CLK_TSENSOR 100 | ||
122 | #define TEGRA124_CLK_I2S3 101 | ||
123 | #define TEGRA124_CLK_I2S4 102 | ||
124 | #define TEGRA124_CLK_I2C4 103 | ||
125 | #define TEGRA124_CLK_SBC5 104 | ||
126 | #define TEGRA124_CLK_SBC6 105 | ||
127 | #define TEGRA124_CLK_D_AUDIO 106 | ||
128 | #define TEGRA124_CLK_APBIF 107 | ||
129 | #define TEGRA124_CLK_DAM0 108 | ||
130 | #define TEGRA124_CLK_DAM1 109 | ||
131 | #define TEGRA124_CLK_DAM2 110 | ||
132 | #define TEGRA124_CLK_HDA2CODEC_2X 111 | ||
133 | /* 112 */ | ||
134 | #define TEGRA124_CLK_AUDIO0_2X 113 | ||
135 | #define TEGRA124_CLK_AUDIO1_2X 114 | ||
136 | #define TEGRA124_CLK_AUDIO2_2X 115 | ||
137 | #define TEGRA124_CLK_AUDIO3_2X 116 | ||
138 | #define TEGRA124_CLK_AUDIO4_2X 117 | ||
139 | #define TEGRA124_CLK_SPDIF_2X 118 | ||
140 | #define TEGRA124_CLK_ACTMON 119 | ||
141 | #define TEGRA124_CLK_EXTERN1 120 | ||
142 | #define TEGRA124_CLK_EXTERN2 121 | ||
143 | #define TEGRA124_CLK_EXTERN3 122 | ||
144 | #define TEGRA124_CLK_SATA_OOB 123 | ||
145 | #define TEGRA124_CLK_SATA 124 | ||
146 | #define TEGRA124_CLK_HDA 125 | ||
147 | /* 126 */ | ||
148 | #define TEGRA124_CLK_SE 127 | ||
149 | |||
150 | #define TEGRA124_CLK_HDA2HDMI 128 | ||
151 | #define TEGRA124_CLK_SATA_COLD 129 | ||
152 | /* 130 */ | ||
153 | /* 131 */ | ||
154 | /* 132 */ | ||
155 | /* 133 */ | ||
156 | /* 134 */ | ||
157 | /* 135 */ | ||
158 | /* 136 */ | ||
159 | /* 137 */ | ||
160 | /* 138 */ | ||
161 | /* 139 */ | ||
162 | /* 140 */ | ||
163 | /* 141 */ | ||
164 | /* 142 */ | ||
165 | /* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ | ||
166 | /* xusb_host_src and xusb_ss_src) */ | ||
167 | #define TEGRA124_CLK_CILAB 144 | ||
168 | #define TEGRA124_CLK_CILCD 145 | ||
169 | #define TEGRA124_CLK_CILE 146 | ||
170 | #define TEGRA124_CLK_DSIALP 147 | ||
171 | #define TEGRA124_CLK_DSIBLP 148 | ||
172 | #define TEGRA124_CLK_ENTROPY 149 | ||
173 | #define TEGRA124_CLK_DDS 150 | ||
174 | /* 151 */ | ||
175 | #define TEGRA124_CLK_DP2 152 | ||
176 | #define TEGRA124_CLK_AMX 153 | ||
177 | #define TEGRA124_CLK_ADX 154 | ||
178 | /* 155 (bit affects dfll_ref and dfll_soc) */ | ||
179 | #define TEGRA124_CLK_XUSB_SS 156 | ||
180 | /* 157 */ | ||
181 | /* 158 */ | ||
182 | /* 159 */ | ||
183 | |||
184 | /* 160 */ | ||
185 | /* 161 */ | ||
186 | /* 162 */ | ||
187 | /* 163 */ | ||
188 | /* 164 */ | ||
189 | /* 165 */ | ||
190 | #define TEGRA124_CLK_I2C6 166 | ||
191 | /* 167 */ | ||
192 | /* 168 */ | ||
193 | /* 169 */ | ||
194 | /* 170 */ | ||
195 | #define TEGRA124_CLK_VIM2_CLK 171 | ||
196 | /* 172 */ | ||
197 | /* 173 */ | ||
198 | /* 174 */ | ||
199 | /* 175 */ | ||
200 | #define TEGRA124_CLK_HDMI_AUDIO 176 | ||
201 | #define TEGRA124_CLK_CLK72MHZ 177 | ||
202 | #define TEGRA124_CLK_VIC03 178 | ||
203 | /* 179 */ | ||
204 | #define TEGRA124_CLK_ADX1 180 | ||
205 | #define TEGRA124_CLK_DPAUX 181 | ||
206 | #define TEGRA124_CLK_SOR0 182 | ||
207 | /* 183 */ | ||
208 | #define TEGRA124_CLK_GPU 184 | ||
209 | #define TEGRA124_CLK_AMX1 185 | ||
210 | /* 186 */ | ||
211 | /* 187 */ | ||
212 | /* 188 */ | ||
213 | /* 189 */ | ||
214 | /* 190 */ | ||
215 | /* 191 */ | ||
216 | #define TEGRA124_CLK_UARTB 192 | ||
217 | #define TEGRA124_CLK_VFIR 193 | ||
218 | #define TEGRA124_CLK_SPDIF_IN 194 | ||
219 | #define TEGRA124_CLK_SPDIF_OUT 195 | ||
220 | #define TEGRA124_CLK_VI 196 | ||
221 | #define TEGRA124_CLK_VI_SENSOR 197 | ||
222 | #define TEGRA124_CLK_FUSE 198 | ||
223 | #define TEGRA124_CLK_FUSE_BURN 199 | ||
224 | #define TEGRA124_CLK_CLK_32K 200 | ||
225 | #define TEGRA124_CLK_CLK_M 201 | ||
226 | #define TEGRA124_CLK_CLK_M_DIV2 202 | ||
227 | #define TEGRA124_CLK_CLK_M_DIV4 203 | ||
228 | #define TEGRA124_CLK_PLL_REF 204 | ||
229 | #define TEGRA124_CLK_PLL_C 205 | ||
230 | #define TEGRA124_CLK_PLL_C_OUT1 206 | ||
231 | #define TEGRA124_CLK_PLL_C2 207 | ||
232 | #define TEGRA124_CLK_PLL_C3 208 | ||
233 | #define TEGRA124_CLK_PLL_M 209 | ||
234 | #define TEGRA124_CLK_PLL_M_OUT1 210 | ||
235 | #define TEGRA124_CLK_PLL_P 211 | ||
236 | #define TEGRA124_CLK_PLL_P_OUT1 212 | ||
237 | #define TEGRA124_CLK_PLL_P_OUT2 213 | ||
238 | #define TEGRA124_CLK_PLL_P_OUT3 214 | ||
239 | #define TEGRA124_CLK_PLL_P_OUT4 215 | ||
240 | #define TEGRA124_CLK_PLL_A 216 | ||
241 | #define TEGRA124_CLK_PLL_A_OUT0 217 | ||
242 | #define TEGRA124_CLK_PLL_D 218 | ||
243 | #define TEGRA124_CLK_PLL_D_OUT0 219 | ||
244 | #define TEGRA124_CLK_PLL_D2 220 | ||
245 | #define TEGRA124_CLK_PLL_D2_OUT0 221 | ||
246 | #define TEGRA124_CLK_PLL_U 222 | ||
247 | #define TEGRA124_CLK_PLL_U_480M 223 | ||
248 | |||
249 | #define TEGRA124_CLK_PLL_U_60M 224 | ||
250 | #define TEGRA124_CLK_PLL_U_48M 225 | ||
251 | #define TEGRA124_CLK_PLL_U_12M 226 | ||
252 | #define TEGRA124_CLK_PLL_X 227 | ||
253 | #define TEGRA124_CLK_PLL_X_OUT0 228 | ||
254 | #define TEGRA124_CLK_PLL_RE_VCO 229 | ||
255 | #define TEGRA124_CLK_PLL_RE_OUT 230 | ||
256 | #define TEGRA124_CLK_PLL_E 231 | ||
257 | #define TEGRA124_CLK_SPDIF_IN_SYNC 232 | ||
258 | #define TEGRA124_CLK_I2S0_SYNC 233 | ||
259 | #define TEGRA124_CLK_I2S1_SYNC 234 | ||
260 | #define TEGRA124_CLK_I2S2_SYNC 235 | ||
261 | #define TEGRA124_CLK_I2S3_SYNC 236 | ||
262 | #define TEGRA124_CLK_I2S4_SYNC 237 | ||
263 | #define TEGRA124_CLK_VIMCLK_SYNC 238 | ||
264 | #define TEGRA124_CLK_AUDIO0 239 | ||
265 | #define TEGRA124_CLK_AUDIO1 240 | ||
266 | #define TEGRA124_CLK_AUDIO2 241 | ||
267 | #define TEGRA124_CLK_AUDIO3 242 | ||
268 | #define TEGRA124_CLK_AUDIO4 243 | ||
269 | #define TEGRA124_CLK_SPDIF 244 | ||
270 | #define TEGRA124_CLK_CLK_OUT_1 245 | ||
271 | #define TEGRA124_CLK_CLK_OUT_2 246 | ||
272 | #define TEGRA124_CLK_CLK_OUT_3 247 | ||
273 | #define TEGRA124_CLK_BLINK 248 | ||
274 | /* 249 */ | ||
275 | /* 250 */ | ||
276 | /* 251 */ | ||
277 | #define TEGRA124_CLK_XUSB_HOST_SRC 252 | ||
278 | #define TEGRA124_CLK_XUSB_FALCON_SRC 253 | ||
279 | #define TEGRA124_CLK_XUSB_FS_SRC 254 | ||
280 | #define TEGRA124_CLK_XUSB_SS_SRC 255 | ||
281 | |||
282 | #define TEGRA124_CLK_XUSB_DEV_SRC 256 | ||
283 | #define TEGRA124_CLK_XUSB_DEV 257 | ||
284 | #define TEGRA124_CLK_XUSB_HS_SRC 258 | ||
285 | #define TEGRA124_CLK_SCLK 259 | ||
286 | #define TEGRA124_CLK_HCLK 260 | ||
287 | #define TEGRA124_CLK_PCLK 261 | ||
288 | #define TEGRA124_CLK_CCLK_G 262 | ||
289 | #define TEGRA124_CLK_CCLK_LP 263 | ||
290 | #define TEGRA124_CLK_DFLL_REF 264 | ||
291 | #define TEGRA124_CLK_DFLL_SOC 265 | ||
292 | #define TEGRA124_CLK_VI_SENSOR2 266 | ||
293 | #define TEGRA124_CLK_PLL_P_OUT5 267 | ||
294 | #define TEGRA124_CLK_CML0 268 | ||
295 | #define TEGRA124_CLK_CML1 269 | ||
296 | #define TEGRA124_CLK_PLL_C4 270 | ||
297 | #define TEGRA124_CLK_PLL_DP 271 | ||
298 | #define TEGRA124_CLK_PLL_E_MUX 272 | ||
299 | /* 273 */ | ||
300 | /* 274 */ | ||
301 | /* 275 */ | ||
302 | /* 276 */ | ||
303 | /* 277 */ | ||
304 | /* 278 */ | ||
305 | /* 279 */ | ||
306 | /* 280 */ | ||
307 | /* 281 */ | ||
308 | /* 282 */ | ||
309 | /* 283 */ | ||
310 | /* 284 */ | ||
311 | /* 285 */ | ||
312 | /* 286 */ | ||
313 | /* 287 */ | ||
314 | |||
315 | /* 288 */ | ||
316 | /* 289 */ | ||
317 | /* 290 */ | ||
318 | /* 291 */ | ||
319 | /* 292 */ | ||
320 | /* 293 */ | ||
321 | /* 294 */ | ||
322 | /* 295 */ | ||
323 | /* 296 */ | ||
324 | /* 297 */ | ||
325 | /* 298 */ | ||
326 | /* 299 */ | ||
327 | #define TEGRA124_CLK_AUDIO0_MUX 300 | ||
328 | #define TEGRA124_CLK_AUDIO1_MUX 301 | ||
329 | #define TEGRA124_CLK_AUDIO2_MUX 302 | ||
330 | #define TEGRA124_CLK_AUDIO3_MUX 303 | ||
331 | #define TEGRA124_CLK_AUDIO4_MUX 304 | ||
332 | #define TEGRA124_CLK_SPDIF_MUX 305 | ||
333 | #define TEGRA124_CLK_CLK_OUT_1_MUX 306 | ||
334 | #define TEGRA124_CLK_CLK_OUT_2_MUX 307 | ||
335 | #define TEGRA124_CLK_CLK_OUT_3_MUX 308 | ||
336 | #define TEGRA124_CLK_DSIA_MUX 309 | ||
337 | #define TEGRA124_CLK_DSIB_MUX 310 | ||
338 | #define TEGRA124_CLK_SOR0_LVDS 311 | ||
339 | #define TEGRA124_CLK_CLK_MAX 312 | ||
340 | |||
341 | #endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */ | ||