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authorPeter De Schrijver <pdeschrijver@nvidia.com>2013-09-26 11:30:01 -0400
committerPeter De Schrijver <pdeschrijver@nvidia.com>2013-11-26 11:43:58 -0500
commit642fb0cf517173948684122403d73513c8c8b033 (patch)
tree207fe1800adbec7c7ad1bcb86b00851c7949bfd6
parent897e1dde1ec1571a28545594633624927fa0a76e (diff)
clk: tegra: PLLE spread spectrum control
Add spread spectrum control for PLLE in Tegra114. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
-rw-r--r--drivers/clk/tegra/clk-pll.c30
1 files changed, 29 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 197074a57754..c9d1e5c68dbc 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -77,7 +77,23 @@
77#define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT) 77#define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
78 78
79#define PLLE_SS_CTRL 0x68 79#define PLLE_SS_CTRL 0x68
80#define PLLE_SS_DISABLE (7 << 10) 80#define PLLE_SS_CNTL_BYPASS_SS BIT(10)
81#define PLLE_SS_CNTL_INTERP_RESET BIT(11)
82#define PLLE_SS_CNTL_SSC_BYP BIT(12)
83#define PLLE_SS_CNTL_CENTER BIT(14)
84#define PLLE_SS_CNTL_INVERT BIT(15)
85#define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
86 PLLE_SS_CNTL_SSC_BYP)
87#define PLLE_SS_MAX_MASK 0x1ff
88#define PLLE_SS_MAX_VAL 0x25
89#define PLLE_SS_INC_MASK (0xff << 16)
90#define PLLE_SS_INC_VAL (0x1 << 16)
91#define PLLE_SS_INCINTRV_MASK (0x3f << 24)
92#define PLLE_SS_INCINTRV_VAL (0x20 << 24)
93#define PLLE_SS_COEFFICIENTS_MASK \
94 (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
95#define PLLE_SS_COEFFICIENTS_VAL \
96 (PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL)
81 97
82#define PLLE_AUX_PLLP_SEL BIT(2) 98#define PLLE_AUX_PLLP_SEL BIT(2)
83#define PLLE_AUX_ENABLE_SWCTL BIT(4) 99#define PLLE_AUX_ENABLE_SWCTL BIT(4)
@@ -1217,6 +1233,18 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw)
1217 if (ret < 0) 1233 if (ret < 0)
1218 goto out; 1234 goto out;
1219 1235
1236 val = pll_readl(PLLE_SS_CTRL, pll);
1237 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
1238 val &= ~PLLE_SS_COEFFICIENTS_MASK;
1239 val |= PLLE_SS_COEFFICIENTS_VAL;
1240 pll_writel(val, PLLE_SS_CTRL, pll);
1241 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
1242 pll_writel(val, PLLE_SS_CTRL, pll);
1243 udelay(1);
1244 val &= ~PLLE_SS_CNTL_INTERP_RESET;
1245 pll_writel(val, PLLE_SS_CTRL, pll);
1246 udelay(1);
1247
1220 /* TODO: enable hw control of xusb brick pll */ 1248 /* TODO: enable hw control of xusb brick pll */
1221 1249
1222out: 1250out: