diff options
author | Joseph Lo <josephl@nvidia.com> | 2013-09-26 05:46:23 -0400 |
---|---|---|
committer | Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-11-26 11:46:55 -0500 |
commit | 61792e40ca008d60331bb55df5faaa8fe220ac24 (patch) | |
tree | 67cb680f6ca4764539bf499c705ab4e8ef32e8da | |
parent | 9e036d3ef0b9fcb34acce5a89d1f2157f4f7b4ab (diff) |
clk: tegra124: add suspend/resume function for tegra_cpu_car_ops
Adding suspend/resume function for tegra_cpu_car_ops. We only save and
restore the setting of the clock of CoreSight. Other clocks still need
to be taken care by clock driver.
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
-rw-r--r-- | drivers/clk/tegra/clk-tegra124.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index 345192233871..8af9d3929016 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include "clk.h" | 28 | #include "clk.h" |
29 | #include "clk-id.h" | 29 | #include "clk-id.h" |
30 | 30 | ||
31 | #define CLK_SOURCE_CSITE 0x1d4 | ||
31 | #define CLK_SOURCE_EMC 0x19c | 32 | #define CLK_SOURCE_EMC 0x19c |
32 | #define CLK_SOURCE_XUSB_SS_SRC 0x610 | 33 | #define CLK_SOURCE_XUSB_SS_SRC 0x610 |
33 | 34 | ||
@@ -115,6 +116,12 @@ | |||
115 | /* Tegra CPU clock and reset control regs */ | 116 | /* Tegra CPU clock and reset control regs */ |
116 | #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 | 117 | #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 |
117 | 118 | ||
119 | #ifdef CONFIG_PM_SLEEP | ||
120 | static struct cpu_clk_suspend_context { | ||
121 | u32 clk_csite_src; | ||
122 | } tegra124_cpu_clk_sctx; | ||
123 | #endif | ||
124 | |||
118 | static void __iomem *clk_base; | 125 | static void __iomem *clk_base; |
119 | static void __iomem *pmc_base; | 126 | static void __iomem *pmc_base; |
120 | 127 | ||
@@ -1302,9 +1309,29 @@ static void tegra124_disable_cpu_clock(u32 cpu) | |||
1302 | /* flow controller would take care in the power sequence. */ | 1309 | /* flow controller would take care in the power sequence. */ |
1303 | } | 1310 | } |
1304 | 1311 | ||
1312 | #ifdef CONFIG_PM_SLEEP | ||
1313 | static void tegra124_cpu_clock_suspend(void) | ||
1314 | { | ||
1315 | /* switch coresite to clk_m, save off original source */ | ||
1316 | tegra124_cpu_clk_sctx.clk_csite_src = | ||
1317 | readl(clk_base + CLK_SOURCE_CSITE); | ||
1318 | writel(3 << 30, clk_base + CLK_SOURCE_CSITE); | ||
1319 | } | ||
1320 | |||
1321 | static void tegra124_cpu_clock_resume(void) | ||
1322 | { | ||
1323 | writel(tegra124_cpu_clk_sctx.clk_csite_src, | ||
1324 | clk_base + CLK_SOURCE_CSITE); | ||
1325 | } | ||
1326 | #endif | ||
1327 | |||
1305 | static struct tegra_cpu_car_ops tegra124_cpu_car_ops = { | 1328 | static struct tegra_cpu_car_ops tegra124_cpu_car_ops = { |
1306 | .wait_for_reset = tegra124_wait_cpu_in_reset, | 1329 | .wait_for_reset = tegra124_wait_cpu_in_reset, |
1307 | .disable_clock = tegra124_disable_cpu_clock, | 1330 | .disable_clock = tegra124_disable_cpu_clock, |
1331 | #ifdef CONFIG_PM_SLEEP | ||
1332 | .suspend = tegra124_cpu_clock_suspend, | ||
1333 | .resume = tegra124_cpu_clock_resume, | ||
1334 | #endif | ||
1308 | }; | 1335 | }; |
1309 | 1336 | ||
1310 | static const struct of_device_id pmc_match[] __initconst = { | 1337 | static const struct of_device_id pmc_match[] __initconst = { |