diff options
author | Thierry Reding <thierry.reding@gmail.com> | 2013-10-02 17:12:40 -0400 |
---|---|---|
committer | Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-11-26 11:43:59 -0500 |
commit | f67a8d21e63876a79f9f94b734049e789d594c7b (patch) | |
tree | ed0b0f5d3f4686483e1c315e3b90eb1f08cb28c8 | |
parent | 642fb0cf517173948684122403d73513c8c8b033 (diff) |
clk: tegra114: Rename gr_2d/gr_3d to gr2d/gr3d
These clocks were named gr2d and gr3d on Tegra20 and Tegra30, so use the
same names on Tegra114 for consistency.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
-rw-r--r-- | drivers/clk/tegra/clk-tegra114.c | 8 | ||||
-rw-r--r-- | include/dt-bindings/clock/tegra114-car.h | 4 |
2 files changed, 6 insertions, 6 deletions
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index 9b8c938477de..2471742d68de 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c | |||
@@ -1846,8 +1846,8 @@ static struct tegra_periph_init_data tegra_periph_clk_list[] = { | |||
1846 | TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, TEGRA114_CLK_UARTB), | 1846 | TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, TEGRA114_CLK_UARTB), |
1847 | TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, TEGRA114_CLK_UARTC), | 1847 | TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, TEGRA114_CLK_UARTC), |
1848 | TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, TEGRA114_CLK_UARTD), | 1848 | TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, TEGRA114_CLK_UARTD), |
1849 | TEGRA_INIT_DATA_INT8("3d", NULL, "3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, &periph_l_regs, 0, TEGRA114_CLK_GR_3D), | 1849 | TEGRA_INIT_DATA_INT8("3d", NULL, "3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, &periph_l_regs, 0, TEGRA114_CLK_GR3D), |
1850 | TEGRA_INIT_DATA_INT8("2d", NULL, "2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, &periph_l_regs, 0, TEGRA114_CLK_GR_2D), | 1850 | TEGRA_INIT_DATA_INT8("2d", NULL, "2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, &periph_l_regs, 0, TEGRA114_CLK_GR2D), |
1851 | TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_VI_SENSOR), | 1851 | TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_VI_SENSOR), |
1852 | TEGRA_INIT_DATA_INT8("vi", "vi", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, &periph_l_regs, 0, TEGRA114_CLK_VI), | 1852 | TEGRA_INIT_DATA_INT8("vi", "vi", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, &periph_l_regs, 0, TEGRA114_CLK_VI), |
1853 | TEGRA_INIT_DATA_INT8("epp", NULL, "epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, TEGRA114_CLK_EPP), | 1853 | TEGRA_INIT_DATA_INT8("epp", NULL, "epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, TEGRA114_CLK_EPP), |
@@ -2186,8 +2186,8 @@ static struct tegra_clk_init_table init_table[] __initdata = { | |||
2186 | {TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0}, | 2186 | {TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0}, |
2187 | {TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1}, | 2187 | {TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1}, |
2188 | {TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1}, | 2188 | {TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1}, |
2189 | {TEGRA114_CLK_GR_2D, TEGRA114_CLK_PLL_C2, 300000000, 0}, | 2189 | {TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0}, |
2190 | {TEGRA114_CLK_GR_3D, TEGRA114_CLK_PLL_C2, 300000000, 0}, | 2190 | {TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0}, |
2191 | 2191 | ||
2192 | /* This MUST be the last entry. */ | 2192 | /* This MUST be the last entry. */ |
2193 | {TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0}, | 2193 | {TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0}, |
diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h index 5d4b90a2c023..6d0d8d8ef31e 100644 --- a/include/dt-bindings/clock/tegra114-car.h +++ b/include/dt-bindings/clock/tegra114-car.h | |||
@@ -37,10 +37,10 @@ | |||
37 | #define TEGRA114_CLK_I2S2 18 | 37 | #define TEGRA114_CLK_I2S2 18 |
38 | #define TEGRA114_CLK_EPP 19 | 38 | #define TEGRA114_CLK_EPP 19 |
39 | /* 20 (register bit affects vi and vi_sensor) */ | 39 | /* 20 (register bit affects vi and vi_sensor) */ |
40 | #define TEGRA114_CLK_GR_2D 21 | 40 | #define TEGRA114_CLK_GR2D 21 |
41 | #define TEGRA114_CLK_USBD 22 | 41 | #define TEGRA114_CLK_USBD 22 |
42 | #define TEGRA114_CLK_ISP 23 | 42 | #define TEGRA114_CLK_ISP 23 |
43 | #define TEGRA114_CLK_GR_3D 24 | 43 | #define TEGRA114_CLK_GR3D 24 |
44 | /* 25 */ | 44 | /* 25 */ |
45 | #define TEGRA114_CLK_DISP2 26 | 45 | #define TEGRA114_CLK_DISP2 26 |
46 | #define TEGRA114_CLK_DISP1 27 | 46 | #define TEGRA114_CLK_DISP1 27 |