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authorPeter De Schrijver <pdeschrijver@nvidia.com>2013-09-03 08:46:01 -0400
committerPeter De Schrijver <pdeschrijver@nvidia.com>2013-11-26 11:46:50 -0500
commita7c8485a0ebbdce303c6709e208bb4fd08aff8ad (patch)
tree4a9355eade04167cacabb23134e11d038cafebbb
parentde4f30fd8403cd67449fbb9dc06a3d898fb9f10c (diff)
clk: tegra: introduce common gen4 super clock
Introduce a common function which performs super clock initialization for Tegra114 and beyond. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Diffstat
-rw-r--r--drivers/clk/tegra/Makefile1
-rw-r--r--drivers/clk/tegra/clk-tegra-super-gen4.c149
-rw-r--r--drivers/clk/tegra/clk-tegra114.c76
-rw-r--r--drivers/clk/tegra/clk.h3
4 files changed, 155 insertions, 74 deletions
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index a02e9a95a4cb..2d837411dfed 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -10,6 +10,7 @@ obj-y += clk-tegra-audio.o
10obj-y += clk-tegra-periph.o 10obj-y += clk-tegra-periph.o
11obj-y += clk-tegra-pmc.o 11obj-y += clk-tegra-pmc.o
12obj-y += clk-tegra-fixed.o 12obj-y += clk-tegra-fixed.o
13obj-y += clk-tegra-super-gen4.o
13obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o 14obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o
14obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o 15obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o
15obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o 16obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o
diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c
new file mode 100644
index 000000000000..05dce4aa2c11
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra-super-gen4.c
@@ -0,0 +1,149 @@
1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/clk-provider.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
22#include <linux/delay.h>
23#include <linux/export.h>
24#include <linux/clk/tegra.h>
25
26#include "clk.h"
27#include "clk-id.h"
28
29#define PLLX_BASE 0xe0
30#define PLLX_MISC 0xe4
31#define PLLX_MISC2 0x514
32#define PLLX_MISC3 0x518
33
34#define CCLKG_BURST_POLICY 0x368
35#define CCLKLP_BURST_POLICY 0x370
36#define SCLK_BURST_POLICY 0x028
37#define SYSTEM_CLK_RATE 0x030
38
39static DEFINE_SPINLOCK(sysrate_lock);
40
41static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
42 "pll_p", "pll_p_out2", "unused",
43 "clk_32k", "pll_m_out1" };
44
45static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
46 "pll_p", "pll_p_out4", "unused",
47 "unused", "pll_x" };
48
49static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
50 "pll_p", "pll_p_out4", "unused",
51 "unused", "pll_x", "pll_x_out0" };
52
53static void __init tegra_sclk_init(void __iomem *clk_base,
54 struct tegra_clk *tegra_clks)
55{
56 struct clk *clk;
57 struct clk **dt_clk;
58
59 /* SCLK */
60 dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks);
61 if (dt_clk) {
62 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
63 ARRAY_SIZE(sclk_parents),
64 CLK_SET_RATE_PARENT,
65 clk_base + SCLK_BURST_POLICY,
66 0, 4, 0, 0, NULL);
67 *dt_clk = clk;
68 }
69
70 /* HCLK */
71 dt_clk = tegra_lookup_dt_id(tegra_clk_hclk, tegra_clks);
72 if (dt_clk) {
73 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
74 clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
75 &sysrate_lock);
76 clk = clk_register_gate(NULL, "hclk", "hclk_div",
77 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
78 clk_base + SYSTEM_CLK_RATE,
79 7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
80 *dt_clk = clk;
81 }
82
83 /* PCLK */
84 dt_clk = tegra_lookup_dt_id(tegra_clk_pclk, tegra_clks);
85 if (!dt_clk)
86 return;
87
88 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
89 clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
90 &sysrate_lock);
91 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT |
92 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE,
93 3, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
94 *dt_clk = clk;
95}
96
97void __init tegra_super_clk_gen4_init(void __iomem *clk_base,
98 void __iomem *pmc_base,
99 struct tegra_clk *tegra_clks,
100 struct tegra_clk_pll_params *params)
101{
102 struct clk *clk;
103 struct clk **dt_clk;
104
105 /* CCLKG */
106 dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_g, tegra_clks);
107 if (dt_clk) {
108 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents,
109 ARRAY_SIZE(cclk_g_parents),
110 CLK_SET_RATE_PARENT,
111 clk_base + CCLKG_BURST_POLICY,
112 0, 4, 0, 0, NULL);
113 *dt_clk = clk;
114 }
115
116 /* CCLKLP */
117 dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_lp, tegra_clks);
118 if (dt_clk) {
119 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
120 ARRAY_SIZE(cclk_lp_parents),
121 CLK_SET_RATE_PARENT,
122 clk_base + CCLKLP_BURST_POLICY,
123 0, 4, 8, 9, NULL);
124 *dt_clk = clk;
125 }
126
127 tegra_sclk_init(clk_base, tegra_clks);
128
129#if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC)
130 /* PLLX */
131 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_x, tegra_clks);
132 if (!dt_clk)
133 return;
134
135 clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base,
136 pmc_base, CLK_IGNORE_UNUSED, params, NULL);
137 *dt_clk = clk;
138
139 /* PLLX_OUT0 */
140
141 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_x_out0, tegra_clks);
142 if (!dt_clk)
143 return;
144 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
145 CLK_SET_RATE_PARENT, 1, 2);
146 *dt_clk = clk;
147#endif
148}
149
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 046dbed0c2c5..0b8c9af5bff3 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -114,9 +114,6 @@
114#define PLLXC_SW_MAX_P 6 114#define PLLXC_SW_MAX_P 6
115 115
116#define CCLKG_BURST_POLICY 0x368 116#define CCLKG_BURST_POLICY 0x368
117#define CCLKLP_BURST_POLICY 0x370
118#define SCLK_BURST_POLICY 0x028
119#define SYSTEM_CLK_RATE 0x030
120 117
121#define UTMIP_PLL_CFG2 0x488 118#define UTMIP_PLL_CFG2 0x488
122#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6) 119#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
@@ -170,7 +167,6 @@ static DEFINE_SPINLOCK(pll_d_lock);
170static DEFINE_SPINLOCK(pll_d2_lock); 167static DEFINE_SPINLOCK(pll_d2_lock);
171static DEFINE_SPINLOCK(pll_u_lock); 168static DEFINE_SPINLOCK(pll_u_lock);
172static DEFINE_SPINLOCK(pll_re_lock); 169static DEFINE_SPINLOCK(pll_re_lock);
173static DEFINE_SPINLOCK(sysrate_lock);
174 170
175static struct div_nmp pllxc_nmp = { 171static struct div_nmp pllxc_nmp = {
176 .divm_shift = 0, 172 .divm_shift = 0,
@@ -1113,16 +1109,6 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
1113 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m", 1109 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
1114 CLK_SET_RATE_PARENT, 1, 1); 1110 CLK_SET_RATE_PARENT, 1, 1);
1115 1111
1116 /* PLLX */
1117 clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base,
1118 pmc, CLK_IGNORE_UNUSED, &pll_x_params, NULL);
1119 clks[TEGRA114_CLK_PLL_X] = clk;
1120
1121 /* PLLX_OUT0 */
1122 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
1123 CLK_SET_RATE_PARENT, 1, 2);
1124 clks[TEGRA114_CLK_PLL_X_OUT0] = clk;
1125
1126 /* PLLU */ 1112 /* PLLU */
1127 val = readl(clk_base + pll_u_params.base_reg); 1113 val = readl(clk_base + pll_u_params.base_reg);
1128 val &= ~BIT(24); /* disable PLLU_OVERRIDE */ 1114 val &= ~BIT(24); /* disable PLLU_OVERRIDE */
@@ -1191,65 +1177,6 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
1191 clks[TEGRA114_CLK_PLL_E_OUT0] = clk; 1177 clks[TEGRA114_CLK_PLL_E_OUT0] = clk;
1192} 1178}
1193 1179
1194static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
1195 "pll_p", "pll_p_out2", "unused",
1196 "clk_32k", "pll_m_out1" };
1197
1198static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1199 "pll_p", "pll_p_out4", "unused",
1200 "unused", "pll_x" };
1201
1202static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1203 "pll_p", "pll_p_out4", "unused",
1204 "unused", "pll_x", "pll_x_out0" };
1205
1206static void __init tegra114_super_clk_init(void __iomem *clk_base)
1207{
1208 struct clk *clk;
1209
1210 /* CCLKG */
1211 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents,
1212 ARRAY_SIZE(cclk_g_parents),
1213 CLK_SET_RATE_PARENT,
1214 clk_base + CCLKG_BURST_POLICY,
1215 0, 4, 0, 0, NULL);
1216 clks[TEGRA114_CLK_CCLK_G] = clk;
1217
1218 /* CCLKLP */
1219 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
1220 ARRAY_SIZE(cclk_lp_parents),
1221 CLK_SET_RATE_PARENT,
1222 clk_base + CCLKLP_BURST_POLICY,
1223 0, 4, 8, 9, NULL);
1224 clks[TEGRA114_CLK_CCLK_LP] = clk;
1225
1226 /* SCLK */
1227 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
1228 ARRAY_SIZE(sclk_parents),
1229 CLK_SET_RATE_PARENT,
1230 clk_base + SCLK_BURST_POLICY,
1231 0, 4, 0, 0, NULL);
1232 clks[TEGRA114_CLK_SCLK] = clk;
1233
1234 /* HCLK */
1235 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
1236 clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
1237 &sysrate_lock);
1238 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT |
1239 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE,
1240 7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
1241 clks[TEGRA114_CLK_HCLK] = clk;
1242
1243 /* PCLK */
1244 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
1245 clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
1246 &sysrate_lock);
1247 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT |
1248 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE,
1249 3, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
1250 clks[TEGRA114_CLK_PCLK] = clk;
1251}
1252
1253static __init void tegra114_periph_clk_init(void __iomem *clk_base, 1180static __init void tegra114_periph_clk_init(void __iomem *clk_base,
1254 void __iomem *pmc_base) 1181 void __iomem *pmc_base)
1255{ 1182{
@@ -1540,7 +1467,8 @@ static void __init tegra114_clock_init(struct device_node *np)
1540 tegra114_periph_clk_init(clk_base, pmc_base); 1467 tegra114_periph_clk_init(clk_base, pmc_base);
1541 tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks, &pll_a_params); 1468 tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks, &pll_a_params);
1542 tegra_pmc_clk_init(pmc_base, tegra114_clks); 1469 tegra_pmc_clk_init(pmc_base, tegra114_clks);
1543 tegra114_super_clk_init(clk_base); 1470 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
1471 &pll_x_params);
1544 1472
1545 tegra_add_of_provider(np); 1473 tegra_add_of_provider(np);
1546 tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); 1474 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 2d4881763902..05abfc5fdff8 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -610,6 +610,9 @@ int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *tegra_clks,
610 unsigned long *input_freqs, int num, 610 unsigned long *input_freqs, int num,
611 unsigned long *osc_freq, 611 unsigned long *osc_freq,
612 unsigned long *pll_ref_freq); 612 unsigned long *pll_ref_freq);
613void tegra_super_clk_gen4_init(void __iomem *clk_base,
614 void __iomem *pmc_base, struct tegra_clk *tegra_clks,
615 struct tegra_clk_pll_params *pll_params);
613 616
614void tegra114_clock_tune_cpu_trimmers_high(void); 617void tegra114_clock_tune_cpu_trimmers_high(void);
615void tegra114_clock_tune_cpu_trimmers_low(void); 618void tegra114_clock_tune_cpu_trimmers_low(void);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-20 18:30:09 -0400