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-rw-r--r--drivers/net/wireless/rt2x00/Kconfig97
-rw-r--r--drivers/net/wireless/rt2x00/Makefile1
-rw-r--r--drivers/net/wireless/rt2x00/rt2400pci.c481
-rw-r--r--drivers/net/wireless/rt2x00/rt2400pci.h6
-rw-r--r--drivers/net/wireless/rt2x00/rt2500pci.c489
-rw-r--r--drivers/net/wireless/rt2x00/rt2500pci.h4
-rw-r--r--drivers/net/wireless/rt2x00/rt2500usb.c264
-rw-r--r--drivers/net/wireless/rt2x00/rt2800.h568
-rw-r--r--drivers/net/wireless/rt2x00/rt2800lib.c1896
-rw-r--r--drivers/net/wireless/rt2x00/rt2800lib.h35
-rw-r--r--drivers/net/wireless/rt2x00/rt2800pci.c893
-rw-r--r--drivers/net/wireless/rt2x00/rt2800pci.h12
-rw-r--r--drivers/net/wireless/rt2x00/rt2800usb.c943
-rw-r--r--drivers/net/wireless/rt2x00/rt2800usb.h4
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00.h345
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00config.c141
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00crypto.c23
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00debug.c74
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00dev.c469
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00dump.h2
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00firmware.c6
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00ht.c125
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00lib.h107
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00link.c78
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00mac.c237
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00pci.c43
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00pci.h19
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00queue.c665
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00queue.h167
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00reg.h6
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00soc.c6
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00usb.c520
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00usb.h49
-rw-r--r--drivers/net/wireless/rt2x00/rt61pci.c573
-rw-r--r--drivers/net/wireless/rt2x00/rt61pci.h64
-rw-r--r--drivers/net/wireless/rt2x00/rt73usb.c445
-rw-r--r--drivers/net/wireless/rt2x00/rt73usb.h38
37 files changed, 6668 insertions, 3227 deletions
diff --git a/drivers/net/wireless/rt2x00/Kconfig b/drivers/net/wireless/rt2x00/Kconfig
index eea1ef2f502b..b2f8b8fd4d2d 100644
--- a/drivers/net/wireless/rt2x00/Kconfig
+++ b/drivers/net/wireless/rt2x00/Kconfig
@@ -53,51 +53,36 @@ config RT61PCI
53 53
54 When compiled as a module, this driver will be called rt61pci. 54 When compiled as a module, this driver will be called rt61pci.
55 55
56config RT2800PCI_PCI
57 boolean
58 depends on PCI
59 default y
60
61config RT2800PCI_SOC
62 boolean
63 depends on RALINK_RT288X || RALINK_RT305X
64 default y
65
66config RT2800PCI 56config RT2800PCI
67 tristate "Ralink rt28xx/rt30xx/rt35xx (PCI/PCIe/PCMCIA) support (EXPERIMENTAL)" 57 tristate "Ralink rt27xx/rt28xx/rt30xx (PCI/PCIe/PCMCIA) support"
68 depends on (RT2800PCI_PCI || RT2800PCI_SOC) && EXPERIMENTAL 58 depends on PCI || RALINK_RT288X || RALINK_RT305X
69 select RT2800_LIB 59 select RT2800_LIB
70 select RT2X00_LIB_PCI if RT2800PCI_PCI 60 select RT2X00_LIB_PCI if PCI
71 select RT2X00_LIB_SOC if RT2800PCI_SOC 61 select RT2X00_LIB_SOC if RALINK_RT288X || RALINK_RT305X
72 select RT2X00_LIB_HT
73 select RT2X00_LIB_FIRMWARE 62 select RT2X00_LIB_FIRMWARE
74 select RT2X00_LIB_CRYPTO 63 select RT2X00_LIB_CRYPTO
75 select CRC_CCITT 64 select CRC_CCITT
76 select EEPROM_93CX6 65 select EEPROM_93CX6
77 ---help--- 66 ---help---
78 This adds support for rt2800/rt3000/rt3500 wireless chipset family. 67 This adds support for rt27xx/rt28xx/rt30xx wireless chipset family.
79 Supported chips: RT2760, RT2790, RT2860, RT2880, RT2890 & RT3052 68 Supported chips: RT2760, RT2790, RT2860, RT2880, RT2890, RT3052,
80 69 RT3090, RT3091 & RT3092
81 This driver is non-functional at the moment and is intended for
82 developers.
83 70
84 When compiled as a module, this driver will be called "rt2800pci.ko". 71 When compiled as a module, this driver will be called "rt2800pci.ko".
85 72
86if RT2800PCI 73if RT2800PCI
87 74
88config RT2800PCI_RT30XX 75config RT2800PCI_RT33XX
89 bool "rt2800pci - Include support for rt30xx (PCI/PCIe/PCMCIA) devices" 76 bool "rt2800pci - Include support for rt33xx devices"
90 default y 77 default y
91 ---help--- 78 ---help---
92 This adds support for rt30xx wireless chipset family to the 79 This adds support for rt33xx wireless chipset family to the
93 rt2800pci driver. 80 rt2800pci driver.
94 Supported chips: RT3090, RT3091 & RT3092 81 Supported chips: RT3390
95
96 Support for these devices is non-functional at the moment and is
97 intended for testers and developers.
98 82
99config RT2800PCI_RT35XX 83config RT2800PCI_RT35XX
100 bool "rt2800pci - Include support for rt35xx (PCI/PCIe/PCMCIA) devices" 84 bool "rt2800pci - Include support for rt35xx devices (EXPERIMENTAL)"
85 depends on EXPERIMENTAL
101 default n 86 default n
102 ---help--- 87 ---help---
103 This adds support for rt35xx wireless chipset family to the 88 This adds support for rt35xx wireless chipset family to the
@@ -107,6 +92,15 @@ config RT2800PCI_RT35XX
107 Support for these devices is non-functional at the moment and is 92 Support for these devices is non-functional at the moment and is
108 intended for testers and developers. 93 intended for testers and developers.
109 94
95config RT2800PCI_RT53XX
96 bool "rt2800pci - Include support for rt53xx devices (EXPERIMENTAL)"
97 depends on EXPERIMENTAL
98 default y
99 ---help---
100 This adds support for rt53xx wireless chipset family to the
101 rt2800pci driver.
102 Supported chips: RT5390
103
110endif 104endif
111 105
112config RT2500USB 106config RT2500USB
@@ -134,39 +128,32 @@ config RT73USB
134 When compiled as a module, this driver will be called rt73usb. 128 When compiled as a module, this driver will be called rt73usb.
135 129
136config RT2800USB 130config RT2800USB
137 tristate "Ralink rt2800 (USB) support (EXPERIMENTAL)" 131 tristate "Ralink rt27xx/rt28xx/rt30xx (USB) support"
138 depends on USB && EXPERIMENTAL 132 depends on USB
139 select RT2800_LIB 133 select RT2800_LIB
140 select RT2X00_LIB_USB 134 select RT2X00_LIB_USB
141 select RT2X00_LIB_HT
142 select RT2X00_LIB_FIRMWARE 135 select RT2X00_LIB_FIRMWARE
143 select RT2X00_LIB_CRYPTO 136 select RT2X00_LIB_CRYPTO
144 select CRC_CCITT 137 select CRC_CCITT
145 ---help--- 138 ---help---
146 This adds experimental support for rt2800 wireless chipset family. 139 This adds support for rt27xx/rt28xx/rt30xx wireless chipset family.
147 Supported chips: RT2770, RT2870 & RT3070. 140 Supported chips: RT2770, RT2870 & RT3070, RT3071 & RT3072
148
149 Known issues:
150 - support for RT2870 chips doesn't work with 802.11n APs yet
151 - support for RT3070 chips is non-functional at the moment
152 141
153 When compiled as a module, this driver will be called "rt2800usb.ko". 142 When compiled as a module, this driver will be called "rt2800usb.ko".
154 143
155if RT2800USB 144if RT2800USB
156 145
157config RT2800USB_RT30XX 146config RT2800USB_RT33XX
158 bool "rt2800usb - Include support for rt30xx (USB) devices" 147 bool "rt2800usb - Include support for rt33xx devices"
159 default y 148 default y
160 ---help--- 149 ---help---
161 This adds support for rt30xx wireless chipset family to the 150 This adds support for rt33xx wireless chipset family to the
162 rt2800usb driver. 151 rt2800usb driver.
163 Supported chips: RT3070, RT3071 & RT3072 152 Supported chips: RT3370
164
165 Support for these devices is non-functional at the moment and is
166 intended for testers and developers.
167 153
168config RT2800USB_RT35XX 154config RT2800USB_RT35XX
169 bool "rt2800usb - Include support for rt35xx (USB) devices" 155 bool "rt2800usb - Include support for rt35xx devices (EXPERIMENTAL)"
156 depends on EXPERIMENTAL
170 default n 157 default n
171 ---help--- 158 ---help---
172 This adds support for rt35xx wireless chipset family to the 159 This adds support for rt35xx wireless chipset family to the
@@ -176,13 +163,21 @@ config RT2800USB_RT35XX
176 Support for these devices is non-functional at the moment and is 163 Support for these devices is non-functional at the moment and is
177 intended for testers and developers. 164 intended for testers and developers.
178 165
166config RT2800USB_RT53XX
167 bool "rt2800usb - Include support for rt53xx devices (EXPERIMENTAL)"
168 depends on EXPERIMENTAL
169 ---help---
170 This adds support for rt53xx wireless chipset family to the
171 rt2800pci driver.
172 Supported chips: RT5370
173
179config RT2800USB_UNKNOWN 174config RT2800USB_UNKNOWN
180 bool "rt2800usb - Include support for unknown (USB) devices" 175 bool "rt2800usb - Include support for unknown (USB) devices"
181 default n 176 default n
182 ---help--- 177 ---help---
183 This adds support for rt2800 family devices that are known to 178 This adds support for rt2800usb devices that are known to
184 have a rt2800 family chipset, but for which the exact chipset 179 have a rt28xx family compatible chipset, but for which the exact
185 is unknown. 180 chipset is unknown.
186 181
187 Support status for these devices is unknown, and enabling these 182 Support status for these devices is unknown, and enabling these
188 devices may or may not work. 183 devices may or may not work.
@@ -207,9 +202,6 @@ config RT2X00_LIB_USB
207config RT2X00_LIB 202config RT2X00_LIB
208 tristate 203 tristate
209 204
210config RT2X00_LIB_HT
211 boolean
212
213config RT2X00_LIB_FIRMWARE 205config RT2X00_LIB_FIRMWARE
214 boolean 206 boolean
215 select FW_LOADER 207 select FW_LOADER
@@ -221,9 +213,6 @@ config RT2X00_LIB_LEDS
221 boolean 213 boolean
222 default y if (RT2X00_LIB=y && LEDS_CLASS=y) || (RT2X00_LIB=m && LEDS_CLASS!=n) 214 default y if (RT2X00_LIB=y && LEDS_CLASS=y) || (RT2X00_LIB=m && LEDS_CLASS!=n)
223 215
224comment "rt2x00 leds support disabled due to modularized LEDS_CLASS and built-in rt2x00"
225 depends on RT2X00_LIB=y && LEDS_CLASS=m
226
227config RT2X00_LIB_DEBUGFS 216config RT2X00_LIB_DEBUGFS
228 bool "Ralink debugfs support" 217 bool "Ralink debugfs support"
229 depends on RT2X00_LIB && MAC80211_DEBUGFS 218 depends on RT2X00_LIB && MAC80211_DEBUGFS
diff --git a/drivers/net/wireless/rt2x00/Makefile b/drivers/net/wireless/rt2x00/Makefile
index 971339858297..349d5b8284a4 100644
--- a/drivers/net/wireless/rt2x00/Makefile
+++ b/drivers/net/wireless/rt2x00/Makefile
@@ -7,7 +7,6 @@ rt2x00lib-$(CONFIG_RT2X00_LIB_DEBUGFS) += rt2x00debug.o
7rt2x00lib-$(CONFIG_RT2X00_LIB_CRYPTO) += rt2x00crypto.o 7rt2x00lib-$(CONFIG_RT2X00_LIB_CRYPTO) += rt2x00crypto.o
8rt2x00lib-$(CONFIG_RT2X00_LIB_FIRMWARE) += rt2x00firmware.o 8rt2x00lib-$(CONFIG_RT2X00_LIB_FIRMWARE) += rt2x00firmware.o
9rt2x00lib-$(CONFIG_RT2X00_LIB_LEDS) += rt2x00leds.o 9rt2x00lib-$(CONFIG_RT2X00_LIB_LEDS) += rt2x00leds.o
10rt2x00lib-$(CONFIG_RT2X00_LIB_HT) += rt2x00ht.o
11 10
12obj-$(CONFIG_RT2X00_LIB) += rt2x00lib.o 11obj-$(CONFIG_RT2X00_LIB) += rt2x00lib.o
13obj-$(CONFIG_RT2X00_LIB_PCI) += rt2x00pci.o 12obj-$(CONFIG_RT2X00_LIB_PCI) += rt2x00pci.o
diff --git a/drivers/net/wireless/rt2x00/rt2400pci.c b/drivers/net/wireless/rt2x00/rt2400pci.c
index 5063e01410e5..937f9e8bf05f 100644
--- a/drivers/net/wireless/rt2x00/rt2400pci.c
+++ b/drivers/net/wireless/rt2x00/rt2400pci.c
@@ -46,7 +46,7 @@
46 * These indirect registers work with busy bits, 46 * These indirect registers work with busy bits,
47 * and we will try maximal REGISTER_BUSY_COUNT times to access 47 * and we will try maximal REGISTER_BUSY_COUNT times to access
48 * the register while taking a REGISTER_BUSY_DELAY us delay 48 * the register while taking a REGISTER_BUSY_DELAY us delay
49 * between each attampt. When the busy bit is still set at that time, 49 * between each attempt. When the busy bit is still set at that time,
50 * the access attempt is considered to have failed, 50 * the access attempt is considered to have failed,
51 * and we will print an error. 51 * and we will print an error.
52 */ 52 */
@@ -305,9 +305,7 @@ static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
305 * Enable synchronisation. 305 * Enable synchronisation.
306 */ 306 */
307 rt2x00pci_register_read(rt2x00dev, CSR14, &reg); 307 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
308 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
309 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync); 308 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
310 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
311 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 309 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
312 } 310 }
313 311
@@ -321,7 +319,8 @@ static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
321} 319}
322 320
323static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev, 321static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
324 struct rt2x00lib_erp *erp) 322 struct rt2x00lib_erp *erp,
323 u32 changed)
325{ 324{
326 int preamble_mask; 325 int preamble_mask;
327 u32 reg; 326 u32 reg;
@@ -329,59 +328,72 @@ static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
329 /* 328 /*
330 * When short preamble is enabled, we should set bit 0x08 329 * When short preamble is enabled, we should set bit 0x08
331 */ 330 */
332 preamble_mask = erp->short_preamble << 3; 331 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
333 332 preamble_mask = erp->short_preamble << 3;
334 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg); 333
335 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x1ff); 334 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
336 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0x13a); 335 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x1ff);
337 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER); 336 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0x13a);
338 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1); 337 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
339 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg); 338 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
340 339 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
341 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg); 340
342 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00); 341 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
343 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04); 342 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
344 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10)); 343 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
345 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg); 344 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
346 345 GET_DURATION(ACK_SIZE, 10));
347 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg); 346 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
348 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask); 347
349 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04); 348 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
350 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20)); 349 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
351 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg); 350 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
352 351 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
353 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg); 352 GET_DURATION(ACK_SIZE, 20));
354 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask); 353 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
355 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04); 354
356 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55)); 355 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
357 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg); 356 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
358 357 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
359 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg); 358 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
360 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask); 359 GET_DURATION(ACK_SIZE, 55));
361 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84); 360 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
362 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110)); 361
363 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg); 362 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
364 363 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
365 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates); 364 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
365 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
366 GET_DURATION(ACK_SIZE, 110));
367 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
368 }
366 369
367 rt2x00pci_register_read(rt2x00dev, CSR11, &reg); 370 if (changed & BSS_CHANGED_BASIC_RATES)
368 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time); 371 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
369 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
370 372
371 rt2x00pci_register_read(rt2x00dev, CSR12, &reg); 373 if (changed & BSS_CHANGED_ERP_SLOT) {
372 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, erp->beacon_int * 16); 374 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
373 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, erp->beacon_int * 16); 375 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
374 rt2x00pci_register_write(rt2x00dev, CSR12, reg); 376 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
375 377
376 rt2x00pci_register_read(rt2x00dev, CSR18, &reg); 378 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
377 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs); 379 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
378 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs); 380 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
379 rt2x00pci_register_write(rt2x00dev, CSR18, reg); 381 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
380 382
381 rt2x00pci_register_read(rt2x00dev, CSR19, &reg); 383 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
382 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs); 384 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
383 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs); 385 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
384 rt2x00pci_register_write(rt2x00dev, CSR19, reg); 386 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
387 }
388
389 if (changed & BSS_CHANGED_BEACON_INT) {
390 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
391 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
392 erp->beacon_int * 16);
393 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
394 erp->beacon_int * 16);
395 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
396 }
385} 397}
386 398
387static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev, 399static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
@@ -619,6 +631,98 @@ static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
619} 631}
620 632
621/* 633/*
634 * Queue handlers.
635 */
636static void rt2400pci_start_queue(struct data_queue *queue)
637{
638 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
639 u32 reg;
640
641 switch (queue->qid) {
642 case QID_RX:
643 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
644 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
645 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
646 break;
647 case QID_BEACON:
648 /*
649 * Allow the tbtt tasklet to be scheduled.
650 */
651 tasklet_enable(&rt2x00dev->tbtt_tasklet);
652
653 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
654 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
655 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
656 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
657 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
658 break;
659 default:
660 break;
661 }
662}
663
664static void rt2400pci_kick_queue(struct data_queue *queue)
665{
666 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
667 u32 reg;
668
669 switch (queue->qid) {
670 case QID_AC_VO:
671 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
672 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
673 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
674 break;
675 case QID_AC_VI:
676 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
677 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
678 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
679 break;
680 case QID_ATIM:
681 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
682 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
683 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
684 break;
685 default:
686 break;
687 }
688}
689
690static void rt2400pci_stop_queue(struct data_queue *queue)
691{
692 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
693 u32 reg;
694
695 switch (queue->qid) {
696 case QID_AC_VO:
697 case QID_AC_VI:
698 case QID_ATIM:
699 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
700 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
701 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
702 break;
703 case QID_RX:
704 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
705 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
706 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
707 break;
708 case QID_BEACON:
709 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
710 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
711 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
712 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
713 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
714
715 /*
716 * Wait for possibly running tbtt tasklets.
717 */
718 tasklet_disable(&rt2x00dev->tbtt_tasklet);
719 break;
720 default:
721 break;
722 }
723}
724
725/*
622 * Initialization functions. 726 * Initialization functions.
623 */ 727 */
624static bool rt2400pci_get_entry_state(struct queue_entry *entry) 728static bool rt2400pci_get_entry_state(struct queue_entry *entry)
@@ -675,7 +779,7 @@ static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
675 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg); 779 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
676 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); 780 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
677 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); 781 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
678 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit); 782 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
679 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); 783 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
680 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg); 784 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
681 785
@@ -691,13 +795,13 @@ static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
691 entry_priv->desc_dma); 795 entry_priv->desc_dma);
692 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); 796 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
693 797
694 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data; 798 entry_priv = rt2x00dev->atim->entries[0].priv_data;
695 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg); 799 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
696 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER, 800 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
697 entry_priv->desc_dma); 801 entry_priv->desc_dma);
698 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); 802 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
699 803
700 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data; 804 entry_priv = rt2x00dev->bcn->entries[0].priv_data;
701 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg); 805 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
702 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER, 806 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
703 entry_priv->desc_dma); 807 entry_priv->desc_dma);
@@ -864,24 +968,12 @@ static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
864/* 968/*
865 * Device state switch handlers. 969 * Device state switch handlers.
866 */ 970 */
867static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
868 enum dev_state state)
869{
870 u32 reg;
871
872 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
873 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
874 (state == STATE_RADIO_RX_OFF) ||
875 (state == STATE_RADIO_RX_OFF_LINK));
876 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
877}
878
879static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev, 971static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
880 enum dev_state state) 972 enum dev_state state)
881{ 973{
882 int mask = (state == STATE_RADIO_IRQ_OFF) || 974 int mask = (state == STATE_RADIO_IRQ_OFF);
883 (state == STATE_RADIO_IRQ_OFF_ISR);
884 u32 reg; 975 u32 reg;
976 unsigned long flags;
885 977
886 /* 978 /*
887 * When interrupts are being enabled, the interrupt registers 979 * When interrupts are being enabled, the interrupt registers
@@ -890,12 +982,20 @@ static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
890 if (state == STATE_RADIO_IRQ_ON) { 982 if (state == STATE_RADIO_IRQ_ON) {
891 rt2x00pci_register_read(rt2x00dev, CSR7, &reg); 983 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
892 rt2x00pci_register_write(rt2x00dev, CSR7, reg); 984 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
985
986 /*
987 * Enable tasklets.
988 */
989 tasklet_enable(&rt2x00dev->txstatus_tasklet);
990 tasklet_enable(&rt2x00dev->rxdone_tasklet);
893 } 991 }
894 992
895 /* 993 /*
896 * Only toggle the interrupts bits we are going to use. 994 * Only toggle the interrupts bits we are going to use.
897 * Non-checked interrupt bits are disabled by default. 995 * Non-checked interrupt bits are disabled by default.
898 */ 996 */
997 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
998
899 rt2x00pci_register_read(rt2x00dev, CSR8, &reg); 999 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
900 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask); 1000 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
901 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask); 1001 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
@@ -903,6 +1003,17 @@ static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
903 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask); 1003 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
904 rt2x00_set_field32(&reg, CSR8_RXDONE, mask); 1004 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
905 rt2x00pci_register_write(rt2x00dev, CSR8, reg); 1005 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1006
1007 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
1008
1009 if (state == STATE_RADIO_IRQ_OFF) {
1010 /*
1011 * Ensure that all tasklets are finished before
1012 * disabling the interrupts.
1013 */
1014 tasklet_disable(&rt2x00dev->txstatus_tasklet);
1015 tasklet_disable(&rt2x00dev->rxdone_tasklet);
1016 }
906} 1017}
907 1018
908static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev) 1019static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
@@ -974,16 +1085,8 @@ static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
974 case STATE_RADIO_OFF: 1085 case STATE_RADIO_OFF:
975 rt2400pci_disable_radio(rt2x00dev); 1086 rt2400pci_disable_radio(rt2x00dev);
976 break; 1087 break;
977 case STATE_RADIO_RX_ON:
978 case STATE_RADIO_RX_ON_LINK:
979 case STATE_RADIO_RX_OFF:
980 case STATE_RADIO_RX_OFF_LINK:
981 rt2400pci_toggle_rx(rt2x00dev, state);
982 break;
983 case STATE_RADIO_IRQ_ON: 1088 case STATE_RADIO_IRQ_ON:
984 case STATE_RADIO_IRQ_ON_ISR:
985 case STATE_RADIO_IRQ_OFF: 1089 case STATE_RADIO_IRQ_OFF:
986 case STATE_RADIO_IRQ_OFF_ISR:
987 rt2400pci_toggle_irq(rt2x00dev, state); 1090 rt2400pci_toggle_irq(rt2x00dev, state);
988 break; 1091 break;
989 case STATE_DEEP_SLEEP: 1092 case STATE_DEEP_SLEEP:
@@ -1007,12 +1110,11 @@ static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1007/* 1110/*
1008 * TX descriptor initialization 1111 * TX descriptor initialization
1009 */ 1112 */
1010static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, 1113static void rt2400pci_write_tx_desc(struct queue_entry *entry,
1011 struct sk_buff *skb,
1012 struct txentry_desc *txdesc) 1114 struct txentry_desc *txdesc)
1013{ 1115{
1014 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 1116 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1015 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data; 1117 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1016 __le32 *txd = entry_priv->desc; 1118 __le32 *txd = entry_priv->desc;
1017 u32 word; 1119 u32 word;
1018 1120
@@ -1029,19 +1131,21 @@ static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1029 rt2x00_desc_write(txd, 2, word); 1131 rt2x00_desc_write(txd, 2, word);
1030 1132
1031 rt2x00_desc_read(txd, 3, &word); 1133 rt2x00_desc_read(txd, 3, &word);
1032 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal); 1134 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
1033 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5); 1135 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1034 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1); 1136 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1035 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service); 1137 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);
1036 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6); 1138 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1037 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1); 1139 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1038 rt2x00_desc_write(txd, 3, word); 1140 rt2x00_desc_write(txd, 3, word);
1039 1141
1040 rt2x00_desc_read(txd, 4, &word); 1142 rt2x00_desc_read(txd, 4, &word);
1041 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low); 1143 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW,
1144 txdesc->u.plcp.length_low);
1042 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8); 1145 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1043 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1); 1146 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1044 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high); 1147 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH,
1148 txdesc->u.plcp.length_high);
1045 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7); 1149 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1046 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1); 1150 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1047 rt2x00_desc_write(txd, 4, word); 1151 rt2x00_desc_write(txd, 4, word);
@@ -1062,7 +1166,7 @@ static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1062 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 1166 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1063 rt2x00_set_field32(&word, TXD_W0_RTS, 1167 rt2x00_set_field32(&word, TXD_W0_RTS,
1064 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)); 1168 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1065 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); 1169 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1066 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 1170 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1067 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); 1171 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1068 rt2x00_desc_write(txd, 0, word); 1172 rt2x00_desc_write(txd, 0, word);
@@ -1091,12 +1195,12 @@ static void rt2400pci_write_beacon(struct queue_entry *entry,
1091 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0); 1195 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1092 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 1196 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1093 1197
1094 rt2x00queue_map_txskb(rt2x00dev, entry->skb); 1198 rt2x00queue_map_txskb(entry);
1095 1199
1096 /* 1200 /*
1097 * Write the TX descriptor for the beacon. 1201 * Write the TX descriptor for the beacon.
1098 */ 1202 */
1099 rt2400pci_write_tx_desc(rt2x00dev, entry->skb, txdesc); 1203 rt2400pci_write_tx_desc(entry, txdesc);
1100 1204
1101 /* 1205 /*
1102 * Dump beacon to userspace through debugfs. 1206 * Dump beacon to userspace through debugfs.
@@ -1106,38 +1210,10 @@ static void rt2400pci_write_beacon(struct queue_entry *entry,
1106 /* 1210 /*
1107 * Enable beaconing again. 1211 * Enable beaconing again.
1108 */ 1212 */
1109 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1110 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1111 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1); 1213 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1112 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 1214 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1113} 1215}
1114 1216
1115static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1116 const enum data_queue_qid queue)
1117{
1118 u32 reg;
1119
1120 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1121 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1122 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1123 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1124 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1125}
1126
1127static void rt2400pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1128 const enum data_queue_qid qid)
1129{
1130 u32 reg;
1131
1132 if (qid == QID_BEACON) {
1133 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1134 } else {
1135 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1136 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1137 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1138 }
1139}
1140
1141/* 1217/*
1142 * RX control handlers 1218 * RX control handlers
1143 */ 1219 */
@@ -1202,7 +1278,7 @@ static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1202static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, 1278static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1203 const enum data_queue_qid queue_idx) 1279 const enum data_queue_qid queue_idx)
1204{ 1280{
1205 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); 1281 struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
1206 struct queue_entry_priv_pci *entry_priv; 1282 struct queue_entry_priv_pci *entry_priv;
1207 struct queue_entry *entry; 1283 struct queue_entry *entry;
1208 struct txdone_entry_desc txdesc; 1284 struct txdone_entry_desc txdesc;
@@ -1238,57 +1314,70 @@ static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1238 } 1314 }
1239} 1315}
1240 1316
1241static irqreturn_t rt2400pci_interrupt_thread(int irq, void *dev_instance) 1317static inline void rt2400pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
1318 struct rt2x00_field32 irq_field)
1242{ 1319{
1243 struct rt2x00_dev *rt2x00dev = dev_instance; 1320 u32 reg;
1244 u32 reg = rt2x00dev->irqvalue[0];
1245 1321
1246 /* 1322 /*
1247 * Handle interrupts, walk through all bits 1323 * Enable a single interrupt. The interrupt mask register
1248 * and run the tasks, the bits are checked in order of 1324 * access needs locking.
1249 * priority.
1250 */ 1325 */
1326 spin_lock_irq(&rt2x00dev->irqmask_lock);
1251 1327
1252 /* 1328 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1253 * 1 - Beacon timer expired interrupt. 1329 rt2x00_set_field32(&reg, irq_field, 0);
1254 */ 1330 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1255 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1256 rt2x00lib_beacondone(rt2x00dev);
1257 1331
1258 /* 1332 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1259 * 2 - Rx ring done interrupt. 1333}
1260 */
1261 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1262 rt2x00pci_rxdone(rt2x00dev);
1263 1334
1264 /* 1335static void rt2400pci_txstatus_tasklet(unsigned long data)
1265 * 3 - Atim ring transmit done interrupt. 1336{
1266 */ 1337 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1267 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING)) 1338 u32 reg;
1268 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1269 1339
1270 /* 1340 /*
1271 * 4 - Priority ring transmit done interrupt. 1341 * Handle all tx queues.
1272 */ 1342 */
1273 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING)) 1343 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1274 rt2400pci_txdone(rt2x00dev, QID_AC_BE); 1344 rt2400pci_txdone(rt2x00dev, QID_AC_VO);
1345 rt2400pci_txdone(rt2x00dev, QID_AC_VI);
1275 1346
1276 /* 1347 /*
1277 * 5 - Tx ring transmit done interrupt. 1348 * Enable all TXDONE interrupts again.
1278 */ 1349 */
1279 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) 1350 spin_lock_irq(&rt2x00dev->irqmask_lock);
1280 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
1281 1351
1282 /* Enable interrupts again. */ 1352 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1283 rt2x00dev->ops->lib->set_device_state(rt2x00dev, 1353 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);
1284 STATE_RADIO_IRQ_ON_ISR); 1354 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);
1285 return IRQ_HANDLED; 1355 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
1356 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1357
1358 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1359}
1360
1361static void rt2400pci_tbtt_tasklet(unsigned long data)
1362{
1363 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1364 rt2x00lib_beacondone(rt2x00dev);
1365 rt2400pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
1366}
1367
1368static void rt2400pci_rxdone_tasklet(unsigned long data)
1369{
1370 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1371 if (rt2x00pci_rxdone(rt2x00dev))
1372 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1373 else
1374 rt2400pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
1286} 1375}
1287 1376
1288static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance) 1377static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1289{ 1378{
1290 struct rt2x00_dev *rt2x00dev = dev_instance; 1379 struct rt2x00_dev *rt2x00dev = dev_instance;
1291 u32 reg; 1380 u32 reg, mask;
1292 1381
1293 /* 1382 /*
1294 * Get the interrupt sources & saved to local variable. 1383 * Get the interrupt sources & saved to local variable.
@@ -1303,14 +1392,44 @@ static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1303 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 1392 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1304 return IRQ_HANDLED; 1393 return IRQ_HANDLED;
1305 1394
1306 /* Store irqvalues for use in the interrupt thread. */ 1395 mask = reg;
1307 rt2x00dev->irqvalue[0] = reg; 1396
1397 /*
1398 * Schedule tasklets for interrupt handling.
1399 */
1400 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1401 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
1402
1403 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1404 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1405
1406 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
1407 rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
1408 rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
1409 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
1410 /*
1411 * Mask out all txdone interrupts.
1412 */
1413 rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
1414 rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
1415 rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
1416 }
1417
1418 /*
1419 * Disable all interrupts for which a tasklet was scheduled right now,
1420 * the tasklet will reenable the appropriate interrupts.
1421 */
1422 spin_lock(&rt2x00dev->irqmask_lock);
1423
1424 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1425 reg |= mask;
1426 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1427
1428 spin_unlock(&rt2x00dev->irqmask_lock);
1429
1308 1430
1309 /* Disable interrupts, will be enabled again in the interrupt thread. */
1310 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
1311 STATE_RADIO_IRQ_OFF_ISR);
1312 1431
1313 return IRQ_WAKE_THREAD; 1432 return IRQ_HANDLED;
1314} 1433}
1315 1434
1316/* 1435/*
@@ -1417,13 +1536,13 @@ static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1417 * Detect if this device has an hardware controlled radio. 1536 * Detect if this device has an hardware controlled radio.
1418 */ 1537 */
1419 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) 1538 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1420 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags); 1539 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
1421 1540
1422 /* 1541 /*
1423 * Check if the BBP tuning should be enabled. 1542 * Check if the BBP tuning should be enabled.
1424 */ 1543 */
1425 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING)) 1544 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1426 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags); 1545 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
1427 1546
1428 return 0; 1547 return 0;
1429} 1548}
@@ -1481,15 +1600,17 @@ static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1481 /* 1600 /*
1482 * Create channel information array 1601 * Create channel information array
1483 */ 1602 */
1484 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL); 1603 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
1485 if (!info) 1604 if (!info)
1486 return -ENOMEM; 1605 return -ENOMEM;
1487 1606
1488 spec->channels_info = info; 1607 spec->channels_info = info;
1489 1608
1490 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START); 1609 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1491 for (i = 0; i < 14; i++) 1610 for (i = 0; i < 14; i++) {
1492 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]); 1611 info[i].max_power = TXPOWER_FROM_DEV(MAX_TXPOWER);
1612 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1613 }
1493 1614
1494 return 0; 1615 return 0;
1495} 1616}
@@ -1519,8 +1640,9 @@ static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1519 /* 1640 /*
1520 * This device requires the atim queue and DMA-mapped skbs. 1641 * This device requires the atim queue and DMA-mapped skbs.
1521 */ 1642 */
1522 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags); 1643 __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
1523 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags); 1644 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
1645 __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
1524 1646
1525 /* 1647 /*
1526 * Set the rssi offset. 1648 * Set the rssi offset.
@@ -1597,11 +1719,17 @@ static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1597 .get_tsf = rt2400pci_get_tsf, 1719 .get_tsf = rt2400pci_get_tsf,
1598 .tx_last_beacon = rt2400pci_tx_last_beacon, 1720 .tx_last_beacon = rt2400pci_tx_last_beacon,
1599 .rfkill_poll = rt2x00mac_rfkill_poll, 1721 .rfkill_poll = rt2x00mac_rfkill_poll,
1722 .flush = rt2x00mac_flush,
1723 .set_antenna = rt2x00mac_set_antenna,
1724 .get_antenna = rt2x00mac_get_antenna,
1725 .get_ringparam = rt2x00mac_get_ringparam,
1600}; 1726};
1601 1727
1602static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = { 1728static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1603 .irq_handler = rt2400pci_interrupt, 1729 .irq_handler = rt2400pci_interrupt,
1604 .irq_handler_thread = rt2400pci_interrupt_thread, 1730 .txstatus_tasklet = rt2400pci_txstatus_tasklet,
1731 .tbtt_tasklet = rt2400pci_tbtt_tasklet,
1732 .rxdone_tasklet = rt2400pci_rxdone_tasklet,
1605 .probe_hw = rt2400pci_probe_hw, 1733 .probe_hw = rt2400pci_probe_hw,
1606 .initialize = rt2x00pci_initialize, 1734 .initialize = rt2x00pci_initialize,
1607 .uninitialize = rt2x00pci_uninitialize, 1735 .uninitialize = rt2x00pci_uninitialize,
@@ -1612,10 +1740,12 @@ static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1612 .link_stats = rt2400pci_link_stats, 1740 .link_stats = rt2400pci_link_stats,
1613 .reset_tuner = rt2400pci_reset_tuner, 1741 .reset_tuner = rt2400pci_reset_tuner,
1614 .link_tuner = rt2400pci_link_tuner, 1742 .link_tuner = rt2400pci_link_tuner,
1743 .start_queue = rt2400pci_start_queue,
1744 .kick_queue = rt2400pci_kick_queue,
1745 .stop_queue = rt2400pci_stop_queue,
1746 .flush_queue = rt2x00pci_flush_queue,
1615 .write_tx_desc = rt2400pci_write_tx_desc, 1747 .write_tx_desc = rt2400pci_write_tx_desc,
1616 .write_beacon = rt2400pci_write_beacon, 1748 .write_beacon = rt2400pci_write_beacon,
1617 .kick_tx_queue = rt2400pci_kick_tx_queue,
1618 .kill_tx_queue = rt2400pci_kill_tx_queue,
1619 .fill_rxdone = rt2400pci_fill_rxdone, 1749 .fill_rxdone = rt2400pci_fill_rxdone,
1620 .config_filter = rt2400pci_config_filter, 1750 .config_filter = rt2400pci_config_filter,
1621 .config_intf = rt2400pci_config_intf, 1751 .config_intf = rt2400pci_config_intf,
@@ -1625,28 +1755,28 @@ static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1625}; 1755};
1626 1756
1627static const struct data_queue_desc rt2400pci_queue_rx = { 1757static const struct data_queue_desc rt2400pci_queue_rx = {
1628 .entry_num = RX_ENTRIES, 1758 .entry_num = 24,
1629 .data_size = DATA_FRAME_SIZE, 1759 .data_size = DATA_FRAME_SIZE,
1630 .desc_size = RXD_DESC_SIZE, 1760 .desc_size = RXD_DESC_SIZE,
1631 .priv_size = sizeof(struct queue_entry_priv_pci), 1761 .priv_size = sizeof(struct queue_entry_priv_pci),
1632}; 1762};
1633 1763
1634static const struct data_queue_desc rt2400pci_queue_tx = { 1764static const struct data_queue_desc rt2400pci_queue_tx = {
1635 .entry_num = TX_ENTRIES, 1765 .entry_num = 24,
1636 .data_size = DATA_FRAME_SIZE, 1766 .data_size = DATA_FRAME_SIZE,
1637 .desc_size = TXD_DESC_SIZE, 1767 .desc_size = TXD_DESC_SIZE,
1638 .priv_size = sizeof(struct queue_entry_priv_pci), 1768 .priv_size = sizeof(struct queue_entry_priv_pci),
1639}; 1769};
1640 1770
1641static const struct data_queue_desc rt2400pci_queue_bcn = { 1771static const struct data_queue_desc rt2400pci_queue_bcn = {
1642 .entry_num = BEACON_ENTRIES, 1772 .entry_num = 1,
1643 .data_size = MGMT_FRAME_SIZE, 1773 .data_size = MGMT_FRAME_SIZE,
1644 .desc_size = TXD_DESC_SIZE, 1774 .desc_size = TXD_DESC_SIZE,
1645 .priv_size = sizeof(struct queue_entry_priv_pci), 1775 .priv_size = sizeof(struct queue_entry_priv_pci),
1646}; 1776};
1647 1777
1648static const struct data_queue_desc rt2400pci_queue_atim = { 1778static const struct data_queue_desc rt2400pci_queue_atim = {
1649 .entry_num = ATIM_ENTRIES, 1779 .entry_num = 8,
1650 .data_size = DATA_FRAME_SIZE, 1780 .data_size = DATA_FRAME_SIZE,
1651 .desc_size = TXD_DESC_SIZE, 1781 .desc_size = TXD_DESC_SIZE,
1652 .priv_size = sizeof(struct queue_entry_priv_pci), 1782 .priv_size = sizeof(struct queue_entry_priv_pci),
@@ -1675,10 +1805,11 @@ static const struct rt2x00_ops rt2400pci_ops = {
1675 * RT2400pci module information. 1805 * RT2400pci module information.
1676 */ 1806 */
1677static DEFINE_PCI_DEVICE_TABLE(rt2400pci_device_table) = { 1807static DEFINE_PCI_DEVICE_TABLE(rt2400pci_device_table) = {
1678 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) }, 1808 { PCI_DEVICE(0x1814, 0x0101) },
1679 { 0, } 1809 { 0, }
1680}; 1810};
1681 1811
1812
1682MODULE_AUTHOR(DRV_PROJECT); 1813MODULE_AUTHOR(DRV_PROJECT);
1683MODULE_VERSION(DRV_VERSION); 1814MODULE_VERSION(DRV_VERSION);
1684MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver."); 1815MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
@@ -1686,10 +1817,16 @@ MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1686MODULE_DEVICE_TABLE(pci, rt2400pci_device_table); 1817MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1687MODULE_LICENSE("GPL"); 1818MODULE_LICENSE("GPL");
1688 1819
1820static int rt2400pci_probe(struct pci_dev *pci_dev,
1821 const struct pci_device_id *id)
1822{
1823 return rt2x00pci_probe(pci_dev, &rt2400pci_ops);
1824}
1825
1689static struct pci_driver rt2400pci_driver = { 1826static struct pci_driver rt2400pci_driver = {
1690 .name = KBUILD_MODNAME, 1827 .name = KBUILD_MODNAME,
1691 .id_table = rt2400pci_device_table, 1828 .id_table = rt2400pci_device_table,
1692 .probe = rt2x00pci_probe, 1829 .probe = rt2400pci_probe,
1693 .remove = __devexit_p(rt2x00pci_remove), 1830 .remove = __devexit_p(rt2x00pci_remove),
1694 .suspend = rt2x00pci_suspend, 1831 .suspend = rt2x00pci_suspend,
1695 .resume = rt2x00pci_resume, 1832 .resume = rt2x00pci_resume,
diff --git a/drivers/net/wireless/rt2x00/rt2400pci.h b/drivers/net/wireless/rt2x00/rt2400pci.h
index c048b18f4133..d3a4a68cc439 100644
--- a/drivers/net/wireless/rt2x00/rt2400pci.h
+++ b/drivers/net/wireless/rt2x00/rt2400pci.h
@@ -809,8 +809,8 @@
809/* 809/*
810 * DMA descriptor defines. 810 * DMA descriptor defines.
811 */ 811 */
812#define TXD_DESC_SIZE ( 8 * sizeof(__le32) ) 812#define TXD_DESC_SIZE (8 * sizeof(__le32))
813#define RXD_DESC_SIZE ( 8 * sizeof(__le32) ) 813#define RXD_DESC_SIZE (8 * sizeof(__le32))
814 814
815/* 815/*
816 * TX descriptor format for TX, PRIO, ATIM and Beacon Ring. 816 * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
@@ -948,6 +948,6 @@
948 ((__CLAMP_TX(__txpower) - MAX_TXPOWER) + MIN_TXPOWER) 948 ((__CLAMP_TX(__txpower) - MAX_TXPOWER) + MIN_TXPOWER)
949 949
950#define TXPOWER_TO_DEV(__txpower) \ 950#define TXPOWER_TO_DEV(__txpower) \
951 MAX_TXPOWER - (__CLAMP_TX(__txpower) - MIN_TXPOWER) 951 (MAX_TXPOWER - (__CLAMP_TX(__txpower) - MIN_TXPOWER))
952 952
953#endif /* RT2400PCI_H */ 953#endif /* RT2400PCI_H */
diff --git a/drivers/net/wireless/rt2x00/rt2500pci.c b/drivers/net/wireless/rt2x00/rt2500pci.c
index c2a555d5376b..d27d7b8ba3b6 100644
--- a/drivers/net/wireless/rt2x00/rt2500pci.c
+++ b/drivers/net/wireless/rt2x00/rt2500pci.c
@@ -293,7 +293,7 @@ static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
293 struct rt2x00intf_conf *conf, 293 struct rt2x00intf_conf *conf,
294 const unsigned int flags) 294 const unsigned int flags)
295{ 295{
296 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON); 296 struct data_queue *queue = rt2x00dev->bcn;
297 unsigned int bcn_preload; 297 unsigned int bcn_preload;
298 u32 reg; 298 u32 reg;
299 299
@@ -311,9 +311,7 @@ static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
311 * Enable synchronisation. 311 * Enable synchronisation.
312 */ 312 */
313 rt2x00pci_register_read(rt2x00dev, CSR14, &reg); 313 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
314 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
315 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync); 314 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
316 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
317 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 315 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
318 } 316 }
319 317
@@ -327,7 +325,8 @@ static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
327} 325}
328 326
329static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev, 327static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
330 struct rt2x00lib_erp *erp) 328 struct rt2x00lib_erp *erp,
329 u32 changed)
331{ 330{
332 int preamble_mask; 331 int preamble_mask;
333 u32 reg; 332 u32 reg;
@@ -335,59 +334,73 @@ static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
335 /* 334 /*
336 * When short preamble is enabled, we should set bit 0x08 335 * When short preamble is enabled, we should set bit 0x08
337 */ 336 */
338 preamble_mask = erp->short_preamble << 3; 337 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
339 338 preamble_mask = erp->short_preamble << 3;
340 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg); 339
341 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x162); 340 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
342 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0xa2); 341 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x162);
343 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER); 342 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0xa2);
344 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1); 343 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
345 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg); 344 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
346 345 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
347 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg); 346
348 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00); 347 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
349 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04); 348 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
350 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10)); 349 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
351 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg); 350 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
352 351 GET_DURATION(ACK_SIZE, 10));
353 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg); 352 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
354 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask); 353
355 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04); 354 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
356 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20)); 355 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
357 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg); 356 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
358 357 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
359 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg); 358 GET_DURATION(ACK_SIZE, 20));
360 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask); 359 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
361 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04); 360
362 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55)); 361 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
363 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg); 362 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
364 363 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
365 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg); 364 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
366 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask); 365 GET_DURATION(ACK_SIZE, 55));
367 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84); 366 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
368 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110)); 367
369 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg); 368 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
370 369 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
371 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates); 370 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
371 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
372 GET_DURATION(ACK_SIZE, 110));
373 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
374 }
372 375
373 rt2x00pci_register_read(rt2x00dev, CSR11, &reg); 376 if (changed & BSS_CHANGED_BASIC_RATES)
374 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time); 377 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
375 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
376 378
377 rt2x00pci_register_read(rt2x00dev, CSR12, &reg); 379 if (changed & BSS_CHANGED_ERP_SLOT) {
378 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, erp->beacon_int * 16); 380 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
379 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, erp->beacon_int * 16); 381 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
380 rt2x00pci_register_write(rt2x00dev, CSR12, reg); 382 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
381 383
382 rt2x00pci_register_read(rt2x00dev, CSR18, &reg); 384 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
383 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs); 385 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
384 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs); 386 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
385 rt2x00pci_register_write(rt2x00dev, CSR18, reg); 387 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
388
389 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
390 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
391 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
392 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
393 }
394
395 if (changed & BSS_CHANGED_BEACON_INT) {
396 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
397 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
398 erp->beacon_int * 16);
399 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
400 erp->beacon_int * 16);
401 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
402 }
386 403
387 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
388 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
389 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
390 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
391} 404}
392 405
393static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev, 406static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
@@ -708,6 +721,98 @@ dynamic_cca_tune:
708} 721}
709 722
710/* 723/*
724 * Queue handlers.
725 */
726static void rt2500pci_start_queue(struct data_queue *queue)
727{
728 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
729 u32 reg;
730
731 switch (queue->qid) {
732 case QID_RX:
733 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
734 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
735 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
736 break;
737 case QID_BEACON:
738 /*
739 * Allow the tbtt tasklet to be scheduled.
740 */
741 tasklet_enable(&rt2x00dev->tbtt_tasklet);
742
743 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
744 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
745 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
746 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
747 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
748 break;
749 default:
750 break;
751 }
752}
753
754static void rt2500pci_kick_queue(struct data_queue *queue)
755{
756 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
757 u32 reg;
758
759 switch (queue->qid) {
760 case QID_AC_VO:
761 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
762 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
763 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
764 break;
765 case QID_AC_VI:
766 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
767 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
768 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
769 break;
770 case QID_ATIM:
771 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
772 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
773 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
774 break;
775 default:
776 break;
777 }
778}
779
780static void rt2500pci_stop_queue(struct data_queue *queue)
781{
782 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
783 u32 reg;
784
785 switch (queue->qid) {
786 case QID_AC_VO:
787 case QID_AC_VI:
788 case QID_ATIM:
789 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
790 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
791 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
792 break;
793 case QID_RX:
794 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
795 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
796 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
797 break;
798 case QID_BEACON:
799 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
800 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
801 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
802 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
803 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
804
805 /*
806 * Wait for possibly running tbtt tasklets.
807 */
808 tasklet_disable(&rt2x00dev->tbtt_tasklet);
809 break;
810 default:
811 break;
812 }
813}
814
815/*
711 * Initialization functions. 816 * Initialization functions.
712 */ 817 */
713static bool rt2500pci_get_entry_state(struct queue_entry *entry) 818static bool rt2500pci_get_entry_state(struct queue_entry *entry)
@@ -760,7 +865,7 @@ static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
760 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg); 865 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
761 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); 866 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
762 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); 867 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
763 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit); 868 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
764 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); 869 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
765 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg); 870 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
766 871
@@ -776,13 +881,13 @@ static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
776 entry_priv->desc_dma); 881 entry_priv->desc_dma);
777 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); 882 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
778 883
779 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data; 884 entry_priv = rt2x00dev->atim->entries[0].priv_data;
780 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg); 885 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
781 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER, 886 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
782 entry_priv->desc_dma); 887 entry_priv->desc_dma);
783 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); 888 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
784 889
785 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data; 890 entry_priv = rt2x00dev->bcn->entries[0].priv_data;
786 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg); 891 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
787 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER, 892 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
788 entry_priv->desc_dma); 893 entry_priv->desc_dma);
@@ -1018,24 +1123,12 @@ static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1018/* 1123/*
1019 * Device state switch handlers. 1124 * Device state switch handlers.
1020 */ 1125 */
1021static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1022 enum dev_state state)
1023{
1024 u32 reg;
1025
1026 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1027 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1028 (state == STATE_RADIO_RX_OFF) ||
1029 (state == STATE_RADIO_RX_OFF_LINK));
1030 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1031}
1032
1033static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev, 1126static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1034 enum dev_state state) 1127 enum dev_state state)
1035{ 1128{
1036 int mask = (state == STATE_RADIO_IRQ_OFF) || 1129 int mask = (state == STATE_RADIO_IRQ_OFF);
1037 (state == STATE_RADIO_IRQ_OFF_ISR);
1038 u32 reg; 1130 u32 reg;
1131 unsigned long flags;
1039 1132
1040 /* 1133 /*
1041 * When interrupts are being enabled, the interrupt registers 1134 * When interrupts are being enabled, the interrupt registers
@@ -1044,12 +1137,20 @@ static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1044 if (state == STATE_RADIO_IRQ_ON) { 1137 if (state == STATE_RADIO_IRQ_ON) {
1045 rt2x00pci_register_read(rt2x00dev, CSR7, &reg); 1138 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1046 rt2x00pci_register_write(rt2x00dev, CSR7, reg); 1139 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1140
1141 /*
1142 * Enable tasklets.
1143 */
1144 tasklet_enable(&rt2x00dev->txstatus_tasklet);
1145 tasklet_enable(&rt2x00dev->rxdone_tasklet);
1047 } 1146 }
1048 1147
1049 /* 1148 /*
1050 * Only toggle the interrupts bits we are going to use. 1149 * Only toggle the interrupts bits we are going to use.
1051 * Non-checked interrupt bits are disabled by default. 1150 * Non-checked interrupt bits are disabled by default.
1052 */ 1151 */
1152 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
1153
1053 rt2x00pci_register_read(rt2x00dev, CSR8, &reg); 1154 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1054 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask); 1155 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1055 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask); 1156 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
@@ -1057,6 +1158,16 @@ static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1057 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask); 1158 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1058 rt2x00_set_field32(&reg, CSR8_RXDONE, mask); 1159 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1059 rt2x00pci_register_write(rt2x00dev, CSR8, reg); 1160 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1161
1162 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
1163
1164 if (state == STATE_RADIO_IRQ_OFF) {
1165 /*
1166 * Ensure that all tasklets are finished.
1167 */
1168 tasklet_disable(&rt2x00dev->txstatus_tasklet);
1169 tasklet_disable(&rt2x00dev->rxdone_tasklet);
1170 }
1060} 1171}
1061 1172
1062static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev) 1173static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
@@ -1128,16 +1239,8 @@ static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1128 case STATE_RADIO_OFF: 1239 case STATE_RADIO_OFF:
1129 rt2500pci_disable_radio(rt2x00dev); 1240 rt2500pci_disable_radio(rt2x00dev);
1130 break; 1241 break;
1131 case STATE_RADIO_RX_ON:
1132 case STATE_RADIO_RX_ON_LINK:
1133 case STATE_RADIO_RX_OFF:
1134 case STATE_RADIO_RX_OFF_LINK:
1135 rt2500pci_toggle_rx(rt2x00dev, state);
1136 break;
1137 case STATE_RADIO_IRQ_ON: 1242 case STATE_RADIO_IRQ_ON:
1138 case STATE_RADIO_IRQ_ON_ISR:
1139 case STATE_RADIO_IRQ_OFF: 1243 case STATE_RADIO_IRQ_OFF:
1140 case STATE_RADIO_IRQ_OFF_ISR:
1141 rt2500pci_toggle_irq(rt2x00dev, state); 1244 rt2500pci_toggle_irq(rt2x00dev, state);
1142 break; 1245 break;
1143 case STATE_DEEP_SLEEP: 1246 case STATE_DEEP_SLEEP:
@@ -1161,12 +1264,11 @@ static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1161/* 1264/*
1162 * TX descriptor initialization 1265 * TX descriptor initialization
1163 */ 1266 */
1164static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, 1267static void rt2500pci_write_tx_desc(struct queue_entry *entry,
1165 struct sk_buff *skb,
1166 struct txentry_desc *txdesc) 1268 struct txentry_desc *txdesc)
1167{ 1269{
1168 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 1270 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1169 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data; 1271 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1170 __le32 *txd = entry_priv->desc; 1272 __le32 *txd = entry_priv->desc;
1171 u32 word; 1273 u32 word;
1172 1274
@@ -1179,16 +1281,18 @@ static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1179 1281
1180 rt2x00_desc_read(txd, 2, &word); 1282 rt2x00_desc_read(txd, 2, &word);
1181 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER); 1283 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1182 rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs); 1284 rt2x00_set_field32(&word, TXD_W2_AIFS, entry->queue->aifs);
1183 rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min); 1285 rt2x00_set_field32(&word, TXD_W2_CWMIN, entry->queue->cw_min);
1184 rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max); 1286 rt2x00_set_field32(&word, TXD_W2_CWMAX, entry->queue->cw_max);
1185 rt2x00_desc_write(txd, 2, word); 1287 rt2x00_desc_write(txd, 2, word);
1186 1288
1187 rt2x00_desc_read(txd, 3, &word); 1289 rt2x00_desc_read(txd, 3, &word);
1188 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal); 1290 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
1189 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service); 1291 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);
1190 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low); 1292 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW,
1191 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high); 1293 txdesc->u.plcp.length_low);
1294 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH,
1295 txdesc->u.plcp.length_high);
1192 rt2x00_desc_write(txd, 3, word); 1296 rt2x00_desc_write(txd, 3, word);
1193 1297
1194 rt2x00_desc_read(txd, 10, &word); 1298 rt2x00_desc_read(txd, 10, &word);
@@ -1213,7 +1317,7 @@ static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1213 rt2x00_set_field32(&word, TXD_W0_OFDM, 1317 rt2x00_set_field32(&word, TXD_W0_OFDM,
1214 (txdesc->rate_mode == RATE_MODE_OFDM)); 1318 (txdesc->rate_mode == RATE_MODE_OFDM));
1215 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1); 1319 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1216 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); 1320 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1217 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 1321 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1218 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); 1322 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1219 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length); 1323 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
@@ -1244,12 +1348,12 @@ static void rt2500pci_write_beacon(struct queue_entry *entry,
1244 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0); 1348 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1245 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 1349 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1246 1350
1247 rt2x00queue_map_txskb(rt2x00dev, entry->skb); 1351 rt2x00queue_map_txskb(entry);
1248 1352
1249 /* 1353 /*
1250 * Write the TX descriptor for the beacon. 1354 * Write the TX descriptor for the beacon.
1251 */ 1355 */
1252 rt2500pci_write_tx_desc(rt2x00dev, entry->skb, txdesc); 1356 rt2500pci_write_tx_desc(entry, txdesc);
1253 1357
1254 /* 1358 /*
1255 * Dump beacon to userspace through debugfs. 1359 * Dump beacon to userspace through debugfs.
@@ -1259,38 +1363,10 @@ static void rt2500pci_write_beacon(struct queue_entry *entry,
1259 /* 1363 /*
1260 * Enable beaconing again. 1364 * Enable beaconing again.
1261 */ 1365 */
1262 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1263 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1264 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1); 1366 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1265 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 1367 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1266} 1368}
1267 1369
1268static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1269 const enum data_queue_qid queue)
1270{
1271 u32 reg;
1272
1273 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1274 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1275 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1276 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1277 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1278}
1279
1280static void rt2500pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1281 const enum data_queue_qid qid)
1282{
1283 u32 reg;
1284
1285 if (qid == QID_BEACON) {
1286 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1287 } else {
1288 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1289 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1290 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1291 }
1292}
1293
1294/* 1370/*
1295 * RX control handlers 1371 * RX control handlers
1296 */ 1372 */
@@ -1334,7 +1410,7 @@ static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1334static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, 1410static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1335 const enum data_queue_qid queue_idx) 1411 const enum data_queue_qid queue_idx)
1336{ 1412{
1337 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); 1413 struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
1338 struct queue_entry_priv_pci *entry_priv; 1414 struct queue_entry_priv_pci *entry_priv;
1339 struct queue_entry *entry; 1415 struct queue_entry *entry;
1340 struct txdone_entry_desc txdesc; 1416 struct txdone_entry_desc txdesc;
@@ -1370,58 +1446,70 @@ static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1370 } 1446 }
1371} 1447}
1372 1448
1373static irqreturn_t rt2500pci_interrupt_thread(int irq, void *dev_instance) 1449static inline void rt2500pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
1450 struct rt2x00_field32 irq_field)
1374{ 1451{
1375 struct rt2x00_dev *rt2x00dev = dev_instance; 1452 u32 reg;
1376 u32 reg = rt2x00dev->irqvalue[0];
1377 1453
1378 /* 1454 /*
1379 * Handle interrupts, walk through all bits 1455 * Enable a single interrupt. The interrupt mask register
1380 * and run the tasks, the bits are checked in order of 1456 * access needs locking.
1381 * priority.
1382 */ 1457 */
1458 spin_lock_irq(&rt2x00dev->irqmask_lock);
1383 1459
1384 /* 1460 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1385 * 1 - Beacon timer expired interrupt. 1461 rt2x00_set_field32(&reg, irq_field, 0);
1386 */ 1462 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1387 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1388 rt2x00lib_beacondone(rt2x00dev);
1389 1463
1390 /* 1464 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1391 * 2 - Rx ring done interrupt. 1465}
1392 */
1393 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1394 rt2x00pci_rxdone(rt2x00dev);
1395 1466
1396 /* 1467static void rt2500pci_txstatus_tasklet(unsigned long data)
1397 * 3 - Atim ring transmit done interrupt. 1468{
1398 */ 1469 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1399 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING)) 1470 u32 reg;
1400 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1401 1471
1402 /* 1472 /*
1403 * 4 - Priority ring transmit done interrupt. 1473 * Handle all tx queues.
1404 */ 1474 */
1405 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING)) 1475 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1406 rt2500pci_txdone(rt2x00dev, QID_AC_BE); 1476 rt2500pci_txdone(rt2x00dev, QID_AC_VO);
1477 rt2500pci_txdone(rt2x00dev, QID_AC_VI);
1407 1478
1408 /* 1479 /*
1409 * 5 - Tx ring transmit done interrupt. 1480 * Enable all TXDONE interrupts again.
1410 */ 1481 */
1411 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) 1482 spin_lock_irq(&rt2x00dev->irqmask_lock);
1412 rt2500pci_txdone(rt2x00dev, QID_AC_BK);
1413 1483
1414 /* Enable interrupts again. */ 1484 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1415 rt2x00dev->ops->lib->set_device_state(rt2x00dev, 1485 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);
1416 STATE_RADIO_IRQ_ON_ISR); 1486 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);
1487 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
1488 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1417 1489
1418 return IRQ_HANDLED; 1490 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1491}
1492
1493static void rt2500pci_tbtt_tasklet(unsigned long data)
1494{
1495 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1496 rt2x00lib_beacondone(rt2x00dev);
1497 rt2500pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
1498}
1499
1500static void rt2500pci_rxdone_tasklet(unsigned long data)
1501{
1502 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1503 if (rt2x00pci_rxdone(rt2x00dev))
1504 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1505 else
1506 rt2500pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
1419} 1507}
1420 1508
1421static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance) 1509static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1422{ 1510{
1423 struct rt2x00_dev *rt2x00dev = dev_instance; 1511 struct rt2x00_dev *rt2x00dev = dev_instance;
1424 u32 reg; 1512 u32 reg, mask;
1425 1513
1426 /* 1514 /*
1427 * Get the interrupt sources & saved to local variable. 1515 * Get the interrupt sources & saved to local variable.
@@ -1436,14 +1524,42 @@ static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1436 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 1524 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1437 return IRQ_HANDLED; 1525 return IRQ_HANDLED;
1438 1526
1439 /* Store irqvalues for use in the interrupt thread. */ 1527 mask = reg;
1440 rt2x00dev->irqvalue[0] = reg; 1528
1529 /*
1530 * Schedule tasklets for interrupt handling.
1531 */
1532 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1533 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
1534
1535 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1536 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1537
1538 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
1539 rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
1540 rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
1541 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
1542 /*
1543 * Mask out all txdone interrupts.
1544 */
1545 rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
1546 rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
1547 rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
1548 }
1549
1550 /*
1551 * Disable all interrupts for which a tasklet was scheduled right now,
1552 * the tasklet will reenable the appropriate interrupts.
1553 */
1554 spin_lock(&rt2x00dev->irqmask_lock);
1555
1556 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1557 reg |= mask;
1558 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1441 1559
1442 /* Disable interrupts, will be enabled again in the interrupt thread. */ 1560 spin_unlock(&rt2x00dev->irqmask_lock);
1443 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
1444 STATE_RADIO_IRQ_OFF_ISR);
1445 1561
1446 return IRQ_WAKE_THREAD; 1562 return IRQ_HANDLED;
1447} 1563}
1448 1564
1449/* 1565/*
@@ -1571,14 +1687,14 @@ static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1571 * Detect if this device has an hardware controlled radio. 1687 * Detect if this device has an hardware controlled radio.
1572 */ 1688 */
1573 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) 1689 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1574 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags); 1690 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
1575 1691
1576 /* 1692 /*
1577 * Check if the BBP tuning should be enabled. 1693 * Check if the BBP tuning should be enabled.
1578 */ 1694 */
1579 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); 1695 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1580 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE)) 1696 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1581 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags); 1697 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
1582 1698
1583 /* 1699 /*
1584 * Read the RSSI <-> dBm offset information. 1700 * Read the RSSI <-> dBm offset information.
@@ -1795,19 +1911,23 @@ static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1795 /* 1911 /*
1796 * Create channel information array 1912 * Create channel information array
1797 */ 1913 */
1798 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL); 1914 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
1799 if (!info) 1915 if (!info)
1800 return -ENOMEM; 1916 return -ENOMEM;
1801 1917
1802 spec->channels_info = info; 1918 spec->channels_info = info;
1803 1919
1804 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START); 1920 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1805 for (i = 0; i < 14; i++) 1921 for (i = 0; i < 14; i++) {
1806 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]); 1922 info[i].max_power = MAX_TXPOWER;
1923 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1924 }
1807 1925
1808 if (spec->num_channels > 14) { 1926 if (spec->num_channels > 14) {
1809 for (i = 14; i < spec->num_channels; i++) 1927 for (i = 14; i < spec->num_channels; i++) {
1810 info[i].tx_power1 = DEFAULT_TXPOWER; 1928 info[i].max_power = MAX_TXPOWER;
1929 info[i].default_power1 = DEFAULT_TXPOWER;
1930 }
1811 } 1931 }
1812 1932
1813 return 0; 1933 return 0;
@@ -1838,8 +1958,9 @@ static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1838 /* 1958 /*
1839 * This device requires the atim queue and DMA-mapped skbs. 1959 * This device requires the atim queue and DMA-mapped skbs.
1840 */ 1960 */
1841 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags); 1961 __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
1842 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags); 1962 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
1963 __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
1843 1964
1844 /* 1965 /*
1845 * Set the rssi offset. 1966 * Set the rssi offset.
@@ -1891,11 +2012,17 @@ static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1891 .get_tsf = rt2500pci_get_tsf, 2012 .get_tsf = rt2500pci_get_tsf,
1892 .tx_last_beacon = rt2500pci_tx_last_beacon, 2013 .tx_last_beacon = rt2500pci_tx_last_beacon,
1893 .rfkill_poll = rt2x00mac_rfkill_poll, 2014 .rfkill_poll = rt2x00mac_rfkill_poll,
2015 .flush = rt2x00mac_flush,
2016 .set_antenna = rt2x00mac_set_antenna,
2017 .get_antenna = rt2x00mac_get_antenna,
2018 .get_ringparam = rt2x00mac_get_ringparam,
1894}; 2019};
1895 2020
1896static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = { 2021static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1897 .irq_handler = rt2500pci_interrupt, 2022 .irq_handler = rt2500pci_interrupt,
1898 .irq_handler_thread = rt2500pci_interrupt_thread, 2023 .txstatus_tasklet = rt2500pci_txstatus_tasklet,
2024 .tbtt_tasklet = rt2500pci_tbtt_tasklet,
2025 .rxdone_tasklet = rt2500pci_rxdone_tasklet,
1899 .probe_hw = rt2500pci_probe_hw, 2026 .probe_hw = rt2500pci_probe_hw,
1900 .initialize = rt2x00pci_initialize, 2027 .initialize = rt2x00pci_initialize,
1901 .uninitialize = rt2x00pci_uninitialize, 2028 .uninitialize = rt2x00pci_uninitialize,
@@ -1906,10 +2033,12 @@ static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1906 .link_stats = rt2500pci_link_stats, 2033 .link_stats = rt2500pci_link_stats,
1907 .reset_tuner = rt2500pci_reset_tuner, 2034 .reset_tuner = rt2500pci_reset_tuner,
1908 .link_tuner = rt2500pci_link_tuner, 2035 .link_tuner = rt2500pci_link_tuner,
2036 .start_queue = rt2500pci_start_queue,
2037 .kick_queue = rt2500pci_kick_queue,
2038 .stop_queue = rt2500pci_stop_queue,
2039 .flush_queue = rt2x00pci_flush_queue,
1909 .write_tx_desc = rt2500pci_write_tx_desc, 2040 .write_tx_desc = rt2500pci_write_tx_desc,
1910 .write_beacon = rt2500pci_write_beacon, 2041 .write_beacon = rt2500pci_write_beacon,
1911 .kick_tx_queue = rt2500pci_kick_tx_queue,
1912 .kill_tx_queue = rt2500pci_kill_tx_queue,
1913 .fill_rxdone = rt2500pci_fill_rxdone, 2042 .fill_rxdone = rt2500pci_fill_rxdone,
1914 .config_filter = rt2500pci_config_filter, 2043 .config_filter = rt2500pci_config_filter,
1915 .config_intf = rt2500pci_config_intf, 2044 .config_intf = rt2500pci_config_intf,
@@ -1919,28 +2048,28 @@ static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1919}; 2048};
1920 2049
1921static const struct data_queue_desc rt2500pci_queue_rx = { 2050static const struct data_queue_desc rt2500pci_queue_rx = {
1922 .entry_num = RX_ENTRIES, 2051 .entry_num = 32,
1923 .data_size = DATA_FRAME_SIZE, 2052 .data_size = DATA_FRAME_SIZE,
1924 .desc_size = RXD_DESC_SIZE, 2053 .desc_size = RXD_DESC_SIZE,
1925 .priv_size = sizeof(struct queue_entry_priv_pci), 2054 .priv_size = sizeof(struct queue_entry_priv_pci),
1926}; 2055};
1927 2056
1928static const struct data_queue_desc rt2500pci_queue_tx = { 2057static const struct data_queue_desc rt2500pci_queue_tx = {
1929 .entry_num = TX_ENTRIES, 2058 .entry_num = 32,
1930 .data_size = DATA_FRAME_SIZE, 2059 .data_size = DATA_FRAME_SIZE,
1931 .desc_size = TXD_DESC_SIZE, 2060 .desc_size = TXD_DESC_SIZE,
1932 .priv_size = sizeof(struct queue_entry_priv_pci), 2061 .priv_size = sizeof(struct queue_entry_priv_pci),
1933}; 2062};
1934 2063
1935static const struct data_queue_desc rt2500pci_queue_bcn = { 2064static const struct data_queue_desc rt2500pci_queue_bcn = {
1936 .entry_num = BEACON_ENTRIES, 2065 .entry_num = 1,
1937 .data_size = MGMT_FRAME_SIZE, 2066 .data_size = MGMT_FRAME_SIZE,
1938 .desc_size = TXD_DESC_SIZE, 2067 .desc_size = TXD_DESC_SIZE,
1939 .priv_size = sizeof(struct queue_entry_priv_pci), 2068 .priv_size = sizeof(struct queue_entry_priv_pci),
1940}; 2069};
1941 2070
1942static const struct data_queue_desc rt2500pci_queue_atim = { 2071static const struct data_queue_desc rt2500pci_queue_atim = {
1943 .entry_num = ATIM_ENTRIES, 2072 .entry_num = 8,
1944 .data_size = DATA_FRAME_SIZE, 2073 .data_size = DATA_FRAME_SIZE,
1945 .desc_size = TXD_DESC_SIZE, 2074 .desc_size = TXD_DESC_SIZE,
1946 .priv_size = sizeof(struct queue_entry_priv_pci), 2075 .priv_size = sizeof(struct queue_entry_priv_pci),
@@ -1969,7 +2098,7 @@ static const struct rt2x00_ops rt2500pci_ops = {
1969 * RT2500pci module information. 2098 * RT2500pci module information.
1970 */ 2099 */
1971static DEFINE_PCI_DEVICE_TABLE(rt2500pci_device_table) = { 2100static DEFINE_PCI_DEVICE_TABLE(rt2500pci_device_table) = {
1972 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) }, 2101 { PCI_DEVICE(0x1814, 0x0201) },
1973 { 0, } 2102 { 0, }
1974}; 2103};
1975 2104
@@ -1980,10 +2109,16 @@ MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1980MODULE_DEVICE_TABLE(pci, rt2500pci_device_table); 2109MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1981MODULE_LICENSE("GPL"); 2110MODULE_LICENSE("GPL");
1982 2111
2112static int rt2500pci_probe(struct pci_dev *pci_dev,
2113 const struct pci_device_id *id)
2114{
2115 return rt2x00pci_probe(pci_dev, &rt2500pci_ops);
2116}
2117
1983static struct pci_driver rt2500pci_driver = { 2118static struct pci_driver rt2500pci_driver = {
1984 .name = KBUILD_MODNAME, 2119 .name = KBUILD_MODNAME,
1985 .id_table = rt2500pci_device_table, 2120 .id_table = rt2500pci_device_table,
1986 .probe = rt2x00pci_probe, 2121 .probe = rt2500pci_probe,
1987 .remove = __devexit_p(rt2x00pci_remove), 2122 .remove = __devexit_p(rt2x00pci_remove),
1988 .suspend = rt2x00pci_suspend, 2123 .suspend = rt2x00pci_suspend,
1989 .resume = rt2x00pci_resume, 2124 .resume = rt2x00pci_resume,
diff --git a/drivers/net/wireless/rt2x00/rt2500pci.h b/drivers/net/wireless/rt2x00/rt2500pci.h
index d708031361ac..2aad7ba8a100 100644
--- a/drivers/net/wireless/rt2x00/rt2500pci.h
+++ b/drivers/net/wireless/rt2x00/rt2500pci.h
@@ -1088,8 +1088,8 @@
1088/* 1088/*
1089 * DMA descriptor defines. 1089 * DMA descriptor defines.
1090 */ 1090 */
1091#define TXD_DESC_SIZE ( 11 * sizeof(__le32) ) 1091#define TXD_DESC_SIZE (11 * sizeof(__le32))
1092#define RXD_DESC_SIZE ( 11 * sizeof(__le32) ) 1092#define RXD_DESC_SIZE (11 * sizeof(__le32))
1093 1093
1094/* 1094/*
1095 * TX descriptor format for TX, PRIO, ATIM and Beacon Ring. 1095 * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
diff --git a/drivers/net/wireless/rt2x00/rt2500usb.c b/drivers/net/wireless/rt2x00/rt2500usb.c
index cdaf93f48263..15237c275486 100644
--- a/drivers/net/wireless/rt2x00/rt2500usb.c
+++ b/drivers/net/wireless/rt2x00/rt2500usb.c
@@ -39,7 +39,7 @@
39/* 39/*
40 * Allow hardware encryption to be disabled. 40 * Allow hardware encryption to be disabled.
41 */ 41 */
42static int modparam_nohwcrypt = 0; 42static int modparam_nohwcrypt;
43module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO); 43module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
44MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 44MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
45 45
@@ -355,7 +355,9 @@ static int rt2500usb_config_key(struct rt2x00_dev *rt2x00dev,
355 * it is known that not work at least on some hardware. 355 * it is known that not work at least on some hardware.
356 * SW crypto will be used in that case. 356 * SW crypto will be used in that case.
357 */ 357 */
358 if (key->alg == ALG_WEP && key->keyidx != 0) 358 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
359 key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
360 key->keyidx != 0)
359 return -EOPNOTSUPP; 361 return -EOPNOTSUPP;
360 362
361 /* 363 /*
@@ -476,9 +478,7 @@ static void rt2500usb_config_intf(struct rt2x00_dev *rt2x00dev,
476 rt2500usb_register_write(rt2x00dev, TXRX_CSR18, reg); 478 rt2500usb_register_write(rt2x00dev, TXRX_CSR18, reg);
477 479
478 rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg); 480 rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg);
479 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 1);
480 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_SYNC, conf->sync); 481 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_SYNC, conf->sync);
481 rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 1);
482 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg); 482 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
483 } 483 }
484 484
@@ -492,24 +492,34 @@ static void rt2500usb_config_intf(struct rt2x00_dev *rt2x00dev,
492} 492}
493 493
494static void rt2500usb_config_erp(struct rt2x00_dev *rt2x00dev, 494static void rt2500usb_config_erp(struct rt2x00_dev *rt2x00dev,
495 struct rt2x00lib_erp *erp) 495 struct rt2x00lib_erp *erp,
496 u32 changed)
496{ 497{
497 u16 reg; 498 u16 reg;
498 499
499 rt2500usb_register_read(rt2x00dev, TXRX_CSR10, &reg); 500 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
500 rt2x00_set_field16(&reg, TXRX_CSR10_AUTORESPOND_PREAMBLE, 501 rt2500usb_register_read(rt2x00dev, TXRX_CSR10, &reg);
501 !!erp->short_preamble); 502 rt2x00_set_field16(&reg, TXRX_CSR10_AUTORESPOND_PREAMBLE,
502 rt2500usb_register_write(rt2x00dev, TXRX_CSR10, reg); 503 !!erp->short_preamble);
504 rt2500usb_register_write(rt2x00dev, TXRX_CSR10, reg);
505 }
503 506
504 rt2500usb_register_write(rt2x00dev, TXRX_CSR11, erp->basic_rates); 507 if (changed & BSS_CHANGED_BASIC_RATES)
508 rt2500usb_register_write(rt2x00dev, TXRX_CSR11,
509 erp->basic_rates);
505 510
506 rt2500usb_register_read(rt2x00dev, TXRX_CSR18, &reg); 511 if (changed & BSS_CHANGED_BEACON_INT) {
507 rt2x00_set_field16(&reg, TXRX_CSR18_INTERVAL, erp->beacon_int * 4); 512 rt2500usb_register_read(rt2x00dev, TXRX_CSR18, &reg);
508 rt2500usb_register_write(rt2x00dev, TXRX_CSR18, reg); 513 rt2x00_set_field16(&reg, TXRX_CSR18_INTERVAL,
514 erp->beacon_int * 4);
515 rt2500usb_register_write(rt2x00dev, TXRX_CSR18, reg);
516 }
509 517
510 rt2500usb_register_write(rt2x00dev, MAC_CSR10, erp->slot_time); 518 if (changed & BSS_CHANGED_ERP_SLOT) {
511 rt2500usb_register_write(rt2x00dev, MAC_CSR11, erp->sifs); 519 rt2500usb_register_write(rt2x00dev, MAC_CSR10, erp->slot_time);
512 rt2500usb_register_write(rt2x00dev, MAC_CSR12, erp->eifs); 520 rt2500usb_register_write(rt2x00dev, MAC_CSR11, erp->sifs);
521 rt2500usb_register_write(rt2x00dev, MAC_CSR12, erp->eifs);
522 }
513} 523}
514 524
515static void rt2500usb_config_ant(struct rt2x00_dev *rt2x00dev, 525static void rt2500usb_config_ant(struct rt2x00_dev *rt2x00dev,
@@ -727,6 +737,55 @@ static void rt2500usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
727} 737}
728 738
729/* 739/*
740 * Queue handlers.
741 */
742static void rt2500usb_start_queue(struct data_queue *queue)
743{
744 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
745 u16 reg;
746
747 switch (queue->qid) {
748 case QID_RX:
749 rt2500usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
750 rt2x00_set_field16(&reg, TXRX_CSR2_DISABLE_RX, 0);
751 rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg);
752 break;
753 case QID_BEACON:
754 rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg);
755 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 1);
756 rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 1);
757 rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 1);
758 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
759 break;
760 default:
761 break;
762 }
763}
764
765static void rt2500usb_stop_queue(struct data_queue *queue)
766{
767 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
768 u16 reg;
769
770 switch (queue->qid) {
771 case QID_RX:
772 rt2500usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
773 rt2x00_set_field16(&reg, TXRX_CSR2_DISABLE_RX, 1);
774 rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg);
775 break;
776 case QID_BEACON:
777 rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg);
778 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 0);
779 rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 0);
780 rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 0);
781 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
782 break;
783 default:
784 break;
785 }
786}
787
788/*
730 * Initialization functions. 789 * Initialization functions.
731 */ 790 */
732static int rt2500usb_init_registers(struct rt2x00_dev *rt2x00dev) 791static int rt2500usb_init_registers(struct rt2x00_dev *rt2x00dev)
@@ -919,18 +978,6 @@ static int rt2500usb_init_bbp(struct rt2x00_dev *rt2x00dev)
919/* 978/*
920 * Device state switch handlers. 979 * Device state switch handlers.
921 */ 980 */
922static void rt2500usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
923 enum dev_state state)
924{
925 u16 reg;
926
927 rt2500usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
928 rt2x00_set_field16(&reg, TXRX_CSR2_DISABLE_RX,
929 (state == STATE_RADIO_RX_OFF) ||
930 (state == STATE_RADIO_RX_OFF_LINK));
931 rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg);
932}
933
934static int rt2500usb_enable_radio(struct rt2x00_dev *rt2x00dev) 981static int rt2500usb_enable_radio(struct rt2x00_dev *rt2x00dev)
935{ 982{
936 /* 983 /*
@@ -1006,16 +1053,8 @@ static int rt2500usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1006 case STATE_RADIO_OFF: 1053 case STATE_RADIO_OFF:
1007 rt2500usb_disable_radio(rt2x00dev); 1054 rt2500usb_disable_radio(rt2x00dev);
1008 break; 1055 break;
1009 case STATE_RADIO_RX_ON:
1010 case STATE_RADIO_RX_ON_LINK:
1011 case STATE_RADIO_RX_OFF:
1012 case STATE_RADIO_RX_OFF_LINK:
1013 rt2500usb_toggle_rx(rt2x00dev, state);
1014 break;
1015 case STATE_RADIO_IRQ_ON: 1056 case STATE_RADIO_IRQ_ON:
1016 case STATE_RADIO_IRQ_ON_ISR:
1017 case STATE_RADIO_IRQ_OFF: 1057 case STATE_RADIO_IRQ_OFF:
1018 case STATE_RADIO_IRQ_OFF_ISR:
1019 /* No support, but no error either */ 1058 /* No support, but no error either */
1020 break; 1059 break;
1021 case STATE_DEEP_SLEEP: 1060 case STATE_DEEP_SLEEP:
@@ -1039,12 +1078,11 @@ static int rt2500usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1039/* 1078/*
1040 * TX descriptor initialization 1079 * TX descriptor initialization
1041 */ 1080 */
1042static void rt2500usb_write_tx_desc(struct rt2x00_dev *rt2x00dev, 1081static void rt2500usb_write_tx_desc(struct queue_entry *entry,
1043 struct sk_buff *skb,
1044 struct txentry_desc *txdesc) 1082 struct txentry_desc *txdesc)
1045{ 1083{
1046 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 1084 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1047 __le32 *txd = (__le32 *) skb->data; 1085 __le32 *txd = (__le32 *) entry->skb->data;
1048 u32 word; 1086 u32 word;
1049 1087
1050 /* 1088 /*
@@ -1062,7 +1100,7 @@ static void rt2500usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1062 (txdesc->rate_mode == RATE_MODE_OFDM)); 1100 (txdesc->rate_mode == RATE_MODE_OFDM));
1063 rt2x00_set_field32(&word, TXD_W0_NEW_SEQ, 1101 rt2x00_set_field32(&word, TXD_W0_NEW_SEQ,
1064 test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags)); 1102 test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags));
1065 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); 1103 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1066 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length); 1104 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1067 rt2x00_set_field32(&word, TXD_W0_CIPHER, !!txdesc->cipher); 1105 rt2x00_set_field32(&word, TXD_W0_CIPHER, !!txdesc->cipher);
1068 rt2x00_set_field32(&word, TXD_W0_KEY_ID, txdesc->key_idx); 1106 rt2x00_set_field32(&word, TXD_W0_KEY_ID, txdesc->key_idx);
@@ -1070,16 +1108,18 @@ static void rt2500usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1070 1108
1071 rt2x00_desc_read(txd, 1, &word); 1109 rt2x00_desc_read(txd, 1, &word);
1072 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset); 1110 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1073 rt2x00_set_field32(&word, TXD_W1_AIFS, txdesc->aifs); 1111 rt2x00_set_field32(&word, TXD_W1_AIFS, entry->queue->aifs);
1074 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min); 1112 rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
1075 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max); 1113 rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
1076 rt2x00_desc_write(txd, 1, word); 1114 rt2x00_desc_write(txd, 1, word);
1077 1115
1078 rt2x00_desc_read(txd, 2, &word); 1116 rt2x00_desc_read(txd, 2, &word);
1079 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal); 1117 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal);
1080 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service); 1118 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service);
1081 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low); 1119 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW,
1082 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high); 1120 txdesc->u.plcp.length_low);
1121 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH,
1122 txdesc->u.plcp.length_high);
1083 rt2x00_desc_write(txd, 2, word); 1123 rt2x00_desc_write(txd, 2, word);
1084 1124
1085 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) { 1125 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
@@ -1127,7 +1167,7 @@ static void rt2500usb_write_beacon(struct queue_entry *entry,
1127 /* 1167 /*
1128 * Write the TX descriptor for the beacon. 1168 * Write the TX descriptor for the beacon.
1129 */ 1169 */
1130 rt2500usb_write_tx_desc(rt2x00dev, entry->skb, txdesc); 1170 rt2500usb_write_tx_desc(entry, txdesc);
1131 1171
1132 /* 1172 /*
1133 * Dump beacon to userspace through debugfs. 1173 * Dump beacon to userspace through debugfs.
@@ -1479,7 +1519,7 @@ static int rt2500usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1479 * Detect if this device has an hardware controlled radio. 1519 * Detect if this device has an hardware controlled radio.
1480 */ 1520 */
1481 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) 1521 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1482 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags); 1522 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
1483 1523
1484 /* 1524 /*
1485 * Read the RSSI <-> dBm offset information. 1525 * Read the RSSI <-> dBm offset information.
@@ -1655,10 +1695,15 @@ static int rt2500usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1655 1695
1656 /* 1696 /*
1657 * Initialize all hw fields. 1697 * Initialize all hw fields.
1698 *
1699 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING unless we are
1700 * capable of sending the buffered frames out after the DTIM
1701 * transmission using rt2x00lib_beacondone. This will send out
1702 * multicast and broadcast traffic immediately instead of buffering it
1703 * infinitly and thus dropping it after some time.
1658 */ 1704 */
1659 rt2x00dev->hw->flags = 1705 rt2x00dev->hw->flags =
1660 IEEE80211_HW_RX_INCLUDES_FCS | 1706 IEEE80211_HW_RX_INCLUDES_FCS |
1661 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1662 IEEE80211_HW_SIGNAL_DBM | 1707 IEEE80211_HW_SIGNAL_DBM |
1663 IEEE80211_HW_SUPPORTS_PS | 1708 IEEE80211_HW_SUPPORTS_PS |
1664 IEEE80211_HW_PS_NULLFUNC_STACK; 1709 IEEE80211_HW_PS_NULLFUNC_STACK;
@@ -1698,19 +1743,23 @@ static int rt2500usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1698 /* 1743 /*
1699 * Create channel information array 1744 * Create channel information array
1700 */ 1745 */
1701 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL); 1746 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
1702 if (!info) 1747 if (!info)
1703 return -ENOMEM; 1748 return -ENOMEM;
1704 1749
1705 spec->channels_info = info; 1750 spec->channels_info = info;
1706 1751
1707 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START); 1752 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1708 for (i = 0; i < 14; i++) 1753 for (i = 0; i < 14; i++) {
1709 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]); 1754 info[i].max_power = MAX_TXPOWER;
1755 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1756 }
1710 1757
1711 if (spec->num_channels > 14) { 1758 if (spec->num_channels > 14) {
1712 for (i = 14; i < spec->num_channels; i++) 1759 for (i = 14; i < spec->num_channels; i++) {
1713 info[i].tx_power1 = DEFAULT_TXPOWER; 1760 info[i].max_power = MAX_TXPOWER;
1761 info[i].default_power1 = DEFAULT_TXPOWER;
1762 }
1714 } 1763 }
1715 1764
1716 return 0; 1765 return 0;
@@ -1741,13 +1790,14 @@ static int rt2500usb_probe_hw(struct rt2x00_dev *rt2x00dev)
1741 /* 1790 /*
1742 * This device requires the atim queue 1791 * This device requires the atim queue
1743 */ 1792 */
1744 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags); 1793 __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
1745 __set_bit(DRIVER_REQUIRE_BEACON_GUARD, &rt2x00dev->flags); 1794 __set_bit(REQUIRE_BEACON_GUARD, &rt2x00dev->cap_flags);
1746 if (!modparam_nohwcrypt) { 1795 if (!modparam_nohwcrypt) {
1747 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags); 1796 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
1748 __set_bit(DRIVER_REQUIRE_COPY_IV, &rt2x00dev->flags); 1797 __set_bit(REQUIRE_COPY_IV, &rt2x00dev->cap_flags);
1749 } 1798 }
1750 __set_bit(DRIVER_SUPPORT_WATCHDOG, &rt2x00dev->flags); 1799 __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
1800 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
1751 1801
1752 /* 1802 /*
1753 * Set the rssi offset. 1803 * Set the rssi offset.
@@ -1773,6 +1823,10 @@ static const struct ieee80211_ops rt2500usb_mac80211_ops = {
1773 .bss_info_changed = rt2x00mac_bss_info_changed, 1823 .bss_info_changed = rt2x00mac_bss_info_changed,
1774 .conf_tx = rt2x00mac_conf_tx, 1824 .conf_tx = rt2x00mac_conf_tx,
1775 .rfkill_poll = rt2x00mac_rfkill_poll, 1825 .rfkill_poll = rt2x00mac_rfkill_poll,
1826 .flush = rt2x00mac_flush,
1827 .set_antenna = rt2x00mac_set_antenna,
1828 .get_antenna = rt2x00mac_get_antenna,
1829 .get_ringparam = rt2x00mac_get_ringparam,
1776}; 1830};
1777 1831
1778static const struct rt2x00lib_ops rt2500usb_rt2x00_ops = { 1832static const struct rt2x00lib_ops rt2500usb_rt2x00_ops = {
@@ -1785,11 +1839,13 @@ static const struct rt2x00lib_ops rt2500usb_rt2x00_ops = {
1785 .link_stats = rt2500usb_link_stats, 1839 .link_stats = rt2500usb_link_stats,
1786 .reset_tuner = rt2500usb_reset_tuner, 1840 .reset_tuner = rt2500usb_reset_tuner,
1787 .watchdog = rt2x00usb_watchdog, 1841 .watchdog = rt2x00usb_watchdog,
1842 .start_queue = rt2500usb_start_queue,
1843 .kick_queue = rt2x00usb_kick_queue,
1844 .stop_queue = rt2500usb_stop_queue,
1845 .flush_queue = rt2x00usb_flush_queue,
1788 .write_tx_desc = rt2500usb_write_tx_desc, 1846 .write_tx_desc = rt2500usb_write_tx_desc,
1789 .write_beacon = rt2500usb_write_beacon, 1847 .write_beacon = rt2500usb_write_beacon,
1790 .get_tx_data_len = rt2500usb_get_tx_data_len, 1848 .get_tx_data_len = rt2500usb_get_tx_data_len,
1791 .kick_tx_queue = rt2x00usb_kick_tx_queue,
1792 .kill_tx_queue = rt2x00usb_kill_tx_queue,
1793 .fill_rxdone = rt2500usb_fill_rxdone, 1849 .fill_rxdone = rt2500usb_fill_rxdone,
1794 .config_shared_key = rt2500usb_config_key, 1850 .config_shared_key = rt2500usb_config_key,
1795 .config_pairwise_key = rt2500usb_config_key, 1851 .config_pairwise_key = rt2500usb_config_key,
@@ -1801,28 +1857,28 @@ static const struct rt2x00lib_ops rt2500usb_rt2x00_ops = {
1801}; 1857};
1802 1858
1803static const struct data_queue_desc rt2500usb_queue_rx = { 1859static const struct data_queue_desc rt2500usb_queue_rx = {
1804 .entry_num = RX_ENTRIES, 1860 .entry_num = 32,
1805 .data_size = DATA_FRAME_SIZE, 1861 .data_size = DATA_FRAME_SIZE,
1806 .desc_size = RXD_DESC_SIZE, 1862 .desc_size = RXD_DESC_SIZE,
1807 .priv_size = sizeof(struct queue_entry_priv_usb), 1863 .priv_size = sizeof(struct queue_entry_priv_usb),
1808}; 1864};
1809 1865
1810static const struct data_queue_desc rt2500usb_queue_tx = { 1866static const struct data_queue_desc rt2500usb_queue_tx = {
1811 .entry_num = TX_ENTRIES, 1867 .entry_num = 32,
1812 .data_size = DATA_FRAME_SIZE, 1868 .data_size = DATA_FRAME_SIZE,
1813 .desc_size = TXD_DESC_SIZE, 1869 .desc_size = TXD_DESC_SIZE,
1814 .priv_size = sizeof(struct queue_entry_priv_usb), 1870 .priv_size = sizeof(struct queue_entry_priv_usb),
1815}; 1871};
1816 1872
1817static const struct data_queue_desc rt2500usb_queue_bcn = { 1873static const struct data_queue_desc rt2500usb_queue_bcn = {
1818 .entry_num = BEACON_ENTRIES, 1874 .entry_num = 1,
1819 .data_size = MGMT_FRAME_SIZE, 1875 .data_size = MGMT_FRAME_SIZE,
1820 .desc_size = TXD_DESC_SIZE, 1876 .desc_size = TXD_DESC_SIZE,
1821 .priv_size = sizeof(struct queue_entry_priv_usb_bcn), 1877 .priv_size = sizeof(struct queue_entry_priv_usb_bcn),
1822}; 1878};
1823 1879
1824static const struct data_queue_desc rt2500usb_queue_atim = { 1880static const struct data_queue_desc rt2500usb_queue_atim = {
1825 .entry_num = ATIM_ENTRIES, 1881 .entry_num = 8,
1826 .data_size = DATA_FRAME_SIZE, 1882 .data_size = DATA_FRAME_SIZE,
1827 .desc_size = TXD_DESC_SIZE, 1883 .desc_size = TXD_DESC_SIZE,
1828 .priv_size = sizeof(struct queue_entry_priv_usb), 1884 .priv_size = sizeof(struct queue_entry_priv_usb),
@@ -1852,58 +1908,54 @@ static const struct rt2x00_ops rt2500usb_ops = {
1852 */ 1908 */
1853static struct usb_device_id rt2500usb_device_table[] = { 1909static struct usb_device_id rt2500usb_device_table[] = {
1854 /* ASUS */ 1910 /* ASUS */
1855 { USB_DEVICE(0x0b05, 0x1706), USB_DEVICE_DATA(&rt2500usb_ops) }, 1911 { USB_DEVICE(0x0b05, 0x1706) },
1856 { USB_DEVICE(0x0b05, 0x1707), USB_DEVICE_DATA(&rt2500usb_ops) }, 1912 { USB_DEVICE(0x0b05, 0x1707) },
1857 /* Belkin */ 1913 /* Belkin */
1858 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt2500usb_ops) }, 1914 { USB_DEVICE(0x050d, 0x7050) },
1859 { USB_DEVICE(0x050d, 0x7051), USB_DEVICE_DATA(&rt2500usb_ops) }, 1915 { USB_DEVICE(0x050d, 0x7051) },
1860 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt2500usb_ops) },
1861 /* Cisco Systems */ 1916 /* Cisco Systems */
1862 { USB_DEVICE(0x13b1, 0x000d), USB_DEVICE_DATA(&rt2500usb_ops) }, 1917 { USB_DEVICE(0x13b1, 0x000d) },
1863 { USB_DEVICE(0x13b1, 0x0011), USB_DEVICE_DATA(&rt2500usb_ops) }, 1918 { USB_DEVICE(0x13b1, 0x0011) },
1864 { USB_DEVICE(0x13b1, 0x001a), USB_DEVICE_DATA(&rt2500usb_ops) }, 1919 { USB_DEVICE(0x13b1, 0x001a) },
1865 /* CNet */
1866 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt2500usb_ops) },
1867 /* Conceptronic */ 1920 /* Conceptronic */
1868 { USB_DEVICE(0x14b2, 0x3c02), USB_DEVICE_DATA(&rt2500usb_ops) }, 1921 { USB_DEVICE(0x14b2, 0x3c02) },
1869 /* D-LINK */ 1922 /* D-LINK */
1870 { USB_DEVICE(0x2001, 0x3c00), USB_DEVICE_DATA(&rt2500usb_ops) }, 1923 { USB_DEVICE(0x2001, 0x3c00) },
1871 /* Gigabyte */ 1924 /* Gigabyte */
1872 { USB_DEVICE(0x1044, 0x8001), USB_DEVICE_DATA(&rt2500usb_ops) }, 1925 { USB_DEVICE(0x1044, 0x8001) },
1873 { USB_DEVICE(0x1044, 0x8007), USB_DEVICE_DATA(&rt2500usb_ops) }, 1926 { USB_DEVICE(0x1044, 0x8007) },
1874 /* Hercules */ 1927 /* Hercules */
1875 { USB_DEVICE(0x06f8, 0xe000), USB_DEVICE_DATA(&rt2500usb_ops) }, 1928 { USB_DEVICE(0x06f8, 0xe000) },
1876 /* Melco */ 1929 /* Melco */
1877 { USB_DEVICE(0x0411, 0x005e), USB_DEVICE_DATA(&rt2500usb_ops) }, 1930 { USB_DEVICE(0x0411, 0x005e) },
1878 { USB_DEVICE(0x0411, 0x0066), USB_DEVICE_DATA(&rt2500usb_ops) }, 1931 { USB_DEVICE(0x0411, 0x0066) },
1879 { USB_DEVICE(0x0411, 0x0067), USB_DEVICE_DATA(&rt2500usb_ops) }, 1932 { USB_DEVICE(0x0411, 0x0067) },
1880 { USB_DEVICE(0x0411, 0x008b), USB_DEVICE_DATA(&rt2500usb_ops) }, 1933 { USB_DEVICE(0x0411, 0x008b) },
1881 { USB_DEVICE(0x0411, 0x0097), USB_DEVICE_DATA(&rt2500usb_ops) }, 1934 { USB_DEVICE(0x0411, 0x0097) },
1882 /* MSI */ 1935 /* MSI */
1883 { USB_DEVICE(0x0db0, 0x6861), USB_DEVICE_DATA(&rt2500usb_ops) }, 1936 { USB_DEVICE(0x0db0, 0x6861) },
1884 { USB_DEVICE(0x0db0, 0x6865), USB_DEVICE_DATA(&rt2500usb_ops) }, 1937 { USB_DEVICE(0x0db0, 0x6865) },
1885 { USB_DEVICE(0x0db0, 0x6869), USB_DEVICE_DATA(&rt2500usb_ops) }, 1938 { USB_DEVICE(0x0db0, 0x6869) },
1886 /* Ralink */ 1939 /* Ralink */
1887 { USB_DEVICE(0x148f, 0x1706), USB_DEVICE_DATA(&rt2500usb_ops) }, 1940 { USB_DEVICE(0x148f, 0x1706) },
1888 { USB_DEVICE(0x148f, 0x2570), USB_DEVICE_DATA(&rt2500usb_ops) }, 1941 { USB_DEVICE(0x148f, 0x2570) },
1889 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt2500usb_ops) }, 1942 { USB_DEVICE(0x148f, 0x9020) },
1890 { USB_DEVICE(0x148f, 0x9020), USB_DEVICE_DATA(&rt2500usb_ops) },
1891 /* Sagem */ 1943 /* Sagem */
1892 { USB_DEVICE(0x079b, 0x004b), USB_DEVICE_DATA(&rt2500usb_ops) }, 1944 { USB_DEVICE(0x079b, 0x004b) },
1893 /* Siemens */ 1945 /* Siemens */
1894 { USB_DEVICE(0x0681, 0x3c06), USB_DEVICE_DATA(&rt2500usb_ops) }, 1946 { USB_DEVICE(0x0681, 0x3c06) },
1895 /* SMC */ 1947 /* SMC */
1896 { USB_DEVICE(0x0707, 0xee13), USB_DEVICE_DATA(&rt2500usb_ops) }, 1948 { USB_DEVICE(0x0707, 0xee13) },
1897 /* Spairon */ 1949 /* Spairon */
1898 { USB_DEVICE(0x114b, 0x0110), USB_DEVICE_DATA(&rt2500usb_ops) }, 1950 { USB_DEVICE(0x114b, 0x0110) },
1899 /* SURECOM */ 1951 /* SURECOM */
1900 { USB_DEVICE(0x0769, 0x11f3), USB_DEVICE_DATA(&rt2500usb_ops) }, 1952 { USB_DEVICE(0x0769, 0x11f3) },
1901 /* Trust */ 1953 /* Trust */
1902 { USB_DEVICE(0x0eb0, 0x9020), USB_DEVICE_DATA(&rt2500usb_ops) }, 1954 { USB_DEVICE(0x0eb0, 0x9020) },
1903 /* VTech */ 1955 /* VTech */
1904 { USB_DEVICE(0x0f88, 0x3012), USB_DEVICE_DATA(&rt2500usb_ops) }, 1956 { USB_DEVICE(0x0f88, 0x3012) },
1905 /* Zinwell */ 1957 /* Zinwell */
1906 { USB_DEVICE(0x5a57, 0x0260), USB_DEVICE_DATA(&rt2500usb_ops) }, 1958 { USB_DEVICE(0x5a57, 0x0260) },
1907 { 0, } 1959 { 0, }
1908}; 1960};
1909 1961
@@ -1914,10 +1966,16 @@ MODULE_SUPPORTED_DEVICE("Ralink RT2570 USB chipset based cards");
1914MODULE_DEVICE_TABLE(usb, rt2500usb_device_table); 1966MODULE_DEVICE_TABLE(usb, rt2500usb_device_table);
1915MODULE_LICENSE("GPL"); 1967MODULE_LICENSE("GPL");
1916 1968
1969static int rt2500usb_probe(struct usb_interface *usb_intf,
1970 const struct usb_device_id *id)
1971{
1972 return rt2x00usb_probe(usb_intf, &rt2500usb_ops);
1973}
1974
1917static struct usb_driver rt2500usb_driver = { 1975static struct usb_driver rt2500usb_driver = {
1918 .name = KBUILD_MODNAME, 1976 .name = KBUILD_MODNAME,
1919 .id_table = rt2500usb_device_table, 1977 .id_table = rt2500usb_device_table,
1920 .probe = rt2x00usb_probe, 1978 .probe = rt2500usb_probe,
1921 .disconnect = rt2x00usb_disconnect, 1979 .disconnect = rt2x00usb_disconnect,
1922 .suspend = rt2x00usb_suspend, 1980 .suspend = rt2x00usb_suspend,
1923 .resume = rt2x00usb_resume, 1981 .resume = rt2x00usb_resume,
diff --git a/drivers/net/wireless/rt2x00/rt2800.h b/drivers/net/wireless/rt2x00/rt2800.h
index ed4ebcdde7c9..f67bc9b31b28 100644
--- a/drivers/net/wireless/rt2x00/rt2800.h
+++ b/drivers/net/wireless/rt2x00/rt2800.h
@@ -1,5 +1,6 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> 2 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> 4 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> 5 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> 6 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
@@ -45,7 +46,13 @@
45 * RF2020 2.4G B/G 46 * RF2020 2.4G B/G
46 * RF3021 2.4G 1T2R 47 * RF3021 2.4G 1T2R
47 * RF3022 2.4G 2T2R 48 * RF3022 2.4G 2T2R
48 * RF3052 2.4G 2T2R 49 * RF3052 2.4G/5G 2T2R
50 * RF2853 2.4G/5G 3T3R
51 * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390)
52 * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392)
53 * RF3853 2.4G/5G 3T3R(RT3883/RT3563/RT3573/RT3593/RT3662)
54 * RF5370 2.4G 1T1R
55 * RF5390 2.4G 1T1R
49 */ 56 */
50#define RF2820 0x0001 57#define RF2820 0x0001
51#define RF2850 0x0002 58#define RF2850 0x0002
@@ -56,7 +63,12 @@
56#define RF3021 0x0007 63#define RF3021 0x0007
57#define RF3022 0x0008 64#define RF3022 0x0008
58#define RF3052 0x0009 65#define RF3052 0x0009
66#define RF2853 0x000a
59#define RF3320 0x000b 67#define RF3320 0x000b
68#define RF3322 0x000c
69#define RF3853 0x000d
70#define RF5370 0x5370
71#define RF5390 0x5390
60 72
61/* 73/*
62 * Chipset revisions. 74 * Chipset revisions.
@@ -69,6 +81,7 @@
69#define REV_RT3071E 0x0211 81#define REV_RT3071E 0x0211
70#define REV_RT3090E 0x0211 82#define REV_RT3090E 0x0211
71#define REV_RT3390E 0x0211 83#define REV_RT3390E 0x0211
84#define REV_RT5390F 0x0502
72 85
73/* 86/*
74 * Signal information. 87 * Signal information.
@@ -113,6 +126,13 @@
113#define E2PROM_CSR_RELOAD FIELD32(0x00000080) 126#define E2PROM_CSR_RELOAD FIELD32(0x00000080)
114 127
115/* 128/*
129 * AUX_CTRL: Aux/PCI-E related configuration
130 */
131#define AUX_CTRL 0x10c
132#define AUX_CTRL_WAKE_PCIE_EN FIELD32(0x00000002)
133#define AUX_CTRL_FORCE_PCIE_CLK FIELD32(0x00000400)
134
135/*
116 * OPT_14: Unknown register used by rt3xxx devices. 136 * OPT_14: Unknown register used by rt3xxx devices.
117 */ 137 */
118#define OPT_14_CSR 0x0114 138#define OPT_14_CSR 0x0114
@@ -205,10 +225,10 @@
205 225
206/* 226/*
207 * WMM_AIFSN_CFG: Aifsn for each EDCA AC 227 * WMM_AIFSN_CFG: Aifsn for each EDCA AC
208 * AIFSN0: AC_BE 228 * AIFSN0: AC_VO
209 * AIFSN1: AC_BK 229 * AIFSN1: AC_VI
210 * AIFSN2: AC_VI 230 * AIFSN2: AC_BE
211 * AIFSN3: AC_VO 231 * AIFSN3: AC_BK
212 */ 232 */
213#define WMM_AIFSN_CFG 0x0214 233#define WMM_AIFSN_CFG 0x0214
214#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f) 234#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
@@ -218,10 +238,10 @@
218 238
219/* 239/*
220 * WMM_CWMIN_CSR: CWmin for each EDCA AC 240 * WMM_CWMIN_CSR: CWmin for each EDCA AC
221 * CWMIN0: AC_BE 241 * CWMIN0: AC_VO
222 * CWMIN1: AC_BK 242 * CWMIN1: AC_VI
223 * CWMIN2: AC_VI 243 * CWMIN2: AC_BE
224 * CWMIN3: AC_VO 244 * CWMIN3: AC_BK
225 */ 245 */
226#define WMM_CWMIN_CFG 0x0218 246#define WMM_CWMIN_CFG 0x0218
227#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f) 247#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
@@ -231,10 +251,10 @@
231 251
232/* 252/*
233 * WMM_CWMAX_CSR: CWmax for each EDCA AC 253 * WMM_CWMAX_CSR: CWmax for each EDCA AC
234 * CWMAX0: AC_BE 254 * CWMAX0: AC_VO
235 * CWMAX1: AC_BK 255 * CWMAX1: AC_VI
236 * CWMAX2: AC_VI 256 * CWMAX2: AC_BE
237 * CWMAX3: AC_VO 257 * CWMAX3: AC_BK
238 */ 258 */
239#define WMM_CWMAX_CFG 0x021c 259#define WMM_CWMAX_CFG 0x021c
240#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f) 260#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
@@ -243,18 +263,18 @@
243#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000) 263#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
244 264
245/* 265/*
246 * AC_TXOP0: AC_BK/AC_BE TXOP register 266 * AC_TXOP0: AC_VO/AC_VI TXOP register
247 * AC0TXOP: AC_BK in unit of 32us 267 * AC0TXOP: AC_VO in unit of 32us
248 * AC1TXOP: AC_BE in unit of 32us 268 * AC1TXOP: AC_VI in unit of 32us
249 */ 269 */
250#define WMM_TXOP0_CFG 0x0220 270#define WMM_TXOP0_CFG 0x0220
251#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff) 271#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
252#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000) 272#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
253 273
254/* 274/*
255 * AC_TXOP1: AC_VO/AC_VI TXOP register 275 * AC_TXOP1: AC_BE/AC_BK TXOP register
256 * AC2TXOP: AC_VI in unit of 32us 276 * AC2TXOP: AC_BE in unit of 32us
257 * AC3TXOP: AC_VO in unit of 32us 277 * AC3TXOP: AC_BK in unit of 32us
258 */ 278 */
259#define WMM_TXOP1_CFG 0x0224 279#define WMM_TXOP1_CFG 0x0224
260#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff) 280#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
@@ -262,6 +282,7 @@
262 282
263/* 283/*
264 * GPIO_CTRL_CFG: 284 * GPIO_CTRL_CFG:
285 * GPIOD: GPIO direction, 0: Output, 1: Input
265 */ 286 */
266#define GPIO_CTRL_CFG 0x0228 287#define GPIO_CTRL_CFG 0x0228
267#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001) 288#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
@@ -272,7 +293,14 @@
272#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020) 293#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
273#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040) 294#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
274#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080) 295#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
275#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100) 296#define GPIO_CTRL_CFG_GPIOD_BIT0 FIELD32(0x00000100)
297#define GPIO_CTRL_CFG_GPIOD_BIT1 FIELD32(0x00000200)
298#define GPIO_CTRL_CFG_GPIOD_BIT2 FIELD32(0x00000400)
299#define GPIO_CTRL_CFG_GPIOD_BIT3 FIELD32(0x00000800)
300#define GPIO_CTRL_CFG_GPIOD_BIT4 FIELD32(0x00001000)
301#define GPIO_CTRL_CFG_GPIOD_BIT5 FIELD32(0x00002000)
302#define GPIO_CTRL_CFG_GPIOD_BIT6 FIELD32(0x00004000)
303#define GPIO_CTRL_CFG_GPIOD_BIT7 FIELD32(0x00008000)
276 304
277/* 305/*
278 * MCU_CMD_CFG 306 * MCU_CMD_CFG
@@ -280,7 +308,7 @@
280#define MCU_CMD_CFG 0x022c 308#define MCU_CMD_CFG 0x022c
281 309
282/* 310/*
283 * AC_BK register offsets 311 * AC_VO register offsets
284 */ 312 */
285#define TX_BASE_PTR0 0x0230 313#define TX_BASE_PTR0 0x0230
286#define TX_MAX_CNT0 0x0234 314#define TX_MAX_CNT0 0x0234
@@ -288,7 +316,7 @@
288#define TX_DTX_IDX0 0x023c 316#define TX_DTX_IDX0 0x023c
289 317
290/* 318/*
291 * AC_BE register offsets 319 * AC_VI register offsets
292 */ 320 */
293#define TX_BASE_PTR1 0x0240 321#define TX_BASE_PTR1 0x0240
294#define TX_MAX_CNT1 0x0244 322#define TX_MAX_CNT1 0x0244
@@ -296,7 +324,7 @@
296#define TX_DTX_IDX1 0x024c 324#define TX_DTX_IDX1 0x024c
297 325
298/* 326/*
299 * AC_VI register offsets 327 * AC_BE register offsets
300 */ 328 */
301#define TX_BASE_PTR2 0x0250 329#define TX_BASE_PTR2 0x0250
302#define TX_MAX_CNT2 0x0254 330#define TX_MAX_CNT2 0x0254
@@ -304,7 +332,7 @@
304#define TX_DTX_IDX2 0x025c 332#define TX_DTX_IDX2 0x025c
305 333
306/* 334/*
307 * AC_VO register offsets 335 * AC_BK register offsets
308 */ 336 */
309#define TX_BASE_PTR3 0x0260 337#define TX_BASE_PTR3 0x0260
310#define TX_MAX_CNT3 0x0264 338#define TX_MAX_CNT3 0x0264
@@ -364,8 +392,12 @@
364 392
365/* 393/*
366 * US_CYC_CNT 394 * US_CYC_CNT
395 * BT_MODE_EN: Bluetooth mode enable
396 * CLOCK CYCLE: Clock cycle count in 1us.
397 * PCI:0x21, PCIE:0x7d, USB:0x1e
367 */ 398 */
368#define US_CYC_CNT 0x02a4 399#define US_CYC_CNT 0x02a4
400#define US_CYC_CNT_BT_MODE_EN FIELD32(0x00000100)
369#define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff) 401#define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff)
370 402
371/* 403/*
@@ -411,10 +443,22 @@
411#define BCN_OFFSET1_BCN7 FIELD32(0xff000000) 443#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
412 444
413/* 445/*
414 * PBF registers 446 * TXRXQ_PCNT: PBF register
415 * Most are for debug. Driver doesn't touch PBF register. 447 * PCNT_TX0Q: Page count for TX hardware queue 0
448 * PCNT_TX1Q: Page count for TX hardware queue 1
449 * PCNT_TX2Q: Page count for TX hardware queue 2
450 * PCNT_RX0Q: Page count for RX hardware queue
416 */ 451 */
417#define TXRXQ_PCNT 0x0438 452#define TXRXQ_PCNT 0x0438
453#define TXRXQ_PCNT_TX0Q FIELD32(0x000000ff)
454#define TXRXQ_PCNT_TX1Q FIELD32(0x0000ff00)
455#define TXRXQ_PCNT_TX2Q FIELD32(0x00ff0000)
456#define TXRXQ_PCNT_RX0Q FIELD32(0xff000000)
457
458/*
459 * PBF register
460 * Debug. Driver doesn't touch PBF register.
461 */
418#define PBF_DBG 0x043c 462#define PBF_DBG 0x043c
419 463
420/* 464/*
@@ -422,7 +466,7 @@
422 */ 466 */
423#define RF_CSR_CFG 0x0500 467#define RF_CSR_CFG 0x0500
424#define RF_CSR_CFG_DATA FIELD32(0x000000ff) 468#define RF_CSR_CFG_DATA FIELD32(0x000000ff)
425#define RF_CSR_CFG_REGNUM FIELD32(0x00001f00) 469#define RF_CSR_CFG_REGNUM FIELD32(0x00003f00)
426#define RF_CSR_CFG_WRITE FIELD32(0x00010000) 470#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
427#define RF_CSR_CFG_BUSY FIELD32(0x00020000) 471#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
428 472
@@ -574,7 +618,7 @@
574 * READ_CONTROL: 0 write BBP, 1 read BBP 618 * READ_CONTROL: 0 write BBP, 1 read BBP
575 * BUSY: ASIC is busy executing BBP commands 619 * BUSY: ASIC is busy executing BBP commands
576 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks 620 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
577 * BBP_RW_MODE: 0 serial, 1 paralell 621 * BBP_RW_MODE: 0 serial, 1 parallel
578 */ 622 */
579#define BBP_CSR_CFG 0x101c 623#define BBP_CSR_CFG 0x101c
580#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff) 624#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
@@ -639,6 +683,18 @@
639#define LED_CFG_LED_POLAR FIELD32(0x40000000) 683#define LED_CFG_LED_POLAR FIELD32(0x40000000)
640 684
641/* 685/*
686 * AMPDU_BA_WINSIZE: Force BlockAck window size
687 * FORCE_WINSIZE_ENABLE:
688 * 0: Disable forcing of BlockAck window size
689 * 1: Enable forcing of BlockAck window size, overwrites values BlockAck
690 * window size values in the TXWI
691 * FORCE_WINSIZE: BlockAck window size
692 */
693#define AMPDU_BA_WINSIZE 0x1040
694#define AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE FIELD32(0x00000020)
695#define AMPDU_BA_WINSIZE_FORCE_WINSIZE FIELD32(0x0000001f)
696
697/*
642 * XIFS_TIME_CFG: MAC timing 698 * XIFS_TIME_CFG: MAC timing
643 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX 699 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
644 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX 700 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
@@ -673,8 +729,18 @@
673 729
674/* 730/*
675 * CH_TIME_CFG: count as channel busy 731 * CH_TIME_CFG: count as channel busy
732 * EIFS_BUSY: Count EIFS as channel busy
733 * NAV_BUSY: Count NAS as channel busy
734 * RX_BUSY: Count RX as channel busy
735 * TX_BUSY: Count TX as channel busy
736 * TMR_EN: Enable channel statistics timer
676 */ 737 */
677#define CH_TIME_CFG 0x110c 738#define CH_TIME_CFG 0x110c
739#define CH_TIME_CFG_EIFS_BUSY FIELD32(0x00000010)
740#define CH_TIME_CFG_NAV_BUSY FIELD32(0x00000008)
741#define CH_TIME_CFG_RX_BUSY FIELD32(0x00000004)
742#define CH_TIME_CFG_TX_BUSY FIELD32(0x00000002)
743#define CH_TIME_CFG_TMR_EN FIELD32(0x00000001)
678 744
679/* 745/*
680 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us 746 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
@@ -698,8 +764,14 @@
698 764
699/* 765/*
700 * TBTT_SYNC_CFG: 766 * TBTT_SYNC_CFG:
767 * BCN_AIFSN: Beacon AIFSN after TBTT interrupt in slots
768 * BCN_CWMIN: Beacon CWMin after TBTT interrupt in slots
701 */ 769 */
702#define TBTT_SYNC_CFG 0x1118 770#define TBTT_SYNC_CFG 0x1118
771#define TBTT_SYNC_CFG_TBTT_ADJUST FIELD32(0x000000ff)
772#define TBTT_SYNC_CFG_BCN_EXP_WIN FIELD32(0x0000ff00)
773#define TBTT_SYNC_CFG_BCN_AIFSN FIELD32(0x000f0000)
774#define TBTT_SYNC_CFG_BCN_CWMIN FIELD32(0x00f00000)
703 775
704/* 776/*
705 * TSF_TIMER_DW0: Local lsb TSF timer, read-only 777 * TSF_TIMER_DW0: Local lsb TSF timer, read-only
@@ -735,16 +807,21 @@
735#define INT_TIMER_EN_GP_TIMER FIELD32(0x00000002) 807#define INT_TIMER_EN_GP_TIMER FIELD32(0x00000002)
736 808
737/* 809/*
738 * CH_IDLE_STA: channel idle time 810 * CH_IDLE_STA: channel idle time (in us)
739 */ 811 */
740#define CH_IDLE_STA 0x1130 812#define CH_IDLE_STA 0x1130
741 813
742/* 814/*
743 * CH_BUSY_STA: channel busy time 815 * CH_BUSY_STA: channel busy time on primary channel (in us)
744 */ 816 */
745#define CH_BUSY_STA 0x1134 817#define CH_BUSY_STA 0x1134
746 818
747/* 819/*
820 * CH_BUSY_STA_SEC: channel busy time on secondary channel in HT40 mode (in us)
821 */
822#define CH_BUSY_STA_SEC 0x1138
823
824/*
748 * MAC_STATUS_CFG: 825 * MAC_STATUS_CFG:
749 * BBP_RF_BUSY: When set to 0, BBP and RF are stable. 826 * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
750 * if 1 or higher one of the 2 registers is busy. 827 * if 1 or higher one of the 2 registers is busy.
@@ -936,8 +1013,31 @@
936 1013
937/* 1014/*
938 * TXOP_CTRL_CFG: 1015 * TXOP_CTRL_CFG:
1016 * TIMEOUT_TRUN_EN: Enable/Disable TXOP timeout truncation
1017 * AC_TRUN_EN: Enable/Disable truncation for AC change
1018 * TXRATEGRP_TRUN_EN: Enable/Disable truncation for TX rate group change
1019 * USER_MODE_TRUN_EN: Enable/Disable truncation for user TXOP mode
1020 * MIMO_PS_TRUN_EN: Enable/Disable truncation for MIMO PS RTS/CTS
1021 * RESERVED_TRUN_EN: Reserved
1022 * LSIG_TXOP_EN: Enable/Disable L-SIG TXOP protection
1023 * EXT_CCA_EN: Enable/Disable extension channel CCA reference (Defer 40Mhz
1024 * transmissions if extension CCA is clear).
1025 * EXT_CCA_DLY: Extension CCA signal delay time (unit: us)
1026 * EXT_CWMIN: CwMin for extension channel backoff
1027 * 0: Disabled
1028 *
939 */ 1029 */
940#define TXOP_CTRL_CFG 0x1340 1030#define TXOP_CTRL_CFG 0x1340
1031#define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN FIELD32(0x00000001)
1032#define TXOP_CTRL_CFG_AC_TRUN_EN FIELD32(0x00000002)
1033#define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN FIELD32(0x00000004)
1034#define TXOP_CTRL_CFG_USER_MODE_TRUN_EN FIELD32(0x00000008)
1035#define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN FIELD32(0x00000010)
1036#define TXOP_CTRL_CFG_RESERVED_TRUN_EN FIELD32(0x00000020)
1037#define TXOP_CTRL_CFG_LSIG_TXOP_EN FIELD32(0x00000040)
1038#define TXOP_CTRL_CFG_EXT_CCA_EN FIELD32(0x00000080)
1039#define TXOP_CTRL_CFG_EXT_CCA_DLY FIELD32(0x0000ff00)
1040#define TXOP_CTRL_CFG_EXT_CWMIN FIELD32(0x000f0000)
941 1041
942/* 1042/*
943 * TX_RTS_CFG: 1043 * TX_RTS_CFG:
@@ -1056,8 +1156,8 @@
1056 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd) 1156 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
1057 * PROTECT_CTRL: Protection control frame type for CCK TX 1157 * PROTECT_CTRL: Protection control frame type for CCK TX
1058 * 0:none, 1:RTS/CTS, 2:CTS-to-self 1158 * 0:none, 1:RTS/CTS, 2:CTS-to-self
1059 * PROTECT_NAV: TXOP protection type for CCK TX 1159 * PROTECT_NAV_SHORT: TXOP protection type for CCK TX with short NAV
1060 * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect 1160 * PROTECT_NAV_LONG: TXOP protection type for CCK TX with long NAV
1061 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow 1161 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
1062 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow 1162 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
1063 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow 1163 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
@@ -1069,7 +1169,8 @@
1069#define CCK_PROT_CFG 0x1364 1169#define CCK_PROT_CFG 0x1364
1070#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1170#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1071#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1171#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1072#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) 1172#define CCK_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1173#define CCK_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1073#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1174#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1074#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1175#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1075#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1176#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
@@ -1084,7 +1185,8 @@
1084#define OFDM_PROT_CFG 0x1368 1185#define OFDM_PROT_CFG 0x1368
1085#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1186#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1086#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1187#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1087#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) 1188#define OFDM_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1189#define OFDM_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1088#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1190#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1089#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1191#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1090#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1192#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
@@ -1099,7 +1201,8 @@
1099#define MM20_PROT_CFG 0x136c 1201#define MM20_PROT_CFG 0x136c
1100#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1202#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1101#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1203#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1102#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) 1204#define MM20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1205#define MM20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1103#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1206#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1104#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1207#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1105#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1208#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
@@ -1114,7 +1217,8 @@
1114#define MM40_PROT_CFG 0x1370 1217#define MM40_PROT_CFG 0x1370
1115#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1218#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1116#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1219#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1117#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) 1220#define MM40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1221#define MM40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1118#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1222#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1119#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1223#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1120#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1224#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
@@ -1129,7 +1233,8 @@
1129#define GF20_PROT_CFG 0x1374 1233#define GF20_PROT_CFG 0x1374
1130#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1234#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1131#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1235#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1132#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) 1236#define GF20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1237#define GF20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1133#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1238#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1134#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1239#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1135#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1240#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
@@ -1144,7 +1249,8 @@
1144#define GF40_PROT_CFG 0x1378 1249#define GF40_PROT_CFG 0x1378
1145#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1250#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1146#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1251#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1147#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) 1252#define GF40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1253#define GF40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1148#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1254#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1149#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1255#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1150#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1256#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
@@ -1318,11 +1424,34 @@
1318#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000) 1424#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1319 1425
1320/* 1426/*
1321 * TX_STA_FIFO: TX Result for specific PID status fifo register 1427 * TX_STA_FIFO: TX Result for specific PID status fifo register.
1428 *
1429 * This register is implemented as FIFO with 16 entries in the HW. Each
1430 * register read fetches the next tx result. If the FIFO is full because
1431 * it wasn't read fast enough after the according interrupt (TX_FIFO_STATUS)
1432 * triggered, the hw seems to simply drop further tx results.
1433 *
1434 * VALID: 1: this tx result is valid
1435 * 0: no valid tx result -> driver should stop reading
1436 * PID_TYPE: The PID latched from the PID field in the TXWI, can be used
1437 * to match a frame with its tx result (even though the PID is
1438 * only 4 bits wide).
1439 * PID_QUEUE: Part of PID_TYPE, this is the queue index number (0-3)
1440 * PID_ENTRY: Part of PID_TYPE, this is the queue entry index number (1-3)
1441 * This identification number is calculated by ((idx % 3) + 1).
1442 * TX_SUCCESS: Indicates tx success (1) or failure (0)
1443 * TX_AGGRE: Indicates if the frame was part of an aggregate (1) or not (0)
1444 * TX_ACK_REQUIRED: Indicates if the frame needed to get ack'ed (1) or not (0)
1445 * WCID: The wireless client ID.
1446 * MCS: The tx rate used during the last transmission of this frame, be it
1447 * successful or not.
1448 * PHYMODE: The phymode used for the transmission.
1322 */ 1449 */
1323#define TX_STA_FIFO 0x1718 1450#define TX_STA_FIFO 0x1718
1324#define TX_STA_FIFO_VALID FIELD32(0x00000001) 1451#define TX_STA_FIFO_VALID FIELD32(0x00000001)
1325#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e) 1452#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1453#define TX_STA_FIFO_PID_QUEUE FIELD32(0x00000006)
1454#define TX_STA_FIFO_PID_ENTRY FIELD32(0x00000018)
1326#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020) 1455#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1327#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040) 1456#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1328#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080) 1457#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
@@ -1405,6 +1534,24 @@
1405 1534
1406/* 1535/*
1407 * Security key table memory. 1536 * Security key table memory.
1537 *
1538 * The pairwise key table shares some memory with the beacon frame
1539 * buffers 6 and 7. That basically means that when beacon 6 & 7
1540 * are used we should only use the reduced pairwise key table which
1541 * has a maximum of 222 entries.
1542 *
1543 * ---------------------------------------------
1544 * |0x4000 | Pairwise Key | Reduced Pairwise |
1545 * | | Table | Key Table |
1546 * | | Size: 256 * 32 | Size: 222 * 32 |
1547 * |0x5BC0 | |-------------------
1548 * | | | Beacon 6 |
1549 * |0x5DC0 | |-------------------
1550 * | | | Beacon 7 |
1551 * |0x5FC0 | |-------------------
1552 * |0x5FFF | |
1553 * --------------------------
1554 *
1408 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry 1555 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1409 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry 1556 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1410 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry 1557 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
@@ -1420,17 +1567,17 @@
1420#define SHARED_KEY_MODE_BASE 0x7000 1567#define SHARED_KEY_MODE_BASE 0x7000
1421 1568
1422#define MAC_WCID_ENTRY(__idx) \ 1569#define MAC_WCID_ENTRY(__idx) \
1423 ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) ) 1570 (MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)))
1424#define PAIRWISE_KEY_ENTRY(__idx) \ 1571#define PAIRWISE_KEY_ENTRY(__idx) \
1425 ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) ) 1572 (PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
1426#define MAC_IVEIV_ENTRY(__idx) \ 1573#define MAC_IVEIV_ENTRY(__idx) \
1427 ( MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)) ) 1574 (MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)))
1428#define MAC_WCID_ATTR_ENTRY(__idx) \ 1575#define MAC_WCID_ATTR_ENTRY(__idx) \
1429 ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) ) 1576 (MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)))
1430#define SHARED_KEY_ENTRY(__idx) \ 1577#define SHARED_KEY_ENTRY(__idx) \
1431 ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) ) 1578 (SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
1432#define SHARED_KEY_MODE_ENTRY(__idx) \ 1579#define SHARED_KEY_MODE_ENTRY(__idx) \
1433 ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) ) 1580 (SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)))
1434 1581
1435struct mac_wcid_entry { 1582struct mac_wcid_entry {
1436 u8 mac[6]; 1583 u8 mac[6];
@@ -1554,7 +1701,8 @@ struct mac_iveiv_entry {
1554 * 2. Extract memory from FCE table for BCN 4~5 1701 * 2. Extract memory from FCE table for BCN 4~5
1555 * 3. Extract memory from Pair-wise key table for BCN 6~7 1702 * 3. Extract memory from Pair-wise key table for BCN 6~7
1556 * It occupied those memory of wcid 238~253 for BCN 6 1703 * It occupied those memory of wcid 238~253 for BCN 6
1557 * and wcid 222~237 for BCN 7 1704 * and wcid 222~237 for BCN 7 (see Security key table memory
1705 * for more info).
1558 * 1706 *
1559 * IMPORTANT NOTE: Not sure why legacy driver does this, 1707 * IMPORTANT NOTE: Not sure why legacy driver does this,
1560 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6. 1708 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
@@ -1569,9 +1717,9 @@ struct mac_iveiv_entry {
1569#define HW_BEACON_BASE7 0x5bc0 1717#define HW_BEACON_BASE7 0x5bc0
1570 1718
1571#define HW_BEACON_OFFSET(__index) \ 1719#define HW_BEACON_OFFSET(__index) \
1572 ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \ 1720 (((__index) < 4) ? (HW_BEACON_BASE0 + (__index * 0x0200)) : \
1573 (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \ 1721 (((__index) < 6) ? (HW_BEACON_BASE4 + ((__index - 4) * 0x0200)) : \
1574 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) ) 1722 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))))
1575 1723
1576/* 1724/*
1577 * BBP registers. 1725 * BBP registers.
@@ -1579,11 +1727,14 @@ struct mac_iveiv_entry {
1579 */ 1727 */
1580 1728
1581/* 1729/*
1582 * BBP 1: TX Antenna & Power 1730 * BBP 1: TX Antenna & Power Control
1583 * POWER: 0 - normal, 1 - drop tx power by 6dBm, 2 - drop tx power by 12dBm, 1731 * POWER_CTRL:
1584 * 3 - increase tx power by 6dBm 1732 * 0 - normal,
1733 * 1 - drop tx power by 6dBm,
1734 * 2 - drop tx power by 12dBm,
1735 * 3 - increase tx power by 6dBm
1585 */ 1736 */
1586#define BBP1_TX_POWER FIELD8(0x07) 1737#define BBP1_TX_POWER_CTRL FIELD8(0x07)
1587#define BBP1_TX_ANTENNA FIELD8(0x18) 1738#define BBP1_TX_ANTENNA FIELD8(0x18)
1588 1739
1589/* 1740/*
@@ -1597,6 +1748,13 @@ struct mac_iveiv_entry {
1597 */ 1748 */
1598#define BBP4_TX_BF FIELD8(0x01) 1749#define BBP4_TX_BF FIELD8(0x01)
1599#define BBP4_BANDWIDTH FIELD8(0x18) 1750#define BBP4_BANDWIDTH FIELD8(0x18)
1751#define BBP4_MAC_IF_CTRL FIELD8(0x40)
1752
1753/*
1754 * BBP 109
1755 */
1756#define BBP109_TX0_POWER FIELD8(0x0f)
1757#define BBP109_TX1_POWER FIELD8(0xf0)
1600 1758
1601/* 1759/*
1602 * BBP 138: Unknown 1760 * BBP 138: Unknown
@@ -1607,6 +1765,11 @@ struct mac_iveiv_entry {
1607#define BBP138_TX_DAC2 FIELD8(0x40) 1765#define BBP138_TX_DAC2 FIELD8(0x40)
1608 1766
1609/* 1767/*
1768 * BBP 152: Rx Ant
1769 */
1770#define BBP152_RX_DEFAULT_ANT FIELD8(0x80)
1771
1772/*
1610 * RFCSR registers 1773 * RFCSR registers
1611 * The wordsize of the RFCSR is 8 bits. 1774 * The wordsize of the RFCSR is 8 bits.
1612 */ 1775 */
@@ -1615,12 +1778,18 @@ struct mac_iveiv_entry {
1615 * RFCSR 1: 1778 * RFCSR 1:
1616 */ 1779 */
1617#define RFCSR1_RF_BLOCK_EN FIELD8(0x01) 1780#define RFCSR1_RF_BLOCK_EN FIELD8(0x01)
1781#define RFCSR1_PLL_PD FIELD8(0x02)
1618#define RFCSR1_RX0_PD FIELD8(0x04) 1782#define RFCSR1_RX0_PD FIELD8(0x04)
1619#define RFCSR1_TX0_PD FIELD8(0x08) 1783#define RFCSR1_TX0_PD FIELD8(0x08)
1620#define RFCSR1_RX1_PD FIELD8(0x10) 1784#define RFCSR1_RX1_PD FIELD8(0x10)
1621#define RFCSR1_TX1_PD FIELD8(0x20) 1785#define RFCSR1_TX1_PD FIELD8(0x20)
1622 1786
1623/* 1787/*
1788 * RFCSR 2:
1789 */
1790#define RFCSR2_RESCAL_EN FIELD8(0x80)
1791
1792/*
1624 * RFCSR 6: 1793 * RFCSR 6:
1625 */ 1794 */
1626#define RFCSR6_R1 FIELD8(0x03) 1795#define RFCSR6_R1 FIELD8(0x03)
@@ -1632,6 +1801,11 @@ struct mac_iveiv_entry {
1632#define RFCSR7_RF_TUNING FIELD8(0x01) 1801#define RFCSR7_RF_TUNING FIELD8(0x01)
1633 1802
1634/* 1803/*
1804 * RFCSR 11:
1805 */
1806#define RFCSR11_R FIELD8(0x03)
1807
1808/*
1635 * RFCSR 12: 1809 * RFCSR 12:
1636 */ 1810 */
1637#define RFCSR12_TX_POWER FIELD8(0x1f) 1811#define RFCSR12_TX_POWER FIELD8(0x1f)
@@ -1652,6 +1826,7 @@ struct mac_iveiv_entry {
1652#define RFCSR17_TXMIXER_GAIN FIELD8(0x07) 1826#define RFCSR17_TXMIXER_GAIN FIELD8(0x07)
1653#define RFCSR17_TX_LO1_EN FIELD8(0x08) 1827#define RFCSR17_TX_LO1_EN FIELD8(0x08)
1654#define RFCSR17_R FIELD8(0x20) 1828#define RFCSR17_R FIELD8(0x20)
1829#define RFCSR17_CODE FIELD8(0x7f)
1655 1830
1656/* 1831/*
1657 * RFCSR 20: 1832 * RFCSR 20:
@@ -1684,9 +1859,33 @@ struct mac_iveiv_entry {
1684/* 1859/*
1685 * RFCSR 30: 1860 * RFCSR 30:
1686 */ 1861 */
1862#define RFCSR30_TX_H20M FIELD8(0x02)
1863#define RFCSR30_RX_H20M FIELD8(0x04)
1864#define RFCSR30_RX_VCM FIELD8(0x18)
1687#define RFCSR30_RF_CALIBRATION FIELD8(0x80) 1865#define RFCSR30_RF_CALIBRATION FIELD8(0x80)
1688 1866
1689/* 1867/*
1868 * RFCSR 31:
1869 */
1870#define RFCSR31_RX_AGC_FC FIELD8(0x1f)
1871#define RFCSR31_RX_H20M FIELD8(0x20)
1872
1873/*
1874 * RFCSR 38:
1875 */
1876#define RFCSR38_RX_LO1_EN FIELD8(0x20)
1877
1878/*
1879 * RFCSR 39:
1880 */
1881#define RFCSR39_RX_LO2_EN FIELD8(0x80)
1882
1883/*
1884 * RFCSR 49:
1885 */
1886#define RFCSR49_TX FIELD8(0x3f)
1887
1888/*
1690 * RF registers 1889 * RF registers
1691 */ 1890 */
1692 1891
@@ -1719,6 +1918,11 @@ struct mac_iveiv_entry {
1719 */ 1918 */
1720 1919
1721/* 1920/*
1921 * Chip ID
1922 */
1923#define EEPROM_CHIP_ID 0x0000
1924
1925/*
1722 * EEPROM Version 1926 * EEPROM Version
1723 */ 1927 */
1724#define EEPROM_VERSION 0x0001 1928#define EEPROM_VERSION 0x0001
@@ -1739,32 +1943,51 @@ struct mac_iveiv_entry {
1739#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00) 1943#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1740 1944
1741/* 1945/*
1742 * EEPROM ANTENNA config 1946 * EEPROM NIC Configuration 0
1743 * RXPATH: 1: 1R, 2: 2R, 3: 3R 1947 * RXPATH: 1: 1R, 2: 2R, 3: 3R
1744 * TXPATH: 1: 1T, 2: 2T 1948 * TXPATH: 1: 1T, 2: 2T, 3: 3T
1745 */ 1949 * RF_TYPE: RFIC type
1746#define EEPROM_ANTENNA 0x001a 1950 */
1747#define EEPROM_ANTENNA_RXPATH FIELD16(0x000f) 1951#define EEPROM_NIC_CONF0 0x001a
1748#define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0) 1952#define EEPROM_NIC_CONF0_RXPATH FIELD16(0x000f)
1749#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00) 1953#define EEPROM_NIC_CONF0_TXPATH FIELD16(0x00f0)
1750 1954#define EEPROM_NIC_CONF0_RF_TYPE FIELD16(0x0f00)
1751/* 1955
1752 * EEPROM NIC config 1956/*
1753 * CARDBUS_ACCEL: 0 - enable, 1 - disable 1957 * EEPROM NIC Configuration 1
1754 */ 1958 * HW_RADIO: 0: disable, 1: enable
1755#define EEPROM_NIC 0x001b 1959 * EXTERNAL_TX_ALC: 0: disable, 1: enable
1756#define EEPROM_NIC_HW_RADIO FIELD16(0x0001) 1960 * EXTERNAL_LNA_2G: 0: disable, 1: enable
1757#define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002) 1961 * EXTERNAL_LNA_5G: 0: disable, 1: enable
1758#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004) 1962 * CARDBUS_ACCEL: 0: enable, 1: disable
1759#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008) 1963 * BW40M_SB_2G: 0: disable, 1: enable
1760#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010) 1964 * BW40M_SB_5G: 0: disable, 1: enable
1761#define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020) 1965 * WPS_PBC: 0: disable, 1: enable
1762#define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040) 1966 * BW40M_2G: 0: enable, 1: disable
1763#define EEPROM_NIC_WPS_PBC FIELD16(0x0080) 1967 * BW40M_5G: 0: enable, 1: disable
1764#define EEPROM_NIC_BW40M_BG FIELD16(0x0100) 1968 * BROADBAND_EXT_LNA: 0: disable, 1: enable
1765#define EEPROM_NIC_BW40M_A FIELD16(0x0200) 1969 * ANT_DIVERSITY: 00: Disable, 01: Diversity,
1766#define EEPROM_NIC_ANT_DIVERSITY FIELD16(0x0800) 1970 * 10: Main antenna, 11: Aux antenna
1767#define EEPROM_NIC_DAC_TEST FIELD16(0x8000) 1971 * INTERNAL_TX_ALC: 0: disable, 1: enable
1972 * BT_COEXIST: 0: disable, 1: enable
1973 * DAC_TEST: 0: disable, 1: enable
1974 */
1975#define EEPROM_NIC_CONF1 0x001b
1976#define EEPROM_NIC_CONF1_HW_RADIO FIELD16(0x0001)
1977#define EEPROM_NIC_CONF1_EXTERNAL_TX_ALC FIELD16(0x0002)
1978#define EEPROM_NIC_CONF1_EXTERNAL_LNA_2G FIELD16(0x0004)
1979#define EEPROM_NIC_CONF1_EXTERNAL_LNA_5G FIELD16(0x0008)
1980#define EEPROM_NIC_CONF1_CARDBUS_ACCEL FIELD16(0x0010)
1981#define EEPROM_NIC_CONF1_BW40M_SB_2G FIELD16(0x0020)
1982#define EEPROM_NIC_CONF1_BW40M_SB_5G FIELD16(0x0040)
1983#define EEPROM_NIC_CONF1_WPS_PBC FIELD16(0x0080)
1984#define EEPROM_NIC_CONF1_BW40M_2G FIELD16(0x0100)
1985#define EEPROM_NIC_CONF1_BW40M_5G FIELD16(0x0200)
1986#define EEPROM_NIC_CONF1_BROADBAND_EXT_LNA FIELD16(0x400)
1987#define EEPROM_NIC_CONF1_ANT_DIVERSITY FIELD16(0x1800)
1988#define EEPROM_NIC_CONF1_INTERNAL_TX_ALC FIELD16(0x2000)
1989#define EEPROM_NIC_CONF1_BT_COEXIST FIELD16(0x4000)
1990#define EEPROM_NIC_CONF1_DAC_TEST FIELD16(0x8000)
1768 1991
1769/* 1992/*
1770 * EEPROM frequency 1993 * EEPROM frequency
@@ -1786,9 +2009,9 @@ struct mac_iveiv_entry {
1786 * POLARITY_GPIO_4: Polarity GPIO4 setting. 2009 * POLARITY_GPIO_4: Polarity GPIO4 setting.
1787 * LED_MODE: Led mode. 2010 * LED_MODE: Led mode.
1788 */ 2011 */
1789#define EEPROM_LED1 0x001e 2012#define EEPROM_LED_AG_CONF 0x001e
1790#define EEPROM_LED2 0x001f 2013#define EEPROM_LED_ACT_CONF 0x001f
1791#define EEPROM_LED3 0x0020 2014#define EEPROM_LED_POLARITY 0x0020
1792#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001) 2015#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
1793#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002) 2016#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
1794#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004) 2017#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
@@ -1800,6 +2023,17 @@ struct mac_iveiv_entry {
1800#define EEPROM_LED_LED_MODE FIELD16(0x1f00) 2023#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
1801 2024
1802/* 2025/*
2026 * EEPROM NIC Configuration 2
2027 * RX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
2028 * TX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
2029 * CRYSTAL: 00: Reserved, 01: One crystal, 10: Two crystal, 11: Reserved
2030 */
2031#define EEPROM_NIC_CONF2 0x0021
2032#define EEPROM_NIC_CONF2_RX_STREAM FIELD16(0x000f)
2033#define EEPROM_NIC_CONF2_TX_STREAM FIELD16(0x00f0)
2034#define EEPROM_NIC_CONF2_CRYSTAL FIELD16(0x0600)
2035
2036/*
1803 * EEPROM LNA 2037 * EEPROM LNA
1804 */ 2038 */
1805#define EEPROM_LNA 0x0022 2039#define EEPROM_LNA 0x0022
@@ -1841,16 +2075,26 @@ struct mac_iveiv_entry {
1841#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00) 2075#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
1842 2076
1843/* 2077/*
2078 * EEPROM EIRP Maximum TX power values(unit: dbm)
2079 */
2080#define EEPROM_EIRP_MAX_TX_POWER 0x0027
2081#define EEPROM_EIRP_MAX_TX_POWER_2GHZ FIELD16(0x00ff)
2082#define EEPROM_EIRP_MAX_TX_POWER_5GHZ FIELD16(0xff00)
2083
2084/*
1844 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power. 2085 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
1845 * This is delta in 40MHZ. 2086 * This is delta in 40MHZ.
1846 * VALUE: Tx Power dalta value (MAX=4) 2087 * VALUE: Tx Power dalta value, MAX=4(unit: dbm)
1847 * TYPE: 1: Plus the delta value, 0: minus the delta value 2088 * TYPE: 1: Plus the delta value, 0: minus the delta value
1848 * TXPOWER: Enable: 2089 * ENABLE: enable tx power compensation for 40BW
1849 */ 2090 */
1850#define EEPROM_TXPOWER_DELTA 0x0028 2091#define EEPROM_TXPOWER_DELTA 0x0028
1851#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f) 2092#define EEPROM_TXPOWER_DELTA_VALUE_2G FIELD16(0x003f)
1852#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040) 2093#define EEPROM_TXPOWER_DELTA_TYPE_2G FIELD16(0x0040)
1853#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080) 2094#define EEPROM_TXPOWER_DELTA_ENABLE_2G FIELD16(0x0080)
2095#define EEPROM_TXPOWER_DELTA_VALUE_5G FIELD16(0x3f00)
2096#define EEPROM_TXPOWER_DELTA_TYPE_5G FIELD16(0x4000)
2097#define EEPROM_TXPOWER_DELTA_ENABLE_5G FIELD16(0x8000)
1854 2098
1855/* 2099/*
1856 * EEPROM TXPOWER 802.11BG 2100 * EEPROM TXPOWER 802.11BG
@@ -1862,6 +2106,59 @@ struct mac_iveiv_entry {
1862#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00) 2106#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
1863 2107
1864/* 2108/*
2109 * EEPROM temperature compensation boundaries 802.11BG
2110 * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
2111 * reduced by (agc_step * -4)
2112 * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
2113 * reduced by (agc_step * -3)
2114 */
2115#define EEPROM_TSSI_BOUND_BG1 0x0037
2116#define EEPROM_TSSI_BOUND_BG1_MINUS4 FIELD16(0x00ff)
2117#define EEPROM_TSSI_BOUND_BG1_MINUS3 FIELD16(0xff00)
2118
2119/*
2120 * EEPROM temperature compensation boundaries 802.11BG
2121 * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
2122 * reduced by (agc_step * -2)
2123 * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
2124 * reduced by (agc_step * -1)
2125 */
2126#define EEPROM_TSSI_BOUND_BG2 0x0038
2127#define EEPROM_TSSI_BOUND_BG2_MINUS2 FIELD16(0x00ff)
2128#define EEPROM_TSSI_BOUND_BG2_MINUS1 FIELD16(0xff00)
2129
2130/*
2131 * EEPROM temperature compensation boundaries 802.11BG
2132 * REF: Reference TSSI value, no tx power changes needed
2133 * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
2134 * increased by (agc_step * 1)
2135 */
2136#define EEPROM_TSSI_BOUND_BG3 0x0039
2137#define EEPROM_TSSI_BOUND_BG3_REF FIELD16(0x00ff)
2138#define EEPROM_TSSI_BOUND_BG3_PLUS1 FIELD16(0xff00)
2139
2140/*
2141 * EEPROM temperature compensation boundaries 802.11BG
2142 * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
2143 * increased by (agc_step * 2)
2144 * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
2145 * increased by (agc_step * 3)
2146 */
2147#define EEPROM_TSSI_BOUND_BG4 0x003a
2148#define EEPROM_TSSI_BOUND_BG4_PLUS2 FIELD16(0x00ff)
2149#define EEPROM_TSSI_BOUND_BG4_PLUS3 FIELD16(0xff00)
2150
2151/*
2152 * EEPROM temperature compensation boundaries 802.11BG
2153 * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
2154 * increased by (agc_step * 4)
2155 * AGC_STEP: Temperature compensation step.
2156 */
2157#define EEPROM_TSSI_BOUND_BG5 0x003b
2158#define EEPROM_TSSI_BOUND_BG5_PLUS4 FIELD16(0x00ff)
2159#define EEPROM_TSSI_BOUND_BG5_AGC_STEP FIELD16(0xff00)
2160
2161/*
1865 * EEPROM TXPOWER 802.11A 2162 * EEPROM TXPOWER 802.11A
1866 */ 2163 */
1867#define EEPROM_TXPOWER_A1 0x003c 2164#define EEPROM_TXPOWER_A1 0x003c
@@ -1871,6 +2168,59 @@ struct mac_iveiv_entry {
1871#define EEPROM_TXPOWER_A_2 FIELD16(0xff00) 2168#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
1872 2169
1873/* 2170/*
2171 * EEPROM temperature compensation boundaries 802.11A
2172 * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
2173 * reduced by (agc_step * -4)
2174 * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
2175 * reduced by (agc_step * -3)
2176 */
2177#define EEPROM_TSSI_BOUND_A1 0x006a
2178#define EEPROM_TSSI_BOUND_A1_MINUS4 FIELD16(0x00ff)
2179#define EEPROM_TSSI_BOUND_A1_MINUS3 FIELD16(0xff00)
2180
2181/*
2182 * EEPROM temperature compensation boundaries 802.11A
2183 * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
2184 * reduced by (agc_step * -2)
2185 * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
2186 * reduced by (agc_step * -1)
2187 */
2188#define EEPROM_TSSI_BOUND_A2 0x006b
2189#define EEPROM_TSSI_BOUND_A2_MINUS2 FIELD16(0x00ff)
2190#define EEPROM_TSSI_BOUND_A2_MINUS1 FIELD16(0xff00)
2191
2192/*
2193 * EEPROM temperature compensation boundaries 802.11A
2194 * REF: Reference TSSI value, no tx power changes needed
2195 * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
2196 * increased by (agc_step * 1)
2197 */
2198#define EEPROM_TSSI_BOUND_A3 0x006c
2199#define EEPROM_TSSI_BOUND_A3_REF FIELD16(0x00ff)
2200#define EEPROM_TSSI_BOUND_A3_PLUS1 FIELD16(0xff00)
2201
2202/*
2203 * EEPROM temperature compensation boundaries 802.11A
2204 * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
2205 * increased by (agc_step * 2)
2206 * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
2207 * increased by (agc_step * 3)
2208 */
2209#define EEPROM_TSSI_BOUND_A4 0x006d
2210#define EEPROM_TSSI_BOUND_A4_PLUS2 FIELD16(0x00ff)
2211#define EEPROM_TSSI_BOUND_A4_PLUS3 FIELD16(0xff00)
2212
2213/*
2214 * EEPROM temperature compensation boundaries 802.11A
2215 * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
2216 * increased by (agc_step * 4)
2217 * AGC_STEP: Temperature compensation step.
2218 */
2219#define EEPROM_TSSI_BOUND_A5 0x006e
2220#define EEPROM_TSSI_BOUND_A5_PLUS4 FIELD16(0x00ff)
2221#define EEPROM_TSSI_BOUND_A5_AGC_STEP FIELD16(0xff00)
2222
2223/*
1874 * EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode 2224 * EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode
1875 */ 2225 */
1876#define EEPROM_TXPOWER_BYRATE 0x006f 2226#define EEPROM_TXPOWER_BYRATE 0x006f
@@ -1898,11 +2248,12 @@ struct mac_iveiv_entry {
1898#define MCU_CURRENT 0x36 2248#define MCU_CURRENT 0x36
1899#define MCU_LED 0x50 2249#define MCU_LED 0x50
1900#define MCU_LED_STRENGTH 0x51 2250#define MCU_LED_STRENGTH 0x51
1901#define MCU_LED_1 0x52 2251#define MCU_LED_AG_CONF 0x52
1902#define MCU_LED_2 0x53 2252#define MCU_LED_ACT_CONF 0x53
1903#define MCU_LED_3 0x54 2253#define MCU_LED_LED_POLARITY 0x54
1904#define MCU_RADAR 0x60 2254#define MCU_RADAR 0x60
1905#define MCU_BOOT_SIGNAL 0x72 2255#define MCU_BOOT_SIGNAL 0x72
2256#define MCU_ANT_SELECT 0X73
1906#define MCU_BBP_SIGNAL 0x80 2257#define MCU_BBP_SIGNAL 0x80
1907#define MCU_POWER_SAVE 0x83 2258#define MCU_POWER_SAVE 0x83
1908 2259
@@ -1914,8 +2265,8 @@ struct mac_iveiv_entry {
1914/* 2265/*
1915 * DMA descriptor defines. 2266 * DMA descriptor defines.
1916 */ 2267 */
1917#define TXWI_DESC_SIZE ( 4 * sizeof(__le32) ) 2268#define TXWI_DESC_SIZE (4 * sizeof(__le32))
1918#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) ) 2269#define RXWI_DESC_SIZE (4 * sizeof(__le32))
1919 2270
1920/* 2271/*
1921 * TX WI structure 2272 * TX WI structure
@@ -1926,8 +2277,17 @@ struct mac_iveiv_entry {
1926 * FRAG: 1 To inform TKIP engine this is a fragment. 2277 * FRAG: 1 To inform TKIP engine this is a fragment.
1927 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode 2278 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
1928 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs 2279 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
1929 * BW: Channel bandwidth 20MHz or 40 MHz 2280 * BW: Channel bandwidth 0:20MHz, 1:40 MHz (for legacy rates this will
2281 * duplicate the frame to both channels).
1930 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED 2282 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
2283 * AMPDU: 1: this frame is eligible for AMPDU aggregation, the hw will
2284 * aggregate consecutive frames with the same RA and QoS TID. If
2285 * a frame A with the same RA and QoS TID but AMPDU=0 is queued
2286 * directly after a frame B with AMPDU=1, frame A might still
2287 * get aggregated into the AMPDU started by frame B. So, setting
2288 * AMPDU to 0 does _not_ necessarily mean the frame is sent as
2289 * MPDU, it can still end up in an AMPDU if the previous frame
2290 * was tagged as AMPDU.
1931 */ 2291 */
1932#define TXWI_W0_FRAG FIELD32(0x00000001) 2292#define TXWI_W0_FRAG FIELD32(0x00000001)
1933#define TXWI_W0_MIMO_PS FIELD32(0x00000002) 2293#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
@@ -1945,6 +2305,19 @@ struct mac_iveiv_entry {
1945 2305
1946/* 2306/*
1947 * Word1 2307 * Word1
2308 * ACK: 0: No Ack needed, 1: Ack needed
2309 * NSEQ: 0: Don't assign hw sequence number, 1: Assign hw sequence number
2310 * BW_WIN_SIZE: BA windows size of the recipient
2311 * WIRELESS_CLI_ID: Client ID for WCID table access
2312 * MPDU_TOTAL_BYTE_COUNT: Length of 802.11 frame
2313 * PACKETID: Will be latched into the TX_STA_FIFO register once the according
2314 * frame was processed. If multiple frames are aggregated together
2315 * (AMPDU==1) the reported tx status will always contain the packet
2316 * id of the first frame. 0: Don't report tx status for this frame.
2317 * PACKETID_QUEUE: Part of PACKETID, This is the queue index (0-3)
2318 * PACKETID_ENTRY: Part of PACKETID, THis is the queue entry index (1-3)
2319 * This identification number is calculated by ((idx % 3) + 1).
2320 * The (+1) is required to prevent PACKETID to become 0.
1948 */ 2321 */
1949#define TXWI_W1_ACK FIELD32(0x00000001) 2322#define TXWI_W1_ACK FIELD32(0x00000001)
1950#define TXWI_W1_NSEQ FIELD32(0x00000002) 2323#define TXWI_W1_NSEQ FIELD32(0x00000002)
@@ -1952,6 +2325,8 @@ struct mac_iveiv_entry {
1952#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00) 2325#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
1953#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000) 2326#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1954#define TXWI_W1_PACKETID FIELD32(0xf0000000) 2327#define TXWI_W1_PACKETID FIELD32(0xf0000000)
2328#define TXWI_W1_PACKETID_QUEUE FIELD32(0x30000000)
2329#define TXWI_W1_PACKETID_ENTRY FIELD32(0xc0000000)
1955 2330
1956/* 2331/*
1957 * Word2 2332 * Word2
@@ -2023,4 +2398,9 @@ struct mac_iveiv_entry {
2023#define TXPOWER_A_TO_DEV(__txpower) \ 2398#define TXPOWER_A_TO_DEV(__txpower) \
2024 clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER) 2399 clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
2025 2400
2401/*
2402 * Board's maximun TX power limitation
2403 */
2404#define EIRP_MAX_TX_POWER_LIMIT 0x50
2405
2026#endif /* RT2800_H */ 2406#endif /* RT2800_H */
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c
index b66e0fd8f0fa..2a6aa85cc6c9 100644
--- a/drivers/net/wireless/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/rt2x00/rt2800lib.c
@@ -1,4 +1,5 @@
1/* 1/*
2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
2 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com> 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
4 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com> 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
@@ -254,18 +255,39 @@ void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
254} 255}
255EXPORT_SYMBOL_GPL(rt2800_mcu_request); 256EXPORT_SYMBOL_GPL(rt2800_mcu_request);
256 257
258int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
259{
260 unsigned int i = 0;
261 u32 reg;
262
263 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
265 if (reg && reg != ~0)
266 return 0;
267 msleep(1);
268 }
269
270 ERROR(rt2x00dev, "Unstable hardware.\n");
271 return -EBUSY;
272}
273EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
274
257int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) 275int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
258{ 276{
259 unsigned int i; 277 unsigned int i;
260 u32 reg; 278 u32 reg;
261 279
280 /*
281 * Some devices are really slow to respond here. Wait a whole second
282 * before timing out.
283 */
262 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 284 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
263 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 285 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
264 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && 286 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
265 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) 287 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
266 return 0; 288 return 0;
267 289
268 msleep(1); 290 msleep(10);
269 } 291 }
270 292
271 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n"); 293 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
@@ -367,22 +389,26 @@ int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
367 u32 reg; 389 u32 reg;
368 390
369 /* 391 /*
370 * Wait for stable hardware. 392 * If driver doesn't wake up firmware here,
393 * rt2800_load_firmware will hang forever when interface is up again.
371 */ 394 */
372 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 395 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
373 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
374 if (reg && reg != ~0)
375 break;
376 msleep(1);
377 }
378 396
379 if (i == REGISTER_BUSY_COUNT) { 397 /*
380 ERROR(rt2x00dev, "Unstable hardware.\n"); 398 * Wait for stable hardware.
399 */
400 if (rt2800_wait_csr_ready(rt2x00dev))
381 return -EBUSY; 401 return -EBUSY;
382 }
383 402
384 if (rt2x00_is_pci(rt2x00dev)) 403 if (rt2x00_is_pci(rt2x00dev)) {
404 if (rt2x00_rt(rt2x00dev, RT5390)) {
405 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
406 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
407 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
408 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
409 }
385 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002); 410 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
411 }
386 412
387 /* 413 /*
388 * Disable DMA, will be reenabled later when enabling 414 * Disable DMA, will be reenabled later when enabling
@@ -427,8 +453,10 @@ int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
427} 453}
428EXPORT_SYMBOL_GPL(rt2800_load_firmware); 454EXPORT_SYMBOL_GPL(rt2800_load_firmware);
429 455
430void rt2800_write_txwi(__le32 *txwi, struct txentry_desc *txdesc) 456void rt2800_write_tx_data(struct queue_entry *entry,
457 struct txentry_desc *txdesc)
431{ 458{
459 __le32 *txwi = rt2800_drv_get_txwi(entry);
432 u32 word; 460 u32 word;
433 461
434 /* 462 /*
@@ -437,20 +465,22 @@ void rt2800_write_txwi(__le32 *txwi, struct txentry_desc *txdesc)
437 rt2x00_desc_read(txwi, 0, &word); 465 rt2x00_desc_read(txwi, 0, &word);
438 rt2x00_set_field32(&word, TXWI_W0_FRAG, 466 rt2x00_set_field32(&word, TXWI_W0_FRAG,
439 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); 467 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
440 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0); 468 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
469 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
441 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0); 470 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
442 rt2x00_set_field32(&word, TXWI_W0_TS, 471 rt2x00_set_field32(&word, TXWI_W0_TS,
443 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 472 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
444 rt2x00_set_field32(&word, TXWI_W0_AMPDU, 473 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
445 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags)); 474 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
446 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density); 475 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
447 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop); 476 txdesc->u.ht.mpdu_density);
448 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs); 477 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
478 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
449 rt2x00_set_field32(&word, TXWI_W0_BW, 479 rt2x00_set_field32(&word, TXWI_W0_BW,
450 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags)); 480 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
451 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI, 481 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
452 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags)); 482 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
453 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc); 483 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
454 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode); 484 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
455 rt2x00_desc_write(txwi, 0, word); 485 rt2x00_desc_write(txwi, 0, word);
456 486
@@ -459,13 +489,14 @@ void rt2800_write_txwi(__le32 *txwi, struct txentry_desc *txdesc)
459 test_bit(ENTRY_TXD_ACK, &txdesc->flags)); 489 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
460 rt2x00_set_field32(&word, TXWI_W1_NSEQ, 490 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
461 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); 491 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
462 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size); 492 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
463 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 493 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
464 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ? 494 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
465 txdesc->key_idx : 0xff); 495 txdesc->key_idx : 0xff);
466 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, 496 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
467 txdesc->length); 497 txdesc->length);
468 rt2x00_set_field32(&word, TXWI_W1_PACKETID, txdesc->queue + 1); 498 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
499 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
469 rt2x00_desc_write(txwi, 1, word); 500 rt2x00_desc_write(txwi, 1, word);
470 501
471 /* 502 /*
@@ -478,9 +509,9 @@ void rt2800_write_txwi(__le32 *txwi, struct txentry_desc *txdesc)
478 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */); 509 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
479 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */); 510 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
480} 511}
481EXPORT_SYMBOL_GPL(rt2800_write_txwi); 512EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
482 513
483static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxwi_w2) 514static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
484{ 515{
485 int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0); 516 int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
486 int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1); 517 int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
@@ -490,7 +521,7 @@ static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxwi_w2)
490 u8 offset1; 521 u8 offset1;
491 u8 offset2; 522 u8 offset2;
492 523
493 if (rt2x00dev->rx_status.band == IEEE80211_BAND_2GHZ) { 524 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
494 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom); 525 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
495 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0); 526 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
496 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1); 527 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
@@ -569,18 +600,184 @@ void rt2800_process_rxwi(struct queue_entry *entry,
569} 600}
570EXPORT_SYMBOL_GPL(rt2800_process_rxwi); 601EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
571 602
603static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
604{
605 __le32 *txwi;
606 u32 word;
607 int wcid, ack, pid;
608 int tx_wcid, tx_ack, tx_pid;
609
610 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
611 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
612 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
613
614 /*
615 * This frames has returned with an IO error,
616 * so the status report is not intended for this
617 * frame.
618 */
619 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) {
620 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
621 return false;
622 }
623
624 /*
625 * Validate if this TX status report is intended for
626 * this entry by comparing the WCID/ACK/PID fields.
627 */
628 txwi = rt2800_drv_get_txwi(entry);
629
630 rt2x00_desc_read(txwi, 1, &word);
631 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
632 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK);
633 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID);
634
635 if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) {
636 WARNING(entry->queue->rt2x00dev,
637 "TX status report missed for queue %d entry %d\n",
638 entry->queue->qid, entry->entry_idx);
639 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
640 return false;
641 }
642
643 return true;
644}
645
646void rt2800_txdone_entry(struct queue_entry *entry, u32 status)
647{
648 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
649 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
650 struct txdone_entry_desc txdesc;
651 u32 word;
652 u16 mcs, real_mcs;
653 int aggr, ampdu;
654 __le32 *txwi;
655
656 /*
657 * Obtain the status about this packet.
658 */
659 txdesc.flags = 0;
660 txwi = rt2800_drv_get_txwi(entry);
661 rt2x00_desc_read(txwi, 0, &word);
662
663 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
664 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
665
666 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
667 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
668
669 /*
670 * If a frame was meant to be sent as a single non-aggregated MPDU
671 * but ended up in an aggregate the used tx rate doesn't correlate
672 * with the one specified in the TXWI as the whole aggregate is sent
673 * with the same rate.
674 *
675 * For example: two frames are sent to rt2x00, the first one sets
676 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
677 * and requests MCS15. If the hw aggregates both frames into one
678 * AMDPU the tx status for both frames will contain MCS7 although
679 * the frame was sent successfully.
680 *
681 * Hence, replace the requested rate with the real tx rate to not
682 * confuse the rate control algortihm by providing clearly wrong
683 * data.
684 */
685 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
686 skbdesc->tx_rate_idx = real_mcs;
687 mcs = real_mcs;
688 }
689
690 if (aggr == 1 || ampdu == 1)
691 __set_bit(TXDONE_AMPDU, &txdesc.flags);
692
693 /*
694 * Ralink has a retry mechanism using a global fallback
695 * table. We setup this fallback table to try the immediate
696 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
697 * always contains the MCS used for the last transmission, be
698 * it successful or not.
699 */
700 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
701 /*
702 * Transmission succeeded. The number of retries is
703 * mcs - real_mcs
704 */
705 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
706 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
707 } else {
708 /*
709 * Transmission failed. The number of retries is
710 * always 7 in this case (for a total number of 8
711 * frames sent).
712 */
713 __set_bit(TXDONE_FAILURE, &txdesc.flags);
714 txdesc.retry = rt2x00dev->long_retry;
715 }
716
717 /*
718 * the frame was retried at least once
719 * -> hw used fallback rates
720 */
721 if (txdesc.retry)
722 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
723
724 rt2x00lib_txdone(entry, &txdesc);
725}
726EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
727
728void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
729{
730 struct data_queue *queue;
731 struct queue_entry *entry;
732 u32 reg;
733 u8 qid;
734
735 while (kfifo_get(&rt2x00dev->txstatus_fifo, &reg)) {
736
737 /* TX_STA_FIFO_PID_QUEUE is a 2-bit field, thus
738 * qid is guaranteed to be one of the TX QIDs
739 */
740 qid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
741 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
742 if (unlikely(!queue)) {
743 WARNING(rt2x00dev, "Got TX status for an unavailable "
744 "queue %u, dropping\n", qid);
745 continue;
746 }
747
748 /*
749 * Inside each queue, we process each entry in a chronological
750 * order. We first check that the queue is not empty.
751 */
752 entry = NULL;
753 while (!rt2x00queue_empty(queue)) {
754 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
755 if (rt2800_txdone_entry_check(entry, reg))
756 break;
757 }
758
759 if (!entry || rt2x00queue_empty(queue))
760 break;
761
762 rt2800_txdone_entry(entry, reg);
763 }
764}
765EXPORT_SYMBOL_GPL(rt2800_txdone);
766
572void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc) 767void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
573{ 768{
574 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 769 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
575 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 770 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
576 unsigned int beacon_base; 771 unsigned int beacon_base;
577 u32 reg; 772 unsigned int padding_len;
773 u32 orig_reg, reg;
578 774
579 /* 775 /*
580 * Disable beaconing while we are reloading the beacon data, 776 * Disable beaconing while we are reloading the beacon data,
581 * otherwise we might be sending out invalid data. 777 * otherwise we might be sending out invalid data.
582 */ 778 */
583 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 779 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
780 orig_reg = reg;
584 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0); 781 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
585 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 782 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
586 783
@@ -600,7 +797,7 @@ void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
600 /* 797 /*
601 * Add the TXWI for the beacon to the skb. 798 * Add the TXWI for the beacon to the skb.
602 */ 799 */
603 rt2800_write_txwi((__le32 *)entry->skb->data, txdesc); 800 rt2800_write_tx_data(entry, txdesc);
604 801
605 /* 802 /*
606 * Dump beacon to userspace through debugfs. 803 * Dump beacon to userspace through debugfs.
@@ -608,17 +805,24 @@ void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
608 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb); 805 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
609 806
610 /* 807 /*
611 * Write entire beacon with TXWI to register. 808 * Write entire beacon with TXWI and padding to register.
612 */ 809 */
810 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
811 if (padding_len && skb_pad(entry->skb, padding_len)) {
812 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
813 /* skb freed by skb_pad() on failure */
814 entry->skb = NULL;
815 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
816 return;
817 }
818
613 beacon_base = HW_BEACON_OFFSET(entry->entry_idx); 819 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
614 rt2800_register_multiwrite(rt2x00dev, beacon_base, 820 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
615 entry->skb->data, entry->skb->len); 821 entry->skb->len + padding_len);
616 822
617 /* 823 /*
618 * Enable beaconing again. 824 * Enable beaconing again.
619 */ 825 */
620 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
621 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
622 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1); 826 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
623 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 827 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
624 828
@@ -630,8 +834,8 @@ void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
630} 834}
631EXPORT_SYMBOL_GPL(rt2800_write_beacon); 835EXPORT_SYMBOL_GPL(rt2800_write_beacon);
632 836
633static void inline rt2800_clear_beacon(struct rt2x00_dev *rt2x00dev, 837static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
634 unsigned int beacon_base) 838 unsigned int beacon_base)
635{ 839{
636 int i; 840 int i;
637 841
@@ -644,6 +848,33 @@ static void inline rt2800_clear_beacon(struct rt2x00_dev *rt2x00dev,
644 rt2800_register_write(rt2x00dev, beacon_base + i, 0); 848 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
645} 849}
646 850
851void rt2800_clear_beacon(struct queue_entry *entry)
852{
853 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
854 u32 reg;
855
856 /*
857 * Disable beaconing while we are reloading the beacon data,
858 * otherwise we might be sending out invalid data.
859 */
860 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
861 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
862 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
863
864 /*
865 * Clear beacon.
866 */
867 rt2800_clear_beacon_register(rt2x00dev,
868 HW_BEACON_OFFSET(entry->entry_idx));
869
870 /*
871 * Enabled beaconing again.
872 */
873 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
874 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
875}
876EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
877
647#ifdef CONFIG_RT2X00_LIB_DEBUGFS 878#ifdef CONFIG_RT2X00_LIB_DEBUGFS
648const struct rt2x00debug rt2800_rt2x00debug = { 879const struct rt2x00debug rt2800_rt2x00debug = {
649 .owner = THIS_MODULE, 880 .owner = THIS_MODULE,
@@ -704,25 +935,49 @@ static void rt2800_brightness_set(struct led_classdev *led_cdev,
704 unsigned int ledmode = 935 unsigned int ledmode =
705 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 936 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
706 EEPROM_FREQ_LED_MODE); 937 EEPROM_FREQ_LED_MODE);
938 u32 reg;
707 939
708 if (led->type == LED_TYPE_RADIO) { 940 /* Check for SoC (SOC devices don't support MCU requests) */
709 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 941 if (rt2x00_is_soc(led->rt2x00dev)) {
710 enabled ? 0x20 : 0); 942 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
711 } else if (led->type == LED_TYPE_ASSOC) { 943
712 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 944 /* Set LED Polarity */
713 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20); 945 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
714 } else if (led->type == LED_TYPE_QUALITY) { 946
715 /* 947 /* Set LED Mode */
716 * The brightness is divided into 6 levels (0 - 5), 948 if (led->type == LED_TYPE_RADIO) {
717 * The specs tell us the following levels: 949 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
718 * 0, 1 ,3, 7, 15, 31 950 enabled ? 3 : 0);
719 * to determine the level in a simple way we can simply 951 } else if (led->type == LED_TYPE_ASSOC) {
720 * work with bitshifting: 952 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
721 * (1 << level) - 1 953 enabled ? 3 : 0);
722 */ 954 } else if (led->type == LED_TYPE_QUALITY) {
723 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, 955 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
724 (1 << brightness / (LED_FULL / 6)) - 1, 956 enabled ? 3 : 0);
725 polarity); 957 }
958
959 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
960
961 } else {
962 if (led->type == LED_TYPE_RADIO) {
963 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
964 enabled ? 0x20 : 0);
965 } else if (led->type == LED_TYPE_ASSOC) {
966 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
967 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
968 } else if (led->type == LED_TYPE_QUALITY) {
969 /*
970 * The brightness is divided into 6 levels (0 - 5),
971 * The specs tell us the following levels:
972 * 0, 1 ,3, 7, 15, 31
973 * to determine the level in a simple way we can simply
974 * work with bitshifting:
975 * (1 << level) - 1
976 */
977 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
978 (1 << brightness / (LED_FULL / 6)) - 1,
979 polarity);
980 }
726 } 981 }
727} 982}
728 983
@@ -804,7 +1059,7 @@ static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
804 1059
805 memset(&wcid_entry, 0, sizeof(wcid_entry)); 1060 memset(&wcid_entry, 0, sizeof(wcid_entry));
806 if (crypto->cmd == SET_KEY) 1061 if (crypto->cmd == SET_KEY)
807 memcpy(&wcid_entry, crypto->address, ETH_ALEN); 1062 memcpy(wcid_entry.mac, crypto->address, ETH_ALEN);
808 rt2800_register_multiwrite(rt2x00dev, offset, 1063 rt2800_register_multiwrite(rt2x00dev, offset,
809 &wcid_entry, sizeof(wcid_entry)); 1064 &wcid_entry, sizeof(wcid_entry));
810} 1065}
@@ -859,23 +1114,44 @@ int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
859} 1114}
860EXPORT_SYMBOL_GPL(rt2800_config_shared_key); 1115EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
861 1116
1117static inline int rt2800_find_pairwise_keyslot(struct rt2x00_dev *rt2x00dev)
1118{
1119 int idx;
1120 u32 offset, reg;
1121
1122 /*
1123 * Search for the first free pairwise key entry and return the
1124 * corresponding index.
1125 *
1126 * Make sure the WCID starts _after_ the last possible shared key
1127 * entry (>32).
1128 *
1129 * Since parts of the pairwise key table might be shared with
1130 * the beacon frame buffers 6 & 7 we should only write into the
1131 * first 222 entries.
1132 */
1133 for (idx = 33; idx <= 222; idx++) {
1134 offset = MAC_WCID_ATTR_ENTRY(idx);
1135 rt2800_register_read(rt2x00dev, offset, &reg);
1136 if (!reg)
1137 return idx;
1138 }
1139 return -1;
1140}
1141
862int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev, 1142int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
863 struct rt2x00lib_crypto *crypto, 1143 struct rt2x00lib_crypto *crypto,
864 struct ieee80211_key_conf *key) 1144 struct ieee80211_key_conf *key)
865{ 1145{
866 struct hw_key_entry key_entry; 1146 struct hw_key_entry key_entry;
867 u32 offset; 1147 u32 offset;
1148 int idx;
868 1149
869 if (crypto->cmd == SET_KEY) { 1150 if (crypto->cmd == SET_KEY) {
870 /* 1151 idx = rt2800_find_pairwise_keyslot(rt2x00dev);
871 * 1 pairwise key is possible per AID, this means that the AID 1152 if (idx < 0)
872 * equals our hw_key_idx. Make sure the WCID starts _after_ the
873 * last possible shared key entry.
874 */
875 if (crypto->aid > (256 - 32))
876 return -ENOSPC; 1153 return -ENOSPC;
877 1154 key->hw_key_idx = idx;
878 key->hw_key_idx = 32 + crypto->aid;
879 1155
880 memcpy(key_entry.key, crypto->key, 1156 memcpy(key_entry.key, crypto->key,
881 sizeof(key_entry.key)); 1157 sizeof(key_entry.key));
@@ -946,48 +1222,64 @@ void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
946 struct rt2x00intf_conf *conf, const unsigned int flags) 1222 struct rt2x00intf_conf *conf, const unsigned int flags)
947{ 1223{
948 u32 reg; 1224 u32 reg;
1225 bool update_bssid = false;
949 1226
950 if (flags & CONFIG_UPDATE_TYPE) { 1227 if (flags & CONFIG_UPDATE_TYPE) {
951 /* 1228 /*
952 * Clear current synchronisation setup.
953 */
954 rt2800_clear_beacon(rt2x00dev,
955 HW_BEACON_OFFSET(intf->beacon->entry_idx));
956 /*
957 * Enable synchronisation. 1229 * Enable synchronisation.
958 */ 1230 */
959 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 1231 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
960 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
961 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync); 1232 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
962 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
963 (conf->sync == TSF_SYNC_ADHOC ||
964 conf->sync == TSF_SYNC_AP_NONE));
965 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1233 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
966 1234
967 /* 1235 if (conf->sync == TSF_SYNC_AP_NONE) {
968 * Enable pre tbtt interrupt for beaconing modes 1236 /*
969 */ 1237 * Tune beacon queue transmit parameters for AP mode
970 rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg); 1238 */
971 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1239 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
972 (conf->sync == TSF_SYNC_AP_NONE)); 1240 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
973 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg); 1241 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
974 1242 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1243 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1244 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1245 } else {
1246 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1247 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1248 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1249 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1250 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1251 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1252 }
975 } 1253 }
976 1254
977 if (flags & CONFIG_UPDATE_MAC) { 1255 if (flags & CONFIG_UPDATE_MAC) {
978 reg = le32_to_cpu(conf->mac[1]); 1256 if (flags & CONFIG_UPDATE_TYPE &&
979 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); 1257 conf->sync == TSF_SYNC_AP_NONE) {
980 conf->mac[1] = cpu_to_le32(reg); 1258 /*
1259 * The BSSID register has to be set to our own mac
1260 * address in AP mode.
1261 */
1262 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1263 update_bssid = true;
1264 }
1265
1266 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1267 reg = le32_to_cpu(conf->mac[1]);
1268 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1269 conf->mac[1] = cpu_to_le32(reg);
1270 }
981 1271
982 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0, 1272 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
983 conf->mac, sizeof(conf->mac)); 1273 conf->mac, sizeof(conf->mac));
984 } 1274 }
985 1275
986 if (flags & CONFIG_UPDATE_BSSID) { 1276 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
987 reg = le32_to_cpu(conf->bssid[1]); 1277 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
988 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3); 1278 reg = le32_to_cpu(conf->bssid[1]);
989 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7); 1279 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
990 conf->bssid[1] = cpu_to_le32(reg); 1280 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1281 conf->bssid[1] = cpu_to_le32(reg);
1282 }
991 1283
992 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0, 1284 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
993 conf->bssid, sizeof(conf->bssid)); 1285 conf->bssid, sizeof(conf->bssid));
@@ -995,45 +1287,178 @@ void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
995} 1287}
996EXPORT_SYMBOL_GPL(rt2800_config_intf); 1288EXPORT_SYMBOL_GPL(rt2800_config_intf);
997 1289
998void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp) 1290static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1291 struct rt2x00lib_erp *erp)
999{ 1292{
1293 bool any_sta_nongf = !!(erp->ht_opmode &
1294 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1295 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1296 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1297 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1000 u32 reg; 1298 u32 reg;
1001 1299
1002 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg); 1300 /* default protection rate for HT20: OFDM 24M */
1003 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1301 mm20_rate = gf20_rate = 0x4004;
1004 !!erp->short_preamble);
1005 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1006 !!erp->short_preamble);
1007 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1008 1302
1009 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg); 1303 /* default protection rate for HT40: duplicate OFDM 24M */
1010 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 1304 mm40_rate = gf40_rate = 0x4084;
1011 erp->cts_protection ? 2 : 0);
1012 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1013 1305
1014 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 1306 switch (protection) {
1015 erp->basic_rates); 1307 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1016 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 1308 /*
1309 * All STAs in this BSS are HT20/40 but there might be
1310 * STAs not supporting greenfield mode.
1311 * => Disable protection for HT transmissions.
1312 */
1313 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1017 1314
1018 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg); 1315 break;
1019 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time); 1316 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1020 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 1317 /*
1318 * All STAs in this BSS are HT20 or HT20/40 but there
1319 * might be STAs not supporting greenfield mode.
1320 * => Protect all HT40 transmissions.
1321 */
1322 mm20_mode = gf20_mode = 0;
1323 mm40_mode = gf40_mode = 2;
1021 1324
1022 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg); 1325 break;
1023 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs); 1326 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1024 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 1327 /*
1328 * Nonmember protection:
1329 * According to 802.11n we _should_ protect all
1330 * HT transmissions (but we don't have to).
1331 *
1332 * But if cts_protection is enabled we _shall_ protect
1333 * all HT transmissions using a CCK rate.
1334 *
1335 * And if any station is non GF we _shall_ protect
1336 * GF transmissions.
1337 *
1338 * We decide to protect everything
1339 * -> fall through to mixed mode.
1340 */
1341 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1342 /*
1343 * Legacy STAs are present
1344 * => Protect all HT transmissions.
1345 */
1346 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1025 1347
1026 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 1348 /*
1027 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1349 * If erp protection is needed we have to protect HT
1028 erp->beacon_int * 16); 1350 * transmissions with CCK 11M long preamble.
1029 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1351 */
1352 if (erp->cts_protection) {
1353 /* don't duplicate RTS/CTS in CCK mode */
1354 mm20_rate = mm40_rate = 0x0003;
1355 gf20_rate = gf40_rate = 0x0003;
1356 }
1357 break;
1358 };
1359
1360 /* check for STAs not supporting greenfield mode */
1361 if (any_sta_nongf)
1362 gf20_mode = gf40_mode = 2;
1363
1364 /* Update HT protection config */
1365 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1366 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1367 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1368 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1369
1370 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1371 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1372 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1373 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1374
1375 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1376 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1377 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1378 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1379
1380 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1381 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1382 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1383 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1384}
1385
1386void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1387 u32 changed)
1388{
1389 u32 reg;
1390
1391 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1392 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1393 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1394 !!erp->short_preamble);
1395 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1396 !!erp->short_preamble);
1397 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1398 }
1399
1400 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1401 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1402 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1403 erp->cts_protection ? 2 : 0);
1404 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1405 }
1406
1407 if (changed & BSS_CHANGED_BASIC_RATES) {
1408 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1409 erp->basic_rates);
1410 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1411 }
1412
1413 if (changed & BSS_CHANGED_ERP_SLOT) {
1414 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1415 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1416 erp->slot_time);
1417 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1418
1419 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1420 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1421 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1422 }
1423
1424 if (changed & BSS_CHANGED_BEACON_INT) {
1425 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1426 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1427 erp->beacon_int * 16);
1428 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1429 }
1430
1431 if (changed & BSS_CHANGED_HT)
1432 rt2800_config_ht_opmode(rt2x00dev, erp);
1030} 1433}
1031EXPORT_SYMBOL_GPL(rt2800_config_erp); 1434EXPORT_SYMBOL_GPL(rt2800_config_erp);
1032 1435
1436static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1437 enum antenna ant)
1438{
1439 u32 reg;
1440 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1441 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1442
1443 if (rt2x00_is_pci(rt2x00dev)) {
1444 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1445 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1446 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1447 } else if (rt2x00_is_usb(rt2x00dev))
1448 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1449 eesk_pin, 0);
1450
1451 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1452 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
1453 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1454 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1455}
1456
1033void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) 1457void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1034{ 1458{
1035 u8 r1; 1459 u8 r1;
1036 u8 r3; 1460 u8 r3;
1461 u16 eeprom;
1037 1462
1038 rt2800_bbp_read(rt2x00dev, 1, &r1); 1463 rt2800_bbp_read(rt2x00dev, 1, &r1);
1039 rt2800_bbp_read(rt2x00dev, 3, &r3); 1464 rt2800_bbp_read(rt2x00dev, 3, &r3);
@@ -1041,7 +1466,7 @@ void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1041 /* 1466 /*
1042 * Configure the TX antenna. 1467 * Configure the TX antenna.
1043 */ 1468 */
1044 switch ((int)ant->tx) { 1469 switch (ant->tx_chain_num) {
1045 case 1: 1470 case 1:
1046 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); 1471 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1047 break; 1472 break;
@@ -1056,8 +1481,18 @@ void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1056 /* 1481 /*
1057 * Configure the RX antenna. 1482 * Configure the RX antenna.
1058 */ 1483 */
1059 switch ((int)ant->rx) { 1484 switch (ant->rx_chain_num) {
1060 case 1: 1485 case 1:
1486 if (rt2x00_rt(rt2x00dev, RT3070) ||
1487 rt2x00_rt(rt2x00dev, RT3090) ||
1488 rt2x00_rt(rt2x00dev, RT3390)) {
1489 rt2x00_eeprom_read(rt2x00dev,
1490 EEPROM_NIC_CONF1, &eeprom);
1491 if (rt2x00_get_field16(eeprom,
1492 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1493 rt2800_set_ant_diversity(rt2x00dev,
1494 rt2x00dev->default_ant.rx);
1495 }
1061 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); 1496 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1062 break; 1497 break;
1063 case 2: 1498 case 2:
@@ -1103,44 +1538,40 @@ static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1103{ 1538{
1104 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); 1539 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1105 1540
1106 if (rt2x00dev->default_ant.tx == 1) 1541 if (rt2x00dev->default_ant.tx_chain_num == 1)
1107 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1); 1542 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1108 1543
1109 if (rt2x00dev->default_ant.rx == 1) { 1544 if (rt2x00dev->default_ant.rx_chain_num == 1) {
1110 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1); 1545 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1111 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 1546 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1112 } else if (rt2x00dev->default_ant.rx == 2) 1547 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1113 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 1548 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1114 1549
1115 if (rf->channel > 14) { 1550 if (rf->channel > 14) {
1116 /* 1551 /*
1117 * When TX power is below 0, we should increase it by 7 to 1552 * When TX power is below 0, we should increase it by 7 to
1118 * make it a positive value (Minumum value is -7). 1553 * make it a positive value (Minimum value is -7).
1119 * However this means that values between 0 and 7 have 1554 * However this means that values between 0 and 7 have
1120 * double meaning, and we should set a 7DBm boost flag. 1555 * double meaning, and we should set a 7DBm boost flag.
1121 */ 1556 */
1122 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST, 1557 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1123 (info->tx_power1 >= 0)); 1558 (info->default_power1 >= 0));
1124 1559
1125 if (info->tx_power1 < 0) 1560 if (info->default_power1 < 0)
1126 info->tx_power1 += 7; 1561 info->default_power1 += 7;
1127 1562
1128 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, 1563 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1129 TXPOWER_A_TO_DEV(info->tx_power1));
1130 1564
1131 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST, 1565 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1132 (info->tx_power2 >= 0)); 1566 (info->default_power2 >= 0));
1133 1567
1134 if (info->tx_power2 < 0) 1568 if (info->default_power2 < 0)
1135 info->tx_power2 += 7; 1569 info->default_power2 += 7;
1136 1570
1137 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, 1571 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1138 TXPOWER_A_TO_DEV(info->tx_power2));
1139 } else { 1572 } else {
1140 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, 1573 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1141 TXPOWER_G_TO_DEV(info->tx_power1)); 1574 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1142 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
1143 TXPOWER_G_TO_DEV(info->tx_power2));
1144 } 1575 }
1145 1576
1146 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf)); 1577 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
@@ -1180,13 +1611,11 @@ static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1180 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 1611 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1181 1612
1182 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); 1613 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1183 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 1614 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1184 TXPOWER_G_TO_DEV(info->tx_power1));
1185 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 1615 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1186 1616
1187 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr); 1617 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1188 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 1618 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1189 TXPOWER_G_TO_DEV(info->tx_power2));
1190 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 1619 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1191 1620
1192 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr); 1621 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
@@ -1201,6 +1630,103 @@ static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1201 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 1630 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1202} 1631}
1203 1632
1633
1634#define RT5390_POWER_BOUND 0x27
1635#define RT5390_FREQ_OFFSET_BOUND 0x5f
1636
1637static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
1638 struct ieee80211_conf *conf,
1639 struct rf_channel *rf,
1640 struct channel_info *info)
1641{
1642 u8 rfcsr;
1643
1644 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1645 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1646 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1647 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1648 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1649
1650 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1651 if (info->default_power1 > RT5390_POWER_BOUND)
1652 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
1653 else
1654 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1655 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1656
1657 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1658 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1659 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
1660 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1661 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1662 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1663
1664 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1665 if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
1666 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
1667 RT5390_FREQ_OFFSET_BOUND);
1668 else
1669 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1670 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1671
1672 if (rf->channel <= 14) {
1673 int idx = rf->channel-1;
1674
1675 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1676 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1677 /* r55/r59 value array of channel 1~14 */
1678 static const char r55_bt_rev[] = {0x83, 0x83,
1679 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1680 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1681 static const char r59_bt_rev[] = {0x0e, 0x0e,
1682 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1683 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1684
1685 rt2800_rfcsr_write(rt2x00dev, 55,
1686 r55_bt_rev[idx]);
1687 rt2800_rfcsr_write(rt2x00dev, 59,
1688 r59_bt_rev[idx]);
1689 } else {
1690 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
1691 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1692 0x88, 0x88, 0x86, 0x85, 0x84};
1693
1694 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
1695 }
1696 } else {
1697 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1698 static const char r55_nonbt_rev[] = {0x23, 0x23,
1699 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
1700 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
1701 static const char r59_nonbt_rev[] = {0x07, 0x07,
1702 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
1703 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
1704
1705 rt2800_rfcsr_write(rt2x00dev, 55,
1706 r55_nonbt_rev[idx]);
1707 rt2800_rfcsr_write(rt2x00dev, 59,
1708 r59_nonbt_rev[idx]);
1709 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
1710 static const char r59_non_bt[] = {0x8f, 0x8f,
1711 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
1712 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
1713
1714 rt2800_rfcsr_write(rt2x00dev, 59,
1715 r59_non_bt[idx]);
1716 }
1717 }
1718 }
1719
1720 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1721 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
1722 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
1723 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1724
1725 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1726 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1727 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1728}
1729
1204static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, 1730static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1205 struct ieee80211_conf *conf, 1731 struct ieee80211_conf *conf,
1206 struct rf_channel *rf, 1732 struct rf_channel *rf,
@@ -1210,11 +1736,24 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1210 unsigned int tx_pin; 1736 unsigned int tx_pin;
1211 u8 bbp; 1737 u8 bbp;
1212 1738
1739 if (rf->channel <= 14) {
1740 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1741 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
1742 } else {
1743 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1744 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
1745 }
1746
1213 if (rt2x00_rf(rt2x00dev, RF2020) || 1747 if (rt2x00_rf(rt2x00dev, RF2020) ||
1214 rt2x00_rf(rt2x00dev, RF3020) || 1748 rt2x00_rf(rt2x00dev, RF3020) ||
1215 rt2x00_rf(rt2x00dev, RF3021) || 1749 rt2x00_rf(rt2x00dev, RF3021) ||
1216 rt2x00_rf(rt2x00dev, RF3022)) 1750 rt2x00_rf(rt2x00dev, RF3022) ||
1751 rt2x00_rf(rt2x00dev, RF3052) ||
1752 rt2x00_rf(rt2x00dev, RF3320))
1217 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info); 1753 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
1754 else if (rt2x00_rf(rt2x00dev, RF5370) ||
1755 rt2x00_rf(rt2x00dev, RF5390))
1756 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
1218 else 1757 else
1219 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); 1758 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
1220 1759
@@ -1227,17 +1766,20 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1227 rt2800_bbp_write(rt2x00dev, 86, 0); 1766 rt2800_bbp_write(rt2x00dev, 86, 0);
1228 1767
1229 if (rf->channel <= 14) { 1768 if (rf->channel <= 14) {
1230 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) { 1769 if (!rt2x00_rt(rt2x00dev, RT5390)) {
1231 rt2800_bbp_write(rt2x00dev, 82, 0x62); 1770 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
1232 rt2800_bbp_write(rt2x00dev, 75, 0x46); 1771 &rt2x00dev->cap_flags)) {
1233 } else { 1772 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1234 rt2800_bbp_write(rt2x00dev, 82, 0x84); 1773 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1235 rt2800_bbp_write(rt2x00dev, 75, 0x50); 1774 } else {
1775 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1776 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1777 }
1236 } 1778 }
1237 } else { 1779 } else {
1238 rt2800_bbp_write(rt2x00dev, 82, 0xf2); 1780 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1239 1781
1240 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) 1782 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
1241 rt2800_bbp_write(rt2x00dev, 75, 0x46); 1783 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1242 else 1784 else
1243 rt2800_bbp_write(rt2x00dev, 75, 0x50); 1785 rt2800_bbp_write(rt2x00dev, 75, 0x50);
@@ -1252,13 +1794,13 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1252 tx_pin = 0; 1794 tx_pin = 0;
1253 1795
1254 /* Turn on unused PA or LNA when not using 1T or 1R */ 1796 /* Turn on unused PA or LNA when not using 1T or 1R */
1255 if (rt2x00dev->default_ant.tx != 1) { 1797 if (rt2x00dev->default_ant.tx_chain_num == 2) {
1256 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1); 1798 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1257 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1); 1799 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1258 } 1800 }
1259 1801
1260 /* Turn on unused PA or LNA when not using 1T or 1R */ 1802 /* Turn on unused PA or LNA when not using 1T or 1R */
1261 if (rt2x00dev->default_ant.rx != 1) { 1803 if (rt2x00dev->default_ant.rx_chain_num == 2) {
1262 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1); 1804 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1263 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1); 1805 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1264 } 1806 }
@@ -1293,32 +1835,243 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1293 } 1835 }
1294 1836
1295 msleep(1); 1837 msleep(1);
1838
1839 /*
1840 * Clear channel statistic counters
1841 */
1842 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
1843 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
1844 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
1845}
1846
1847static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
1848{
1849 u8 tssi_bounds[9];
1850 u8 current_tssi;
1851 u16 eeprom;
1852 u8 step;
1853 int i;
1854
1855 /*
1856 * Read TSSI boundaries for temperature compensation from
1857 * the EEPROM.
1858 *
1859 * Array idx 0 1 2 3 4 5 6 7 8
1860 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
1861 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
1862 */
1863 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1864 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
1865 tssi_bounds[0] = rt2x00_get_field16(eeprom,
1866 EEPROM_TSSI_BOUND_BG1_MINUS4);
1867 tssi_bounds[1] = rt2x00_get_field16(eeprom,
1868 EEPROM_TSSI_BOUND_BG1_MINUS3);
1869
1870 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
1871 tssi_bounds[2] = rt2x00_get_field16(eeprom,
1872 EEPROM_TSSI_BOUND_BG2_MINUS2);
1873 tssi_bounds[3] = rt2x00_get_field16(eeprom,
1874 EEPROM_TSSI_BOUND_BG2_MINUS1);
1875
1876 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
1877 tssi_bounds[4] = rt2x00_get_field16(eeprom,
1878 EEPROM_TSSI_BOUND_BG3_REF);
1879 tssi_bounds[5] = rt2x00_get_field16(eeprom,
1880 EEPROM_TSSI_BOUND_BG3_PLUS1);
1881
1882 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
1883 tssi_bounds[6] = rt2x00_get_field16(eeprom,
1884 EEPROM_TSSI_BOUND_BG4_PLUS2);
1885 tssi_bounds[7] = rt2x00_get_field16(eeprom,
1886 EEPROM_TSSI_BOUND_BG4_PLUS3);
1887
1888 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
1889 tssi_bounds[8] = rt2x00_get_field16(eeprom,
1890 EEPROM_TSSI_BOUND_BG5_PLUS4);
1891
1892 step = rt2x00_get_field16(eeprom,
1893 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
1894 } else {
1895 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
1896 tssi_bounds[0] = rt2x00_get_field16(eeprom,
1897 EEPROM_TSSI_BOUND_A1_MINUS4);
1898 tssi_bounds[1] = rt2x00_get_field16(eeprom,
1899 EEPROM_TSSI_BOUND_A1_MINUS3);
1900
1901 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
1902 tssi_bounds[2] = rt2x00_get_field16(eeprom,
1903 EEPROM_TSSI_BOUND_A2_MINUS2);
1904 tssi_bounds[3] = rt2x00_get_field16(eeprom,
1905 EEPROM_TSSI_BOUND_A2_MINUS1);
1906
1907 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
1908 tssi_bounds[4] = rt2x00_get_field16(eeprom,
1909 EEPROM_TSSI_BOUND_A3_REF);
1910 tssi_bounds[5] = rt2x00_get_field16(eeprom,
1911 EEPROM_TSSI_BOUND_A3_PLUS1);
1912
1913 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
1914 tssi_bounds[6] = rt2x00_get_field16(eeprom,
1915 EEPROM_TSSI_BOUND_A4_PLUS2);
1916 tssi_bounds[7] = rt2x00_get_field16(eeprom,
1917 EEPROM_TSSI_BOUND_A4_PLUS3);
1918
1919 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
1920 tssi_bounds[8] = rt2x00_get_field16(eeprom,
1921 EEPROM_TSSI_BOUND_A5_PLUS4);
1922
1923 step = rt2x00_get_field16(eeprom,
1924 EEPROM_TSSI_BOUND_A5_AGC_STEP);
1925 }
1926
1927 /*
1928 * Check if temperature compensation is supported.
1929 */
1930 if (tssi_bounds[4] == 0xff)
1931 return 0;
1932
1933 /*
1934 * Read current TSSI (BBP 49).
1935 */
1936 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
1937
1938 /*
1939 * Compare TSSI value (BBP49) with the compensation boundaries
1940 * from the EEPROM and increase or decrease tx power.
1941 */
1942 for (i = 0; i <= 3; i++) {
1943 if (current_tssi > tssi_bounds[i])
1944 break;
1945 }
1946
1947 if (i == 4) {
1948 for (i = 8; i >= 5; i--) {
1949 if (current_tssi < tssi_bounds[i])
1950 break;
1951 }
1952 }
1953
1954 return (i - 4) * step;
1955}
1956
1957static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
1958 enum ieee80211_band band)
1959{
1960 u16 eeprom;
1961 u8 comp_en;
1962 u8 comp_type;
1963 int comp_value = 0;
1964
1965 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
1966
1967 /*
1968 * HT40 compensation not required.
1969 */
1970 if (eeprom == 0xffff ||
1971 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1972 return 0;
1973
1974 if (band == IEEE80211_BAND_2GHZ) {
1975 comp_en = rt2x00_get_field16(eeprom,
1976 EEPROM_TXPOWER_DELTA_ENABLE_2G);
1977 if (comp_en) {
1978 comp_type = rt2x00_get_field16(eeprom,
1979 EEPROM_TXPOWER_DELTA_TYPE_2G);
1980 comp_value = rt2x00_get_field16(eeprom,
1981 EEPROM_TXPOWER_DELTA_VALUE_2G);
1982 if (!comp_type)
1983 comp_value = -comp_value;
1984 }
1985 } else {
1986 comp_en = rt2x00_get_field16(eeprom,
1987 EEPROM_TXPOWER_DELTA_ENABLE_5G);
1988 if (comp_en) {
1989 comp_type = rt2x00_get_field16(eeprom,
1990 EEPROM_TXPOWER_DELTA_TYPE_5G);
1991 comp_value = rt2x00_get_field16(eeprom,
1992 EEPROM_TXPOWER_DELTA_VALUE_5G);
1993 if (!comp_type)
1994 comp_value = -comp_value;
1995 }
1996 }
1997
1998 return comp_value;
1999}
2000
2001static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2002 enum ieee80211_band band, int power_level,
2003 u8 txpower, int delta)
2004{
2005 u32 reg;
2006 u16 eeprom;
2007 u8 criterion;
2008 u8 eirp_txpower;
2009 u8 eirp_txpower_criterion;
2010 u8 reg_limit;
2011
2012 if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
2013 return txpower;
2014
2015 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
2016 /*
2017 * Check if eirp txpower exceed txpower_limit.
2018 * We use OFDM 6M as criterion and its eirp txpower
2019 * is stored at EEPROM_EIRP_MAX_TX_POWER.
2020 * .11b data rate need add additional 4dbm
2021 * when calculating eirp txpower.
2022 */
2023 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
2024 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
2025
2026 rt2x00_eeprom_read(rt2x00dev,
2027 EEPROM_EIRP_MAX_TX_POWER, &eeprom);
2028
2029 if (band == IEEE80211_BAND_2GHZ)
2030 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2031 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2032 else
2033 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2034 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2035
2036 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2037 (is_rate_b ? 4 : 0) + delta;
2038
2039 reg_limit = (eirp_txpower > power_level) ?
2040 (eirp_txpower - power_level) : 0;
2041 } else
2042 reg_limit = 0;
2043
2044 return txpower + delta - reg_limit;
1296} 2045}
1297 2046
1298static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev, 2047static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
1299 const int max_txpower) 2048 enum ieee80211_band band,
2049 int power_level)
1300{ 2050{
1301 u8 txpower; 2051 u8 txpower;
1302 u8 max_value = (u8)max_txpower;
1303 u16 eeprom; 2052 u16 eeprom;
1304 int i; 2053 int i, is_rate_b;
1305 u32 reg; 2054 u32 reg;
1306 u8 r1; 2055 u8 r1;
1307 u32 offset; 2056 u32 offset;
2057 int delta;
1308 2058
1309 /* 2059 /*
1310 * set to normal tx power mode: +/- 0dBm 2060 * Calculate HT40 compensation delta
1311 */ 2061 */
1312 rt2800_bbp_read(rt2x00dev, 1, &r1); 2062 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
1313 rt2x00_set_field8(&r1, BBP1_TX_POWER, 0);
1314 rt2800_bbp_write(rt2x00dev, 1, r1);
1315 2063
1316 /* 2064 /*
1317 * The eeprom contains the tx power values for each rate. These 2065 * calculate temperature compensation delta
1318 * values map to 100% tx power. Each 16bit word contains four tx
1319 * power values and the order is the same as used in the TX_PWR_CFG
1320 * registers.
1321 */ 2066 */
2067 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
2068
2069 /*
2070 * set to normal bbp tx power control mode: +/- 0dBm
2071 */
2072 rt2800_bbp_read(rt2x00dev, 1, &r1);
2073 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
2074 rt2800_bbp_write(rt2x00dev, 1, r1);
1322 offset = TX_PWR_CFG_0; 2075 offset = TX_PWR_CFG_0;
1323 2076
1324 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) { 2077 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
@@ -1332,73 +2085,99 @@ static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
1332 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i, 2085 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
1333 &eeprom); 2086 &eeprom);
1334 2087
1335 /* TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS, 2088 is_rate_b = i ? 0 : 1;
2089 /*
2090 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
1336 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12, 2091 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
1337 * TX_PWR_CFG_4: unknown */ 2092 * TX_PWR_CFG_4: unknown
2093 */
1338 txpower = rt2x00_get_field16(eeprom, 2094 txpower = rt2x00_get_field16(eeprom,
1339 EEPROM_TXPOWER_BYRATE_RATE0); 2095 EEPROM_TXPOWER_BYRATE_RATE0);
1340 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, 2096 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
1341 min(txpower, max_value)); 2097 power_level, txpower, delta);
2098 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
1342 2099
1343 /* TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS, 2100 /*
2101 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
1344 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13, 2102 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
1345 * TX_PWR_CFG_4: unknown */ 2103 * TX_PWR_CFG_4: unknown
2104 */
1346 txpower = rt2x00_get_field16(eeprom, 2105 txpower = rt2x00_get_field16(eeprom,
1347 EEPROM_TXPOWER_BYRATE_RATE1); 2106 EEPROM_TXPOWER_BYRATE_RATE1);
1348 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, 2107 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
1349 min(txpower, max_value)); 2108 power_level, txpower, delta);
2109 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
1350 2110
1351 /* TX_PWR_CFG_0: 55MBS, TX_PWR_CFG_1: 48MBS, 2111 /*
2112 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
1352 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14, 2113 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
1353 * TX_PWR_CFG_4: unknown */ 2114 * TX_PWR_CFG_4: unknown
2115 */
1354 txpower = rt2x00_get_field16(eeprom, 2116 txpower = rt2x00_get_field16(eeprom,
1355 EEPROM_TXPOWER_BYRATE_RATE2); 2117 EEPROM_TXPOWER_BYRATE_RATE2);
1356 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, 2118 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
1357 min(txpower, max_value)); 2119 power_level, txpower, delta);
2120 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
1358 2121
1359 /* TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS, 2122 /*
2123 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
1360 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15, 2124 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
1361 * TX_PWR_CFG_4: unknown */ 2125 * TX_PWR_CFG_4: unknown
2126 */
1362 txpower = rt2x00_get_field16(eeprom, 2127 txpower = rt2x00_get_field16(eeprom,
1363 EEPROM_TXPOWER_BYRATE_RATE3); 2128 EEPROM_TXPOWER_BYRATE_RATE3);
1364 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, 2129 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
1365 min(txpower, max_value)); 2130 power_level, txpower, delta);
2131 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
1366 2132
1367 /* read the next four txpower values */ 2133 /* read the next four txpower values */
1368 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1, 2134 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
1369 &eeprom); 2135 &eeprom);
1370 2136
1371 /* TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0, 2137 is_rate_b = 0;
2138 /*
2139 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
1372 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown, 2140 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
1373 * TX_PWR_CFG_4: unknown */ 2141 * TX_PWR_CFG_4: unknown
2142 */
1374 txpower = rt2x00_get_field16(eeprom, 2143 txpower = rt2x00_get_field16(eeprom,
1375 EEPROM_TXPOWER_BYRATE_RATE0); 2144 EEPROM_TXPOWER_BYRATE_RATE0);
1376 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, 2145 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
1377 min(txpower, max_value)); 2146 power_level, txpower, delta);
2147 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
1378 2148
1379 /* TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1, 2149 /*
2150 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
1380 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown, 2151 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
1381 * TX_PWR_CFG_4: unknown */ 2152 * TX_PWR_CFG_4: unknown
2153 */
1382 txpower = rt2x00_get_field16(eeprom, 2154 txpower = rt2x00_get_field16(eeprom,
1383 EEPROM_TXPOWER_BYRATE_RATE1); 2155 EEPROM_TXPOWER_BYRATE_RATE1);
1384 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, 2156 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
1385 min(txpower, max_value)); 2157 power_level, txpower, delta);
2158 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
1386 2159
1387 /* TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2, 2160 /*
2161 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
1388 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown, 2162 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
1389 * TX_PWR_CFG_4: unknown */ 2163 * TX_PWR_CFG_4: unknown
2164 */
1390 txpower = rt2x00_get_field16(eeprom, 2165 txpower = rt2x00_get_field16(eeprom,
1391 EEPROM_TXPOWER_BYRATE_RATE2); 2166 EEPROM_TXPOWER_BYRATE_RATE2);
1392 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, 2167 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
1393 min(txpower, max_value)); 2168 power_level, txpower, delta);
2169 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
1394 2170
1395 /* TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3, 2171 /*
2172 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
1396 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown, 2173 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
1397 * TX_PWR_CFG_4: unknown */ 2174 * TX_PWR_CFG_4: unknown
2175 */
1398 txpower = rt2x00_get_field16(eeprom, 2176 txpower = rt2x00_get_field16(eeprom,
1399 EEPROM_TXPOWER_BYRATE_RATE3); 2177 EEPROM_TXPOWER_BYRATE_RATE3);
1400 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, 2178 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
1401 min(txpower, max_value)); 2179 power_level, txpower, delta);
2180 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
1402 2181
1403 rt2800_register_write(rt2x00dev, offset, reg); 2182 rt2800_register_write(rt2x00dev, offset, reg);
1404 2183
@@ -1407,6 +2186,13 @@ static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
1407 } 2186 }
1408} 2187}
1409 2188
2189void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
2190{
2191 rt2800_config_txpower(rt2x00dev, rt2x00dev->curr_band,
2192 rt2x00dev->tx_power);
2193}
2194EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
2195
1410static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev, 2196static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1411 struct rt2x00lib_conf *libconf) 2197 struct rt2x00lib_conf *libconf)
1412{ 2198{
@@ -1457,11 +2243,15 @@ void rt2800_config(struct rt2x00_dev *rt2x00dev,
1457 /* Always recalculate LNA gain before changing configuration */ 2243 /* Always recalculate LNA gain before changing configuration */
1458 rt2800_config_lna_gain(rt2x00dev, libconf); 2244 rt2800_config_lna_gain(rt2x00dev, libconf);
1459 2245
1460 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) 2246 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
1461 rt2800_config_channel(rt2x00dev, libconf->conf, 2247 rt2800_config_channel(rt2x00dev, libconf->conf,
1462 &libconf->rf, &libconf->channel); 2248 &libconf->rf, &libconf->channel);
2249 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2250 libconf->conf->power_level);
2251 }
1463 if (flags & IEEE80211_CONF_CHANGE_POWER) 2252 if (flags & IEEE80211_CONF_CHANGE_POWER)
1464 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level); 2253 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2254 libconf->conf->power_level);
1465 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 2255 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1466 rt2800_config_retry_limit(rt2x00dev, libconf); 2256 rt2800_config_retry_limit(rt2x00dev, libconf);
1467 if (flags & IEEE80211_CONF_CHANGE_PS) 2257 if (flags & IEEE80211_CONF_CHANGE_PS)
@@ -1490,7 +2280,8 @@ static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1490 if (rt2x00_rt(rt2x00dev, RT3070) || 2280 if (rt2x00_rt(rt2x00dev, RT3070) ||
1491 rt2x00_rt(rt2x00dev, RT3071) || 2281 rt2x00_rt(rt2x00dev, RT3071) ||
1492 rt2x00_rt(rt2x00dev, RT3090) || 2282 rt2x00_rt(rt2x00dev, RT3090) ||
1493 rt2x00_rt(rt2x00dev, RT3390)) 2283 rt2x00_rt(rt2x00dev, RT3390) ||
2284 rt2x00_rt(rt2x00dev, RT5390))
1494 return 0x1c + (2 * rt2x00dev->lna_gain); 2285 return 0x1c + (2 * rt2x00dev->lna_gain);
1495 else 2286 else
1496 return 0x2e + rt2x00dev->lna_gain; 2287 return 0x2e + rt2x00dev->lna_gain;
@@ -1536,7 +2327,7 @@ EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1536/* 2327/*
1537 * Initialization functions. 2328 * Initialization functions.
1538 */ 2329 */
1539int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 2330static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1540{ 2331{
1541 u32 reg; 2332 u32 reg;
1542 u16 eeprom; 2333 u16 eeprom;
@@ -1598,8 +2389,8 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1598 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 2389 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1599 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 2390 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1600 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 2391 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
1601 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); 2392 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
1602 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST)) 2393 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
1603 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 2394 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1604 0x0000002c); 2395 0x0000002c);
1605 else 2396 else
@@ -1621,7 +2412,11 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1621 } else if (rt2800_is_305x_soc(rt2x00dev)) { 2412 } else if (rt2800_is_305x_soc(rt2x00dev)) {
1622 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 2413 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1623 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 2414 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1624 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f); 2415 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
2416 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2417 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2418 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2419 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1625 } else { 2420 } else {
1626 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); 2421 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1627 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 2422 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
@@ -1690,7 +2485,7 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1690 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg); 2485 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1691 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3); 2486 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
1692 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0); 2487 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1693 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1); 2488 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
1694 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); 2489 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1695 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 2490 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1696 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); 2491 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
@@ -1703,7 +2498,7 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1703 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg); 2498 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1704 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3); 2499 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
1705 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0); 2500 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1706 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1); 2501 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
1707 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); 2502 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1708 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 2503 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1709 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); 2504 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
@@ -1716,7 +2511,7 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1716 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg); 2511 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1717 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004); 2512 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1718 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0); 2513 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1719 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1); 2514 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
1720 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1); 2515 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1721 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 2516 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1722 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 2517 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
@@ -1728,9 +2523,8 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1728 2523
1729 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg); 2524 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1730 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084); 2525 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1731 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 2526 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1732 !rt2x00_is_usb(rt2x00dev)); 2527 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
1733 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1734 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1); 2528 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1735 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 2529 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1736 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 2530 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
@@ -1743,7 +2537,7 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1743 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg); 2537 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1744 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004); 2538 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1745 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0); 2539 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1746 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1); 2540 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
1747 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1); 2541 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1748 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 2542 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1749 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 2543 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
@@ -1756,7 +2550,7 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1756 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg); 2550 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1757 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084); 2551 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1758 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0); 2552 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1759 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1); 2553 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
1760 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1); 2554 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1761 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 2555 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1762 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 2556 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
@@ -1782,7 +2576,23 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1782 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 2576 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1783 } 2577 }
1784 2578
1785 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f); 2579 /*
2580 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2581 * although it is reserved.
2582 */
2583 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2584 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2585 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2586 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2587 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2588 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2589 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2590 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2591 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2592 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2593 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2594 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2595
1786 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002); 2596 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1787 2597
1788 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg); 2598 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
@@ -1819,30 +2629,34 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1819 SHARED_KEY_MODE_ENTRY(i), 0); 2629 SHARED_KEY_MODE_ENTRY(i), 0);
1820 2630
1821 for (i = 0; i < 256; i++) { 2631 for (i = 0; i < 256; i++) {
1822 u32 wcid[2] = { 0xffffffff, 0x00ffffff }; 2632 static const u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1823 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i), 2633 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1824 wcid, sizeof(wcid)); 2634 wcid, sizeof(wcid));
1825 2635
1826 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1); 2636 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 0);
1827 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0); 2637 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1828 } 2638 }
1829 2639
1830 /* 2640 /*
1831 * Clear all beacons 2641 * Clear all beacons
1832 */ 2642 */
1833 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE0); 2643 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
1834 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE1); 2644 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
1835 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE2); 2645 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
1836 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE3); 2646 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
1837 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE4); 2647 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
1838 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE5); 2648 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
1839 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE6); 2649 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
1840 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE7); 2650 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
1841 2651
1842 if (rt2x00_is_usb(rt2x00dev)) { 2652 if (rt2x00_is_usb(rt2x00dev)) {
1843 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg); 2653 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
1844 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30); 2654 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
1845 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 2655 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2656 } else if (rt2x00_is_pcie(rt2x00dev)) {
2657 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2658 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
2659 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
1846 } 2660 }
1847 2661
1848 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg); 2662 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
@@ -1886,6 +2700,14 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1886 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg); 2700 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1887 2701
1888 /* 2702 /*
2703 * Do not force the BA window size, we use the TXWI to set it
2704 */
2705 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2706 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2707 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2708 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2709
2710 /*
1889 * We must clear the error counters. 2711 * We must clear the error counters.
1890 * These registers are cleared on read, 2712 * These registers are cleared on read,
1891 * so we may pass a useless variable to store the value. 2713 * so we may pass a useless variable to store the value.
@@ -1904,9 +2726,19 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1904 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4); 2726 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
1905 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg); 2727 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
1906 2728
2729 /*
2730 * Set up channel statistics timer
2731 */
2732 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
2733 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
2734 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
2735 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
2736 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
2737 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
2738 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
2739
1907 return 0; 2740 return 0;
1908} 2741}
1909EXPORT_SYMBOL_GPL(rt2800_init_registers);
1910 2742
1911static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev) 2743static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1912{ 2744{
@@ -1949,7 +2781,7 @@ static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1949 return -EACCES; 2781 return -EACCES;
1950} 2782}
1951 2783
1952int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) 2784static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1953{ 2785{
1954 unsigned int i; 2786 unsigned int i;
1955 u16 eeprom; 2787 u16 eeprom;
@@ -1960,15 +2792,31 @@ int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1960 rt2800_wait_bbp_ready(rt2x00dev))) 2792 rt2800_wait_bbp_ready(rt2x00dev)))
1961 return -EACCES; 2793 return -EACCES;
1962 2794
1963 if (rt2800_is_305x_soc(rt2x00dev)) 2795 if (rt2x00_rt(rt2x00dev, RT5390)) {
2796 rt2800_bbp_read(rt2x00dev, 4, &value);
2797 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
2798 rt2800_bbp_write(rt2x00dev, 4, value);
2799 }
2800
2801 if (rt2800_is_305x_soc(rt2x00dev) ||
2802 rt2x00_rt(rt2x00dev, RT5390))
1964 rt2800_bbp_write(rt2x00dev, 31, 0x08); 2803 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1965 2804
1966 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 2805 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1967 rt2800_bbp_write(rt2x00dev, 66, 0x38); 2806 rt2800_bbp_write(rt2x00dev, 66, 0x38);
1968 2807
2808 if (rt2x00_rt(rt2x00dev, RT5390))
2809 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2810
1969 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 2811 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1970 rt2800_bbp_write(rt2x00dev, 69, 0x16); 2812 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1971 rt2800_bbp_write(rt2x00dev, 73, 0x12); 2813 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2814 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2815 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2816 rt2800_bbp_write(rt2x00dev, 73, 0x13);
2817 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2818 rt2800_bbp_write(rt2x00dev, 76, 0x28);
2819 rt2800_bbp_write(rt2x00dev, 77, 0x59);
1972 } else { 2820 } else {
1973 rt2800_bbp_write(rt2x00dev, 69, 0x12); 2821 rt2800_bbp_write(rt2x00dev, 69, 0x12);
1974 rt2800_bbp_write(rt2x00dev, 73, 0x10); 2822 rt2800_bbp_write(rt2x00dev, 73, 0x10);
@@ -1979,7 +2827,8 @@ int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1979 if (rt2x00_rt(rt2x00dev, RT3070) || 2827 if (rt2x00_rt(rt2x00dev, RT3070) ||
1980 rt2x00_rt(rt2x00dev, RT3071) || 2828 rt2x00_rt(rt2x00dev, RT3071) ||
1981 rt2x00_rt(rt2x00dev, RT3090) || 2829 rt2x00_rt(rt2x00dev, RT3090) ||
1982 rt2x00_rt(rt2x00dev, RT3390)) { 2830 rt2x00_rt(rt2x00dev, RT3390) ||
2831 rt2x00_rt(rt2x00dev, RT5390)) {
1983 rt2800_bbp_write(rt2x00dev, 79, 0x13); 2832 rt2800_bbp_write(rt2x00dev, 79, 0x13);
1984 rt2800_bbp_write(rt2x00dev, 80, 0x05); 2833 rt2800_bbp_write(rt2x00dev, 80, 0x05);
1985 rt2800_bbp_write(rt2x00dev, 81, 0x33); 2834 rt2800_bbp_write(rt2x00dev, 81, 0x33);
@@ -1991,46 +2840,108 @@ int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1991 } 2840 }
1992 2841
1993 rt2800_bbp_write(rt2x00dev, 82, 0x62); 2842 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1994 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 2843 if (rt2x00_rt(rt2x00dev, RT5390))
2844 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
2845 else
2846 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1995 2847
1996 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D)) 2848 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
1997 rt2800_bbp_write(rt2x00dev, 84, 0x19); 2849 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2850 else if (rt2x00_rt(rt2x00dev, RT5390))
2851 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
1998 else 2852 else
1999 rt2800_bbp_write(rt2x00dev, 84, 0x99); 2853 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2000 2854
2001 rt2800_bbp_write(rt2x00dev, 86, 0x00); 2855 if (rt2x00_rt(rt2x00dev, RT5390))
2856 rt2800_bbp_write(rt2x00dev, 86, 0x38);
2857 else
2858 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2859
2002 rt2800_bbp_write(rt2x00dev, 91, 0x04); 2860 rt2800_bbp_write(rt2x00dev, 91, 0x04);
2003 rt2800_bbp_write(rt2x00dev, 92, 0x00); 2861
2862 if (rt2x00_rt(rt2x00dev, RT5390))
2863 rt2800_bbp_write(rt2x00dev, 92, 0x02);
2864 else
2865 rt2800_bbp_write(rt2x00dev, 92, 0x00);
2004 2866
2005 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) || 2867 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
2006 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) || 2868 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
2007 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) || 2869 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
2008 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) || 2870 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2871 rt2x00_rt(rt2x00dev, RT5390) ||
2009 rt2800_is_305x_soc(rt2x00dev)) 2872 rt2800_is_305x_soc(rt2x00dev))
2010 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 2873 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2011 else 2874 else
2012 rt2800_bbp_write(rt2x00dev, 103, 0x00); 2875 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2013 2876
2877 if (rt2x00_rt(rt2x00dev, RT5390))
2878 rt2800_bbp_write(rt2x00dev, 104, 0x92);
2879
2014 if (rt2800_is_305x_soc(rt2x00dev)) 2880 if (rt2800_is_305x_soc(rt2x00dev))
2015 rt2800_bbp_write(rt2x00dev, 105, 0x01); 2881 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2882 else if (rt2x00_rt(rt2x00dev, RT5390))
2883 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
2016 else 2884 else
2017 rt2800_bbp_write(rt2x00dev, 105, 0x05); 2885 rt2800_bbp_write(rt2x00dev, 105, 0x05);
2018 rt2800_bbp_write(rt2x00dev, 106, 0x35); 2886
2887 if (rt2x00_rt(rt2x00dev, RT5390))
2888 rt2800_bbp_write(rt2x00dev, 106, 0x03);
2889 else
2890 rt2800_bbp_write(rt2x00dev, 106, 0x35);
2891
2892 if (rt2x00_rt(rt2x00dev, RT5390))
2893 rt2800_bbp_write(rt2x00dev, 128, 0x12);
2019 2894
2020 if (rt2x00_rt(rt2x00dev, RT3071) || 2895 if (rt2x00_rt(rt2x00dev, RT3071) ||
2021 rt2x00_rt(rt2x00dev, RT3090) || 2896 rt2x00_rt(rt2x00dev, RT3090) ||
2022 rt2x00_rt(rt2x00dev, RT3390)) { 2897 rt2x00_rt(rt2x00dev, RT3390) ||
2898 rt2x00_rt(rt2x00dev, RT5390)) {
2023 rt2800_bbp_read(rt2x00dev, 138, &value); 2899 rt2800_bbp_read(rt2x00dev, 138, &value);
2024 2900
2025 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); 2901 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2026 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1) 2902 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
2027 value |= 0x20; 2903 value |= 0x20;
2028 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) 2904 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
2029 value &= ~0x02; 2905 value &= ~0x02;
2030 2906
2031 rt2800_bbp_write(rt2x00dev, 138, value); 2907 rt2800_bbp_write(rt2x00dev, 138, value);
2032 } 2908 }
2033 2909
2910 if (rt2x00_rt(rt2x00dev, RT5390)) {
2911 int ant, div_mode;
2912
2913 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2914 div_mode = rt2x00_get_field16(eeprom,
2915 EEPROM_NIC_CONF1_ANT_DIVERSITY);
2916 ant = (div_mode == 3) ? 1 : 0;
2917
2918 /* check if this is a Bluetooth combo card */
2919 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2920 u32 reg;
2921
2922 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
2923 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
2924 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
2925 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
2926 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
2927 if (ant == 0)
2928 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
2929 else if (ant == 1)
2930 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
2931 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
2932 }
2933
2934 rt2800_bbp_read(rt2x00dev, 152, &value);
2935 if (ant == 0)
2936 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
2937 else
2938 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
2939 rt2800_bbp_write(rt2x00dev, 152, value);
2940
2941 /* Init frequency calibration */
2942 rt2800_bbp_write(rt2x00dev, 142, 1);
2943 rt2800_bbp_write(rt2x00dev, 143, 57);
2944 }
2034 2945
2035 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 2946 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2036 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); 2947 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
@@ -2044,7 +2955,6 @@ int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2044 2955
2045 return 0; 2956 return 0;
2046} 2957}
2047EXPORT_SYMBOL_GPL(rt2800_init_bbp);
2048 2958
2049static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, 2959static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2050 bool bw40, u8 rfcsr24, u8 filter_target) 2960 bool bw40, u8 rfcsr24, u8 filter_target)
@@ -2062,6 +2972,10 @@ static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2062 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40); 2972 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2063 rt2800_bbp_write(rt2x00dev, 4, bbp); 2973 rt2800_bbp_write(rt2x00dev, 4, bbp);
2064 2974
2975 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2976 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
2977 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2978
2065 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); 2979 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2066 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1); 2980 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2067 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 2981 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
@@ -2106,7 +3020,7 @@ static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2106 return rfcsr24; 3020 return rfcsr24;
2107} 3021}
2108 3022
2109int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) 3023static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2110{ 3024{
2111 u8 rfcsr; 3025 u8 rfcsr;
2112 u8 bbp; 3026 u8 bbp;
@@ -2117,18 +3031,28 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2117 !rt2x00_rt(rt2x00dev, RT3071) && 3031 !rt2x00_rt(rt2x00dev, RT3071) &&
2118 !rt2x00_rt(rt2x00dev, RT3090) && 3032 !rt2x00_rt(rt2x00dev, RT3090) &&
2119 !rt2x00_rt(rt2x00dev, RT3390) && 3033 !rt2x00_rt(rt2x00dev, RT3390) &&
3034 !rt2x00_rt(rt2x00dev, RT5390) &&
2120 !rt2800_is_305x_soc(rt2x00dev)) 3035 !rt2800_is_305x_soc(rt2x00dev))
2121 return 0; 3036 return 0;
2122 3037
2123 /* 3038 /*
2124 * Init RF calibration. 3039 * Init RF calibration.
2125 */ 3040 */
2126 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); 3041 if (rt2x00_rt(rt2x00dev, RT5390)) {
2127 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); 3042 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
2128 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 3043 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
2129 msleep(1); 3044 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
2130 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); 3045 msleep(1);
2131 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 3046 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
3047 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3048 } else {
3049 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3050 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
3051 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3052 msleep(1);
3053 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
3054 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3055 }
2132 3056
2133 if (rt2x00_rt(rt2x00dev, RT3070) || 3057 if (rt2x00_rt(rt2x00dev, RT3070) ||
2134 rt2x00_rt(rt2x00dev, RT3071) || 3058 rt2x00_rt(rt2x00dev, RT3071) ||
@@ -2136,7 +3060,7 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2136 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 3060 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2137 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 3061 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2138 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 3062 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2139 rt2800_rfcsr_write(rt2x00dev, 7, 0x70); 3063 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
2140 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 3064 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2141 rt2800_rfcsr_write(rt2x00dev, 10, 0x41); 3065 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
2142 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 3066 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
@@ -2219,6 +3143,87 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2219 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 3143 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2220 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 3144 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2221 return 0; 3145 return 0;
3146 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3147 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3148 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3149 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3150 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3151 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3152 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3153 else
3154 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3155 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3156 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3157 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3158 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
3159 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3160 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3161 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3162 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3163 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3164 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
3165
3166 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3167 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
3168 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3169 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
3170 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
3171 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3172 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3173 else
3174 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
3175 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
3176 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3177 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3178 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3179
3180 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3181 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3182 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3183 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3184 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3185 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3186 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3187 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3188 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3189 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3190
3191 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3192 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3193 else
3194 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3195 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3196 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3197 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3198 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3199 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3200 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3201 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3202 else
3203 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3204 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3205 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3206 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3207
3208 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3209 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3210 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3211 else
3212 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3213 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3214 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3215 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3216 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3217 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3218 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3219
3220 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3221 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3222 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3223 else
3224 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3225 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3226 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
2222 } 3227 }
2223 3228
2224 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 3229 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
@@ -2228,23 +3233,27 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2228 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 3233 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2229 } else if (rt2x00_rt(rt2x00dev, RT3071) || 3234 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2230 rt2x00_rt(rt2x00dev, RT3090)) { 3235 rt2x00_rt(rt2x00dev, RT3090)) {
3236 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
3237
2231 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); 3238 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2232 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 3239 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
2233 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 3240 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2234 3241
2235 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
2236
2237 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg); 3242 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2238 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1); 3243 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2239 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 3244 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2240 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) { 3245 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
2241 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); 3246 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2242 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST)) 3247 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
2243 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3); 3248 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2244 else 3249 else
2245 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0); 3250 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
2246 } 3251 }
2247 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 3252 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3253
3254 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3255 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3256 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
2248 } else if (rt2x00_rt(rt2x00dev, RT3390)) { 3257 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2249 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg); 3258 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
2250 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0); 3259 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
@@ -2268,21 +3277,23 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2268 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15); 3277 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
2269 } 3278 }
2270 3279
2271 /* 3280 if (!rt2x00_rt(rt2x00dev, RT5390)) {
2272 * Set back to initial state 3281 /*
2273 */ 3282 * Set back to initial state
2274 rt2800_bbp_write(rt2x00dev, 24, 0); 3283 */
3284 rt2800_bbp_write(rt2x00dev, 24, 0);
2275 3285
2276 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); 3286 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2277 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0); 3287 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
2278 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 3288 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2279 3289
2280 /* 3290 /*
2281 * set BBP back to BW20 3291 * Set BBP back to BW20
2282 */ 3292 */
2283 rt2800_bbp_read(rt2x00dev, 4, &bbp); 3293 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2284 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); 3294 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
2285 rt2800_bbp_write(rt2x00dev, 4, bbp); 3295 rt2800_bbp_write(rt2x00dev, 4, bbp);
3296 }
2286 3297
2287 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) || 3298 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2288 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 3299 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
@@ -2294,28 +3305,33 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2294 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1); 3305 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
2295 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); 3306 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2296 3307
2297 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr); 3308 if (!rt2x00_rt(rt2x00dev, RT5390)) {
2298 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0); 3309 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2299 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 3310 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
2300 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 3311 if (rt2x00_rt(rt2x00dev, RT3070) ||
2301 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 3312 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2302 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) 3313 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2303 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1); 3314 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2304 } 3315 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2305 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom); 3316 &rt2x00dev->cap_flags))
2306 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1) 3317 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
2307 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN, 3318 }
2308 rt2x00_get_field16(eeprom, 3319 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2309 EEPROM_TXMIXER_GAIN_BG_VAL)); 3320 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2310 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 3321 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
3322 rt2x00_get_field16(eeprom,
3323 EEPROM_TXMIXER_GAIN_BG_VAL));
3324 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3325 }
2311 3326
2312 if (rt2x00_rt(rt2x00dev, RT3090)) { 3327 if (rt2x00_rt(rt2x00dev, RT3090)) {
2313 rt2800_bbp_read(rt2x00dev, 138, &bbp); 3328 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2314 3329
2315 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); 3330 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
2316 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) 3331 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3332 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
2317 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0); 3333 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
2318 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1) 3334 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
2319 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1); 3335 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
2320 3336
2321 rt2800_bbp_write(rt2x00dev, 138, bbp); 3337 rt2800_bbp_write(rt2x00dev, 138, bbp);
@@ -2345,10 +3361,9 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2345 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 3361 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2346 } 3362 }
2347 3363
2348 if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) { 3364 if (rt2x00_rt(rt2x00dev, RT3070)) {
2349 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr); 3365 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
2350 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) || 3366 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
2351 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
2352 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3); 3367 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
2353 else 3368 else
2354 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0); 3369 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
@@ -2358,9 +3373,110 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2358 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr); 3373 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2359 } 3374 }
2360 3375
3376 if (rt2x00_rt(rt2x00dev, RT5390)) {
3377 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
3378 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
3379 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
3380
3381 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
3382 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
3383 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3384
3385 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3386 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
3387 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3388 }
3389
2361 return 0; 3390 return 0;
2362} 3391}
2363EXPORT_SYMBOL_GPL(rt2800_init_rfcsr); 3392
3393int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
3394{
3395 u32 reg;
3396 u16 word;
3397
3398 /*
3399 * Initialize all registers.
3400 */
3401 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
3402 rt2800_init_registers(rt2x00dev) ||
3403 rt2800_init_bbp(rt2x00dev) ||
3404 rt2800_init_rfcsr(rt2x00dev)))
3405 return -EIO;
3406
3407 /*
3408 * Send signal to firmware during boot time.
3409 */
3410 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
3411
3412 if (rt2x00_is_usb(rt2x00dev) &&
3413 (rt2x00_rt(rt2x00dev, RT3070) ||
3414 rt2x00_rt(rt2x00dev, RT3071) ||
3415 rt2x00_rt(rt2x00dev, RT3572))) {
3416 udelay(200);
3417 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
3418 udelay(10);
3419 }
3420
3421 /*
3422 * Enable RX.
3423 */
3424 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3425 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3426 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3427 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3428
3429 udelay(50);
3430
3431 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3432 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
3433 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
3434 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
3435 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
3436 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3437
3438 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3439 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3440 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
3441 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3442
3443 /*
3444 * Initialize LED control
3445 */
3446 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
3447 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
3448 word & 0xff, (word >> 8) & 0xff);
3449
3450 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
3451 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
3452 word & 0xff, (word >> 8) & 0xff);
3453
3454 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
3455 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
3456 word & 0xff, (word >> 8) & 0xff);
3457
3458 return 0;
3459}
3460EXPORT_SYMBOL_GPL(rt2800_enable_radio);
3461
3462void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
3463{
3464 u32 reg;
3465
3466 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3467 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3468 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3469 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3470
3471 /* Wait for DMA, ignore error */
3472 rt2800_wait_wpdma_ready(rt2x00dev);
3473
3474 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3475 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
3476 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3477 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3478}
3479EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2364 3480
2365int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev) 3481int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
2366{ 3482{
@@ -2424,38 +3540,41 @@ int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2424 EEPROM(rt2x00dev, "MAC: %pM\n", mac); 3540 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2425 } 3541 }
2426 3542
2427 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); 3543 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
2428 if (word == 0xffff) { 3544 if (word == 0xffff) {
2429 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2); 3545 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
2430 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1); 3546 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
2431 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820); 3547 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
2432 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); 3548 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
2433 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word); 3549 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2434 } else if (rt2x00_rt(rt2x00dev, RT2860) || 3550 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
2435 rt2x00_rt(rt2x00dev, RT2872)) { 3551 rt2x00_rt(rt2x00dev, RT2872)) {
2436 /* 3552 /*
2437 * There is a max of 2 RX streams for RT28x0 series 3553 * There is a max of 2 RX streams for RT28x0 series
2438 */ 3554 */
2439 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2) 3555 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
2440 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2); 3556 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
2441 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); 3557 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
2442 } 3558 }
2443 3559
2444 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word); 3560 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
2445 if (word == 0xffff) { 3561 if (word == 0xffff) {
2446 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0); 3562 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
2447 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0); 3563 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
2448 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0); 3564 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
2449 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0); 3565 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
2450 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0); 3566 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
2451 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0); 3567 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
2452 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0); 3568 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
2453 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0); 3569 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
2454 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0); 3570 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
2455 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0); 3571 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
2456 rt2x00_set_field16(&word, EEPROM_NIC_ANT_DIVERSITY, 0); 3572 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
2457 rt2x00_set_field16(&word, EEPROM_NIC_DAC_TEST, 0); 3573 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
2458 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word); 3574 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
3575 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
3576 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3577 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
2459 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word); 3578 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2460 } 3579 }
2461 3580
@@ -2470,9 +3589,9 @@ int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2470 LED_MODE_TXRX_ACTIVITY); 3589 LED_MODE_TXRX_ACTIVITY);
2471 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0); 3590 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2472 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 3591 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2473 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555); 3592 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
2474 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221); 3593 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
2475 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8); 3594 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
2476 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word); 3595 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
2477 } 3596 }
2478 3597
@@ -2529,13 +3648,18 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2529 /* 3648 /*
2530 * Read EEPROM word for configuration. 3649 * Read EEPROM word for configuration.
2531 */ 3650 */
2532 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); 3651 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2533 3652
2534 /* 3653 /*
2535 * Identify RF chipset. 3654 * Identify RF chipset by EEPROM value
3655 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
3656 * RT53xx: defined in "EEPROM_CHIP_ID" field
2536 */ 3657 */
2537 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2538 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg); 3658 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
3659 if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390)
3660 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
3661 else
3662 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
2539 3663
2540 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET), 3664 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2541 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION)); 3665 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
@@ -2547,7 +3671,8 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2547 !rt2x00_rt(rt2x00dev, RT3071) && 3671 !rt2x00_rt(rt2x00dev, RT3071) &&
2548 !rt2x00_rt(rt2x00dev, RT3090) && 3672 !rt2x00_rt(rt2x00dev, RT3090) &&
2549 !rt2x00_rt(rt2x00dev, RT3390) && 3673 !rt2x00_rt(rt2x00dev, RT3390) &&
2550 !rt2x00_rt(rt2x00dev, RT3572)) { 3674 !rt2x00_rt(rt2x00dev, RT3572) &&
3675 !rt2x00_rt(rt2x00dev, RT5390)) {
2551 ERROR(rt2x00dev, "Invalid RT chipset detected.\n"); 3676 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2552 return -ENODEV; 3677 return -ENODEV;
2553 } 3678 }
@@ -2560,7 +3685,10 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2560 !rt2x00_rf(rt2x00dev, RF2020) && 3685 !rt2x00_rf(rt2x00dev, RF2020) &&
2561 !rt2x00_rf(rt2x00dev, RF3021) && 3686 !rt2x00_rf(rt2x00dev, RF3021) &&
2562 !rt2x00_rf(rt2x00dev, RF3022) && 3687 !rt2x00_rf(rt2x00dev, RF3022) &&
2563 !rt2x00_rf(rt2x00dev, RF3052)) { 3688 !rt2x00_rf(rt2x00dev, RF3052) &&
3689 !rt2x00_rf(rt2x00dev, RF3320) &&
3690 !rt2x00_rf(rt2x00dev, RF5370) &&
3691 !rt2x00_rf(rt2x00dev, RF5390)) {
2564 ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); 3692 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2565 return -ENODEV; 3693 return -ENODEV;
2566 } 3694 }
@@ -2568,32 +3696,60 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2568 /* 3696 /*
2569 * Identify default antenna configuration. 3697 * Identify default antenna configuration.
2570 */ 3698 */
2571 rt2x00dev->default_ant.tx = 3699 rt2x00dev->default_ant.tx_chain_num =
2572 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH); 3700 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
2573 rt2x00dev->default_ant.rx = 3701 rt2x00dev->default_ant.rx_chain_num =
2574 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH); 3702 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
3703
3704 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3705
3706 if (rt2x00_rt(rt2x00dev, RT3070) ||
3707 rt2x00_rt(rt2x00dev, RT3090) ||
3708 rt2x00_rt(rt2x00dev, RT3390)) {
3709 value = rt2x00_get_field16(eeprom,
3710 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3711 switch (value) {
3712 case 0:
3713 case 1:
3714 case 2:
3715 rt2x00dev->default_ant.tx = ANTENNA_A;
3716 rt2x00dev->default_ant.rx = ANTENNA_A;
3717 break;
3718 case 3:
3719 rt2x00dev->default_ant.tx = ANTENNA_A;
3720 rt2x00dev->default_ant.rx = ANTENNA_B;
3721 break;
3722 }
3723 } else {
3724 rt2x00dev->default_ant.tx = ANTENNA_A;
3725 rt2x00dev->default_ant.rx = ANTENNA_A;
3726 }
2575 3727
2576 /* 3728 /*
2577 * Read frequency offset and RF programming sequence. 3729 * Determine external LNA informations.
2578 */ 3730 */
2579 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); 3731 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
2580 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); 3732 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
3733 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
3734 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
2581 3735
2582 /* 3736 /*
2583 * Read external LNA informations. 3737 * Detect if this device has an hardware controlled radio.
2584 */ 3738 */
2585 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); 3739 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
3740 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
2586 3741
2587 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A)) 3742 /*
2588 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags); 3743 * Detect if this device has Bluetooth co-existence.
2589 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG)) 3744 */
2590 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags); 3745 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
3746 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
2591 3747
2592 /* 3748 /*
2593 * Detect if this device has an hardware controlled radio. 3749 * Read frequency offset and RF programming sequence.
2594 */ 3750 */
2595 if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO)) 3751 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2596 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags); 3752 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2597 3753
2598 /* 3754 /*
2599 * Store led settings, for correct led behaviour. 3755 * Store led settings, for correct led behaviour.
@@ -2603,9 +3759,18 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2603 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); 3759 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2604 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY); 3760 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2605 3761
2606 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg); 3762 rt2x00dev->led_mcu_reg = eeprom;
2607#endif /* CONFIG_RT2X00_LIB_LEDS */ 3763#endif /* CONFIG_RT2X00_LIB_LEDS */
2608 3764
3765 /*
3766 * Check if support EIRP tx power limit feature.
3767 */
3768 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
3769
3770 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
3771 EIRP_MAX_TX_POWER_LIMIT)
3772 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
3773
2609 return 0; 3774 return 0;
2610} 3775}
2611EXPORT_SYMBOL_GPL(rt2800_init_eeprom); 3776EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
@@ -2755,8 +3920,8 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2755{ 3920{
2756 struct hw_mode_spec *spec = &rt2x00dev->spec; 3921 struct hw_mode_spec *spec = &rt2x00dev->spec;
2757 struct channel_info *info; 3922 struct channel_info *info;
2758 char *tx_power1; 3923 char *default_power1;
2759 char *tx_power2; 3924 char *default_power2;
2760 unsigned int i; 3925 unsigned int i;
2761 u16 eeprom; 3926 u16 eeprom;
2762 3927
@@ -2770,11 +3935,20 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2770 * Initialize all hw fields. 3935 * Initialize all hw fields.
2771 */ 3936 */
2772 rt2x00dev->hw->flags = 3937 rt2x00dev->hw->flags =
2773 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2774 IEEE80211_HW_SIGNAL_DBM | 3938 IEEE80211_HW_SIGNAL_DBM |
2775 IEEE80211_HW_SUPPORTS_PS | 3939 IEEE80211_HW_SUPPORTS_PS |
2776 IEEE80211_HW_PS_NULLFUNC_STACK | 3940 IEEE80211_HW_PS_NULLFUNC_STACK |
2777 IEEE80211_HW_AMPDU_AGGREGATION; 3941 IEEE80211_HW_AMPDU_AGGREGATION;
3942 /*
3943 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
3944 * unless we are capable of sending the buffered frames out after the
3945 * DTIM transmission using rt2x00lib_beacondone. This will send out
3946 * multicast and broadcast traffic immediately instead of buffering it
3947 * infinitly and thus dropping it after some time.
3948 */
3949 if (!rt2x00_is_usb(rt2x00dev))
3950 rt2x00dev->hw->flags |=
3951 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
2778 3952
2779 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); 3953 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2780 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 3954 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
@@ -2785,15 +3959,16 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2785 * As rt2800 has a global fallback table we cannot specify 3959 * As rt2800 has a global fallback table we cannot specify
2786 * more then one tx rate per frame but since the hw will 3960 * more then one tx rate per frame but since the hw will
2787 * try several rates (based on the fallback table) we should 3961 * try several rates (based on the fallback table) we should
2788 * still initialize max_rates to the maximum number of rates 3962 * initialize max_report_rates to the maximum number of rates
2789 * we are going to try. Otherwise mac80211 will truncate our 3963 * we are going to try. Otherwise mac80211 will truncate our
2790 * reported tx rates and the rc algortihm will end up with 3964 * reported tx rates and the rc algortihm will end up with
2791 * incorrect data. 3965 * incorrect data.
2792 */ 3966 */
2793 rt2x00dev->hw->max_rates = 7; 3967 rt2x00dev->hw->max_rates = 1;
3968 rt2x00dev->hw->max_report_rates = 7;
2794 rt2x00dev->hw->max_rate_tries = 1; 3969 rt2x00dev->hw->max_rate_tries = 1;
2795 3970
2796 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); 3971 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2797 3972
2798 /* 3973 /*
2799 * Initialize hw_mode information. 3974 * Initialize hw_mode information.
@@ -2813,7 +3988,10 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2813 } else if (rt2x00_rf(rt2x00dev, RF3020) || 3988 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
2814 rt2x00_rf(rt2x00dev, RF2020) || 3989 rt2x00_rf(rt2x00dev, RF2020) ||
2815 rt2x00_rf(rt2x00dev, RF3021) || 3990 rt2x00_rf(rt2x00dev, RF3021) ||
2816 rt2x00_rf(rt2x00dev, RF3022)) { 3991 rt2x00_rf(rt2x00dev, RF3022) ||
3992 rt2x00_rf(rt2x00dev, RF3320) ||
3993 rt2x00_rf(rt2x00dev, RF5370) ||
3994 rt2x00_rf(rt2x00dev, RF5390)) {
2817 spec->num_channels = 14; 3995 spec->num_channels = 14;
2818 spec->channels = rf_vals_3x; 3996 spec->channels = rf_vals_3x;
2819 } else if (rt2x00_rf(rt2x00dev, RF3052)) { 3997 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
@@ -2836,11 +4014,11 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2836 IEEE80211_HT_CAP_SGI_20 | 4014 IEEE80211_HT_CAP_SGI_20 |
2837 IEEE80211_HT_CAP_SGI_40; 4015 IEEE80211_HT_CAP_SGI_40;
2838 4016
2839 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) >= 2) 4017 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
2840 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC; 4018 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
2841 4019
2842 spec->ht.cap |= 4020 spec->ht.cap |=
2843 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) << 4021 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
2844 IEEE80211_HT_CAP_RX_STBC_SHIFT; 4022 IEEE80211_HT_CAP_RX_STBC_SHIFT;
2845 4023
2846 spec->ht.ampdu_factor = 3; 4024 spec->ht.ampdu_factor = 3;
@@ -2848,10 +4026,10 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2848 spec->ht.mcs.tx_params = 4026 spec->ht.mcs.tx_params =
2849 IEEE80211_HT_MCS_TX_DEFINED | 4027 IEEE80211_HT_MCS_TX_DEFINED |
2850 IEEE80211_HT_MCS_TX_RX_DIFF | 4028 IEEE80211_HT_MCS_TX_RX_DIFF |
2851 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) << 4029 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
2852 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); 4030 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2853 4031
2854 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) { 4032 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
2855 case 3: 4033 case 3:
2856 spec->ht.mcs.rx_mask[2] = 0xff; 4034 spec->ht.mcs.rx_mask[2] = 0xff;
2857 case 2: 4035 case 2:
@@ -2865,27 +4043,27 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2865 /* 4043 /*
2866 * Create channel information array 4044 * Create channel information array
2867 */ 4045 */
2868 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL); 4046 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
2869 if (!info) 4047 if (!info)
2870 return -ENOMEM; 4048 return -ENOMEM;
2871 4049
2872 spec->channels_info = info; 4050 spec->channels_info = info;
2873 4051
2874 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1); 4052 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2875 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2); 4053 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2876 4054
2877 for (i = 0; i < 14; i++) { 4055 for (i = 0; i < 14; i++) {
2878 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]); 4056 info[i].default_power1 = default_power1[i];
2879 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]); 4057 info[i].default_power2 = default_power2[i];
2880 } 4058 }
2881 4059
2882 if (spec->num_channels > 14) { 4060 if (spec->num_channels > 14) {
2883 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1); 4061 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2884 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2); 4062 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2885 4063
2886 for (i = 14; i < spec->num_channels; i++) { 4064 for (i = 14; i < spec->num_channels; i++) {
2887 info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]); 4065 info[i].default_power1 = default_power1[i];
2888 info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]); 4066 info[i].default_power2 = default_power2[i];
2889 } 4067 }
2890 } 4068 }
2891 4069
@@ -2977,7 +4155,7 @@ int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2977 if (queue_idx >= 4) 4155 if (queue_idx >= 4)
2978 return 0; 4156 return 0;
2979 4157
2980 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); 4158 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2981 4159
2982 /* Update WMM TXOP register */ 4160 /* Update WMM TXOP register */
2983 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2))); 4161 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
@@ -3035,15 +4213,20 @@ EXPORT_SYMBOL_GPL(rt2800_get_tsf);
3035 4213
3036int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 4214int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3037 enum ieee80211_ampdu_mlme_action action, 4215 enum ieee80211_ampdu_mlme_action action,
3038 struct ieee80211_sta *sta, u16 tid, u16 *ssn) 4216 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4217 u8 buf_size)
3039{ 4218{
3040 int ret = 0; 4219 int ret = 0;
3041 4220
3042 switch (action) { 4221 switch (action) {
3043 case IEEE80211_AMPDU_RX_START: 4222 case IEEE80211_AMPDU_RX_START:
3044 case IEEE80211_AMPDU_RX_STOP: 4223 case IEEE80211_AMPDU_RX_STOP:
3045 /* we don't support RX aggregation yet */ 4224 /*
3046 ret = -ENOTSUPP; 4225 * The hw itself takes care of setting up BlockAck mechanisms.
4226 * So, we only have to allow mac80211 to nagotiate a BlockAck
4227 * agreement. Once that is done, the hw will BlockAck incoming
4228 * AMPDUs without further setup.
4229 */
3047 break; 4230 break;
3048 case IEEE80211_AMPDU_TX_START: 4231 case IEEE80211_AMPDU_TX_START:
3049 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); 4232 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
@@ -3061,6 +4244,37 @@ int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3061} 4244}
3062EXPORT_SYMBOL_GPL(rt2800_ampdu_action); 4245EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
3063 4246
4247int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
4248 struct survey_info *survey)
4249{
4250 struct rt2x00_dev *rt2x00dev = hw->priv;
4251 struct ieee80211_conf *conf = &hw->conf;
4252 u32 idle, busy, busy_ext;
4253
4254 if (idx != 0)
4255 return -ENOENT;
4256
4257 survey->channel = conf->channel;
4258
4259 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
4260 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
4261 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
4262
4263 if (idle || busy) {
4264 survey->filled = SURVEY_INFO_CHANNEL_TIME |
4265 SURVEY_INFO_CHANNEL_TIME_BUSY |
4266 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
4267
4268 survey->channel_time = (idle + busy) / 1000;
4269 survey->channel_time_busy = busy / 1000;
4270 survey->channel_time_ext_busy = busy_ext / 1000;
4271 }
4272
4273 return 0;
4274
4275}
4276EXPORT_SYMBOL_GPL(rt2800_get_survey);
4277
3064MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz"); 4278MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
3065MODULE_VERSION(DRV_VERSION); 4279MODULE_VERSION(DRV_VERSION);
3066MODULE_DESCRIPTION("Ralink RT2800 library"); 4280MODULE_DESCRIPTION("Ralink RT2800 library");
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.h b/drivers/net/wireless/rt2x00/rt2800lib.h
index 091641e3c5e2..f2d15941c71a 100644
--- a/drivers/net/wireless/rt2x00/rt2800lib.h
+++ b/drivers/net/wireless/rt2x00/rt2800lib.h
@@ -1,4 +1,6 @@
1/* 1/*
2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
2 Copyright (C) 2009 Bartlomiej Zolnierkiewicz 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz
3 5
4 This program is free software; you can redistribute it and/or modify 6 This program is free software; you can redistribute it and/or modify
@@ -44,6 +46,7 @@ struct rt2800_ops {
44 int (*drv_write_firmware)(struct rt2x00_dev *rt2x00dev, 46 int (*drv_write_firmware)(struct rt2x00_dev *rt2x00dev,
45 const u8 *data, const size_t len); 47 const u8 *data, const size_t len);
46 int (*drv_init_registers)(struct rt2x00_dev *rt2x00dev); 48 int (*drv_init_registers)(struct rt2x00_dev *rt2x00dev);
49 __le32 *(*drv_get_txwi)(struct queue_entry *entry);
47}; 50};
48 51
49static inline void rt2800_register_read(struct rt2x00_dev *rt2x00dev, 52static inline void rt2800_register_read(struct rt2x00_dev *rt2x00dev,
@@ -126,19 +129,34 @@ static inline int rt2800_drv_init_registers(struct rt2x00_dev *rt2x00dev)
126 return rt2800ops->drv_init_registers(rt2x00dev); 129 return rt2800ops->drv_init_registers(rt2x00dev);
127} 130}
128 131
132static inline __le32 *rt2800_drv_get_txwi(struct queue_entry *entry)
133{
134 const struct rt2800_ops *rt2800ops = entry->queue->rt2x00dev->ops->drv;
135
136 return rt2800ops->drv_get_txwi(entry);
137}
138
129void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev, 139void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
130 const u8 command, const u8 token, 140 const u8 command, const u8 token,
131 const u8 arg0, const u8 arg1); 141 const u8 arg0, const u8 arg1);
132 142
143int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev);
144int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev);
145
133int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev, 146int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
134 const u8 *data, const size_t len); 147 const u8 *data, const size_t len);
135int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev, 148int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
136 const u8 *data, const size_t len); 149 const u8 *data, const size_t len);
137 150
138void rt2800_write_txwi(__le32 *txwi, struct txentry_desc *txdesc); 151void rt2800_write_tx_data(struct queue_entry *entry,
152 struct txentry_desc *txdesc);
139void rt2800_process_rxwi(struct queue_entry *entry, struct rxdone_entry_desc *txdesc); 153void rt2800_process_rxwi(struct queue_entry *entry, struct rxdone_entry_desc *txdesc);
140 154
155void rt2800_txdone(struct rt2x00_dev *rt2x00dev);
156void rt2800_txdone_entry(struct queue_entry *entry, u32 status);
157
141void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc); 158void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc);
159void rt2800_clear_beacon(struct queue_entry *entry);
142 160
143extern const struct rt2x00debug rt2800_rt2x00debug; 161extern const struct rt2x00debug rt2800_rt2x00debug;
144 162
@@ -153,7 +171,8 @@ void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
153 const unsigned int filter_flags); 171 const unsigned int filter_flags);
154void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, 172void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
155 struct rt2x00intf_conf *conf, const unsigned int flags); 173 struct rt2x00intf_conf *conf, const unsigned int flags);
156void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp); 174void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
175 u32 changed);
157void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant); 176void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant);
158void rt2800_config(struct rt2x00_dev *rt2x00dev, 177void rt2800_config(struct rt2x00_dev *rt2x00dev,
159 struct rt2x00lib_conf *libconf, 178 struct rt2x00lib_conf *libconf,
@@ -162,11 +181,10 @@ void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual);
162void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual); 181void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual);
163void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual, 182void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
164 const u32 count); 183 const u32 count);
184void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev);
165 185
166int rt2800_init_registers(struct rt2x00_dev *rt2x00dev); 186int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev);
167int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev); 187void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev);
168int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev);
169int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev);
170 188
171int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev); 189int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev);
172void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev); 190void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev);
@@ -182,6 +200,9 @@ int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
182u64 rt2800_get_tsf(struct ieee80211_hw *hw); 200u64 rt2800_get_tsf(struct ieee80211_hw *hw);
183int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 201int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
184 enum ieee80211_ampdu_mlme_action action, 202 enum ieee80211_ampdu_mlme_action action,
185 struct ieee80211_sta *sta, u16 tid, u16 *ssn); 203 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
204 u8 buf_size);
205int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
206 struct survey_info *survey);
186 207
187#endif /* RT2800LIB_H */ 208#endif /* RT2800LIB_H */
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c
index 39b3846fa340..cc4a54f571b8 100644
--- a/drivers/net/wireless/rt2x00/rt2800pci.c
+++ b/drivers/net/wireless/rt2x00/rt2800pci.c
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com> 2 Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> 3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> 4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> 5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
@@ -66,7 +66,7 @@ static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
66 return; 66 return;
67 67
68 for (i = 0; i < 200; i++) { 68 for (i = 0; i < 200; i++) {
69 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg); 69 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
70 70
71 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) || 71 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
72 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) || 72 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
@@ -80,30 +80,32 @@ static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
80 if (i == 200) 80 if (i == 200)
81 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n"); 81 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
82 82
83 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0); 83 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
84 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0); 84 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
85} 85}
86 86
87#ifdef CONFIG_RT2800PCI_SOC 87#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
88static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev) 88static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
89{ 89{
90 u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */ 90 void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
91 91
92 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE); 92 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
93
94 iounmap(base_addr);
93} 95}
94#else 96#else
95static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev) 97static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
96{ 98{
97} 99}
98#endif /* CONFIG_RT2800PCI_SOC */ 100#endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
99 101
100#ifdef CONFIG_RT2800PCI_PCI 102#ifdef CONFIG_PCI
101static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom) 103static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
102{ 104{
103 struct rt2x00_dev *rt2x00dev = eeprom->data; 105 struct rt2x00_dev *rt2x00dev = eeprom->data;
104 u32 reg; 106 u32 reg;
105 107
106 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg); 108 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
107 109
108 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN); 110 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
109 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT); 111 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
@@ -125,7 +127,7 @@ static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
125 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT, 127 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
126 !!eeprom->reg_chip_select); 128 !!eeprom->reg_chip_select);
127 129
128 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg); 130 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
129} 131}
130 132
131static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev) 133static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
@@ -133,7 +135,7 @@ static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
133 struct eeprom_93cx6 eeprom; 135 struct eeprom_93cx6 eeprom;
134 u32 reg; 136 u32 reg;
135 137
136 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg); 138 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
137 139
138 eeprom.data = rt2x00dev; 140 eeprom.data = rt2x00dev;
139 eeprom.register_read = rt2800pci_eepromregister_read; 141 eeprom.register_read = rt2800pci_eepromregister_read;
@@ -181,7 +183,101 @@ static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
181static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev) 183static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
182{ 184{
183} 185}
184#endif /* CONFIG_RT2800PCI_PCI */ 186#endif /* CONFIG_PCI */
187
188/*
189 * Queue handlers.
190 */
191static void rt2800pci_start_queue(struct data_queue *queue)
192{
193 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
194 u32 reg;
195
196 switch (queue->qid) {
197 case QID_RX:
198 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
199 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
200 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
201 break;
202 case QID_BEACON:
203 /*
204 * Allow beacon tasklets to be scheduled for periodic
205 * beacon updates.
206 */
207 tasklet_enable(&rt2x00dev->tbtt_tasklet);
208 tasklet_enable(&rt2x00dev->pretbtt_tasklet);
209
210 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
211 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
212 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
213 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
214 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
215
216 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, &reg);
217 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
218 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
219 break;
220 default:
221 break;
222 };
223}
224
225static void rt2800pci_kick_queue(struct data_queue *queue)
226{
227 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
228 struct queue_entry *entry;
229
230 switch (queue->qid) {
231 case QID_AC_VO:
232 case QID_AC_VI:
233 case QID_AC_BE:
234 case QID_AC_BK:
235 entry = rt2x00queue_get_entry(queue, Q_INDEX);
236 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(queue->qid),
237 entry->entry_idx);
238 break;
239 case QID_MGMT:
240 entry = rt2x00queue_get_entry(queue, Q_INDEX);
241 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(5),
242 entry->entry_idx);
243 break;
244 default:
245 break;
246 }
247}
248
249static void rt2800pci_stop_queue(struct data_queue *queue)
250{
251 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
252 u32 reg;
253
254 switch (queue->qid) {
255 case QID_RX:
256 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
257 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
258 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
259 break;
260 case QID_BEACON:
261 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
262 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
263 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
264 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
265 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
266
267 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, &reg);
268 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
269 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
270
271 /*
272 * Wait for tbtt tasklets to finish.
273 */
274 tasklet_disable(&rt2x00dev->tbtt_tasklet);
275 tasklet_disable(&rt2x00dev->pretbtt_tasklet);
276 break;
277 default:
278 break;
279 }
280}
185 281
186/* 282/*
187 * Firmware functions 283 * Firmware functions
@@ -196,26 +292,24 @@ static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
196{ 292{
197 u32 reg; 293 u32 reg;
198 294
199 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
200
201 /* 295 /*
202 * enable Host program ram write selection 296 * enable Host program ram write selection
203 */ 297 */
204 reg = 0; 298 reg = 0;
205 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1); 299 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
206 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg); 300 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
207 301
208 /* 302 /*
209 * Write firmware to device. 303 * Write firmware to device.
210 */ 304 */
211 rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, 305 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
212 data, len); 306 data, len);
213 307
214 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000); 308 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
215 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001); 309 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
216 310
217 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 311 rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
218 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 312 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
219 313
220 return 0; 314 return 0;
221} 315}
@@ -243,6 +337,7 @@ static void rt2800pci_clear_entry(struct queue_entry *entry)
243{ 337{
244 struct queue_entry_priv_pci *entry_priv = entry->priv_data; 338 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
245 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 339 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
340 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
246 u32 word; 341 u32 word;
247 342
248 if (entry->queue->qid == QID_RX) { 343 if (entry->queue->qid == QID_RX) {
@@ -253,6 +348,13 @@ static void rt2800pci_clear_entry(struct queue_entry *entry)
253 rt2x00_desc_read(entry_priv->desc, 1, &word); 348 rt2x00_desc_read(entry_priv->desc, 1, &word);
254 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0); 349 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
255 rt2x00_desc_write(entry_priv->desc, 1, word); 350 rt2x00_desc_write(entry_priv->desc, 1, word);
351
352 /*
353 * Set RX IDX in register to inform hardware that we have
354 * handled this entry and it is available for reuse again.
355 */
356 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
357 entry->entry_idx);
256 } else { 358 } else {
257 rt2x00_desc_read(entry_priv->desc, 1, &word); 359 rt2x00_desc_read(entry_priv->desc, 1, &word);
258 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1); 360 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
@@ -269,45 +371,51 @@ static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
269 * Initialize registers. 371 * Initialize registers.
270 */ 372 */
271 entry_priv = rt2x00dev->tx[0].entries[0].priv_data; 373 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
272 rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma); 374 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
273 rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit); 375 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0,
274 rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0); 376 rt2x00dev->tx[0].limit);
275 rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0); 377 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
378 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
276 379
277 entry_priv = rt2x00dev->tx[1].entries[0].priv_data; 380 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
278 rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma); 381 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
279 rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit); 382 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1,
280 rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0); 383 rt2x00dev->tx[1].limit);
281 rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0); 384 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
385 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
282 386
283 entry_priv = rt2x00dev->tx[2].entries[0].priv_data; 387 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
284 rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma); 388 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
285 rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit); 389 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2,
286 rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0); 390 rt2x00dev->tx[2].limit);
287 rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0); 391 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
392 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
288 393
289 entry_priv = rt2x00dev->tx[3].entries[0].priv_data; 394 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
290 rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma); 395 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
291 rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit); 396 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3,
292 rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0); 397 rt2x00dev->tx[3].limit);
293 rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0); 398 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
399 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
294 400
295 entry_priv = rt2x00dev->rx->entries[0].priv_data; 401 entry_priv = rt2x00dev->rx->entries[0].priv_data;
296 rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma); 402 rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
297 rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit); 403 rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT,
298 rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1); 404 rt2x00dev->rx[0].limit);
299 rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0); 405 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
406 rt2x00dev->rx[0].limit - 1);
407 rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
300 408
301 /* 409 /*
302 * Enable global DMA configuration 410 * Enable global DMA configuration
303 */ 411 */
304 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 412 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
305 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 413 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
306 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 414 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
307 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 415 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
308 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 416 rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
309 417
310 rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0); 418 rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
311 419
312 return 0; 420 return 0;
313} 421}
@@ -315,54 +423,62 @@ static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
315/* 423/*
316 * Device state switch handlers. 424 * Device state switch handlers.
317 */ 425 */
318static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
319 enum dev_state state)
320{
321 u32 reg;
322
323 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
324 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
325 (state == STATE_RADIO_RX_ON) ||
326 (state == STATE_RADIO_RX_ON_LINK));
327 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
328}
329
330static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev, 426static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
331 enum dev_state state) 427 enum dev_state state)
332{ 428{
333 int mask = (state == STATE_RADIO_IRQ_ON) || 429 int mask = (state == STATE_RADIO_IRQ_ON);
334 (state == STATE_RADIO_IRQ_ON_ISR);
335 u32 reg; 430 u32 reg;
431 unsigned long flags;
336 432
337 /* 433 /*
338 * When interrupts are being enabled, the interrupt registers 434 * When interrupts are being enabled, the interrupt registers
339 * should clear the register to assure a clean state. 435 * should clear the register to assure a clean state.
340 */ 436 */
341 if (state == STATE_RADIO_IRQ_ON) { 437 if (state == STATE_RADIO_IRQ_ON) {
342 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg); 438 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
343 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg); 439 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
440
441 /*
442 * Enable tasklets. The beacon related tasklets are
443 * enabled when the beacon queue is started.
444 */
445 tasklet_enable(&rt2x00dev->txstatus_tasklet);
446 tasklet_enable(&rt2x00dev->rxdone_tasklet);
447 tasklet_enable(&rt2x00dev->autowake_tasklet);
344 } 448 }
345 449
346 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg); 450 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
347 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask); 451 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
348 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask); 452 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, 0);
453 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, 0);
349 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask); 454 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
350 rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask); 455 rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, 0);
351 rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask); 456 rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, 0);
352 rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask); 457 rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, 0);
353 rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask); 458 rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, 0);
354 rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask); 459 rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, 0);
355 rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask); 460 rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, 0);
356 rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask); 461 rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, 0);
357 rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask); 462 rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, 0);
358 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask); 463 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
359 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask); 464 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
360 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask); 465 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
361 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask); 466 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
362 rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask); 467 rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, 0);
363 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask); 468 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, 0);
364 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask); 469 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, 0);
365 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg); 470 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
471 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
472
473 if (state == STATE_RADIO_IRQ_OFF) {
474 /*
475 * Ensure that all tasklets are finished before
476 * disabling the interrupts.
477 */
478 tasklet_disable(&rt2x00dev->txstatus_tasklet);
479 tasklet_disable(&rt2x00dev->rxdone_tasklet);
480 tasklet_disable(&rt2x00dev->autowake_tasklet);
481 }
366} 482}
367 483
368static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev) 484static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
@@ -372,7 +488,7 @@ static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
372 /* 488 /*
373 * Reset DMA indexes 489 * Reset DMA indexes
374 */ 490 */
375 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg); 491 rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
376 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1); 492 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
377 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1); 493 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
378 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1); 494 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
@@ -380,130 +496,60 @@ static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
380 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1); 496 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
381 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1); 497 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
382 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1); 498 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
383 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg); 499 rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
384 500
385 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f); 501 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
386 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00); 502 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
387 503
388 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 504 if (rt2x00_rt(rt2x00dev, RT5390)) {
505 rt2x00pci_register_read(rt2x00dev, AUX_CTRL, &reg);
506 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
507 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
508 rt2x00pci_register_write(rt2x00dev, AUX_CTRL, reg);
509 }
389 510
390 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 511 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
512
513 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
391 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1); 514 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
392 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1); 515 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
393 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 516 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
394 517
395 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); 518 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
396 519
397 return 0; 520 return 0;
398} 521}
399 522
400static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev) 523static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
401{ 524{
402 u32 reg;
403 u16 word;
404
405 /*
406 * Initialize all registers.
407 */
408 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) || 525 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
409 rt2800pci_init_queues(rt2x00dev) || 526 rt2800pci_init_queues(rt2x00dev)))
410 rt2800_init_registers(rt2x00dev) ||
411 rt2800_wait_wpdma_ready(rt2x00dev) ||
412 rt2800_init_bbp(rt2x00dev) ||
413 rt2800_init_rfcsr(rt2x00dev)))
414 return -EIO; 527 return -EIO;
415 528
416 /* 529 return rt2800_enable_radio(rt2x00dev);
417 * Send signal to firmware during boot time.
418 */
419 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
420
421 /*
422 * Enable RX.
423 */
424 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
425 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
426 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
427 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
428
429 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
430 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
431 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
432 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
433 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
434 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
435
436 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
437 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
438 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
439 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
440
441 /*
442 * Initialize LED control
443 */
444 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
445 rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
446 word & 0xff, (word >> 8) & 0xff);
447
448 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
449 rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
450 word & 0xff, (word >> 8) & 0xff);
451
452 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
453 rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
454 word & 0xff, (word >> 8) & 0xff);
455
456 return 0;
457} 530}
458 531
459static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev) 532static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
460{ 533{
461 u32 reg; 534 if (rt2x00_is_soc(rt2x00dev)) {
462 535 rt2800_disable_radio(rt2x00dev);
463 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 536 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
464 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 537 rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
465 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 538 }
466 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
467 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
468 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
469 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
470
471 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
472 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
473 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
474
475 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
476
477 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
478 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
479 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
480 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
481 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
482 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
483 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
484 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
485 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
486
487 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
488 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
489
490 /* Wait for DMA, ignore error */
491 rt2800_wait_wpdma_ready(rt2x00dev);
492} 539}
493 540
494static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev, 541static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
495 enum dev_state state) 542 enum dev_state state)
496{ 543{
497 /*
498 * Always put the device to sleep (even when we intend to wakeup!)
499 * if the device is booting and wasn't asleep it will return
500 * failure when attempting to wakeup.
501 */
502 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
503
504 if (state == STATE_AWAKE) { 544 if (state == STATE_AWAKE) {
505 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0); 545 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0x02);
506 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP); 546 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
547 } else if (state == STATE_SLEEP) {
548 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
549 0xffffffff);
550 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID,
551 0xffffffff);
552 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0x01, 0xff, 0x01);
507 } 553 }
508 554
509 return 0; 555 return 0;
@@ -533,16 +579,8 @@ static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
533 rt2800pci_disable_radio(rt2x00dev); 579 rt2800pci_disable_radio(rt2x00dev);
534 rt2800pci_set_state(rt2x00dev, STATE_SLEEP); 580 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
535 break; 581 break;
536 case STATE_RADIO_RX_ON:
537 case STATE_RADIO_RX_ON_LINK:
538 case STATE_RADIO_RX_OFF:
539 case STATE_RADIO_RX_OFF_LINK:
540 rt2800pci_toggle_rx(rt2x00dev, state);
541 break;
542 case STATE_RADIO_IRQ_ON: 582 case STATE_RADIO_IRQ_ON:
543 case STATE_RADIO_IRQ_ON_ISR:
544 case STATE_RADIO_IRQ_OFF: 583 case STATE_RADIO_IRQ_OFF:
545 case STATE_RADIO_IRQ_OFF_ISR:
546 rt2800pci_toggle_irq(rt2x00dev, state); 584 rt2800pci_toggle_irq(rt2x00dev, state);
547 break; 585 break;
548 case STATE_DEEP_SLEEP: 586 case STATE_DEEP_SLEEP:
@@ -566,21 +604,16 @@ static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
566/* 604/*
567 * TX descriptor initialization 605 * TX descriptor initialization
568 */ 606 */
569static void rt2800pci_write_tx_data(struct queue_entry* entry, 607static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
570 struct txentry_desc *txdesc)
571{ 608{
572 __le32 *txwi = (__le32 *) entry->skb->data; 609 return (__le32 *) entry->skb->data;
573
574 rt2800_write_txwi(txwi, txdesc);
575} 610}
576 611
577 612static void rt2800pci_write_tx_desc(struct queue_entry *entry,
578static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
579 struct sk_buff *skb,
580 struct txentry_desc *txdesc) 613 struct txentry_desc *txdesc)
581{ 614{
582 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 615 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
583 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data; 616 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
584 __le32 *txd = entry_priv->desc; 617 __le32 *txd = entry_priv->desc;
585 u32 word; 618 u32 word;
586 619
@@ -600,7 +633,7 @@ static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
600 rt2x00_desc_write(txd, 0, word); 633 rt2x00_desc_write(txd, 0, word);
601 634
602 rt2x00_desc_read(txd, 1, &word); 635 rt2x00_desc_read(txd, 1, &word);
603 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len); 636 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
604 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1, 637 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
605 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); 638 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
606 rt2x00_set_field32(&word, TXD_W1_BURST, 639 rt2x00_set_field32(&word, TXD_W1_BURST,
@@ -629,53 +662,11 @@ static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
629} 662}
630 663
631/* 664/*
632 * TX data initialization
633 */
634static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
635 const enum data_queue_qid queue_idx)
636{
637 struct data_queue *queue;
638 unsigned int idx, qidx = 0;
639
640 if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
641 return;
642
643 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
644 idx = queue->index[Q_INDEX];
645
646 if (queue_idx == QID_MGMT)
647 qidx = 5;
648 else
649 qidx = queue_idx;
650
651 rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
652}
653
654static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
655 const enum data_queue_qid qid)
656{
657 u32 reg;
658
659 if (qid == QID_BEACON) {
660 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
661 return;
662 }
663
664 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
665 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
666 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
667 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
668 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
669 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
670}
671
672/*
673 * RX control handlers 665 * RX control handlers
674 */ 666 */
675static void rt2800pci_fill_rxdone(struct queue_entry *entry, 667static void rt2800pci_fill_rxdone(struct queue_entry *entry,
676 struct rxdone_entry_desc *rxdesc) 668 struct rxdone_entry_desc *rxdesc)
677{ 669{
678 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
679 struct queue_entry_priv_pci *entry_priv = entry->priv_data; 670 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
680 __le32 *rxd = entry_priv->desc; 671 __le32 *rxd = entry_priv->desc;
681 u32 word; 672 u32 word;
@@ -701,6 +692,12 @@ static void rt2800pci_fill_rxdone(struct queue_entry *entry,
701 */ 692 */
702 rxdesc->flags |= RX_FLAG_IV_STRIPPED; 693 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
703 694
695 /*
696 * The hardware has already checked the Michael Mic and has
697 * stripped it from the frame. Signal this to mac80211.
698 */
699 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
700
704 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS) 701 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
705 rxdesc->flags |= RX_FLAG_DECRYPTED; 702 rxdesc->flags |= RX_FLAG_DECRYPTED;
706 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC) 703 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
@@ -717,179 +714,177 @@ static void rt2800pci_fill_rxdone(struct queue_entry *entry,
717 * Process the RXWI structure that is at the start of the buffer. 714 * Process the RXWI structure that is at the start of the buffer.
718 */ 715 */
719 rt2800_process_rxwi(entry, rxdesc); 716 rt2800_process_rxwi(entry, rxdesc);
720
721 /*
722 * Set RX IDX in register to inform hardware that we have handled
723 * this entry and it is available for reuse again.
724 */
725 rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
726} 717}
727 718
728/* 719/*
729 * Interrupt functions. 720 * Interrupt functions.
730 */ 721 */
731static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev) 722static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
723{
724 struct ieee80211_conf conf = { .flags = 0 };
725 struct rt2x00lib_conf libconf = { .conf = &conf };
726
727 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
728}
729
730static bool rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
732{ 731{
733 struct data_queue *queue; 732 struct data_queue *queue;
734 struct queue_entry *entry; 733 struct queue_entry *entry;
735 __le32 *txwi; 734 u32 status;
736 struct txdone_entry_desc txdesc; 735 u8 qid;
737 u32 word; 736 int max_tx_done = 16;
738 u32 reg;
739 int wcid, ack, pid, tx_wcid, tx_ack, tx_pid;
740 u16 mcs, real_mcs;
741 int i;
742 737
743 /* 738 while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
744 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO 739 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
745 * at most X times and also stop processing once the TX_STA_FIFO_VALID 740 if (unlikely(qid >= QID_RX)) {
746 * flag is not set anymore. 741 /*
747 * 742 * Unknown queue, this shouldn't happen. Just drop
748 * The legacy drivers use X=TX_RING_SIZE but state in a comment 743 * this tx status.
749 * that the TX_STA_FIFO stack has a size of 16. We stick to our 744 */
750 * tx ring size for now. 745 WARNING(rt2x00dev, "Got TX status report with "
751 */ 746 "unexpected pid %u, dropping\n", qid);
752 for (i = 0; i < TX_ENTRIES; i++) {
753 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
754 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
755 break; 747 break;
748 }
756 749
757 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID); 750 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
758 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED); 751 if (unlikely(queue == NULL)) {
759 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
760
761 /*
762 * Skip this entry when it contains an invalid
763 * queue identication number.
764 */
765 if (pid <= 0 || pid > QID_RX)
766 continue;
767
768 queue = rt2x00queue_get_queue(rt2x00dev, pid - 1);
769 if (unlikely(!queue))
770 continue;
771
772 /*
773 * Inside each queue, we process each entry in a chronological
774 * order. We first check that the queue is not empty.
775 */
776 if (rt2x00queue_empty(queue))
777 continue;
778 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
779
780 /* Check if we got a match by looking at WCID/ACK/PID
781 * fields */
782 txwi = (__le32 *) entry->skb->data;
783
784 rt2x00_desc_read(txwi, 1, &word);
785 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
786 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK);
787 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID);
788
789 if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid))
790 WARNING(rt2x00dev, "invalid TX_STA_FIFO content\n");
791
792 /*
793 * Obtain the status about this packet.
794 */
795 txdesc.flags = 0;
796 rt2x00_desc_read(txwi, 0, &word);
797 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
798 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
799
800 /*
801 * Ralink has a retry mechanism using a global fallback
802 * table. We setup this fallback table to try the immediate
803 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
804 * always contains the MCS used for the last transmission, be
805 * it successful or not.
806 */
807 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS)) {
808 /* 752 /*
809 * Transmission succeeded. The number of retries is 753 * The queue is NULL, this shouldn't happen. Stop
810 * mcs - real_mcs 754 * processing here and drop the tx status
811 */ 755 */
812 __set_bit(TXDONE_SUCCESS, &txdesc.flags); 756 WARNING(rt2x00dev, "Got TX status for an unavailable "
813 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0); 757 "queue %u, dropping\n", qid);
814 } else { 758 break;
759 }
760
761 if (unlikely(rt2x00queue_empty(queue))) {
815 /* 762 /*
816 * Transmission failed. The number of retries is 763 * The queue is empty. Stop processing here
817 * always 7 in this case (for a total number of 8 764 * and drop the tx status.
818 * frames sent).
819 */ 765 */
820 __set_bit(TXDONE_FAILURE, &txdesc.flags); 766 WARNING(rt2x00dev, "Got TX status for an empty "
821 txdesc.retry = 7; 767 "queue %u, dropping\n", qid);
768 break;
822 } 769 }
823 770
824 /* 771 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
825 * the frame was retried at least once 772 rt2800_txdone_entry(entry, status);
826 * -> hw used fallback rates
827 */
828 if (txdesc.retry)
829 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
830 773
831 rt2x00lib_txdone(entry, &txdesc); 774 if (--max_tx_done == 0)
775 break;
832 } 776 }
777
778 return !max_tx_done;
833} 779}
834 780
835static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev) 781static inline void rt2800pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
782 struct rt2x00_field32 irq_field)
836{ 783{
837 struct ieee80211_conf conf = { .flags = 0 }; 784 u32 reg;
838 struct rt2x00lib_conf libconf = { .conf = &conf };
839 785
840 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS); 786 /*
787 * Enable a single interrupt. The interrupt mask register
788 * access needs locking.
789 */
790 spin_lock_irq(&rt2x00dev->irqmask_lock);
791 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
792 rt2x00_set_field32(&reg, irq_field, 1);
793 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
794 spin_unlock_irq(&rt2x00dev->irqmask_lock);
841} 795}
842 796
843static irqreturn_t rt2800pci_interrupt_thread(int irq, void *dev_instance) 797static void rt2800pci_txstatus_tasklet(unsigned long data)
844{ 798{
845 struct rt2x00_dev *rt2x00dev = dev_instance; 799 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
846 u32 reg = rt2x00dev->irqvalue[0]; 800 if (rt2800pci_txdone(rt2x00dev))
801 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
847 802
848 /* 803 /*
849 * 1 - Pre TBTT interrupt. 804 * No need to enable the tx status interrupt here as we always
805 * leave it enabled to minimize the possibility of a tx status
806 * register overflow. See comment in interrupt handler.
850 */ 807 */
851 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT)) 808}
852 rt2x00lib_pretbtt(rt2x00dev);
853 809
854 /* 810static void rt2800pci_pretbtt_tasklet(unsigned long data)
855 * 2 - Beacondone interrupt. 811{
856 */ 812 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
857 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT)) 813 rt2x00lib_pretbtt(rt2x00dev);
858 rt2x00lib_beacondone(rt2x00dev); 814 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_PRE_TBTT);
815}
859 816
860 /* 817static void rt2800pci_tbtt_tasklet(unsigned long data)
861 * 3 - Rx ring done interrupt. 818{
862 */ 819 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
863 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE)) 820 rt2x00lib_beacondone(rt2x00dev);
864 rt2x00pci_rxdone(rt2x00dev); 821 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TBTT);
822}
865 823
866 /* 824static void rt2800pci_rxdone_tasklet(unsigned long data)
867 * 4 - Tx done interrupt. 825{
868 */ 826 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
869 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) 827 if (rt2x00pci_rxdone(rt2x00dev))
870 rt2800pci_txdone(rt2x00dev); 828 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
829 else
830 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
831}
832
833static void rt2800pci_autowake_tasklet(unsigned long data)
834{
835 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
836 rt2800pci_wakeup(rt2x00dev);
837 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_AUTO_WAKEUP);
838}
839
840static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
841{
842 u32 status;
843 int i;
871 844
872 /* 845 /*
873 * 5 - Auto wakeup interrupt. 846 * The TX_FIFO_STATUS interrupt needs special care. We should
847 * read TX_STA_FIFO but we should do it immediately as otherwise
848 * the register can overflow and we would lose status reports.
849 *
850 * Hence, read the TX_STA_FIFO register and copy all tx status
851 * reports into a kernel FIFO which is handled in the txstatus
852 * tasklet. We use a tasklet to process the tx status reports
853 * because we can schedule the tasklet multiple times (when the
854 * interrupt fires again during tx status processing).
855 *
856 * Furthermore we don't disable the TX_FIFO_STATUS
857 * interrupt here but leave it enabled so that the TX_STA_FIFO
858 * can also be read while the tx status tasklet gets executed.
859 *
860 * Since we have only one producer and one consumer we don't
861 * need to lock the kfifo.
874 */ 862 */
875 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP)) 863 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
876 rt2800pci_wakeup(rt2x00dev); 864 rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &status);
877 865
878 /* Enable interrupts again. */ 866 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
879 rt2x00dev->ops->lib->set_device_state(rt2x00dev, 867 break;
880 STATE_RADIO_IRQ_ON_ISR);
881 868
882 return IRQ_HANDLED; 869 if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
870 WARNING(rt2x00dev, "TX status FIFO overrun,"
871 "drop tx status report.\n");
872 break;
873 }
874 }
875
876 /* Schedule the tasklet for processing the tx status. */
877 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
883} 878}
884 879
885static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance) 880static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
886{ 881{
887 struct rt2x00_dev *rt2x00dev = dev_instance; 882 struct rt2x00_dev *rt2x00dev = dev_instance;
888 u32 reg; 883 u32 reg, mask;
889 884
890 /* Read status and ACK all interrupts */ 885 /* Read status and ACK all interrupts */
891 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg); 886 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
892 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg); 887 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
893 888
894 if (!reg) 889 if (!reg)
895 return IRQ_NONE; 890 return IRQ_NONE;
@@ -897,15 +892,44 @@ static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
897 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 892 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
898 return IRQ_HANDLED; 893 return IRQ_HANDLED;
899 894
900 /* Store irqvalue for use in the interrupt thread. */ 895 /*
901 rt2x00dev->irqvalue[0] = reg; 896 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
897 * for interrupts and interrupt masks we can just use the value of
898 * INT_SOURCE_CSR to create the interrupt mask.
899 */
900 mask = ~reg;
902 901
903 /* Disable interrupts, will be enabled again in the interrupt thread. */ 902 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {
904 rt2x00dev->ops->lib->set_device_state(rt2x00dev, 903 rt2800pci_txstatus_interrupt(rt2x00dev);
905 STATE_RADIO_IRQ_OFF_ISR); 904 /*
905 * Never disable the TX_FIFO_STATUS interrupt.
906 */
907 rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
908 }
906 909
910 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
911 tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);
907 912
908 return IRQ_WAKE_THREAD; 913 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
914 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
915
916 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
917 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
918
919 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
920 tasklet_schedule(&rt2x00dev->autowake_tasklet);
921
922 /*
923 * Disable all interrupts for which a tasklet was scheduled right now,
924 * the tasklet will reenable the appropriate interrupts.
925 */
926 spin_lock(&rt2x00dev->irqmask_lock);
927 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
928 reg &= mask;
929 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
930 spin_unlock(&rt2x00dev->irqmask_lock);
931
932 return IRQ_HANDLED;
909} 933}
910 934
911/* 935/*
@@ -952,25 +976,28 @@ static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
952 * This device has multiple filters for control frames 976 * This device has multiple filters for control frames
953 * and has a separate filter for PS Poll frames. 977 * and has a separate filter for PS Poll frames.
954 */ 978 */
955 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags); 979 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
956 __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags); 980 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
957 981
958 /* 982 /*
959 * This device has a pre tbtt interrupt and thus fetches 983 * This device has a pre tbtt interrupt and thus fetches
960 * a new beacon directly prior to transmission. 984 * a new beacon directly prior to transmission.
961 */ 985 */
962 __set_bit(DRIVER_SUPPORT_PRE_TBTT_INTERRUPT, &rt2x00dev->flags); 986 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
963 987
964 /* 988 /*
965 * This device requires firmware. 989 * This device requires firmware.
966 */ 990 */
967 if (!rt2x00_is_soc(rt2x00dev)) 991 if (!rt2x00_is_soc(rt2x00dev))
968 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags); 992 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
969 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags); 993 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
970 __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags); 994 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
995 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
996 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
971 if (!modparam_nohwcrypt) 997 if (!modparam_nohwcrypt)
972 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags); 998 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
973 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags); 999 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
1000 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
974 1001
975 /* 1002 /*
976 * Set the rssi offset. 1003 * Set the rssi offset.
@@ -999,6 +1026,9 @@ static const struct ieee80211_ops rt2800pci_mac80211_ops = {
999 .get_tsf = rt2800_get_tsf, 1026 .get_tsf = rt2800_get_tsf,
1000 .rfkill_poll = rt2x00mac_rfkill_poll, 1027 .rfkill_poll = rt2x00mac_rfkill_poll,
1001 .ampdu_action = rt2800_ampdu_action, 1028 .ampdu_action = rt2800_ampdu_action,
1029 .flush = rt2x00mac_flush,
1030 .get_survey = rt2800_get_survey,
1031 .get_ringparam = rt2x00mac_get_ringparam,
1002}; 1032};
1003 1033
1004static const struct rt2800_ops rt2800pci_rt2800_ops = { 1034static const struct rt2800_ops rt2800pci_rt2800_ops = {
@@ -1011,11 +1041,16 @@ static const struct rt2800_ops rt2800pci_rt2800_ops = {
1011 .regbusy_read = rt2x00pci_regbusy_read, 1041 .regbusy_read = rt2x00pci_regbusy_read,
1012 .drv_write_firmware = rt2800pci_write_firmware, 1042 .drv_write_firmware = rt2800pci_write_firmware,
1013 .drv_init_registers = rt2800pci_init_registers, 1043 .drv_init_registers = rt2800pci_init_registers,
1044 .drv_get_txwi = rt2800pci_get_txwi,
1014}; 1045};
1015 1046
1016static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = { 1047static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1017 .irq_handler = rt2800pci_interrupt, 1048 .irq_handler = rt2800pci_interrupt,
1018 .irq_handler_thread = rt2800pci_interrupt_thread, 1049 .txstatus_tasklet = rt2800pci_txstatus_tasklet,
1050 .pretbtt_tasklet = rt2800pci_pretbtt_tasklet,
1051 .tbtt_tasklet = rt2800pci_tbtt_tasklet,
1052 .rxdone_tasklet = rt2800pci_rxdone_tasklet,
1053 .autowake_tasklet = rt2800pci_autowake_tasklet,
1019 .probe_hw = rt2800pci_probe_hw, 1054 .probe_hw = rt2800pci_probe_hw,
1020 .get_firmware_name = rt2800pci_get_firmware_name, 1055 .get_firmware_name = rt2800pci_get_firmware_name,
1021 .check_firmware = rt2800_check_firmware, 1056 .check_firmware = rt2800_check_firmware,
@@ -1029,11 +1064,15 @@ static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1029 .link_stats = rt2800_link_stats, 1064 .link_stats = rt2800_link_stats,
1030 .reset_tuner = rt2800_reset_tuner, 1065 .reset_tuner = rt2800_reset_tuner,
1031 .link_tuner = rt2800_link_tuner, 1066 .link_tuner = rt2800_link_tuner,
1067 .gain_calibration = rt2800_gain_calibration,
1068 .start_queue = rt2800pci_start_queue,
1069 .kick_queue = rt2800pci_kick_queue,
1070 .stop_queue = rt2800pci_stop_queue,
1071 .flush_queue = rt2x00pci_flush_queue,
1032 .write_tx_desc = rt2800pci_write_tx_desc, 1072 .write_tx_desc = rt2800pci_write_tx_desc,
1033 .write_tx_data = rt2800pci_write_tx_data, 1073 .write_tx_data = rt2800_write_tx_data,
1034 .write_beacon = rt2800_write_beacon, 1074 .write_beacon = rt2800_write_beacon,
1035 .kick_tx_queue = rt2800pci_kick_tx_queue, 1075 .clear_beacon = rt2800_clear_beacon,
1036 .kill_tx_queue = rt2800pci_kill_tx_queue,
1037 .fill_rxdone = rt2800pci_fill_rxdone, 1076 .fill_rxdone = rt2800pci_fill_rxdone,
1038 .config_shared_key = rt2800_config_shared_key, 1077 .config_shared_key = rt2800_config_shared_key,
1039 .config_pairwise_key = rt2800_config_pairwise_key, 1078 .config_pairwise_key = rt2800_config_pairwise_key,
@@ -1045,21 +1084,21 @@ static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1045}; 1084};
1046 1085
1047static const struct data_queue_desc rt2800pci_queue_rx = { 1086static const struct data_queue_desc rt2800pci_queue_rx = {
1048 .entry_num = RX_ENTRIES, 1087 .entry_num = 128,
1049 .data_size = AGGREGATION_SIZE, 1088 .data_size = AGGREGATION_SIZE,
1050 .desc_size = RXD_DESC_SIZE, 1089 .desc_size = RXD_DESC_SIZE,
1051 .priv_size = sizeof(struct queue_entry_priv_pci), 1090 .priv_size = sizeof(struct queue_entry_priv_pci),
1052}; 1091};
1053 1092
1054static const struct data_queue_desc rt2800pci_queue_tx = { 1093static const struct data_queue_desc rt2800pci_queue_tx = {
1055 .entry_num = TX_ENTRIES, 1094 .entry_num = 64,
1056 .data_size = AGGREGATION_SIZE, 1095 .data_size = AGGREGATION_SIZE,
1057 .desc_size = TXD_DESC_SIZE, 1096 .desc_size = TXD_DESC_SIZE,
1058 .priv_size = sizeof(struct queue_entry_priv_pci), 1097 .priv_size = sizeof(struct queue_entry_priv_pci),
1059}; 1098};
1060 1099
1061static const struct data_queue_desc rt2800pci_queue_bcn = { 1100static const struct data_queue_desc rt2800pci_queue_bcn = {
1062 .entry_num = 8 * BEACON_ENTRIES, 1101 .entry_num = 8,
1063 .data_size = 0, /* No DMA required for beacons */ 1102 .data_size = 0, /* No DMA required for beacons */
1064 .desc_size = TXWI_DESC_SIZE, 1103 .desc_size = TXWI_DESC_SIZE,
1065 .priv_size = sizeof(struct queue_entry_priv_pci), 1104 .priv_size = sizeof(struct queue_entry_priv_pci),
@@ -1087,48 +1126,54 @@ static const struct rt2x00_ops rt2800pci_ops = {
1087/* 1126/*
1088 * RT2800pci module information. 1127 * RT2800pci module information.
1089 */ 1128 */
1090#ifdef CONFIG_RT2800PCI_PCI 1129#ifdef CONFIG_PCI
1091static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = { 1130static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1092 { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1131 { PCI_DEVICE(0x1814, 0x0601) },
1093 { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1132 { PCI_DEVICE(0x1814, 0x0681) },
1094 { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1133 { PCI_DEVICE(0x1814, 0x0701) },
1095 { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1134 { PCI_DEVICE(0x1814, 0x0781) },
1096 { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1135 { PCI_DEVICE(0x1814, 0x3090) },
1097 { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1136 { PCI_DEVICE(0x1814, 0x3091) },
1098 { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1137 { PCI_DEVICE(0x1814, 0x3092) },
1099 { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1138 { PCI_DEVICE(0x1432, 0x7708) },
1100 { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1139 { PCI_DEVICE(0x1432, 0x7727) },
1101 { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1140 { PCI_DEVICE(0x1432, 0x7728) },
1102 { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1141 { PCI_DEVICE(0x1432, 0x7738) },
1103 { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1142 { PCI_DEVICE(0x1432, 0x7748) },
1104#ifdef CONFIG_RT2800PCI_RT30XX 1143 { PCI_DEVICE(0x1432, 0x7758) },
1105 { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1144 { PCI_DEVICE(0x1432, 0x7768) },
1106 { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1145 { PCI_DEVICE(0x1462, 0x891a) },
1107 { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1146 { PCI_DEVICE(0x1a3b, 0x1059) },
1108 { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1147#ifdef CONFIG_RT2800PCI_RT33XX
1148 { PCI_DEVICE(0x1814, 0x3390) },
1109#endif 1149#endif
1110#ifdef CONFIG_RT2800PCI_RT35XX 1150#ifdef CONFIG_RT2800PCI_RT35XX
1111 { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1151 { PCI_DEVICE(0x1432, 0x7711) },
1112 { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1152 { PCI_DEVICE(0x1432, 0x7722) },
1113 { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1153 { PCI_DEVICE(0x1814, 0x3060) },
1114 { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1154 { PCI_DEVICE(0x1814, 0x3062) },
1115 { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1155 { PCI_DEVICE(0x1814, 0x3562) },
1156 { PCI_DEVICE(0x1814, 0x3592) },
1157 { PCI_DEVICE(0x1814, 0x3593) },
1158#endif
1159#ifdef CONFIG_RT2800PCI_RT53XX
1160 { PCI_DEVICE(0x1814, 0x5390) },
1116#endif 1161#endif
1117 { 0, } 1162 { 0, }
1118}; 1163};
1119#endif /* CONFIG_RT2800PCI_PCI */ 1164#endif /* CONFIG_PCI */
1120 1165
1121MODULE_AUTHOR(DRV_PROJECT); 1166MODULE_AUTHOR(DRV_PROJECT);
1122MODULE_VERSION(DRV_VERSION); 1167MODULE_VERSION(DRV_VERSION);
1123MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver."); 1168MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1124MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards"); 1169MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1125#ifdef CONFIG_RT2800PCI_PCI 1170#ifdef CONFIG_PCI
1126MODULE_FIRMWARE(FIRMWARE_RT2860); 1171MODULE_FIRMWARE(FIRMWARE_RT2860);
1127MODULE_DEVICE_TABLE(pci, rt2800pci_device_table); 1172MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1128#endif /* CONFIG_RT2800PCI_PCI */ 1173#endif /* CONFIG_PCI */
1129MODULE_LICENSE("GPL"); 1174MODULE_LICENSE("GPL");
1130 1175
1131#ifdef CONFIG_RT2800PCI_SOC 1176#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1132static int rt2800soc_probe(struct platform_device *pdev) 1177static int rt2800soc_probe(struct platform_device *pdev)
1133{ 1178{
1134 return rt2x00soc_probe(pdev, &rt2800pci_ops); 1179 return rt2x00soc_probe(pdev, &rt2800pci_ops);
@@ -1145,32 +1190,38 @@ static struct platform_driver rt2800soc_driver = {
1145 .suspend = rt2x00soc_suspend, 1190 .suspend = rt2x00soc_suspend,
1146 .resume = rt2x00soc_resume, 1191 .resume = rt2x00soc_resume,
1147}; 1192};
1148#endif /* CONFIG_RT2800PCI_SOC */ 1193#endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
1194
1195#ifdef CONFIG_PCI
1196static int rt2800pci_probe(struct pci_dev *pci_dev,
1197 const struct pci_device_id *id)
1198{
1199 return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
1200}
1149 1201
1150#ifdef CONFIG_RT2800PCI_PCI
1151static struct pci_driver rt2800pci_driver = { 1202static struct pci_driver rt2800pci_driver = {
1152 .name = KBUILD_MODNAME, 1203 .name = KBUILD_MODNAME,
1153 .id_table = rt2800pci_device_table, 1204 .id_table = rt2800pci_device_table,
1154 .probe = rt2x00pci_probe, 1205 .probe = rt2800pci_probe,
1155 .remove = __devexit_p(rt2x00pci_remove), 1206 .remove = __devexit_p(rt2x00pci_remove),
1156 .suspend = rt2x00pci_suspend, 1207 .suspend = rt2x00pci_suspend,
1157 .resume = rt2x00pci_resume, 1208 .resume = rt2x00pci_resume,
1158}; 1209};
1159#endif /* CONFIG_RT2800PCI_PCI */ 1210#endif /* CONFIG_PCI */
1160 1211
1161static int __init rt2800pci_init(void) 1212static int __init rt2800pci_init(void)
1162{ 1213{
1163 int ret = 0; 1214 int ret = 0;
1164 1215
1165#ifdef CONFIG_RT2800PCI_SOC 1216#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1166 ret = platform_driver_register(&rt2800soc_driver); 1217 ret = platform_driver_register(&rt2800soc_driver);
1167 if (ret) 1218 if (ret)
1168 return ret; 1219 return ret;
1169#endif 1220#endif
1170#ifdef CONFIG_RT2800PCI_PCI 1221#ifdef CONFIG_PCI
1171 ret = pci_register_driver(&rt2800pci_driver); 1222 ret = pci_register_driver(&rt2800pci_driver);
1172 if (ret) { 1223 if (ret) {
1173#ifdef CONFIG_RT2800PCI_SOC 1224#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1174 platform_driver_unregister(&rt2800soc_driver); 1225 platform_driver_unregister(&rt2800soc_driver);
1175#endif 1226#endif
1176 return ret; 1227 return ret;
@@ -1182,10 +1233,10 @@ static int __init rt2800pci_init(void)
1182 1233
1183static void __exit rt2800pci_exit(void) 1234static void __exit rt2800pci_exit(void)
1184{ 1235{
1185#ifdef CONFIG_RT2800PCI_PCI 1236#ifdef CONFIG_PCI
1186 pci_unregister_driver(&rt2800pci_driver); 1237 pci_unregister_driver(&rt2800pci_driver);
1187#endif 1238#endif
1188#ifdef CONFIG_RT2800PCI_SOC 1239#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1189 platform_driver_unregister(&rt2800soc_driver); 1240 platform_driver_unregister(&rt2800soc_driver);
1190#endif 1241#endif
1191} 1242}
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.h b/drivers/net/wireless/rt2x00/rt2800pci.h
index 5a8dda9b5b5a..70e050d904c8 100644
--- a/drivers/net/wireless/rt2x00/rt2800pci.h
+++ b/drivers/net/wireless/rt2x00/rt2800pci.h
@@ -38,10 +38,10 @@
38 * Queue register offset macros 38 * Queue register offset macros
39 */ 39 */
40#define TX_QUEUE_REG_OFFSET 0x10 40#define TX_QUEUE_REG_OFFSET 0x10
41#define TX_BASE_PTR(__x) TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET) 41#define TX_BASE_PTR(__x) (TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET))
42#define TX_MAX_CNT(__x) TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET) 42#define TX_MAX_CNT(__x) (TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET))
43#define TX_CTX_IDX(__x) TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET) 43#define TX_CTX_IDX(__x) (TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET))
44#define TX_DTX_IDX(__x) TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET) 44#define TX_DTX_IDX(__x) (TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET))
45 45
46/* 46/*
47 * 8051 firmware image. 47 * 8051 firmware image.
@@ -52,8 +52,8 @@
52/* 52/*
53 * DMA descriptor defines. 53 * DMA descriptor defines.
54 */ 54 */
55#define TXD_DESC_SIZE ( 4 * sizeof(__le32) ) 55#define TXD_DESC_SIZE (4 * sizeof(__le32))
56#define RXD_DESC_SIZE ( 4 * sizeof(__le32) ) 56#define RXD_DESC_SIZE (4 * sizeof(__le32))
57 57
58/* 58/*
59 * TX descriptor format for TX, PRIO and Beacon Ring. 59 * TX descriptor format for TX, PRIO and Beacon Ring.
diff --git a/drivers/net/wireless/rt2x00/rt2800usb.c b/drivers/net/wireless/rt2x00/rt2800usb.c
index 5a2dfe87c6b6..ba82c972703a 100644
--- a/drivers/net/wireless/rt2x00/rt2800usb.c
+++ b/drivers/net/wireless/rt2x00/rt2800usb.c
@@ -1,5 +1,6 @@
1/* 1/*
2 Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com> 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> 4 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> 5 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> 6 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
@@ -44,11 +45,117 @@
44/* 45/*
45 * Allow hardware encryption to be disabled. 46 * Allow hardware encryption to be disabled.
46 */ 47 */
47static int modparam_nohwcrypt = 0; 48static int modparam_nohwcrypt;
48module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO); 49module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
49MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 50MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
50 51
51/* 52/*
53 * Queue handlers.
54 */
55static void rt2800usb_start_queue(struct data_queue *queue)
56{
57 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
58 u32 reg;
59
60 switch (queue->qid) {
61 case QID_RX:
62 rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
63 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
64 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
65 break;
66 case QID_BEACON:
67 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
68 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
69 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
70 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
71 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
72 break;
73 default:
74 break;
75 }
76}
77
78static void rt2800usb_stop_queue(struct data_queue *queue)
79{
80 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
81 u32 reg;
82
83 switch (queue->qid) {
84 case QID_RX:
85 rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
86 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
87 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
88 break;
89 case QID_BEACON:
90 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
91 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
92 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
93 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
94 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
95 break;
96 default:
97 break;
98 }
99}
100
101/*
102 * test if there is an entry in any TX queue for which DMA is done
103 * but the TX status has not been returned yet
104 */
105static bool rt2800usb_txstatus_pending(struct rt2x00_dev *rt2x00dev)
106{
107 struct data_queue *queue;
108
109 tx_queue_for_each(rt2x00dev, queue) {
110 if (rt2x00queue_get_entry(queue, Q_INDEX_DMA_DONE) !=
111 rt2x00queue_get_entry(queue, Q_INDEX_DONE))
112 return true;
113 }
114 return false;
115}
116
117static bool rt2800usb_tx_sta_fifo_read_completed(struct rt2x00_dev *rt2x00dev,
118 int urb_status, u32 tx_status)
119{
120 if (urb_status) {
121 WARNING(rt2x00dev, "rt2x00usb_register_read_async failed: %d\n", urb_status);
122 return false;
123 }
124
125 /* try to read all TX_STA_FIFO entries before scheduling txdone_work */
126 if (rt2x00_get_field32(tx_status, TX_STA_FIFO_VALID)) {
127 if (!kfifo_put(&rt2x00dev->txstatus_fifo, &tx_status)) {
128 WARNING(rt2x00dev, "TX status FIFO overrun, "
129 "drop tx status report.\n");
130 queue_work(rt2x00dev->workqueue, &rt2x00dev->txdone_work);
131 } else
132 return true;
133 } else if (!kfifo_is_empty(&rt2x00dev->txstatus_fifo)) {
134 queue_work(rt2x00dev->workqueue, &rt2x00dev->txdone_work);
135 } else if (rt2800usb_txstatus_pending(rt2x00dev)) {
136 mod_timer(&rt2x00dev->txstatus_timer, jiffies + msecs_to_jiffies(2));
137 }
138
139 return false;
140}
141
142static void rt2800usb_tx_dma_done(struct queue_entry *entry)
143{
144 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
145
146 rt2x00usb_register_read_async(rt2x00dev, TX_STA_FIFO,
147 rt2800usb_tx_sta_fifo_read_completed);
148}
149
150static void rt2800usb_tx_sta_fifo_timeout(unsigned long data)
151{
152 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
153
154 rt2x00usb_register_read_async(rt2x00dev, TX_STA_FIFO,
155 rt2800usb_tx_sta_fifo_read_completed);
156}
157
158/*
52 * Firmware functions 159 * Firmware functions
53 */ 160 */
54static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev) 161static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
@@ -79,11 +186,11 @@ static int rt2800usb_write_firmware(struct rt2x00_dev *rt2x00dev,
79 /* 186 /*
80 * Write firmware to device. 187 * Write firmware to device.
81 */ 188 */
82 rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, 189 rt2x00usb_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
83 data + offset, length); 190 data + offset, length);
84 191
85 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0); 192 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
86 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0); 193 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
87 194
88 /* 195 /*
89 * Send firmware request to device to load firmware, 196 * Send firmware request to device to load firmware,
@@ -98,20 +205,7 @@ static int rt2800usb_write_firmware(struct rt2x00_dev *rt2x00dev,
98 } 205 }
99 206
100 msleep(10); 207 msleep(10);
101 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 208 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
102
103 /*
104 * Send signal to firmware during boot time.
105 */
106 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
107
108 if (rt2x00_rt(rt2x00dev, RT3070) ||
109 rt2x00_rt(rt2x00dev, RT3071) ||
110 rt2x00_rt(rt2x00dev, RT3572)) {
111 udelay(200);
112 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
113 udelay(10);
114 }
115 209
116 return 0; 210 return 0;
117} 211}
@@ -119,52 +213,32 @@ static int rt2800usb_write_firmware(struct rt2x00_dev *rt2x00dev,
119/* 213/*
120 * Device state switch handlers. 214 * Device state switch handlers.
121 */ 215 */
122static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
123 enum dev_state state)
124{
125 u32 reg;
126
127 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
128 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
129 (state == STATE_RADIO_RX_ON) ||
130 (state == STATE_RADIO_RX_ON_LINK));
131 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
132}
133
134static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev) 216static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
135{ 217{
136 u32 reg; 218 u32 reg;
137 int i;
138 219
139 /* 220 /*
140 * Wait until BBP and RF are ready. 221 * Wait until BBP and RF are ready.
141 */ 222 */
142 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 223 if (rt2800_wait_csr_ready(rt2x00dev))
143 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
144 if (reg && reg != ~0)
145 break;
146 msleep(1);
147 }
148
149 if (i == REGISTER_BUSY_COUNT) {
150 ERROR(rt2x00dev, "Unstable hardware.\n");
151 return -EBUSY; 224 return -EBUSY;
152 }
153 225
154 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg); 226 rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
155 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000); 227 rt2x00usb_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000);
228
229 rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
156 230
157 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 231 rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
158 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1); 232 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
159 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1); 233 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
160 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 234 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
161 235
162 rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000); 236 rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
163 237
164 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0, 238 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
165 USB_MODE_RESET, REGISTER_TIMEOUT); 239 USB_MODE_RESET, REGISTER_TIMEOUT);
166 240
167 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); 241 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
168 242
169 return 0; 243 return 0;
170} 244}
@@ -172,31 +246,11 @@ static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
172static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev) 246static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
173{ 247{
174 u32 reg; 248 u32 reg;
175 u16 word;
176 249
177 /* 250 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev)))
178 * Initialize all registers.
179 */
180 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
181 rt2800_init_registers(rt2x00dev) ||
182 rt2800_init_bbp(rt2x00dev) ||
183 rt2800_init_rfcsr(rt2x00dev)))
184 return -EIO; 251 return -EIO;
185 252
186 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 253 rt2x00usb_register_read(rt2x00dev, USB_DMA_CFG, &reg);
187 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
188 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
189
190 udelay(50);
191
192 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
193 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
194 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
195 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
196 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
197
198
199 rt2800_register_read(rt2x00dev, USB_DMA_CFG, &reg);
200 rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0); 254 rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0);
201 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN, 0); 255 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN, 0);
202 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_TIMEOUT, 128); 256 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_TIMEOUT, 128);
@@ -205,50 +259,18 @@ static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
205 * this limit so reduce the number to prevent errors. 259 * this limit so reduce the number to prevent errors.
206 */ 260 */
207 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_LIMIT, 261 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_LIMIT,
208 ((RX_ENTRIES * DATA_FRAME_SIZE) / 1024) - 3); 262 ((rt2x00dev->ops->rx->entry_num * DATA_FRAME_SIZE)
263 / 1024) - 3);
209 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1); 264 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1);
210 rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1); 265 rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1);
211 rt2800_register_write(rt2x00dev, USB_DMA_CFG, reg); 266 rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, reg);
212
213 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
214 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
215 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
216 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
217
218 /*
219 * Initialize LED control
220 */
221 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
222 rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
223 word & 0xff, (word >> 8) & 0xff);
224 267
225 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word); 268 return rt2800_enable_radio(rt2x00dev);
226 rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
227 word & 0xff, (word >> 8) & 0xff);
228
229 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
230 rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
231 word & 0xff, (word >> 8) & 0xff);
232
233 return 0;
234} 269}
235 270
236static void rt2800usb_disable_radio(struct rt2x00_dev *rt2x00dev) 271static void rt2800usb_disable_radio(struct rt2x00_dev *rt2x00dev)
237{ 272{
238 u32 reg; 273 rt2800_disable_radio(rt2x00dev);
239
240 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
241 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
242 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
243 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
244
245 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
246 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
247 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
248
249 /* Wait for DMA, ignore error */
250 rt2800_wait_wpdma_ready(rt2x00dev);
251
252 rt2x00usb_disable_radio(rt2x00dev); 274 rt2x00usb_disable_radio(rt2x00dev);
253} 275}
254 276
@@ -256,9 +278,9 @@ static int rt2800usb_set_state(struct rt2x00_dev *rt2x00dev,
256 enum dev_state state) 278 enum dev_state state)
257{ 279{
258 if (state == STATE_AWAKE) 280 if (state == STATE_AWAKE)
259 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0); 281 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 2);
260 else 282 else
261 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2); 283 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0xff, 2);
262 284
263 return 0; 285 return 0;
264} 286}
@@ -287,16 +309,8 @@ static int rt2800usb_set_device_state(struct rt2x00_dev *rt2x00dev,
287 rt2800usb_disable_radio(rt2x00dev); 309 rt2800usb_disable_radio(rt2x00dev);
288 rt2800usb_set_state(rt2x00dev, STATE_SLEEP); 310 rt2800usb_set_state(rt2x00dev, STATE_SLEEP);
289 break; 311 break;
290 case STATE_RADIO_RX_ON:
291 case STATE_RADIO_RX_ON_LINK:
292 case STATE_RADIO_RX_OFF:
293 case STATE_RADIO_RX_OFF_LINK:
294 rt2800usb_toggle_rx(rt2x00dev, state);
295 break;
296 case STATE_RADIO_IRQ_ON: 312 case STATE_RADIO_IRQ_ON:
297 case STATE_RADIO_IRQ_ON_ISR:
298 case STATE_RADIO_IRQ_OFF: 313 case STATE_RADIO_IRQ_OFF:
299 case STATE_RADIO_IRQ_OFF_ISR:
300 /* No support, but no error either */ 314 /* No support, but no error either */
301 break; 315 break;
302 case STATE_DEEP_SLEEP: 316 case STATE_DEEP_SLEEP:
@@ -318,31 +332,78 @@ static int rt2800usb_set_device_state(struct rt2x00_dev *rt2x00dev,
318} 332}
319 333
320/* 334/*
321 * TX descriptor initialization 335 * Watchdog handlers
322 */ 336 */
323static void rt2800usb_write_tx_data(struct queue_entry* entry, 337static void rt2800usb_watchdog(struct rt2x00_dev *rt2x00dev)
324 struct txentry_desc *txdesc)
325{ 338{
326 __le32 *txwi = (__le32 *) (entry->skb->data + TXINFO_DESC_SIZE); 339 unsigned int i;
340 u32 reg;
341
342 rt2x00usb_register_read(rt2x00dev, TXRXQ_PCNT, &reg);
343 if (rt2x00_get_field32(reg, TXRXQ_PCNT_TX0Q)) {
344 WARNING(rt2x00dev, "TX HW queue 0 timed out,"
345 " invoke forced kick\n");
346
347 rt2x00usb_register_write(rt2x00dev, PBF_CFG, 0xf40012);
348
349 for (i = 0; i < 10; i++) {
350 udelay(10);
351 if (!rt2x00_get_field32(reg, TXRXQ_PCNT_TX0Q))
352 break;
353 }
327 354
328 rt2800_write_txwi(txwi, txdesc); 355 rt2x00usb_register_write(rt2x00dev, PBF_CFG, 0xf40006);
356 }
357
358 rt2x00usb_register_read(rt2x00dev, TXRXQ_PCNT, &reg);
359 if (rt2x00_get_field32(reg, TXRXQ_PCNT_TX1Q)) {
360 WARNING(rt2x00dev, "TX HW queue 1 timed out,"
361 " invoke forced kick\n");
362
363 rt2x00usb_register_write(rt2x00dev, PBF_CFG, 0xf4000a);
364
365 for (i = 0; i < 10; i++) {
366 udelay(10);
367 if (!rt2x00_get_field32(reg, TXRXQ_PCNT_TX1Q))
368 break;
369 }
370
371 rt2x00usb_register_write(rt2x00dev, PBF_CFG, 0xf40006);
372 }
373
374 rt2x00usb_watchdog(rt2x00dev);
329} 375}
330 376
377/*
378 * TX descriptor initialization
379 */
380static __le32 *rt2800usb_get_txwi(struct queue_entry *entry)
381{
382 if (entry->queue->qid == QID_BEACON)
383 return (__le32 *) (entry->skb->data);
384 else
385 return (__le32 *) (entry->skb->data + TXINFO_DESC_SIZE);
386}
331 387
332static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev, 388static void rt2800usb_write_tx_desc(struct queue_entry *entry,
333 struct sk_buff *skb,
334 struct txentry_desc *txdesc) 389 struct txentry_desc *txdesc)
335{ 390{
336 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 391 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
337 __le32 *txi = (__le32 *) skb->data; 392 __le32 *txi = (__le32 *) entry->skb->data;
338 u32 word; 393 u32 word;
339 394
340 /* 395 /*
341 * Initialize TXINFO descriptor 396 * Initialize TXINFO descriptor
342 */ 397 */
343 rt2x00_desc_read(txi, 0, &word); 398 rt2x00_desc_read(txi, 0, &word);
399
400 /*
401 * The size of TXINFO_W0_USB_DMA_TX_PKT_LEN is
402 * TXWI + 802.11 header + L2 pad + payload + pad,
403 * so need to decrease size of TXINFO and USB end pad.
404 */
344 rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN, 405 rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN,
345 skb->len - TXINFO_DESC_SIZE); 406 entry->skb->len - TXINFO_DESC_SIZE - 4);
346 rt2x00_set_field32(&word, TXINFO_W0_WIV, 407 rt2x00_set_field32(&word, TXINFO_W0_WIV,
347 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags)); 408 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
348 rt2x00_set_field32(&word, TXINFO_W0_QSEL, 2); 409 rt2x00_set_field32(&word, TXINFO_W0_QSEL, 2);
@@ -360,22 +421,80 @@ static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
360 skbdesc->desc_len = TXINFO_DESC_SIZE + TXWI_DESC_SIZE; 421 skbdesc->desc_len = TXINFO_DESC_SIZE + TXWI_DESC_SIZE;
361} 422}
362 423
424static void rt2800usb_write_tx_data(struct queue_entry *entry,
425 struct txentry_desc *txdesc)
426{
427 unsigned int len;
428 int err;
429
430 rt2800_write_tx_data(entry, txdesc);
431
432 /*
433 * pad(1~3 bytes) is added after each 802.11 payload.
434 * USB end pad(4 bytes) is added at each USB bulk out packet end.
435 * TX frame format is :
436 * | TXINFO | TXWI | 802.11 header | L2 pad | payload | pad | USB end pad |
437 * |<------------- tx_pkt_len ------------->|
438 */
439 len = roundup(entry->skb->len, 4) + 4;
440 err = skb_padto(entry->skb, len);
441 if (unlikely(err)) {
442 WARNING(entry->queue->rt2x00dev, "TX SKB padding error, out of memory\n");
443 return;
444 }
445
446 entry->skb->len = len;
447}
448
363/* 449/*
364 * TX data initialization 450 * TX data initialization
365 */ 451 */
366static int rt2800usb_get_tx_data_len(struct queue_entry *entry) 452static int rt2800usb_get_tx_data_len(struct queue_entry *entry)
367{ 453{
368 int length; 454 return entry->skb->len;
455}
456
457/*
458 * TX control handlers
459 */
460static void rt2800usb_work_txdone(struct work_struct *work)
461{
462 struct rt2x00_dev *rt2x00dev =
463 container_of(work, struct rt2x00_dev, txdone_work);
464 struct data_queue *queue;
465 struct queue_entry *entry;
466
467 rt2800_txdone(rt2x00dev);
369 468
370 /* 469 /*
371 * The length _must_ include 4 bytes padding, 470 * Process any trailing TX status reports for IO failures,
372 * it should always be multiple of 4, 471 * we loop until we find the first non-IO error entry. This
373 * but it must _not_ be a multiple of the USB packet size. 472 * can either be a frame which is free, is being uploaded,
473 * or has completed the upload but didn't have an entry
474 * in the TX_STAT_FIFO register yet.
374 */ 475 */
375 length = roundup(entry->skb->len + 4, 4); 476 tx_queue_for_each(rt2x00dev, queue) {
376 length += (4 * !(length % entry->queue->usb_maxpacket)); 477 while (!rt2x00queue_empty(queue)) {
478 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
479
480 if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags))
481 break;
482 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags))
483 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
484 else if (rt2x00queue_status_timeout(entry))
485 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
486 else
487 break;
488 }
489 }
377 490
378 return length; 491 /*
492 * The hw may delay sending the packet after DMA complete
493 * if the medium is busy, thus the TX_STA_FIFO entry is
494 * also delayed -> use a timer to retrieve it.
495 */
496 if (rt2800usb_txstatus_pending(rt2x00dev))
497 mod_timer(&rt2x00dev->txstatus_timer, jiffies + msecs_to_jiffies(2));
379} 498}
380 499
381/* 500/*
@@ -433,6 +552,12 @@ static void rt2800usb_fill_rxdone(struct queue_entry *entry,
433 */ 552 */
434 rxdesc->flags |= RX_FLAG_IV_STRIPPED; 553 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
435 554
555 /*
556 * The hardware has already checked the Michael Mic and has
557 * stripped it from the frame. Signal this to mac80211.
558 */
559 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
560
436 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS) 561 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
437 rxdesc->flags |= RX_FLAG_DECRYPTED; 562 rxdesc->flags |= RX_FLAG_DECRYPTED;
438 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC) 563 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
@@ -496,24 +621,35 @@ static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
496 * This device has multiple filters for control frames 621 * This device has multiple filters for control frames
497 * and has a separate filter for PS Poll frames. 622 * and has a separate filter for PS Poll frames.
498 */ 623 */
499 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags); 624 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
500 __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags); 625 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
501 626
502 /* 627 /*
503 * This device requires firmware. 628 * This device requires firmware.
504 */ 629 */
505 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags); 630 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
506 __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags); 631 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
507 if (!modparam_nohwcrypt) 632 if (!modparam_nohwcrypt)
508 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags); 633 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
509 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags); 634 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
510 __set_bit(DRIVER_SUPPORT_WATCHDOG, &rt2x00dev->flags); 635 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
636 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
637 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
638
639 setup_timer(&rt2x00dev->txstatus_timer,
640 rt2800usb_tx_sta_fifo_timeout,
641 (unsigned long) rt2x00dev);
511 642
512 /* 643 /*
513 * Set the rssi offset. 644 * Set the rssi offset.
514 */ 645 */
515 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; 646 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
516 647
648 /*
649 * Overwrite TX done handler
650 */
651 PREPARE_WORK(&rt2x00dev->txdone_work, rt2800usb_work_txdone);
652
517 return 0; 653 return 0;
518} 654}
519 655
@@ -537,6 +673,9 @@ static const struct ieee80211_ops rt2800usb_mac80211_ops = {
537 .get_tsf = rt2800_get_tsf, 673 .get_tsf = rt2800_get_tsf,
538 .rfkill_poll = rt2x00mac_rfkill_poll, 674 .rfkill_poll = rt2x00mac_rfkill_poll,
539 .ampdu_action = rt2800_ampdu_action, 675 .ampdu_action = rt2800_ampdu_action,
676 .flush = rt2x00mac_flush,
677 .get_survey = rt2800_get_survey,
678 .get_ringparam = rt2x00mac_get_ringparam,
540}; 679};
541 680
542static const struct rt2800_ops rt2800usb_rt2800_ops = { 681static const struct rt2800_ops rt2800usb_rt2800_ops = {
@@ -549,6 +688,7 @@ static const struct rt2800_ops rt2800usb_rt2800_ops = {
549 .regbusy_read = rt2x00usb_regbusy_read, 688 .regbusy_read = rt2x00usb_regbusy_read,
550 .drv_write_firmware = rt2800usb_write_firmware, 689 .drv_write_firmware = rt2800usb_write_firmware,
551 .drv_init_registers = rt2800usb_init_registers, 690 .drv_init_registers = rt2800usb_init_registers,
691 .drv_get_txwi = rt2800usb_get_txwi,
552}; 692};
553 693
554static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = { 694static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
@@ -564,13 +704,18 @@ static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
564 .link_stats = rt2800_link_stats, 704 .link_stats = rt2800_link_stats,
565 .reset_tuner = rt2800_reset_tuner, 705 .reset_tuner = rt2800_reset_tuner,
566 .link_tuner = rt2800_link_tuner, 706 .link_tuner = rt2800_link_tuner,
567 .watchdog = rt2x00usb_watchdog, 707 .gain_calibration = rt2800_gain_calibration,
708 .watchdog = rt2800usb_watchdog,
709 .start_queue = rt2800usb_start_queue,
710 .kick_queue = rt2x00usb_kick_queue,
711 .stop_queue = rt2800usb_stop_queue,
712 .flush_queue = rt2x00usb_flush_queue,
713 .tx_dma_done = rt2800usb_tx_dma_done,
568 .write_tx_desc = rt2800usb_write_tx_desc, 714 .write_tx_desc = rt2800usb_write_tx_desc,
569 .write_tx_data = rt2800usb_write_tx_data, 715 .write_tx_data = rt2800usb_write_tx_data,
570 .write_beacon = rt2800_write_beacon, 716 .write_beacon = rt2800_write_beacon,
717 .clear_beacon = rt2800_clear_beacon,
571 .get_tx_data_len = rt2800usb_get_tx_data_len, 718 .get_tx_data_len = rt2800usb_get_tx_data_len,
572 .kick_tx_queue = rt2x00usb_kick_tx_queue,
573 .kill_tx_queue = rt2x00usb_kill_tx_queue,
574 .fill_rxdone = rt2800usb_fill_rxdone, 719 .fill_rxdone = rt2800usb_fill_rxdone,
575 .config_shared_key = rt2800_config_shared_key, 720 .config_shared_key = rt2800_config_shared_key,
576 .config_pairwise_key = rt2800_config_pairwise_key, 721 .config_pairwise_key = rt2800_config_pairwise_key,
@@ -582,21 +727,21 @@ static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
582}; 727};
583 728
584static const struct data_queue_desc rt2800usb_queue_rx = { 729static const struct data_queue_desc rt2800usb_queue_rx = {
585 .entry_num = RX_ENTRIES, 730 .entry_num = 128,
586 .data_size = AGGREGATION_SIZE, 731 .data_size = AGGREGATION_SIZE,
587 .desc_size = RXINFO_DESC_SIZE + RXWI_DESC_SIZE, 732 .desc_size = RXINFO_DESC_SIZE + RXWI_DESC_SIZE,
588 .priv_size = sizeof(struct queue_entry_priv_usb), 733 .priv_size = sizeof(struct queue_entry_priv_usb),
589}; 734};
590 735
591static const struct data_queue_desc rt2800usb_queue_tx = { 736static const struct data_queue_desc rt2800usb_queue_tx = {
592 .entry_num = TX_ENTRIES, 737 .entry_num = 64,
593 .data_size = AGGREGATION_SIZE, 738 .data_size = AGGREGATION_SIZE,
594 .desc_size = TXINFO_DESC_SIZE + TXWI_DESC_SIZE, 739 .desc_size = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
595 .priv_size = sizeof(struct queue_entry_priv_usb), 740 .priv_size = sizeof(struct queue_entry_priv_usb),
596}; 741};
597 742
598static const struct data_queue_desc rt2800usb_queue_bcn = { 743static const struct data_queue_desc rt2800usb_queue_bcn = {
599 .entry_num = 8 * BEACON_ENTRIES, 744 .entry_num = 8,
600 .data_size = MGMT_FRAME_SIZE, 745 .data_size = MGMT_FRAME_SIZE,
601 .desc_size = TXINFO_DESC_SIZE + TXWI_DESC_SIZE, 746 .desc_size = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
602 .priv_size = sizeof(struct queue_entry_priv_usb), 747 .priv_size = sizeof(struct queue_entry_priv_usb),
@@ -626,300 +771,340 @@ static const struct rt2x00_ops rt2800usb_ops = {
626 */ 771 */
627static struct usb_device_id rt2800usb_device_table[] = { 772static struct usb_device_id rt2800usb_device_table[] = {
628 /* Abocom */ 773 /* Abocom */
629 { USB_DEVICE(0x07b8, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) }, 774 { USB_DEVICE(0x07b8, 0x2870) },
630 { USB_DEVICE(0x07b8, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) }, 775 { USB_DEVICE(0x07b8, 0x2770) },
631 { USB_DEVICE(0x1482, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) }, 776 { USB_DEVICE(0x07b8, 0x3070) },
777 { USB_DEVICE(0x07b8, 0x3071) },
778 { USB_DEVICE(0x07b8, 0x3072) },
779 { USB_DEVICE(0x1482, 0x3c09) },
780 /* AirTies */
781 { USB_DEVICE(0x1eda, 0x2012) },
782 { USB_DEVICE(0x1eda, 0x2310) },
632 /* Allwin */ 783 /* Allwin */
633 { USB_DEVICE(0x8516, 0x2070), USB_DEVICE_DATA(&rt2800usb_ops) }, 784 { USB_DEVICE(0x8516, 0x2070) },
634 { USB_DEVICE(0x8516, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) }, 785 { USB_DEVICE(0x8516, 0x2770) },
635 { USB_DEVICE(0x8516, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) }, 786 { USB_DEVICE(0x8516, 0x2870) },
787 { USB_DEVICE(0x8516, 0x3070) },
788 { USB_DEVICE(0x8516, 0x3071) },
789 { USB_DEVICE(0x8516, 0x3072) },
790 /* Alpha Networks */
791 { USB_DEVICE(0x14b2, 0x3c06) },
792 { USB_DEVICE(0x14b2, 0x3c07) },
793 { USB_DEVICE(0x14b2, 0x3c09) },
794 { USB_DEVICE(0x14b2, 0x3c12) },
795 { USB_DEVICE(0x14b2, 0x3c23) },
796 { USB_DEVICE(0x14b2, 0x3c25) },
797 { USB_DEVICE(0x14b2, 0x3c27) },
798 { USB_DEVICE(0x14b2, 0x3c28) },
799 { USB_DEVICE(0x14b2, 0x3c2c) },
636 /* Amit */ 800 /* Amit */
637 { USB_DEVICE(0x15c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) }, 801 { USB_DEVICE(0x15c5, 0x0008) },
638 /* Askey */ 802 /* Askey */
639 { USB_DEVICE(0x1690, 0x0740), USB_DEVICE_DATA(&rt2800usb_ops) }, 803 { USB_DEVICE(0x1690, 0x0740) },
640 /* ASUS */ 804 /* ASUS */
641 { USB_DEVICE(0x0b05, 0x1731), USB_DEVICE_DATA(&rt2800usb_ops) }, 805 { USB_DEVICE(0x0b05, 0x1731) },
642 { USB_DEVICE(0x0b05, 0x1732), USB_DEVICE_DATA(&rt2800usb_ops) }, 806 { USB_DEVICE(0x0b05, 0x1732) },
643 { USB_DEVICE(0x0b05, 0x1742), USB_DEVICE_DATA(&rt2800usb_ops) }, 807 { USB_DEVICE(0x0b05, 0x1742) },
808 { USB_DEVICE(0x0b05, 0x1784) },
809 { USB_DEVICE(0x1761, 0x0b05) },
644 /* AzureWave */ 810 /* AzureWave */
645 { USB_DEVICE(0x13d3, 0x3247), USB_DEVICE_DATA(&rt2800usb_ops) }, 811 { USB_DEVICE(0x13d3, 0x3247) },
812 { USB_DEVICE(0x13d3, 0x3273) },
813 { USB_DEVICE(0x13d3, 0x3305) },
814 { USB_DEVICE(0x13d3, 0x3307) },
815 { USB_DEVICE(0x13d3, 0x3321) },
646 /* Belkin */ 816 /* Belkin */
647 { USB_DEVICE(0x050d, 0x8053), USB_DEVICE_DATA(&rt2800usb_ops) }, 817 { USB_DEVICE(0x050d, 0x8053) },
648 { USB_DEVICE(0x050d, 0x805c), USB_DEVICE_DATA(&rt2800usb_ops) }, 818 { USB_DEVICE(0x050d, 0x805c) },
649 { USB_DEVICE(0x050d, 0x815c), USB_DEVICE_DATA(&rt2800usb_ops) }, 819 { USB_DEVICE(0x050d, 0x815c) },
820 { USB_DEVICE(0x050d, 0x825b) },
821 { USB_DEVICE(0x050d, 0x935a) },
822 { USB_DEVICE(0x050d, 0x935b) },
650 /* Buffalo */ 823 /* Buffalo */
651 { USB_DEVICE(0x0411, 0x00e8), USB_DEVICE_DATA(&rt2800usb_ops) }, 824 { USB_DEVICE(0x0411, 0x00e8) },
652 /* Conceptronic */ 825 { USB_DEVICE(0x0411, 0x016f) },
653 { USB_DEVICE(0x14b2, 0x3c06), USB_DEVICE_DATA(&rt2800usb_ops) }, 826 { USB_DEVICE(0x0411, 0x01a2) },
654 { USB_DEVICE(0x14b2, 0x3c07), USB_DEVICE_DATA(&rt2800usb_ops) },
655 { USB_DEVICE(0x14b2, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
656 { USB_DEVICE(0x14b2, 0x3c23), USB_DEVICE_DATA(&rt2800usb_ops) },
657 { USB_DEVICE(0x14b2, 0x3c25), USB_DEVICE_DATA(&rt2800usb_ops) },
658 { USB_DEVICE(0x14b2, 0x3c27), USB_DEVICE_DATA(&rt2800usb_ops) },
659 { USB_DEVICE(0x14b2, 0x3c28), USB_DEVICE_DATA(&rt2800usb_ops) },
660 /* Corega */ 827 /* Corega */
661 { USB_DEVICE(0x07aa, 0x002f), USB_DEVICE_DATA(&rt2800usb_ops) }, 828 { USB_DEVICE(0x07aa, 0x002f) },
662 { USB_DEVICE(0x07aa, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) }, 829 { USB_DEVICE(0x07aa, 0x003c) },
663 { USB_DEVICE(0x07aa, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) }, 830 { USB_DEVICE(0x07aa, 0x003f) },
831 { USB_DEVICE(0x18c5, 0x0012) },
664 /* D-Link */ 832 /* D-Link */
665 { USB_DEVICE(0x07d1, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) }, 833 { USB_DEVICE(0x07d1, 0x3c09) },
666 { USB_DEVICE(0x07d1, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) }, 834 { USB_DEVICE(0x07d1, 0x3c0a) },
835 { USB_DEVICE(0x07d1, 0x3c0d) },
836 { USB_DEVICE(0x07d1, 0x3c0e) },
837 { USB_DEVICE(0x07d1, 0x3c0f) },
838 { USB_DEVICE(0x07d1, 0x3c11) },
839 { USB_DEVICE(0x07d1, 0x3c16) },
840 /* Draytek */
841 { USB_DEVICE(0x07fa, 0x7712) },
667 /* Edimax */ 842 /* Edimax */
668 { USB_DEVICE(0x7392, 0x7717), USB_DEVICE_DATA(&rt2800usb_ops) }, 843 { USB_DEVICE(0x7392, 0x7711) },
669 { USB_DEVICE(0x7392, 0x7718), USB_DEVICE_DATA(&rt2800usb_ops) }, 844 { USB_DEVICE(0x7392, 0x7717) },
845 { USB_DEVICE(0x7392, 0x7718) },
846 /* Encore */
847 { USB_DEVICE(0x203d, 0x1480) },
848 { USB_DEVICE(0x203d, 0x14a9) },
670 /* EnGenius */ 849 /* EnGenius */
671 { USB_DEVICE(0x1740, 0x9701), USB_DEVICE_DATA(&rt2800usb_ops) }, 850 { USB_DEVICE(0x1740, 0x9701) },
672 { USB_DEVICE(0x1740, 0x9702), USB_DEVICE_DATA(&rt2800usb_ops) }, 851 { USB_DEVICE(0x1740, 0x9702) },
852 { USB_DEVICE(0x1740, 0x9703) },
853 { USB_DEVICE(0x1740, 0x9705) },
854 { USB_DEVICE(0x1740, 0x9706) },
855 { USB_DEVICE(0x1740, 0x9707) },
856 { USB_DEVICE(0x1740, 0x9708) },
857 { USB_DEVICE(0x1740, 0x9709) },
858 /* Gemtek */
859 { USB_DEVICE(0x15a9, 0x0012) },
673 /* Gigabyte */ 860 /* Gigabyte */
674 { USB_DEVICE(0x1044, 0x800b), USB_DEVICE_DATA(&rt2800usb_ops) }, 861 { USB_DEVICE(0x1044, 0x800b) },
862 { USB_DEVICE(0x1044, 0x800d) },
675 /* Hawking */ 863 /* Hawking */
676 { USB_DEVICE(0x0e66, 0x0001), USB_DEVICE_DATA(&rt2800usb_ops) }, 864 { USB_DEVICE(0x0e66, 0x0001) },
677 { USB_DEVICE(0x0e66, 0x0003), USB_DEVICE_DATA(&rt2800usb_ops) }, 865 { USB_DEVICE(0x0e66, 0x0003) },
678 { USB_DEVICE(0x0e66, 0x0009), USB_DEVICE_DATA(&rt2800usb_ops) }, 866 { USB_DEVICE(0x0e66, 0x0009) },
679 { USB_DEVICE(0x0e66, 0x000b), USB_DEVICE_DATA(&rt2800usb_ops) }, 867 { USB_DEVICE(0x0e66, 0x000b) },
680 { USB_DEVICE(0x0e66, 0x0013), USB_DEVICE_DATA(&rt2800usb_ops) }, 868 { USB_DEVICE(0x0e66, 0x0013) },
681 { USB_DEVICE(0x0e66, 0x0017), USB_DEVICE_DATA(&rt2800usb_ops) }, 869 { USB_DEVICE(0x0e66, 0x0017) },
682 { USB_DEVICE(0x0e66, 0x0018), USB_DEVICE_DATA(&rt2800usb_ops) }, 870 { USB_DEVICE(0x0e66, 0x0018) },
871 /* I-O DATA */
872 { USB_DEVICE(0x04bb, 0x0945) },
873 { USB_DEVICE(0x04bb, 0x0947) },
874 { USB_DEVICE(0x04bb, 0x0948) },
683 /* Linksys */ 875 /* Linksys */
684 { USB_DEVICE(0x1737, 0x0070), USB_DEVICE_DATA(&rt2800usb_ops) }, 876 { USB_DEVICE(0x13b1, 0x0031) },
685 { USB_DEVICE(0x1737, 0x0071), USB_DEVICE_DATA(&rt2800usb_ops) }, 877 { USB_DEVICE(0x1737, 0x0070) },
878 { USB_DEVICE(0x1737, 0x0071) },
686 /* Logitec */ 879 /* Logitec */
687 { USB_DEVICE(0x0789, 0x0162), USB_DEVICE_DATA(&rt2800usb_ops) }, 880 { USB_DEVICE(0x0789, 0x0162) },
688 { USB_DEVICE(0x0789, 0x0163), USB_DEVICE_DATA(&rt2800usb_ops) }, 881 { USB_DEVICE(0x0789, 0x0163) },
689 { USB_DEVICE(0x0789, 0x0164), USB_DEVICE_DATA(&rt2800usb_ops) }, 882 { USB_DEVICE(0x0789, 0x0164) },
883 { USB_DEVICE(0x0789, 0x0166) },
690 /* Motorola */ 884 /* Motorola */
691 { USB_DEVICE(0x100d, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) }, 885 { USB_DEVICE(0x100d, 0x9031) },
692 /* MSI */ 886 /* MSI */
693 { USB_DEVICE(0x0db0, 0x6899), USB_DEVICE_DATA(&rt2800usb_ops) }, 887 { USB_DEVICE(0x0db0, 0x3820) },
888 { USB_DEVICE(0x0db0, 0x3821) },
889 { USB_DEVICE(0x0db0, 0x3822) },
890 { USB_DEVICE(0x0db0, 0x3870) },
891 { USB_DEVICE(0x0db0, 0x3871) },
892 { USB_DEVICE(0x0db0, 0x6899) },
893 { USB_DEVICE(0x0db0, 0x821a) },
894 { USB_DEVICE(0x0db0, 0x822a) },
895 { USB_DEVICE(0x0db0, 0x822b) },
896 { USB_DEVICE(0x0db0, 0x822c) },
897 { USB_DEVICE(0x0db0, 0x870a) },
898 { USB_DEVICE(0x0db0, 0x871a) },
899 { USB_DEVICE(0x0db0, 0x871b) },
900 { USB_DEVICE(0x0db0, 0x871c) },
901 { USB_DEVICE(0x0db0, 0x899a) },
902 /* Para */
903 { USB_DEVICE(0x20b8, 0x8888) },
904 /* Pegatron */
905 { USB_DEVICE(0x1d4d, 0x000c) },
906 { USB_DEVICE(0x1d4d, 0x000e) },
907 { USB_DEVICE(0x1d4d, 0x0011) },
694 /* Philips */ 908 /* Philips */
695 { USB_DEVICE(0x0471, 0x200f), USB_DEVICE_DATA(&rt2800usb_ops) }, 909 { USB_DEVICE(0x0471, 0x200f) },
696 /* Planex */ 910 /* Planex */
697 { USB_DEVICE(0x2019, 0xed06), USB_DEVICE_DATA(&rt2800usb_ops) }, 911 { USB_DEVICE(0x2019, 0xab25) },
912 { USB_DEVICE(0x2019, 0xed06) },
913 /* Quanta */
914 { USB_DEVICE(0x1a32, 0x0304) },
698 /* Ralink */ 915 /* Ralink */
699 { USB_DEVICE(0x148f, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) }, 916 { USB_DEVICE(0x148f, 0x2070) },
700 { USB_DEVICE(0x148f, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) }, 917 { USB_DEVICE(0x148f, 0x2770) },
918 { USB_DEVICE(0x148f, 0x2870) },
919 { USB_DEVICE(0x148f, 0x3070) },
920 { USB_DEVICE(0x148f, 0x3071) },
921 { USB_DEVICE(0x148f, 0x3072) },
701 /* Samsung */ 922 /* Samsung */
702 { USB_DEVICE(0x04e8, 0x2018), USB_DEVICE_DATA(&rt2800usb_ops) }, 923 { USB_DEVICE(0x04e8, 0x2018) },
703 /* Siemens */ 924 /* Siemens */
704 { USB_DEVICE(0x129b, 0x1828), USB_DEVICE_DATA(&rt2800usb_ops) }, 925 { USB_DEVICE(0x129b, 0x1828) },
705 /* Sitecom */ 926 /* Sitecom */
706 { USB_DEVICE(0x0df6, 0x0017), USB_DEVICE_DATA(&rt2800usb_ops) }, 927 { USB_DEVICE(0x0df6, 0x0017) },
707 { USB_DEVICE(0x0df6, 0x002b), USB_DEVICE_DATA(&rt2800usb_ops) }, 928 { USB_DEVICE(0x0df6, 0x002b) },
708 { USB_DEVICE(0x0df6, 0x002c), USB_DEVICE_DATA(&rt2800usb_ops) }, 929 { USB_DEVICE(0x0df6, 0x002c) },
709 { USB_DEVICE(0x0df6, 0x002d), USB_DEVICE_DATA(&rt2800usb_ops) }, 930 { USB_DEVICE(0x0df6, 0x002d) },
710 { USB_DEVICE(0x0df6, 0x0039), USB_DEVICE_DATA(&rt2800usb_ops) }, 931 { USB_DEVICE(0x0df6, 0x0039) },
711 { USB_DEVICE(0x0df6, 0x003b), USB_DEVICE_DATA(&rt2800usb_ops) }, 932 { USB_DEVICE(0x0df6, 0x003b) },
712 { USB_DEVICE(0x0df6, 0x003d), USB_DEVICE_DATA(&rt2800usb_ops) }, 933 { USB_DEVICE(0x0df6, 0x003d) },
713 { USB_DEVICE(0x0df6, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) }, 934 { USB_DEVICE(0x0df6, 0x003e) },
935 { USB_DEVICE(0x0df6, 0x003f) },
936 { USB_DEVICE(0x0df6, 0x0040) },
937 { USB_DEVICE(0x0df6, 0x0042) },
938 { USB_DEVICE(0x0df6, 0x0047) },
939 { USB_DEVICE(0x0df6, 0x0048) },
940 { USB_DEVICE(0x0df6, 0x0051) },
941 { USB_DEVICE(0x0df6, 0x005f) },
714 /* SMC */ 942 /* SMC */
715 { USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) }, 943 { USB_DEVICE(0x083a, 0x6618) },
716 { USB_DEVICE(0x083a, 0x7512), USB_DEVICE_DATA(&rt2800usb_ops) }, 944 { USB_DEVICE(0x083a, 0x7511) },
717 { USB_DEVICE(0x083a, 0x7522), USB_DEVICE_DATA(&rt2800usb_ops) }, 945 { USB_DEVICE(0x083a, 0x7512) },
718 { USB_DEVICE(0x083a, 0x8522), USB_DEVICE_DATA(&rt2800usb_ops) }, 946 { USB_DEVICE(0x083a, 0x7522) },
719 { USB_DEVICE(0x083a, 0xa618), USB_DEVICE_DATA(&rt2800usb_ops) }, 947 { USB_DEVICE(0x083a, 0x8522) },
720 { USB_DEVICE(0x083a, 0xb522), USB_DEVICE_DATA(&rt2800usb_ops) }, 948 { USB_DEVICE(0x083a, 0xa618) },
949 { USB_DEVICE(0x083a, 0xa701) },
950 { USB_DEVICE(0x083a, 0xa702) },
951 { USB_DEVICE(0x083a, 0xa703) },
952 { USB_DEVICE(0x083a, 0xb522) },
721 /* Sparklan */ 953 /* Sparklan */
722 { USB_DEVICE(0x15a9, 0x0006), USB_DEVICE_DATA(&rt2800usb_ops) }, 954 { USB_DEVICE(0x15a9, 0x0006) },
723 /* Sweex */ 955 /* Sweex */
724 { USB_DEVICE(0x177f, 0x0302), USB_DEVICE_DATA(&rt2800usb_ops) }, 956 { USB_DEVICE(0x177f, 0x0302) },
725 /* U-Media*/ 957 /* U-Media */
726 { USB_DEVICE(0x157e, 0x300e), USB_DEVICE_DATA(&rt2800usb_ops) }, 958 { USB_DEVICE(0x157e, 0x300e) },
959 { USB_DEVICE(0x157e, 0x3013) },
727 /* ZCOM */ 960 /* ZCOM */
728 { USB_DEVICE(0x0cde, 0x0022), USB_DEVICE_DATA(&rt2800usb_ops) }, 961 { USB_DEVICE(0x0cde, 0x0022) },
729 { USB_DEVICE(0x0cde, 0x0025), USB_DEVICE_DATA(&rt2800usb_ops) }, 962 { USB_DEVICE(0x0cde, 0x0025) },
730 /* Zinwell */ 963 /* Zinwell */
731 { USB_DEVICE(0x5a57, 0x0280), USB_DEVICE_DATA(&rt2800usb_ops) }, 964 { USB_DEVICE(0x5a57, 0x0280) },
732 { USB_DEVICE(0x5a57, 0x0282), USB_DEVICE_DATA(&rt2800usb_ops) }, 965 { USB_DEVICE(0x5a57, 0x0282) },
966 { USB_DEVICE(0x5a57, 0x0283) },
967 { USB_DEVICE(0x5a57, 0x5257) },
733 /* Zyxel */ 968 /* Zyxel */
734 { USB_DEVICE(0x0586, 0x3416), USB_DEVICE_DATA(&rt2800usb_ops) }, 969 { USB_DEVICE(0x0586, 0x3416) },
735#ifdef CONFIG_RT2800USB_RT30XX 970 { USB_DEVICE(0x0586, 0x3418) },
736 /* Abocom */ 971 { USB_DEVICE(0x0586, 0x341e) },
737 { USB_DEVICE(0x07b8, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) }, 972 { USB_DEVICE(0x0586, 0x343e) },
738 { USB_DEVICE(0x07b8, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) }, 973#ifdef CONFIG_RT2800USB_RT33XX
739 { USB_DEVICE(0x07b8, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
740 /* AirTies */
741 { USB_DEVICE(0x1eda, 0x2310), USB_DEVICE_DATA(&rt2800usb_ops) },
742 /* Allwin */
743 { USB_DEVICE(0x8516, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
744 { USB_DEVICE(0x8516, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
745 { USB_DEVICE(0x8516, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
746 /* ASUS */
747 { USB_DEVICE(0x0b05, 0x1784), USB_DEVICE_DATA(&rt2800usb_ops) },
748 /* AzureWave */
749 { USB_DEVICE(0x13d3, 0x3273), USB_DEVICE_DATA(&rt2800usb_ops) },
750 { USB_DEVICE(0x13d3, 0x3305), USB_DEVICE_DATA(&rt2800usb_ops) },
751 { USB_DEVICE(0x13d3, 0x3307), USB_DEVICE_DATA(&rt2800usb_ops) },
752 { USB_DEVICE(0x13d3, 0x3321), USB_DEVICE_DATA(&rt2800usb_ops) },
753 /* Conceptronic */
754 { USB_DEVICE(0x14b2, 0x3c12), USB_DEVICE_DATA(&rt2800usb_ops) },
755 /* Corega */
756 { USB_DEVICE(0x18c5, 0x0012), USB_DEVICE_DATA(&rt2800usb_ops) },
757 /* D-Link */
758 { USB_DEVICE(0x07d1, 0x3c0a), USB_DEVICE_DATA(&rt2800usb_ops) },
759 { USB_DEVICE(0x07d1, 0x3c0d), USB_DEVICE_DATA(&rt2800usb_ops) },
760 { USB_DEVICE(0x07d1, 0x3c0e), USB_DEVICE_DATA(&rt2800usb_ops) },
761 { USB_DEVICE(0x07d1, 0x3c0f), USB_DEVICE_DATA(&rt2800usb_ops) },
762 { USB_DEVICE(0x07d1, 0x3c16), USB_DEVICE_DATA(&rt2800usb_ops) },
763 /* Draytek */
764 { USB_DEVICE(0x07fa, 0x7712), USB_DEVICE_DATA(&rt2800usb_ops) },
765 /* Edimax */
766 { USB_DEVICE(0x7392, 0x7711), USB_DEVICE_DATA(&rt2800usb_ops) },
767 /* Encore */
768 { USB_DEVICE(0x203d, 0x1480), USB_DEVICE_DATA(&rt2800usb_ops) },
769 { USB_DEVICE(0x203d, 0x14a9), USB_DEVICE_DATA(&rt2800usb_ops) },
770 /* EnGenius */
771 { USB_DEVICE(0x1740, 0x9703), USB_DEVICE_DATA(&rt2800usb_ops) },
772 { USB_DEVICE(0x1740, 0x9705), USB_DEVICE_DATA(&rt2800usb_ops) },
773 { USB_DEVICE(0x1740, 0x9706), USB_DEVICE_DATA(&rt2800usb_ops) },
774 { USB_DEVICE(0x1740, 0x9707), USB_DEVICE_DATA(&rt2800usb_ops) },
775 { USB_DEVICE(0x1740, 0x9708), USB_DEVICE_DATA(&rt2800usb_ops) },
776 { USB_DEVICE(0x1740, 0x9709), USB_DEVICE_DATA(&rt2800usb_ops) },
777 /* Gigabyte */
778 { USB_DEVICE(0x1044, 0x800d), USB_DEVICE_DATA(&rt2800usb_ops) },
779 /* I-O DATA */
780 { USB_DEVICE(0x04bb, 0x0945), USB_DEVICE_DATA(&rt2800usb_ops) },
781 { USB_DEVICE(0x04bb, 0x0947), USB_DEVICE_DATA(&rt2800usb_ops) },
782 { USB_DEVICE(0x04bb, 0x0948), USB_DEVICE_DATA(&rt2800usb_ops) },
783 /* Logitec */
784 { USB_DEVICE(0x0789, 0x0166), USB_DEVICE_DATA(&rt2800usb_ops) },
785 /* MSI */
786 { USB_DEVICE(0x0db0, 0x3820), USB_DEVICE_DATA(&rt2800usb_ops) },
787 { USB_DEVICE(0x0db0, 0x3821), USB_DEVICE_DATA(&rt2800usb_ops) },
788 { USB_DEVICE(0x0db0, 0x3822), USB_DEVICE_DATA(&rt2800usb_ops) },
789 { USB_DEVICE(0x0db0, 0x3870), USB_DEVICE_DATA(&rt2800usb_ops) },
790 { USB_DEVICE(0x0db0, 0x3871), USB_DEVICE_DATA(&rt2800usb_ops) },
791 { USB_DEVICE(0x0db0, 0x821a), USB_DEVICE_DATA(&rt2800usb_ops) },
792 { USB_DEVICE(0x0db0, 0x822a), USB_DEVICE_DATA(&rt2800usb_ops) },
793 { USB_DEVICE(0x0db0, 0x822b), USB_DEVICE_DATA(&rt2800usb_ops) },
794 { USB_DEVICE(0x0db0, 0x822c), USB_DEVICE_DATA(&rt2800usb_ops) },
795 { USB_DEVICE(0x0db0, 0x870a), USB_DEVICE_DATA(&rt2800usb_ops) },
796 { USB_DEVICE(0x0db0, 0x871a), USB_DEVICE_DATA(&rt2800usb_ops) },
797 { USB_DEVICE(0x0db0, 0x871b), USB_DEVICE_DATA(&rt2800usb_ops) },
798 { USB_DEVICE(0x0db0, 0x871c), USB_DEVICE_DATA(&rt2800usb_ops) },
799 { USB_DEVICE(0x0db0, 0x899a), USB_DEVICE_DATA(&rt2800usb_ops) },
800 /* Para */
801 { USB_DEVICE(0x20b8, 0x8888), USB_DEVICE_DATA(&rt2800usb_ops) },
802 /* Pegatron */
803 { USB_DEVICE(0x1d4d, 0x000c), USB_DEVICE_DATA(&rt2800usb_ops) },
804 { USB_DEVICE(0x1d4d, 0x000e), USB_DEVICE_DATA(&rt2800usb_ops) },
805 /* Planex */
806 { USB_DEVICE(0x2019, 0xab25), USB_DEVICE_DATA(&rt2800usb_ops) },
807 /* Quanta */
808 { USB_DEVICE(0x1a32, 0x0304), USB_DEVICE_DATA(&rt2800usb_ops) },
809 /* Ralink */ 974 /* Ralink */
810 { USB_DEVICE(0x148f, 0x2070), USB_DEVICE_DATA(&rt2800usb_ops) }, 975 { USB_DEVICE(0x148f, 0x3370) },
811 { USB_DEVICE(0x148f, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) }, 976 { USB_DEVICE(0x148f, 0x8070) },
812 { USB_DEVICE(0x148f, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
813 { USB_DEVICE(0x148f, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
814 /* Sitecom */ 977 /* Sitecom */
815 { USB_DEVICE(0x0df6, 0x003e), USB_DEVICE_DATA(&rt2800usb_ops) }, 978 { USB_DEVICE(0x0df6, 0x0050) },
816 { USB_DEVICE(0x0df6, 0x0040), USB_DEVICE_DATA(&rt2800usb_ops) },
817 { USB_DEVICE(0x0df6, 0x0042), USB_DEVICE_DATA(&rt2800usb_ops) },
818 { USB_DEVICE(0x0df6, 0x0047), USB_DEVICE_DATA(&rt2800usb_ops) },
819 { USB_DEVICE(0x0df6, 0x0048), USB_DEVICE_DATA(&rt2800usb_ops) },
820 /* SMC */
821 { USB_DEVICE(0x083a, 0x7511), USB_DEVICE_DATA(&rt2800usb_ops) },
822 { USB_DEVICE(0x083a, 0xa701), USB_DEVICE_DATA(&rt2800usb_ops) },
823 { USB_DEVICE(0x083a, 0xa702), USB_DEVICE_DATA(&rt2800usb_ops) },
824 { USB_DEVICE(0x083a, 0xa703), USB_DEVICE_DATA(&rt2800usb_ops) },
825 /* Zinwell */
826 { USB_DEVICE(0x5a57, 0x0283), USB_DEVICE_DATA(&rt2800usb_ops) },
827 { USB_DEVICE(0x5a57, 0x5257), USB_DEVICE_DATA(&rt2800usb_ops) },
828#endif 979#endif
829#ifdef CONFIG_RT2800USB_RT35XX 980#ifdef CONFIG_RT2800USB_RT35XX
830 /* Allwin */ 981 /* Allwin */
831 { USB_DEVICE(0x8516, 0x3572), USB_DEVICE_DATA(&rt2800usb_ops) }, 982 { USB_DEVICE(0x8516, 0x3572) },
832 /* Askey */ 983 /* Askey */
833 { USB_DEVICE(0x1690, 0x0744), USB_DEVICE_DATA(&rt2800usb_ops) }, 984 { USB_DEVICE(0x1690, 0x0744) },
834 /* Cisco */ 985 /* Cisco */
835 { USB_DEVICE(0x167b, 0x4001), USB_DEVICE_DATA(&rt2800usb_ops) }, 986 { USB_DEVICE(0x167b, 0x4001) },
836 /* EnGenius */ 987 /* EnGenius */
837 { USB_DEVICE(0x1740, 0x9801), USB_DEVICE_DATA(&rt2800usb_ops) }, 988 { USB_DEVICE(0x1740, 0x9801) },
838 /* I-O DATA */ 989 /* I-O DATA */
839 { USB_DEVICE(0x04bb, 0x0944), USB_DEVICE_DATA(&rt2800usb_ops) }, 990 { USB_DEVICE(0x04bb, 0x0944) },
991 /* Linksys */
992 { USB_DEVICE(0x13b1, 0x002f) },
993 { USB_DEVICE(0x1737, 0x0079) },
840 /* Ralink */ 994 /* Ralink */
841 { USB_DEVICE(0x148f, 0x3370), USB_DEVICE_DATA(&rt2800usb_ops) }, 995 { USB_DEVICE(0x148f, 0x3572) },
842 { USB_DEVICE(0x148f, 0x3572), USB_DEVICE_DATA(&rt2800usb_ops) },
843 { USB_DEVICE(0x148f, 0x8070), USB_DEVICE_DATA(&rt2800usb_ops) },
844 /* Sitecom */ 996 /* Sitecom */
845 { USB_DEVICE(0x0df6, 0x0041), USB_DEVICE_DATA(&rt2800usb_ops) }, 997 { USB_DEVICE(0x0df6, 0x0041) },
846 { USB_DEVICE(0x0df6, 0x0050), USB_DEVICE_DATA(&rt2800usb_ops) }, 998 /* Toshiba */
999 { USB_DEVICE(0x0930, 0x0a07) },
847 /* Zinwell */ 1000 /* Zinwell */
848 { USB_DEVICE(0x5a57, 0x0284), USB_DEVICE_DATA(&rt2800usb_ops) }, 1001 { USB_DEVICE(0x5a57, 0x0284) },
1002#endif
1003#ifdef CONFIG_RT2800USB_RT53XX
1004 /* Azurewave */
1005 { USB_DEVICE(0x13d3, 0x3329) },
1006 { USB_DEVICE(0x13d3, 0x3365) },
1007 /* Ralink */
1008 { USB_DEVICE(0x148f, 0x5370) },
1009 { USB_DEVICE(0x148f, 0x5372) },
849#endif 1010#endif
850#ifdef CONFIG_RT2800USB_UNKNOWN 1011#ifdef CONFIG_RT2800USB_UNKNOWN
851 /* 1012 /*
852 * Unclear what kind of devices these are (they aren't supported by the 1013 * Unclear what kind of devices these are (they aren't supported by the
853 * vendor linux driver). 1014 * vendor linux driver).
854 */ 1015 */
1016 /* Abocom */
1017 { USB_DEVICE(0x07b8, 0x3073) },
1018 { USB_DEVICE(0x07b8, 0x3074) },
1019 /* Alpha Networks */
1020 { USB_DEVICE(0x14b2, 0x3c08) },
1021 { USB_DEVICE(0x14b2, 0x3c11) },
855 /* Amigo */ 1022 /* Amigo */
856 { USB_DEVICE(0x0e0b, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) }, 1023 { USB_DEVICE(0x0e0b, 0x9031) },
857 { USB_DEVICE(0x0e0b, 0x9041), USB_DEVICE_DATA(&rt2800usb_ops) }, 1024 { USB_DEVICE(0x0e0b, 0x9041) },
858 /* ASUS */ 1025 /* ASUS */
859 { USB_DEVICE(0x0b05, 0x1760), USB_DEVICE_DATA(&rt2800usb_ops) }, 1026 { USB_DEVICE(0x0b05, 0x166a) },
860 { USB_DEVICE(0x0b05, 0x1761), USB_DEVICE_DATA(&rt2800usb_ops) }, 1027 { USB_DEVICE(0x0b05, 0x1760) },
861 { USB_DEVICE(0x0b05, 0x1790), USB_DEVICE_DATA(&rt2800usb_ops) }, 1028 { USB_DEVICE(0x0b05, 0x1761) },
862 { USB_DEVICE(0x1761, 0x0b05), USB_DEVICE_DATA(&rt2800usb_ops) }, 1029 { USB_DEVICE(0x0b05, 0x1790) },
1030 { USB_DEVICE(0x0b05, 0x179d) },
863 /* AzureWave */ 1031 /* AzureWave */
864 { USB_DEVICE(0x13d3, 0x3262), USB_DEVICE_DATA(&rt2800usb_ops) }, 1032 { USB_DEVICE(0x13d3, 0x3262) },
865 { USB_DEVICE(0x13d3, 0x3284), USB_DEVICE_DATA(&rt2800usb_ops) }, 1033 { USB_DEVICE(0x13d3, 0x3284) },
866 { USB_DEVICE(0x13d3, 0x3322), USB_DEVICE_DATA(&rt2800usb_ops) }, 1034 { USB_DEVICE(0x13d3, 0x3322) },
867 /* Belkin */ 1035 /* Belkin */
868 { USB_DEVICE(0x050d, 0x825a), USB_DEVICE_DATA(&rt2800usb_ops) }, 1036 { USB_DEVICE(0x050d, 0x1003) },
1037 { USB_DEVICE(0x050d, 0x825a) },
869 /* Buffalo */ 1038 /* Buffalo */
870 { USB_DEVICE(0x0411, 0x012e), USB_DEVICE_DATA(&rt2800usb_ops) }, 1039 { USB_DEVICE(0x0411, 0x012e) },
871 { USB_DEVICE(0x0411, 0x0148), USB_DEVICE_DATA(&rt2800usb_ops) }, 1040 { USB_DEVICE(0x0411, 0x0148) },
872 { USB_DEVICE(0x0411, 0x0150), USB_DEVICE_DATA(&rt2800usb_ops) }, 1041 { USB_DEVICE(0x0411, 0x0150) },
873 { USB_DEVICE(0x0411, 0x015d), USB_DEVICE_DATA(&rt2800usb_ops) }, 1042 { USB_DEVICE(0x0411, 0x015d) },
874 /* Conceptronic */
875 { USB_DEVICE(0x14b2, 0x3c08), USB_DEVICE_DATA(&rt2800usb_ops) },
876 { USB_DEVICE(0x14b2, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
877 /* Corega */ 1043 /* Corega */
878 { USB_DEVICE(0x07aa, 0x0041), USB_DEVICE_DATA(&rt2800usb_ops) }, 1044 { USB_DEVICE(0x07aa, 0x0041) },
879 { USB_DEVICE(0x07aa, 0x0042), USB_DEVICE_DATA(&rt2800usb_ops) }, 1045 { USB_DEVICE(0x07aa, 0x0042) },
880 { USB_DEVICE(0x18c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) }, 1046 { USB_DEVICE(0x18c5, 0x0008) },
881 /* D-Link */ 1047 /* D-Link */
882 { USB_DEVICE(0x07d1, 0x3c0b), USB_DEVICE_DATA(&rt2800usb_ops) }, 1048 { USB_DEVICE(0x07d1, 0x3c0b) },
883 { USB_DEVICE(0x07d1, 0x3c13), USB_DEVICE_DATA(&rt2800usb_ops) }, 1049 { USB_DEVICE(0x07d1, 0x3c13) },
884 { USB_DEVICE(0x07d1, 0x3c15), USB_DEVICE_DATA(&rt2800usb_ops) }, 1050 { USB_DEVICE(0x07d1, 0x3c15) },
885 { USB_DEVICE(0x07d1, 0x3c17), USB_DEVICE_DATA(&rt2800usb_ops) }, 1051 { USB_DEVICE(0x07d1, 0x3c17) },
1052 { USB_DEVICE(0x2001, 0x3c17) },
1053 /* Edimax */
1054 { USB_DEVICE(0x7392, 0x4085) },
1055 { USB_DEVICE(0x7392, 0x7722) },
886 /* Encore */ 1056 /* Encore */
887 { USB_DEVICE(0x203d, 0x14a1), USB_DEVICE_DATA(&rt2800usb_ops) }, 1057 { USB_DEVICE(0x203d, 0x14a1) },
888 /* Gemtek */ 1058 /* Gemtek */
889 { USB_DEVICE(0x15a9, 0x0010), USB_DEVICE_DATA(&rt2800usb_ops) }, 1059 { USB_DEVICE(0x15a9, 0x0010) },
890 /* Gigabyte */ 1060 /* Gigabyte */
891 { USB_DEVICE(0x1044, 0x800c), USB_DEVICE_DATA(&rt2800usb_ops) }, 1061 { USB_DEVICE(0x1044, 0x800c) },
1062 /* Huawei */
1063 { USB_DEVICE(0x148f, 0xf101) },
1064 /* I-O DATA */
1065 { USB_DEVICE(0x04bb, 0x094b) },
892 /* LevelOne */ 1066 /* LevelOne */
893 { USB_DEVICE(0x1740, 0x0605), USB_DEVICE_DATA(&rt2800usb_ops) }, 1067 { USB_DEVICE(0x1740, 0x0605) },
894 { USB_DEVICE(0x1740, 0x0615), USB_DEVICE_DATA(&rt2800usb_ops) }, 1068 { USB_DEVICE(0x1740, 0x0615) },
895 /* Linksys */ 1069 /* Linksys */
896 { USB_DEVICE(0x1737, 0x0077), USB_DEVICE_DATA(&rt2800usb_ops) }, 1070 { USB_DEVICE(0x1737, 0x0077) },
897 { USB_DEVICE(0x1737, 0x0078), USB_DEVICE_DATA(&rt2800usb_ops) }, 1071 { USB_DEVICE(0x1737, 0x0078) },
898 { USB_DEVICE(0x1737, 0x0079), USB_DEVICE_DATA(&rt2800usb_ops) }, 1072 /* Logitec */
1073 { USB_DEVICE(0x0789, 0x0168) },
1074 { USB_DEVICE(0x0789, 0x0169) },
899 /* Motorola */ 1075 /* Motorola */
900 { USB_DEVICE(0x100d, 0x9032), USB_DEVICE_DATA(&rt2800usb_ops) }, 1076 { USB_DEVICE(0x100d, 0x9032) },
901 /* Ovislink */ 1077 /* Ovislink */
902 { USB_DEVICE(0x1b75, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) }, 1078 { USB_DEVICE(0x1b75, 0x3071) },
903 { USB_DEVICE(0x1b75, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) }, 1079 { USB_DEVICE(0x1b75, 0x3072) },
904 /* Pegatron */ 1080 /* Pegatron */
905 { USB_DEVICE(0x05a6, 0x0101), USB_DEVICE_DATA(&rt2800usb_ops) }, 1081 { USB_DEVICE(0x05a6, 0x0101) },
906 { USB_DEVICE(0x1d4d, 0x0002), USB_DEVICE_DATA(&rt2800usb_ops) }, 1082 { USB_DEVICE(0x1d4d, 0x0002) },
907 { USB_DEVICE(0x1d4d, 0x0010), USB_DEVICE_DATA(&rt2800usb_ops) }, 1083 { USB_DEVICE(0x1d4d, 0x0010) },
908 { USB_DEVICE(0x1d4d, 0x0011), USB_DEVICE_DATA(&rt2800usb_ops) },
909 /* Planex */ 1084 /* Planex */
910 { USB_DEVICE(0x2019, 0xab24), USB_DEVICE_DATA(&rt2800usb_ops) }, 1085 { USB_DEVICE(0x2019, 0x5201) },
1086 { USB_DEVICE(0x2019, 0xab24) },
911 /* Qcom */ 1087 /* Qcom */
912 { USB_DEVICE(0x18e8, 0x6259), USB_DEVICE_DATA(&rt2800usb_ops) }, 1088 { USB_DEVICE(0x18e8, 0x6259) },
1089 /* RadioShack */
1090 { USB_DEVICE(0x08b9, 0x1197) },
1091 /* Sitecom */
1092 { USB_DEVICE(0x0df6, 0x003c) },
1093 { USB_DEVICE(0x0df6, 0x004a) },
1094 { USB_DEVICE(0x0df6, 0x004d) },
1095 { USB_DEVICE(0x0df6, 0x0053) },
1096 { USB_DEVICE(0x0df6, 0x0060) },
1097 { USB_DEVICE(0x0df6, 0x0062) },
913 /* SMC */ 1098 /* SMC */
914 { USB_DEVICE(0x083a, 0xa512), USB_DEVICE_DATA(&rt2800usb_ops) }, 1099 { USB_DEVICE(0x083a, 0xa512) },
915 { USB_DEVICE(0x083a, 0xc522), USB_DEVICE_DATA(&rt2800usb_ops) }, 1100 { USB_DEVICE(0x083a, 0xc522) },
916 { USB_DEVICE(0x083a, 0xd522), USB_DEVICE_DATA(&rt2800usb_ops) }, 1101 { USB_DEVICE(0x083a, 0xd522) },
917 { USB_DEVICE(0x083a, 0xf511), USB_DEVICE_DATA(&rt2800usb_ops) }, 1102 { USB_DEVICE(0x083a, 0xf511) },
918 /* Sweex */ 1103 /* Sweex */
919 { USB_DEVICE(0x177f, 0x0153), USB_DEVICE_DATA(&rt2800usb_ops) }, 1104 { USB_DEVICE(0x177f, 0x0153) },
920 { USB_DEVICE(0x177f, 0x0313), USB_DEVICE_DATA(&rt2800usb_ops) }, 1105 { USB_DEVICE(0x177f, 0x0313) },
921 /* Zyxel */ 1106 /* Zyxel */
922 { USB_DEVICE(0x0586, 0x341a), USB_DEVICE_DATA(&rt2800usb_ops) }, 1107 { USB_DEVICE(0x0586, 0x341a) },
923#endif 1108#endif
924 { 0, } 1109 { 0, }
925}; 1110};
@@ -932,10 +1117,16 @@ MODULE_DEVICE_TABLE(usb, rt2800usb_device_table);
932MODULE_FIRMWARE(FIRMWARE_RT2870); 1117MODULE_FIRMWARE(FIRMWARE_RT2870);
933MODULE_LICENSE("GPL"); 1118MODULE_LICENSE("GPL");
934 1119
1120static int rt2800usb_probe(struct usb_interface *usb_intf,
1121 const struct usb_device_id *id)
1122{
1123 return rt2x00usb_probe(usb_intf, &rt2800usb_ops);
1124}
1125
935static struct usb_driver rt2800usb_driver = { 1126static struct usb_driver rt2800usb_driver = {
936 .name = KBUILD_MODNAME, 1127 .name = KBUILD_MODNAME,
937 .id_table = rt2800usb_device_table, 1128 .id_table = rt2800usb_device_table,
938 .probe = rt2x00usb_probe, 1129 .probe = rt2800usb_probe,
939 .disconnect = rt2x00usb_disconnect, 1130 .disconnect = rt2x00usb_disconnect,
940 .suspend = rt2x00usb_suspend, 1131 .suspend = rt2x00usb_suspend,
941 .resume = rt2x00usb_resume, 1132 .resume = rt2x00usb_resume,
diff --git a/drivers/net/wireless/rt2x00/rt2800usb.h b/drivers/net/wireless/rt2x00/rt2800usb.h
index 0722badccf86..671ea3592610 100644
--- a/drivers/net/wireless/rt2x00/rt2800usb.h
+++ b/drivers/net/wireless/rt2x00/rt2800usb.h
@@ -40,8 +40,8 @@
40/* 40/*
41 * DMA descriptor defines. 41 * DMA descriptor defines.
42 */ 42 */
43#define TXINFO_DESC_SIZE ( 1 * sizeof(__le32) ) 43#define TXINFO_DESC_SIZE (1 * sizeof(__le32))
44#define RXINFO_DESC_SIZE ( 1 * sizeof(__le32) ) 44#define RXINFO_DESC_SIZE (1 * sizeof(__le32))
45 45
46/* 46/*
47 * TX Info structure 47 * TX Info structure
diff --git a/drivers/net/wireless/rt2x00/rt2x00.h b/drivers/net/wireless/rt2x00/rt2x00.h
index c21af38cc5af..c446db69bd3c 100644
--- a/drivers/net/wireless/rt2x00/rt2x00.h
+++ b/drivers/net/wireless/rt2x00/rt2x00.h
@@ -1,5 +1,6 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com> 4 Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com>
4 <http://rt2x00.serialmonkey.com> 5 <http://rt2x00.serialmonkey.com>
5 6
@@ -35,6 +36,8 @@
35#include <linux/mutex.h> 36#include <linux/mutex.h>
36#include <linux/etherdevice.h> 37#include <linux/etherdevice.h>
37#include <linux/input-polldev.h> 38#include <linux/input-polldev.h>
39#include <linux/kfifo.h>
40#include <linux/timer.h>
38 41
39#include <net/mac80211.h> 42#include <net/mac80211.h>
40 43
@@ -64,7 +67,7 @@
64 67
65#ifdef CONFIG_RT2X00_DEBUG 68#ifdef CONFIG_RT2X00_DEBUG
66#define DEBUG_PRINTK(__dev, __kernlvl, __lvl, __msg, __args...) \ 69#define DEBUG_PRINTK(__dev, __kernlvl, __lvl, __msg, __args...) \
67 DEBUG_PRINTK_MSG(__dev, __kernlvl, __lvl, __msg, ##__args); 70 DEBUG_PRINTK_MSG(__dev, __kernlvl, __lvl, __msg, ##__args)
68#else 71#else
69#define DEBUG_PRINTK(__dev, __kernlvl, __lvl, __msg, __args...) \ 72#define DEBUG_PRINTK(__dev, __kernlvl, __lvl, __msg, __args...) \
70 do { } while (0) 73 do { } while (0)
@@ -187,6 +190,7 @@ struct rt2x00_chip {
187#define RT3572 0x3572 190#define RT3572 0x3572
188#define RT3593 0x3593 /* PCIe */ 191#define RT3593 0x3593 /* PCIe */
189#define RT3883 0x3883 /* WSOC */ 192#define RT3883 0x3883 /* WSOC */
193#define RT5390 0x5390 /* 2.4GHz */
190 194
191 u16 rf; 195 u16 rf;
192 u16 rev; 196 u16 rev;
@@ -212,8 +216,9 @@ struct channel_info {
212 unsigned int flags; 216 unsigned int flags;
213#define GEOGRAPHY_ALLOWED 0x00000001 217#define GEOGRAPHY_ALLOWED 0x00000001
214 218
215 short tx_power1; 219 short max_power;
216 short tx_power2; 220 short default_power1;
221 short default_power2;
217}; 222};
218 223
219/* 224/*
@@ -222,6 +227,8 @@ struct channel_info {
222struct antenna_setup { 227struct antenna_setup {
223 enum antenna rx; 228 enum antenna rx;
224 enum antenna tx; 229 enum antenna tx;
230 u8 rx_chain_num;
231 u8 tx_chain_num;
225}; 232};
226 233
227/* 234/*
@@ -335,8 +342,22 @@ struct link {
335 342
336 /* 343 /*
337 * Work structure for scheduling periodic watchdog monitoring. 344 * Work structure for scheduling periodic watchdog monitoring.
345 * This work must be scheduled on the kernel workqueue, while
346 * all other work structures must be queued on the mac80211
347 * workqueue. This guarantees that the watchdog can schedule
348 * other work structures and wait for their completion in order
349 * to bring the device/driver back into the desired state.
338 */ 350 */
339 struct delayed_work watchdog_work; 351 struct delayed_work watchdog_work;
352
353 /*
354 * Work structure for scheduling periodic AGC adjustments.
355 */
356 struct delayed_work agc_work;
357};
358
359enum rt2x00_delayed_flags {
360 DELAYED_UPDATE_BEACON,
340}; 361};
341 362
342/* 363/*
@@ -346,22 +367,6 @@ struct link {
346 */ 367 */
347struct rt2x00_intf { 368struct rt2x00_intf {
348 /* 369 /*
349 * All fields within the rt2x00_intf structure
350 * must be protected with a spinlock.
351 */
352 spinlock_t lock;
353
354 /*
355 * MAC of the device.
356 */
357 u8 mac[ETH_ALEN];
358
359 /*
360 * BBSID of the AP to associate with.
361 */
362 u8 bssid[ETH_ALEN];
363
364 /*
365 * beacon->skb must be protected with the mutex. 370 * beacon->skb must be protected with the mutex.
366 */ 371 */
367 struct mutex beacon_skb_mutex; 372 struct mutex beacon_skb_mutex;
@@ -372,12 +377,12 @@ struct rt2x00_intf {
372 * dedicated beacon entry. 377 * dedicated beacon entry.
373 */ 378 */
374 struct queue_entry *beacon; 379 struct queue_entry *beacon;
380 bool enable_beacon;
375 381
376 /* 382 /*
377 * Actions that needed rescheduling. 383 * Actions that needed rescheduling.
378 */ 384 */
379 unsigned int delayed_flags; 385 unsigned long delayed_flags;
380#define DELAYED_UPDATE_BEACON 0x00000001
381 386
382 /* 387 /*
383 * Software sequence counter, this is only required 388 * Software sequence counter, this is only required
@@ -455,6 +460,7 @@ struct rt2x00lib_erp {
455 short eifs; 460 short eifs;
456 461
457 u16 beacon_int; 462 u16 beacon_int;
463 u16 ht_opmode;
458}; 464};
459 465
460/* 466/*
@@ -467,7 +473,6 @@ struct rt2x00lib_crypto {
467 const u8 *address; 473 const u8 *address;
468 474
469 u32 bssidx; 475 u32 bssidx;
470 u32 aid;
471 476
472 u8 key[16]; 477 u8 key[16];
473 u8 tx_mic[8]; 478 u8 tx_mic[8];
@@ -485,13 +490,13 @@ struct rt2x00intf_conf {
485 enum nl80211_iftype type; 490 enum nl80211_iftype type;
486 491
487 /* 492 /*
488 * TSF sync value, this is dependant on the operation type. 493 * TSF sync value, this is dependent on the operation type.
489 */ 494 */
490 enum tsf_sync sync; 495 enum tsf_sync sync;
491 496
492 /* 497 /*
493 * The MAC and BSSID addressess are simple array of bytes, 498 * The MAC and BSSID addresses are simple array of bytes,
494 * these arrays are little endian, so when sending the addressess 499 * these arrays are little endian, so when sending the addresses
495 * to the drivers, copy the it into a endian-signed variable. 500 * to the drivers, copy the it into a endian-signed variable.
496 * 501 *
497 * Note that all devices (except rt2500usb) have 32 bits 502 * Note that all devices (except rt2500usb) have 32 bits
@@ -515,9 +520,13 @@ struct rt2x00lib_ops {
515 irq_handler_t irq_handler; 520 irq_handler_t irq_handler;
516 521
517 /* 522 /*
518 * Threaded Interrupt handlers. 523 * TX status tasklet handler.
519 */ 524 */
520 irq_handler_t irq_handler_thread; 525 void (*txstatus_tasklet) (unsigned long data);
526 void (*pretbtt_tasklet) (unsigned long data);
527 void (*tbtt_tasklet) (unsigned long data);
528 void (*rxdone_tasklet) (unsigned long data);
529 void (*autowake_tasklet) (unsigned long data);
521 530
522 /* 531 /*
523 * Device init handlers. 532 * Device init handlers.
@@ -553,23 +562,29 @@ struct rt2x00lib_ops {
553 struct link_qual *qual); 562 struct link_qual *qual);
554 void (*link_tuner) (struct rt2x00_dev *rt2x00dev, 563 void (*link_tuner) (struct rt2x00_dev *rt2x00dev,
555 struct link_qual *qual, const u32 count); 564 struct link_qual *qual, const u32 count);
565 void (*gain_calibration) (struct rt2x00_dev *rt2x00dev);
566
567 /*
568 * Data queue handlers.
569 */
556 void (*watchdog) (struct rt2x00_dev *rt2x00dev); 570 void (*watchdog) (struct rt2x00_dev *rt2x00dev);
571 void (*start_queue) (struct data_queue *queue);
572 void (*kick_queue) (struct data_queue *queue);
573 void (*stop_queue) (struct data_queue *queue);
574 void (*flush_queue) (struct data_queue *queue, bool drop);
575 void (*tx_dma_done) (struct queue_entry *entry);
557 576
558 /* 577 /*
559 * TX control handlers 578 * TX control handlers
560 */ 579 */
561 void (*write_tx_desc) (struct rt2x00_dev *rt2x00dev, 580 void (*write_tx_desc) (struct queue_entry *entry,
562 struct sk_buff *skb,
563 struct txentry_desc *txdesc); 581 struct txentry_desc *txdesc);
564 void (*write_tx_data) (struct queue_entry *entry, 582 void (*write_tx_data) (struct queue_entry *entry,
565 struct txentry_desc *txdesc); 583 struct txentry_desc *txdesc);
566 void (*write_beacon) (struct queue_entry *entry, 584 void (*write_beacon) (struct queue_entry *entry,
567 struct txentry_desc *txdesc); 585 struct txentry_desc *txdesc);
586 void (*clear_beacon) (struct queue_entry *entry);
568 int (*get_tx_data_len) (struct queue_entry *entry); 587 int (*get_tx_data_len) (struct queue_entry *entry);
569 void (*kick_tx_queue) (struct rt2x00_dev *rt2x00dev,
570 const enum data_queue_qid queue);
571 void (*kill_tx_queue) (struct rt2x00_dev *rt2x00dev,
572 const enum data_queue_qid queue);
573 588
574 /* 589 /*
575 * RX control handlers 590 * RX control handlers
@@ -597,7 +612,8 @@ struct rt2x00lib_ops {
597#define CONFIG_UPDATE_BSSID ( 1 << 3 ) 612#define CONFIG_UPDATE_BSSID ( 1 << 3 )
598 613
599 void (*config_erp) (struct rt2x00_dev *rt2x00dev, 614 void (*config_erp) (struct rt2x00_dev *rt2x00dev,
600 struct rt2x00lib_erp *erp); 615 struct rt2x00lib_erp *erp,
616 u32 changed);
601 void (*config_ant) (struct rt2x00_dev *rt2x00dev, 617 void (*config_ant) (struct rt2x00_dev *rt2x00dev,
602 struct antenna_setup *ant); 618 struct antenna_setup *ant);
603 void (*config) (struct rt2x00_dev *rt2x00dev, 619 void (*config) (struct rt2x00_dev *rt2x00dev,
@@ -629,11 +645,11 @@ struct rt2x00_ops {
629}; 645};
630 646
631/* 647/*
632 * rt2x00 device flags 648 * rt2x00 state flags
633 */ 649 */
634enum rt2x00_flags { 650enum rt2x00_state_flags {
635 /* 651 /*
636 * Device state flags 652 * Device flags
637 */ 653 */
638 DEVICE_STATE_PRESENT, 654 DEVICE_STATE_PRESENT,
639 DEVICE_STATE_REGISTERED_HW, 655 DEVICE_STATE_REGISTERED_HW,
@@ -643,35 +659,47 @@ enum rt2x00_flags {
643 DEVICE_STATE_SCANNING, 659 DEVICE_STATE_SCANNING,
644 660
645 /* 661 /*
646 * Driver requirements
647 */
648 DRIVER_REQUIRE_FIRMWARE,
649 DRIVER_REQUIRE_BEACON_GUARD,
650 DRIVER_REQUIRE_ATIM_QUEUE,
651 DRIVER_REQUIRE_DMA,
652 DRIVER_REQUIRE_COPY_IV,
653 DRIVER_REQUIRE_L2PAD,
654
655 /*
656 * Driver features
657 */
658 CONFIG_SUPPORT_HW_BUTTON,
659 CONFIG_SUPPORT_HW_CRYPTO,
660 DRIVER_SUPPORT_CONTROL_FILTERS,
661 DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL,
662 DRIVER_SUPPORT_PRE_TBTT_INTERRUPT,
663 DRIVER_SUPPORT_LINK_TUNING,
664 DRIVER_SUPPORT_WATCHDOG,
665
666 /*
667 * Driver configuration 662 * Driver configuration
668 */ 663 */
669 CONFIG_FRAME_TYPE,
670 CONFIG_RF_SEQUENCE,
671 CONFIG_EXTERNAL_LNA_A,
672 CONFIG_EXTERNAL_LNA_BG,
673 CONFIG_DOUBLE_ANTENNA,
674 CONFIG_CHANNEL_HT40, 664 CONFIG_CHANNEL_HT40,
665 CONFIG_POWERSAVING,
666};
667
668/*
669 * rt2x00 capability flags
670 */
671enum rt2x00_capability_flags {
672 /*
673 * Requirements
674 */
675 REQUIRE_FIRMWARE,
676 REQUIRE_BEACON_GUARD,
677 REQUIRE_ATIM_QUEUE,
678 REQUIRE_DMA,
679 REQUIRE_COPY_IV,
680 REQUIRE_L2PAD,
681 REQUIRE_TXSTATUS_FIFO,
682 REQUIRE_TASKLET_CONTEXT,
683 REQUIRE_SW_SEQNO,
684 REQUIRE_HT_TX_DESC,
685 REQUIRE_PS_AUTOWAKE,
686
687 /*
688 * Capabilities
689 */
690 CAPABILITY_HW_BUTTON,
691 CAPABILITY_HW_CRYPTO,
692 CAPABILITY_POWER_LIMIT,
693 CAPABILITY_CONTROL_FILTERS,
694 CAPABILITY_CONTROL_FILTER_PSPOLL,
695 CAPABILITY_PRE_TBTT_INTERRUPT,
696 CAPABILITY_LINK_TUNING,
697 CAPABILITY_FRAME_TYPE,
698 CAPABILITY_RF_SEQUENCE,
699 CAPABILITY_EXTERNAL_LNA_A,
700 CAPABILITY_EXTERNAL_LNA_BG,
701 CAPABILITY_DOUBLE_ANTENNA,
702 CAPABILITY_BT_COEXIST,
675}; 703};
676 704
677/* 705/*
@@ -698,6 +726,7 @@ struct rt2x00_dev {
698 struct ieee80211_hw *hw; 726 struct ieee80211_hw *hw;
699 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS]; 727 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
700 enum ieee80211_band curr_band; 728 enum ieee80211_band curr_band;
729 int curr_freq;
701 730
702 /* 731 /*
703 * If enabled, the debugfs interface structures 732 * If enabled, the debugfs interface structures
@@ -719,13 +748,20 @@ struct rt2x00_dev {
719#endif /* CONFIG_RT2X00_LIB_LEDS */ 748#endif /* CONFIG_RT2X00_LIB_LEDS */
720 749
721 /* 750 /*
722 * Device flags. 751 * Device state flags.
723 * In these flags the current status and some 752 * In these flags the current status is stored.
724 * of the device capabilities are stored. 753 * Access to these flags should occur atomically.
725 */ 754 */
726 unsigned long flags; 755 unsigned long flags;
727 756
728 /* 757 /*
758 * Device capabiltiy flags.
759 * In these flags the device/driver capabilities are stored.
760 * Access to these flags should occur non-atomically.
761 */
762 unsigned long cap_flags;
763
764 /*
729 * Device information, Bus IRQ and name (PCI, SoC) 765 * Device information, Bus IRQ and name (PCI, SoC)
730 */ 766 */
731 int irq; 767 int irq;
@@ -780,10 +816,12 @@ struct rt2x00_dev {
780 * - Open ap interface count. 816 * - Open ap interface count.
781 * - Open sta interface count. 817 * - Open sta interface count.
782 * - Association count. 818 * - Association count.
819 * - Beaconing enabled count.
783 */ 820 */
784 unsigned int intf_ap_count; 821 unsigned int intf_ap_count;
785 unsigned int intf_sta_count; 822 unsigned int intf_sta_count;
786 unsigned int intf_associated; 823 unsigned int intf_associated;
824 unsigned int intf_beaconing;
787 825
788 /* 826 /*
789 * Link quality 827 * Link quality
@@ -839,20 +877,32 @@ struct rt2x00_dev {
839 u8 calibration[2]; 877 u8 calibration[2];
840 878
841 /* 879 /*
880 * Association id.
881 */
882 u16 aid;
883
884 /*
842 * Beacon interval. 885 * Beacon interval.
843 */ 886 */
844 u16 beacon_int; 887 u16 beacon_int;
845 888
889 /**
890 * Timestamp of last received beacon
891 */
892 unsigned long last_beacon;
893
846 /* 894 /*
847 * Low level statistics which will have 895 * Low level statistics which will have
848 * to be kept up to date while device is running. 896 * to be kept up to date while device is running.
849 */ 897 */
850 struct ieee80211_low_level_stats low_level_stats; 898 struct ieee80211_low_level_stats low_level_stats;
851 899
852 /* 900 /**
853 * RX configuration information. 901 * Work queue for all work which should not be placed
902 * on the mac80211 workqueue (because of dependencies
903 * between various work structures).
854 */ 904 */
855 struct ieee80211_rx_status rx_status; 905 struct workqueue_struct *workqueue;
856 906
857 /* 907 /*
858 * Scheduled work. 908 * Scheduled work.
@@ -862,15 +912,25 @@ struct rt2x00_dev {
862 */ 912 */
863 struct work_struct intf_work; 913 struct work_struct intf_work;
864 914
915 /**
916 * Scheduled work for TX/RX done handling (USB devices)
917 */
918 struct work_struct rxdone_work;
919 struct work_struct txdone_work;
920
921 /*
922 * Powersaving work
923 */
924 struct delayed_work autowakeup_work;
925
865 /* 926 /*
866 * Data queue arrays for RX, TX and Beacon. 927 * Data queue arrays for RX, TX, Beacon and ATIM.
867 * The Beacon array also contains the Atim queue
868 * if that is supported by the device.
869 */ 928 */
870 unsigned int data_queues; 929 unsigned int data_queues;
871 struct data_queue *rx; 930 struct data_queue *rx;
872 struct data_queue *tx; 931 struct data_queue *tx;
873 struct data_queue *bcn; 932 struct data_queue *bcn;
933 struct data_queue *atim;
874 934
875 /* 935 /*
876 * Firmware image. 936 * Firmware image.
@@ -878,10 +938,28 @@ struct rt2x00_dev {
878 const struct firmware *fw; 938 const struct firmware *fw;
879 939
880 /* 940 /*
881 * Interrupt values, stored between interrupt service routine 941 * FIFO for storing tx status reports between isr and tasklet.
882 * and interrupt thread routine. 942 */
943 DECLARE_KFIFO_PTR(txstatus_fifo, u32);
944
945 /*
946 * Timer to ensure tx status reports are read (rt2800usb).
947 */
948 struct timer_list txstatus_timer;
949
950 /*
951 * Tasklet for processing tx status reports (rt2800pci).
952 */
953 struct tasklet_struct txstatus_tasklet;
954 struct tasklet_struct pretbtt_tasklet;
955 struct tasklet_struct tbtt_tasklet;
956 struct tasklet_struct rxdone_tasklet;
957 struct tasklet_struct autowake_tasklet;
958
959 /*
960 * Protect the interrupt mask register.
883 */ 961 */
884 u32 irqvalue[2]; 962 spinlock_t irqmask_lock;
885}; 963};
886 964
887/* 965/*
@@ -890,7 +968,7 @@ struct rt2x00_dev {
890 * in those cases REGISTER_BUSY_COUNT attempts should be 968 * in those cases REGISTER_BUSY_COUNT attempts should be
891 * taken with a REGISTER_BUSY_DELAY interval. 969 * taken with a REGISTER_BUSY_DELAY interval.
892 */ 970 */
893#define REGISTER_BUSY_COUNT 5 971#define REGISTER_BUSY_COUNT 100
894#define REGISTER_BUSY_DELAY 100 972#define REGISTER_BUSY_DELAY 100
895 973
896/* 974/*
@@ -1016,25 +1094,35 @@ static inline bool rt2x00_is_soc(struct rt2x00_dev *rt2x00dev)
1016 1094
1017/** 1095/**
1018 * rt2x00queue_map_txskb - Map a skb into DMA for TX purposes. 1096 * rt2x00queue_map_txskb - Map a skb into DMA for TX purposes.
1019 * @rt2x00dev: Pointer to &struct rt2x00_dev. 1097 * @entry: Pointer to &struct queue_entry
1020 * @skb: The skb to map.
1021 */ 1098 */
1022void rt2x00queue_map_txskb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb); 1099void rt2x00queue_map_txskb(struct queue_entry *entry);
1023 1100
1024/** 1101/**
1025 * rt2x00queue_unmap_skb - Unmap a skb from DMA. 1102 * rt2x00queue_unmap_skb - Unmap a skb from DMA.
1026 * @rt2x00dev: Pointer to &struct rt2x00_dev. 1103 * @entry: Pointer to &struct queue_entry
1027 * @skb: The skb to unmap.
1028 */ 1104 */
1029void rt2x00queue_unmap_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb); 1105void rt2x00queue_unmap_skb(struct queue_entry *entry);
1030 1106
1031/** 1107/**
1032 * rt2x00queue_get_queue - Convert queue index to queue pointer 1108 * rt2x00queue_get_tx_queue - Convert tx queue index to queue pointer
1033 * @rt2x00dev: Pointer to &struct rt2x00_dev. 1109 * @rt2x00dev: Pointer to &struct rt2x00_dev.
1034 * @queue: rt2x00 queue index (see &enum data_queue_qid). 1110 * @queue: rt2x00 queue index (see &enum data_queue_qid).
1111 *
1112 * Returns NULL for non tx queues.
1035 */ 1113 */
1036struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev, 1114static inline struct data_queue *
1037 const enum data_queue_qid queue); 1115rt2x00queue_get_tx_queue(struct rt2x00_dev *rt2x00dev,
1116 const enum data_queue_qid queue)
1117{
1118 if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx)
1119 return &rt2x00dev->tx[queue];
1120
1121 if (queue == QID_ATIM)
1122 return rt2x00dev->atim;
1123
1124 return NULL;
1125}
1038 1126
1039/** 1127/**
1040 * rt2x00queue_get_entry - Get queue entry where the given index points to. 1128 * rt2x00queue_get_entry - Get queue entry where the given index points to.
@@ -1044,6 +1132,78 @@ struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev,
1044struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue, 1132struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
1045 enum queue_index index); 1133 enum queue_index index);
1046 1134
1135/**
1136 * rt2x00queue_pause_queue - Pause a data queue
1137 * @queue: Pointer to &struct data_queue.
1138 *
1139 * This function will pause the data queue locally, preventing
1140 * new frames to be added to the queue (while the hardware is
1141 * still allowed to run).
1142 */
1143void rt2x00queue_pause_queue(struct data_queue *queue);
1144
1145/**
1146 * rt2x00queue_unpause_queue - unpause a data queue
1147 * @queue: Pointer to &struct data_queue.
1148 *
1149 * This function will unpause the data queue locally, allowing
1150 * new frames to be added to the queue again.
1151 */
1152void rt2x00queue_unpause_queue(struct data_queue *queue);
1153
1154/**
1155 * rt2x00queue_start_queue - Start a data queue
1156 * @queue: Pointer to &struct data_queue.
1157 *
1158 * This function will start handling all pending frames in the queue.
1159 */
1160void rt2x00queue_start_queue(struct data_queue *queue);
1161
1162/**
1163 * rt2x00queue_stop_queue - Halt a data queue
1164 * @queue: Pointer to &struct data_queue.
1165 *
1166 * This function will stop all pending frames in the queue.
1167 */
1168void rt2x00queue_stop_queue(struct data_queue *queue);
1169
1170/**
1171 * rt2x00queue_flush_queue - Flush a data queue
1172 * @queue: Pointer to &struct data_queue.
1173 * @drop: True to drop all pending frames.
1174 *
1175 * This function will flush the queue. After this call
1176 * the queue is guaranteed to be empty.
1177 */
1178void rt2x00queue_flush_queue(struct data_queue *queue, bool drop);
1179
1180/**
1181 * rt2x00queue_start_queues - Start all data queues
1182 * @rt2x00dev: Pointer to &struct rt2x00_dev.
1183 *
1184 * This function will loop through all available queues to start them
1185 */
1186void rt2x00queue_start_queues(struct rt2x00_dev *rt2x00dev);
1187
1188/**
1189 * rt2x00queue_stop_queues - Halt all data queues
1190 * @rt2x00dev: Pointer to &struct rt2x00_dev.
1191 *
1192 * This function will loop through all available queues to stop
1193 * any pending frames.
1194 */
1195void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev);
1196
1197/**
1198 * rt2x00queue_flush_queues - Flush all data queues
1199 * @rt2x00dev: Pointer to &struct rt2x00_dev.
1200 * @drop: True to drop all pending frames.
1201 *
1202 * This function will loop through all available queues to flush
1203 * any pending frames.
1204 */
1205void rt2x00queue_flush_queues(struct rt2x00_dev *rt2x00dev, bool drop);
1206
1047/* 1207/*
1048 * Debugfs handlers. 1208 * Debugfs handlers.
1049 */ 1209 */
@@ -1069,15 +1229,17 @@ static inline void rt2x00debug_dump_frame(struct rt2x00_dev *rt2x00dev,
1069 */ 1229 */
1070void rt2x00lib_beacondone(struct rt2x00_dev *rt2x00dev); 1230void rt2x00lib_beacondone(struct rt2x00_dev *rt2x00dev);
1071void rt2x00lib_pretbtt(struct rt2x00_dev *rt2x00dev); 1231void rt2x00lib_pretbtt(struct rt2x00_dev *rt2x00dev);
1232void rt2x00lib_dmastart(struct queue_entry *entry);
1233void rt2x00lib_dmadone(struct queue_entry *entry);
1072void rt2x00lib_txdone(struct queue_entry *entry, 1234void rt2x00lib_txdone(struct queue_entry *entry,
1073 struct txdone_entry_desc *txdesc); 1235 struct txdone_entry_desc *txdesc);
1074void rt2x00lib_rxdone(struct rt2x00_dev *rt2x00dev, 1236void rt2x00lib_txdone_noinfo(struct queue_entry *entry, u32 status);
1075 struct queue_entry *entry); 1237void rt2x00lib_rxdone(struct queue_entry *entry);
1076 1238
1077/* 1239/*
1078 * mac80211 handlers. 1240 * mac80211 handlers.
1079 */ 1241 */
1080int rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb); 1242void rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
1081int rt2x00mac_start(struct ieee80211_hw *hw); 1243int rt2x00mac_start(struct ieee80211_hw *hw);
1082void rt2x00mac_stop(struct ieee80211_hw *hw); 1244void rt2x00mac_stop(struct ieee80211_hw *hw);
1083int rt2x00mac_add_interface(struct ieee80211_hw *hw, 1245int rt2x00mac_add_interface(struct ieee80211_hw *hw,
@@ -1109,6 +1271,11 @@ void rt2x00mac_bss_info_changed(struct ieee80211_hw *hw,
1109int rt2x00mac_conf_tx(struct ieee80211_hw *hw, u16 queue, 1271int rt2x00mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
1110 const struct ieee80211_tx_queue_params *params); 1272 const struct ieee80211_tx_queue_params *params);
1111void rt2x00mac_rfkill_poll(struct ieee80211_hw *hw); 1273void rt2x00mac_rfkill_poll(struct ieee80211_hw *hw);
1274void rt2x00mac_flush(struct ieee80211_hw *hw, bool drop);
1275int rt2x00mac_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant);
1276int rt2x00mac_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant);
1277void rt2x00mac_get_ringparam(struct ieee80211_hw *hw,
1278 u32 *tx, u32 *tx_max, u32 *rx, u32 *rx_max);
1112 1279
1113/* 1280/*
1114 * Driver allocation handlers. 1281 * Driver allocation handlers.
diff --git a/drivers/net/wireless/rt2x00/rt2x00config.c b/drivers/net/wireless/rt2x00/rt2x00config.c
index 953dc4f2c6af..b704e5b183d0 100644
--- a/drivers/net/wireless/rt2x00/rt2x00config.c
+++ b/drivers/net/wireless/rt2x00/rt2x00config.c
@@ -60,15 +60,15 @@ void rt2x00lib_config_intf(struct rt2x00_dev *rt2x00dev,
60 * Note that when NULL is passed as address we will send 60 * Note that when NULL is passed as address we will send
61 * 00:00:00:00:00 to the device to clear the address. 61 * 00:00:00:00:00 to the device to clear the address.
62 * This will prevent the device being confused when it wants 62 * This will prevent the device being confused when it wants
63 * to ACK frames or consideres itself associated. 63 * to ACK frames or considers itself associated.
64 */ 64 */
65 memset(&conf.mac, 0, sizeof(conf.mac)); 65 memset(conf.mac, 0, sizeof(conf.mac));
66 if (mac) 66 if (mac)
67 memcpy(&conf.mac, mac, ETH_ALEN); 67 memcpy(conf.mac, mac, ETH_ALEN);
68 68
69 memset(&conf.bssid, 0, sizeof(conf.bssid)); 69 memset(conf.bssid, 0, sizeof(conf.bssid));
70 if (bssid) 70 if (bssid)
71 memcpy(&conf.bssid, bssid, ETH_ALEN); 71 memcpy(conf.bssid, bssid, ETH_ALEN);
72 72
73 flags |= CONFIG_UPDATE_TYPE; 73 flags |= CONFIG_UPDATE_TYPE;
74 if (mac || (!rt2x00dev->intf_ap_count && !rt2x00dev->intf_sta_count)) 74 if (mac || (!rt2x00dev->intf_ap_count && !rt2x00dev->intf_sta_count))
@@ -81,7 +81,8 @@ void rt2x00lib_config_intf(struct rt2x00_dev *rt2x00dev,
81 81
82void rt2x00lib_config_erp(struct rt2x00_dev *rt2x00dev, 82void rt2x00lib_config_erp(struct rt2x00_dev *rt2x00dev,
83 struct rt2x00_intf *intf, 83 struct rt2x00_intf *intf,
84 struct ieee80211_bss_conf *bss_conf) 84 struct ieee80211_bss_conf *bss_conf,
85 u32 changed)
85{ 86{
86 struct rt2x00lib_erp erp; 87 struct rt2x00lib_erp erp;
87 88
@@ -99,19 +100,17 @@ void rt2x00lib_config_erp(struct rt2x00_dev *rt2x00dev,
99 erp.basic_rates = bss_conf->basic_rates; 100 erp.basic_rates = bss_conf->basic_rates;
100 erp.beacon_int = bss_conf->beacon_int; 101 erp.beacon_int = bss_conf->beacon_int;
101 102
103 /* Update the AID, this is needed for dynamic PS support */
104 rt2x00dev->aid = bss_conf->assoc ? bss_conf->aid : 0;
105 rt2x00dev->last_beacon = bss_conf->timestamp;
106
102 /* Update global beacon interval time, this is needed for PS support */ 107 /* Update global beacon interval time, this is needed for PS support */
103 rt2x00dev->beacon_int = bss_conf->beacon_int; 108 rt2x00dev->beacon_int = bss_conf->beacon_int;
104 109
105 rt2x00dev->ops->lib->config_erp(rt2x00dev, &erp); 110 if (changed & BSS_CHANGED_HT)
106} 111 erp.ht_opmode = bss_conf->ht_operation_mode;
107 112
108static inline 113 rt2x00dev->ops->lib->config_erp(rt2x00dev, &erp, changed);
109enum antenna rt2x00lib_config_antenna_check(enum antenna current_ant,
110 enum antenna default_ant)
111{
112 if (current_ant != ANTENNA_SW_DIVERSITY)
113 return current_ant;
114 return (default_ant != ANTENNA_SW_DIVERSITY) ? default_ant : ANTENNA_B;
115} 114}
116 115
117void rt2x00lib_config_antenna(struct rt2x00_dev *rt2x00dev, 116void rt2x00lib_config_antenna(struct rt2x00_dev *rt2x00dev,
@@ -122,35 +121,43 @@ void rt2x00lib_config_antenna(struct rt2x00_dev *rt2x00dev,
122 struct antenna_setup *active = &rt2x00dev->link.ant.active; 121 struct antenna_setup *active = &rt2x00dev->link.ant.active;
123 122
124 /* 123 /*
125 * Failsafe: Make sure we are not sending the 124 * When the caller tries to send the SW diversity,
126 * ANTENNA_SW_DIVERSITY state to the driver. 125 * we must update the ANTENNA_RX_DIVERSITY flag to
127 * If that happens, fallback to hardware defaults, 126 * enable the antenna diversity in the link tuner.
128 * or our own default. 127 *
129 * If diversity handling is active for a particular antenna, 128 * Secondly, we must guarentee we never send the
130 * we shouldn't overwrite that antenna. 129 * software antenna diversity command to the driver.
131 * The calls to rt2x00lib_config_antenna_check()
132 * might have caused that we restore back to the already
133 * active setting. If that has happened we can quit.
134 */ 130 */
135 if (!(ant->flags & ANTENNA_RX_DIVERSITY)) 131 if (!(ant->flags & ANTENNA_RX_DIVERSITY)) {
136 config.rx = rt2x00lib_config_antenna_check(config.rx, def->rx); 132 if (config.rx == ANTENNA_SW_DIVERSITY) {
137 else 133 ant->flags |= ANTENNA_RX_DIVERSITY;
134
135 if (def->rx == ANTENNA_SW_DIVERSITY)
136 config.rx = ANTENNA_B;
137 else
138 config.rx = def->rx;
139 }
140 } else if (config.rx == ANTENNA_SW_DIVERSITY)
138 config.rx = active->rx; 141 config.rx = active->rx;
139 142
140 if (!(ant->flags & ANTENNA_TX_DIVERSITY)) 143 if (!(ant->flags & ANTENNA_TX_DIVERSITY)) {
141 config.tx = rt2x00lib_config_antenna_check(config.tx, def->tx); 144 if (config.tx == ANTENNA_SW_DIVERSITY) {
142 else 145 ant->flags |= ANTENNA_TX_DIVERSITY;
143 config.tx = active->tx;
144 146
145 if (config.rx == active->rx && config.tx == active->tx) 147 if (def->tx == ANTENNA_SW_DIVERSITY)
146 return; 148 config.tx = ANTENNA_B;
149 else
150 config.tx = def->tx;
151 }
152 } else if (config.tx == ANTENNA_SW_DIVERSITY)
153 config.tx = active->tx;
147 154
148 /* 155 /*
149 * Antenna setup changes require the RX to be disabled, 156 * Antenna setup changes require the RX to be disabled,
150 * else the changes will be ignored by the device. 157 * else the changes will be ignored by the device.
151 */ 158 */
152 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 159 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
153 rt2x00lib_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF_LINK); 160 rt2x00queue_stop_queue(rt2x00dev->rx);
154 161
155 /* 162 /*
156 * Write new antenna setup to device and reset the link tuner. 163 * Write new antenna setup to device and reset the link tuner.
@@ -164,7 +171,35 @@ void rt2x00lib_config_antenna(struct rt2x00_dev *rt2x00dev,
164 memcpy(active, &config, sizeof(config)); 171 memcpy(active, &config, sizeof(config));
165 172
166 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 173 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
167 rt2x00lib_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON_LINK); 174 rt2x00queue_start_queue(rt2x00dev->rx);
175}
176
177static u16 rt2x00ht_center_channel(struct rt2x00_dev *rt2x00dev,
178 struct ieee80211_conf *conf)
179{
180 struct hw_mode_spec *spec = &rt2x00dev->spec;
181 int center_channel;
182 u16 i;
183
184 /*
185 * Initialize center channel to current channel.
186 */
187 center_channel = spec->channels[conf->channel->hw_value].channel;
188
189 /*
190 * Adjust center channel to HT40+ and HT40- operation.
191 */
192 if (conf_is_ht40_plus(conf))
193 center_channel += 2;
194 else if (conf_is_ht40_minus(conf))
195 center_channel -= (center_channel == 14) ? 1 : 2;
196
197 for (i = 0; i < spec->num_channels; i++)
198 if (spec->channels[i].channel == center_channel)
199 return i;
200
201 WARN_ON(1);
202 return conf->channel->hw_value;
168} 203}
169 204
170void rt2x00lib_config(struct rt2x00_dev *rt2x00dev, 205void rt2x00lib_config(struct rt2x00_dev *rt2x00dev,
@@ -173,6 +208,9 @@ void rt2x00lib_config(struct rt2x00_dev *rt2x00dev,
173{ 208{
174 struct rt2x00lib_conf libconf; 209 struct rt2x00lib_conf libconf;
175 u16 hw_value; 210 u16 hw_value;
211 u16 autowake_timeout;
212 u16 beacon_int;
213 u16 beacon_diff;
176 214
177 memset(&libconf, 0, sizeof(libconf)); 215 memset(&libconf, 0, sizeof(libconf));
178 216
@@ -180,10 +218,10 @@ void rt2x00lib_config(struct rt2x00_dev *rt2x00dev,
180 218
181 if (ieee80211_flags & IEEE80211_CONF_CHANGE_CHANNEL) { 219 if (ieee80211_flags & IEEE80211_CONF_CHANGE_CHANNEL) {
182 if (conf_is_ht40(conf)) { 220 if (conf_is_ht40(conf)) {
183 __set_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags); 221 set_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags);
184 hw_value = rt2x00ht_center_channel(rt2x00dev, conf); 222 hw_value = rt2x00ht_center_channel(rt2x00dev, conf);
185 } else { 223 } else {
186 __clear_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags); 224 clear_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags);
187 hw_value = conf->channel->hw_value; 225 hw_value = conf->channel->hw_value;
188 } 226 }
189 227
@@ -196,6 +234,10 @@ void rt2x00lib_config(struct rt2x00_dev *rt2x00dev,
196 sizeof(libconf.channel)); 234 sizeof(libconf.channel));
197 } 235 }
198 236
237 if (test_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags) &&
238 (ieee80211_flags & IEEE80211_CONF_CHANGE_PS))
239 cancel_delayed_work_sync(&rt2x00dev->autowakeup_work);
240
199 /* 241 /*
200 * Start configuration. 242 * Start configuration.
201 */ 243 */
@@ -208,11 +250,30 @@ void rt2x00lib_config(struct rt2x00_dev *rt2x00dev,
208 if (ieee80211_flags & IEEE80211_CONF_CHANGE_CHANNEL) 250 if (ieee80211_flags & IEEE80211_CONF_CHANGE_CHANNEL)
209 rt2x00link_reset_tuner(rt2x00dev, false); 251 rt2x00link_reset_tuner(rt2x00dev, false);
210 252
253 if (test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags) &&
254 test_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags) &&
255 (ieee80211_flags & IEEE80211_CONF_CHANGE_PS) &&
256 (conf->flags & IEEE80211_CONF_PS)) {
257 beacon_diff = (long)jiffies - (long)rt2x00dev->last_beacon;
258 beacon_int = msecs_to_jiffies(rt2x00dev->beacon_int);
259
260 if (beacon_diff > beacon_int)
261 beacon_diff = 0;
262
263 autowake_timeout = (conf->max_sleep_period * beacon_int) - beacon_diff;
264 queue_delayed_work(rt2x00dev->workqueue,
265 &rt2x00dev->autowakeup_work,
266 autowake_timeout - 15);
267 }
268
269 if (conf->flags & IEEE80211_CONF_PS)
270 set_bit(CONFIG_POWERSAVING, &rt2x00dev->flags);
271 else
272 clear_bit(CONFIG_POWERSAVING, &rt2x00dev->flags);
273
211 rt2x00dev->curr_band = conf->channel->band; 274 rt2x00dev->curr_band = conf->channel->band;
275 rt2x00dev->curr_freq = conf->channel->center_freq;
212 rt2x00dev->tx_power = conf->power_level; 276 rt2x00dev->tx_power = conf->power_level;
213 rt2x00dev->short_retry = conf->short_frame_max_tx_count; 277 rt2x00dev->short_retry = conf->short_frame_max_tx_count;
214 rt2x00dev->long_retry = conf->long_frame_max_tx_count; 278 rt2x00dev->long_retry = conf->long_frame_max_tx_count;
215
216 rt2x00dev->rx_status.band = conf->channel->band;
217 rt2x00dev->rx_status.freq = conf->channel->center_freq;
218} 279}
diff --git a/drivers/net/wireless/rt2x00/rt2x00crypto.c b/drivers/net/wireless/rt2x00/rt2x00crypto.c
index 583dacd8d241..1bb9d46077ff 100644
--- a/drivers/net/wireless/rt2x00/rt2x00crypto.c
+++ b/drivers/net/wireless/rt2x00/rt2x00crypto.c
@@ -31,15 +31,14 @@
31 31
32enum cipher rt2x00crypto_key_to_cipher(struct ieee80211_key_conf *key) 32enum cipher rt2x00crypto_key_to_cipher(struct ieee80211_key_conf *key)
33{ 33{
34 switch (key->alg) { 34 switch (key->cipher) {
35 case ALG_WEP: 35 case WLAN_CIPHER_SUITE_WEP40:
36 if (key->keylen == WLAN_KEY_LEN_WEP40) 36 return CIPHER_WEP64;
37 return CIPHER_WEP64; 37 case WLAN_CIPHER_SUITE_WEP104:
38 else 38 return CIPHER_WEP128;
39 return CIPHER_WEP128; 39 case WLAN_CIPHER_SUITE_TKIP:
40 case ALG_TKIP:
41 return CIPHER_TKIP; 40 return CIPHER_TKIP;
42 case ALG_CCMP: 41 case WLAN_CIPHER_SUITE_CCMP:
43 return CIPHER_AES; 42 return CIPHER_AES;
44 default: 43 default:
45 return CIPHER_NONE; 44 return CIPHER_NONE;
@@ -53,7 +52,7 @@ void rt2x00crypto_create_tx_descriptor(struct queue_entry *entry,
53 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb); 52 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
54 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key; 53 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
55 54
56 if (!test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags) || !hw_key) 55 if (!test_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags) || !hw_key)
57 return; 56 return;
58 57
59 __set_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags); 58 __set_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags);
@@ -81,7 +80,7 @@ unsigned int rt2x00crypto_tx_overhead(struct rt2x00_dev *rt2x00dev,
81 struct ieee80211_key_conf *key = tx_info->control.hw_key; 80 struct ieee80211_key_conf *key = tx_info->control.hw_key;
82 unsigned int overhead = 0; 81 unsigned int overhead = 0;
83 82
84 if (!test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags) || !key) 83 if (!test_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags) || !key)
85 return overhead; 84 return overhead;
86 85
87 /* 86 /*
@@ -95,7 +94,7 @@ unsigned int rt2x00crypto_tx_overhead(struct rt2x00_dev *rt2x00dev,
95 overhead += key->iv_len; 94 overhead += key->iv_len;
96 95
97 if (!(key->flags & IEEE80211_KEY_FLAG_GENERATE_MMIC)) { 96 if (!(key->flags & IEEE80211_KEY_FLAG_GENERATE_MMIC)) {
98 if (key->alg == ALG_TKIP) 97 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
99 overhead += 8; 98 overhead += 8;
100 } 99 }
101 100
@@ -238,7 +237,7 @@ void rt2x00crypto_rx_insert_iv(struct sk_buff *skb,
238 } 237 }
239 238
240 /* 239 /*
241 * NOTE: Always count the payload as transfered, 240 * NOTE: Always count the payload as transferred,
242 * even when alignment was set to zero. This is required 241 * even when alignment was set to zero. This is required
243 * for determining the correct offset for the ICV data. 242 * for determining the correct offset for the ICV data.
244 */ 243 */
diff --git a/drivers/net/wireless/rt2x00/rt2x00debug.c b/drivers/net/wireless/rt2x00/rt2x00debug.c
index b0498e7e7aae..78787fcc919e 100644
--- a/drivers/net/wireless/rt2x00/rt2x00debug.c
+++ b/drivers/net/wireless/rt2x00/rt2x00debug.c
@@ -63,7 +63,8 @@ struct rt2x00debug_intf {
63 * - driver folder 63 * - driver folder
64 * - driver file 64 * - driver file
65 * - chipset file 65 * - chipset file
66 * - device flags file 66 * - device state flags file
67 * - device capability flags file
67 * - register folder 68 * - register folder
68 * - csr offset/value files 69 * - csr offset/value files
69 * - eeprom offset/value files 70 * - eeprom offset/value files
@@ -78,6 +79,7 @@ struct rt2x00debug_intf {
78 struct dentry *driver_entry; 79 struct dentry *driver_entry;
79 struct dentry *chipset_entry; 80 struct dentry *chipset_entry;
80 struct dentry *dev_flags; 81 struct dentry *dev_flags;
82 struct dentry *cap_flags;
81 struct dentry *register_folder; 83 struct dentry *register_folder;
82 struct dentry *csr_off_entry; 84 struct dentry *csr_off_entry;
83 struct dentry *csr_val_entry; 85 struct dentry *csr_val_entry;
@@ -162,11 +164,11 @@ void rt2x00debug_dump_frame(struct rt2x00_dev *rt2x00dev,
162 struct timeval timestamp; 164 struct timeval timestamp;
163 u32 data_len; 165 u32 data_len;
164 166
165 do_gettimeofday(&timestamp); 167 if (likely(!test_bit(FRAME_DUMP_FILE_OPEN, &intf->frame_dump_flags)))
166
167 if (!test_bit(FRAME_DUMP_FILE_OPEN, &intf->frame_dump_flags))
168 return; 168 return;
169 169
170 do_gettimeofday(&timestamp);
171
170 if (skb_queue_len(&intf->frame_dump_skbqueue) > 20) { 172 if (skb_queue_len(&intf->frame_dump_skbqueue) > 20) {
171 DEBUG(rt2x00dev, "txrx dump queue length exceeded.\n"); 173 DEBUG(rt2x00dev, "txrx dump queue length exceeded.\n");
172 return; 174 return;
@@ -315,6 +317,7 @@ static const struct file_operations rt2x00debug_fop_queue_dump = {
315 .poll = rt2x00debug_poll_queue_dump, 317 .poll = rt2x00debug_poll_queue_dump,
316 .open = rt2x00debug_open_queue_dump, 318 .open = rt2x00debug_open_queue_dump,
317 .release = rt2x00debug_release_queue_dump, 319 .release = rt2x00debug_release_queue_dump,
320 .llseek = default_llseek,
318}; 321};
319 322
320static ssize_t rt2x00debug_read_queue_stats(struct file *file, 323static ssize_t rt2x00debug_read_queue_stats(struct file *file,
@@ -333,23 +336,24 @@ static ssize_t rt2x00debug_read_queue_stats(struct file *file,
333 if (*offset) 336 if (*offset)
334 return 0; 337 return 0;
335 338
336 data = kzalloc(lines * MAX_LINE_LENGTH, GFP_KERNEL); 339 data = kcalloc(lines, MAX_LINE_LENGTH, GFP_KERNEL);
337 if (!data) 340 if (!data)
338 return -ENOMEM; 341 return -ENOMEM;
339 342
340 temp = data + 343 temp = data +
341 sprintf(data, "qid\tcount\tlimit\tlength\tindex\tdone\tcrypto\n"); 344 sprintf(data, "qid\tflags\t\tcount\tlimit\tlength\tindex\tdma done\tdone\n");
342 345
343 queue_for_each(intf->rt2x00dev, queue) { 346 queue_for_each(intf->rt2x00dev, queue) {
344 spin_lock_irqsave(&queue->lock, irqflags); 347 spin_lock_irqsave(&queue->index_lock, irqflags);
345 348
346 temp += sprintf(temp, "%d\t%d\t%d\t%d\t%d\t%d\t%d\n", queue->qid, 349 temp += sprintf(temp, "%d\t0x%.8x\t%d\t%d\t%d\t%d\t%d\t\t%d\n",
350 queue->qid, (unsigned int)queue->flags,
347 queue->count, queue->limit, queue->length, 351 queue->count, queue->limit, queue->length,
348 queue->index[Q_INDEX], 352 queue->index[Q_INDEX],
349 queue->index[Q_INDEX_DONE], 353 queue->index[Q_INDEX_DMA_DONE],
350 queue->index[Q_INDEX_CRYPTO]); 354 queue->index[Q_INDEX_DONE]);
351 355
352 spin_unlock_irqrestore(&queue->lock, irqflags); 356 spin_unlock_irqrestore(&queue->index_lock, irqflags);
353 } 357 }
354 358
355 size = strlen(data); 359 size = strlen(data);
@@ -371,6 +375,7 @@ static const struct file_operations rt2x00debug_fop_queue_stats = {
371 .read = rt2x00debug_read_queue_stats, 375 .read = rt2x00debug_read_queue_stats,
372 .open = rt2x00debug_file_open, 376 .open = rt2x00debug_file_open,
373 .release = rt2x00debug_file_release, 377 .release = rt2x00debug_file_release,
378 .llseek = default_llseek,
374}; 379};
375 380
376#ifdef CONFIG_RT2X00_LIB_CRYPTO 381#ifdef CONFIG_RT2X00_LIB_CRYPTO
@@ -380,7 +385,7 @@ static ssize_t rt2x00debug_read_crypto_stats(struct file *file,
380 loff_t *offset) 385 loff_t *offset)
381{ 386{
382 struct rt2x00debug_intf *intf = file->private_data; 387 struct rt2x00debug_intf *intf = file->private_data;
383 char *name[] = { "WEP64", "WEP128", "TKIP", "AES" }; 388 static const char * const name[] = { "WEP64", "WEP128", "TKIP", "AES" };
384 char *data; 389 char *data;
385 char *temp; 390 char *temp;
386 size_t size; 391 size_t size;
@@ -423,6 +428,7 @@ static const struct file_operations rt2x00debug_fop_crypto_stats = {
423 .read = rt2x00debug_read_crypto_stats, 428 .read = rt2x00debug_read_crypto_stats,
424 .open = rt2x00debug_file_open, 429 .open = rt2x00debug_file_open,
425 .release = rt2x00debug_file_release, 430 .release = rt2x00debug_file_release,
431 .llseek = default_llseek,
426}; 432};
427#endif 433#endif
428 434
@@ -481,6 +487,9 @@ static ssize_t rt2x00debug_write_##__name(struct file *file, \
481 if (index >= debug->__name.word_count) \ 487 if (index >= debug->__name.word_count) \
482 return -EINVAL; \ 488 return -EINVAL; \
483 \ 489 \
490 if (length > sizeof(line)) \
491 return -EINVAL; \
492 \
484 if (copy_from_user(line, buf, length)) \ 493 if (copy_from_user(line, buf, length)) \
485 return -EFAULT; \ 494 return -EFAULT; \
486 \ 495 \
@@ -509,6 +518,7 @@ static const struct file_operations rt2x00debug_fop_##__name = {\
509 .write = rt2x00debug_write_##__name, \ 518 .write = rt2x00debug_write_##__name, \
510 .open = rt2x00debug_file_open, \ 519 .open = rt2x00debug_file_open, \
511 .release = rt2x00debug_file_release, \ 520 .release = rt2x00debug_file_release, \
521 .llseek = generic_file_llseek, \
512}; 522};
513 523
514RT2X00DEBUGFS_OPS(csr, "0x%.8x\n", u32); 524RT2X00DEBUGFS_OPS(csr, "0x%.8x\n", u32);
@@ -542,6 +552,36 @@ static const struct file_operations rt2x00debug_fop_dev_flags = {
542 .read = rt2x00debug_read_dev_flags, 552 .read = rt2x00debug_read_dev_flags,
543 .open = rt2x00debug_file_open, 553 .open = rt2x00debug_file_open,
544 .release = rt2x00debug_file_release, 554 .release = rt2x00debug_file_release,
555 .llseek = default_llseek,
556};
557
558static ssize_t rt2x00debug_read_cap_flags(struct file *file,
559 char __user *buf,
560 size_t length,
561 loff_t *offset)
562{
563 struct rt2x00debug_intf *intf = file->private_data;
564 char line[16];
565 size_t size;
566
567 if (*offset)
568 return 0;
569
570 size = sprintf(line, "0x%.8x\n", (unsigned int)intf->rt2x00dev->cap_flags);
571
572 if (copy_to_user(buf, line, size))
573 return -EFAULT;
574
575 *offset += size;
576 return size;
577}
578
579static const struct file_operations rt2x00debug_fop_cap_flags = {
580 .owner = THIS_MODULE,
581 .read = rt2x00debug_read_cap_flags,
582 .open = rt2x00debug_file_open,
583 .release = rt2x00debug_file_release,
584 .llseek = default_llseek,
545}; 585};
546 586
547static struct dentry *rt2x00debug_create_file_driver(const char *name, 587static struct dentry *rt2x00debug_create_file_driver(const char *name,
@@ -559,7 +599,6 @@ static struct dentry *rt2x00debug_create_file_driver(const char *name,
559 blob->data = data; 599 blob->data = data;
560 data += sprintf(data, "driver:\t%s\n", intf->rt2x00dev->ops->name); 600 data += sprintf(data, "driver:\t%s\n", intf->rt2x00dev->ops->name);
561 data += sprintf(data, "version:\t%s\n", DRV_VERSION); 601 data += sprintf(data, "version:\t%s\n", DRV_VERSION);
562 data += sprintf(data, "compiled:\t%s %s\n", __DATE__, __TIME__);
563 blob->size = strlen(blob->data); 602 blob->size = strlen(blob->data);
564 603
565 return debugfs_create_blob(name, S_IRUSR, intf->driver_folder, blob); 604 return debugfs_create_blob(name, S_IRUSR, intf->driver_folder, blob);
@@ -644,6 +683,12 @@ void rt2x00debug_register(struct rt2x00_dev *rt2x00dev)
644 if (IS_ERR(intf->dev_flags) || !intf->dev_flags) 683 if (IS_ERR(intf->dev_flags) || !intf->dev_flags)
645 goto exit; 684 goto exit;
646 685
686 intf->cap_flags = debugfs_create_file("cap_flags", S_IRUSR,
687 intf->driver_folder, intf,
688 &rt2x00debug_fop_cap_flags);
689 if (IS_ERR(intf->cap_flags) || !intf->cap_flags)
690 goto exit;
691
647 intf->register_folder = 692 intf->register_folder =
648 debugfs_create_dir("register", intf->driver_folder); 693 debugfs_create_dir("register", intf->driver_folder);
649 if (IS_ERR(intf->register_folder) || !intf->register_folder) 694 if (IS_ERR(intf->register_folder) || !intf->register_folder)
@@ -697,7 +742,7 @@ void rt2x00debug_register(struct rt2x00_dev *rt2x00dev)
697 intf, &rt2x00debug_fop_queue_stats); 742 intf, &rt2x00debug_fop_queue_stats);
698 743
699#ifdef CONFIG_RT2X00_LIB_CRYPTO 744#ifdef CONFIG_RT2X00_LIB_CRYPTO
700 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) 745 if (test_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags))
701 intf->crypto_stats_entry = 746 intf->crypto_stats_entry =
702 debugfs_create_file("crypto", S_IRUGO, intf->queue_folder, 747 debugfs_create_file("crypto", S_IRUGO, intf->queue_folder,
703 intf, &rt2x00debug_fop_crypto_stats); 748 intf, &rt2x00debug_fop_crypto_stats);
@@ -735,6 +780,7 @@ void rt2x00debug_deregister(struct rt2x00_dev *rt2x00dev)
735 debugfs_remove(intf->csr_off_entry); 780 debugfs_remove(intf->csr_off_entry);
736 debugfs_remove(intf->register_folder); 781 debugfs_remove(intf->register_folder);
737 debugfs_remove(intf->dev_flags); 782 debugfs_remove(intf->dev_flags);
783 debugfs_remove(intf->cap_flags);
738 debugfs_remove(intf->chipset_entry); 784 debugfs_remove(intf->chipset_entry);
739 debugfs_remove(intf->driver_entry); 785 debugfs_remove(intf->driver_entry);
740 debugfs_remove(intf->driver_folder); 786 debugfs_remove(intf->driver_folder);
diff --git a/drivers/net/wireless/rt2x00/rt2x00dev.c b/drivers/net/wireless/rt2x00/rt2x00dev.c
index 585e8166f22a..939821b4af2f 100644
--- a/drivers/net/wireless/rt2x00/rt2x00dev.c
+++ b/drivers/net/wireless/rt2x00/rt2x00dev.c
@@ -1,5 +1,6 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 4 <http://rt2x00.serialmonkey.com>
4 5
5 This program is free software; you can redistribute it and/or modify 6 This program is free software; you can redistribute it and/or modify
@@ -26,6 +27,7 @@
26#include <linux/kernel.h> 27#include <linux/kernel.h>
27#include <linux/module.h> 28#include <linux/module.h>
28#include <linux/slab.h> 29#include <linux/slab.h>
30#include <linux/log2.h>
29 31
30#include "rt2x00.h" 32#include "rt2x00.h"
31#include "rt2x00lib.h" 33#include "rt2x00lib.h"
@@ -65,20 +67,17 @@ int rt2x00lib_enable_radio(struct rt2x00_dev *rt2x00dev)
65 set_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags); 67 set_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags);
66 68
67 /* 69 /*
68 * Enable RX. 70 * Enable queues.
69 */ 71 */
70 rt2x00lib_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON); 72 rt2x00queue_start_queues(rt2x00dev);
73 rt2x00link_start_tuner(rt2x00dev);
74 rt2x00link_start_agc(rt2x00dev);
71 75
72 /* 76 /*
73 * Start watchdog monitoring. 77 * Start watchdog monitoring.
74 */ 78 */
75 rt2x00link_start_watchdog(rt2x00dev); 79 rt2x00link_start_watchdog(rt2x00dev);
76 80
77 /*
78 * Start the TX queues.
79 */
80 ieee80211_wake_queues(rt2x00dev->hw);
81
82 return 0; 81 return 0;
83} 82}
84 83
@@ -88,20 +87,17 @@ void rt2x00lib_disable_radio(struct rt2x00_dev *rt2x00dev)
88 return; 87 return;
89 88
90 /* 89 /*
91 * Stop the TX queues in mac80211.
92 */
93 ieee80211_stop_queues(rt2x00dev->hw);
94 rt2x00queue_stop_queues(rt2x00dev);
95
96 /*
97 * Stop watchdog monitoring. 90 * Stop watchdog monitoring.
98 */ 91 */
99 rt2x00link_stop_watchdog(rt2x00dev); 92 rt2x00link_stop_watchdog(rt2x00dev);
100 93
101 /* 94 /*
102 * Disable RX. 95 * Stop all queues
103 */ 96 */
104 rt2x00lib_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF); 97 rt2x00link_stop_agc(rt2x00dev);
98 rt2x00link_stop_tuner(rt2x00dev);
99 rt2x00queue_stop_queues(rt2x00dev);
100 rt2x00queue_flush_queues(rt2x00dev, true);
105 101
106 /* 102 /*
107 * Disable radio. 103 * Disable radio.
@@ -112,41 +108,11 @@ void rt2x00lib_disable_radio(struct rt2x00_dev *rt2x00dev)
112 rt2x00leds_led_radio(rt2x00dev, false); 108 rt2x00leds_led_radio(rt2x00dev, false);
113} 109}
114 110
115void rt2x00lib_toggle_rx(struct rt2x00_dev *rt2x00dev, enum dev_state state)
116{
117 /*
118 * When we are disabling the RX, we should also stop the link tuner.
119 */
120 if (state == STATE_RADIO_RX_OFF)
121 rt2x00link_stop_tuner(rt2x00dev);
122
123 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
124
125 /*
126 * When we are enabling the RX, we should also start the link tuner.
127 */
128 if (state == STATE_RADIO_RX_ON)
129 rt2x00link_start_tuner(rt2x00dev);
130}
131
132static void rt2x00lib_intf_scheduled_iter(void *data, u8 *mac, 111static void rt2x00lib_intf_scheduled_iter(void *data, u8 *mac,
133 struct ieee80211_vif *vif) 112 struct ieee80211_vif *vif)
134{ 113{
135 struct rt2x00_dev *rt2x00dev = data; 114 struct rt2x00_dev *rt2x00dev = data;
136 struct rt2x00_intf *intf = vif_to_intf(vif); 115 struct rt2x00_intf *intf = vif_to_intf(vif);
137 int delayed_flags;
138
139 /*
140 * Copy all data we need during this action under the protection
141 * of a spinlock. Otherwise race conditions might occur which results
142 * into an invalid configuration.
143 */
144 spin_lock(&intf->lock);
145
146 delayed_flags = intf->delayed_flags;
147 intf->delayed_flags = 0;
148
149 spin_unlock(&intf->lock);
150 116
151 /* 117 /*
152 * It is possible the radio was disabled while the work had been 118 * It is possible the radio was disabled while the work had been
@@ -157,8 +123,8 @@ static void rt2x00lib_intf_scheduled_iter(void *data, u8 *mac,
157 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 123 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
158 return; 124 return;
159 125
160 if (delayed_flags & DELAYED_UPDATE_BEACON) 126 if (test_and_clear_bit(DELAYED_UPDATE_BEACON, &intf->delayed_flags))
161 rt2x00queue_update_beacon(rt2x00dev, vif, true); 127 rt2x00queue_update_beacon(rt2x00dev, vif);
162} 128}
163 129
164static void rt2x00lib_intf_scheduled(struct work_struct *work) 130static void rt2x00lib_intf_scheduled(struct work_struct *work)
@@ -175,6 +141,19 @@ static void rt2x00lib_intf_scheduled(struct work_struct *work)
175 rt2x00dev); 141 rt2x00dev);
176} 142}
177 143
144static void rt2x00lib_autowakeup(struct work_struct *work)
145{
146 struct rt2x00_dev *rt2x00dev =
147 container_of(work, struct rt2x00_dev, autowakeup_work.work);
148
149 if (!test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags))
150 return;
151
152 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
153 ERROR(rt2x00dev, "Device failed to wakeup.\n");
154 clear_bit(CONFIG_POWERSAVING, &rt2x00dev->flags);
155}
156
178/* 157/*
179 * Interrupt context handlers. 158 * Interrupt context handlers.
180 */ 159 */
@@ -211,7 +190,13 @@ static void rt2x00lib_beaconupdate_iter(void *data, u8 *mac,
211 vif->type != NL80211_IFTYPE_WDS) 190 vif->type != NL80211_IFTYPE_WDS)
212 return; 191 return;
213 192
214 rt2x00queue_update_beacon(rt2x00dev, vif, true); 193 /*
194 * Update the beacon without locking. This is safe on PCI devices
195 * as they only update the beacon periodically here. This should
196 * never be called for USB devices.
197 */
198 WARN_ON(rt2x00_is_usb(rt2x00dev));
199 rt2x00queue_update_beacon_locked(rt2x00dev, vif);
215} 200}
216 201
217void rt2x00lib_beacondone(struct rt2x00_dev *rt2x00dev) 202void rt2x00lib_beacondone(struct rt2x00_dev *rt2x00dev)
@@ -220,21 +205,21 @@ void rt2x00lib_beacondone(struct rt2x00_dev *rt2x00dev)
220 return; 205 return;
221 206
222 /* send buffered bc/mc frames out for every bssid */ 207 /* send buffered bc/mc frames out for every bssid */
223 ieee80211_iterate_active_interfaces(rt2x00dev->hw, 208 ieee80211_iterate_active_interfaces_atomic(rt2x00dev->hw,
224 rt2x00lib_bc_buffer_iter, 209 rt2x00lib_bc_buffer_iter,
225 rt2x00dev); 210 rt2x00dev);
226 /* 211 /*
227 * Devices with pre tbtt interrupt don't need to update the beacon 212 * Devices with pre tbtt interrupt don't need to update the beacon
228 * here as they will fetch the next beacon directly prior to 213 * here as they will fetch the next beacon directly prior to
229 * transmission. 214 * transmission.
230 */ 215 */
231 if (test_bit(DRIVER_SUPPORT_PRE_TBTT_INTERRUPT, &rt2x00dev->flags)) 216 if (test_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags))
232 return; 217 return;
233 218
234 /* fetch next beacon */ 219 /* fetch next beacon */
235 ieee80211_iterate_active_interfaces(rt2x00dev->hw, 220 ieee80211_iterate_active_interfaces_atomic(rt2x00dev->hw,
236 rt2x00lib_beaconupdate_iter, 221 rt2x00lib_beaconupdate_iter,
237 rt2x00dev); 222 rt2x00dev);
238} 223}
239EXPORT_SYMBOL_GPL(rt2x00lib_beacondone); 224EXPORT_SYMBOL_GPL(rt2x00lib_beacondone);
240 225
@@ -244,29 +229,42 @@ void rt2x00lib_pretbtt(struct rt2x00_dev *rt2x00dev)
244 return; 229 return;
245 230
246 /* fetch next beacon */ 231 /* fetch next beacon */
247 ieee80211_iterate_active_interfaces(rt2x00dev->hw, 232 ieee80211_iterate_active_interfaces_atomic(rt2x00dev->hw,
248 rt2x00lib_beaconupdate_iter, 233 rt2x00lib_beaconupdate_iter,
249 rt2x00dev); 234 rt2x00dev);
250} 235}
251EXPORT_SYMBOL_GPL(rt2x00lib_pretbtt); 236EXPORT_SYMBOL_GPL(rt2x00lib_pretbtt);
252 237
238void rt2x00lib_dmastart(struct queue_entry *entry)
239{
240 set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
241 rt2x00queue_index_inc(entry, Q_INDEX);
242}
243EXPORT_SYMBOL_GPL(rt2x00lib_dmastart);
244
245void rt2x00lib_dmadone(struct queue_entry *entry)
246{
247 set_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags);
248 clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
249 rt2x00queue_index_inc(entry, Q_INDEX_DMA_DONE);
250}
251EXPORT_SYMBOL_GPL(rt2x00lib_dmadone);
252
253void rt2x00lib_txdone(struct queue_entry *entry, 253void rt2x00lib_txdone(struct queue_entry *entry,
254 struct txdone_entry_desc *txdesc) 254 struct txdone_entry_desc *txdesc)
255{ 255{
256 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 256 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
257 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb); 257 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
258 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 258 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
259 enum data_queue_qid qid = skb_get_queue_mapping(entry->skb); 259 unsigned int header_length, i;
260 unsigned int header_length = ieee80211_get_hdrlen_from_skb(entry->skb);
261 u8 rate_idx, rate_flags, retry_rates; 260 u8 rate_idx, rate_flags, retry_rates;
262 u8 skbdesc_flags = skbdesc->flags; 261 u8 skbdesc_flags = skbdesc->flags;
263 unsigned int i;
264 bool success; 262 bool success;
265 263
266 /* 264 /*
267 * Unmap the skb. 265 * Unmap the skb.
268 */ 266 */
269 rt2x00queue_unmap_skb(rt2x00dev, entry->skb); 267 rt2x00queue_unmap_skb(entry);
270 268
271 /* 269 /*
272 * Remove the extra tx headroom from the skb. 270 * Remove the extra tx headroom from the skb.
@@ -279,9 +277,14 @@ void rt2x00lib_txdone(struct queue_entry *entry,
279 skbdesc->flags &= ~SKBDESC_DESC_IN_SKB; 277 skbdesc->flags &= ~SKBDESC_DESC_IN_SKB;
280 278
281 /* 279 /*
280 * Determine the length of 802.11 header.
281 */
282 header_length = ieee80211_get_hdrlen_from_skb(entry->skb);
283
284 /*
282 * Remove L2 padding which was added during 285 * Remove L2 padding which was added during
283 */ 286 */
284 if (test_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags)) 287 if (test_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags))
285 rt2x00queue_remove_l2pad(entry->skb, header_length); 288 rt2x00queue_remove_l2pad(entry->skb, header_length);
286 289
287 /* 290 /*
@@ -290,7 +293,7 @@ void rt2x00lib_txdone(struct queue_entry *entry,
290 * mac80211 will expect the same data to be present it the 293 * mac80211 will expect the same data to be present it the
291 * frame as it was passed to us. 294 * frame as it was passed to us.
292 */ 295 */
293 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) 296 if (test_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags))
294 rt2x00crypto_tx_insert_iv(entry->skb, header_length); 297 rt2x00crypto_tx_insert_iv(entry->skb, header_length);
295 298
296 /* 299 /*
@@ -363,10 +366,14 @@ void rt2x00lib_txdone(struct queue_entry *entry,
363 * which would allow the rc algorithm to better decide on 366 * which would allow the rc algorithm to better decide on
364 * which rates are suitable. 367 * which rates are suitable.
365 */ 368 */
366 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { 369 if (test_bit(TXDONE_AMPDU, &txdesc->flags) ||
370 tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
367 tx_info->flags |= IEEE80211_TX_STAT_AMPDU; 371 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
368 tx_info->status.ampdu_len = 1; 372 tx_info->status.ampdu_len = 1;
369 tx_info->status.ampdu_ack_len = success ? 1 : 0; 373 tx_info->status.ampdu_ack_len = success ? 1 : 0;
374
375 if (!success)
376 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
370 } 377 }
371 378
372 if (rate_flags & IEEE80211_TX_RC_USE_RTS_CTS) { 379 if (rate_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
@@ -382,17 +389,12 @@ void rt2x00lib_txdone(struct queue_entry *entry,
382 * through a mac80211 library call (RTS/CTS) then we should not 389 * through a mac80211 library call (RTS/CTS) then we should not
383 * send the status report back. 390 * send the status report back.
384 */ 391 */
385 if (!(skbdesc_flags & SKBDESC_NOT_MAC80211)) 392 if (!(skbdesc_flags & SKBDESC_NOT_MAC80211)) {
386 /* 393 if (test_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags))
387 * Only PCI and SOC devices process the tx status in process
388 * context. Hence use ieee80211_tx_status for PCI and SOC
389 * devices and stick to ieee80211_tx_status_irqsafe for USB.
390 */
391 if (rt2x00_is_usb(rt2x00dev))
392 ieee80211_tx_status_irqsafe(rt2x00dev->hw, entry->skb);
393 else
394 ieee80211_tx_status(rt2x00dev->hw, entry->skb); 394 ieee80211_tx_status(rt2x00dev->hw, entry->skb);
395 else 395 else
396 ieee80211_tx_status_ni(rt2x00dev->hw, entry->skb);
397 } else
396 dev_kfree_skb_any(entry->skb); 398 dev_kfree_skb_any(entry->skb);
397 399
398 /* 400 /*
@@ -403,8 +405,7 @@ void rt2x00lib_txdone(struct queue_entry *entry,
403 405
404 rt2x00dev->ops->lib->clear_entry(entry); 406 rt2x00dev->ops->lib->clear_entry(entry);
405 407
406 clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags); 408 rt2x00queue_index_inc(entry, Q_INDEX_DONE);
407 rt2x00queue_index_inc(entry->queue, Q_INDEX_DONE);
408 409
409 /* 410 /*
410 * If the data queue was below the threshold before the txdone 411 * If the data queue was below the threshold before the txdone
@@ -412,69 +413,168 @@ void rt2x00lib_txdone(struct queue_entry *entry,
412 * is reenabled when the txdone handler has finished. 413 * is reenabled when the txdone handler has finished.
413 */ 414 */
414 if (!rt2x00queue_threshold(entry->queue)) 415 if (!rt2x00queue_threshold(entry->queue))
415 ieee80211_wake_queue(rt2x00dev->hw, qid); 416 rt2x00queue_unpause_queue(entry->queue);
416} 417}
417EXPORT_SYMBOL_GPL(rt2x00lib_txdone); 418EXPORT_SYMBOL_GPL(rt2x00lib_txdone);
418 419
420void rt2x00lib_txdone_noinfo(struct queue_entry *entry, u32 status)
421{
422 struct txdone_entry_desc txdesc;
423
424 txdesc.flags = 0;
425 __set_bit(status, &txdesc.flags);
426 txdesc.retry = 0;
427
428 rt2x00lib_txdone(entry, &txdesc);
429}
430EXPORT_SYMBOL_GPL(rt2x00lib_txdone_noinfo);
431
432static u8 *rt2x00lib_find_ie(u8 *data, unsigned int len, u8 ie)
433{
434 struct ieee80211_mgmt *mgmt = (void *)data;
435 u8 *pos, *end;
436
437 pos = (u8 *)mgmt->u.beacon.variable;
438 end = data + len;
439 while (pos < end) {
440 if (pos + 2 + pos[1] > end)
441 return NULL;
442
443 if (pos[0] == ie)
444 return pos;
445
446 pos += 2 + pos[1];
447 }
448
449 return NULL;
450}
451
452static void rt2x00lib_rxdone_check_ps(struct rt2x00_dev *rt2x00dev,
453 struct sk_buff *skb,
454 struct rxdone_entry_desc *rxdesc)
455{
456 struct ieee80211_hdr *hdr = (void *) skb->data;
457 struct ieee80211_tim_ie *tim_ie;
458 u8 *tim;
459 u8 tim_len;
460 bool cam;
461
462 /* If this is not a beacon, or if mac80211 has no powersaving
463 * configured, or if the device is already in powersaving mode
464 * we can exit now. */
465 if (likely(!ieee80211_is_beacon(hdr->frame_control) ||
466 !(rt2x00dev->hw->conf.flags & IEEE80211_CONF_PS)))
467 return;
468
469 /* min. beacon length + FCS_LEN */
470 if (skb->len <= 40 + FCS_LEN)
471 return;
472
473 /* and only beacons from the associated BSSID, please */
474 if (!(rxdesc->dev_flags & RXDONE_MY_BSS) ||
475 !rt2x00dev->aid)
476 return;
477
478 rt2x00dev->last_beacon = jiffies;
479
480 tim = rt2x00lib_find_ie(skb->data, skb->len - FCS_LEN, WLAN_EID_TIM);
481 if (!tim)
482 return;
483
484 if (tim[1] < sizeof(*tim_ie))
485 return;
486
487 tim_len = tim[1];
488 tim_ie = (struct ieee80211_tim_ie *) &tim[2];
489
490 /* Check whenever the PHY can be turned off again. */
491
492 /* 1. What about buffered unicast traffic for our AID? */
493 cam = ieee80211_check_tim(tim_ie, tim_len, rt2x00dev->aid);
494
495 /* 2. Maybe the AP wants to send multicast/broadcast data? */
496 cam |= (tim_ie->bitmap_ctrl & 0x01);
497
498 if (!cam && !test_bit(CONFIG_POWERSAVING, &rt2x00dev->flags))
499 rt2x00lib_config(rt2x00dev, &rt2x00dev->hw->conf,
500 IEEE80211_CONF_CHANGE_PS);
501}
502
419static int rt2x00lib_rxdone_read_signal(struct rt2x00_dev *rt2x00dev, 503static int rt2x00lib_rxdone_read_signal(struct rt2x00_dev *rt2x00dev,
420 struct rxdone_entry_desc *rxdesc) 504 struct rxdone_entry_desc *rxdesc)
421{ 505{
422 struct ieee80211_supported_band *sband; 506 struct ieee80211_supported_band *sband;
423 const struct rt2x00_rate *rate; 507 const struct rt2x00_rate *rate;
424 unsigned int i; 508 unsigned int i;
425 int signal; 509 int signal = rxdesc->signal;
426 int type; 510 int type = (rxdesc->dev_flags & RXDONE_SIGNAL_MASK);
427
428 /*
429 * For non-HT rates the MCS value needs to contain the
430 * actually used rate modulation (CCK or OFDM).
431 */
432 if (rxdesc->dev_flags & RXDONE_SIGNAL_MCS)
433 signal = RATE_MCS(rxdesc->rate_mode, rxdesc->signal);
434 else
435 signal = rxdesc->signal;
436 511
437 type = (rxdesc->dev_flags & RXDONE_SIGNAL_MASK); 512 switch (rxdesc->rate_mode) {
438 513 case RATE_MODE_CCK:
439 sband = &rt2x00dev->bands[rt2x00dev->curr_band]; 514 case RATE_MODE_OFDM:
440 for (i = 0; i < sband->n_bitrates; i++) { 515 /*
441 rate = rt2x00_get_rate(sband->bitrates[i].hw_value); 516 * For non-HT rates the MCS value needs to contain the
442 517 * actually used rate modulation (CCK or OFDM).
443 if (((type == RXDONE_SIGNAL_PLCP) && 518 */
444 (rate->plcp == signal)) || 519 if (rxdesc->dev_flags & RXDONE_SIGNAL_MCS)
445 ((type == RXDONE_SIGNAL_BITRATE) && 520 signal = RATE_MCS(rxdesc->rate_mode, signal);
446 (rate->bitrate == signal)) || 521
447 ((type == RXDONE_SIGNAL_MCS) && 522 sband = &rt2x00dev->bands[rt2x00dev->curr_band];
448 (rate->mcs == signal))) { 523 for (i = 0; i < sband->n_bitrates; i++) {
449 return i; 524 rate = rt2x00_get_rate(sband->bitrates[i].hw_value);
525 if (((type == RXDONE_SIGNAL_PLCP) &&
526 (rate->plcp == signal)) ||
527 ((type == RXDONE_SIGNAL_BITRATE) &&
528 (rate->bitrate == signal)) ||
529 ((type == RXDONE_SIGNAL_MCS) &&
530 (rate->mcs == signal))) {
531 return i;
532 }
450 } 533 }
534 break;
535 case RATE_MODE_HT_MIX:
536 case RATE_MODE_HT_GREENFIELD:
537 if (signal >= 0 && signal <= 76)
538 return signal;
539 break;
540 default:
541 break;
451 } 542 }
452 543
453 WARNING(rt2x00dev, "Frame received with unrecognized signal, " 544 WARNING(rt2x00dev, "Frame received with unrecognized signal, "
454 "signal=0x%.4x, type=%d.\n", signal, type); 545 "mode=0x%.4x, signal=0x%.4x, type=%d.\n",
546 rxdesc->rate_mode, signal, type);
455 return 0; 547 return 0;
456} 548}
457 549
458void rt2x00lib_rxdone(struct rt2x00_dev *rt2x00dev, 550void rt2x00lib_rxdone(struct queue_entry *entry)
459 struct queue_entry *entry)
460{ 551{
552 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
461 struct rxdone_entry_desc rxdesc; 553 struct rxdone_entry_desc rxdesc;
462 struct sk_buff *skb; 554 struct sk_buff *skb;
463 struct ieee80211_rx_status *rx_status = &rt2x00dev->rx_status; 555 struct ieee80211_rx_status *rx_status;
464 unsigned int header_length; 556 unsigned int header_length;
465 int rate_idx; 557 int rate_idx;
558
559 if (!test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags) ||
560 !test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
561 goto submit_entry;
562
563 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags))
564 goto submit_entry;
565
466 /* 566 /*
467 * Allocate a new sk_buffer. If no new buffer available, drop the 567 * Allocate a new sk_buffer. If no new buffer available, drop the
468 * received frame and reuse the existing buffer. 568 * received frame and reuse the existing buffer.
469 */ 569 */
470 skb = rt2x00queue_alloc_rxskb(rt2x00dev, entry); 570 skb = rt2x00queue_alloc_rxskb(entry);
471 if (!skb) 571 if (!skb)
472 return; 572 goto submit_entry;
473 573
474 /* 574 /*
475 * Unmap the skb. 575 * Unmap the skb.
476 */ 576 */
477 rt2x00queue_unmap_skb(rt2x00dev, entry->skb); 577 rt2x00queue_unmap_skb(entry);
478 578
479 /* 579 /*
480 * Extract the RXD details. 580 * Extract the RXD details.
@@ -502,64 +602,57 @@ void rt2x00lib_rxdone(struct rt2x00_dev *rt2x00dev,
502 (rxdesc.size > header_length) && 602 (rxdesc.size > header_length) &&
503 (rxdesc.dev_flags & RXDONE_L2PAD)) 603 (rxdesc.dev_flags & RXDONE_L2PAD))
504 rt2x00queue_remove_l2pad(entry->skb, header_length); 604 rt2x00queue_remove_l2pad(entry->skb, header_length);
505 else
506 rt2x00queue_align_payload(entry->skb, header_length);
507 605
508 /* Trim buffer to correct size */ 606 /* Trim buffer to correct size */
509 skb_trim(entry->skb, rxdesc.size); 607 skb_trim(entry->skb, rxdesc.size);
510 608
511 /* 609 /*
512 * Check if the frame was received using HT. In that case, 610 * Translate the signal to the correct bitrate index.
513 * the rate is the MCS index and should be passed to mac80211
514 * directly. Otherwise we need to translate the signal to
515 * the correct bitrate index.
516 */ 611 */
517 if (rxdesc.rate_mode == RATE_MODE_CCK || 612 rate_idx = rt2x00lib_rxdone_read_signal(rt2x00dev, &rxdesc);
518 rxdesc.rate_mode == RATE_MODE_OFDM) { 613 if (rxdesc.rate_mode == RATE_MODE_HT_MIX ||
519 rate_idx = rt2x00lib_rxdone_read_signal(rt2x00dev, &rxdesc); 614 rxdesc.rate_mode == RATE_MODE_HT_GREENFIELD)
520 } else {
521 rxdesc.flags |= RX_FLAG_HT; 615 rxdesc.flags |= RX_FLAG_HT;
522 rate_idx = rxdesc.signal; 616
523 } 617 /*
618 * Check if this is a beacon, and more frames have been
619 * buffered while we were in powersaving mode.
620 */
621 rt2x00lib_rxdone_check_ps(rt2x00dev, entry->skb, &rxdesc);
524 622
525 /* 623 /*
526 * Update extra components 624 * Update extra components
527 */ 625 */
528 rt2x00link_update_stats(rt2x00dev, entry->skb, &rxdesc); 626 rt2x00link_update_stats(rt2x00dev, entry->skb, &rxdesc);
529 rt2x00debug_update_crypto(rt2x00dev, &rxdesc); 627 rt2x00debug_update_crypto(rt2x00dev, &rxdesc);
628 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_RXDONE, entry->skb);
530 629
630 /*
631 * Initialize RX status information, and send frame
632 * to mac80211.
633 */
634 rx_status = IEEE80211_SKB_RXCB(entry->skb);
531 rx_status->mactime = rxdesc.timestamp; 635 rx_status->mactime = rxdesc.timestamp;
636 rx_status->band = rt2x00dev->curr_band;
637 rx_status->freq = rt2x00dev->curr_freq;
532 rx_status->rate_idx = rate_idx; 638 rx_status->rate_idx = rate_idx;
533 rx_status->signal = rxdesc.rssi; 639 rx_status->signal = rxdesc.rssi;
534 rx_status->flag = rxdesc.flags; 640 rx_status->flag = rxdesc.flags;
535 rx_status->antenna = rt2x00dev->link.ant.active.rx; 641 rx_status->antenna = rt2x00dev->link.ant.active.rx;
536 642
537 /* 643 ieee80211_rx_ni(rt2x00dev->hw, entry->skb);
538 * Send frame to mac80211 & debugfs.
539 * mac80211 will clean up the skb structure.
540 */
541 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_RXDONE, entry->skb);
542 memcpy(IEEE80211_SKB_RXCB(entry->skb), rx_status, sizeof(*rx_status));
543
544 /*
545 * Currently only PCI and SOC devices handle rx interrupts in process
546 * context. Hence, use ieee80211_rx_irqsafe for USB and ieee80211_rx_ni
547 * for PCI and SOC devices.
548 */
549 if (rt2x00_is_usb(rt2x00dev))
550 ieee80211_rx_irqsafe(rt2x00dev->hw, entry->skb);
551 else
552 ieee80211_rx_ni(rt2x00dev->hw, entry->skb);
553 644
554 /* 645 /*
555 * Replace the skb with the freshly allocated one. 646 * Replace the skb with the freshly allocated one.
556 */ 647 */
557 entry->skb = skb; 648 entry->skb = skb;
558 entry->flags = 0;
559
560 rt2x00dev->ops->lib->clear_entry(entry);
561 649
562 rt2x00queue_index_inc(entry->queue, Q_INDEX); 650submit_entry:
651 entry->flags = 0;
652 rt2x00queue_index_inc(entry, Q_INDEX_DONE);
653 if (test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags) &&
654 test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
655 rt2x00dev->ops->lib->clear_entry(entry);
563} 656}
564EXPORT_SYMBOL_GPL(rt2x00lib_rxdone); 657EXPORT_SYMBOL_GPL(rt2x00lib_rxdone);
565 658
@@ -657,7 +750,10 @@ static void rt2x00lib_channel(struct ieee80211_channel *entry,
657 const int channel, const int tx_power, 750 const int channel, const int tx_power,
658 const int value) 751 const int value)
659{ 752{
660 entry->center_freq = ieee80211_channel_to_frequency(channel); 753 /* XXX: this assumption about the band is wrong for 802.11j */
754 entry->band = channel <= 14 ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
755 entry->center_freq = ieee80211_channel_to_frequency(channel,
756 entry->band);
661 entry->hw_value = value; 757 entry->hw_value = value;
662 entry->max_power = tx_power; 758 entry->max_power = tx_power;
663 entry->max_antenna_gain = 0xff; 759 entry->max_antenna_gain = 0xff;
@@ -668,7 +764,7 @@ static void rt2x00lib_rate(struct ieee80211_rate *entry,
668{ 764{
669 entry->flags = 0; 765 entry->flags = 0;
670 entry->bitrate = rate->bitrate; 766 entry->bitrate = rate->bitrate;
671 entry->hw_value =index; 767 entry->hw_value = index;
672 entry->hw_value_short = index; 768 entry->hw_value_short = index;
673 769
674 if (rate->flags & DEV_RATE_SHORT_PREAMBLE) 770 if (rate->flags & DEV_RATE_SHORT_PREAMBLE)
@@ -710,7 +806,7 @@ static int rt2x00lib_probe_hw_modes(struct rt2x00_dev *rt2x00dev,
710 for (i = 0; i < spec->num_channels; i++) { 806 for (i = 0; i < spec->num_channels; i++) {
711 rt2x00lib_channel(&channels[i], 807 rt2x00lib_channel(&channels[i],
712 spec->channels[i].channel, 808 spec->channels[i].channel,
713 spec->channels_info[i].tx_power1, i); 809 spec->channels_info[i].max_power, i);
714 } 810 }
715 811
716 /* 812 /*
@@ -800,12 +896,55 @@ static int rt2x00lib_probe_hw(struct rt2x00_dev *rt2x00dev)
800 /* 896 /*
801 * Take TX headroom required for alignment into account. 897 * Take TX headroom required for alignment into account.
802 */ 898 */
803 if (test_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags)) 899 if (test_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags))
804 rt2x00dev->hw->extra_tx_headroom += RT2X00_L2PAD_SIZE; 900 rt2x00dev->hw->extra_tx_headroom += RT2X00_L2PAD_SIZE;
805 else if (test_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags)) 901 else if (test_bit(REQUIRE_DMA, &rt2x00dev->cap_flags))
806 rt2x00dev->hw->extra_tx_headroom += RT2X00_ALIGN_SIZE; 902 rt2x00dev->hw->extra_tx_headroom += RT2X00_ALIGN_SIZE;
807 903
808 /* 904 /*
905 * Allocate tx status FIFO for driver use.
906 */
907 if (test_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags)) {
908 /*
909 * Allocate the txstatus fifo. In the worst case the tx
910 * status fifo has to hold the tx status of all entries
911 * in all tx queues. Hence, calculate the kfifo size as
912 * tx_queues * entry_num and round up to the nearest
913 * power of 2.
914 */
915 int kfifo_size =
916 roundup_pow_of_two(rt2x00dev->ops->tx_queues *
917 rt2x00dev->ops->tx->entry_num *
918 sizeof(u32));
919
920 status = kfifo_alloc(&rt2x00dev->txstatus_fifo, kfifo_size,
921 GFP_KERNEL);
922 if (status)
923 return status;
924 }
925
926 /*
927 * Initialize tasklets if used by the driver. Tasklets are
928 * disabled until the interrupts are turned on. The driver
929 * has to handle that.
930 */
931#define RT2X00_TASKLET_INIT(taskletname) \
932 if (rt2x00dev->ops->lib->taskletname) { \
933 tasklet_init(&rt2x00dev->taskletname, \
934 rt2x00dev->ops->lib->taskletname, \
935 (unsigned long)rt2x00dev); \
936 tasklet_disable(&rt2x00dev->taskletname); \
937 }
938
939 RT2X00_TASKLET_INIT(txstatus_tasklet);
940 RT2X00_TASKLET_INIT(pretbtt_tasklet);
941 RT2X00_TASKLET_INIT(tbtt_tasklet);
942 RT2X00_TASKLET_INIT(rxdone_tasklet);
943 RT2X00_TASKLET_INIT(autowake_tasklet);
944
945#undef RT2X00_TASKLET_INIT
946
947 /*
809 * Register HW. 948 * Register HW.
810 */ 949 */
811 status = ieee80211_register_hw(rt2x00dev->hw); 950 status = ieee80211_register_hw(rt2x00dev->hw);
@@ -902,10 +1041,8 @@ int rt2x00lib_start(struct rt2x00_dev *rt2x00dev)
902 1041
903 /* Enable the radio */ 1042 /* Enable the radio */
904 retval = rt2x00lib_enable_radio(rt2x00dev); 1043 retval = rt2x00lib_enable_radio(rt2x00dev);
905 if (retval) { 1044 if (retval)
906 rt2x00queue_uninitialize(rt2x00dev);
907 return retval; 1045 return retval;
908 }
909 1046
910 set_bit(DEVICE_STATE_STARTED, &rt2x00dev->flags); 1047 set_bit(DEVICE_STATE_STARTED, &rt2x00dev->flags);
911 1048
@@ -935,6 +1072,7 @@ int rt2x00lib_probe_dev(struct rt2x00_dev *rt2x00dev)
935{ 1072{
936 int retval = -ENOMEM; 1073 int retval = -ENOMEM;
937 1074
1075 spin_lock_init(&rt2x00dev->irqmask_lock);
938 mutex_init(&rt2x00dev->csr_mutex); 1076 mutex_init(&rt2x00dev->csr_mutex);
939 1077
940 set_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags); 1078 set_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags);
@@ -959,9 +1097,17 @@ int rt2x00lib_probe_dev(struct rt2x00_dev *rt2x00dev)
959 BIT(NL80211_IFTYPE_WDS); 1097 BIT(NL80211_IFTYPE_WDS);
960 1098
961 /* 1099 /*
962 * Initialize configuration work. 1100 * Initialize work.
963 */ 1101 */
1102 rt2x00dev->workqueue =
1103 alloc_ordered_workqueue(wiphy_name(rt2x00dev->hw->wiphy), 0);
1104 if (!rt2x00dev->workqueue) {
1105 retval = -ENOMEM;
1106 goto exit;
1107 }
1108
964 INIT_WORK(&rt2x00dev->intf_work, rt2x00lib_intf_scheduled); 1109 INIT_WORK(&rt2x00dev->intf_work, rt2x00lib_intf_scheduled);
1110 INIT_DELAYED_WORK(&rt2x00dev->autowakeup_work, rt2x00lib_autowakeup);
965 1111
966 /* 1112 /*
967 * Let the driver probe the device to detect the capabilities. 1113 * Let the driver probe the device to detect the capabilities.
@@ -1017,6 +1163,27 @@ void rt2x00lib_remove_dev(struct rt2x00_dev *rt2x00dev)
1017 * Stop all work. 1163 * Stop all work.
1018 */ 1164 */
1019 cancel_work_sync(&rt2x00dev->intf_work); 1165 cancel_work_sync(&rt2x00dev->intf_work);
1166 cancel_delayed_work_sync(&rt2x00dev->autowakeup_work);
1167 if (rt2x00_is_usb(rt2x00dev)) {
1168 del_timer_sync(&rt2x00dev->txstatus_timer);
1169 cancel_work_sync(&rt2x00dev->rxdone_work);
1170 cancel_work_sync(&rt2x00dev->txdone_work);
1171 }
1172 destroy_workqueue(rt2x00dev->workqueue);
1173
1174 /*
1175 * Free the tx status fifo.
1176 */
1177 kfifo_free(&rt2x00dev->txstatus_fifo);
1178
1179 /*
1180 * Kill the tx status tasklet.
1181 */
1182 tasklet_kill(&rt2x00dev->txstatus_tasklet);
1183 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
1184 tasklet_kill(&rt2x00dev->tbtt_tasklet);
1185 tasklet_kill(&rt2x00dev->rxdone_tasklet);
1186 tasklet_kill(&rt2x00dev->autowake_tasklet);
1020 1187
1021 /* 1188 /*
1022 * Uninitialize device. 1189 * Uninitialize device.
diff --git a/drivers/net/wireless/rt2x00/rt2x00dump.h b/drivers/net/wireless/rt2x00/rt2x00dump.h
index 5d6e0b83151f..063ebcce97f8 100644
--- a/drivers/net/wireless/rt2x00/rt2x00dump.h
+++ b/drivers/net/wireless/rt2x00/rt2x00dump.h
@@ -51,7 +51,7 @@
51 * [rt2x00dump header][hardware descriptor][ieee802.11 frame] 51 * [rt2x00dump header][hardware descriptor][ieee802.11 frame]
52 * 52 *
53 * rt2x00dump header: The description of the dumped frame, as well as 53 * rt2x00dump header: The description of the dumped frame, as well as
54 * additional information usefull for debugging. See &rt2x00dump_hdr. 54 * additional information useful for debugging. See &rt2x00dump_hdr.
55 * hardware descriptor: Descriptor that was used to receive or transmit 55 * hardware descriptor: Descriptor that was used to receive or transmit
56 * the frame. 56 * the frame.
57 * ieee802.11 frame: The actual frame that was received or transmitted. 57 * ieee802.11 frame: The actual frame that was received or transmitted.
diff --git a/drivers/net/wireless/rt2x00/rt2x00firmware.c b/drivers/net/wireless/rt2x00/rt2x00firmware.c
index b818a43c4672..f316aad30612 100644
--- a/drivers/net/wireless/rt2x00/rt2x00firmware.c
+++ b/drivers/net/wireless/rt2x00/rt2x00firmware.c
@@ -58,11 +58,15 @@ static int rt2x00lib_request_firmware(struct rt2x00_dev *rt2x00dev)
58 58
59 if (!fw || !fw->size || !fw->data) { 59 if (!fw || !fw->size || !fw->data) {
60 ERROR(rt2x00dev, "Failed to read Firmware.\n"); 60 ERROR(rt2x00dev, "Failed to read Firmware.\n");
61 release_firmware(fw);
61 return -ENOENT; 62 return -ENOENT;
62 } 63 }
63 64
64 INFO(rt2x00dev, "Firmware detected - version: %d.%d.\n", 65 INFO(rt2x00dev, "Firmware detected - version: %d.%d.\n",
65 fw->data[fw->size - 4], fw->data[fw->size - 3]); 66 fw->data[fw->size - 4], fw->data[fw->size - 3]);
67 snprintf(rt2x00dev->hw->wiphy->fw_version,
68 sizeof(rt2x00dev->hw->wiphy->fw_version), "%d.%d",
69 fw->data[fw->size - 4], fw->data[fw->size - 3]);
66 70
67 retval = rt2x00dev->ops->lib->check_firmware(rt2x00dev, fw->data, fw->size); 71 retval = rt2x00dev->ops->lib->check_firmware(rt2x00dev, fw->data, fw->size);
68 switch (retval) { 72 switch (retval) {
@@ -95,7 +99,7 @@ int rt2x00lib_load_firmware(struct rt2x00_dev *rt2x00dev)
95{ 99{
96 int retval; 100 int retval;
97 101
98 if (!test_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags)) 102 if (!test_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags))
99 return 0; 103 return 0;
100 104
101 if (!rt2x00dev->fw) { 105 if (!rt2x00dev->fw) {
diff --git a/drivers/net/wireless/rt2x00/rt2x00ht.c b/drivers/net/wireless/rt2x00/rt2x00ht.c
deleted file mode 100644
index c004cd3a8847..000000000000
--- a/drivers/net/wireless/rt2x00/rt2x00ht.c
+++ /dev/null
@@ -1,125 +0,0 @@
1/*
2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2x00lib
23 Abstract: rt2x00 HT specific routines.
24 */
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28
29#include "rt2x00.h"
30#include "rt2x00lib.h"
31
32void rt2x00ht_create_tx_descriptor(struct queue_entry *entry,
33 struct txentry_desc *txdesc,
34 const struct rt2x00_rate *hwrate)
35{
36 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
37 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
38 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
39
40 if (tx_info->control.sta)
41 txdesc->mpdu_density =
42 tx_info->control.sta->ht_cap.ampdu_density;
43 else
44 txdesc->mpdu_density = 0;
45
46 txdesc->ba_size = 7; /* FIXME: What value is needed? */
47
48 txdesc->stbc =
49 (tx_info->flags & IEEE80211_TX_CTL_STBC) >> IEEE80211_TX_CTL_STBC_SHIFT;
50
51 /*
52 * If IEEE80211_TX_RC_MCS is set txrate->idx just contains the
53 * mcs rate to be used
54 */
55 if (txrate->flags & IEEE80211_TX_RC_MCS) {
56 txdesc->mcs = txrate->idx;
57 } else {
58 txdesc->mcs = rt2x00_get_rate_mcs(hwrate->mcs);
59 if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
60 txdesc->mcs |= 0x08;
61 }
62
63
64 /*
65 * Convert flags
66 */
67 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
68 __set_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags);
69
70 /*
71 * Determine HT Mix/Greenfield rate mode
72 */
73 if (txrate->flags & IEEE80211_TX_RC_MCS)
74 txdesc->rate_mode = RATE_MODE_HT_MIX;
75 if (txrate->flags & IEEE80211_TX_RC_GREEN_FIELD)
76 txdesc->rate_mode = RATE_MODE_HT_GREENFIELD;
77 if (txrate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
78 __set_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags);
79 if (txrate->flags & IEEE80211_TX_RC_SHORT_GI)
80 __set_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags);
81
82 /*
83 * Determine IFS values
84 * - Use TXOP_BACKOFF for management frames
85 * - Use TXOP_SIFS for fragment bursts
86 * - Use TXOP_HTTXOP for everything else
87 *
88 * Note: rt2800 devices won't use CTS protection (if used)
89 * for frames not transmitted with TXOP_HTTXOP
90 */
91 if (ieee80211_is_mgmt(hdr->frame_control))
92 txdesc->txop = TXOP_BACKOFF;
93 else if (!(tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT))
94 txdesc->txop = TXOP_SIFS;
95 else
96 txdesc->txop = TXOP_HTTXOP;
97}
98
99u16 rt2x00ht_center_channel(struct rt2x00_dev *rt2x00dev,
100 struct ieee80211_conf *conf)
101{
102 struct hw_mode_spec *spec = &rt2x00dev->spec;
103 int center_channel;
104 u16 i;
105
106 /*
107 * Initialize center channel to current channel.
108 */
109 center_channel = spec->channels[conf->channel->hw_value].channel;
110
111 /*
112 * Adjust center channel to HT40+ and HT40- operation.
113 */
114 if (conf_is_ht40_plus(conf))
115 center_channel += 2;
116 else if (conf_is_ht40_minus(conf))
117 center_channel -= (center_channel == 14) ? 1 : 2;
118
119 for (i = 0; i < spec->num_channels; i++)
120 if (spec->channels[i].channel == center_channel)
121 return i;
122
123 WARN_ON(1);
124 return conf->channel->hw_value;
125}
diff --git a/drivers/net/wireless/rt2x00/rt2x00lib.h b/drivers/net/wireless/rt2x00/rt2x00lib.h
index dc5c6574aaf4..322cc4f3de5d 100644
--- a/drivers/net/wireless/rt2x00/rt2x00lib.h
+++ b/drivers/net/wireless/rt2x00/rt2x00lib.h
@@ -32,6 +32,7 @@
32 */ 32 */
33#define WATCHDOG_INTERVAL round_jiffies_relative(HZ) 33#define WATCHDOG_INTERVAL round_jiffies_relative(HZ)
34#define LINK_TUNE_INTERVAL round_jiffies_relative(HZ) 34#define LINK_TUNE_INTERVAL round_jiffies_relative(HZ)
35#define AGC_INTERVAL round_jiffies_relative(4 * HZ)
35 36
36/* 37/*
37 * rt2x00_rate: Per rate device information 38 * rt2x00_rate: Per rate device information
@@ -57,7 +58,7 @@ static inline const struct rt2x00_rate *rt2x00_get_rate(const u16 hw_value)
57} 58}
58 59
59#define RATE_MCS(__mode, __mcs) \ 60#define RATE_MCS(__mode, __mcs) \
60 ( (((__mode) & 0x00ff) << 8) | ((__mcs) & 0x00ff) ) 61 ((((__mode) & 0x00ff) << 8) | ((__mcs) & 0x00ff))
61 62
62static inline int rt2x00_get_rate_mcs(const u16 mcs_value) 63static inline int rt2x00_get_rate_mcs(const u16 mcs_value)
63{ 64{
@@ -69,7 +70,6 @@ static inline int rt2x00_get_rate_mcs(const u16 mcs_value)
69 */ 70 */
70int rt2x00lib_enable_radio(struct rt2x00_dev *rt2x00dev); 71int rt2x00lib_enable_radio(struct rt2x00_dev *rt2x00dev);
71void rt2x00lib_disable_radio(struct rt2x00_dev *rt2x00dev); 72void rt2x00lib_disable_radio(struct rt2x00_dev *rt2x00dev);
72void rt2x00lib_toggle_rx(struct rt2x00_dev *rt2x00dev, enum dev_state state);
73 73
74/* 74/*
75 * Initialization handlers. 75 * Initialization handlers.
@@ -86,7 +86,8 @@ void rt2x00lib_config_intf(struct rt2x00_dev *rt2x00dev,
86 const u8 *mac, const u8 *bssid); 86 const u8 *mac, const u8 *bssid);
87void rt2x00lib_config_erp(struct rt2x00_dev *rt2x00dev, 87void rt2x00lib_config_erp(struct rt2x00_dev *rt2x00dev,
88 struct rt2x00_intf *intf, 88 struct rt2x00_intf *intf,
89 struct ieee80211_bss_conf *conf); 89 struct ieee80211_bss_conf *conf,
90 u32 changed);
90void rt2x00lib_config_antenna(struct rt2x00_dev *rt2x00dev, 91void rt2x00lib_config_antenna(struct rt2x00_dev *rt2x00dev,
91 struct antenna_setup ant); 92 struct antenna_setup ant);
92void rt2x00lib_config(struct rt2x00_dev *rt2x00dev, 93void rt2x00lib_config(struct rt2x00_dev *rt2x00dev,
@@ -99,18 +100,15 @@ void rt2x00lib_config(struct rt2x00_dev *rt2x00dev,
99 100
100/** 101/**
101 * rt2x00queue_alloc_rxskb - allocate a skb for RX purposes. 102 * rt2x00queue_alloc_rxskb - allocate a skb for RX purposes.
102 * @rt2x00dev: Pointer to &struct rt2x00_dev. 103 * @entry: The entry for which the skb will be applicable.
103 * @queue: The queue for which the skb will be applicable.
104 */ 104 */
105struct sk_buff *rt2x00queue_alloc_rxskb(struct rt2x00_dev *rt2x00dev, 105struct sk_buff *rt2x00queue_alloc_rxskb(struct queue_entry *entry);
106 struct queue_entry *entry);
107 106
108/** 107/**
109 * rt2x00queue_free_skb - free a skb 108 * rt2x00queue_free_skb - free a skb
110 * @rt2x00dev: Pointer to &struct rt2x00_dev. 109 * @entry: The entry for which the skb will be applicable.
111 * @skb: The skb to free.
112 */ 110 */
113void rt2x00queue_free_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb); 111void rt2x00queue_free_skb(struct queue_entry *entry);
114 112
115/** 113/**
116 * rt2x00queue_align_frame - Align 802.11 frame to 4-byte boundary 114 * rt2x00queue_align_frame - Align 802.11 frame to 4-byte boundary
@@ -122,16 +120,6 @@ void rt2x00queue_free_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb);
122void rt2x00queue_align_frame(struct sk_buff *skb); 120void rt2x00queue_align_frame(struct sk_buff *skb);
123 121
124/** 122/**
125 * rt2x00queue_align_payload - Align 802.11 payload to 4-byte boundary
126 * @skb: The skb to align
127 * @header_length: Length of 802.11 header
128 *
129 * Align the 802.11 payload to a 4-byte boundary, this could
130 * mean the header is not aligned properly though.
131 */
132void rt2x00queue_align_payload(struct sk_buff *skb, unsigned int header_length);
133
134/**
135 * rt2x00queue_insert_l2pad - Align 802.11 header & payload to 4-byte boundary 123 * rt2x00queue_insert_l2pad - Align 802.11 header & payload to 4-byte boundary
136 * @skb: The skb to align 124 * @skb: The skb to align
137 * @header_length: Length of 802.11 header 125 * @header_length: Length of 802.11 header
@@ -160,34 +148,41 @@ int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
160 bool local); 148 bool local);
161 149
162/** 150/**
163 * rt2x00queue_update_beacon - Send new beacon from mac80211 to hardware 151 * rt2x00queue_update_beacon - Send new beacon from mac80211
152 * to hardware. Handles locking by itself (mutex).
164 * @rt2x00dev: Pointer to &struct rt2x00_dev. 153 * @rt2x00dev: Pointer to &struct rt2x00_dev.
165 * @vif: Interface for which the beacon should be updated. 154 * @vif: Interface for which the beacon should be updated.
166 * @enable_beacon: Enable beaconing
167 */ 155 */
168int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev, 156int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
169 struct ieee80211_vif *vif, 157 struct ieee80211_vif *vif);
170 const bool enable_beacon);
171 158
172/** 159/**
173 * rt2x00queue_index_inc - Index incrementation function 160 * rt2x00queue_update_beacon_locked - Send new beacon from mac80211
174 * @queue: Queue (&struct data_queue) to perform the action on. 161 * to hardware. Caller needs to ensure locking.
175 * @index: Index type (&enum queue_index) to perform the action on. 162 * @rt2x00dev: Pointer to &struct rt2x00_dev.
176 * 163 * @vif: Interface for which the beacon should be updated.
177 * This function will increase the requested index on the queue,
178 * it will grab the appropriate locks and handle queue overflow events by
179 * resetting the index to the start of the queue.
180 */ 164 */
181void rt2x00queue_index_inc(struct data_queue *queue, enum queue_index index); 165int rt2x00queue_update_beacon_locked(struct rt2x00_dev *rt2x00dev,
166 struct ieee80211_vif *vif);
182 167
183/** 168/**
184 * rt2x00queue_stop_queues - Halt all data queues 169 * rt2x00queue_clear_beacon - Clear beacon in hardware
185 * @rt2x00dev: Pointer to &struct rt2x00_dev. 170 * @rt2x00dev: Pointer to &struct rt2x00_dev.
171 * @vif: Interface for which the beacon should be updated.
172 */
173int rt2x00queue_clear_beacon(struct rt2x00_dev *rt2x00dev,
174 struct ieee80211_vif *vif);
175
176/**
177 * rt2x00queue_index_inc - Index incrementation function
178 * @entry: Queue entry (&struct queue_entry) to perform the action on.
179 * @index: Index type (&enum queue_index) to perform the action on.
186 * 180 *
187 * This function will loop through all available queues to stop 181 * This function will increase the requested index on the entry's queue,
188 * any pending outgoing frames. 182 * it will grab the appropriate locks and handle queue overflow events by
183 * resetting the index to the start of the queue.
189 */ 184 */
190void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev); 185void rt2x00queue_index_inc(struct queue_entry *entry, enum queue_index index);
191 186
192/** 187/**
193 * rt2x00queue_init_queues - Initialize all data queues 188 * rt2x00queue_init_queues - Initialize all data queues
@@ -277,6 +272,18 @@ void rt2x00link_start_watchdog(struct rt2x00_dev *rt2x00dev);
277void rt2x00link_stop_watchdog(struct rt2x00_dev *rt2x00dev); 272void rt2x00link_stop_watchdog(struct rt2x00_dev *rt2x00dev);
278 273
279/** 274/**
275 * rt2x00link_start_agc - Start periodic gain calibration
276 * @rt2x00dev: Pointer to &struct rt2x00_dev.
277 */
278void rt2x00link_start_agc(struct rt2x00_dev *rt2x00dev);
279
280/**
281 * rt2x00link_stop_agc - Stop periodic gain calibration
282 * @rt2x00dev: Pointer to &struct rt2x00_dev.
283 */
284void rt2x00link_stop_agc(struct rt2x00_dev *rt2x00dev);
285
286/**
280 * rt2x00link_register - Initialize link tuning & watchdog functionality 287 * rt2x00link_register - Initialize link tuning & watchdog functionality
281 * @rt2x00dev: Pointer to &struct rt2x00_dev. 288 * @rt2x00dev: Pointer to &struct rt2x00_dev.
282 * 289 *
@@ -381,41 +388,17 @@ static inline void rt2x00crypto_rx_insert_iv(struct sk_buff *skb,
381#endif /* CONFIG_RT2X00_LIB_CRYPTO */ 388#endif /* CONFIG_RT2X00_LIB_CRYPTO */
382 389
383/* 390/*
384 * HT handlers.
385 */
386#ifdef CONFIG_RT2X00_LIB_HT
387void rt2x00ht_create_tx_descriptor(struct queue_entry *entry,
388 struct txentry_desc *txdesc,
389 const struct rt2x00_rate *hwrate);
390
391u16 rt2x00ht_center_channel(struct rt2x00_dev *rt2x00dev,
392 struct ieee80211_conf *conf);
393#else
394static inline void rt2x00ht_create_tx_descriptor(struct queue_entry *entry,
395 struct txentry_desc *txdesc,
396 const struct rt2x00_rate *hwrate)
397{
398}
399
400static inline u16 rt2x00ht_center_channel(struct rt2x00_dev *rt2x00dev,
401 struct ieee80211_conf *conf)
402{
403 return conf->channel->hw_value;
404}
405#endif /* CONFIG_RT2X00_LIB_HT */
406
407/*
408 * RFkill handlers. 391 * RFkill handlers.
409 */ 392 */
410static inline void rt2x00rfkill_register(struct rt2x00_dev *rt2x00dev) 393static inline void rt2x00rfkill_register(struct rt2x00_dev *rt2x00dev)
411{ 394{
412 if (test_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags)) 395 if (test_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags))
413 wiphy_rfkill_start_polling(rt2x00dev->hw->wiphy); 396 wiphy_rfkill_start_polling(rt2x00dev->hw->wiphy);
414} 397}
415 398
416static inline void rt2x00rfkill_unregister(struct rt2x00_dev *rt2x00dev) 399static inline void rt2x00rfkill_unregister(struct rt2x00_dev *rt2x00dev)
417{ 400{
418 if (test_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags)) 401 if (test_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags))
419 wiphy_rfkill_stop_polling(rt2x00dev->hw->wiphy); 402 wiphy_rfkill_stop_polling(rt2x00dev->hw->wiphy);
420} 403}
421 404
diff --git a/drivers/net/wireless/rt2x00/rt2x00link.c b/drivers/net/wireless/rt2x00/rt2x00link.c
index 666cef3f8472..ea10b0068f82 100644
--- a/drivers/net/wireless/rt2x00/rt2x00link.c
+++ b/drivers/net/wireless/rt2x00/rt2x00link.c
@@ -67,7 +67,7 @@
67 (__avg).avg_weight ? \ 67 (__avg).avg_weight ? \
68 ((((__avg).avg_weight * ((AVG_SAMPLES) - 1)) + \ 68 ((((__avg).avg_weight * ((AVG_SAMPLES) - 1)) + \
69 ((__val) * (AVG_FACTOR))) / \ 69 ((__val) * (AVG_FACTOR))) / \
70 (AVG_SAMPLES) ) : \ 70 (AVG_SAMPLES)) : \
71 ((__val) * (AVG_FACTOR)); \ 71 ((__val) * (AVG_FACTOR)); \
72 __new.avg = __new.avg_weight / (AVG_FACTOR); \ 72 __new.avg = __new.avg_weight / (AVG_FACTOR); \
73 __new; \ 73 __new; \
@@ -188,31 +188,17 @@ static void rt2x00lib_antenna_diversity_eval(struct rt2x00_dev *rt2x00dev)
188static bool rt2x00lib_antenna_diversity(struct rt2x00_dev *rt2x00dev) 188static bool rt2x00lib_antenna_diversity(struct rt2x00_dev *rt2x00dev)
189{ 189{
190 struct link_ant *ant = &rt2x00dev->link.ant; 190 struct link_ant *ant = &rt2x00dev->link.ant;
191 unsigned int flags = ant->flags;
192 191
193 /* 192 /*
194 * Determine if software diversity is enabled for 193 * Determine if software diversity is enabled for
195 * either the TX or RX antenna (or both). 194 * either the TX or RX antenna (or both).
196 * Always perform this check since within the link
197 * tuner interval the configuration might have changed.
198 */ 195 */
199 flags &= ~ANTENNA_RX_DIVERSITY;
200 flags &= ~ANTENNA_TX_DIVERSITY;
201
202 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
203 flags |= ANTENNA_RX_DIVERSITY;
204 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
205 flags |= ANTENNA_TX_DIVERSITY;
206
207 if (!(ant->flags & ANTENNA_RX_DIVERSITY) && 196 if (!(ant->flags & ANTENNA_RX_DIVERSITY) &&
208 !(ant->flags & ANTENNA_TX_DIVERSITY)) { 197 !(ant->flags & ANTENNA_TX_DIVERSITY)) {
209 ant->flags = 0; 198 ant->flags = 0;
210 return true; 199 return true;
211 } 200 }
212 201
213 /* Update flags */
214 ant->flags = flags;
215
216 /* 202 /*
217 * If we have only sampled the data over the last period 203 * If we have only sampled the data over the last period
218 * we should now harvest the data. Otherwise just evaluate 204 * we should now harvest the data. Otherwise just evaluate
@@ -240,6 +226,12 @@ void rt2x00link_update_stats(struct rt2x00_dev *rt2x00dev,
240 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 226 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
241 227
242 /* 228 /*
229 * No need to update the stats for !=STA interfaces
230 */
231 if (!rt2x00dev->intf_sta_count)
232 return;
233
234 /*
243 * Frame was received successfully since non-succesfull 235 * Frame was received successfully since non-succesfull
244 * frames would have been dropped by the hardware. 236 * frames would have been dropped by the hardware.
245 */ 237 */
@@ -281,7 +273,7 @@ void rt2x00link_start_tuner(struct rt2x00_dev *rt2x00dev)
281 /** 273 /**
282 * While scanning, link tuning is disabled. By default 274 * While scanning, link tuning is disabled. By default
283 * the most sensitive settings will be used to make sure 275 * the most sensitive settings will be used to make sure
284 * that all beacons and probe responses will be recieved 276 * that all beacons and probe responses will be received
285 * during the scan. 277 * during the scan.
286 */ 278 */
287 if (test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) 279 if (test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags))
@@ -381,7 +373,7 @@ static void rt2x00link_tuner(struct work_struct *work)
381 * do not support link tuning at all, while other devices can disable 373 * do not support link tuning at all, while other devices can disable
382 * the feature from the EEPROM. 374 * the feature from the EEPROM.
383 */ 375 */
384 if (test_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags)) 376 if (test_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags))
385 rt2x00dev->ops->lib->link_tuner(rt2x00dev, qual, link->count); 377 rt2x00dev->ops->lib->link_tuner(rt2x00dev, qual, link->count);
386 378
387 /* 379 /*
@@ -411,12 +403,11 @@ void rt2x00link_start_watchdog(struct rt2x00_dev *rt2x00dev)
411{ 403{
412 struct link *link = &rt2x00dev->link; 404 struct link *link = &rt2x00dev->link;
413 405
414 if (!test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags) || 406 if (test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags) &&
415 !test_bit(DRIVER_SUPPORT_WATCHDOG, &rt2x00dev->flags)) 407 rt2x00dev->ops->lib->watchdog)
416 return; 408 ieee80211_queue_delayed_work(rt2x00dev->hw,
417 409 &link->watchdog_work,
418 ieee80211_queue_delayed_work(rt2x00dev->hw, 410 WATCHDOG_INTERVAL);
419 &link->watchdog_work, WATCHDOG_INTERVAL);
420} 411}
421 412
422void rt2x00link_stop_watchdog(struct rt2x00_dev *rt2x00dev) 413void rt2x00link_stop_watchdog(struct rt2x00_dev *rt2x00dev)
@@ -441,11 +432,50 @@ static void rt2x00link_watchdog(struct work_struct *work)
441 432
442 if (test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags)) 433 if (test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags))
443 ieee80211_queue_delayed_work(rt2x00dev->hw, 434 ieee80211_queue_delayed_work(rt2x00dev->hw,
444 &link->watchdog_work, WATCHDOG_INTERVAL); 435 &link->watchdog_work,
436 WATCHDOG_INTERVAL);
437}
438
439void rt2x00link_start_agc(struct rt2x00_dev *rt2x00dev)
440{
441 struct link *link = &rt2x00dev->link;
442
443 if (test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags) &&
444 rt2x00dev->ops->lib->gain_calibration)
445 ieee80211_queue_delayed_work(rt2x00dev->hw,
446 &link->agc_work,
447 AGC_INTERVAL);
448}
449
450void rt2x00link_stop_agc(struct rt2x00_dev *rt2x00dev)
451{
452 cancel_delayed_work_sync(&rt2x00dev->link.agc_work);
453}
454
455static void rt2x00link_agc(struct work_struct *work)
456{
457 struct rt2x00_dev *rt2x00dev =
458 container_of(work, struct rt2x00_dev, link.agc_work.work);
459 struct link *link = &rt2x00dev->link;
460
461 /*
462 * When the radio is shutting down we should
463 * immediately cease the watchdog monitoring.
464 */
465 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
466 return;
467
468 rt2x00dev->ops->lib->gain_calibration(rt2x00dev);
469
470 if (test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags))
471 ieee80211_queue_delayed_work(rt2x00dev->hw,
472 &link->agc_work,
473 AGC_INTERVAL);
445} 474}
446 475
447void rt2x00link_register(struct rt2x00_dev *rt2x00dev) 476void rt2x00link_register(struct rt2x00_dev *rt2x00dev)
448{ 477{
478 INIT_DELAYED_WORK(&rt2x00dev->link.agc_work, rt2x00link_agc);
449 INIT_DELAYED_WORK(&rt2x00dev->link.watchdog_work, rt2x00link_watchdog); 479 INIT_DELAYED_WORK(&rt2x00dev->link.watchdog_work, rt2x00link_watchdog);
450 INIT_DELAYED_WORK(&rt2x00dev->link.work, rt2x00link_tuner); 480 INIT_DELAYED_WORK(&rt2x00dev->link.work, rt2x00link_tuner);
451} 481}
diff --git a/drivers/net/wireless/rt2x00/rt2x00mac.c b/drivers/net/wireless/rt2x00/rt2x00mac.c
index 235e037e6509..93bec140e598 100644
--- a/drivers/net/wireless/rt2x00/rt2x00mac.c
+++ b/drivers/net/wireless/rt2x00/rt2x00mac.c
@@ -99,12 +99,12 @@ static int rt2x00mac_tx_rts_cts(struct rt2x00_dev *rt2x00dev,
99 return retval; 99 return retval;
100} 100}
101 101
102int rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) 102void rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
103{ 103{
104 struct rt2x00_dev *rt2x00dev = hw->priv; 104 struct rt2x00_dev *rt2x00dev = hw->priv;
105 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 105 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
106 enum data_queue_qid qid = skb_get_queue_mapping(skb); 106 enum data_queue_qid qid = skb_get_queue_mapping(skb);
107 struct data_queue *queue; 107 struct data_queue *queue = NULL;
108 108
109 /* 109 /*
110 * Mac80211 might be calling this function while we are trying 110 * Mac80211 might be calling this function while we are trying
@@ -116,13 +116,13 @@ int rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
116 goto exit_fail; 116 goto exit_fail;
117 117
118 /* 118 /*
119 * Determine which queue to put packet on. 119 * Use the ATIM queue if appropriate and present.
120 */ 120 */
121 if (tx_info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM && 121 if (tx_info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM &&
122 test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) 122 test_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags))
123 queue = rt2x00queue_get_queue(rt2x00dev, QID_ATIM); 123 qid = QID_ATIM;
124 else 124
125 queue = rt2x00queue_get_queue(rt2x00dev, qid); 125 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
126 if (unlikely(!queue)) { 126 if (unlikely(!queue)) {
127 ERROR(rt2x00dev, 127 ERROR(rt2x00dev,
128 "Attempt to send packet over invalid queue %d.\n" 128 "Attempt to send packet over invalid queue %d.\n"
@@ -139,9 +139,9 @@ int rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
139 * either RTS or CTS-to-self frame and handles everything 139 * either RTS or CTS-to-self frame and handles everything
140 * inside the hardware. 140 * inside the hardware.
141 */ 141 */
142 if ((tx_info->control.rates[0].flags & (IEEE80211_TX_RC_USE_RTS_CTS | 142 if (!rt2x00dev->ops->hw->set_rts_threshold &&
143 IEEE80211_TX_RC_USE_CTS_PROTECT)) && 143 (tx_info->control.rates[0].flags & (IEEE80211_TX_RC_USE_RTS_CTS |
144 !rt2x00dev->ops->hw->set_rts_threshold) { 144 IEEE80211_TX_RC_USE_CTS_PROTECT))) {
145 if (rt2x00queue_available(queue) <= 1) 145 if (rt2x00queue_available(queue) <= 1)
146 goto exit_fail; 146 goto exit_fail;
147 147
@@ -149,18 +149,17 @@ int rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
149 goto exit_fail; 149 goto exit_fail;
150 } 150 }
151 151
152 if (rt2x00queue_write_tx_frame(queue, skb, false)) 152 if (unlikely(rt2x00queue_write_tx_frame(queue, skb, false)))
153 goto exit_fail; 153 goto exit_fail;
154 154
155 if (rt2x00queue_threshold(queue)) 155 if (rt2x00queue_threshold(queue))
156 ieee80211_stop_queue(rt2x00dev->hw, qid); 156 rt2x00queue_pause_queue(queue);
157 157
158 return NETDEV_TX_OK; 158 return;
159 159
160 exit_fail: 160 exit_fail:
161 ieee80211_stop_queue(rt2x00dev->hw, qid); 161 rt2x00queue_pause_queue(queue);
162 dev_kfree_skb_any(skb); 162 dev_kfree_skb_any(skb);
163 return NETDEV_TX_OK;
164} 163}
165EXPORT_SYMBOL_GPL(rt2x00mac_tx); 164EXPORT_SYMBOL_GPL(rt2x00mac_tx);
166 165
@@ -191,7 +190,7 @@ int rt2x00mac_add_interface(struct ieee80211_hw *hw,
191{ 190{
192 struct rt2x00_dev *rt2x00dev = hw->priv; 191 struct rt2x00_dev *rt2x00dev = hw->priv;
193 struct rt2x00_intf *intf = vif_to_intf(vif); 192 struct rt2x00_intf *intf = vif_to_intf(vif);
194 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON); 193 struct data_queue *queue = rt2x00dev->bcn;
195 struct queue_entry *entry = NULL; 194 struct queue_entry *entry = NULL;
196 unsigned int i; 195 unsigned int i;
197 196
@@ -268,13 +267,12 @@ int rt2x00mac_add_interface(struct ieee80211_hw *hw,
268 else 267 else
269 rt2x00dev->intf_sta_count++; 268 rt2x00dev->intf_sta_count++;
270 269
271 spin_lock_init(&intf->lock);
272 spin_lock_init(&intf->seqlock); 270 spin_lock_init(&intf->seqlock);
273 mutex_init(&intf->beacon_skb_mutex); 271 mutex_init(&intf->beacon_skb_mutex);
274 intf->beacon = entry; 272 intf->beacon = entry;
275 273
276 /* 274 /*
277 * The MAC adddress must be configured after the device 275 * The MAC address must be configured after the device
278 * has been initialized. Otherwise the device can reset 276 * has been initialized. Otherwise the device can reset
279 * the MAC registers. 277 * the MAC registers.
280 * The BSSID address must only be configured in AP mode, 278 * The BSSID address must only be configured in AP mode,
@@ -282,15 +280,8 @@ int rt2x00mac_add_interface(struct ieee80211_hw *hw,
282 * STA interfaces at this time, since this can cause 280 * STA interfaces at this time, since this can cause
283 * invalid behavior in the device. 281 * invalid behavior in the device.
284 */ 282 */
285 memcpy(&intf->mac, vif->addr, ETH_ALEN); 283 rt2x00lib_config_intf(rt2x00dev, intf, vif->type,
286 if (vif->type == NL80211_IFTYPE_AP) { 284 vif->addr, NULL);
287 memcpy(&intf->bssid, vif->addr, ETH_ALEN);
288 rt2x00lib_config_intf(rt2x00dev, intf, vif->type,
289 intf->mac, intf->bssid);
290 } else {
291 rt2x00lib_config_intf(rt2x00dev, intf, vif->type,
292 intf->mac, NULL);
293 }
294 285
295 /* 286 /*
296 * Some filters depend on the current working mode. We can force 287 * Some filters depend on the current working mode. We can force
@@ -358,7 +349,7 @@ int rt2x00mac_config(struct ieee80211_hw *hw, u32 changed)
358 * if for any reason the link tuner must be reset, this will be 349 * if for any reason the link tuner must be reset, this will be
359 * handled by rt2x00lib_config(). 350 * handled by rt2x00lib_config().
360 */ 351 */
361 rt2x00lib_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF_LINK); 352 rt2x00queue_stop_queue(rt2x00dev->rx);
362 353
363 /* 354 /*
364 * When we've just turned on the radio, we want to reprogram 355 * When we've just turned on the radio, we want to reprogram
@@ -376,7 +367,7 @@ int rt2x00mac_config(struct ieee80211_hw *hw, u32 changed)
376 rt2x00lib_config_antenna(rt2x00dev, rt2x00dev->default_ant); 367 rt2x00lib_config_antenna(rt2x00dev, rt2x00dev->default_ant);
377 368
378 /* Turn RX back on */ 369 /* Turn RX back on */
379 rt2x00lib_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON_LINK); 370 rt2x00queue_start_queue(rt2x00dev->rx);
380 371
381 return 0; 372 return 0;
382} 373}
@@ -420,11 +411,11 @@ void rt2x00mac_configure_filter(struct ieee80211_hw *hw,
420 * of different types, but has no a separate filter for PS Poll frames, 411 * of different types, but has no a separate filter for PS Poll frames,
421 * FIF_CONTROL flag implies FIF_PSPOLL. 412 * FIF_CONTROL flag implies FIF_PSPOLL.
422 */ 413 */
423 if (!test_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags)) { 414 if (!test_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags)) {
424 if (*total_flags & FIF_CONTROL || *total_flags & FIF_PSPOLL) 415 if (*total_flags & FIF_CONTROL || *total_flags & FIF_PSPOLL)
425 *total_flags |= FIF_CONTROL | FIF_PSPOLL; 416 *total_flags |= FIF_CONTROL | FIF_PSPOLL;
426 } 417 }
427 if (!test_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags)) { 418 if (!test_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags)) {
428 if (*total_flags & FIF_CONTROL) 419 if (*total_flags & FIF_CONTROL)
429 *total_flags |= FIF_PSPOLL; 420 *total_flags |= FIF_PSPOLL;
430 } 421 }
@@ -451,9 +442,7 @@ static void rt2x00mac_set_tim_iter(void *data, u8 *mac,
451 vif->type != NL80211_IFTYPE_WDS) 442 vif->type != NL80211_IFTYPE_WDS)
452 return; 443 return;
453 444
454 spin_lock(&intf->lock); 445 set_bit(DELAYED_UPDATE_BEACON, &intf->delayed_flags);
455 intf->delayed_flags |= DELAYED_UPDATE_BEACON;
456 spin_unlock(&intf->lock);
457} 446}
458 447
459int rt2x00mac_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, 448int rt2x00mac_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
@@ -478,17 +467,17 @@ EXPORT_SYMBOL_GPL(rt2x00mac_set_tim);
478static void memcpy_tkip(struct rt2x00lib_crypto *crypto, u8 *key, u8 key_len) 467static void memcpy_tkip(struct rt2x00lib_crypto *crypto, u8 *key, u8 key_len)
479{ 468{
480 if (key_len > NL80211_TKIP_DATA_OFFSET_ENCR_KEY) 469 if (key_len > NL80211_TKIP_DATA_OFFSET_ENCR_KEY)
481 memcpy(&crypto->key, 470 memcpy(crypto->key,
482 &key[NL80211_TKIP_DATA_OFFSET_ENCR_KEY], 471 &key[NL80211_TKIP_DATA_OFFSET_ENCR_KEY],
483 sizeof(crypto->key)); 472 sizeof(crypto->key));
484 473
485 if (key_len > NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY) 474 if (key_len > NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY)
486 memcpy(&crypto->tx_mic, 475 memcpy(crypto->tx_mic,
487 &key[NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY], 476 &key[NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY],
488 sizeof(crypto->tx_mic)); 477 sizeof(crypto->tx_mic));
489 478
490 if (key_len > NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY) 479 if (key_len > NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY)
491 memcpy(&crypto->rx_mic, 480 memcpy(crypto->rx_mic,
492 &key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY], 481 &key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY],
493 sizeof(crypto->rx_mic)); 482 sizeof(crypto->rx_mic));
494} 483}
@@ -498,7 +487,6 @@ int rt2x00mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
498 struct ieee80211_key_conf *key) 487 struct ieee80211_key_conf *key)
499{ 488{
500 struct rt2x00_dev *rt2x00dev = hw->priv; 489 struct rt2x00_dev *rt2x00dev = hw->priv;
501 struct rt2x00_intf *intf = vif_to_intf(vif);
502 int (*set_key) (struct rt2x00_dev *rt2x00dev, 490 int (*set_key) (struct rt2x00_dev *rt2x00dev,
503 struct rt2x00lib_crypto *crypto, 491 struct rt2x00lib_crypto *crypto,
504 struct ieee80211_key_conf *key); 492 struct ieee80211_key_conf *key);
@@ -508,7 +496,7 @@ int rt2x00mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
508 496
509 if (!test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags)) 497 if (!test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags))
510 return 0; 498 return 0;
511 else if (!test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) 499 else if (!test_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags))
512 return -EOPNOTSUPP; 500 return -EOPNOTSUPP;
513 else if (key->keylen > 32) 501 else if (key->keylen > 32)
514 return -ENOSPC; 502 return -ENOSPC;
@@ -522,7 +510,7 @@ int rt2x00mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
522 if (rt2x00dev->intf_sta_count) 510 if (rt2x00dev->intf_sta_count)
523 crypto.bssidx = 0; 511 crypto.bssidx = 0;
524 else 512 else
525 crypto.bssidx = intf->mac[5] & (rt2x00dev->ops->max_ap_intf - 1); 513 crypto.bssidx = vif->addr[5] & (rt2x00dev->ops->max_ap_intf - 1);
526 514
527 crypto.cipher = rt2x00crypto_key_to_cipher(key); 515 crypto.cipher = rt2x00crypto_key_to_cipher(key);
528 if (crypto.cipher == CIPHER_NONE) 516 if (crypto.cipher == CIPHER_NONE)
@@ -530,17 +518,15 @@ int rt2x00mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
530 518
531 crypto.cmd = cmd; 519 crypto.cmd = cmd;
532 520
533 if (sta) { 521 if (sta)
534 /* some drivers need the AID */
535 crypto.aid = sta->aid;
536 crypto.address = sta->addr; 522 crypto.address = sta->addr;
537 } else 523 else
538 crypto.address = bcast_addr; 524 crypto.address = bcast_addr;
539 525
540 if (crypto.cipher == CIPHER_TKIP) 526 if (crypto.cipher == CIPHER_TKIP)
541 memcpy_tkip(&crypto, &key->key[0], key->keylen); 527 memcpy_tkip(&crypto, &key->key[0], key->keylen);
542 else 528 else
543 memcpy(&crypto.key, &key->key[0], key->keylen); 529 memcpy(crypto.key, &key->key[0], key->keylen);
544 /* 530 /*
545 * Each BSS has a maximum of 4 shared keys. 531 * Each BSS has a maximum of 4 shared keys.
546 * Shared key index values: 532 * Shared key index values:
@@ -576,7 +562,7 @@ EXPORT_SYMBOL_GPL(rt2x00mac_set_key);
576void rt2x00mac_sw_scan_start(struct ieee80211_hw *hw) 562void rt2x00mac_sw_scan_start(struct ieee80211_hw *hw)
577{ 563{
578 struct rt2x00_dev *rt2x00dev = hw->priv; 564 struct rt2x00_dev *rt2x00dev = hw->priv;
579 __set_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags); 565 set_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags);
580 rt2x00link_stop_tuner(rt2x00dev); 566 rt2x00link_stop_tuner(rt2x00dev);
581} 567}
582EXPORT_SYMBOL_GPL(rt2x00mac_sw_scan_start); 568EXPORT_SYMBOL_GPL(rt2x00mac_sw_scan_start);
@@ -584,7 +570,7 @@ EXPORT_SYMBOL_GPL(rt2x00mac_sw_scan_start);
584void rt2x00mac_sw_scan_complete(struct ieee80211_hw *hw) 570void rt2x00mac_sw_scan_complete(struct ieee80211_hw *hw)
585{ 571{
586 struct rt2x00_dev *rt2x00dev = hw->priv; 572 struct rt2x00_dev *rt2x00dev = hw->priv;
587 __clear_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags); 573 clear_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags);
588 rt2x00link_start_tuner(rt2x00dev); 574 rt2x00link_start_tuner(rt2x00dev);
589} 575}
590EXPORT_SYMBOL_GPL(rt2x00mac_sw_scan_complete); 576EXPORT_SYMBOL_GPL(rt2x00mac_sw_scan_complete);
@@ -620,33 +606,55 @@ void rt2x00mac_bss_info_changed(struct ieee80211_hw *hw,
620 if (!test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags)) 606 if (!test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags))
621 return; 607 return;
622 608
623 spin_lock(&intf->lock);
624
625 /* 609 /*
626 * conf->bssid can be NULL if coming from the internal 610 * Update the BSSID.
627 * beacon update routine.
628 */ 611 */
629 if (changes & BSS_CHANGED_BSSID) 612 if (changes & BSS_CHANGED_BSSID)
630 memcpy(&intf->bssid, bss_conf->bssid, ETH_ALEN); 613 rt2x00lib_config_intf(rt2x00dev, intf, vif->type, NULL,
631 614 bss_conf->bssid);
632 spin_unlock(&intf->lock);
633 615
634 /* 616 /*
635 * Call rt2x00_config_intf() outside of the spinlock context since 617 * Update the beacon. This is only required on USB devices. PCI
636 * the call will sleep for USB drivers. By using the ieee80211_if_conf 618 * devices fetch beacons periodically.
637 * values as arguments we make keep access to rt2x00_intf thread safe
638 * even without the lock.
639 */ 619 */
640 if (changes & BSS_CHANGED_BSSID) 620 if (changes & BSS_CHANGED_BEACON && rt2x00_is_usb(rt2x00dev))
641 rt2x00lib_config_intf(rt2x00dev, intf, vif->type, NULL, 621 rt2x00queue_update_beacon(rt2x00dev, vif);
642 bss_conf->bssid);
643 622
644 /* 623 /*
645 * Update the beacon. 624 * Start/stop beaconing.
646 */ 625 */
647 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED)) 626 if (changes & BSS_CHANGED_BEACON_ENABLED) {
648 rt2x00queue_update_beacon(rt2x00dev, vif, 627 if (!bss_conf->enable_beacon && intf->enable_beacon) {
649 bss_conf->enable_beacon); 628 rt2x00queue_clear_beacon(rt2x00dev, vif);
629 rt2x00dev->intf_beaconing--;
630 intf->enable_beacon = false;
631
632 if (rt2x00dev->intf_beaconing == 0) {
633 /*
634 * Last beaconing interface disabled
635 * -> stop beacon queue.
636 */
637 mutex_lock(&intf->beacon_skb_mutex);
638 rt2x00queue_stop_queue(rt2x00dev->bcn);
639 mutex_unlock(&intf->beacon_skb_mutex);
640 }
641
642
643 } else if (bss_conf->enable_beacon && !intf->enable_beacon) {
644 rt2x00dev->intf_beaconing++;
645 intf->enable_beacon = true;
646
647 if (rt2x00dev->intf_beaconing == 1) {
648 /*
649 * First beaconing interface enabled
650 * -> start beacon queue.
651 */
652 mutex_lock(&intf->beacon_skb_mutex);
653 rt2x00queue_start_queue(rt2x00dev->bcn);
654 mutex_unlock(&intf->beacon_skb_mutex);
655 }
656 }
657 }
650 658
651 /* 659 /*
652 * When the association status has changed we must reset the link 660 * When the association status has changed we must reset the link
@@ -669,8 +677,10 @@ void rt2x00mac_bss_info_changed(struct ieee80211_hw *hw,
669 * When the erp information has changed, we should perform 677 * When the erp information has changed, we should perform
670 * additional configuration steps. For all other changes we are done. 678 * additional configuration steps. For all other changes we are done.
671 */ 679 */
672 if (changes & ~(BSS_CHANGED_ASSOC | BSS_CHANGED_HT)) 680 if (changes & (BSS_CHANGED_ERP_CTS_PROT | BSS_CHANGED_ERP_PREAMBLE |
673 rt2x00lib_config_erp(rt2x00dev, intf, bss_conf); 681 BSS_CHANGED_ERP_SLOT | BSS_CHANGED_BASIC_RATES |
682 BSS_CHANGED_BEACON_INT | BSS_CHANGED_HT))
683 rt2x00lib_config_erp(rt2x00dev, intf, bss_conf, changes);
674} 684}
675EXPORT_SYMBOL_GPL(rt2x00mac_bss_info_changed); 685EXPORT_SYMBOL_GPL(rt2x00mac_bss_info_changed);
676 686
@@ -680,7 +690,7 @@ int rt2x00mac_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
680 struct rt2x00_dev *rt2x00dev = hw->priv; 690 struct rt2x00_dev *rt2x00dev = hw->priv;
681 struct data_queue *queue; 691 struct data_queue *queue;
682 692
683 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); 693 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
684 if (unlikely(!queue)) 694 if (unlikely(!queue))
685 return -EINVAL; 695 return -EINVAL;
686 696
@@ -717,3 +727,94 @@ void rt2x00mac_rfkill_poll(struct ieee80211_hw *hw)
717 wiphy_rfkill_set_hw_state(hw->wiphy, !active); 727 wiphy_rfkill_set_hw_state(hw->wiphy, !active);
718} 728}
719EXPORT_SYMBOL_GPL(rt2x00mac_rfkill_poll); 729EXPORT_SYMBOL_GPL(rt2x00mac_rfkill_poll);
730
731void rt2x00mac_flush(struct ieee80211_hw *hw, bool drop)
732{
733 struct rt2x00_dev *rt2x00dev = hw->priv;
734 struct data_queue *queue;
735
736 tx_queue_for_each(rt2x00dev, queue)
737 rt2x00queue_flush_queue(queue, drop);
738}
739EXPORT_SYMBOL_GPL(rt2x00mac_flush);
740
741int rt2x00mac_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
742{
743 struct rt2x00_dev *rt2x00dev = hw->priv;
744 struct link_ant *ant = &rt2x00dev->link.ant;
745 struct antenna_setup *def = &rt2x00dev->default_ant;
746 struct antenna_setup setup;
747
748 // The antenna value is not supposed to be 0,
749 // or exceed the maximum number of antenna's.
750 if (!tx_ant || (tx_ant & ~3) || !rx_ant || (rx_ant & ~3))
751 return -EINVAL;
752
753 // When the client tried to configure the antenna to or from
754 // diversity mode, we must reset the default antenna as well
755 // as that controls the diversity switch.
756 if (ant->flags & ANTENNA_TX_DIVERSITY && tx_ant != 3)
757 ant->flags &= ~ANTENNA_TX_DIVERSITY;
758 if (ant->flags & ANTENNA_RX_DIVERSITY && rx_ant != 3)
759 ant->flags &= ~ANTENNA_RX_DIVERSITY;
760
761 // If diversity is being enabled, check if we need hardware
762 // or software diversity. In the latter case, reset the value,
763 // and make sure we update the antenna flags to have the
764 // link tuner pick up the diversity tuning.
765 if (tx_ant == 3 && def->tx == ANTENNA_SW_DIVERSITY) {
766 tx_ant = ANTENNA_SW_DIVERSITY;
767 ant->flags |= ANTENNA_TX_DIVERSITY;
768 }
769
770 if (rx_ant == 3 && def->rx == ANTENNA_SW_DIVERSITY) {
771 rx_ant = ANTENNA_SW_DIVERSITY;
772 ant->flags |= ANTENNA_RX_DIVERSITY;
773 }
774
775 setup.tx = tx_ant;
776 setup.rx = rx_ant;
777
778 rt2x00lib_config_antenna(rt2x00dev, setup);
779
780 return 0;
781}
782EXPORT_SYMBOL_GPL(rt2x00mac_set_antenna);
783
784int rt2x00mac_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
785{
786 struct rt2x00_dev *rt2x00dev = hw->priv;
787 struct link_ant *ant = &rt2x00dev->link.ant;
788 struct antenna_setup *active = &rt2x00dev->link.ant.active;
789
790 // When software diversity is active, we must report this to the
791 // client and not the current active antenna state.
792 if (ant->flags & ANTENNA_TX_DIVERSITY)
793 *tx_ant = ANTENNA_HW_DIVERSITY;
794 else
795 *tx_ant = active->tx;
796
797 if (ant->flags & ANTENNA_RX_DIVERSITY)
798 *rx_ant = ANTENNA_HW_DIVERSITY;
799 else
800 *rx_ant = active->rx;
801
802 return 0;
803}
804EXPORT_SYMBOL_GPL(rt2x00mac_get_antenna);
805
806void rt2x00mac_get_ringparam(struct ieee80211_hw *hw,
807 u32 *tx, u32 *tx_max, u32 *rx, u32 *rx_max)
808{
809 struct rt2x00_dev *rt2x00dev = hw->priv;
810 struct data_queue *queue;
811
812 tx_queue_for_each(rt2x00dev, queue) {
813 *tx += queue->length;
814 *tx_max += queue->limit;
815 }
816
817 *rx = rt2x00dev->rx->length;
818 *rx_max = rt2x00dev->rx->limit;
819}
820EXPORT_SYMBOL_GPL(rt2x00mac_get_ringparam);
diff --git a/drivers/net/wireless/rt2x00/rt2x00pci.c b/drivers/net/wireless/rt2x00/rt2x00pci.c
index 63c2cc408e15..17148bb24426 100644
--- a/drivers/net/wireless/rt2x00/rt2x00pci.c
+++ b/drivers/net/wireless/rt2x00/rt2x00pci.c
@@ -60,14 +60,15 @@ int rt2x00pci_regbusy_read(struct rt2x00_dev *rt2x00dev,
60} 60}
61EXPORT_SYMBOL_GPL(rt2x00pci_regbusy_read); 61EXPORT_SYMBOL_GPL(rt2x00pci_regbusy_read);
62 62
63void rt2x00pci_rxdone(struct rt2x00_dev *rt2x00dev) 63bool rt2x00pci_rxdone(struct rt2x00_dev *rt2x00dev)
64{ 64{
65 struct data_queue *queue = rt2x00dev->rx; 65 struct data_queue *queue = rt2x00dev->rx;
66 struct queue_entry *entry; 66 struct queue_entry *entry;
67 struct queue_entry_priv_pci *entry_priv; 67 struct queue_entry_priv_pci *entry_priv;
68 struct skb_frame_desc *skbdesc; 68 struct skb_frame_desc *skbdesc;
69 int max_rx = 16;
69 70
70 while (1) { 71 while (--max_rx) {
71 entry = rt2x00queue_get_entry(queue, Q_INDEX); 72 entry = rt2x00queue_get_entry(queue, Q_INDEX);
72 entry_priv = entry->priv_data; 73 entry_priv = entry->priv_data;
73 74
@@ -82,13 +83,31 @@ void rt2x00pci_rxdone(struct rt2x00_dev *rt2x00dev)
82 skbdesc->desc_len = entry->queue->desc_size; 83 skbdesc->desc_len = entry->queue->desc_size;
83 84
84 /* 85 /*
86 * DMA is already done, notify rt2x00lib that
87 * it finished successfully.
88 */
89 rt2x00lib_dmastart(entry);
90 rt2x00lib_dmadone(entry);
91
92 /*
85 * Send the frame to rt2x00lib for further processing. 93 * Send the frame to rt2x00lib for further processing.
86 */ 94 */
87 rt2x00lib_rxdone(rt2x00dev, entry); 95 rt2x00lib_rxdone(entry);
88 } 96 }
97
98 return !max_rx;
89} 99}
90EXPORT_SYMBOL_GPL(rt2x00pci_rxdone); 100EXPORT_SYMBOL_GPL(rt2x00pci_rxdone);
91 101
102void rt2x00pci_flush_queue(struct data_queue *queue, bool drop)
103{
104 unsigned int i;
105
106 for (i = 0; !rt2x00queue_empty(queue) && i < 10; i++)
107 msleep(10);
108}
109EXPORT_SYMBOL_GPL(rt2x00pci_flush_queue);
110
92/* 111/*
93 * Device initialization handlers. 112 * Device initialization handlers.
94 */ 113 */
@@ -105,7 +124,7 @@ static int rt2x00pci_alloc_queue_dma(struct rt2x00_dev *rt2x00dev,
105 */ 124 */
106 addr = dma_alloc_coherent(rt2x00dev->dev, 125 addr = dma_alloc_coherent(rt2x00dev->dev,
107 queue->limit * queue->desc_size, 126 queue->limit * queue->desc_size,
108 &dma, GFP_KERNEL | GFP_DMA); 127 &dma, GFP_KERNEL);
109 if (!addr) 128 if (!addr)
110 return -ENOMEM; 129 return -ENOMEM;
111 130
@@ -153,10 +172,9 @@ int rt2x00pci_initialize(struct rt2x00_dev *rt2x00dev)
153 /* 172 /*
154 * Register interrupt handler. 173 * Register interrupt handler.
155 */ 174 */
156 status = request_threaded_irq(rt2x00dev->irq, 175 status = request_irq(rt2x00dev->irq,
157 rt2x00dev->ops->lib->irq_handler, 176 rt2x00dev->ops->lib->irq_handler,
158 rt2x00dev->ops->lib->irq_handler_thread, 177 IRQF_SHARED, rt2x00dev->name, rt2x00dev);
159 IRQF_SHARED, rt2x00dev->name, rt2x00dev);
160 if (status) { 178 if (status) {
161 ERROR(rt2x00dev, "IRQ %d allocation failed (error %d).\n", 179 ERROR(rt2x00dev, "IRQ %d allocation failed (error %d).\n",
162 rt2x00dev->irq, status); 180 rt2x00dev->irq, status);
@@ -233,9 +251,8 @@ exit:
233 return -ENOMEM; 251 return -ENOMEM;
234} 252}
235 253
236int rt2x00pci_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) 254int rt2x00pci_probe(struct pci_dev *pci_dev, const struct rt2x00_ops *ops)
237{ 255{
238 struct rt2x00_ops *ops = (struct rt2x00_ops *)id->driver_data;
239 struct ieee80211_hw *hw; 256 struct ieee80211_hw *hw;
240 struct rt2x00_dev *rt2x00dev; 257 struct rt2x00_dev *rt2x00dev;
241 int retval; 258 int retval;
@@ -279,7 +296,7 @@ int rt2x00pci_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
279 rt2x00dev->irq = pci_dev->irq; 296 rt2x00dev->irq = pci_dev->irq;
280 rt2x00dev->name = pci_name(pci_dev); 297 rt2x00dev->name = pci_name(pci_dev);
281 298
282 if (pci_dev->is_pcie) 299 if (pci_is_pcie(pci_dev))
283 rt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_PCIE); 300 rt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_PCIE);
284 else 301 else
285 rt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_PCI); 302 rt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_PCI);
@@ -356,12 +373,12 @@ int rt2x00pci_resume(struct pci_dev *pci_dev)
356 struct rt2x00_dev *rt2x00dev = hw->priv; 373 struct rt2x00_dev *rt2x00dev = hw->priv;
357 374
358 if (pci_set_power_state(pci_dev, PCI_D0) || 375 if (pci_set_power_state(pci_dev, PCI_D0) ||
359 pci_enable_device(pci_dev) || 376 pci_enable_device(pci_dev)) {
360 pci_restore_state(pci_dev)) {
361 ERROR(rt2x00dev, "Failed to resume device.\n"); 377 ERROR(rt2x00dev, "Failed to resume device.\n");
362 return -EIO; 378 return -EIO;
363 } 379 }
364 380
381 pci_restore_state(pci_dev);
365 return rt2x00lib_resume(rt2x00dev); 382 return rt2x00lib_resume(rt2x00dev);
366} 383}
367EXPORT_SYMBOL_GPL(rt2x00pci_resume); 384EXPORT_SYMBOL_GPL(rt2x00pci_resume);
diff --git a/drivers/net/wireless/rt2x00/rt2x00pci.h b/drivers/net/wireless/rt2x00/rt2x00pci.h
index b854d62ff99b..e2c99f2b9a14 100644
--- a/drivers/net/wireless/rt2x00/rt2x00pci.h
+++ b/drivers/net/wireless/rt2x00/rt2x00pci.h
@@ -64,7 +64,7 @@ static inline void rt2x00pci_register_multiwrite(struct rt2x00_dev *rt2x00dev,
64 const void *value, 64 const void *value,
65 const u32 length) 65 const u32 length)
66{ 66{
67 memcpy_toio(rt2x00dev->csr.base + offset, value, length); 67 __iowrite32_copy(rt2x00dev->csr.base + offset, value, length >> 2);
68} 68}
69 69
70/** 70/**
@@ -101,8 +101,21 @@ struct queue_entry_priv_pci {
101/** 101/**
102 * rt2x00pci_rxdone - Handle RX done events 102 * rt2x00pci_rxdone - Handle RX done events
103 * @rt2x00dev: Device pointer, see &struct rt2x00_dev. 103 * @rt2x00dev: Device pointer, see &struct rt2x00_dev.
104 *
105 * Returns true if there are still rx frames pending and false if all
106 * pending rx frames were processed.
107 */
108bool rt2x00pci_rxdone(struct rt2x00_dev *rt2x00dev);
109
110/**
111 * rt2x00pci_flush_queue - Flush data queue
112 * @queue: Data queue to stop
113 * @drop: True to drop all pending frames.
114 *
115 * This will wait for a maximum of 100ms, waiting for the queues
116 * to become empty.
104 */ 117 */
105void rt2x00pci_rxdone(struct rt2x00_dev *rt2x00dev); 118void rt2x00pci_flush_queue(struct data_queue *queue, bool drop);
106 119
107/* 120/*
108 * Device initialization handlers. 121 * Device initialization handlers.
@@ -113,7 +126,7 @@ void rt2x00pci_uninitialize(struct rt2x00_dev *rt2x00dev);
113/* 126/*
114 * PCI driver handlers. 127 * PCI driver handlers.
115 */ 128 */
116int rt2x00pci_probe(struct pci_dev *pci_dev, const struct pci_device_id *id); 129int rt2x00pci_probe(struct pci_dev *pci_dev, const struct rt2x00_ops *ops);
117void rt2x00pci_remove(struct pci_dev *pci_dev); 130void rt2x00pci_remove(struct pci_dev *pci_dev);
118#ifdef CONFIG_PM 131#ifdef CONFIG_PM
119int rt2x00pci_suspend(struct pci_dev *pci_dev, pm_message_t state); 132int rt2x00pci_suspend(struct pci_dev *pci_dev, pm_message_t state);
diff --git a/drivers/net/wireless/rt2x00/rt2x00queue.c b/drivers/net/wireless/rt2x00/rt2x00queue.c
index a3401d301058..ab8c16f8bcaf 100644
--- a/drivers/net/wireless/rt2x00/rt2x00queue.c
+++ b/drivers/net/wireless/rt2x00/rt2x00queue.c
@@ -1,5 +1,6 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com> 4 Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com>
4 <http://rt2x00.serialmonkey.com> 5 <http://rt2x00.serialmonkey.com>
5 6
@@ -32,9 +33,9 @@
32#include "rt2x00.h" 33#include "rt2x00.h"
33#include "rt2x00lib.h" 34#include "rt2x00lib.h"
34 35
35struct sk_buff *rt2x00queue_alloc_rxskb(struct rt2x00_dev *rt2x00dev, 36struct sk_buff *rt2x00queue_alloc_rxskb(struct queue_entry *entry)
36 struct queue_entry *entry)
37{ 37{
38 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
38 struct sk_buff *skb; 39 struct sk_buff *skb;
39 struct skb_frame_desc *skbdesc; 40 struct skb_frame_desc *skbdesc;
40 unsigned int frame_size; 41 unsigned int frame_size;
@@ -59,7 +60,7 @@ struct sk_buff *rt2x00queue_alloc_rxskb(struct rt2x00_dev *rt2x00dev,
59 * at least 8 bytes bytes available in headroom for IV/EIV 60 * at least 8 bytes bytes available in headroom for IV/EIV
60 * and 8 bytes for ICV data as tailroon. 61 * and 8 bytes for ICV data as tailroon.
61 */ 62 */
62 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) { 63 if (test_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags)) {
63 head_size += 8; 64 head_size += 8;
64 tail_size += 8; 65 tail_size += 8;
65 } 66 }
@@ -85,7 +86,7 @@ struct sk_buff *rt2x00queue_alloc_rxskb(struct rt2x00_dev *rt2x00dev,
85 memset(skbdesc, 0, sizeof(*skbdesc)); 86 memset(skbdesc, 0, sizeof(*skbdesc));
86 skbdesc->entry = entry; 87 skbdesc->entry = entry;
87 88
88 if (test_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags)) { 89 if (test_bit(REQUIRE_DMA, &rt2x00dev->cap_flags)) {
89 skbdesc->skb_dma = dma_map_single(rt2x00dev->dev, 90 skbdesc->skb_dma = dma_map_single(rt2x00dev->dev,
90 skb->data, 91 skb->data,
91 skb->len, 92 skb->len,
@@ -96,41 +97,42 @@ struct sk_buff *rt2x00queue_alloc_rxskb(struct rt2x00_dev *rt2x00dev,
96 return skb; 97 return skb;
97} 98}
98 99
99void rt2x00queue_map_txskb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb) 100void rt2x00queue_map_txskb(struct queue_entry *entry)
100{ 101{
101 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 102 struct device *dev = entry->queue->rt2x00dev->dev;
103 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
102 104
103 skbdesc->skb_dma = 105 skbdesc->skb_dma =
104 dma_map_single(rt2x00dev->dev, skb->data, skb->len, DMA_TO_DEVICE); 106 dma_map_single(dev, entry->skb->data, entry->skb->len, DMA_TO_DEVICE);
105 skbdesc->flags |= SKBDESC_DMA_MAPPED_TX; 107 skbdesc->flags |= SKBDESC_DMA_MAPPED_TX;
106} 108}
107EXPORT_SYMBOL_GPL(rt2x00queue_map_txskb); 109EXPORT_SYMBOL_GPL(rt2x00queue_map_txskb);
108 110
109void rt2x00queue_unmap_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb) 111void rt2x00queue_unmap_skb(struct queue_entry *entry)
110{ 112{
111 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 113 struct device *dev = entry->queue->rt2x00dev->dev;
114 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
112 115
113 if (skbdesc->flags & SKBDESC_DMA_MAPPED_RX) { 116 if (skbdesc->flags & SKBDESC_DMA_MAPPED_RX) {
114 dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma, skb->len, 117 dma_unmap_single(dev, skbdesc->skb_dma, entry->skb->len,
115 DMA_FROM_DEVICE); 118 DMA_FROM_DEVICE);
116 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_RX; 119 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_RX;
117 } 120 } else if (skbdesc->flags & SKBDESC_DMA_MAPPED_TX) {
118 121 dma_unmap_single(dev, skbdesc->skb_dma, entry->skb->len,
119 if (skbdesc->flags & SKBDESC_DMA_MAPPED_TX) {
120 dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma, skb->len,
121 DMA_TO_DEVICE); 122 DMA_TO_DEVICE);
122 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX; 123 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX;
123 } 124 }
124} 125}
125EXPORT_SYMBOL_GPL(rt2x00queue_unmap_skb); 126EXPORT_SYMBOL_GPL(rt2x00queue_unmap_skb);
126 127
127void rt2x00queue_free_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb) 128void rt2x00queue_free_skb(struct queue_entry *entry)
128{ 129{
129 if (!skb) 130 if (!entry->skb)
130 return; 131 return;
131 132
132 rt2x00queue_unmap_skb(rt2x00dev, skb); 133 rt2x00queue_unmap_skb(entry);
133 dev_kfree_skb_any(skb); 134 dev_kfree_skb_any(entry->skb);
135 entry->skb = NULL;
134} 136}
135 137
136void rt2x00queue_align_frame(struct sk_buff *skb) 138void rt2x00queue_align_frame(struct sk_buff *skb)
@@ -146,19 +148,6 @@ void rt2x00queue_align_frame(struct sk_buff *skb)
146 skb_trim(skb, frame_length); 148 skb_trim(skb, frame_length);
147} 149}
148 150
149void rt2x00queue_align_payload(struct sk_buff *skb, unsigned int header_length)
150{
151 unsigned int frame_length = skb->len;
152 unsigned int align = ALIGN_SIZE(skb, header_length);
153
154 if (!align)
155 return;
156
157 skb_push(skb, align);
158 memmove(skb->data, skb->data + align, frame_length);
159 skb_trim(skb, frame_length);
160}
161
162void rt2x00queue_insert_l2pad(struct sk_buff *skb, unsigned int header_length) 151void rt2x00queue_insert_l2pad(struct sk_buff *skb, unsigned int header_length)
163{ 152{
164 unsigned int payload_length = skb->len - header_length; 153 unsigned int payload_length = skb->len - header_length;
@@ -197,7 +186,12 @@ void rt2x00queue_insert_l2pad(struct sk_buff *skb, unsigned int header_length)
197 186
198void rt2x00queue_remove_l2pad(struct sk_buff *skb, unsigned int header_length) 187void rt2x00queue_remove_l2pad(struct sk_buff *skb, unsigned int header_length)
199{ 188{
200 unsigned int l2pad = L2PAD_SIZE(header_length); 189 /*
190 * L2 padding is only present if the skb contains more than just the
191 * IEEE 802.11 header.
192 */
193 unsigned int l2pad = (skb->len > header_length) ?
194 L2PAD_SIZE(header_length) : 0;
201 195
202 if (!l2pad) 196 if (!l2pad)
203 return; 197 return;
@@ -214,14 +208,17 @@ static void rt2x00queue_create_tx_descriptor_seq(struct queue_entry *entry,
214 struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif); 208 struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
215 unsigned long irqflags; 209 unsigned long irqflags;
216 210
217 if (!(tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) || 211 if (!(tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ))
218 unlikely(!tx_info->control.vif)) 212 return;
213
214 __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags);
215
216 if (!test_bit(REQUIRE_SW_SEQNO, &entry->queue->rt2x00dev->cap_flags))
219 return; 217 return;
220 218
221 /* 219 /*
222 * Hardware should insert sequence counter. 220 * The hardware is not able to insert a sequence number. Assign a
223 * FIXME: We insert a software sequence counter first for 221 * software generated one here.
224 * hardware that doesn't support hardware sequence counting.
225 * 222 *
226 * This is wrong because beacons are not getting sequence 223 * This is wrong because beacons are not getting sequence
227 * numbers assigned properly. 224 * numbers assigned properly.
@@ -239,7 +236,6 @@ static void rt2x00queue_create_tx_descriptor_seq(struct queue_entry *entry,
239 236
240 spin_unlock_irqrestore(&intf->seqlock, irqflags); 237 spin_unlock_irqrestore(&intf->seqlock, irqflags);
241 238
242 __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags);
243} 239}
244 240
245static void rt2x00queue_create_tx_descriptor_plcp(struct queue_entry *entry, 241static void rt2x00queue_create_tx_descriptor_plcp(struct queue_entry *entry,
@@ -253,6 +249,16 @@ static void rt2x00queue_create_tx_descriptor_plcp(struct queue_entry *entry,
253 unsigned int duration; 249 unsigned int duration;
254 unsigned int residual; 250 unsigned int residual;
255 251
252 /*
253 * Determine with what IFS priority this frame should be send.
254 * Set ifs to IFS_SIFS when the this is not the first fragment,
255 * or this fragment came after RTS/CTS.
256 */
257 if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags))
258 txdesc->u.plcp.ifs = IFS_BACKOFF;
259 else
260 txdesc->u.plcp.ifs = IFS_SIFS;
261
256 /* Data length + CRC + Crypto overhead (IV/EIV/ICV/MIC) */ 262 /* Data length + CRC + Crypto overhead (IV/EIV/ICV/MIC) */
257 data_length = entry->skb->len + 4; 263 data_length = entry->skb->len + 4;
258 data_length += rt2x00crypto_tx_overhead(rt2x00dev, entry->skb); 264 data_length += rt2x00crypto_tx_overhead(rt2x00dev, entry->skb);
@@ -261,12 +267,12 @@ static void rt2x00queue_create_tx_descriptor_plcp(struct queue_entry *entry,
261 * PLCP setup 267 * PLCP setup
262 * Length calculation depends on OFDM/CCK rate. 268 * Length calculation depends on OFDM/CCK rate.
263 */ 269 */
264 txdesc->signal = hwrate->plcp; 270 txdesc->u.plcp.signal = hwrate->plcp;
265 txdesc->service = 0x04; 271 txdesc->u.plcp.service = 0x04;
266 272
267 if (hwrate->flags & DEV_RATE_OFDM) { 273 if (hwrate->flags & DEV_RATE_OFDM) {
268 txdesc->length_high = (data_length >> 6) & 0x3f; 274 txdesc->u.plcp.length_high = (data_length >> 6) & 0x3f;
269 txdesc->length_low = data_length & 0x3f; 275 txdesc->u.plcp.length_low = data_length & 0x3f;
270 } else { 276 } else {
271 /* 277 /*
272 * Convert length to microseconds. 278 * Convert length to microseconds.
@@ -281,42 +287,113 @@ static void rt2x00queue_create_tx_descriptor_plcp(struct queue_entry *entry,
281 * Check if we need to set the Length Extension 287 * Check if we need to set the Length Extension
282 */ 288 */
283 if (hwrate->bitrate == 110 && residual <= 30) 289 if (hwrate->bitrate == 110 && residual <= 30)
284 txdesc->service |= 0x80; 290 txdesc->u.plcp.service |= 0x80;
285 } 291 }
286 292
287 txdesc->length_high = (duration >> 8) & 0xff; 293 txdesc->u.plcp.length_high = (duration >> 8) & 0xff;
288 txdesc->length_low = duration & 0xff; 294 txdesc->u.plcp.length_low = duration & 0xff;
289 295
290 /* 296 /*
291 * When preamble is enabled we should set the 297 * When preamble is enabled we should set the
292 * preamble bit for the signal. 298 * preamble bit for the signal.
293 */ 299 */
294 if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 300 if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
295 txdesc->signal |= 0x08; 301 txdesc->u.plcp.signal |= 0x08;
296 } 302 }
297} 303}
298 304
305static void rt2x00queue_create_tx_descriptor_ht(struct queue_entry *entry,
306 struct txentry_desc *txdesc,
307 const struct rt2x00_rate *hwrate)
308{
309 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
310 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
311 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
312
313 if (tx_info->control.sta)
314 txdesc->u.ht.mpdu_density =
315 tx_info->control.sta->ht_cap.ampdu_density;
316
317 txdesc->u.ht.ba_size = 7; /* FIXME: What value is needed? */
318
319 /*
320 * Only one STBC stream is supported for now.
321 */
322 if (tx_info->flags & IEEE80211_TX_CTL_STBC)
323 txdesc->u.ht.stbc = 1;
324
325 /*
326 * If IEEE80211_TX_RC_MCS is set txrate->idx just contains the
327 * mcs rate to be used
328 */
329 if (txrate->flags & IEEE80211_TX_RC_MCS) {
330 txdesc->u.ht.mcs = txrate->idx;
331
332 /*
333 * MIMO PS should be set to 1 for STA's using dynamic SM PS
334 * when using more then one tx stream (>MCS7).
335 */
336 if (tx_info->control.sta && txdesc->u.ht.mcs > 7 &&
337 ((tx_info->control.sta->ht_cap.cap &
338 IEEE80211_HT_CAP_SM_PS) >>
339 IEEE80211_HT_CAP_SM_PS_SHIFT) ==
340 WLAN_HT_CAP_SM_PS_DYNAMIC)
341 __set_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags);
342 } else {
343 txdesc->u.ht.mcs = rt2x00_get_rate_mcs(hwrate->mcs);
344 if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
345 txdesc->u.ht.mcs |= 0x08;
346 }
347
348 /*
349 * This frame is eligible for an AMPDU, however, don't aggregate
350 * frames that are intended to probe a specific tx rate.
351 */
352 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU &&
353 !(tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE))
354 __set_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags);
355
356 /*
357 * Set 40Mhz mode if necessary (for legacy rates this will
358 * duplicate the frame to both channels).
359 */
360 if (txrate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH ||
361 txrate->flags & IEEE80211_TX_RC_DUP_DATA)
362 __set_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags);
363 if (txrate->flags & IEEE80211_TX_RC_SHORT_GI)
364 __set_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags);
365
366 /*
367 * Determine IFS values
368 * - Use TXOP_BACKOFF for management frames except beacons
369 * - Use TXOP_SIFS for fragment bursts
370 * - Use TXOP_HTTXOP for everything else
371 *
372 * Note: rt2800 devices won't use CTS protection (if used)
373 * for frames not transmitted with TXOP_HTTXOP
374 */
375 if (ieee80211_is_mgmt(hdr->frame_control) &&
376 !ieee80211_is_beacon(hdr->frame_control))
377 txdesc->u.ht.txop = TXOP_BACKOFF;
378 else if (!(tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT))
379 txdesc->u.ht.txop = TXOP_SIFS;
380 else
381 txdesc->u.ht.txop = TXOP_HTTXOP;
382}
383
299static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry, 384static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
300 struct txentry_desc *txdesc) 385 struct txentry_desc *txdesc)
301{ 386{
302 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 387 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
303 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb); 388 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
304 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data; 389 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
305 struct ieee80211_rate *rate = 390 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
306 ieee80211_get_tx_rate(rt2x00dev->hw, tx_info); 391 struct ieee80211_rate *rate;
307 const struct rt2x00_rate *hwrate; 392 const struct rt2x00_rate *hwrate = NULL;
308 393
309 memset(txdesc, 0, sizeof(*txdesc)); 394 memset(txdesc, 0, sizeof(*txdesc));
310 395
311 /* 396 /*
312 * Initialize information from queue
313 */
314 txdesc->queue = entry->queue->qid;
315 txdesc->cw_min = entry->queue->cw_min;
316 txdesc->cw_max = entry->queue->cw_max;
317 txdesc->aifs = entry->queue->aifs;
318
319 /*
320 * Header and frame information. 397 * Header and frame information.
321 */ 398 */
322 txdesc->length = entry->skb->len; 399 txdesc->length = entry->skb->len;
@@ -366,42 +443,42 @@ static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
366 443
367 /* 444 /*
368 * Beacons and probe responses require the tsf timestamp 445 * Beacons and probe responses require the tsf timestamp
369 * to be inserted into the frame, except for a frame that has been injected 446 * to be inserted into the frame.
370 * through a monitor interface. This latter is needed for testing a
371 * monitor interface.
372 */ 447 */
373 if ((ieee80211_is_beacon(hdr->frame_control) || 448 if (ieee80211_is_beacon(hdr->frame_control) ||
374 ieee80211_is_probe_resp(hdr->frame_control)) && 449 ieee80211_is_probe_resp(hdr->frame_control))
375 (!(tx_info->flags & IEEE80211_TX_CTL_INJECTED)))
376 __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags); 450 __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags);
377 451
378 /*
379 * Determine with what IFS priority this frame should be send.
380 * Set ifs to IFS_SIFS when the this is not the first fragment,
381 * or this fragment came after RTS/CTS.
382 */
383 if ((tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) && 452 if ((tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) &&
384 !test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)) { 453 !test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags))
385 __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags); 454 __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags);
386 txdesc->ifs = IFS_BACKOFF;
387 } else
388 txdesc->ifs = IFS_SIFS;
389 455
390 /* 456 /*
391 * Determine rate modulation. 457 * Determine rate modulation.
392 */ 458 */
393 hwrate = rt2x00_get_rate(rate->hw_value); 459 if (txrate->flags & IEEE80211_TX_RC_GREEN_FIELD)
394 txdesc->rate_mode = RATE_MODE_CCK; 460 txdesc->rate_mode = RATE_MODE_HT_GREENFIELD;
395 if (hwrate->flags & DEV_RATE_OFDM) 461 else if (txrate->flags & IEEE80211_TX_RC_MCS)
396 txdesc->rate_mode = RATE_MODE_OFDM; 462 txdesc->rate_mode = RATE_MODE_HT_MIX;
463 else {
464 rate = ieee80211_get_tx_rate(rt2x00dev->hw, tx_info);
465 hwrate = rt2x00_get_rate(rate->hw_value);
466 if (hwrate->flags & DEV_RATE_OFDM)
467 txdesc->rate_mode = RATE_MODE_OFDM;
468 else
469 txdesc->rate_mode = RATE_MODE_CCK;
470 }
397 471
398 /* 472 /*
399 * Apply TX descriptor handling by components 473 * Apply TX descriptor handling by components
400 */ 474 */
401 rt2x00crypto_create_tx_descriptor(entry, txdesc); 475 rt2x00crypto_create_tx_descriptor(entry, txdesc);
402 rt2x00ht_create_tx_descriptor(entry, txdesc, hwrate);
403 rt2x00queue_create_tx_descriptor_seq(entry, txdesc); 476 rt2x00queue_create_tx_descriptor_seq(entry, txdesc);
404 rt2x00queue_create_tx_descriptor_plcp(entry, txdesc, hwrate); 477
478 if (test_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags))
479 rt2x00queue_create_tx_descriptor_ht(entry, txdesc, hwrate);
480 else
481 rt2x00queue_create_tx_descriptor_plcp(entry, txdesc, hwrate);
405} 482}
406 483
407static int rt2x00queue_write_tx_data(struct queue_entry *entry, 484static int rt2x00queue_write_tx_data(struct queue_entry *entry,
@@ -438,8 +515,8 @@ static int rt2x00queue_write_tx_data(struct queue_entry *entry,
438 /* 515 /*
439 * Map the skb to DMA. 516 * Map the skb to DMA.
440 */ 517 */
441 if (test_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags)) 518 if (test_bit(REQUIRE_DMA, &rt2x00dev->cap_flags))
442 rt2x00queue_map_txskb(rt2x00dev, entry->skb); 519 rt2x00queue_map_txskb(entry);
443 520
444 return 0; 521 return 0;
445} 522}
@@ -448,23 +525,19 @@ static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry,
448 struct txentry_desc *txdesc) 525 struct txentry_desc *txdesc)
449{ 526{
450 struct data_queue *queue = entry->queue; 527 struct data_queue *queue = entry->queue;
451 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
452 528
453 rt2x00dev->ops->lib->write_tx_desc(rt2x00dev, entry->skb, txdesc); 529 queue->rt2x00dev->ops->lib->write_tx_desc(entry, txdesc);
454 530
455 /* 531 /*
456 * All processing on the frame has been completed, this means 532 * All processing on the frame has been completed, this means
457 * it is now ready to be dumped to userspace through debugfs. 533 * it is now ready to be dumped to userspace through debugfs.
458 */ 534 */
459 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_TX, entry->skb); 535 rt2x00debug_dump_frame(queue->rt2x00dev, DUMP_FRAME_TX, entry->skb);
460} 536}
461 537
462static void rt2x00queue_kick_tx_queue(struct queue_entry *entry, 538static void rt2x00queue_kick_tx_queue(struct data_queue *queue,
463 struct txentry_desc *txdesc) 539 struct txentry_desc *txdesc)
464{ 540{
465 struct data_queue *queue = entry->queue;
466 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
467
468 /* 541 /*
469 * Check if we need to kick the queue, there are however a few rules 542 * Check if we need to kick the queue, there are however a few rules
470 * 1) Don't kick unless this is the last in frame in a burst. 543 * 1) Don't kick unless this is the last in frame in a burst.
@@ -476,7 +549,7 @@ static void rt2x00queue_kick_tx_queue(struct queue_entry *entry,
476 */ 549 */
477 if (rt2x00queue_threshold(queue) || 550 if (rt2x00queue_threshold(queue) ||
478 !test_bit(ENTRY_TXD_BURST, &txdesc->flags)) 551 !test_bit(ENTRY_TXD_BURST, &txdesc->flags))
479 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, queue->qid); 552 queue->rt2x00dev->ops->lib->kick_queue(queue);
480} 553}
481 554
482int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb, 555int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
@@ -488,10 +561,14 @@ int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
488 struct skb_frame_desc *skbdesc; 561 struct skb_frame_desc *skbdesc;
489 u8 rate_idx, rate_flags; 562 u8 rate_idx, rate_flags;
490 563
491 if (unlikely(rt2x00queue_full(queue))) 564 if (unlikely(rt2x00queue_full(queue))) {
565 ERROR(queue->rt2x00dev,
566 "Dropping frame due to full tx queue %d.\n", queue->qid);
492 return -ENOBUFS; 567 return -ENOBUFS;
568 }
493 569
494 if (test_and_set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags)) { 570 if (unlikely(test_and_set_bit(ENTRY_OWNER_DEVICE_DATA,
571 &entry->flags))) {
495 ERROR(queue->rt2x00dev, 572 ERROR(queue->rt2x00dev,
496 "Arrived at non-free entry in the non-full queue %d.\n" 573 "Arrived at non-free entry in the non-full queue %d.\n"
497 "Please file bug report to %s.\n", 574 "Please file bug report to %s.\n",
@@ -531,23 +608,23 @@ int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
531 */ 608 */
532 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) && 609 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) &&
533 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags)) { 610 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags)) {
534 if (test_bit(DRIVER_REQUIRE_COPY_IV, &queue->rt2x00dev->flags)) 611 if (test_bit(REQUIRE_COPY_IV, &queue->rt2x00dev->cap_flags))
535 rt2x00crypto_tx_copy_iv(skb, &txdesc); 612 rt2x00crypto_tx_copy_iv(skb, &txdesc);
536 else 613 else
537 rt2x00crypto_tx_remove_iv(skb, &txdesc); 614 rt2x00crypto_tx_remove_iv(skb, &txdesc);
538 } 615 }
539 616
540 /* 617 /*
541 * When DMA allocation is required we should guarentee to the 618 * When DMA allocation is required we should guarantee to the
542 * driver that the DMA is aligned to a 4-byte boundary. 619 * driver that the DMA is aligned to a 4-byte boundary.
543 * However some drivers require L2 padding to pad the payload 620 * However some drivers require L2 padding to pad the payload
544 * rather then the header. This could be a requirement for 621 * rather then the header. This could be a requirement for
545 * PCI and USB devices, while header alignment only is valid 622 * PCI and USB devices, while header alignment only is valid
546 * for PCI devices. 623 * for PCI devices.
547 */ 624 */
548 if (test_bit(DRIVER_REQUIRE_L2PAD, &queue->rt2x00dev->flags)) 625 if (test_bit(REQUIRE_L2PAD, &queue->rt2x00dev->cap_flags))
549 rt2x00queue_insert_l2pad(entry->skb, txdesc.header_length); 626 rt2x00queue_insert_l2pad(entry->skb, txdesc.header_length);
550 else if (test_bit(DRIVER_REQUIRE_DMA, &queue->rt2x00dev->flags)) 627 else if (test_bit(REQUIRE_DMA, &queue->rt2x00dev->cap_flags))
551 rt2x00queue_align_frame(entry->skb); 628 rt2x00queue_align_frame(entry->skb);
552 629
553 /* 630 /*
@@ -563,20 +640,17 @@ int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
563 640
564 set_bit(ENTRY_DATA_PENDING, &entry->flags); 641 set_bit(ENTRY_DATA_PENDING, &entry->flags);
565 642
566 rt2x00queue_index_inc(queue, Q_INDEX); 643 rt2x00queue_index_inc(entry, Q_INDEX);
567 rt2x00queue_write_tx_descriptor(entry, &txdesc); 644 rt2x00queue_write_tx_descriptor(entry, &txdesc);
568 rt2x00queue_kick_tx_queue(entry, &txdesc); 645 rt2x00queue_kick_tx_queue(queue, &txdesc);
569 646
570 return 0; 647 return 0;
571} 648}
572 649
573int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev, 650int rt2x00queue_clear_beacon(struct rt2x00_dev *rt2x00dev,
574 struct ieee80211_vif *vif, 651 struct ieee80211_vif *vif)
575 const bool enable_beacon)
576{ 652{
577 struct rt2x00_intf *intf = vif_to_intf(vif); 653 struct rt2x00_intf *intf = vif_to_intf(vif);
578 struct skb_frame_desc *skbdesc;
579 struct txentry_desc txdesc;
580 654
581 if (unlikely(!intf->beacon)) 655 if (unlikely(!intf->beacon))
582 return -ENOBUFS; 656 return -ENOBUFS;
@@ -586,20 +660,38 @@ int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
586 /* 660 /*
587 * Clean up the beacon skb. 661 * Clean up the beacon skb.
588 */ 662 */
589 rt2x00queue_free_skb(rt2x00dev, intf->beacon->skb); 663 rt2x00queue_free_skb(intf->beacon);
590 intf->beacon->skb = NULL;
591 664
592 if (!enable_beacon) { 665 /*
593 rt2x00dev->ops->lib->kill_tx_queue(rt2x00dev, QID_BEACON); 666 * Clear beacon (single bssid devices don't need to clear the beacon
594 mutex_unlock(&intf->beacon_skb_mutex); 667 * since the beacon queue will get stopped anyway).
595 return 0; 668 */
596 } 669 if (rt2x00dev->ops->lib->clear_beacon)
670 rt2x00dev->ops->lib->clear_beacon(intf->beacon);
671
672 mutex_unlock(&intf->beacon_skb_mutex);
673
674 return 0;
675}
676
677int rt2x00queue_update_beacon_locked(struct rt2x00_dev *rt2x00dev,
678 struct ieee80211_vif *vif)
679{
680 struct rt2x00_intf *intf = vif_to_intf(vif);
681 struct skb_frame_desc *skbdesc;
682 struct txentry_desc txdesc;
683
684 if (unlikely(!intf->beacon))
685 return -ENOBUFS;
686
687 /*
688 * Clean up the beacon skb.
689 */
690 rt2x00queue_free_skb(intf->beacon);
597 691
598 intf->beacon->skb = ieee80211_beacon_get(rt2x00dev->hw, vif); 692 intf->beacon->skb = ieee80211_beacon_get(rt2x00dev->hw, vif);
599 if (!intf->beacon->skb) { 693 if (!intf->beacon->skb)
600 mutex_unlock(&intf->beacon_skb_mutex);
601 return -ENOMEM; 694 return -ENOMEM;
602 }
603 695
604 /* 696 /*
605 * Copy all TX descriptor information into txdesc, 697 * Copy all TX descriptor information into txdesc,
@@ -616,37 +708,81 @@ int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
616 skbdesc->entry = intf->beacon; 708 skbdesc->entry = intf->beacon;
617 709
618 /* 710 /*
619 * Send beacon to hardware and enable beacon genaration.. 711 * Send beacon to hardware.
620 */ 712 */
621 rt2x00dev->ops->lib->write_beacon(intf->beacon, &txdesc); 713 rt2x00dev->ops->lib->write_beacon(intf->beacon, &txdesc);
622 714
715 return 0;
716
717}
718
719int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
720 struct ieee80211_vif *vif)
721{
722 struct rt2x00_intf *intf = vif_to_intf(vif);
723 int ret;
724
725 mutex_lock(&intf->beacon_skb_mutex);
726 ret = rt2x00queue_update_beacon_locked(rt2x00dev, vif);
623 mutex_unlock(&intf->beacon_skb_mutex); 727 mutex_unlock(&intf->beacon_skb_mutex);
624 728
625 return 0; 729 return ret;
626} 730}
627 731
628struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev, 732bool rt2x00queue_for_each_entry(struct data_queue *queue,
629 const enum data_queue_qid queue) 733 enum queue_index start,
734 enum queue_index end,
735 void *data,
736 bool (*fn)(struct queue_entry *entry,
737 void *data))
630{ 738{
631 int atim = test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags); 739 unsigned long irqflags;
740 unsigned int index_start;
741 unsigned int index_end;
742 unsigned int i;
632 743
633 if (queue == QID_RX) 744 if (unlikely(start >= Q_INDEX_MAX || end >= Q_INDEX_MAX)) {
634 return rt2x00dev->rx; 745 ERROR(queue->rt2x00dev,
746 "Entry requested from invalid index range (%d - %d)\n",
747 start, end);
748 return true;
749 }
635 750
636 if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx) 751 /*
637 return &rt2x00dev->tx[queue]; 752 * Only protect the range we are going to loop over,
753 * if during our loop a extra entry is set to pending
754 * it should not be kicked during this run, since it
755 * is part of another TX operation.
756 */
757 spin_lock_irqsave(&queue->index_lock, irqflags);
758 index_start = queue->index[start];
759 index_end = queue->index[end];
760 spin_unlock_irqrestore(&queue->index_lock, irqflags);
638 761
639 if (!rt2x00dev->bcn) 762 /*
640 return NULL; 763 * Start from the TX done pointer, this guarantees that we will
764 * send out all frames in the correct order.
765 */
766 if (index_start < index_end) {
767 for (i = index_start; i < index_end; i++) {
768 if (fn(&queue->entries[i], data))
769 return true;
770 }
771 } else {
772 for (i = index_start; i < queue->limit; i++) {
773 if (fn(&queue->entries[i], data))
774 return true;
775 }
641 776
642 if (queue == QID_BEACON) 777 for (i = 0; i < index_end; i++) {
643 return &rt2x00dev->bcn[0]; 778 if (fn(&queue->entries[i], data))
644 else if (queue == QID_ATIM && atim) 779 return true;
645 return &rt2x00dev->bcn[1]; 780 }
781 }
646 782
647 return NULL; 783 return false;
648} 784}
649EXPORT_SYMBOL_GPL(rt2x00queue_get_queue); 785EXPORT_SYMBOL_GPL(rt2x00queue_for_each_entry);
650 786
651struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue, 787struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
652 enum queue_index index) 788 enum queue_index index)
@@ -660,18 +796,19 @@ struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
660 return NULL; 796 return NULL;
661 } 797 }
662 798
663 spin_lock_irqsave(&queue->lock, irqflags); 799 spin_lock_irqsave(&queue->index_lock, irqflags);
664 800
665 entry = &queue->entries[queue->index[index]]; 801 entry = &queue->entries[queue->index[index]];
666 802
667 spin_unlock_irqrestore(&queue->lock, irqflags); 803 spin_unlock_irqrestore(&queue->index_lock, irqflags);
668 804
669 return entry; 805 return entry;
670} 806}
671EXPORT_SYMBOL_GPL(rt2x00queue_get_entry); 807EXPORT_SYMBOL_GPL(rt2x00queue_get_entry);
672 808
673void rt2x00queue_index_inc(struct data_queue *queue, enum queue_index index) 809void rt2x00queue_index_inc(struct queue_entry *entry, enum queue_index index)
674{ 810{
811 struct data_queue *queue = entry->queue;
675 unsigned long irqflags; 812 unsigned long irqflags;
676 813
677 if (unlikely(index >= Q_INDEX_MAX)) { 814 if (unlikely(index >= Q_INDEX_MAX)) {
@@ -680,45 +817,233 @@ void rt2x00queue_index_inc(struct data_queue *queue, enum queue_index index)
680 return; 817 return;
681 } 818 }
682 819
683 spin_lock_irqsave(&queue->lock, irqflags); 820 spin_lock_irqsave(&queue->index_lock, irqflags);
684 821
685 queue->index[index]++; 822 queue->index[index]++;
686 if (queue->index[index] >= queue->limit) 823 if (queue->index[index] >= queue->limit)
687 queue->index[index] = 0; 824 queue->index[index] = 0;
688 825
826 entry->last_action = jiffies;
827
689 if (index == Q_INDEX) { 828 if (index == Q_INDEX) {
690 queue->length++; 829 queue->length++;
691 queue->last_index = jiffies;
692 } else if (index == Q_INDEX_DONE) { 830 } else if (index == Q_INDEX_DONE) {
693 queue->length--; 831 queue->length--;
694 queue->count++; 832 queue->count++;
695 queue->last_index_done = jiffies;
696 } 833 }
697 834
698 spin_unlock_irqrestore(&queue->lock, irqflags); 835 spin_unlock_irqrestore(&queue->index_lock, irqflags);
699} 836}
700 837
701static void rt2x00queue_reset(struct data_queue *queue) 838void rt2x00queue_pause_queue(struct data_queue *queue)
702{ 839{
703 unsigned long irqflags; 840 if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) ||
841 !test_bit(QUEUE_STARTED, &queue->flags) ||
842 test_and_set_bit(QUEUE_PAUSED, &queue->flags))
843 return;
704 844
705 spin_lock_irqsave(&queue->lock, irqflags); 845 switch (queue->qid) {
846 case QID_AC_VO:
847 case QID_AC_VI:
848 case QID_AC_BE:
849 case QID_AC_BK:
850 /*
851 * For TX queues, we have to disable the queue
852 * inside mac80211.
853 */
854 ieee80211_stop_queue(queue->rt2x00dev->hw, queue->qid);
855 break;
856 default:
857 break;
858 }
859}
860EXPORT_SYMBOL_GPL(rt2x00queue_pause_queue);
706 861
707 queue->count = 0; 862void rt2x00queue_unpause_queue(struct data_queue *queue)
708 queue->length = 0; 863{
709 queue->last_index = jiffies; 864 if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) ||
710 queue->last_index_done = jiffies; 865 !test_bit(QUEUE_STARTED, &queue->flags) ||
711 memset(queue->index, 0, sizeof(queue->index)); 866 !test_and_clear_bit(QUEUE_PAUSED, &queue->flags))
867 return;
712 868
713 spin_unlock_irqrestore(&queue->lock, irqflags); 869 switch (queue->qid) {
870 case QID_AC_VO:
871 case QID_AC_VI:
872 case QID_AC_BE:
873 case QID_AC_BK:
874 /*
875 * For TX queues, we have to enable the queue
876 * inside mac80211.
877 */
878 ieee80211_wake_queue(queue->rt2x00dev->hw, queue->qid);
879 break;
880 case QID_RX:
881 /*
882 * For RX we need to kick the queue now in order to
883 * receive frames.
884 */
885 queue->rt2x00dev->ops->lib->kick_queue(queue);
886 default:
887 break;
888 }
889}
890EXPORT_SYMBOL_GPL(rt2x00queue_unpause_queue);
891
892void rt2x00queue_start_queue(struct data_queue *queue)
893{
894 mutex_lock(&queue->status_lock);
895
896 if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) ||
897 test_and_set_bit(QUEUE_STARTED, &queue->flags)) {
898 mutex_unlock(&queue->status_lock);
899 return;
900 }
901
902 set_bit(QUEUE_PAUSED, &queue->flags);
903
904 queue->rt2x00dev->ops->lib->start_queue(queue);
905
906 rt2x00queue_unpause_queue(queue);
907
908 mutex_unlock(&queue->status_lock);
714} 909}
910EXPORT_SYMBOL_GPL(rt2x00queue_start_queue);
911
912void rt2x00queue_stop_queue(struct data_queue *queue)
913{
914 mutex_lock(&queue->status_lock);
915
916 if (!test_and_clear_bit(QUEUE_STARTED, &queue->flags)) {
917 mutex_unlock(&queue->status_lock);
918 return;
919 }
920
921 rt2x00queue_pause_queue(queue);
922
923 queue->rt2x00dev->ops->lib->stop_queue(queue);
924
925 mutex_unlock(&queue->status_lock);
926}
927EXPORT_SYMBOL_GPL(rt2x00queue_stop_queue);
928
929void rt2x00queue_flush_queue(struct data_queue *queue, bool drop)
930{
931 bool started;
932 bool tx_queue =
933 (queue->qid == QID_AC_VO) ||
934 (queue->qid == QID_AC_VI) ||
935 (queue->qid == QID_AC_BE) ||
936 (queue->qid == QID_AC_BK);
937
938 mutex_lock(&queue->status_lock);
939
940 /*
941 * If the queue has been started, we must stop it temporarily
942 * to prevent any new frames to be queued on the device. If
943 * we are not dropping the pending frames, the queue must
944 * only be stopped in the software and not the hardware,
945 * otherwise the queue will never become empty on its own.
946 */
947 started = test_bit(QUEUE_STARTED, &queue->flags);
948 if (started) {
949 /*
950 * Pause the queue
951 */
952 rt2x00queue_pause_queue(queue);
953
954 /*
955 * If we are not supposed to drop any pending
956 * frames, this means we must force a start (=kick)
957 * to the queue to make sure the hardware will
958 * start transmitting.
959 */
960 if (!drop && tx_queue)
961 queue->rt2x00dev->ops->lib->kick_queue(queue);
962 }
963
964 /*
965 * Check if driver supports flushing, if that is the case we can
966 * defer the flushing to the driver. Otherwise we must use the
967 * alternative which just waits for the queue to become empty.
968 */
969 if (likely(queue->rt2x00dev->ops->lib->flush_queue))
970 queue->rt2x00dev->ops->lib->flush_queue(queue, drop);
971
972 /*
973 * The queue flush has failed...
974 */
975 if (unlikely(!rt2x00queue_empty(queue)))
976 WARNING(queue->rt2x00dev, "Queue %d failed to flush\n", queue->qid);
977
978 /*
979 * Restore the queue to the previous status
980 */
981 if (started)
982 rt2x00queue_unpause_queue(queue);
983
984 mutex_unlock(&queue->status_lock);
985}
986EXPORT_SYMBOL_GPL(rt2x00queue_flush_queue);
987
988void rt2x00queue_start_queues(struct rt2x00_dev *rt2x00dev)
989{
990 struct data_queue *queue;
991
992 /*
993 * rt2x00queue_start_queue will call ieee80211_wake_queue
994 * for each queue after is has been properly initialized.
995 */
996 tx_queue_for_each(rt2x00dev, queue)
997 rt2x00queue_start_queue(queue);
998
999 rt2x00queue_start_queue(rt2x00dev->rx);
1000}
1001EXPORT_SYMBOL_GPL(rt2x00queue_start_queues);
715 1002
716void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev) 1003void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev)
717{ 1004{
718 struct data_queue *queue; 1005 struct data_queue *queue;
719 1006
720 txall_queue_for_each(rt2x00dev, queue) 1007 /*
721 rt2x00dev->ops->lib->kill_tx_queue(rt2x00dev, queue->qid); 1008 * rt2x00queue_stop_queue will call ieee80211_stop_queue
1009 * as well, but we are completely shutting doing everything
1010 * now, so it is much safer to stop all TX queues at once,
1011 * and use rt2x00queue_stop_queue for cleaning up.
1012 */
1013 ieee80211_stop_queues(rt2x00dev->hw);
1014
1015 tx_queue_for_each(rt2x00dev, queue)
1016 rt2x00queue_stop_queue(queue);
1017
1018 rt2x00queue_stop_queue(rt2x00dev->rx);
1019}
1020EXPORT_SYMBOL_GPL(rt2x00queue_stop_queues);
1021
1022void rt2x00queue_flush_queues(struct rt2x00_dev *rt2x00dev, bool drop)
1023{
1024 struct data_queue *queue;
1025
1026 tx_queue_for_each(rt2x00dev, queue)
1027 rt2x00queue_flush_queue(queue, drop);
1028
1029 rt2x00queue_flush_queue(rt2x00dev->rx, drop);
1030}
1031EXPORT_SYMBOL_GPL(rt2x00queue_flush_queues);
1032
1033static void rt2x00queue_reset(struct data_queue *queue)
1034{
1035 unsigned long irqflags;
1036 unsigned int i;
1037
1038 spin_lock_irqsave(&queue->index_lock, irqflags);
1039
1040 queue->count = 0;
1041 queue->length = 0;
1042
1043 for (i = 0; i < Q_INDEX_MAX; i++)
1044 queue->index[i] = 0;
1045
1046 spin_unlock_irqrestore(&queue->index_lock, irqflags);
722} 1047}
723 1048
724void rt2x00queue_init_queues(struct rt2x00_dev *rt2x00dev) 1049void rt2x00queue_init_queues(struct rt2x00_dev *rt2x00dev)
@@ -729,11 +1054,8 @@ void rt2x00queue_init_queues(struct rt2x00_dev *rt2x00dev)
729 queue_for_each(rt2x00dev, queue) { 1054 queue_for_each(rt2x00dev, queue) {
730 rt2x00queue_reset(queue); 1055 rt2x00queue_reset(queue);
731 1056
732 for (i = 0; i < queue->limit; i++) { 1057 for (i = 0; i < queue->limit; i++)
733 queue->entries[i].flags = 0;
734
735 rt2x00dev->ops->lib->clear_entry(&queue->entries[i]); 1058 rt2x00dev->ops->lib->clear_entry(&queue->entries[i]);
736 }
737 } 1059 }
738} 1060}
739 1061
@@ -755,13 +1077,13 @@ static int rt2x00queue_alloc_entries(struct data_queue *queue,
755 * Allocate all queue entries. 1077 * Allocate all queue entries.
756 */ 1078 */
757 entry_size = sizeof(*entries) + qdesc->priv_size; 1079 entry_size = sizeof(*entries) + qdesc->priv_size;
758 entries = kzalloc(queue->limit * entry_size, GFP_KERNEL); 1080 entries = kcalloc(queue->limit, entry_size, GFP_KERNEL);
759 if (!entries) 1081 if (!entries)
760 return -ENOMEM; 1082 return -ENOMEM;
761 1083
762#define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \ 1084#define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \
763 ( ((char *)(__base)) + ((__limit) * (__esize)) + \ 1085 (((char *)(__base)) + ((__limit) * (__esize)) + \
764 ((__index) * (__psize)) ) 1086 ((__index) * (__psize)))
765 1087
766 for (i = 0; i < queue->limit; i++) { 1088 for (i = 0; i < queue->limit; i++) {
767 entries[i].flags = 0; 1089 entries[i].flags = 0;
@@ -780,8 +1102,7 @@ static int rt2x00queue_alloc_entries(struct data_queue *queue,
780 return 0; 1102 return 0;
781} 1103}
782 1104
783static void rt2x00queue_free_skbs(struct rt2x00_dev *rt2x00dev, 1105static void rt2x00queue_free_skbs(struct data_queue *queue)
784 struct data_queue *queue)
785{ 1106{
786 unsigned int i; 1107 unsigned int i;
787 1108
@@ -789,19 +1110,17 @@ static void rt2x00queue_free_skbs(struct rt2x00_dev *rt2x00dev,
789 return; 1110 return;
790 1111
791 for (i = 0; i < queue->limit; i++) { 1112 for (i = 0; i < queue->limit; i++) {
792 if (queue->entries[i].skb) 1113 rt2x00queue_free_skb(&queue->entries[i]);
793 rt2x00queue_free_skb(rt2x00dev, queue->entries[i].skb);
794 } 1114 }
795} 1115}
796 1116
797static int rt2x00queue_alloc_rxskbs(struct rt2x00_dev *rt2x00dev, 1117static int rt2x00queue_alloc_rxskbs(struct data_queue *queue)
798 struct data_queue *queue)
799{ 1118{
800 unsigned int i; 1119 unsigned int i;
801 struct sk_buff *skb; 1120 struct sk_buff *skb;
802 1121
803 for (i = 0; i < queue->limit; i++) { 1122 for (i = 0; i < queue->limit; i++) {
804 skb = rt2x00queue_alloc_rxskb(rt2x00dev, &queue->entries[i]); 1123 skb = rt2x00queue_alloc_rxskb(&queue->entries[i]);
805 if (!skb) 1124 if (!skb)
806 return -ENOMEM; 1125 return -ENOMEM;
807 queue->entries[i].skb = skb; 1126 queue->entries[i].skb = skb;
@@ -829,14 +1148,14 @@ int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev)
829 if (status) 1148 if (status)
830 goto exit; 1149 goto exit;
831 1150
832 if (test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) { 1151 if (test_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags)) {
833 status = rt2x00queue_alloc_entries(&rt2x00dev->bcn[1], 1152 status = rt2x00queue_alloc_entries(rt2x00dev->atim,
834 rt2x00dev->ops->atim); 1153 rt2x00dev->ops->atim);
835 if (status) 1154 if (status)
836 goto exit; 1155 goto exit;
837 } 1156 }
838 1157
839 status = rt2x00queue_alloc_rxskbs(rt2x00dev, rt2x00dev->rx); 1158 status = rt2x00queue_alloc_rxskbs(rt2x00dev->rx);
840 if (status) 1159 if (status)
841 goto exit; 1160 goto exit;
842 1161
@@ -854,7 +1173,7 @@ void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev)
854{ 1173{
855 struct data_queue *queue; 1174 struct data_queue *queue;
856 1175
857 rt2x00queue_free_skbs(rt2x00dev, rt2x00dev->rx); 1176 rt2x00queue_free_skbs(rt2x00dev->rx);
858 1177
859 queue_for_each(rt2x00dev, queue) { 1178 queue_for_each(rt2x00dev, queue) {
860 kfree(queue->entries); 1179 kfree(queue->entries);
@@ -865,7 +1184,8 @@ void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev)
865static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev, 1184static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev,
866 struct data_queue *queue, enum data_queue_qid qid) 1185 struct data_queue *queue, enum data_queue_qid qid)
867{ 1186{
868 spin_lock_init(&queue->lock); 1187 mutex_init(&queue->status_lock);
1188 spin_lock_init(&queue->index_lock);
869 1189
870 queue->rt2x00dev = rt2x00dev; 1190 queue->rt2x00dev = rt2x00dev;
871 queue->qid = qid; 1191 queue->qid = qid;
@@ -880,7 +1200,7 @@ int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
880 struct data_queue *queue; 1200 struct data_queue *queue;
881 enum data_queue_qid qid; 1201 enum data_queue_qid qid;
882 unsigned int req_atim = 1202 unsigned int req_atim =
883 !!test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags); 1203 !!test_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
884 1204
885 /* 1205 /*
886 * We need the following queues: 1206 * We need the following queues:
@@ -891,7 +1211,7 @@ int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
891 */ 1211 */
892 rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim; 1212 rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim;
893 1213
894 queue = kzalloc(rt2x00dev->data_queues * sizeof(*queue), GFP_KERNEL); 1214 queue = kcalloc(rt2x00dev->data_queues, sizeof(*queue), GFP_KERNEL);
895 if (!queue) { 1215 if (!queue) {
896 ERROR(rt2x00dev, "Queue allocation failed.\n"); 1216 ERROR(rt2x00dev, "Queue allocation failed.\n");
897 return -ENOMEM; 1217 return -ENOMEM;
@@ -903,11 +1223,12 @@ int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
903 rt2x00dev->rx = queue; 1223 rt2x00dev->rx = queue;
904 rt2x00dev->tx = &queue[1]; 1224 rt2x00dev->tx = &queue[1];
905 rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues]; 1225 rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues];
1226 rt2x00dev->atim = req_atim ? &queue[2 + rt2x00dev->ops->tx_queues] : NULL;
906 1227
907 /* 1228 /*
908 * Initialize queue parameters. 1229 * Initialize queue parameters.
909 * RX: qid = QID_RX 1230 * RX: qid = QID_RX
910 * TX: qid = QID_AC_BE + index 1231 * TX: qid = QID_AC_VO + index
911 * TX: cw_min: 2^5 = 32. 1232 * TX: cw_min: 2^5 = 32.
912 * TX: cw_max: 2^10 = 1024. 1233 * TX: cw_max: 2^10 = 1024.
913 * BCN: qid = QID_BEACON 1234 * BCN: qid = QID_BEACON
@@ -915,13 +1236,13 @@ int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
915 */ 1236 */
916 rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX); 1237 rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX);
917 1238
918 qid = QID_AC_BE; 1239 qid = QID_AC_VO;
919 tx_queue_for_each(rt2x00dev, queue) 1240 tx_queue_for_each(rt2x00dev, queue)
920 rt2x00queue_init(rt2x00dev, queue, qid++); 1241 rt2x00queue_init(rt2x00dev, queue, qid++);
921 1242
922 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[0], QID_BEACON); 1243 rt2x00queue_init(rt2x00dev, rt2x00dev->bcn, QID_BEACON);
923 if (req_atim) 1244 if (req_atim)
924 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[1], QID_ATIM); 1245 rt2x00queue_init(rt2x00dev, rt2x00dev->atim, QID_ATIM);
925 1246
926 return 0; 1247 return 0;
927} 1248}
diff --git a/drivers/net/wireless/rt2x00/rt2x00queue.h b/drivers/net/wireless/rt2x00/rt2x00queue.h
index 191e7775a9c0..167d45873dca 100644
--- a/drivers/net/wireless/rt2x00/rt2x00queue.h
+++ b/drivers/net/wireless/rt2x00/rt2x00queue.h
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> 2 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
@@ -43,28 +43,12 @@
43#define AGGREGATION_SIZE 3840 43#define AGGREGATION_SIZE 3840
44 44
45/** 45/**
46 * DOC: Number of entries per queue
47 *
48 * Under normal load without fragmentation, 12 entries are sufficient
49 * without the queue being filled up to the maximum. When using fragmentation
50 * and the queue threshold code, we need to add some additional margins to
51 * make sure the queue will never (or only under extreme load) fill up
52 * completely.
53 * Since we don't use preallocated DMA, having a large number of queue entries
54 * will have minimal impact on the memory requirements for the queue.
55 */
56#define RX_ENTRIES 24
57#define TX_ENTRIES 24
58#define BEACON_ENTRIES 1
59#define ATIM_ENTRIES 8
60
61/**
62 * enum data_queue_qid: Queue identification 46 * enum data_queue_qid: Queue identification
63 * 47 *
48 * @QID_AC_VO: AC VO queue
49 * @QID_AC_VI: AC VI queue
64 * @QID_AC_BE: AC BE queue 50 * @QID_AC_BE: AC BE queue
65 * @QID_AC_BK: AC BK queue 51 * @QID_AC_BK: AC BK queue
66 * @QID_AC_VI: AC VI queue
67 * @QID_AC_VO: AC VO queue
68 * @QID_HCCA: HCCA queue 52 * @QID_HCCA: HCCA queue
69 * @QID_MGMT: MGMT queue (prio queue) 53 * @QID_MGMT: MGMT queue (prio queue)
70 * @QID_RX: RX queue 54 * @QID_RX: RX queue
@@ -73,10 +57,10 @@
73 * @QID_ATIM: Atim queue (value unspeficied, don't send it to device) 57 * @QID_ATIM: Atim queue (value unspeficied, don't send it to device)
74 */ 58 */
75enum data_queue_qid { 59enum data_queue_qid {
76 QID_AC_BE = 0, 60 QID_AC_VO = 0,
77 QID_AC_BK = 1, 61 QID_AC_VI = 1,
78 QID_AC_VI = 2, 62 QID_AC_BE = 2,
79 QID_AC_VO = 3, 63 QID_AC_BK = 3,
80 QID_HCCA = 4, 64 QID_HCCA = 4,
81 QID_MGMT = 13, 65 QID_MGMT = 13,
82 QID_RX = 14, 66 QID_RX = 14,
@@ -233,6 +217,7 @@ enum txdone_entry_desc_flags {
233 TXDONE_FALLBACK, 217 TXDONE_FALLBACK,
234 TXDONE_FAILURE, 218 TXDONE_FAILURE,
235 TXDONE_EXCESSIVE_RETRY, 219 TXDONE_EXCESSIVE_RETRY,
220 TXDONE_AMPDU,
236}; 221};
237 222
238/** 223/**
@@ -268,6 +253,7 @@ struct txdone_entry_desc {
268 * @ENTRY_TXD_HT_AMPDU: This frame is part of an AMPDU. 253 * @ENTRY_TXD_HT_AMPDU: This frame is part of an AMPDU.
269 * @ENTRY_TXD_HT_BW_40: Use 40MHz Bandwidth. 254 * @ENTRY_TXD_HT_BW_40: Use 40MHz Bandwidth.
270 * @ENTRY_TXD_HT_SHORT_GI: Use short GI. 255 * @ENTRY_TXD_HT_SHORT_GI: Use short GI.
256 * @ENTRY_TXD_HT_MIMO_PS: The receiving STA is in dynamic SM PS mode.
271 */ 257 */
272enum txentry_desc_flags { 258enum txentry_desc_flags {
273 ENTRY_TXD_RTS_FRAME, 259 ENTRY_TXD_RTS_FRAME,
@@ -286,6 +272,7 @@ enum txentry_desc_flags {
286 ENTRY_TXD_HT_AMPDU, 272 ENTRY_TXD_HT_AMPDU,
287 ENTRY_TXD_HT_BW_40, 273 ENTRY_TXD_HT_BW_40,
288 ENTRY_TXD_HT_SHORT_GI, 274 ENTRY_TXD_HT_SHORT_GI,
275 ENTRY_TXD_HT_MIMO_PS,
289}; 276};
290 277
291/** 278/**
@@ -294,7 +281,6 @@ enum txentry_desc_flags {
294 * Summary of information for the frame descriptor before sending a TX frame. 281 * Summary of information for the frame descriptor before sending a TX frame.
295 * 282 *
296 * @flags: Descriptor flags (See &enum queue_entry_flags). 283 * @flags: Descriptor flags (See &enum queue_entry_flags).
297 * @queue: Queue identification (See &enum data_queue_qid).
298 * @length: Length of the entire frame. 284 * @length: Length of the entire frame.
299 * @header_length: Length of 802.11 header. 285 * @header_length: Length of 802.11 header.
300 * @length_high: PLCP length high word. 286 * @length_high: PLCP length high word.
@@ -307,11 +293,8 @@ enum txentry_desc_flags {
307 * @rate_mode: Rate mode (See @enum rate_modulation). 293 * @rate_mode: Rate mode (See @enum rate_modulation).
308 * @mpdu_density: MDPU density. 294 * @mpdu_density: MDPU density.
309 * @retry_limit: Max number of retries. 295 * @retry_limit: Max number of retries.
310 * @aifs: AIFS value.
311 * @ifs: IFS value. 296 * @ifs: IFS value.
312 * @txop: IFS value for 11n capable chips. 297 * @txop: IFS value for 11n capable chips.
313 * @cw_min: cwmin value.
314 * @cw_max: cwmax value.
315 * @cipher: Cipher type used for encryption. 298 * @cipher: Cipher type used for encryption.
316 * @key_idx: Key index used for encryption. 299 * @key_idx: Key index used for encryption.
317 * @iv_offset: Position where IV should be inserted by hardware. 300 * @iv_offset: Position where IV should be inserted by hardware.
@@ -320,28 +303,30 @@ enum txentry_desc_flags {
320struct txentry_desc { 303struct txentry_desc {
321 unsigned long flags; 304 unsigned long flags;
322 305
323 enum data_queue_qid queue;
324
325 u16 length; 306 u16 length;
326 u16 header_length; 307 u16 header_length;
327 308
328 u16 length_high; 309 union {
329 u16 length_low; 310 struct {
330 u16 signal; 311 u16 length_high;
331 u16 service; 312 u16 length_low;
332 313 u16 signal;
333 u16 mcs; 314 u16 service;
334 u16 stbc; 315 enum ifs ifs;
335 u16 ba_size; 316 } plcp;
336 u16 rate_mode; 317
337 u16 mpdu_density; 318 struct {
319 u16 mcs;
320 u8 stbc;
321 u8 ba_size;
322 u8 mpdu_density;
323 enum txop txop;
324 } ht;
325 } u;
326
327 enum rate_modulation rate_mode;
338 328
339 short retry_limit; 329 short retry_limit;
340 short aifs;
341 short ifs;
342 short txop;
343 short cw_min;
344 short cw_max;
345 330
346 enum cipher cipher; 331 enum cipher cipher;
347 u16 key_idx; 332 u16 key_idx;
@@ -358,32 +343,38 @@ struct txentry_desc {
358 * @ENTRY_OWNER_DEVICE_DATA: This entry is owned by the device for data 343 * @ENTRY_OWNER_DEVICE_DATA: This entry is owned by the device for data
359 * transfer (either TX or RX depending on the queue). The entry should 344 * transfer (either TX or RX depending on the queue). The entry should
360 * only be touched after the device has signaled it is done with it. 345 * only be touched after the device has signaled it is done with it.
361 * @ENTRY_OWNER_DEVICE_CRYPTO: This entry is owned by the device for data
362 * encryption or decryption. The entry should only be touched after
363 * the device has signaled it is done with it.
364 * @ENTRY_DATA_PENDING: This entry contains a valid frame and is waiting 346 * @ENTRY_DATA_PENDING: This entry contains a valid frame and is waiting
365 * for the signal to start sending. 347 * for the signal to start sending.
348 * @ENTRY_DATA_IO_FAILED: Hardware indicated that an IO error occurred
349 * while transferring the data to the hardware. No TX status report will
350 * be expected from the hardware.
351 * @ENTRY_DATA_STATUS_PENDING: The entry has been send to the device and
352 * returned. It is now waiting for the status reporting before the
353 * entry can be reused again.
366 */ 354 */
367enum queue_entry_flags { 355enum queue_entry_flags {
368 ENTRY_BCN_ASSIGNED, 356 ENTRY_BCN_ASSIGNED,
369 ENTRY_OWNER_DEVICE_DATA, 357 ENTRY_OWNER_DEVICE_DATA,
370 ENTRY_OWNER_DEVICE_CRYPTO,
371 ENTRY_DATA_PENDING, 358 ENTRY_DATA_PENDING,
359 ENTRY_DATA_IO_FAILED,
360 ENTRY_DATA_STATUS_PENDING,
372}; 361};
373 362
374/** 363/**
375 * struct queue_entry: Entry inside the &struct data_queue 364 * struct queue_entry: Entry inside the &struct data_queue
376 * 365 *
377 * @flags: Entry flags, see &enum queue_entry_flags. 366 * @flags: Entry flags, see &enum queue_entry_flags.
367 * @last_action: Timestamp of last change.
378 * @queue: The data queue (&struct data_queue) to which this entry belongs. 368 * @queue: The data queue (&struct data_queue) to which this entry belongs.
379 * @skb: The buffer which is currently being transmitted (for TX queue), 369 * @skb: The buffer which is currently being transmitted (for TX queue),
380 * or used to directly recieve data in (for RX queue). 370 * or used to directly receive data in (for RX queue).
381 * @entry_idx: The entry index number. 371 * @entry_idx: The entry index number.
382 * @priv_data: Private data belonging to this queue entry. The pointer 372 * @priv_data: Private data belonging to this queue entry. The pointer
383 * points to data specific to a particular driver and queue type. 373 * points to data specific to a particular driver and queue type.
384 */ 374 */
385struct queue_entry { 375struct queue_entry {
386 unsigned long flags; 376 unsigned long flags;
377 unsigned long last_action;
387 378
388 struct data_queue *queue; 379 struct data_queue *queue;
389 380
@@ -399,29 +390,49 @@ struct queue_entry {
399 * 390 *
400 * @Q_INDEX: Index pointer to the current entry in the queue, if this entry is 391 * @Q_INDEX: Index pointer to the current entry in the queue, if this entry is
401 * owned by the hardware then the queue is considered to be full. 392 * owned by the hardware then the queue is considered to be full.
393 * @Q_INDEX_DMA_DONE: Index pointer for the next entry which will have been
394 * transferred to the hardware.
402 * @Q_INDEX_DONE: Index pointer to the next entry which will be completed by 395 * @Q_INDEX_DONE: Index pointer to the next entry which will be completed by
403 * the hardware and for which we need to run the txdone handler. If this 396 * the hardware and for which we need to run the txdone handler. If this
404 * entry is not owned by the hardware the queue is considered to be empty. 397 * entry is not owned by the hardware the queue is considered to be empty.
405 * @Q_INDEX_CRYPTO: Index pointer to the next entry which encryption/decription
406 * will be completed by the hardware next.
407 * @Q_INDEX_MAX: Keep last, used in &struct data_queue to determine the size 398 * @Q_INDEX_MAX: Keep last, used in &struct data_queue to determine the size
408 * of the index array. 399 * of the index array.
409 */ 400 */
410enum queue_index { 401enum queue_index {
411 Q_INDEX, 402 Q_INDEX,
403 Q_INDEX_DMA_DONE,
412 Q_INDEX_DONE, 404 Q_INDEX_DONE,
413 Q_INDEX_CRYPTO,
414 Q_INDEX_MAX, 405 Q_INDEX_MAX,
415}; 406};
416 407
417/** 408/**
409 * enum data_queue_flags: Status flags for data queues
410 *
411 * @QUEUE_STARTED: The queue has been started. Fox RX queues this means the
412 * device might be DMA'ing skbuffers. TX queues will accept skbuffers to
413 * be transmitted and beacon queues will start beaconing the configured
414 * beacons.
415 * @QUEUE_PAUSED: The queue has been started but is currently paused.
416 * When this bit is set, the queue has been stopped in mac80211,
417 * preventing new frames to be enqueued. However, a few frames
418 * might still appear shortly after the pausing...
419 */
420enum data_queue_flags {
421 QUEUE_STARTED,
422 QUEUE_PAUSED,
423};
424
425/**
418 * struct data_queue: Data queue 426 * struct data_queue: Data queue
419 * 427 *
420 * @rt2x00dev: Pointer to main &struct rt2x00dev where this queue belongs to. 428 * @rt2x00dev: Pointer to main &struct rt2x00dev where this queue belongs to.
421 * @entries: Base address of the &struct queue_entry which are 429 * @entries: Base address of the &struct queue_entry which are
422 * part of this queue. 430 * part of this queue.
423 * @qid: The queue identification, see &enum data_queue_qid. 431 * @qid: The queue identification, see &enum data_queue_qid.
424 * @lock: Spinlock to protect index handling. Whenever @index, @index_done or 432 * @flags: Entry flags, see &enum queue_entry_flags.
433 * @status_lock: The mutex for protecting the start/stop/flush
434 * handling on this queue.
435 * @index_lock: Spinlock to protect index handling. Whenever @index, @index_done or
425 * @index_crypt needs to be changed this lock should be grabbed to prevent 436 * @index_crypt needs to be changed this lock should be grabbed to prevent
426 * index corruption due to concurrency. 437 * index corruption due to concurrency.
427 * @count: Number of frames handled in the queue. 438 * @count: Number of frames handled in the queue.
@@ -444,10 +455,11 @@ struct data_queue {
444 struct queue_entry *entries; 455 struct queue_entry *entries;
445 456
446 enum data_queue_qid qid; 457 enum data_queue_qid qid;
458 unsigned long flags;
459
460 struct mutex status_lock;
461 spinlock_t index_lock;
447 462
448 spinlock_t lock;
449 unsigned long last_index;
450 unsigned long last_index_done;
451 unsigned int count; 463 unsigned int count;
452 unsigned short limit; 464 unsigned short limit;
453 unsigned short threshold; 465 unsigned short threshold;
@@ -565,6 +577,28 @@ struct data_queue_desc {
565 queue_loop(__entry, (__dev)->tx, queue_end(__dev)) 577 queue_loop(__entry, (__dev)->tx, queue_end(__dev))
566 578
567/** 579/**
580 * rt2x00queue_for_each_entry - Loop through all entries in the queue
581 * @queue: Pointer to @data_queue
582 * @start: &enum queue_index Pointer to start index
583 * @end: &enum queue_index Pointer to end index
584 * @data: Data to pass to the callback function
585 * @fn: The function to call for each &struct queue_entry
586 *
587 * This will walk through all entries in the queue, in chronological
588 * order. This means it will start at the current @start pointer
589 * and will walk through the queue until it reaches the @end pointer.
590 *
591 * If fn returns true for an entry rt2x00queue_for_each_entry will stop
592 * processing and return true as well.
593 */
594bool rt2x00queue_for_each_entry(struct data_queue *queue,
595 enum queue_index start,
596 enum queue_index end,
597 void *data,
598 bool (*fn)(struct queue_entry *entry,
599 void *data));
600
601/**
568 * rt2x00queue_empty - Check if the queue is empty. 602 * rt2x00queue_empty - Check if the queue is empty.
569 * @queue: Queue to check if empty. 603 * @queue: Queue to check if empty.
570 */ 604 */
@@ -601,12 +635,25 @@ static inline int rt2x00queue_threshold(struct data_queue *queue)
601} 635}
602 636
603/** 637/**
604 * rt2x00queue_timeout - Check if a timeout occured for this queue 638 * rt2x00queue_status_timeout - Check if a timeout occurred for STATUS reports
605 * @queue: Queue to check. 639 * @entry: Queue entry to check.
640 */
641static inline int rt2x00queue_status_timeout(struct queue_entry *entry)
642{
643 if (!test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
644 return false;
645 return time_after(jiffies, entry->last_action + msecs_to_jiffies(100));
646}
647
648/**
649 * rt2x00queue_dma_timeout - Check if a timeout occurred for DMA transfers
650 * @entry: Queue entry to check.
606 */ 651 */
607static inline int rt2x00queue_timeout(struct data_queue *queue) 652static inline int rt2x00queue_dma_timeout(struct queue_entry *entry)
608{ 653{
609 return time_after(queue->last_index, queue->last_index_done + (HZ / 10)); 654 if (!test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags))
655 return false;
656 return time_after(jiffies, entry->last_action + msecs_to_jiffies(100));
610} 657}
611 658
612/** 659/**
diff --git a/drivers/net/wireless/rt2x00/rt2x00reg.h b/drivers/net/wireless/rt2x00/rt2x00reg.h
index cef94621cef7..6f867eec49cc 100644
--- a/drivers/net/wireless/rt2x00/rt2x00reg.h
+++ b/drivers/net/wireless/rt2x00/rt2x00reg.h
@@ -83,14 +83,8 @@ enum dev_state {
83 */ 83 */
84 STATE_RADIO_ON, 84 STATE_RADIO_ON,
85 STATE_RADIO_OFF, 85 STATE_RADIO_OFF,
86 STATE_RADIO_RX_ON,
87 STATE_RADIO_RX_OFF,
88 STATE_RADIO_RX_ON_LINK,
89 STATE_RADIO_RX_OFF_LINK,
90 STATE_RADIO_IRQ_ON, 86 STATE_RADIO_IRQ_ON,
91 STATE_RADIO_IRQ_OFF, 87 STATE_RADIO_IRQ_OFF,
92 STATE_RADIO_IRQ_ON_ISR,
93 STATE_RADIO_IRQ_OFF_ISR,
94}; 88};
95 89
96/* 90/*
diff --git a/drivers/net/wireless/rt2x00/rt2x00soc.c b/drivers/net/wireless/rt2x00/rt2x00soc.c
index fc98063de71d..2aa5c38022f3 100644
--- a/drivers/net/wireless/rt2x00/rt2x00soc.c
+++ b/drivers/net/wireless/rt2x00/rt2x00soc.c
@@ -40,6 +40,8 @@ static void rt2x00soc_free_reg(struct rt2x00_dev *rt2x00dev)
40 40
41 kfree(rt2x00dev->eeprom); 41 kfree(rt2x00dev->eeprom);
42 rt2x00dev->eeprom = NULL; 42 rt2x00dev->eeprom = NULL;
43
44 iounmap(rt2x00dev->csr.base);
43} 45}
44 46
45static int rt2x00soc_alloc_reg(struct rt2x00_dev *rt2x00dev) 47static int rt2x00soc_alloc_reg(struct rt2x00_dev *rt2x00dev)
@@ -51,9 +53,9 @@ static int rt2x00soc_alloc_reg(struct rt2x00_dev *rt2x00dev)
51 if (!res) 53 if (!res)
52 return -ENODEV; 54 return -ENODEV;
53 55
54 rt2x00dev->csr.base = (void __iomem *)KSEG1ADDR(res->start); 56 rt2x00dev->csr.base = ioremap(res->start, resource_size(res));
55 if (!rt2x00dev->csr.base) 57 if (!rt2x00dev->csr.base)
56 goto exit; 58 return -ENOMEM;
57 59
58 rt2x00dev->eeprom = kzalloc(rt2x00dev->ops->eeprom_size, GFP_KERNEL); 60 rt2x00dev->eeprom = kzalloc(rt2x00dev->ops->eeprom_size, GFP_KERNEL);
59 if (!rt2x00dev->eeprom) 61 if (!rt2x00dev->eeprom)
diff --git a/drivers/net/wireless/rt2x00/rt2x00usb.c b/drivers/net/wireless/rt2x00/rt2x00usb.c
index ff3a36622d1b..8f90f6268077 100644
--- a/drivers/net/wireless/rt2x00/rt2x00usb.c
+++ b/drivers/net/wireless/rt2x00/rt2x00usb.c
@@ -1,5 +1,6 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 4 <http://rt2x00.serialmonkey.com>
4 5
5 This program is free software; you can redistribute it and/or modify 6 This program is free software; you can redistribute it and/or modify
@@ -164,221 +165,399 @@ int rt2x00usb_regbusy_read(struct rt2x00_dev *rt2x00dev,
164} 165}
165EXPORT_SYMBOL_GPL(rt2x00usb_regbusy_read); 166EXPORT_SYMBOL_GPL(rt2x00usb_regbusy_read);
166 167
167/* 168
168 * TX data handlers. 169struct rt2x00_async_read_data {
169 */ 170 __le32 reg;
170static void rt2x00usb_interrupt_txdone(struct urb *urb) 171 struct usb_ctrlrequest cr;
172 struct rt2x00_dev *rt2x00dev;
173 bool (*callback)(struct rt2x00_dev *, int, u32);
174};
175
176static void rt2x00usb_register_read_async_cb(struct urb *urb)
171{ 177{
172 struct queue_entry *entry = (struct queue_entry *)urb->context; 178 struct rt2x00_async_read_data *rd = urb->context;
173 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 179 if (rd->callback(rd->rt2x00dev, urb->status, le32_to_cpu(rd->reg))) {
174 struct txdone_entry_desc txdesc; 180 if (usb_submit_urb(urb, GFP_ATOMIC) < 0)
181 kfree(rd);
182 } else
183 kfree(rd);
184}
185
186void rt2x00usb_register_read_async(struct rt2x00_dev *rt2x00dev,
187 const unsigned int offset,
188 bool (*callback)(struct rt2x00_dev*, int, u32))
189{
190 struct usb_device *usb_dev = to_usb_device_intf(rt2x00dev->dev);
191 struct urb *urb;
192 struct rt2x00_async_read_data *rd;
193
194 rd = kmalloc(sizeof(*rd), GFP_ATOMIC);
195 if (!rd)
196 return;
175 197
176 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags) || 198 urb = usb_alloc_urb(0, GFP_ATOMIC);
177 !test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags)) 199 if (!urb) {
200 kfree(rd);
178 return; 201 return;
202 }
179 203
204 rd->rt2x00dev = rt2x00dev;
205 rd->callback = callback;
206 rd->cr.bRequestType = USB_VENDOR_REQUEST_IN;
207 rd->cr.bRequest = USB_MULTI_READ;
208 rd->cr.wValue = 0;
209 rd->cr.wIndex = cpu_to_le16(offset);
210 rd->cr.wLength = cpu_to_le16(sizeof(u32));
211
212 usb_fill_control_urb(urb, usb_dev, usb_rcvctrlpipe(usb_dev, 0),
213 (unsigned char *)(&rd->cr), &rd->reg, sizeof(rd->reg),
214 rt2x00usb_register_read_async_cb, rd);
215 if (usb_submit_urb(urb, GFP_ATOMIC) < 0)
216 kfree(rd);
217 usb_free_urb(urb);
218}
219EXPORT_SYMBOL_GPL(rt2x00usb_register_read_async);
220
221/*
222 * TX data handlers.
223 */
224static void rt2x00usb_work_txdone_entry(struct queue_entry *entry)
225{
180 /* 226 /*
181 * Obtain the status about this packet. 227 * If the transfer to hardware succeeded, it does not mean the
182 * Note that when the status is 0 it does not mean the
183 * frame was send out correctly. It only means the frame 228 * frame was send out correctly. It only means the frame
184 * was succesfully pushed to the hardware, we have no 229 * was successfully pushed to the hardware, we have no
185 * way to determine the transmission status right now. 230 * way to determine the transmission status right now.
186 * (Only indirectly by looking at the failed TX counters 231 * (Only indirectly by looking at the failed TX counters
187 * in the register). 232 * in the register).
188 */ 233 */
189 txdesc.flags = 0; 234 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags))
190 if (!urb->status) 235 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
191 __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
192 else 236 else
193 __set_bit(TXDONE_FAILURE, &txdesc.flags); 237 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
194 txdesc.retry = 0;
195
196 rt2x00lib_txdone(entry, &txdesc);
197} 238}
198 239
199static inline void rt2x00usb_kick_tx_entry(struct queue_entry *entry) 240static void rt2x00usb_work_txdone(struct work_struct *work)
200{ 241{
201 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 242 struct rt2x00_dev *rt2x00dev =
202 struct usb_device *usb_dev = to_usb_device_intf(rt2x00dev->dev); 243 container_of(work, struct rt2x00_dev, txdone_work);
203 struct queue_entry_priv_usb *entry_priv = entry->priv_data; 244 struct data_queue *queue;
204 u32 length; 245 struct queue_entry *entry;
205 246
206 if (test_and_clear_bit(ENTRY_DATA_PENDING, &entry->flags)) { 247 tx_queue_for_each(rt2x00dev, queue) {
207 /* 248 while (!rt2x00queue_empty(queue)) {
208 * USB devices cannot blindly pass the skb->len as the 249 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
209 * length of the data to usb_fill_bulk_urb. Pass the skb
210 * to the driver to determine what the length should be.
211 */
212 length = rt2x00dev->ops->lib->get_tx_data_len(entry);
213 250
214 usb_fill_bulk_urb(entry_priv->urb, usb_dev, 251 if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||
215 usb_sndbulkpipe(usb_dev, entry->queue->usb_endpoint), 252 !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
216 entry->skb->data, length, 253 break;
217 rt2x00usb_interrupt_txdone, entry);
218 254
219 usb_submit_urb(entry_priv->urb, GFP_ATOMIC); 255 rt2x00usb_work_txdone_entry(entry);
256 }
220 } 257 }
221} 258}
222 259
223void rt2x00usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev, 260static void rt2x00usb_interrupt_txdone(struct urb *urb)
224 const enum data_queue_qid qid)
225{ 261{
226 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, qid); 262 struct queue_entry *entry = (struct queue_entry *)urb->context;
227 unsigned long irqflags; 263 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
228 unsigned int index; 264
229 unsigned int index_done; 265 if (!test_and_clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags))
230 unsigned int i; 266 return;
267
268 if (rt2x00dev->ops->lib->tx_dma_done)
269 rt2x00dev->ops->lib->tx_dma_done(entry);
231 270
232 /* 271 /*
233 * Only protect the range we are going to loop over, 272 * Report the frame as DMA done
234 * if during our loop a extra entry is set to pending
235 * it should not be kicked during this run, since it
236 * is part of another TX operation.
237 */ 273 */
238 spin_lock_irqsave(&queue->lock, irqflags); 274 rt2x00lib_dmadone(entry);
239 index = queue->index[Q_INDEX];
240 index_done = queue->index[Q_INDEX_DONE];
241 spin_unlock_irqrestore(&queue->lock, irqflags);
242 275
243 /* 276 /*
244 * Start from the TX done pointer, this guarentees that we will 277 * Check if the frame was correctly uploaded
245 * send out all frames in the correct order.
246 */ 278 */
247 if (index_done < index) { 279 if (urb->status)
248 for (i = index_done; i < index; i++) 280 set_bit(ENTRY_DATA_IO_FAILED, &entry->flags);
249 rt2x00usb_kick_tx_entry(&queue->entries[i]);
250 } else {
251 for (i = index_done; i < queue->limit; i++)
252 rt2x00usb_kick_tx_entry(&queue->entries[i]);
253 281
254 for (i = 0; i < index; i++) 282 /*
255 rt2x00usb_kick_tx_entry(&queue->entries[i]); 283 * Schedule the delayed work for reading the TX status
256 } 284 * from the device.
285 */
286 if (!test_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags) ||
287 !kfifo_is_empty(&rt2x00dev->txstatus_fifo))
288 queue_work(rt2x00dev->workqueue, &rt2x00dev->txdone_work);
257} 289}
258EXPORT_SYMBOL_GPL(rt2x00usb_kick_tx_queue);
259 290
260void rt2x00usb_kill_tx_queue(struct rt2x00_dev *rt2x00dev, 291static bool rt2x00usb_kick_tx_entry(struct queue_entry *entry, void* data)
261 const enum data_queue_qid qid)
262{ 292{
263 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, qid); 293 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
264 struct queue_entry_priv_usb *entry_priv; 294 struct usb_device *usb_dev = to_usb_device_intf(rt2x00dev->dev);
265 struct queue_entry_priv_usb_bcn *bcn_priv; 295 struct queue_entry_priv_usb *entry_priv = entry->priv_data;
266 unsigned int i; 296 u32 length;
267 bool kill_guard; 297 int status;
268 298
269 /* 299 if (!test_and_clear_bit(ENTRY_DATA_PENDING, &entry->flags) ||
270 * When killing the beacon queue, we must also kill 300 test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
271 * the beacon guard byte. 301 return false;
272 */
273 kill_guard =
274 (qid == QID_BEACON) &&
275 (test_bit(DRIVER_REQUIRE_BEACON_GUARD, &rt2x00dev->flags));
276 302
277 /* 303 /*
278 * Cancel all entries. 304 * USB devices cannot blindly pass the skb->len as the
305 * length of the data to usb_fill_bulk_urb. Pass the skb
306 * to the driver to determine what the length should be.
279 */ 307 */
280 for (i = 0; i < queue->limit; i++) { 308 length = rt2x00dev->ops->lib->get_tx_data_len(entry);
281 entry_priv = queue->entries[i].priv_data; 309
282 usb_kill_urb(entry_priv->urb); 310 usb_fill_bulk_urb(entry_priv->urb, usb_dev,
311 usb_sndbulkpipe(usb_dev, entry->queue->usb_endpoint),
312 entry->skb->data, length,
313 rt2x00usb_interrupt_txdone, entry);
314
315 status = usb_submit_urb(entry_priv->urb, GFP_ATOMIC);
316 if (status) {
317 if (status == -ENODEV)
318 clear_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags);
319 set_bit(ENTRY_DATA_IO_FAILED, &entry->flags);
320 rt2x00lib_dmadone(entry);
321 }
322
323 return false;
324}
325
326/*
327 * RX data handlers.
328 */
329static void rt2x00usb_work_rxdone(struct work_struct *work)
330{
331 struct rt2x00_dev *rt2x00dev =
332 container_of(work, struct rt2x00_dev, rxdone_work);
333 struct queue_entry *entry;
334 struct skb_frame_desc *skbdesc;
335 u8 rxd[32];
336
337 while (!rt2x00queue_empty(rt2x00dev->rx)) {
338 entry = rt2x00queue_get_entry(rt2x00dev->rx, Q_INDEX_DONE);
339
340 if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||
341 !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
342 break;
283 343
284 /* 344 /*
285 * Kill guardian urb (if required by driver). 345 * Fill in desc fields of the skb descriptor
286 */ 346 */
287 if (kill_guard) { 347 skbdesc = get_skb_frame_desc(entry->skb);
288 bcn_priv = queue->entries[i].priv_data; 348 skbdesc->desc = rxd;
289 usb_kill_urb(bcn_priv->guardian_urb); 349 skbdesc->desc_len = entry->queue->desc_size;
290 } 350
351 /*
352 * Send the frame to rt2x00lib for further processing.
353 */
354 rt2x00lib_rxdone(entry);
291 } 355 }
292} 356}
293EXPORT_SYMBOL_GPL(rt2x00usb_kill_tx_queue);
294 357
295static void rt2x00usb_watchdog_reset_tx(struct data_queue *queue) 358static void rt2x00usb_interrupt_rxdone(struct urb *urb)
296{ 359{
297 struct queue_entry_priv_usb *entry_priv; 360 struct queue_entry *entry = (struct queue_entry *)urb->context;
298 unsigned short threshold = queue->threshold; 361 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
299 362
300 WARNING(queue->rt2x00dev, "TX queue %d timed out, invoke reset", queue->qid); 363 if (!test_and_clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags))
364 return;
301 365
302 /* 366 /*
303 * Temporarily disable the TX queue, this will force mac80211 367 * Report the frame as DMA done
304 * to use the other queues until this queue has been restored.
305 *
306 * Set the queue threshold to the queue limit. This prevents the
307 * queue from being enabled during the txdone handler.
308 */ 368 */
309 queue->threshold = queue->limit; 369 rt2x00lib_dmadone(entry);
310 ieee80211_stop_queue(queue->rt2x00dev->hw, queue->qid);
311 370
312 /* 371 /*
313 * Reset all currently uploaded TX frames. 372 * Check if the received data is simply too small
373 * to be actually valid, or if the urb is signaling
374 * a problem.
314 */ 375 */
315 while (!rt2x00queue_empty(queue)) { 376 if (urb->actual_length < entry->queue->desc_size || urb->status)
316 entry_priv = rt2x00queue_get_entry(queue, Q_INDEX_DONE)->priv_data; 377 set_bit(ENTRY_DATA_IO_FAILED, &entry->flags);
317 usb_kill_urb(entry_priv->urb);
318
319 /*
320 * We need a short delay here to wait for
321 * the URB to be canceled and invoked the tx_done handler.
322 */
323 udelay(200);
324 }
325 378
326 /* 379 /*
327 * The queue has been reset, and mac80211 is allowed to use the 380 * Schedule the delayed work for reading the RX status
328 * queue again. 381 * from the device.
329 */ 382 */
330 queue->threshold = threshold; 383 queue_work(rt2x00dev->workqueue, &rt2x00dev->rxdone_work);
331 ieee80211_wake_queue(queue->rt2x00dev->hw, queue->qid);
332} 384}
333 385
334void rt2x00usb_watchdog(struct rt2x00_dev *rt2x00dev) 386static bool rt2x00usb_kick_rx_entry(struct queue_entry *entry, void* data)
335{ 387{
336 struct data_queue *queue; 388 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
389 struct usb_device *usb_dev = to_usb_device_intf(rt2x00dev->dev);
390 struct queue_entry_priv_usb *entry_priv = entry->priv_data;
391 int status;
337 392
338 tx_queue_for_each(rt2x00dev, queue) { 393 if (test_and_set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||
339 if (rt2x00queue_timeout(queue)) 394 test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
340 rt2x00usb_watchdog_reset_tx(queue); 395 return false;
396
397 rt2x00lib_dmastart(entry);
398
399 usb_fill_bulk_urb(entry_priv->urb, usb_dev,
400 usb_rcvbulkpipe(usb_dev, entry->queue->usb_endpoint),
401 entry->skb->data, entry->skb->len,
402 rt2x00usb_interrupt_rxdone, entry);
403
404 status = usb_submit_urb(entry_priv->urb, GFP_ATOMIC);
405 if (status) {
406 if (status == -ENODEV)
407 clear_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags);
408 set_bit(ENTRY_DATA_IO_FAILED, &entry->flags);
409 rt2x00lib_dmadone(entry);
341 } 410 }
411
412 return false;
342} 413}
343EXPORT_SYMBOL_GPL(rt2x00usb_watchdog);
344 414
345/* 415void rt2x00usb_kick_queue(struct data_queue *queue)
346 * RX data handlers. 416{
347 */ 417 switch (queue->qid) {
348static void rt2x00usb_interrupt_rxdone(struct urb *urb) 418 case QID_AC_VO:
419 case QID_AC_VI:
420 case QID_AC_BE:
421 case QID_AC_BK:
422 if (!rt2x00queue_empty(queue))
423 rt2x00queue_for_each_entry(queue,
424 Q_INDEX_DONE,
425 Q_INDEX,
426 NULL,
427 rt2x00usb_kick_tx_entry);
428 break;
429 case QID_RX:
430 if (!rt2x00queue_full(queue))
431 rt2x00queue_for_each_entry(queue,
432 Q_INDEX_DONE,
433 Q_INDEX,
434 NULL,
435 rt2x00usb_kick_rx_entry);
436 break;
437 default:
438 break;
439 }
440}
441EXPORT_SYMBOL_GPL(rt2x00usb_kick_queue);
442
443static bool rt2x00usb_flush_entry(struct queue_entry *entry, void* data)
349{ 444{
350 struct queue_entry *entry = (struct queue_entry *)urb->context;
351 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 445 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
352 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 446 struct queue_entry_priv_usb *entry_priv = entry->priv_data;
353 u8 rxd[32]; 447 struct queue_entry_priv_usb_bcn *bcn_priv = entry->priv_data;
354 448
355 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags) || 449 if (!test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags))
356 !test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags)) 450 return false;
357 return;
358 451
359 /* 452 usb_kill_urb(entry_priv->urb);
360 * Check if the received data is simply too small
361 * to be actually valid, or if the urb is signaling
362 * a problem.
363 */
364 if (urb->actual_length < entry->queue->desc_size || urb->status) {
365 set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
366 usb_submit_urb(urb, GFP_ATOMIC);
367 return;
368 }
369 453
370 /* 454 /*
371 * Fill in desc fields of the skb descriptor 455 * Kill guardian urb (if required by driver).
372 */ 456 */
373 skbdesc->desc = rxd; 457 if ((entry->queue->qid == QID_BEACON) &&
374 skbdesc->desc_len = entry->queue->desc_size; 458 (test_bit(REQUIRE_BEACON_GUARD, &rt2x00dev->cap_flags)))
459 usb_kill_urb(bcn_priv->guardian_urb);
460
461 return false;
462}
463
464void rt2x00usb_flush_queue(struct data_queue *queue, bool drop)
465{
466 struct work_struct *completion;
467 unsigned int i;
468
469 if (drop)
470 rt2x00queue_for_each_entry(queue, Q_INDEX_DONE, Q_INDEX, NULL,
471 rt2x00usb_flush_entry);
375 472
376 /* 473 /*
377 * Send the frame to rt2x00lib for further processing. 474 * Obtain the queue completion handler
378 */ 475 */
379 rt2x00lib_rxdone(rt2x00dev, entry); 476 switch (queue->qid) {
477 case QID_AC_VO:
478 case QID_AC_VI:
479 case QID_AC_BE:
480 case QID_AC_BK:
481 completion = &queue->rt2x00dev->txdone_work;
482 break;
483 case QID_RX:
484 completion = &queue->rt2x00dev->rxdone_work;
485 break;
486 default:
487 return;
488 }
489
490 for (i = 0; i < 10; i++) {
491 /*
492 * Check if the driver is already done, otherwise we
493 * have to sleep a little while to give the driver/hw
494 * the oppurtunity to complete interrupt process itself.
495 */
496 if (rt2x00queue_empty(queue))
497 break;
498
499 /*
500 * Schedule the completion handler manually, when this
501 * worker function runs, it should cleanup the queue.
502 */
503 queue_work(queue->rt2x00dev->workqueue, completion);
504
505 /*
506 * Wait for a little while to give the driver
507 * the oppurtunity to recover itself.
508 */
509 msleep(10);
510 }
511}
512EXPORT_SYMBOL_GPL(rt2x00usb_flush_queue);
513
514static void rt2x00usb_watchdog_tx_dma(struct data_queue *queue)
515{
516 WARNING(queue->rt2x00dev, "TX queue %d DMA timed out,"
517 " invoke forced forced reset\n", queue->qid);
518
519 rt2x00queue_flush_queue(queue, true);
520}
521
522static void rt2x00usb_watchdog_tx_status(struct data_queue *queue)
523{
524 WARNING(queue->rt2x00dev, "TX queue %d status timed out,"
525 " invoke forced tx handler\n", queue->qid);
526
527 queue_work(queue->rt2x00dev->workqueue, &queue->rt2x00dev->txdone_work);
380} 528}
381 529
530static int rt2x00usb_status_timeout(struct data_queue *queue)
531{
532 struct queue_entry *entry;
533
534 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
535 return rt2x00queue_status_timeout(entry);
536}
537
538static int rt2x00usb_dma_timeout(struct data_queue *queue)
539{
540 struct queue_entry *entry;
541
542 entry = rt2x00queue_get_entry(queue, Q_INDEX_DMA_DONE);
543 return rt2x00queue_dma_timeout(entry);
544}
545
546void rt2x00usb_watchdog(struct rt2x00_dev *rt2x00dev)
547{
548 struct data_queue *queue;
549
550 tx_queue_for_each(rt2x00dev, queue) {
551 if (!rt2x00queue_empty(queue)) {
552 if (rt2x00usb_dma_timeout(queue))
553 rt2x00usb_watchdog_tx_dma(queue);
554 if (rt2x00usb_status_timeout(queue))
555 rt2x00usb_watchdog_tx_status(queue);
556 }
557 }
558}
559EXPORT_SYMBOL_GPL(rt2x00usb_watchdog);
560
382/* 561/*
383 * Radio handlers 562 * Radio handlers
384 */ 563 */
@@ -386,12 +565,6 @@ void rt2x00usb_disable_radio(struct rt2x00_dev *rt2x00dev)
386{ 565{
387 rt2x00usb_vendor_request_sw(rt2x00dev, USB_RX_CONTROL, 0, 0, 566 rt2x00usb_vendor_request_sw(rt2x00dev, USB_RX_CONTROL, 0, 0,
388 REGISTER_TIMEOUT); 567 REGISTER_TIMEOUT);
389
390 /*
391 * The USB version of kill_tx_queue also works
392 * on the RX queue.
393 */
394 rt2x00dev->ops->lib->kill_tx_queue(rt2x00dev, QID_RX);
395} 568}
396EXPORT_SYMBOL_GPL(rt2x00usb_disable_radio); 569EXPORT_SYMBOL_GPL(rt2x00usb_disable_radio);
397 570
@@ -400,22 +573,10 @@ EXPORT_SYMBOL_GPL(rt2x00usb_disable_radio);
400 */ 573 */
401void rt2x00usb_clear_entry(struct queue_entry *entry) 574void rt2x00usb_clear_entry(struct queue_entry *entry)
402{ 575{
403 struct usb_device *usb_dev = 576 entry->flags = 0;
404 to_usb_device_intf(entry->queue->rt2x00dev->dev);
405 struct queue_entry_priv_usb *entry_priv = entry->priv_data;
406 int pipe;
407
408 if (entry->queue->qid == QID_RX) {
409 pipe = usb_rcvbulkpipe(usb_dev, entry->queue->usb_endpoint);
410 usb_fill_bulk_urb(entry_priv->urb, usb_dev, pipe,
411 entry->skb->data, entry->skb->len,
412 rt2x00usb_interrupt_rxdone, entry);
413 577
414 set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags); 578 if (entry->queue->qid == QID_RX)
415 usb_submit_urb(entry_priv->urb, GFP_ATOMIC); 579 rt2x00usb_kick_rx_entry(entry, NULL);
416 } else {
417 entry->flags = 0;
418 }
419} 580}
420EXPORT_SYMBOL_GPL(rt2x00usb_clear_entry); 581EXPORT_SYMBOL_GPL(rt2x00usb_clear_entry);
421 582
@@ -489,9 +650,9 @@ static int rt2x00usb_find_endpoints(struct rt2x00_dev *rt2x00dev)
489 return 0; 650 return 0;
490} 651}
491 652
492static int rt2x00usb_alloc_urb(struct rt2x00_dev *rt2x00dev, 653static int rt2x00usb_alloc_entries(struct data_queue *queue)
493 struct data_queue *queue)
494{ 654{
655 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
495 struct queue_entry_priv_usb *entry_priv; 656 struct queue_entry_priv_usb *entry_priv;
496 struct queue_entry_priv_usb_bcn *bcn_priv; 657 struct queue_entry_priv_usb_bcn *bcn_priv;
497 unsigned int i; 658 unsigned int i;
@@ -508,8 +669,8 @@ static int rt2x00usb_alloc_urb(struct rt2x00_dev *rt2x00dev,
508 * no guardian byte was required for the beacon, 669 * no guardian byte was required for the beacon,
509 * then we are done. 670 * then we are done.
510 */ 671 */
511 if (rt2x00dev->bcn != queue || 672 if (queue->qid != QID_BEACON ||
512 !test_bit(DRIVER_REQUIRE_BEACON_GUARD, &rt2x00dev->flags)) 673 !test_bit(REQUIRE_BEACON_GUARD, &rt2x00dev->cap_flags))
513 return 0; 674 return 0;
514 675
515 for (i = 0; i < queue->limit; i++) { 676 for (i = 0; i < queue->limit; i++) {
@@ -522,9 +683,9 @@ static int rt2x00usb_alloc_urb(struct rt2x00_dev *rt2x00dev,
522 return 0; 683 return 0;
523} 684}
524 685
525static void rt2x00usb_free_urb(struct rt2x00_dev *rt2x00dev, 686static void rt2x00usb_free_entries(struct data_queue *queue)
526 struct data_queue *queue)
527{ 687{
688 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
528 struct queue_entry_priv_usb *entry_priv; 689 struct queue_entry_priv_usb *entry_priv;
529 struct queue_entry_priv_usb_bcn *bcn_priv; 690 struct queue_entry_priv_usb_bcn *bcn_priv;
530 unsigned int i; 691 unsigned int i;
@@ -543,8 +704,8 @@ static void rt2x00usb_free_urb(struct rt2x00_dev *rt2x00dev,
543 * no guardian byte was required for the beacon, 704 * no guardian byte was required for the beacon,
544 * then we are done. 705 * then we are done.
545 */ 706 */
546 if (rt2x00dev->bcn != queue || 707 if (queue->qid != QID_BEACON ||
547 !test_bit(DRIVER_REQUIRE_BEACON_GUARD, &rt2x00dev->flags)) 708 !test_bit(REQUIRE_BEACON_GUARD, &rt2x00dev->cap_flags))
548 return; 709 return;
549 710
550 for (i = 0; i < queue->limit; i++) { 711 for (i = 0; i < queue->limit; i++) {
@@ -570,7 +731,7 @@ int rt2x00usb_initialize(struct rt2x00_dev *rt2x00dev)
570 * Allocate DMA 731 * Allocate DMA
571 */ 732 */
572 queue_for_each(rt2x00dev, queue) { 733 queue_for_each(rt2x00dev, queue) {
573 status = rt2x00usb_alloc_urb(rt2x00dev, queue); 734 status = rt2x00usb_alloc_entries(queue);
574 if (status) 735 if (status)
575 goto exit; 736 goto exit;
576 } 737 }
@@ -589,7 +750,7 @@ void rt2x00usb_uninitialize(struct rt2x00_dev *rt2x00dev)
589 struct data_queue *queue; 750 struct data_queue *queue;
590 751
591 queue_for_each(rt2x00dev, queue) 752 queue_for_each(rt2x00dev, queue)
592 rt2x00usb_free_urb(rt2x00dev, queue); 753 rt2x00usb_free_entries(queue);
593} 754}
594EXPORT_SYMBOL_GPL(rt2x00usb_uninitialize); 755EXPORT_SYMBOL_GPL(rt2x00usb_uninitialize);
595 756
@@ -633,10 +794,9 @@ exit:
633} 794}
634 795
635int rt2x00usb_probe(struct usb_interface *usb_intf, 796int rt2x00usb_probe(struct usb_interface *usb_intf,
636 const struct usb_device_id *id) 797 const struct rt2x00_ops *ops)
637{ 798{
638 struct usb_device *usb_dev = interface_to_usbdev(usb_intf); 799 struct usb_device *usb_dev = interface_to_usbdev(usb_intf);
639 struct rt2x00_ops *ops = (struct rt2x00_ops *)id->driver_info;
640 struct ieee80211_hw *hw; 800 struct ieee80211_hw *hw;
641 struct rt2x00_dev *rt2x00dev; 801 struct rt2x00_dev *rt2x00dev;
642 int retval; 802 int retval;
@@ -659,6 +819,10 @@ int rt2x00usb_probe(struct usb_interface *usb_intf,
659 819
660 rt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_USB); 820 rt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_USB);
661 821
822 INIT_WORK(&rt2x00dev->rxdone_work, rt2x00usb_work_rxdone);
823 INIT_WORK(&rt2x00dev->txdone_work, rt2x00usb_work_txdone);
824 init_timer(&rt2x00dev->txstatus_timer);
825
662 retval = rt2x00usb_alloc_reg(rt2x00dev); 826 retval = rt2x00usb_alloc_reg(rt2x00dev);
663 if (retval) 827 if (retval)
664 goto exit_free_device; 828 goto exit_free_device;
diff --git a/drivers/net/wireless/rt2x00/rt2x00usb.h b/drivers/net/wireless/rt2x00/rt2x00usb.h
index d3d3ddc40875..323ca7b2b095 100644
--- a/drivers/net/wireless/rt2x00/rt2x00usb.h
+++ b/drivers/net/wireless/rt2x00/rt2x00usb.h
@@ -35,12 +35,6 @@
35}) 35})
36 36
37/* 37/*
38 * This variable should be used with the
39 * usb_driver structure initialization.
40 */
41#define USB_DEVICE_DATA(__ops) .driver_info = (kernel_ulong_t)(__ops)
42
43/*
44 * For USB vendor requests we need to pass a timeout 38 * For USB vendor requests we need to pass a timeout
45 * time in ms, for this we use the REGISTER_TIMEOUT, 39 * time in ms, for this we use the REGISTER_TIMEOUT,
46 * however when loading firmware a higher value is 40 * however when loading firmware a higher value is
@@ -345,6 +339,23 @@ int rt2x00usb_regbusy_read(struct rt2x00_dev *rt2x00dev,
345 const struct rt2x00_field32 field, 339 const struct rt2x00_field32 field,
346 u32 *reg); 340 u32 *reg);
347 341
342/**
343 * rt2x00usb_register_read_async - Asynchronously read 32bit register word
344 * @rt2x00dev: Device pointer, see &struct rt2x00_dev.
345 * @offset: Register offset
346 * @callback: Functon to call when read completes.
347 *
348 * Submit a control URB to read a 32bit register. This safe to
349 * be called from atomic context. The callback will be called
350 * when the URB completes. Otherwise the function is similar
351 * to rt2x00usb_register_read().
352 * When the callback function returns false, the memory will be cleaned up,
353 * when it returns true, the urb will be fired again.
354 */
355void rt2x00usb_register_read_async(struct rt2x00_dev *rt2x00dev,
356 const unsigned int offset,
357 bool (*callback)(struct rt2x00_dev*, int, u32));
358
348/* 359/*
349 * Radio handlers 360 * Radio handlers
350 */ 361 */
@@ -378,33 +389,31 @@ struct queue_entry_priv_usb_bcn {
378}; 389};
379 390
380/** 391/**
381 * rt2x00usb_kick_tx_queue - Kick data queue 392 * rt2x00usb_kick_queue - Kick data queue
382 * @rt2x00dev: Pointer to &struct rt2x00_dev 393 * @queue: Data queue to kick
383 * @qid: Data queue to kick
384 * 394 *
385 * This will walk through all entries of the queue and push all pending 395 * This will walk through all entries of the queue and push all pending
386 * frames to the hardware as a single burst. 396 * frames to the hardware as a single burst.
387 */ 397 */
388void rt2x00usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev, 398void rt2x00usb_kick_queue(struct data_queue *queue);
389 const enum data_queue_qid qid);
390 399
391/** 400/**
392 * rt2x00usb_kill_tx_queue - Kill data queue 401 * rt2x00usb_flush_queue - Flush data queue
393 * @rt2x00dev: Pointer to &struct rt2x00_dev 402 * @queue: Data queue to stop
394 * @qid: Data queue to kill 403 * @drop: True to drop all pending frames.
395 * 404 *
396 * This will walk through all entries of the queue and kill all 405 * This will walk through all entries of the queue and will optionally
397 * previously kicked frames before they can be send. 406 * kill all URB's which were send to the device, or at least wait until
407 * they have been returned from the device..
398 */ 408 */
399void rt2x00usb_kill_tx_queue(struct rt2x00_dev *rt2x00dev, 409void rt2x00usb_flush_queue(struct data_queue *queue, bool drop);
400 const enum data_queue_qid qid);
401 410
402/** 411/**
403 * rt2x00usb_watchdog - Watchdog for USB communication 412 * rt2x00usb_watchdog - Watchdog for USB communication
404 * @rt2x00dev: Pointer to &struct rt2x00_dev 413 * @rt2x00dev: Pointer to &struct rt2x00_dev
405 * 414 *
406 * Check the health of the USB communication and determine 415 * Check the health of the USB communication and determine
407 * if timeouts have occured. If this is the case, this function 416 * if timeouts have occurred. If this is the case, this function
408 * will reset all communication to restore functionality again. 417 * will reset all communication to restore functionality again.
409 */ 418 */
410void rt2x00usb_watchdog(struct rt2x00_dev *rt2x00dev); 419void rt2x00usb_watchdog(struct rt2x00_dev *rt2x00dev);
@@ -420,7 +429,7 @@ void rt2x00usb_uninitialize(struct rt2x00_dev *rt2x00dev);
420 * USB driver handlers. 429 * USB driver handlers.
421 */ 430 */
422int rt2x00usb_probe(struct usb_interface *usb_intf, 431int rt2x00usb_probe(struct usb_interface *usb_intf,
423 const struct usb_device_id *id); 432 const struct rt2x00_ops *ops);
424void rt2x00usb_disconnect(struct usb_interface *usb_intf); 433void rt2x00usb_disconnect(struct usb_interface *usb_intf);
425#ifdef CONFIG_PM 434#ifdef CONFIG_PM
426int rt2x00usb_suspend(struct usb_interface *usb_intf, pm_message_t state); 435int rt2x00usb_suspend(struct usb_interface *usb_intf, pm_message_t state);
diff --git a/drivers/net/wireless/rt2x00/rt61pci.c b/drivers/net/wireless/rt2x00/rt61pci.c
index e539c6cb636f..9d35ec16a3a5 100644
--- a/drivers/net/wireless/rt2x00/rt61pci.c
+++ b/drivers/net/wireless/rt2x00/rt61pci.c
@@ -551,26 +551,14 @@ static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
551 struct rt2x00intf_conf *conf, 551 struct rt2x00intf_conf *conf,
552 const unsigned int flags) 552 const unsigned int flags)
553{ 553{
554 unsigned int beacon_base;
555 u32 reg; 554 u32 reg;
556 555
557 if (flags & CONFIG_UPDATE_TYPE) { 556 if (flags & CONFIG_UPDATE_TYPE) {
558 /* 557 /*
559 * Clear current synchronisation setup.
560 * For the Beacon base registers, we only need to clear
561 * the first byte since that byte contains the VALID and OWNER
562 * bits which (when set to 0) will invalidate the entire beacon.
563 */
564 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
565 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
566
567 /*
568 * Enable synchronisation. 558 * Enable synchronisation.
569 */ 559 */
570 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg); 560 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
571 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
572 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync); 561 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
573 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
574 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); 562 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
575 } 563 }
576 564
@@ -594,7 +582,8 @@ static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
594} 582}
595 583
596static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev, 584static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
597 struct rt2x00lib_erp *erp) 585 struct rt2x00lib_erp *erp,
586 u32 changed)
598{ 587{
599 u32 reg; 588 u32 reg;
600 589
@@ -603,28 +592,36 @@ static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
603 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); 592 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
604 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); 593 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
605 594
606 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg); 595 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
607 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1); 596 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
608 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE, 597 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
609 !!erp->short_preamble); 598 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
610 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg); 599 !!erp->short_preamble);
600 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
601 }
611 602
612 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates); 603 if (changed & BSS_CHANGED_BASIC_RATES)
604 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5,
605 erp->basic_rates);
613 606
614 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg); 607 if (changed & BSS_CHANGED_BEACON_INT) {
615 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 608 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
616 erp->beacon_int * 16); 609 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
617 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); 610 erp->beacon_int * 16);
611 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
612 }
618 613
619 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg); 614 if (changed & BSS_CHANGED_ERP_SLOT) {
620 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time); 615 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
621 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg); 616 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
617 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
622 618
623 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg); 619 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
624 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs); 620 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
625 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); 621 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
626 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs); 622 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
627 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg); 623 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
624 }
628} 625}
629 626
630static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev, 627static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
@@ -686,7 +683,7 @@ static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
686 683
687 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529)); 684 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529));
688 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 685 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
689 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)); 686 !test_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags));
690 687
691 /* 688 /*
692 * Configure the RX antenna. 689 * Configure the RX antenna.
@@ -814,10 +811,10 @@ static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
814 811
815 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { 812 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
816 sel = antenna_sel_a; 813 sel = antenna_sel_a;
817 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags); 814 lna = test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
818 } else { 815 } else {
819 sel = antenna_sel_bg; 816 sel = antenna_sel_bg;
820 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags); 817 lna = test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
821 } 818 }
822 819
823 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++) 820 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
@@ -837,7 +834,7 @@ static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
837 else if (rt2x00_rf(rt2x00dev, RF2527)) 834 else if (rt2x00_rf(rt2x00dev, RF2527))
838 rt61pci_config_antenna_2x(rt2x00dev, ant); 835 rt61pci_config_antenna_2x(rt2x00dev, ant);
839 else if (rt2x00_rf(rt2x00dev, RF2529)) { 836 else if (rt2x00_rf(rt2x00dev, RF2529)) {
840 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) 837 if (test_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags))
841 rt61pci_config_antenna_2x(rt2x00dev, ant); 838 rt61pci_config_antenna_2x(rt2x00dev, ant);
842 else 839 else
843 rt61pci_config_antenna_2529(rt2x00dev, ant); 840 rt61pci_config_antenna_2529(rt2x00dev, ant);
@@ -851,13 +848,13 @@ static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
851 short lna_gain = 0; 848 short lna_gain = 0;
852 849
853 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) { 850 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
854 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) 851 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags))
855 lna_gain += 14; 852 lna_gain += 14;
856 853
857 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom); 854 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
858 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1); 855 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
859 } else { 856 } else {
860 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) 857 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
861 lna_gain += 14; 858 lna_gain += 14;
862 859
863 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom); 860 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
@@ -1050,17 +1047,17 @@ static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1050 /* 1047 /*
1051 * Determine r17 bounds. 1048 * Determine r17 bounds.
1052 */ 1049 */
1053 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) { 1050 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1054 low_bound = 0x28; 1051 low_bound = 0x28;
1055 up_bound = 0x48; 1052 up_bound = 0x48;
1056 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) { 1053 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags)) {
1057 low_bound += 0x10; 1054 low_bound += 0x10;
1058 up_bound += 0x10; 1055 up_bound += 0x10;
1059 } 1056 }
1060 } else { 1057 } else {
1061 low_bound = 0x20; 1058 low_bound = 0x20;
1062 up_bound = 0x40; 1059 up_bound = 0x40;
1063 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) { 1060 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags)) {
1064 low_bound += 0x10; 1061 low_bound += 0x10;
1065 up_bound += 0x10; 1062 up_bound += 0x10;
1066 } 1063 }
@@ -1131,6 +1128,116 @@ dynamic_cca_tune:
1131} 1128}
1132 1129
1133/* 1130/*
1131 * Queue handlers.
1132 */
1133static void rt61pci_start_queue(struct data_queue *queue)
1134{
1135 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1136 u32 reg;
1137
1138 switch (queue->qid) {
1139 case QID_RX:
1140 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1141 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1142 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1143 break;
1144 case QID_BEACON:
1145 /*
1146 * Allow the tbtt tasklet to be scheduled.
1147 */
1148 tasklet_enable(&rt2x00dev->tbtt_tasklet);
1149
1150 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1151 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1152 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1153 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1154 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1155 break;
1156 default:
1157 break;
1158 }
1159}
1160
1161static void rt61pci_kick_queue(struct data_queue *queue)
1162{
1163 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1164 u32 reg;
1165
1166 switch (queue->qid) {
1167 case QID_AC_VO:
1168 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1169 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, 1);
1170 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1171 break;
1172 case QID_AC_VI:
1173 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1174 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, 1);
1175 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1176 break;
1177 case QID_AC_BE:
1178 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1179 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, 1);
1180 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1181 break;
1182 case QID_AC_BK:
1183 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1184 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, 1);
1185 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1186 break;
1187 default:
1188 break;
1189 }
1190}
1191
1192static void rt61pci_stop_queue(struct data_queue *queue)
1193{
1194 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1195 u32 reg;
1196
1197 switch (queue->qid) {
1198 case QID_AC_VO:
1199 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1200 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1201 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1202 break;
1203 case QID_AC_VI:
1204 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1205 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1206 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1207 break;
1208 case QID_AC_BE:
1209 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1210 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1211 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1212 break;
1213 case QID_AC_BK:
1214 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1215 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1216 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1217 break;
1218 case QID_RX:
1219 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1220 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1);
1221 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1222 break;
1223 case QID_BEACON:
1224 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1225 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1226 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1227 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1228 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1229
1230 /*
1231 * Wait for possibly running tbtt tasklets.
1232 */
1233 tasklet_disable(&rt2x00dev->tbtt_tasklet);
1234 break;
1235 default:
1236 break;
1237 }
1238}
1239
1240/*
1134 * Firmware functions 1241 * Firmware functions
1135 */ 1242 */
1136static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev) 1243static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
@@ -1607,24 +1714,12 @@ static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1607/* 1714/*
1608 * Device state switch handlers. 1715 * Device state switch handlers.
1609 */ 1716 */
1610static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1611 enum dev_state state)
1612{
1613 u32 reg;
1614
1615 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1616 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1617 (state == STATE_RADIO_RX_OFF) ||
1618 (state == STATE_RADIO_RX_OFF_LINK));
1619 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1620}
1621
1622static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev, 1717static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1623 enum dev_state state) 1718 enum dev_state state)
1624{ 1719{
1625 int mask = (state == STATE_RADIO_IRQ_OFF) || 1720 int mask = (state == STATE_RADIO_IRQ_OFF);
1626 (state == STATE_RADIO_IRQ_OFF_ISR);
1627 u32 reg; 1721 u32 reg;
1722 unsigned long flags;
1628 1723
1629 /* 1724 /*
1630 * When interrupts are being enabled, the interrupt registers 1725 * When interrupts are being enabled, the interrupt registers
@@ -1636,15 +1731,25 @@ static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1636 1731
1637 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg); 1732 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1638 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg); 1733 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1734
1735 /*
1736 * Enable tasklets.
1737 */
1738 tasklet_enable(&rt2x00dev->txstatus_tasklet);
1739 tasklet_enable(&rt2x00dev->rxdone_tasklet);
1740 tasklet_enable(&rt2x00dev->autowake_tasklet);
1639 } 1741 }
1640 1742
1641 /* 1743 /*
1642 * Only toggle the interrupts bits we are going to use. 1744 * Only toggle the interrupts bits we are going to use.
1643 * Non-checked interrupt bits are disabled by default. 1745 * Non-checked interrupt bits are disabled by default.
1644 */ 1746 */
1747 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
1748
1645 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg); 1749 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1646 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask); 1750 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1647 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask); 1751 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1752 rt2x00_set_field32(&reg, INT_MASK_CSR_BEACON_DONE, mask);
1648 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask); 1753 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1649 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff); 1754 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1650 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg); 1755 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
@@ -1658,7 +1763,19 @@ static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1658 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask); 1763 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1659 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask); 1764 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1660 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask); 1765 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1766 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_TWAKEUP, mask);
1661 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); 1767 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1768
1769 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
1770
1771 if (state == STATE_RADIO_IRQ_OFF) {
1772 /*
1773 * Ensure that all tasklets are finished.
1774 */
1775 tasklet_disable(&rt2x00dev->txstatus_tasklet);
1776 tasklet_disable(&rt2x00dev->rxdone_tasklet);
1777 tasklet_disable(&rt2x00dev->autowake_tasklet);
1778 }
1662} 1779}
1663 1780
1664static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev) 1781static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
@@ -1733,16 +1850,8 @@ static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1733 case STATE_RADIO_OFF: 1850 case STATE_RADIO_OFF:
1734 rt61pci_disable_radio(rt2x00dev); 1851 rt61pci_disable_radio(rt2x00dev);
1735 break; 1852 break;
1736 case STATE_RADIO_RX_ON:
1737 case STATE_RADIO_RX_ON_LINK:
1738 case STATE_RADIO_RX_OFF:
1739 case STATE_RADIO_RX_OFF_LINK:
1740 rt61pci_toggle_rx(rt2x00dev, state);
1741 break;
1742 case STATE_RADIO_IRQ_ON: 1853 case STATE_RADIO_IRQ_ON:
1743 case STATE_RADIO_IRQ_ON_ISR:
1744 case STATE_RADIO_IRQ_OFF: 1854 case STATE_RADIO_IRQ_OFF:
1745 case STATE_RADIO_IRQ_OFF_ISR:
1746 rt61pci_toggle_irq(rt2x00dev, state); 1855 rt61pci_toggle_irq(rt2x00dev, state);
1747 break; 1856 break;
1748 case STATE_DEEP_SLEEP: 1857 case STATE_DEEP_SLEEP:
@@ -1766,12 +1875,11 @@ static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1766/* 1875/*
1767 * TX descriptor initialization 1876 * TX descriptor initialization
1768 */ 1877 */
1769static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, 1878static void rt61pci_write_tx_desc(struct queue_entry *entry,
1770 struct sk_buff *skb,
1771 struct txentry_desc *txdesc) 1879 struct txentry_desc *txdesc)
1772{ 1880{
1773 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 1881 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1774 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data; 1882 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1775 __le32 *txd = entry_priv->desc; 1883 __le32 *txd = entry_priv->desc;
1776 u32 word; 1884 u32 word;
1777 1885
@@ -1779,10 +1887,10 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1779 * Start writing the descriptor words. 1887 * Start writing the descriptor words.
1780 */ 1888 */
1781 rt2x00_desc_read(txd, 1, &word); 1889 rt2x00_desc_read(txd, 1, &word);
1782 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue); 1890 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid);
1783 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs); 1891 rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs);
1784 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min); 1892 rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
1785 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max); 1893 rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
1786 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset); 1894 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1787 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1895 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1788 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); 1896 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
@@ -1790,10 +1898,12 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1790 rt2x00_desc_write(txd, 1, word); 1898 rt2x00_desc_write(txd, 1, word);
1791 1899
1792 rt2x00_desc_read(txd, 2, &word); 1900 rt2x00_desc_read(txd, 2, &word);
1793 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal); 1901 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal);
1794 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service); 1902 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service);
1795 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low); 1903 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW,
1796 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high); 1904 txdesc->u.plcp.length_low);
1905 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH,
1906 txdesc->u.plcp.length_high);
1797 rt2x00_desc_write(txd, 2, word); 1907 rt2x00_desc_write(txd, 2, word);
1798 1908
1799 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) { 1909 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
@@ -1802,15 +1912,15 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1802 } 1912 }
1803 1913
1804 rt2x00_desc_read(txd, 5, &word); 1914 rt2x00_desc_read(txd, 5, &word);
1805 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid); 1915 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
1806 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, 1916 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1807 skbdesc->entry->entry_idx); 1917 skbdesc->entry->entry_idx);
1808 rt2x00_set_field32(&word, TXD_W5_TX_POWER, 1918 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1809 TXPOWER_TO_DEV(rt2x00dev->tx_power)); 1919 TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power));
1810 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1); 1920 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1811 rt2x00_desc_write(txd, 5, word); 1921 rt2x00_desc_write(txd, 5, word);
1812 1922
1813 if (txdesc->queue != QID_BEACON) { 1923 if (entry->queue->qid != QID_BEACON) {
1814 rt2x00_desc_read(txd, 6, &word); 1924 rt2x00_desc_read(txd, 6, &word);
1815 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS, 1925 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1816 skbdesc->skb_dma); 1926 skbdesc->skb_dma);
@@ -1838,7 +1948,7 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1838 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 1948 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1839 rt2x00_set_field32(&word, TXD_W0_OFDM, 1949 rt2x00_set_field32(&word, TXD_W0_OFDM,
1840 (txdesc->rate_mode == RATE_MODE_OFDM)); 1950 (txdesc->rate_mode == RATE_MODE_OFDM));
1841 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); 1951 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1842 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 1952 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1843 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); 1953 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1844 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 1954 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
@@ -1856,8 +1966,8 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1856 * Register descriptor details in skb frame descriptor. 1966 * Register descriptor details in skb frame descriptor.
1857 */ 1967 */
1858 skbdesc->desc = txd; 1968 skbdesc->desc = txd;
1859 skbdesc->desc_len = 1969 skbdesc->desc_len = (entry->queue->qid == QID_BEACON) ? TXINFO_SIZE :
1860 (txdesc->queue == QID_BEACON) ? TXINFO_SIZE : TXD_DESC_SIZE; 1970 TXD_DESC_SIZE;
1861} 1971}
1862 1972
1863/* 1973/*
@@ -1869,20 +1979,22 @@ static void rt61pci_write_beacon(struct queue_entry *entry,
1869 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1979 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1870 struct queue_entry_priv_pci *entry_priv = entry->priv_data; 1980 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1871 unsigned int beacon_base; 1981 unsigned int beacon_base;
1872 u32 reg; 1982 unsigned int padding_len;
1983 u32 orig_reg, reg;
1873 1984
1874 /* 1985 /*
1875 * Disable beaconing while we are reloading the beacon data, 1986 * Disable beaconing while we are reloading the beacon data,
1876 * otherwise we might be sending out invalid data. 1987 * otherwise we might be sending out invalid data.
1877 */ 1988 */
1878 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg); 1989 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1990 orig_reg = reg;
1879 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0); 1991 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1880 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); 1992 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1881 1993
1882 /* 1994 /*
1883 * Write the TX descriptor for the beacon. 1995 * Write the TX descriptor for the beacon.
1884 */ 1996 */
1885 rt61pci_write_tx_desc(rt2x00dev, entry->skb, txdesc); 1997 rt61pci_write_tx_desc(entry, txdesc);
1886 1998
1887 /* 1999 /*
1888 * Dump beacon to userspace through debugfs. 2000 * Dump beacon to userspace through debugfs.
@@ -1890,13 +2002,23 @@ static void rt61pci_write_beacon(struct queue_entry *entry,
1890 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb); 2002 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1891 2003
1892 /* 2004 /*
1893 * Write entire beacon with descriptor to register. 2005 * Write entire beacon with descriptor and padding to register.
1894 */ 2006 */
2007 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
2008 if (padding_len && skb_pad(entry->skb, padding_len)) {
2009 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
2010 /* skb freed by skb_pad() on failure */
2011 entry->skb = NULL;
2012 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, orig_reg);
2013 return;
2014 }
2015
1895 beacon_base = HW_BEACON_OFFSET(entry->entry_idx); 2016 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1896 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base, 2017 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
1897 entry_priv->desc, TXINFO_SIZE); 2018 entry_priv->desc, TXINFO_SIZE);
1898 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE, 2019 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE,
1899 entry->skb->data, entry->skb->len); 2020 entry->skb->data,
2021 entry->skb->len + padding_len);
1900 2022
1901 /* 2023 /*
1902 * Enable beaconing again. 2024 * Enable beaconing again.
@@ -1906,8 +2028,6 @@ static void rt61pci_write_beacon(struct queue_entry *entry,
1906 */ 2028 */
1907 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008); 2029 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1908 2030
1909 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1910 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1911 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1); 2031 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1912 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); 2032 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1913 2033
@@ -1918,35 +2038,30 @@ static void rt61pci_write_beacon(struct queue_entry *entry,
1918 entry->skb = NULL; 2038 entry->skb = NULL;
1919} 2039}
1920 2040
1921static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, 2041static void rt61pci_clear_beacon(struct queue_entry *entry)
1922 const enum data_queue_qid queue)
1923{ 2042{
2043 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1924 u32 reg; 2044 u32 reg;
1925 2045
1926 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg); 2046 /*
1927 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE)); 2047 * Disable beaconing while we are reloading the beacon data,
1928 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK)); 2048 * otherwise we might be sending out invalid data.
1929 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI)); 2049 */
1930 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO)); 2050 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1931 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); 2051 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1932} 2052 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1933
1934static void rt61pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1935 const enum data_queue_qid qid)
1936{
1937 u32 reg;
1938 2053
1939 if (qid == QID_BEACON) { 2054 /*
1940 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0); 2055 * Clear beacon.
1941 return; 2056 */
1942 } 2057 rt2x00pci_register_write(rt2x00dev,
2058 HW_BEACON_OFFSET(entry->entry_idx), 0);
1943 2059
1944 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg); 2060 /*
1945 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, (qid == QID_AC_BE)); 2061 * Enable beaconing again.
1946 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, (qid == QID_AC_BK)); 2062 */
1947 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, (qid == QID_AC_VI)); 2063 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1948 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, (qid == QID_AC_VO)); 2064 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1949 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1950} 2065}
1951 2066
1952/* 2067/*
@@ -1972,7 +2087,7 @@ static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1972 return 0; 2087 return 0;
1973 } 2088 }
1974 2089
1975 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) { 2090 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1976 if (lna == 3 || lna == 2) 2091 if (lna == 3 || lna == 2)
1977 offset += 10; 2092 offset += 10;
1978 } 2093 }
@@ -2013,9 +2128,8 @@ static void rt61pci_fill_rxdone(struct queue_entry *entry,
2013 rxdesc->flags |= RX_FLAG_IV_STRIPPED; 2128 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2014 2129
2015 /* 2130 /*
2016 * FIXME: Legacy driver indicates that the frame does 2131 * The hardware has already checked the Michael Mic and has
2017 * contain the Michael Mic. Unfortunately, in rt2x00 2132 * stripped it from the frame. Signal this to mac80211.
2018 * the MIC seems to be missing completely...
2019 */ 2133 */
2020 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED; 2134 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
2021 2135
@@ -2068,7 +2182,7 @@ static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2068 * that the TX_STA_FIFO stack has a size of 16. We stick to our 2182 * that the TX_STA_FIFO stack has a size of 16. We stick to our
2069 * tx ring size for now. 2183 * tx ring size for now.
2070 */ 2184 */
2071 for (i = 0; i < TX_ENTRIES; i++) { 2185 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
2072 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg); 2186 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
2073 if (!rt2x00_get_field32(reg, STA_CSR4_VALID)) 2187 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2074 break; 2188 break;
@@ -2078,7 +2192,7 @@ static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2078 * queue identication number. 2192 * queue identication number.
2079 */ 2193 */
2080 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE); 2194 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
2081 queue = rt2x00queue_get_queue(rt2x00dev, type); 2195 queue = rt2x00queue_get_tx_queue(rt2x00dev, type);
2082 if (unlikely(!queue)) 2196 if (unlikely(!queue))
2083 continue; 2197 continue;
2084 2198
@@ -2107,11 +2221,7 @@ static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2107 "TX status report missed for entry %d\n", 2221 "TX status report missed for entry %d\n",
2108 entry_done->entry_idx); 2222 entry_done->entry_idx);
2109 2223
2110 txdesc.flags = 0; 2224 rt2x00lib_txdone_noinfo(entry_done, TXDONE_UNKNOWN);
2111 __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
2112 txdesc.retry = 0;
2113
2114 rt2x00lib_txdone(entry_done, &txdesc);
2115 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 2225 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2116 } 2226 }
2117 2227
@@ -2150,61 +2260,79 @@ static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev)
2150 rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS); 2260 rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
2151} 2261}
2152 2262
2153static irqreturn_t rt61pci_interrupt_thread(int irq, void *dev_instance) 2263static inline void rt61pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
2264 struct rt2x00_field32 irq_field)
2154{ 2265{
2155 struct rt2x00_dev *rt2x00dev = dev_instance; 2266 u32 reg;
2156 u32 reg = rt2x00dev->irqvalue[0];
2157 u32 reg_mcu = rt2x00dev->irqvalue[1];
2158 2267
2159 /* 2268 /*
2160 * Handle interrupts, walk through all bits 2269 * Enable a single interrupt. The interrupt mask register
2161 * and run the tasks, the bits are checked in order of 2270 * access needs locking.
2162 * priority.
2163 */ 2271 */
2272 spin_lock_irq(&rt2x00dev->irqmask_lock);
2164 2273
2165 /* 2274 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
2166 * 1 - Rx ring done interrupt. 2275 rt2x00_set_field32(&reg, irq_field, 0);
2167 */ 2276 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
2168 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2169 rt2x00pci_rxdone(rt2x00dev);
2170 2277
2171 /* 2278 spin_unlock_irq(&rt2x00dev->irqmask_lock);
2172 * 2 - Tx ring done interrupt. 2279}
2173 */
2174 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2175 rt61pci_txdone(rt2x00dev);
2176 2280
2177 /* 2281static void rt61pci_enable_mcu_interrupt(struct rt2x00_dev *rt2x00dev,
2178 * 3 - Handle MCU command done. 2282 struct rt2x00_field32 irq_field)
2179 */ 2283{
2180 if (reg_mcu) 2284 u32 reg;
2181 rt2x00pci_register_write(rt2x00dev,
2182 M2H_CMD_DONE_CSR, 0xffffffff);
2183 2285
2184 /* 2286 /*
2185 * 4 - MCU Autowakeup interrupt. 2287 * Enable a single MCU interrupt. The interrupt mask register
2288 * access needs locking.
2186 */ 2289 */
2187 if (rt2x00_get_field32(reg_mcu, MCU_INT_SOURCE_CSR_TWAKEUP)) 2290 spin_lock_irq(&rt2x00dev->irqmask_lock);
2188 rt61pci_wakeup(rt2x00dev);
2189 2291
2190 /* 2292 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
2191 * 5 - Beacon done interrupt. 2293 rt2x00_set_field32(&reg, irq_field, 0);
2192 */ 2294 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
2193 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE))
2194 rt2x00lib_beacondone(rt2x00dev);
2195 2295
2196 /* Enable interrupts again. */ 2296 spin_unlock_irq(&rt2x00dev->irqmask_lock);
2197 rt2x00dev->ops->lib->set_device_state(rt2x00dev, 2297}
2198 STATE_RADIO_IRQ_ON_ISR); 2298
2199 return IRQ_HANDLED; 2299static void rt61pci_txstatus_tasklet(unsigned long data)
2300{
2301 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2302 rt61pci_txdone(rt2x00dev);
2303 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TXDONE);
2304}
2305
2306static void rt61pci_tbtt_tasklet(unsigned long data)
2307{
2308 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2309 rt2x00lib_beacondone(rt2x00dev);
2310 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_BEACON_DONE);
2311}
2312
2313static void rt61pci_rxdone_tasklet(unsigned long data)
2314{
2315 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2316 if (rt2x00pci_rxdone(rt2x00dev))
2317 rt2x00pci_rxdone(rt2x00dev);
2318 else
2319 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RXDONE);
2200} 2320}
2201 2321
2322static void rt61pci_autowake_tasklet(unsigned long data)
2323{
2324 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2325 rt61pci_wakeup(rt2x00dev);
2326 rt2x00pci_register_write(rt2x00dev,
2327 M2H_CMD_DONE_CSR, 0xffffffff);
2328 rt61pci_enable_mcu_interrupt(rt2x00dev, MCU_INT_MASK_CSR_TWAKEUP);
2329}
2202 2330
2203static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance) 2331static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2204{ 2332{
2205 struct rt2x00_dev *rt2x00dev = dev_instance; 2333 struct rt2x00_dev *rt2x00dev = dev_instance;
2206 u32 reg_mcu; 2334 u32 reg_mcu, mask_mcu;
2207 u32 reg; 2335 u32 reg, mask;
2208 2336
2209 /* 2337 /*
2210 * Get the interrupt sources & saved to local variable. 2338 * Get the interrupt sources & saved to local variable.
@@ -2222,14 +2350,46 @@ static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2222 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 2350 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2223 return IRQ_HANDLED; 2351 return IRQ_HANDLED;
2224 2352
2225 /* Store irqvalues for use in the interrupt thread. */ 2353 /*
2226 rt2x00dev->irqvalue[0] = reg; 2354 * Schedule tasklets for interrupt handling.
2227 rt2x00dev->irqvalue[1] = reg_mcu; 2355 */
2356 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2357 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
2358
2359 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2360 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
2361
2362 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE))
2363 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
2364
2365 if (rt2x00_get_field32(reg_mcu, MCU_INT_SOURCE_CSR_TWAKEUP))
2366 tasklet_schedule(&rt2x00dev->autowake_tasklet);
2367
2368 /*
2369 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
2370 * for interrupts and interrupt masks we can just use the value of
2371 * INT_SOURCE_CSR to create the interrupt mask.
2372 */
2373 mask = reg;
2374 mask_mcu = reg_mcu;
2375
2376 /*
2377 * Disable all interrupts for which a tasklet was scheduled right now,
2378 * the tasklet will reenable the appropriate interrupts.
2379 */
2380 spin_lock(&rt2x00dev->irqmask_lock);
2381
2382 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
2383 reg |= mask;
2384 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
2385
2386 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
2387 reg |= mask_mcu;
2388 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
2389
2390 spin_unlock(&rt2x00dev->irqmask_lock);
2228 2391
2229 /* Disable interrupts, will be enabled again in the interrupt thread. */ 2392 return IRQ_HANDLED;
2230 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
2231 STATE_RADIO_IRQ_OFF_ISR);
2232 return IRQ_WAKE_THREAD;
2233} 2393}
2234 2394
2235/* 2395/*
@@ -2377,7 +2537,7 @@ static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2377 * Determine number of antennas. 2537 * Determine number of antennas.
2378 */ 2538 */
2379 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2) 2539 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2380 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags); 2540 __set_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags);
2381 2541
2382 /* 2542 /*
2383 * Identify default antenna configuration. 2543 * Identify default antenna configuration.
@@ -2391,20 +2551,20 @@ static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2391 * Read the Frame type. 2551 * Read the Frame type.
2392 */ 2552 */
2393 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE)) 2553 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2394 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags); 2554 __set_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags);
2395 2555
2396 /* 2556 /*
2397 * Detect if this device has a hardware controlled radio. 2557 * Detect if this device has a hardware controlled radio.
2398 */ 2558 */
2399 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) 2559 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2400 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags); 2560 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
2401 2561
2402 /* 2562 /*
2403 * Read frequency offset and RF programming sequence. 2563 * Read frequency offset and RF programming sequence.
2404 */ 2564 */
2405 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); 2565 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2406 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ)) 2566 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2407 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags); 2567 __set_bit(CAPABILITY_RF_SEQUENCE, &rt2x00dev->cap_flags);
2408 2568
2409 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); 2569 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2410 2570
@@ -2414,9 +2574,9 @@ static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2414 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); 2574 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2415 2575
2416 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A)) 2576 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2417 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags); 2577 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
2418 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG)) 2578 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2419 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags); 2579 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
2420 2580
2421 /* 2581 /*
2422 * When working with a RF2529 chip without double antenna, 2582 * When working with a RF2529 chip without double antenna,
@@ -2424,7 +2584,7 @@ static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2424 * eeprom word. 2584 * eeprom word.
2425 */ 2585 */
2426 if (rt2x00_rf(rt2x00dev, RF2529) && 2586 if (rt2x00_rf(rt2x00dev, RF2529) &&
2427 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) { 2587 !test_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags)) {
2428 rt2x00dev->default_ant.rx = 2588 rt2x00dev->default_ant.rx =
2429 ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED); 2589 ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED);
2430 rt2x00dev->default_ant.tx = 2590 rt2x00dev->default_ant.tx =
@@ -2624,12 +2784,13 @@ static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2624 * As rt61 has a global fallback table we cannot specify 2784 * As rt61 has a global fallback table we cannot specify
2625 * more then one tx rate per frame but since the hw will 2785 * more then one tx rate per frame but since the hw will
2626 * try several rates (based on the fallback table) we should 2786 * try several rates (based on the fallback table) we should
2627 * still initialize max_rates to the maximum number of rates 2787 * initialize max_report_rates to the maximum number of rates
2628 * we are going to try. Otherwise mac80211 will truncate our 2788 * we are going to try. Otherwise mac80211 will truncate our
2629 * reported tx rates and the rc algortihm will end up with 2789 * reported tx rates and the rc algortihm will end up with
2630 * incorrect data. 2790 * incorrect data.
2631 */ 2791 */
2632 rt2x00dev->hw->max_rates = 7; 2792 rt2x00dev->hw->max_rates = 1;
2793 rt2x00dev->hw->max_report_rates = 7;
2633 rt2x00dev->hw->max_rate_tries = 1; 2794 rt2x00dev->hw->max_rate_tries = 1;
2634 2795
2635 /* 2796 /*
@@ -2638,7 +2799,7 @@ static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2638 spec->supported_bands = SUPPORT_BAND_2GHZ; 2799 spec->supported_bands = SUPPORT_BAND_2GHZ;
2639 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; 2800 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2640 2801
2641 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) { 2802 if (!test_bit(CAPABILITY_RF_SEQUENCE, &rt2x00dev->cap_flags)) {
2642 spec->num_channels = 14; 2803 spec->num_channels = 14;
2643 spec->channels = rf_vals_noseq; 2804 spec->channels = rf_vals_noseq;
2644 } else { 2805 } else {
@@ -2654,20 +2815,24 @@ static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2654 /* 2815 /*
2655 * Create channel information array 2816 * Create channel information array
2656 */ 2817 */
2657 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL); 2818 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
2658 if (!info) 2819 if (!info)
2659 return -ENOMEM; 2820 return -ENOMEM;
2660 2821
2661 spec->channels_info = info; 2822 spec->channels_info = info;
2662 2823
2663 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START); 2824 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2664 for (i = 0; i < 14; i++) 2825 for (i = 0; i < 14; i++) {
2665 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]); 2826 info[i].max_power = MAX_TXPOWER;
2827 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2828 }
2666 2829
2667 if (spec->num_channels > 14) { 2830 if (spec->num_channels > 14) {
2668 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START); 2831 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2669 for (i = 14; i < spec->num_channels; i++) 2832 for (i = 14; i < spec->num_channels; i++) {
2670 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]); 2833 info[i].max_power = MAX_TXPOWER;
2834 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2835 }
2671 } 2836 }
2672 2837
2673 return 0; 2838 return 0;
@@ -2704,16 +2869,16 @@ static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2704 * This device has multiple filters for control frames, 2869 * This device has multiple filters for control frames,
2705 * but has no a separate filter for PS Poll frames. 2870 * but has no a separate filter for PS Poll frames.
2706 */ 2871 */
2707 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags); 2872 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
2708 2873
2709 /* 2874 /*
2710 * This device requires firmware and DMA mapped skbs. 2875 * This device requires firmware and DMA mapped skbs.
2711 */ 2876 */
2712 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags); 2877 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
2713 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags); 2878 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
2714 if (!modparam_nohwcrypt) 2879 if (!modparam_nohwcrypt)
2715 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags); 2880 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
2716 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags); 2881 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
2717 2882
2718 /* 2883 /*
2719 * Set the rssi offset. 2884 * Set the rssi offset.
@@ -2753,7 +2918,7 @@ static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2753 if (queue_idx >= 4) 2918 if (queue_idx >= 4)
2754 return 0; 2919 return 0;
2755 2920
2756 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); 2921 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2757 2922
2758 /* Update WMM TXOP register */ 2923 /* Update WMM TXOP register */
2759 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2))); 2924 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
@@ -2813,11 +2978,18 @@ static const struct ieee80211_ops rt61pci_mac80211_ops = {
2813 .conf_tx = rt61pci_conf_tx, 2978 .conf_tx = rt61pci_conf_tx,
2814 .get_tsf = rt61pci_get_tsf, 2979 .get_tsf = rt61pci_get_tsf,
2815 .rfkill_poll = rt2x00mac_rfkill_poll, 2980 .rfkill_poll = rt2x00mac_rfkill_poll,
2981 .flush = rt2x00mac_flush,
2982 .set_antenna = rt2x00mac_set_antenna,
2983 .get_antenna = rt2x00mac_get_antenna,
2984 .get_ringparam = rt2x00mac_get_ringparam,
2816}; 2985};
2817 2986
2818static const struct rt2x00lib_ops rt61pci_rt2x00_ops = { 2987static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2819 .irq_handler = rt61pci_interrupt, 2988 .irq_handler = rt61pci_interrupt,
2820 .irq_handler_thread = rt61pci_interrupt_thread, 2989 .txstatus_tasklet = rt61pci_txstatus_tasklet,
2990 .tbtt_tasklet = rt61pci_tbtt_tasklet,
2991 .rxdone_tasklet = rt61pci_rxdone_tasklet,
2992 .autowake_tasklet = rt61pci_autowake_tasklet,
2821 .probe_hw = rt61pci_probe_hw, 2993 .probe_hw = rt61pci_probe_hw,
2822 .get_firmware_name = rt61pci_get_firmware_name, 2994 .get_firmware_name = rt61pci_get_firmware_name,
2823 .check_firmware = rt61pci_check_firmware, 2995 .check_firmware = rt61pci_check_firmware,
@@ -2831,10 +3003,13 @@ static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2831 .link_stats = rt61pci_link_stats, 3003 .link_stats = rt61pci_link_stats,
2832 .reset_tuner = rt61pci_reset_tuner, 3004 .reset_tuner = rt61pci_reset_tuner,
2833 .link_tuner = rt61pci_link_tuner, 3005 .link_tuner = rt61pci_link_tuner,
3006 .start_queue = rt61pci_start_queue,
3007 .kick_queue = rt61pci_kick_queue,
3008 .stop_queue = rt61pci_stop_queue,
3009 .flush_queue = rt2x00pci_flush_queue,
2834 .write_tx_desc = rt61pci_write_tx_desc, 3010 .write_tx_desc = rt61pci_write_tx_desc,
2835 .write_beacon = rt61pci_write_beacon, 3011 .write_beacon = rt61pci_write_beacon,
2836 .kick_tx_queue = rt61pci_kick_tx_queue, 3012 .clear_beacon = rt61pci_clear_beacon,
2837 .kill_tx_queue = rt61pci_kill_tx_queue,
2838 .fill_rxdone = rt61pci_fill_rxdone, 3013 .fill_rxdone = rt61pci_fill_rxdone,
2839 .config_shared_key = rt61pci_config_shared_key, 3014 .config_shared_key = rt61pci_config_shared_key,
2840 .config_pairwise_key = rt61pci_config_pairwise_key, 3015 .config_pairwise_key = rt61pci_config_pairwise_key,
@@ -2846,21 +3021,21 @@ static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2846}; 3021};
2847 3022
2848static const struct data_queue_desc rt61pci_queue_rx = { 3023static const struct data_queue_desc rt61pci_queue_rx = {
2849 .entry_num = RX_ENTRIES, 3024 .entry_num = 32,
2850 .data_size = DATA_FRAME_SIZE, 3025 .data_size = DATA_FRAME_SIZE,
2851 .desc_size = RXD_DESC_SIZE, 3026 .desc_size = RXD_DESC_SIZE,
2852 .priv_size = sizeof(struct queue_entry_priv_pci), 3027 .priv_size = sizeof(struct queue_entry_priv_pci),
2853}; 3028};
2854 3029
2855static const struct data_queue_desc rt61pci_queue_tx = { 3030static const struct data_queue_desc rt61pci_queue_tx = {
2856 .entry_num = TX_ENTRIES, 3031 .entry_num = 32,
2857 .data_size = DATA_FRAME_SIZE, 3032 .data_size = DATA_FRAME_SIZE,
2858 .desc_size = TXD_DESC_SIZE, 3033 .desc_size = TXD_DESC_SIZE,
2859 .priv_size = sizeof(struct queue_entry_priv_pci), 3034 .priv_size = sizeof(struct queue_entry_priv_pci),
2860}; 3035};
2861 3036
2862static const struct data_queue_desc rt61pci_queue_bcn = { 3037static const struct data_queue_desc rt61pci_queue_bcn = {
2863 .entry_num = 4 * BEACON_ENTRIES, 3038 .entry_num = 4,
2864 .data_size = 0, /* No DMA required for beacons */ 3039 .data_size = 0, /* No DMA required for beacons */
2865 .desc_size = TXINFO_SIZE, 3040 .desc_size = TXINFO_SIZE,
2866 .priv_size = sizeof(struct queue_entry_priv_pci), 3041 .priv_size = sizeof(struct queue_entry_priv_pci),
@@ -2889,11 +3064,11 @@ static const struct rt2x00_ops rt61pci_ops = {
2889 */ 3064 */
2890static DEFINE_PCI_DEVICE_TABLE(rt61pci_device_table) = { 3065static DEFINE_PCI_DEVICE_TABLE(rt61pci_device_table) = {
2891 /* RT2561s */ 3066 /* RT2561s */
2892 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) }, 3067 { PCI_DEVICE(0x1814, 0x0301) },
2893 /* RT2561 v2 */ 3068 /* RT2561 v2 */
2894 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) }, 3069 { PCI_DEVICE(0x1814, 0x0302) },
2895 /* RT2661 */ 3070 /* RT2661 */
2896 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) }, 3071 { PCI_DEVICE(0x1814, 0x0401) },
2897 { 0, } 3072 { 0, }
2898}; 3073};
2899 3074
@@ -2908,10 +3083,16 @@ MODULE_FIRMWARE(FIRMWARE_RT2561s);
2908MODULE_FIRMWARE(FIRMWARE_RT2661); 3083MODULE_FIRMWARE(FIRMWARE_RT2661);
2909MODULE_LICENSE("GPL"); 3084MODULE_LICENSE("GPL");
2910 3085
3086static int rt61pci_probe(struct pci_dev *pci_dev,
3087 const struct pci_device_id *id)
3088{
3089 return rt2x00pci_probe(pci_dev, &rt61pci_ops);
3090}
3091
2911static struct pci_driver rt61pci_driver = { 3092static struct pci_driver rt61pci_driver = {
2912 .name = KBUILD_MODNAME, 3093 .name = KBUILD_MODNAME,
2913 .id_table = rt61pci_device_table, 3094 .id_table = rt61pci_device_table,
2914 .probe = rt2x00pci_probe, 3095 .probe = rt61pci_probe,
2915 .remove = __devexit_p(rt2x00pci_remove), 3096 .remove = __devexit_p(rt2x00pci_remove),
2916 .suspend = rt2x00pci_suspend, 3097 .suspend = rt2x00pci_suspend,
2917 .resume = rt2x00pci_resume, 3098 .resume = rt2x00pci_resume,
diff --git a/drivers/net/wireless/rt2x00/rt61pci.h b/drivers/net/wireless/rt2x00/rt61pci.h
index e2e728ab0b2e..e3cd6db76b0e 100644
--- a/drivers/net/wireless/rt2x00/rt61pci.h
+++ b/drivers/net/wireless/rt2x00/rt61pci.h
@@ -412,7 +412,7 @@ struct hw_pairwise_ta_entry {
412 * DROP_VERSION_ERROR: Drop version error frame. 412 * DROP_VERSION_ERROR: Drop version error frame.
413 * DROP_MULTICAST: Drop multicast frames. 413 * DROP_MULTICAST: Drop multicast frames.
414 * DROP_BORADCAST: Drop broadcast frames. 414 * DROP_BORADCAST: Drop broadcast frames.
415 * ROP_ACK_CTS: Drop received ACK and CTS. 415 * DROP_ACK_CTS: Drop received ACK and CTS.
416 */ 416 */
417#define TXRX_CSR0 0x3040 417#define TXRX_CSR0 0x3040
418#define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff) 418#define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff)
@@ -784,25 +784,25 @@ struct hw_pairwise_ta_entry {
784 */ 784 */
785 785
786/* 786/*
787 * AC0_BASE_CSR: AC_BK base address. 787 * AC0_BASE_CSR: AC_VO base address.
788 */ 788 */
789#define AC0_BASE_CSR 0x3400 789#define AC0_BASE_CSR 0x3400
790#define AC0_BASE_CSR_RING_REGISTER FIELD32(0xffffffff) 790#define AC0_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
791 791
792/* 792/*
793 * AC1_BASE_CSR: AC_BE base address. 793 * AC1_BASE_CSR: AC_VI base address.
794 */ 794 */
795#define AC1_BASE_CSR 0x3404 795#define AC1_BASE_CSR 0x3404
796#define AC1_BASE_CSR_RING_REGISTER FIELD32(0xffffffff) 796#define AC1_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
797 797
798/* 798/*
799 * AC2_BASE_CSR: AC_VI base address. 799 * AC2_BASE_CSR: AC_BE base address.
800 */ 800 */
801#define AC2_BASE_CSR 0x3408 801#define AC2_BASE_CSR 0x3408
802#define AC2_BASE_CSR_RING_REGISTER FIELD32(0xffffffff) 802#define AC2_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
803 803
804/* 804/*
805 * AC3_BASE_CSR: AC_VO base address. 805 * AC3_BASE_CSR: AC_BK base address.
806 */ 806 */
807#define AC3_BASE_CSR 0x340c 807#define AC3_BASE_CSR 0x340c
808#define AC3_BASE_CSR_RING_REGISTER FIELD32(0xffffffff) 808#define AC3_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
@@ -814,7 +814,7 @@ struct hw_pairwise_ta_entry {
814#define MGMT_BASE_CSR_RING_REGISTER FIELD32(0xffffffff) 814#define MGMT_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
815 815
816/* 816/*
817 * TX_RING_CSR0: TX Ring size for AC_BK, AC_BE, AC_VI, AC_VO. 817 * TX_RING_CSR0: TX Ring size for AC_VO, AC_VI, AC_BE, AC_BK.
818 */ 818 */
819#define TX_RING_CSR0 0x3418 819#define TX_RING_CSR0 0x3418
820#define TX_RING_CSR0_AC0_RING_SIZE FIELD32(0x000000ff) 820#define TX_RING_CSR0_AC0_RING_SIZE FIELD32(0x000000ff)
@@ -833,10 +833,10 @@ struct hw_pairwise_ta_entry {
833 833
834/* 834/*
835 * AIFSN_CSR: AIFSN for each EDCA AC. 835 * AIFSN_CSR: AIFSN for each EDCA AC.
836 * AIFSN0: For AC_BK. 836 * AIFSN0: For AC_VO.
837 * AIFSN1: For AC_BE. 837 * AIFSN1: For AC_VI.
838 * AIFSN2: For AC_VI. 838 * AIFSN2: For AC_BE.
839 * AIFSN3: For AC_VO. 839 * AIFSN3: For AC_BK.
840 */ 840 */
841#define AIFSN_CSR 0x3420 841#define AIFSN_CSR 0x3420
842#define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f) 842#define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f)
@@ -846,10 +846,10 @@ struct hw_pairwise_ta_entry {
846 846
847/* 847/*
848 * CWMIN_CSR: CWmin for each EDCA AC. 848 * CWMIN_CSR: CWmin for each EDCA AC.
849 * CWMIN0: For AC_BK. 849 * CWMIN0: For AC_VO.
850 * CWMIN1: For AC_BE. 850 * CWMIN1: For AC_VI.
851 * CWMIN2: For AC_VI. 851 * CWMIN2: For AC_BE.
852 * CWMIN3: For AC_VO. 852 * CWMIN3: For AC_BK.
853 */ 853 */
854#define CWMIN_CSR 0x3424 854#define CWMIN_CSR 0x3424
855#define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f) 855#define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f)
@@ -859,10 +859,10 @@ struct hw_pairwise_ta_entry {
859 859
860/* 860/*
861 * CWMAX_CSR: CWmax for each EDCA AC. 861 * CWMAX_CSR: CWmax for each EDCA AC.
862 * CWMAX0: For AC_BK. 862 * CWMAX0: For AC_VO.
863 * CWMAX1: For AC_BE. 863 * CWMAX1: For AC_VI.
864 * CWMAX2: For AC_VI. 864 * CWMAX2: For AC_BE.
865 * CWMAX3: For AC_VO. 865 * CWMAX3: For AC_BK.
866 */ 866 */
867#define CWMAX_CSR 0x3428 867#define CWMAX_CSR 0x3428
868#define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f) 868#define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f)
@@ -883,14 +883,14 @@ struct hw_pairwise_ta_entry {
883 883
884/* 884/*
885 * TX_CNTL_CSR: KICK/Abort TX. 885 * TX_CNTL_CSR: KICK/Abort TX.
886 * KICK_TX_AC0: For AC_BK. 886 * KICK_TX_AC0: For AC_VO.
887 * KICK_TX_AC1: For AC_BE. 887 * KICK_TX_AC1: For AC_VI.
888 * KICK_TX_AC2: For AC_VI. 888 * KICK_TX_AC2: For AC_BE.
889 * KICK_TX_AC3: For AC_VO. 889 * KICK_TX_AC3: For AC_BK.
890 * ABORT_TX_AC0: For AC_BK. 890 * ABORT_TX_AC0: For AC_VO.
891 * ABORT_TX_AC1: For AC_BE. 891 * ABORT_TX_AC1: For AC_VI.
892 * ABORT_TX_AC2: For AC_VI. 892 * ABORT_TX_AC2: For AC_BE.
893 * ABORT_TX_AC3: For AC_VO. 893 * ABORT_TX_AC3: For AC_BK.
894 */ 894 */
895#define TX_CNTL_CSR 0x3430 895#define TX_CNTL_CSR 0x3430
896#define TX_CNTL_CSR_KICK_TX_AC0 FIELD32(0x00000001) 896#define TX_CNTL_CSR_KICK_TX_AC0 FIELD32(0x00000001)
@@ -1010,18 +1010,18 @@ struct hw_pairwise_ta_entry {
1010#define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040) 1010#define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
1011 1011
1012/* 1012/*
1013 * AC_TXOP_CSR0: AC_BK/AC_BE TXOP register. 1013 * AC_TXOP_CSR0: AC_VO/AC_VI TXOP register.
1014 * AC0_TX_OP: For AC_BK, in unit of 32us. 1014 * AC0_TX_OP: For AC_VO, in unit of 32us.
1015 * AC1_TX_OP: For AC_BE, in unit of 32us. 1015 * AC1_TX_OP: For AC_VI, in unit of 32us.
1016 */ 1016 */
1017#define AC_TXOP_CSR0 0x3474 1017#define AC_TXOP_CSR0 0x3474
1018#define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff) 1018#define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff)
1019#define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000) 1019#define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000)
1020 1020
1021/* 1021/*
1022 * AC_TXOP_CSR1: AC_VO/AC_VI TXOP register. 1022 * AC_TXOP_CSR1: AC_BE/AC_BK TXOP register.
1023 * AC2_TX_OP: For AC_VI, in unit of 32us. 1023 * AC2_TX_OP: For AC_BE, in unit of 32us.
1024 * AC3_TX_OP: For AC_VO, in unit of 32us. 1024 * AC3_TX_OP: For AC_BK, in unit of 32us.
1025 */ 1025 */
1026#define AC_TXOP_CSR1 0x3478 1026#define AC_TXOP_CSR1 0x3478
1027#define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff) 1027#define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff)
diff --git a/drivers/net/wireless/rt2x00/rt73usb.c b/drivers/net/wireless/rt2x00/rt73usb.c
index aa9de18fd410..ad20953cbf05 100644
--- a/drivers/net/wireless/rt2x00/rt73usb.c
+++ b/drivers/net/wireless/rt2x00/rt73usb.c
@@ -40,7 +40,7 @@
40/* 40/*
41 * Allow hardware encryption to be disabled. 41 * Allow hardware encryption to be disabled.
42 */ 42 */
43static int modparam_nohwcrypt = 0; 43static int modparam_nohwcrypt;
44module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO); 44module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
45MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 45MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
46 46
@@ -502,26 +502,14 @@ static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
502 struct rt2x00intf_conf *conf, 502 struct rt2x00intf_conf *conf,
503 const unsigned int flags) 503 const unsigned int flags)
504{ 504{
505 unsigned int beacon_base;
506 u32 reg; 505 u32 reg;
507 506
508 if (flags & CONFIG_UPDATE_TYPE) { 507 if (flags & CONFIG_UPDATE_TYPE) {
509 /* 508 /*
510 * Clear current synchronisation setup.
511 * For the Beacon base registers we only need to clear
512 * the first byte since that byte contains the VALID and OWNER
513 * bits which (when set to 0) will invalidate the entire beacon.
514 */
515 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
516 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
517
518 /*
519 * Enable synchronisation. 509 * Enable synchronisation.
520 */ 510 */
521 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg); 511 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
522 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
523 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync); 512 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
524 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
525 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); 513 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
526 } 514 }
527 515
@@ -545,7 +533,8 @@ static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
545} 533}
546 534
547static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev, 535static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
548 struct rt2x00lib_erp *erp) 536 struct rt2x00lib_erp *erp,
537 u32 changed)
549{ 538{
550 u32 reg; 539 u32 reg;
551 540
@@ -554,28 +543,36 @@ static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
554 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); 543 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
555 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); 544 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
556 545
557 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg); 546 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
558 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1); 547 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
559 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE, 548 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
560 !!erp->short_preamble); 549 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
561 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg); 550 !!erp->short_preamble);
551 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
552 }
562 553
563 rt2x00usb_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates); 554 if (changed & BSS_CHANGED_BASIC_RATES)
555 rt2x00usb_register_write(rt2x00dev, TXRX_CSR5,
556 erp->basic_rates);
564 557
565 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg); 558 if (changed & BSS_CHANGED_BEACON_INT) {
566 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 559 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
567 erp->beacon_int * 16); 560 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
568 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); 561 erp->beacon_int * 16);
562 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
563 }
569 564
570 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg); 565 if (changed & BSS_CHANGED_ERP_SLOT) {
571 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time); 566 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
572 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg); 567 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
568 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
573 569
574 rt2x00usb_register_read(rt2x00dev, MAC_CSR8, &reg); 570 rt2x00usb_register_read(rt2x00dev, MAC_CSR8, &reg);
575 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs); 571 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
576 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); 572 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
577 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs); 573 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
578 rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg); 574 rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg);
575 }
579} 576}
580 577
581static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev, 578static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
@@ -598,7 +595,7 @@ static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
598 switch (ant->rx) { 595 switch (ant->rx) {
599 case ANTENNA_HW_DIVERSITY: 596 case ANTENNA_HW_DIVERSITY:
600 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2); 597 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
601 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags) 598 temp = !test_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags)
602 && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ); 599 && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
603 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp); 600 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
604 break; 601 break;
@@ -639,7 +636,7 @@ static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
639 636
640 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0); 637 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
641 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 638 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
642 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)); 639 !test_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags));
643 640
644 /* 641 /*
645 * Configure the RX antenna. 642 * Configure the RX antenna.
@@ -712,10 +709,10 @@ static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
712 709
713 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { 710 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
714 sel = antenna_sel_a; 711 sel = antenna_sel_a;
715 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags); 712 lna = test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
716 } else { 713 } else {
717 sel = antenna_sel_bg; 714 sel = antenna_sel_bg;
718 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags); 715 lna = test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
719 } 716 }
720 717
721 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++) 718 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
@@ -743,7 +740,7 @@ static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
743 short lna_gain = 0; 740 short lna_gain = 0;
744 741
745 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) { 742 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
746 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) 743 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags))
747 lna_gain += 14; 744 lna_gain += 14;
748 745
749 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom); 746 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
@@ -929,11 +926,11 @@ static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev,
929 /* 926 /*
930 * Determine r17 bounds. 927 * Determine r17 bounds.
931 */ 928 */
932 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) { 929 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
933 low_bound = 0x28; 930 low_bound = 0x28;
934 up_bound = 0x48; 931 up_bound = 0x48;
935 932
936 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) { 933 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags)) {
937 low_bound += 0x10; 934 low_bound += 0x10;
938 up_bound += 0x10; 935 up_bound += 0x10;
939 } 936 }
@@ -949,7 +946,7 @@ static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev,
949 up_bound = 0x1c; 946 up_bound = 0x1c;
950 } 947 }
951 948
952 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) { 949 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags)) {
953 low_bound += 0x14; 950 low_bound += 0x14;
954 up_bound += 0x10; 951 up_bound += 0x10;
955 } 952 }
@@ -1022,6 +1019,55 @@ dynamic_cca_tune:
1022} 1019}
1023 1020
1024/* 1021/*
1022 * Queue handlers.
1023 */
1024static void rt73usb_start_queue(struct data_queue *queue)
1025{
1026 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1027 u32 reg;
1028
1029 switch (queue->qid) {
1030 case QID_RX:
1031 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1032 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1033 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1034 break;
1035 case QID_BEACON:
1036 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1037 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1038 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1039 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1040 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1041 break;
1042 default:
1043 break;
1044 }
1045}
1046
1047static void rt73usb_stop_queue(struct data_queue *queue)
1048{
1049 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1050 u32 reg;
1051
1052 switch (queue->qid) {
1053 case QID_RX:
1054 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1055 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1);
1056 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1057 break;
1058 case QID_BEACON:
1059 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1060 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1061 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1062 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1063 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1064 break;
1065 default:
1066 break;
1067 }
1068}
1069
1070/*
1025 * Firmware functions 1071 * Firmware functions
1026 */ 1072 */
1027static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev) 1073static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
@@ -1315,18 +1361,6 @@ static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1315/* 1361/*
1316 * Device state switch handlers. 1362 * Device state switch handlers.
1317 */ 1363 */
1318static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1319 enum dev_state state)
1320{
1321 u32 reg;
1322
1323 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1324 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1325 (state == STATE_RADIO_RX_OFF) ||
1326 (state == STATE_RADIO_RX_OFF_LINK));
1327 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1328}
1329
1330static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev) 1364static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1331{ 1365{
1332 /* 1366 /*
@@ -1393,16 +1427,8 @@ static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1393 case STATE_RADIO_OFF: 1427 case STATE_RADIO_OFF:
1394 rt73usb_disable_radio(rt2x00dev); 1428 rt73usb_disable_radio(rt2x00dev);
1395 break; 1429 break;
1396 case STATE_RADIO_RX_ON:
1397 case STATE_RADIO_RX_ON_LINK:
1398 case STATE_RADIO_RX_OFF:
1399 case STATE_RADIO_RX_OFF_LINK:
1400 rt73usb_toggle_rx(rt2x00dev, state);
1401 break;
1402 case STATE_RADIO_IRQ_ON: 1430 case STATE_RADIO_IRQ_ON:
1403 case STATE_RADIO_IRQ_ON_ISR:
1404 case STATE_RADIO_IRQ_OFF: 1431 case STATE_RADIO_IRQ_OFF:
1405 case STATE_RADIO_IRQ_OFF_ISR:
1406 /* No support, but no error either */ 1432 /* No support, but no error either */
1407 break; 1433 break;
1408 case STATE_DEEP_SLEEP: 1434 case STATE_DEEP_SLEEP:
@@ -1426,12 +1452,11 @@ static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1426/* 1452/*
1427 * TX descriptor initialization 1453 * TX descriptor initialization
1428 */ 1454 */
1429static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev, 1455static void rt73usb_write_tx_desc(struct queue_entry *entry,
1430 struct sk_buff *skb,
1431 struct txentry_desc *txdesc) 1456 struct txentry_desc *txdesc)
1432{ 1457{
1433 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 1458 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1434 __le32 *txd = (__le32 *) skb->data; 1459 __le32 *txd = (__le32 *) entry->skb->data;
1435 u32 word; 1460 u32 word;
1436 1461
1437 /* 1462 /*
@@ -1449,7 +1474,7 @@ static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1449 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 1474 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1450 rt2x00_set_field32(&word, TXD_W0_OFDM, 1475 rt2x00_set_field32(&word, TXD_W0_OFDM,
1451 (txdesc->rate_mode == RATE_MODE_OFDM)); 1476 (txdesc->rate_mode == RATE_MODE_OFDM));
1452 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); 1477 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1453 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 1478 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1454 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); 1479 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1455 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 1480 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
@@ -1464,20 +1489,22 @@ static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1464 rt2x00_desc_write(txd, 0, word); 1489 rt2x00_desc_write(txd, 0, word);
1465 1490
1466 rt2x00_desc_read(txd, 1, &word); 1491 rt2x00_desc_read(txd, 1, &word);
1467 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue); 1492 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid);
1468 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs); 1493 rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs);
1469 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min); 1494 rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
1470 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max); 1495 rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
1471 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset); 1496 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1472 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1497 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1473 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); 1498 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1474 rt2x00_desc_write(txd, 1, word); 1499 rt2x00_desc_write(txd, 1, word);
1475 1500
1476 rt2x00_desc_read(txd, 2, &word); 1501 rt2x00_desc_read(txd, 2, &word);
1477 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal); 1502 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal);
1478 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service); 1503 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service);
1479 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low); 1504 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW,
1480 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high); 1505 txdesc->u.plcp.length_low);
1506 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH,
1507 txdesc->u.plcp.length_high);
1481 rt2x00_desc_write(txd, 2, word); 1508 rt2x00_desc_write(txd, 2, word);
1482 1509
1483 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) { 1510 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
@@ -1487,7 +1514,7 @@ static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1487 1514
1488 rt2x00_desc_read(txd, 5, &word); 1515 rt2x00_desc_read(txd, 5, &word);
1489 rt2x00_set_field32(&word, TXD_W5_TX_POWER, 1516 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1490 TXPOWER_TO_DEV(rt2x00dev->tx_power)); 1517 TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power));
1491 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1); 1518 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1492 rt2x00_desc_write(txd, 5, word); 1519 rt2x00_desc_write(txd, 5, word);
1493 1520
@@ -1507,13 +1534,15 @@ static void rt73usb_write_beacon(struct queue_entry *entry,
1507{ 1534{
1508 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1535 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1509 unsigned int beacon_base; 1536 unsigned int beacon_base;
1510 u32 reg; 1537 unsigned int padding_len;
1538 u32 orig_reg, reg;
1511 1539
1512 /* 1540 /*
1513 * Disable beaconing while we are reloading the beacon data, 1541 * Disable beaconing while we are reloading the beacon data,
1514 * otherwise we might be sending out invalid data. 1542 * otherwise we might be sending out invalid data.
1515 */ 1543 */
1516 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg); 1544 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1545 orig_reg = reg;
1517 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0); 1546 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1518 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); 1547 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1519 1548
@@ -1526,7 +1555,7 @@ static void rt73usb_write_beacon(struct queue_entry *entry,
1526 /* 1555 /*
1527 * Write the TX descriptor for the beacon. 1556 * Write the TX descriptor for the beacon.
1528 */ 1557 */
1529 rt73usb_write_tx_desc(rt2x00dev, entry->skb, txdesc); 1558 rt73usb_write_tx_desc(entry, txdesc);
1530 1559
1531 /* 1560 /*
1532 * Dump beacon to userspace through debugfs. 1561 * Dump beacon to userspace through debugfs.
@@ -1534,11 +1563,20 @@ static void rt73usb_write_beacon(struct queue_entry *entry,
1534 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb); 1563 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1535 1564
1536 /* 1565 /*
1537 * Write entire beacon with descriptor to register. 1566 * Write entire beacon with descriptor and padding to register.
1538 */ 1567 */
1568 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
1569 if (padding_len && skb_pad(entry->skb, padding_len)) {
1570 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
1571 /* skb freed by skb_pad() on failure */
1572 entry->skb = NULL;
1573 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, orig_reg);
1574 return;
1575 }
1576
1539 beacon_base = HW_BEACON_OFFSET(entry->entry_idx); 1577 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1540 rt2x00usb_register_multiwrite(rt2x00dev, beacon_base, 1578 rt2x00usb_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1541 entry->skb->data, entry->skb->len); 1579 entry->skb->len + padding_len);
1542 1580
1543 /* 1581 /*
1544 * Enable beaconing again. 1582 * Enable beaconing again.
@@ -1548,8 +1586,6 @@ static void rt73usb_write_beacon(struct queue_entry *entry,
1548 */ 1586 */
1549 rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008); 1587 rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1550 1588
1551 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1552 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1553 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1); 1589 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1554 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); 1590 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1555 1591
@@ -1560,6 +1596,33 @@ static void rt73usb_write_beacon(struct queue_entry *entry,
1560 entry->skb = NULL; 1596 entry->skb = NULL;
1561} 1597}
1562 1598
1599static void rt73usb_clear_beacon(struct queue_entry *entry)
1600{
1601 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1602 unsigned int beacon_base;
1603 u32 reg;
1604
1605 /*
1606 * Disable beaconing while we are reloading the beacon data,
1607 * otherwise we might be sending out invalid data.
1608 */
1609 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1610 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1611 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1612
1613 /*
1614 * Clear beacon.
1615 */
1616 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1617 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
1618
1619 /*
1620 * Enable beaconing again.
1621 */
1622 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1623 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1624}
1625
1563static int rt73usb_get_tx_data_len(struct queue_entry *entry) 1626static int rt73usb_get_tx_data_len(struct queue_entry *entry)
1564{ 1627{
1565 int length; 1628 int length;
@@ -1597,8 +1660,8 @@ static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1597 return 0; 1660 return 0;
1598 } 1661 }
1599 1662
1600 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) { 1663 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1601 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) { 1664 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags)) {
1602 if (lna == 3 || lna == 2) 1665 if (lna == 3 || lna == 2)
1603 offset += 10; 1666 offset += 10;
1604 } else { 1667 } else {
@@ -1656,9 +1719,8 @@ static void rt73usb_fill_rxdone(struct queue_entry *entry,
1656 rxdesc->flags |= RX_FLAG_IV_STRIPPED; 1719 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1657 1720
1658 /* 1721 /*
1659 * FIXME: Legacy driver indicates that the frame does 1722 * The hardware has already checked the Michael Mic and has
1660 * contain the Michael Mic. Unfortunately, in rt2x00 1723 * stripped it from the frame. Signal this to mac80211.
1661 * the MIC seems to be missing completely...
1662 */ 1724 */
1663 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED; 1725 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1664 1726
@@ -1837,13 +1899,13 @@ static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1837 * Read the Frame type. 1899 * Read the Frame type.
1838 */ 1900 */
1839 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE)) 1901 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1840 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags); 1902 __set_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags);
1841 1903
1842 /* 1904 /*
1843 * Detect if this device has an hardware controlled radio. 1905 * Detect if this device has an hardware controlled radio.
1844 */ 1906 */
1845 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) 1907 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1846 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags); 1908 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
1847 1909
1848 /* 1910 /*
1849 * Read frequency offset. 1911 * Read frequency offset.
@@ -1857,8 +1919,8 @@ static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1857 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); 1919 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1858 1920
1859 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) { 1921 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1860 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags); 1922 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
1861 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags); 1923 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
1862 } 1924 }
1863 1925
1864 /* 1926 /*
@@ -2047,9 +2109,14 @@ static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2047 2109
2048 /* 2110 /*
2049 * Initialize all hw fields. 2111 * Initialize all hw fields.
2112 *
2113 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING unless we are
2114 * capable of sending the buffered frames out after the DTIM
2115 * transmission using rt2x00lib_beacondone. This will send out
2116 * multicast and broadcast traffic immediately instead of buffering it
2117 * infinitly and thus dropping it after some time.
2050 */ 2118 */
2051 rt2x00dev->hw->flags = 2119 rt2x00dev->hw->flags =
2052 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2053 IEEE80211_HW_SIGNAL_DBM | 2120 IEEE80211_HW_SIGNAL_DBM |
2054 IEEE80211_HW_SUPPORTS_PS | 2121 IEEE80211_HW_SUPPORTS_PS |
2055 IEEE80211_HW_PS_NULLFUNC_STACK; 2122 IEEE80211_HW_PS_NULLFUNC_STACK;
@@ -2084,20 +2151,24 @@ static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2084 /* 2151 /*
2085 * Create channel information array 2152 * Create channel information array
2086 */ 2153 */
2087 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL); 2154 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
2088 if (!info) 2155 if (!info)
2089 return -ENOMEM; 2156 return -ENOMEM;
2090 2157
2091 spec->channels_info = info; 2158 spec->channels_info = info;
2092 2159
2093 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START); 2160 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2094 for (i = 0; i < 14; i++) 2161 for (i = 0; i < 14; i++) {
2095 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]); 2162 info[i].max_power = MAX_TXPOWER;
2163 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2164 }
2096 2165
2097 if (spec->num_channels > 14) { 2166 if (spec->num_channels > 14) {
2098 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START); 2167 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2099 for (i = 14; i < spec->num_channels; i++) 2168 for (i = 14; i < spec->num_channels; i++) {
2100 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]); 2169 info[i].max_power = MAX_TXPOWER;
2170 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2171 }
2101 } 2172 }
2102 2173
2103 return 0; 2174 return 0;
@@ -2129,16 +2200,16 @@ static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2129 * This device has multiple filters for control frames, 2200 * This device has multiple filters for control frames,
2130 * but has no a separate filter for PS Poll frames. 2201 * but has no a separate filter for PS Poll frames.
2131 */ 2202 */
2132 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags); 2203 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
2133 2204
2134 /* 2205 /*
2135 * This device requires firmware. 2206 * This device requires firmware.
2136 */ 2207 */
2137 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags); 2208 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
2138 if (!modparam_nohwcrypt) 2209 if (!modparam_nohwcrypt)
2139 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags); 2210 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
2140 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags); 2211 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
2141 __set_bit(DRIVER_SUPPORT_WATCHDOG, &rt2x00dev->flags); 2212 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
2142 2213
2143 /* 2214 /*
2144 * Set the rssi offset. 2215 * Set the rssi offset.
@@ -2178,7 +2249,7 @@ static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2178 if (queue_idx >= 4) 2249 if (queue_idx >= 4)
2179 return 0; 2250 return 0;
2180 2251
2181 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); 2252 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2182 2253
2183 /* Update WMM TXOP register */ 2254 /* Update WMM TXOP register */
2184 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2))); 2255 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
@@ -2239,6 +2310,10 @@ static const struct ieee80211_ops rt73usb_mac80211_ops = {
2239 .conf_tx = rt73usb_conf_tx, 2310 .conf_tx = rt73usb_conf_tx,
2240 .get_tsf = rt73usb_get_tsf, 2311 .get_tsf = rt73usb_get_tsf,
2241 .rfkill_poll = rt2x00mac_rfkill_poll, 2312 .rfkill_poll = rt2x00mac_rfkill_poll,
2313 .flush = rt2x00mac_flush,
2314 .set_antenna = rt2x00mac_set_antenna,
2315 .get_antenna = rt2x00mac_get_antenna,
2316 .get_ringparam = rt2x00mac_get_ringparam,
2242}; 2317};
2243 2318
2244static const struct rt2x00lib_ops rt73usb_rt2x00_ops = { 2319static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
@@ -2255,11 +2330,14 @@ static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2255 .reset_tuner = rt73usb_reset_tuner, 2330 .reset_tuner = rt73usb_reset_tuner,
2256 .link_tuner = rt73usb_link_tuner, 2331 .link_tuner = rt73usb_link_tuner,
2257 .watchdog = rt2x00usb_watchdog, 2332 .watchdog = rt2x00usb_watchdog,
2333 .start_queue = rt73usb_start_queue,
2334 .kick_queue = rt2x00usb_kick_queue,
2335 .stop_queue = rt73usb_stop_queue,
2336 .flush_queue = rt2x00usb_flush_queue,
2258 .write_tx_desc = rt73usb_write_tx_desc, 2337 .write_tx_desc = rt73usb_write_tx_desc,
2259 .write_beacon = rt73usb_write_beacon, 2338 .write_beacon = rt73usb_write_beacon,
2339 .clear_beacon = rt73usb_clear_beacon,
2260 .get_tx_data_len = rt73usb_get_tx_data_len, 2340 .get_tx_data_len = rt73usb_get_tx_data_len,
2261 .kick_tx_queue = rt2x00usb_kick_tx_queue,
2262 .kill_tx_queue = rt2x00usb_kill_tx_queue,
2263 .fill_rxdone = rt73usb_fill_rxdone, 2341 .fill_rxdone = rt73usb_fill_rxdone,
2264 .config_shared_key = rt73usb_config_shared_key, 2342 .config_shared_key = rt73usb_config_shared_key,
2265 .config_pairwise_key = rt73usb_config_pairwise_key, 2343 .config_pairwise_key = rt73usb_config_pairwise_key,
@@ -2271,21 +2349,21 @@ static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2271}; 2349};
2272 2350
2273static const struct data_queue_desc rt73usb_queue_rx = { 2351static const struct data_queue_desc rt73usb_queue_rx = {
2274 .entry_num = RX_ENTRIES, 2352 .entry_num = 32,
2275 .data_size = DATA_FRAME_SIZE, 2353 .data_size = DATA_FRAME_SIZE,
2276 .desc_size = RXD_DESC_SIZE, 2354 .desc_size = RXD_DESC_SIZE,
2277 .priv_size = sizeof(struct queue_entry_priv_usb), 2355 .priv_size = sizeof(struct queue_entry_priv_usb),
2278}; 2356};
2279 2357
2280static const struct data_queue_desc rt73usb_queue_tx = { 2358static const struct data_queue_desc rt73usb_queue_tx = {
2281 .entry_num = TX_ENTRIES, 2359 .entry_num = 32,
2282 .data_size = DATA_FRAME_SIZE, 2360 .data_size = DATA_FRAME_SIZE,
2283 .desc_size = TXD_DESC_SIZE, 2361 .desc_size = TXD_DESC_SIZE,
2284 .priv_size = sizeof(struct queue_entry_priv_usb), 2362 .priv_size = sizeof(struct queue_entry_priv_usb),
2285}; 2363};
2286 2364
2287static const struct data_queue_desc rt73usb_queue_bcn = { 2365static const struct data_queue_desc rt73usb_queue_bcn = {
2288 .entry_num = 4 * BEACON_ENTRIES, 2366 .entry_num = 4,
2289 .data_size = MGMT_FRAME_SIZE, 2367 .data_size = MGMT_FRAME_SIZE,
2290 .desc_size = TXINFO_SIZE, 2368 .desc_size = TXINFO_SIZE,
2291 .priv_size = sizeof(struct queue_entry_priv_usb), 2369 .priv_size = sizeof(struct queue_entry_priv_usb),
@@ -2314,112 +2392,113 @@ static const struct rt2x00_ops rt73usb_ops = {
2314 */ 2392 */
2315static struct usb_device_id rt73usb_device_table[] = { 2393static struct usb_device_id rt73usb_device_table[] = {
2316 /* AboCom */ 2394 /* AboCom */
2317 { USB_DEVICE(0x07b8, 0xb21b), USB_DEVICE_DATA(&rt73usb_ops) }, 2395 { USB_DEVICE(0x07b8, 0xb21b) },
2318 { USB_DEVICE(0x07b8, 0xb21c), USB_DEVICE_DATA(&rt73usb_ops) }, 2396 { USB_DEVICE(0x07b8, 0xb21c) },
2319 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) }, 2397 { USB_DEVICE(0x07b8, 0xb21d) },
2320 { USB_DEVICE(0x07b8, 0xb21e), USB_DEVICE_DATA(&rt73usb_ops) }, 2398 { USB_DEVICE(0x07b8, 0xb21e) },
2321 { USB_DEVICE(0x07b8, 0xb21f), USB_DEVICE_DATA(&rt73usb_ops) }, 2399 { USB_DEVICE(0x07b8, 0xb21f) },
2322 /* AL */ 2400 /* AL */
2323 { USB_DEVICE(0x14b2, 0x3c10), USB_DEVICE_DATA(&rt73usb_ops) }, 2401 { USB_DEVICE(0x14b2, 0x3c10) },
2324 /* Amigo */ 2402 /* Amigo */
2325 { USB_DEVICE(0x148f, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) }, 2403 { USB_DEVICE(0x148f, 0x9021) },
2326 { USB_DEVICE(0x0eb0, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) }, 2404 { USB_DEVICE(0x0eb0, 0x9021) },
2327 /* AMIT */ 2405 /* AMIT */
2328 { USB_DEVICE(0x18c5, 0x0002), USB_DEVICE_DATA(&rt73usb_ops) }, 2406 { USB_DEVICE(0x18c5, 0x0002) },
2329 /* Askey */ 2407 /* Askey */
2330 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) }, 2408 { USB_DEVICE(0x1690, 0x0722) },
2331 /* ASUS */ 2409 /* ASUS */
2332 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) }, 2410 { USB_DEVICE(0x0b05, 0x1723) },
2333 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) }, 2411 { USB_DEVICE(0x0b05, 0x1724) },
2334 /* Belkin */ 2412 /* Belkin */
2335 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) }, 2413 { USB_DEVICE(0x050d, 0x705a) },
2336 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) }, 2414 { USB_DEVICE(0x050d, 0x905b) },
2337 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) }, 2415 { USB_DEVICE(0x050d, 0x905c) },
2338 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
2339 /* Billionton */ 2416 /* Billionton */
2340 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) }, 2417 { USB_DEVICE(0x1631, 0xc019) },
2341 { USB_DEVICE(0x08dd, 0x0120), USB_DEVICE_DATA(&rt73usb_ops) }, 2418 { USB_DEVICE(0x08dd, 0x0120) },
2342 /* Buffalo */ 2419 /* Buffalo */
2343 { USB_DEVICE(0x0411, 0x00d8), USB_DEVICE_DATA(&rt73usb_ops) }, 2420 { USB_DEVICE(0x0411, 0x00d8) },
2344 { USB_DEVICE(0x0411, 0x00d9), USB_DEVICE_DATA(&rt73usb_ops) }, 2421 { USB_DEVICE(0x0411, 0x00d9) },
2345 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) }, 2422 { USB_DEVICE(0x0411, 0x00f4) },
2346 { USB_DEVICE(0x0411, 0x0116), USB_DEVICE_DATA(&rt73usb_ops) }, 2423 { USB_DEVICE(0x0411, 0x0116) },
2347 { USB_DEVICE(0x0411, 0x0119), USB_DEVICE_DATA(&rt73usb_ops) }, 2424 { USB_DEVICE(0x0411, 0x0119) },
2425 { USB_DEVICE(0x0411, 0x0137) },
2348 /* CEIVA */ 2426 /* CEIVA */
2349 { USB_DEVICE(0x178d, 0x02be), USB_DEVICE_DATA(&rt73usb_ops) }, 2427 { USB_DEVICE(0x178d, 0x02be) },
2350 /* CNet */ 2428 /* CNet */
2351 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) }, 2429 { USB_DEVICE(0x1371, 0x9022) },
2352 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) }, 2430 { USB_DEVICE(0x1371, 0x9032) },
2353 /* Conceptronic */ 2431 /* Conceptronic */
2354 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) }, 2432 { USB_DEVICE(0x14b2, 0x3c22) },
2355 /* Corega */ 2433 /* Corega */
2356 { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) }, 2434 { USB_DEVICE(0x07aa, 0x002e) },
2357 /* D-Link */ 2435 /* D-Link */
2358 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) }, 2436 { USB_DEVICE(0x07d1, 0x3c03) },
2359 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) }, 2437 { USB_DEVICE(0x07d1, 0x3c04) },
2360 { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) }, 2438 { USB_DEVICE(0x07d1, 0x3c06) },
2361 { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) }, 2439 { USB_DEVICE(0x07d1, 0x3c07) },
2362 /* Edimax */ 2440 /* Edimax */
2363 { USB_DEVICE(0x7392, 0x7318), USB_DEVICE_DATA(&rt73usb_ops) }, 2441 { USB_DEVICE(0x7392, 0x7318) },
2364 { USB_DEVICE(0x7392, 0x7618), USB_DEVICE_DATA(&rt73usb_ops) }, 2442 { USB_DEVICE(0x7392, 0x7618) },
2365 /* EnGenius */ 2443 /* EnGenius */
2366 { USB_DEVICE(0x1740, 0x3701), USB_DEVICE_DATA(&rt73usb_ops) }, 2444 { USB_DEVICE(0x1740, 0x3701) },
2367 /* Gemtek */ 2445 /* Gemtek */
2368 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) }, 2446 { USB_DEVICE(0x15a9, 0x0004) },
2369 /* Gigabyte */ 2447 /* Gigabyte */
2370 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) }, 2448 { USB_DEVICE(0x1044, 0x8008) },
2371 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) }, 2449 { USB_DEVICE(0x1044, 0x800a) },
2372 /* Huawei-3Com */ 2450 /* Huawei-3Com */
2373 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) }, 2451 { USB_DEVICE(0x1472, 0x0009) },
2374 /* Hercules */ 2452 /* Hercules */
2375 { USB_DEVICE(0x06f8, 0xe002), USB_DEVICE_DATA(&rt73usb_ops) }, 2453 { USB_DEVICE(0x06f8, 0xe002) },
2376 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) }, 2454 { USB_DEVICE(0x06f8, 0xe010) },
2377 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) }, 2455 { USB_DEVICE(0x06f8, 0xe020) },
2378 /* Linksys */ 2456 /* Linksys */
2379 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) }, 2457 { USB_DEVICE(0x13b1, 0x0020) },
2380 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) }, 2458 { USB_DEVICE(0x13b1, 0x0023) },
2381 { USB_DEVICE(0x13b1, 0x0028), USB_DEVICE_DATA(&rt73usb_ops) }, 2459 { USB_DEVICE(0x13b1, 0x0028) },
2382 /* MSI */ 2460 /* MSI */
2383 { USB_DEVICE(0x0db0, 0x4600), USB_DEVICE_DATA(&rt73usb_ops) }, 2461 { USB_DEVICE(0x0db0, 0x4600) },
2384 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) }, 2462 { USB_DEVICE(0x0db0, 0x6877) },
2385 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) }, 2463 { USB_DEVICE(0x0db0, 0x6874) },
2386 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) }, 2464 { USB_DEVICE(0x0db0, 0xa861) },
2387 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) }, 2465 { USB_DEVICE(0x0db0, 0xa874) },
2388 /* Ovislink */ 2466 /* Ovislink */
2389 { USB_DEVICE(0x1b75, 0x7318), USB_DEVICE_DATA(&rt73usb_ops) }, 2467 { USB_DEVICE(0x1b75, 0x7318) },
2390 /* Ralink */ 2468 /* Ralink */
2391 { USB_DEVICE(0x04bb, 0x093d), USB_DEVICE_DATA(&rt73usb_ops) }, 2469 { USB_DEVICE(0x04bb, 0x093d) },
2392 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) }, 2470 { USB_DEVICE(0x148f, 0x2573) },
2393 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) }, 2471 { USB_DEVICE(0x148f, 0x2671) },
2472 { USB_DEVICE(0x0812, 0x3101) },
2394 /* Qcom */ 2473 /* Qcom */
2395 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) }, 2474 { USB_DEVICE(0x18e8, 0x6196) },
2396 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) }, 2475 { USB_DEVICE(0x18e8, 0x6229) },
2397 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) }, 2476 { USB_DEVICE(0x18e8, 0x6238) },
2398 /* Samsung */ 2477 /* Samsung */
2399 { USB_DEVICE(0x04e8, 0x4471), USB_DEVICE_DATA(&rt73usb_ops) }, 2478 { USB_DEVICE(0x04e8, 0x4471) },
2400 /* Senao */ 2479 /* Senao */
2401 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) }, 2480 { USB_DEVICE(0x1740, 0x7100) },
2402 /* Sitecom */ 2481 /* Sitecom */
2403 { USB_DEVICE(0x0df6, 0x0024), USB_DEVICE_DATA(&rt73usb_ops) }, 2482 { USB_DEVICE(0x0df6, 0x0024) },
2404 { USB_DEVICE(0x0df6, 0x0027), USB_DEVICE_DATA(&rt73usb_ops) }, 2483 { USB_DEVICE(0x0df6, 0x0027) },
2405 { USB_DEVICE(0x0df6, 0x002f), USB_DEVICE_DATA(&rt73usb_ops) }, 2484 { USB_DEVICE(0x0df6, 0x002f) },
2406 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) }, 2485 { USB_DEVICE(0x0df6, 0x90ac) },
2407 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) }, 2486 { USB_DEVICE(0x0df6, 0x9712) },
2408 /* Surecom */ 2487 /* Surecom */
2409 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) }, 2488 { USB_DEVICE(0x0769, 0x31f3) },
2410 /* Tilgin */ 2489 /* Tilgin */
2411 { USB_DEVICE(0x6933, 0x5001), USB_DEVICE_DATA(&rt73usb_ops) }, 2490 { USB_DEVICE(0x6933, 0x5001) },
2412 /* Philips */ 2491 /* Philips */
2413 { USB_DEVICE(0x0471, 0x200a), USB_DEVICE_DATA(&rt73usb_ops) }, 2492 { USB_DEVICE(0x0471, 0x200a) },
2414 /* Planex */ 2493 /* Planex */
2415 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) }, 2494 { USB_DEVICE(0x2019, 0xab01) },
2416 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) }, 2495 { USB_DEVICE(0x2019, 0xab50) },
2417 /* WideTell */ 2496 /* WideTell */
2418 { USB_DEVICE(0x7167, 0x3840), USB_DEVICE_DATA(&rt73usb_ops) }, 2497 { USB_DEVICE(0x7167, 0x3840) },
2419 /* Zcom */ 2498 /* Zcom */
2420 { USB_DEVICE(0x0cde, 0x001c), USB_DEVICE_DATA(&rt73usb_ops) }, 2499 { USB_DEVICE(0x0cde, 0x001c) },
2421 /* ZyXEL */ 2500 /* ZyXEL */
2422 { USB_DEVICE(0x0586, 0x3415), USB_DEVICE_DATA(&rt73usb_ops) }, 2501 { USB_DEVICE(0x0586, 0x3415) },
2423 { 0, } 2502 { 0, }
2424}; 2503};
2425 2504
@@ -2431,10 +2510,16 @@ MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2431MODULE_FIRMWARE(FIRMWARE_RT2571); 2510MODULE_FIRMWARE(FIRMWARE_RT2571);
2432MODULE_LICENSE("GPL"); 2511MODULE_LICENSE("GPL");
2433 2512
2513static int rt73usb_probe(struct usb_interface *usb_intf,
2514 const struct usb_device_id *id)
2515{
2516 return rt2x00usb_probe(usb_intf, &rt73usb_ops);
2517}
2518
2434static struct usb_driver rt73usb_driver = { 2519static struct usb_driver rt73usb_driver = {
2435 .name = KBUILD_MODNAME, 2520 .name = KBUILD_MODNAME,
2436 .id_table = rt73usb_device_table, 2521 .id_table = rt73usb_device_table,
2437 .probe = rt2x00usb_probe, 2522 .probe = rt73usb_probe,
2438 .disconnect = rt2x00usb_disconnect, 2523 .disconnect = rt2x00usb_disconnect,
2439 .suspend = rt2x00usb_suspend, 2524 .suspend = rt2x00usb_suspend,
2440 .resume = rt2x00usb_resume, 2525 .resume = rt2x00usb_resume,
diff --git a/drivers/net/wireless/rt2x00/rt73usb.h b/drivers/net/wireless/rt2x00/rt73usb.h
index 44d5b2bebd39..9f6b470414d3 100644
--- a/drivers/net/wireless/rt2x00/rt73usb.h
+++ b/drivers/net/wireless/rt2x00/rt73usb.h
@@ -322,7 +322,7 @@ struct hw_pairwise_ta_entry {
322 * DROP_VERSION_ERROR: Drop version error frame. 322 * DROP_VERSION_ERROR: Drop version error frame.
323 * DROP_MULTICAST: Drop multicast frames. 323 * DROP_MULTICAST: Drop multicast frames.
324 * DROP_BORADCAST: Drop broadcast frames. 324 * DROP_BORADCAST: Drop broadcast frames.
325 * ROP_ACK_CTS: Drop received ACK and CTS. 325 * DROP_ACK_CTS: Drop received ACK and CTS.
326 */ 326 */
327#define TXRX_CSR0 0x3040 327#define TXRX_CSR0 0x3040
328#define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff) 328#define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff)
@@ -689,10 +689,10 @@ struct hw_pairwise_ta_entry {
689 689
690/* 690/*
691 * AIFSN_CSR: AIFSN for each EDCA AC. 691 * AIFSN_CSR: AIFSN for each EDCA AC.
692 * AIFSN0: For AC_BK. 692 * AIFSN0: For AC_VO.
693 * AIFSN1: For AC_BE. 693 * AIFSN1: For AC_VI.
694 * AIFSN2: For AC_VI. 694 * AIFSN2: For AC_BE.
695 * AIFSN3: For AC_VO. 695 * AIFSN3: For AC_BK.
696 */ 696 */
697#define AIFSN_CSR 0x0400 697#define AIFSN_CSR 0x0400
698#define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f) 698#define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f)
@@ -702,10 +702,10 @@ struct hw_pairwise_ta_entry {
702 702
703/* 703/*
704 * CWMIN_CSR: CWmin for each EDCA AC. 704 * CWMIN_CSR: CWmin for each EDCA AC.
705 * CWMIN0: For AC_BK. 705 * CWMIN0: For AC_VO.
706 * CWMIN1: For AC_BE. 706 * CWMIN1: For AC_VI.
707 * CWMIN2: For AC_VI. 707 * CWMIN2: For AC_BE.
708 * CWMIN3: For AC_VO. 708 * CWMIN3: For AC_BK.
709 */ 709 */
710#define CWMIN_CSR 0x0404 710#define CWMIN_CSR 0x0404
711#define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f) 711#define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f)
@@ -715,10 +715,10 @@ struct hw_pairwise_ta_entry {
715 715
716/* 716/*
717 * CWMAX_CSR: CWmax for each EDCA AC. 717 * CWMAX_CSR: CWmax for each EDCA AC.
718 * CWMAX0: For AC_BK. 718 * CWMAX0: For AC_VO.
719 * CWMAX1: For AC_BE. 719 * CWMAX1: For AC_VI.
720 * CWMAX2: For AC_VI. 720 * CWMAX2: For AC_BE.
721 * CWMAX3: For AC_VO. 721 * CWMAX3: For AC_BK.
722 */ 722 */
723#define CWMAX_CSR 0x0408 723#define CWMAX_CSR 0x0408
724#define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f) 724#define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f)
@@ -727,18 +727,18 @@ struct hw_pairwise_ta_entry {
727#define CWMAX_CSR_CWMAX3 FIELD32(0x0000f000) 727#define CWMAX_CSR_CWMAX3 FIELD32(0x0000f000)
728 728
729/* 729/*
730 * AC_TXOP_CSR0: AC_BK/AC_BE TXOP register. 730 * AC_TXOP_CSR0: AC_VO/AC_VI TXOP register.
731 * AC0_TX_OP: For AC_BK, in unit of 32us. 731 * AC0_TX_OP: For AC_VO, in unit of 32us.
732 * AC1_TX_OP: For AC_BE, in unit of 32us. 732 * AC1_TX_OP: For AC_VI, in unit of 32us.
733 */ 733 */
734#define AC_TXOP_CSR0 0x040c 734#define AC_TXOP_CSR0 0x040c
735#define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff) 735#define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff)
736#define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000) 736#define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000)
737 737
738/* 738/*
739 * AC_TXOP_CSR1: AC_VO/AC_VI TXOP register. 739 * AC_TXOP_CSR1: AC_BE/AC_BK TXOP register.
740 * AC2_TX_OP: For AC_VI, in unit of 32us. 740 * AC2_TX_OP: For AC_BE, in unit of 32us.
741 * AC3_TX_OP: For AC_VO, in unit of 32us. 741 * AC3_TX_OP: For AC_BK, in unit of 32us.
742 */ 742 */
743#define AC_TXOP_CSR1 0x0410 743#define AC_TXOP_CSR1 0x0410
744#define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff) 744#define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff)
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-06 23:18:35 -0400