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path: root/drivers/net/wireless/rt2x00/rt2500pci.c
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Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2500pci.c')
-rw-r--r--drivers/net/wireless/rt2x00/rt2500pci.c489
1 files changed, 312 insertions, 177 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2500pci.c b/drivers/net/wireless/rt2x00/rt2500pci.c
index c2a555d5376b..d27d7b8ba3b6 100644
--- a/drivers/net/wireless/rt2x00/rt2500pci.c
+++ b/drivers/net/wireless/rt2x00/rt2500pci.c
@@ -293,7 +293,7 @@ static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
293 struct rt2x00intf_conf *conf, 293 struct rt2x00intf_conf *conf,
294 const unsigned int flags) 294 const unsigned int flags)
295{ 295{
296 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON); 296 struct data_queue *queue = rt2x00dev->bcn;
297 unsigned int bcn_preload; 297 unsigned int bcn_preload;
298 u32 reg; 298 u32 reg;
299 299
@@ -311,9 +311,7 @@ static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
311 * Enable synchronisation. 311 * Enable synchronisation.
312 */ 312 */
313 rt2x00pci_register_read(rt2x00dev, CSR14, &reg); 313 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
314 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
315 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync); 314 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
316 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
317 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 315 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
318 } 316 }
319 317
@@ -327,7 +325,8 @@ static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
327} 325}
328 326
329static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev, 327static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
330 struct rt2x00lib_erp *erp) 328 struct rt2x00lib_erp *erp,
329 u32 changed)
331{ 330{
332 int preamble_mask; 331 int preamble_mask;
333 u32 reg; 332 u32 reg;
@@ -335,59 +334,73 @@ static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
335 /* 334 /*
336 * When short preamble is enabled, we should set bit 0x08 335 * When short preamble is enabled, we should set bit 0x08
337 */ 336 */
338 preamble_mask = erp->short_preamble << 3; 337 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
339 338 preamble_mask = erp->short_preamble << 3;
340 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg); 339
341 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x162); 340 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
342 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0xa2); 341 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x162);
343 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER); 342 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0xa2);
344 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1); 343 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
345 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg); 344 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
346 345 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
347 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg); 346
348 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00); 347 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
349 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04); 348 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
350 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10)); 349 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
351 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg); 350 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
352 351 GET_DURATION(ACK_SIZE, 10));
353 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg); 352 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
354 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask); 353
355 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04); 354 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
356 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20)); 355 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
357 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg); 356 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
358 357 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
359 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg); 358 GET_DURATION(ACK_SIZE, 20));
360 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask); 359 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
361 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04); 360
362 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55)); 361 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
363 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg); 362 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
364 363 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
365 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg); 364 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
366 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask); 365 GET_DURATION(ACK_SIZE, 55));
367 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84); 366 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
368 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110)); 367
369 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg); 368 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
370 369 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
371 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates); 370 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
371 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
372 GET_DURATION(ACK_SIZE, 110));
373 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
374 }
372 375
373 rt2x00pci_register_read(rt2x00dev, CSR11, &reg); 376 if (changed & BSS_CHANGED_BASIC_RATES)
374 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time); 377 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
375 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
376 378
377 rt2x00pci_register_read(rt2x00dev, CSR12, &reg); 379 if (changed & BSS_CHANGED_ERP_SLOT) {
378 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, erp->beacon_int * 16); 380 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
379 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, erp->beacon_int * 16); 381 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
380 rt2x00pci_register_write(rt2x00dev, CSR12, reg); 382 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
381 383
382 rt2x00pci_register_read(rt2x00dev, CSR18, &reg); 384 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
383 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs); 385 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
384 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs); 386 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
385 rt2x00pci_register_write(rt2x00dev, CSR18, reg); 387 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
388
389 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
390 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
391 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
392 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
393 }
394
395 if (changed & BSS_CHANGED_BEACON_INT) {
396 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
397 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
398 erp->beacon_int * 16);
399 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
400 erp->beacon_int * 16);
401 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
402 }
386 403
387 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
388 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
389 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
390 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
391} 404}
392 405
393static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev, 406static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
@@ -708,6 +721,98 @@ dynamic_cca_tune:
708} 721}
709 722
710/* 723/*
724 * Queue handlers.
725 */
726static void rt2500pci_start_queue(struct data_queue *queue)
727{
728 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
729 u32 reg;
730
731 switch (queue->qid) {
732 case QID_RX:
733 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
734 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
735 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
736 break;
737 case QID_BEACON:
738 /*
739 * Allow the tbtt tasklet to be scheduled.
740 */
741 tasklet_enable(&rt2x00dev->tbtt_tasklet);
742
743 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
744 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
745 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
746 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
747 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
748 break;
749 default:
750 break;
751 }
752}
753
754static void rt2500pci_kick_queue(struct data_queue *queue)
755{
756 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
757 u32 reg;
758
759 switch (queue->qid) {
760 case QID_AC_VO:
761 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
762 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
763 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
764 break;
765 case QID_AC_VI:
766 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
767 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
768 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
769 break;
770 case QID_ATIM:
771 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
772 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
773 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
774 break;
775 default:
776 break;
777 }
778}
779
780static void rt2500pci_stop_queue(struct data_queue *queue)
781{
782 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
783 u32 reg;
784
785 switch (queue->qid) {
786 case QID_AC_VO:
787 case QID_AC_VI:
788 case QID_ATIM:
789 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
790 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
791 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
792 break;
793 case QID_RX:
794 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
795 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
796 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
797 break;
798 case QID_BEACON:
799 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
800 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
801 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
802 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
803 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
804
805 /*
806 * Wait for possibly running tbtt tasklets.
807 */
808 tasklet_disable(&rt2x00dev->tbtt_tasklet);
809 break;
810 default:
811 break;
812 }
813}
814
815/*
711 * Initialization functions. 816 * Initialization functions.
712 */ 817 */
713static bool rt2500pci_get_entry_state(struct queue_entry *entry) 818static bool rt2500pci_get_entry_state(struct queue_entry *entry)
@@ -760,7 +865,7 @@ static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
760 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg); 865 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
761 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); 866 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
762 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); 867 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
763 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit); 868 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
764 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); 869 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
765 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg); 870 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
766 871
@@ -776,13 +881,13 @@ static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
776 entry_priv->desc_dma); 881 entry_priv->desc_dma);
777 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); 882 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
778 883
779 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data; 884 entry_priv = rt2x00dev->atim->entries[0].priv_data;
780 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg); 885 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
781 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER, 886 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
782 entry_priv->desc_dma); 887 entry_priv->desc_dma);
783 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); 888 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
784 889
785 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data; 890 entry_priv = rt2x00dev->bcn->entries[0].priv_data;
786 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg); 891 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
787 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER, 892 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
788 entry_priv->desc_dma); 893 entry_priv->desc_dma);
@@ -1018,24 +1123,12 @@ static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1018/* 1123/*
1019 * Device state switch handlers. 1124 * Device state switch handlers.
1020 */ 1125 */
1021static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1022 enum dev_state state)
1023{
1024 u32 reg;
1025
1026 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1027 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1028 (state == STATE_RADIO_RX_OFF) ||
1029 (state == STATE_RADIO_RX_OFF_LINK));
1030 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1031}
1032
1033static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev, 1126static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1034 enum dev_state state) 1127 enum dev_state state)
1035{ 1128{
1036 int mask = (state == STATE_RADIO_IRQ_OFF) || 1129 int mask = (state == STATE_RADIO_IRQ_OFF);
1037 (state == STATE_RADIO_IRQ_OFF_ISR);
1038 u32 reg; 1130 u32 reg;
1131 unsigned long flags;
1039 1132
1040 /* 1133 /*
1041 * When interrupts are being enabled, the interrupt registers 1134 * When interrupts are being enabled, the interrupt registers
@@ -1044,12 +1137,20 @@ static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1044 if (state == STATE_RADIO_IRQ_ON) { 1137 if (state == STATE_RADIO_IRQ_ON) {
1045 rt2x00pci_register_read(rt2x00dev, CSR7, &reg); 1138 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1046 rt2x00pci_register_write(rt2x00dev, CSR7, reg); 1139 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1140
1141 /*
1142 * Enable tasklets.
1143 */
1144 tasklet_enable(&rt2x00dev->txstatus_tasklet);
1145 tasklet_enable(&rt2x00dev->rxdone_tasklet);
1047 } 1146 }
1048 1147
1049 /* 1148 /*
1050 * Only toggle the interrupts bits we are going to use. 1149 * Only toggle the interrupts bits we are going to use.
1051 * Non-checked interrupt bits are disabled by default. 1150 * Non-checked interrupt bits are disabled by default.
1052 */ 1151 */
1152 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
1153
1053 rt2x00pci_register_read(rt2x00dev, CSR8, &reg); 1154 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1054 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask); 1155 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1055 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask); 1156 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
@@ -1057,6 +1158,16 @@ static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1057 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask); 1158 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1058 rt2x00_set_field32(&reg, CSR8_RXDONE, mask); 1159 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1059 rt2x00pci_register_write(rt2x00dev, CSR8, reg); 1160 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1161
1162 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
1163
1164 if (state == STATE_RADIO_IRQ_OFF) {
1165 /*
1166 * Ensure that all tasklets are finished.
1167 */
1168 tasklet_disable(&rt2x00dev->txstatus_tasklet);
1169 tasklet_disable(&rt2x00dev->rxdone_tasklet);
1170 }
1060} 1171}
1061 1172
1062static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev) 1173static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
@@ -1128,16 +1239,8 @@ static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1128 case STATE_RADIO_OFF: 1239 case STATE_RADIO_OFF:
1129 rt2500pci_disable_radio(rt2x00dev); 1240 rt2500pci_disable_radio(rt2x00dev);
1130 break; 1241 break;
1131 case STATE_RADIO_RX_ON:
1132 case STATE_RADIO_RX_ON_LINK:
1133 case STATE_RADIO_RX_OFF:
1134 case STATE_RADIO_RX_OFF_LINK:
1135 rt2500pci_toggle_rx(rt2x00dev, state);
1136 break;
1137 case STATE_RADIO_IRQ_ON: 1242 case STATE_RADIO_IRQ_ON:
1138 case STATE_RADIO_IRQ_ON_ISR:
1139 case STATE_RADIO_IRQ_OFF: 1243 case STATE_RADIO_IRQ_OFF:
1140 case STATE_RADIO_IRQ_OFF_ISR:
1141 rt2500pci_toggle_irq(rt2x00dev, state); 1244 rt2500pci_toggle_irq(rt2x00dev, state);
1142 break; 1245 break;
1143 case STATE_DEEP_SLEEP: 1246 case STATE_DEEP_SLEEP:
@@ -1161,12 +1264,11 @@ static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1161/* 1264/*
1162 * TX descriptor initialization 1265 * TX descriptor initialization
1163 */ 1266 */
1164static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, 1267static void rt2500pci_write_tx_desc(struct queue_entry *entry,
1165 struct sk_buff *skb,
1166 struct txentry_desc *txdesc) 1268 struct txentry_desc *txdesc)
1167{ 1269{
1168 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 1270 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1169 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data; 1271 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1170 __le32 *txd = entry_priv->desc; 1272 __le32 *txd = entry_priv->desc;
1171 u32 word; 1273 u32 word;
1172 1274
@@ -1179,16 +1281,18 @@ static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1179 1281
1180 rt2x00_desc_read(txd, 2, &word); 1282 rt2x00_desc_read(txd, 2, &word);
1181 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER); 1283 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1182 rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs); 1284 rt2x00_set_field32(&word, TXD_W2_AIFS, entry->queue->aifs);
1183 rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min); 1285 rt2x00_set_field32(&word, TXD_W2_CWMIN, entry->queue->cw_min);
1184 rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max); 1286 rt2x00_set_field32(&word, TXD_W2_CWMAX, entry->queue->cw_max);
1185 rt2x00_desc_write(txd, 2, word); 1287 rt2x00_desc_write(txd, 2, word);
1186 1288
1187 rt2x00_desc_read(txd, 3, &word); 1289 rt2x00_desc_read(txd, 3, &word);
1188 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal); 1290 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
1189 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service); 1291 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);
1190 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low); 1292 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW,
1191 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high); 1293 txdesc->u.plcp.length_low);
1294 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH,
1295 txdesc->u.plcp.length_high);
1192 rt2x00_desc_write(txd, 3, word); 1296 rt2x00_desc_write(txd, 3, word);
1193 1297
1194 rt2x00_desc_read(txd, 10, &word); 1298 rt2x00_desc_read(txd, 10, &word);
@@ -1213,7 +1317,7 @@ static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1213 rt2x00_set_field32(&word, TXD_W0_OFDM, 1317 rt2x00_set_field32(&word, TXD_W0_OFDM,
1214 (txdesc->rate_mode == RATE_MODE_OFDM)); 1318 (txdesc->rate_mode == RATE_MODE_OFDM));
1215 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1); 1319 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1216 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); 1320 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1217 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 1321 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1218 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); 1322 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1219 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length); 1323 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
@@ -1244,12 +1348,12 @@ static void rt2500pci_write_beacon(struct queue_entry *entry,
1244 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0); 1348 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1245 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 1349 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1246 1350
1247 rt2x00queue_map_txskb(rt2x00dev, entry->skb); 1351 rt2x00queue_map_txskb(entry);
1248 1352
1249 /* 1353 /*
1250 * Write the TX descriptor for the beacon. 1354 * Write the TX descriptor for the beacon.
1251 */ 1355 */
1252 rt2500pci_write_tx_desc(rt2x00dev, entry->skb, txdesc); 1356 rt2500pci_write_tx_desc(entry, txdesc);
1253 1357
1254 /* 1358 /*
1255 * Dump beacon to userspace through debugfs. 1359 * Dump beacon to userspace through debugfs.
@@ -1259,38 +1363,10 @@ static void rt2500pci_write_beacon(struct queue_entry *entry,
1259 /* 1363 /*
1260 * Enable beaconing again. 1364 * Enable beaconing again.
1261 */ 1365 */
1262 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1263 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1264 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1); 1366 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1265 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 1367 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1266} 1368}
1267 1369
1268static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1269 const enum data_queue_qid queue)
1270{
1271 u32 reg;
1272
1273 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1274 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1275 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1276 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1277 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1278}
1279
1280static void rt2500pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1281 const enum data_queue_qid qid)
1282{
1283 u32 reg;
1284
1285 if (qid == QID_BEACON) {
1286 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1287 } else {
1288 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1289 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1290 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1291 }
1292}
1293
1294/* 1370/*
1295 * RX control handlers 1371 * RX control handlers
1296 */ 1372 */
@@ -1334,7 +1410,7 @@ static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1334static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, 1410static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1335 const enum data_queue_qid queue_idx) 1411 const enum data_queue_qid queue_idx)
1336{ 1412{
1337 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); 1413 struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
1338 struct queue_entry_priv_pci *entry_priv; 1414 struct queue_entry_priv_pci *entry_priv;
1339 struct queue_entry *entry; 1415 struct queue_entry *entry;
1340 struct txdone_entry_desc txdesc; 1416 struct txdone_entry_desc txdesc;
@@ -1370,58 +1446,70 @@ static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1370 } 1446 }
1371} 1447}
1372 1448
1373static irqreturn_t rt2500pci_interrupt_thread(int irq, void *dev_instance) 1449static inline void rt2500pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
1450 struct rt2x00_field32 irq_field)
1374{ 1451{
1375 struct rt2x00_dev *rt2x00dev = dev_instance; 1452 u32 reg;
1376 u32 reg = rt2x00dev->irqvalue[0];
1377 1453
1378 /* 1454 /*
1379 * Handle interrupts, walk through all bits 1455 * Enable a single interrupt. The interrupt mask register
1380 * and run the tasks, the bits are checked in order of 1456 * access needs locking.
1381 * priority.
1382 */ 1457 */
1458 spin_lock_irq(&rt2x00dev->irqmask_lock);
1383 1459
1384 /* 1460 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1385 * 1 - Beacon timer expired interrupt. 1461 rt2x00_set_field32(&reg, irq_field, 0);
1386 */ 1462 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1387 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1388 rt2x00lib_beacondone(rt2x00dev);
1389 1463
1390 /* 1464 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1391 * 2 - Rx ring done interrupt. 1465}
1392 */
1393 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1394 rt2x00pci_rxdone(rt2x00dev);
1395 1466
1396 /* 1467static void rt2500pci_txstatus_tasklet(unsigned long data)
1397 * 3 - Atim ring transmit done interrupt. 1468{
1398 */ 1469 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1399 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING)) 1470 u32 reg;
1400 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1401 1471
1402 /* 1472 /*
1403 * 4 - Priority ring transmit done interrupt. 1473 * Handle all tx queues.
1404 */ 1474 */
1405 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING)) 1475 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1406 rt2500pci_txdone(rt2x00dev, QID_AC_BE); 1476 rt2500pci_txdone(rt2x00dev, QID_AC_VO);
1477 rt2500pci_txdone(rt2x00dev, QID_AC_VI);
1407 1478
1408 /* 1479 /*
1409 * 5 - Tx ring transmit done interrupt. 1480 * Enable all TXDONE interrupts again.
1410 */ 1481 */
1411 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) 1482 spin_lock_irq(&rt2x00dev->irqmask_lock);
1412 rt2500pci_txdone(rt2x00dev, QID_AC_BK);
1413 1483
1414 /* Enable interrupts again. */ 1484 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1415 rt2x00dev->ops->lib->set_device_state(rt2x00dev, 1485 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);
1416 STATE_RADIO_IRQ_ON_ISR); 1486 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);
1487 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
1488 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1417 1489
1418 return IRQ_HANDLED; 1490 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1491}
1492
1493static void rt2500pci_tbtt_tasklet(unsigned long data)
1494{
1495 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1496 rt2x00lib_beacondone(rt2x00dev);
1497 rt2500pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
1498}
1499
1500static void rt2500pci_rxdone_tasklet(unsigned long data)
1501{
1502 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1503 if (rt2x00pci_rxdone(rt2x00dev))
1504 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1505 else
1506 rt2500pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
1419} 1507}
1420 1508
1421static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance) 1509static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1422{ 1510{
1423 struct rt2x00_dev *rt2x00dev = dev_instance; 1511 struct rt2x00_dev *rt2x00dev = dev_instance;
1424 u32 reg; 1512 u32 reg, mask;
1425 1513
1426 /* 1514 /*
1427 * Get the interrupt sources & saved to local variable. 1515 * Get the interrupt sources & saved to local variable.
@@ -1436,14 +1524,42 @@ static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1436 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 1524 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1437 return IRQ_HANDLED; 1525 return IRQ_HANDLED;
1438 1526
1439 /* Store irqvalues for use in the interrupt thread. */ 1527 mask = reg;
1440 rt2x00dev->irqvalue[0] = reg; 1528
1529 /*
1530 * Schedule tasklets for interrupt handling.
1531 */
1532 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1533 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
1534
1535 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1536 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1537
1538 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
1539 rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
1540 rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
1541 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
1542 /*
1543 * Mask out all txdone interrupts.
1544 */
1545 rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
1546 rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
1547 rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
1548 }
1549
1550 /*
1551 * Disable all interrupts for which a tasklet was scheduled right now,
1552 * the tasklet will reenable the appropriate interrupts.
1553 */
1554 spin_lock(&rt2x00dev->irqmask_lock);
1555
1556 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1557 reg |= mask;
1558 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1441 1559
1442 /* Disable interrupts, will be enabled again in the interrupt thread. */ 1560 spin_unlock(&rt2x00dev->irqmask_lock);
1443 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
1444 STATE_RADIO_IRQ_OFF_ISR);
1445 1561
1446 return IRQ_WAKE_THREAD; 1562 return IRQ_HANDLED;
1447} 1563}
1448 1564
1449/* 1565/*
@@ -1571,14 +1687,14 @@ static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1571 * Detect if this device has an hardware controlled radio. 1687 * Detect if this device has an hardware controlled radio.
1572 */ 1688 */
1573 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) 1689 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1574 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags); 1690 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
1575 1691
1576 /* 1692 /*
1577 * Check if the BBP tuning should be enabled. 1693 * Check if the BBP tuning should be enabled.
1578 */ 1694 */
1579 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); 1695 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1580 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE)) 1696 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1581 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags); 1697 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
1582 1698
1583 /* 1699 /*
1584 * Read the RSSI <-> dBm offset information. 1700 * Read the RSSI <-> dBm offset information.
@@ -1795,19 +1911,23 @@ static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1795 /* 1911 /*
1796 * Create channel information array 1912 * Create channel information array
1797 */ 1913 */
1798 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL); 1914 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
1799 if (!info) 1915 if (!info)
1800 return -ENOMEM; 1916 return -ENOMEM;
1801 1917
1802 spec->channels_info = info; 1918 spec->channels_info = info;
1803 1919
1804 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START); 1920 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1805 for (i = 0; i < 14; i++) 1921 for (i = 0; i < 14; i++) {
1806 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]); 1922 info[i].max_power = MAX_TXPOWER;
1923 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1924 }
1807 1925
1808 if (spec->num_channels > 14) { 1926 if (spec->num_channels > 14) {
1809 for (i = 14; i < spec->num_channels; i++) 1927 for (i = 14; i < spec->num_channels; i++) {
1810 info[i].tx_power1 = DEFAULT_TXPOWER; 1928 info[i].max_power = MAX_TXPOWER;
1929 info[i].default_power1 = DEFAULT_TXPOWER;
1930 }
1811 } 1931 }
1812 1932
1813 return 0; 1933 return 0;
@@ -1838,8 +1958,9 @@ static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1838 /* 1958 /*
1839 * This device requires the atim queue and DMA-mapped skbs. 1959 * This device requires the atim queue and DMA-mapped skbs.
1840 */ 1960 */
1841 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags); 1961 __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
1842 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags); 1962 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
1963 __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
1843 1964
1844 /* 1965 /*
1845 * Set the rssi offset. 1966 * Set the rssi offset.
@@ -1891,11 +2012,17 @@ static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1891 .get_tsf = rt2500pci_get_tsf, 2012 .get_tsf = rt2500pci_get_tsf,
1892 .tx_last_beacon = rt2500pci_tx_last_beacon, 2013 .tx_last_beacon = rt2500pci_tx_last_beacon,
1893 .rfkill_poll = rt2x00mac_rfkill_poll, 2014 .rfkill_poll = rt2x00mac_rfkill_poll,
2015 .flush = rt2x00mac_flush,
2016 .set_antenna = rt2x00mac_set_antenna,
2017 .get_antenna = rt2x00mac_get_antenna,
2018 .get_ringparam = rt2x00mac_get_ringparam,
1894}; 2019};
1895 2020
1896static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = { 2021static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1897 .irq_handler = rt2500pci_interrupt, 2022 .irq_handler = rt2500pci_interrupt,
1898 .irq_handler_thread = rt2500pci_interrupt_thread, 2023 .txstatus_tasklet = rt2500pci_txstatus_tasklet,
2024 .tbtt_tasklet = rt2500pci_tbtt_tasklet,
2025 .rxdone_tasklet = rt2500pci_rxdone_tasklet,
1899 .probe_hw = rt2500pci_probe_hw, 2026 .probe_hw = rt2500pci_probe_hw,
1900 .initialize = rt2x00pci_initialize, 2027 .initialize = rt2x00pci_initialize,
1901 .uninitialize = rt2x00pci_uninitialize, 2028 .uninitialize = rt2x00pci_uninitialize,
@@ -1906,10 +2033,12 @@ static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1906 .link_stats = rt2500pci_link_stats, 2033 .link_stats = rt2500pci_link_stats,
1907 .reset_tuner = rt2500pci_reset_tuner, 2034 .reset_tuner = rt2500pci_reset_tuner,
1908 .link_tuner = rt2500pci_link_tuner, 2035 .link_tuner = rt2500pci_link_tuner,
2036 .start_queue = rt2500pci_start_queue,
2037 .kick_queue = rt2500pci_kick_queue,
2038 .stop_queue = rt2500pci_stop_queue,
2039 .flush_queue = rt2x00pci_flush_queue,
1909 .write_tx_desc = rt2500pci_write_tx_desc, 2040 .write_tx_desc = rt2500pci_write_tx_desc,
1910 .write_beacon = rt2500pci_write_beacon, 2041 .write_beacon = rt2500pci_write_beacon,
1911 .kick_tx_queue = rt2500pci_kick_tx_queue,
1912 .kill_tx_queue = rt2500pci_kill_tx_queue,
1913 .fill_rxdone = rt2500pci_fill_rxdone, 2042 .fill_rxdone = rt2500pci_fill_rxdone,
1914 .config_filter = rt2500pci_config_filter, 2043 .config_filter = rt2500pci_config_filter,
1915 .config_intf = rt2500pci_config_intf, 2044 .config_intf = rt2500pci_config_intf,
@@ -1919,28 +2048,28 @@ static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1919}; 2048};
1920 2049
1921static const struct data_queue_desc rt2500pci_queue_rx = { 2050static const struct data_queue_desc rt2500pci_queue_rx = {
1922 .entry_num = RX_ENTRIES, 2051 .entry_num = 32,
1923 .data_size = DATA_FRAME_SIZE, 2052 .data_size = DATA_FRAME_SIZE,
1924 .desc_size = RXD_DESC_SIZE, 2053 .desc_size = RXD_DESC_SIZE,
1925 .priv_size = sizeof(struct queue_entry_priv_pci), 2054 .priv_size = sizeof(struct queue_entry_priv_pci),
1926}; 2055};
1927 2056
1928static const struct data_queue_desc rt2500pci_queue_tx = { 2057static const struct data_queue_desc rt2500pci_queue_tx = {
1929 .entry_num = TX_ENTRIES, 2058 .entry_num = 32,
1930 .data_size = DATA_FRAME_SIZE, 2059 .data_size = DATA_FRAME_SIZE,
1931 .desc_size = TXD_DESC_SIZE, 2060 .desc_size = TXD_DESC_SIZE,
1932 .priv_size = sizeof(struct queue_entry_priv_pci), 2061 .priv_size = sizeof(struct queue_entry_priv_pci),
1933}; 2062};
1934 2063
1935static const struct data_queue_desc rt2500pci_queue_bcn = { 2064static const struct data_queue_desc rt2500pci_queue_bcn = {
1936 .entry_num = BEACON_ENTRIES, 2065 .entry_num = 1,
1937 .data_size = MGMT_FRAME_SIZE, 2066 .data_size = MGMT_FRAME_SIZE,
1938 .desc_size = TXD_DESC_SIZE, 2067 .desc_size = TXD_DESC_SIZE,
1939 .priv_size = sizeof(struct queue_entry_priv_pci), 2068 .priv_size = sizeof(struct queue_entry_priv_pci),
1940}; 2069};
1941 2070
1942static const struct data_queue_desc rt2500pci_queue_atim = { 2071static const struct data_queue_desc rt2500pci_queue_atim = {
1943 .entry_num = ATIM_ENTRIES, 2072 .entry_num = 8,
1944 .data_size = DATA_FRAME_SIZE, 2073 .data_size = DATA_FRAME_SIZE,
1945 .desc_size = TXD_DESC_SIZE, 2074 .desc_size = TXD_DESC_SIZE,
1946 .priv_size = sizeof(struct queue_entry_priv_pci), 2075 .priv_size = sizeof(struct queue_entry_priv_pci),
@@ -1969,7 +2098,7 @@ static const struct rt2x00_ops rt2500pci_ops = {
1969 * RT2500pci module information. 2098 * RT2500pci module information.
1970 */ 2099 */
1971static DEFINE_PCI_DEVICE_TABLE(rt2500pci_device_table) = { 2100static DEFINE_PCI_DEVICE_TABLE(rt2500pci_device_table) = {
1972 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) }, 2101 { PCI_DEVICE(0x1814, 0x0201) },
1973 { 0, } 2102 { 0, }
1974}; 2103};
1975 2104
@@ -1980,10 +2109,16 @@ MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1980MODULE_DEVICE_TABLE(pci, rt2500pci_device_table); 2109MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1981MODULE_LICENSE("GPL"); 2110MODULE_LICENSE("GPL");
1982 2111
2112static int rt2500pci_probe(struct pci_dev *pci_dev,
2113 const struct pci_device_id *id)
2114{
2115 return rt2x00pci_probe(pci_dev, &rt2500pci_ops);
2116}
2117
1983static struct pci_driver rt2500pci_driver = { 2118static struct pci_driver rt2500pci_driver = {
1984 .name = KBUILD_MODNAME, 2119 .name = KBUILD_MODNAME,
1985 .id_table = rt2500pci_device_table, 2120 .id_table = rt2500pci_device_table,
1986 .probe = rt2x00pci_probe, 2121 .probe = rt2500pci_probe,
1987 .remove = __devexit_p(rt2x00pci_remove), 2122 .remove = __devexit_p(rt2x00pci_remove),
1988 .suspend = rt2x00pci_suspend, 2123 .suspend = rt2x00pci_suspend,
1989 .resume = rt2x00pci_resume, 2124 .resume = rt2x00pci_resume,
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-10 13:39:40 -0400