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path: root/drivers/net/wireless/rt2x00/rt2800pci.c
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Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2800pci.c')
-rw-r--r--drivers/net/wireless/rt2x00/rt2800pci.c893
1 files changed, 472 insertions, 421 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c
index 39b3846fa340..cc4a54f571b8 100644
--- a/drivers/net/wireless/rt2x00/rt2800pci.c
+++ b/drivers/net/wireless/rt2x00/rt2800pci.c
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com> 2 Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> 3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> 4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> 5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
@@ -66,7 +66,7 @@ static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
66 return; 66 return;
67 67
68 for (i = 0; i < 200; i++) { 68 for (i = 0; i < 200; i++) {
69 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg); 69 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
70 70
71 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) || 71 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
72 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) || 72 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
@@ -80,30 +80,32 @@ static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
80 if (i == 200) 80 if (i == 200)
81 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n"); 81 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
82 82
83 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0); 83 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
84 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0); 84 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
85} 85}
86 86
87#ifdef CONFIG_RT2800PCI_SOC 87#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
88static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev) 88static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
89{ 89{
90 u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */ 90 void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
91 91
92 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE); 92 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
93
94 iounmap(base_addr);
93} 95}
94#else 96#else
95static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev) 97static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
96{ 98{
97} 99}
98#endif /* CONFIG_RT2800PCI_SOC */ 100#endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
99 101
100#ifdef CONFIG_RT2800PCI_PCI 102#ifdef CONFIG_PCI
101static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom) 103static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
102{ 104{
103 struct rt2x00_dev *rt2x00dev = eeprom->data; 105 struct rt2x00_dev *rt2x00dev = eeprom->data;
104 u32 reg; 106 u32 reg;
105 107
106 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg); 108 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
107 109
108 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN); 110 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
109 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT); 111 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
@@ -125,7 +127,7 @@ static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
125 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT, 127 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
126 !!eeprom->reg_chip_select); 128 !!eeprom->reg_chip_select);
127 129
128 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg); 130 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
129} 131}
130 132
131static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev) 133static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
@@ -133,7 +135,7 @@ static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
133 struct eeprom_93cx6 eeprom; 135 struct eeprom_93cx6 eeprom;
134 u32 reg; 136 u32 reg;
135 137
136 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg); 138 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
137 139
138 eeprom.data = rt2x00dev; 140 eeprom.data = rt2x00dev;
139 eeprom.register_read = rt2800pci_eepromregister_read; 141 eeprom.register_read = rt2800pci_eepromregister_read;
@@ -181,7 +183,101 @@ static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
181static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev) 183static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
182{ 184{
183} 185}
184#endif /* CONFIG_RT2800PCI_PCI */ 186#endif /* CONFIG_PCI */
187
188/*
189 * Queue handlers.
190 */
191static void rt2800pci_start_queue(struct data_queue *queue)
192{
193 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
194 u32 reg;
195
196 switch (queue->qid) {
197 case QID_RX:
198 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
199 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
200 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
201 break;
202 case QID_BEACON:
203 /*
204 * Allow beacon tasklets to be scheduled for periodic
205 * beacon updates.
206 */
207 tasklet_enable(&rt2x00dev->tbtt_tasklet);
208 tasklet_enable(&rt2x00dev->pretbtt_tasklet);
209
210 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
211 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
212 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
213 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
214 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
215
216 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, &reg);
217 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
218 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
219 break;
220 default:
221 break;
222 };
223}
224
225static void rt2800pci_kick_queue(struct data_queue *queue)
226{
227 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
228 struct queue_entry *entry;
229
230 switch (queue->qid) {
231 case QID_AC_VO:
232 case QID_AC_VI:
233 case QID_AC_BE:
234 case QID_AC_BK:
235 entry = rt2x00queue_get_entry(queue, Q_INDEX);
236 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(queue->qid),
237 entry->entry_idx);
238 break;
239 case QID_MGMT:
240 entry = rt2x00queue_get_entry(queue, Q_INDEX);
241 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(5),
242 entry->entry_idx);
243 break;
244 default:
245 break;
246 }
247}
248
249static void rt2800pci_stop_queue(struct data_queue *queue)
250{
251 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
252 u32 reg;
253
254 switch (queue->qid) {
255 case QID_RX:
256 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
257 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
258 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
259 break;
260 case QID_BEACON:
261 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
262 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
263 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
264 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
265 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
266
267 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, &reg);
268 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
269 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
270
271 /*
272 * Wait for tbtt tasklets to finish.
273 */
274 tasklet_disable(&rt2x00dev->tbtt_tasklet);
275 tasklet_disable(&rt2x00dev->pretbtt_tasklet);
276 break;
277 default:
278 break;
279 }
280}
185 281
186/* 282/*
187 * Firmware functions 283 * Firmware functions
@@ -196,26 +292,24 @@ static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
196{ 292{
197 u32 reg; 293 u32 reg;
198 294
199 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
200
201 /* 295 /*
202 * enable Host program ram write selection 296 * enable Host program ram write selection
203 */ 297 */
204 reg = 0; 298 reg = 0;
205 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1); 299 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
206 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg); 300 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
207 301
208 /* 302 /*
209 * Write firmware to device. 303 * Write firmware to device.
210 */ 304 */
211 rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, 305 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
212 data, len); 306 data, len);
213 307
214 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000); 308 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
215 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001); 309 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
216 310
217 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 311 rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
218 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 312 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
219 313
220 return 0; 314 return 0;
221} 315}
@@ -243,6 +337,7 @@ static void rt2800pci_clear_entry(struct queue_entry *entry)
243{ 337{
244 struct queue_entry_priv_pci *entry_priv = entry->priv_data; 338 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
245 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 339 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
340 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
246 u32 word; 341 u32 word;
247 342
248 if (entry->queue->qid == QID_RX) { 343 if (entry->queue->qid == QID_RX) {
@@ -253,6 +348,13 @@ static void rt2800pci_clear_entry(struct queue_entry *entry)
253 rt2x00_desc_read(entry_priv->desc, 1, &word); 348 rt2x00_desc_read(entry_priv->desc, 1, &word);
254 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0); 349 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
255 rt2x00_desc_write(entry_priv->desc, 1, word); 350 rt2x00_desc_write(entry_priv->desc, 1, word);
351
352 /*
353 * Set RX IDX in register to inform hardware that we have
354 * handled this entry and it is available for reuse again.
355 */
356 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
357 entry->entry_idx);
256 } else { 358 } else {
257 rt2x00_desc_read(entry_priv->desc, 1, &word); 359 rt2x00_desc_read(entry_priv->desc, 1, &word);
258 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1); 360 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
@@ -269,45 +371,51 @@ static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
269 * Initialize registers. 371 * Initialize registers.
270 */ 372 */
271 entry_priv = rt2x00dev->tx[0].entries[0].priv_data; 373 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
272 rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma); 374 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
273 rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit); 375 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0,
274 rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0); 376 rt2x00dev->tx[0].limit);
275 rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0); 377 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
378 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
276 379
277 entry_priv = rt2x00dev->tx[1].entries[0].priv_data; 380 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
278 rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma); 381 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
279 rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit); 382 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1,
280 rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0); 383 rt2x00dev->tx[1].limit);
281 rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0); 384 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
385 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
282 386
283 entry_priv = rt2x00dev->tx[2].entries[0].priv_data; 387 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
284 rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma); 388 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
285 rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit); 389 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2,
286 rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0); 390 rt2x00dev->tx[2].limit);
287 rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0); 391 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
392 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
288 393
289 entry_priv = rt2x00dev->tx[3].entries[0].priv_data; 394 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
290 rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma); 395 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
291 rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit); 396 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3,
292 rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0); 397 rt2x00dev->tx[3].limit);
293 rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0); 398 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
399 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
294 400
295 entry_priv = rt2x00dev->rx->entries[0].priv_data; 401 entry_priv = rt2x00dev->rx->entries[0].priv_data;
296 rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma); 402 rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
297 rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit); 403 rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT,
298 rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1); 404 rt2x00dev->rx[0].limit);
299 rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0); 405 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
406 rt2x00dev->rx[0].limit - 1);
407 rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
300 408
301 /* 409 /*
302 * Enable global DMA configuration 410 * Enable global DMA configuration
303 */ 411 */
304 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 412 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
305 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 413 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
306 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 414 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
307 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 415 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
308 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 416 rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
309 417
310 rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0); 418 rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
311 419
312 return 0; 420 return 0;
313} 421}
@@ -315,54 +423,62 @@ static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
315/* 423/*
316 * Device state switch handlers. 424 * Device state switch handlers.
317 */ 425 */
318static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
319 enum dev_state state)
320{
321 u32 reg;
322
323 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
324 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
325 (state == STATE_RADIO_RX_ON) ||
326 (state == STATE_RADIO_RX_ON_LINK));
327 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
328}
329
330static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev, 426static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
331 enum dev_state state) 427 enum dev_state state)
332{ 428{
333 int mask = (state == STATE_RADIO_IRQ_ON) || 429 int mask = (state == STATE_RADIO_IRQ_ON);
334 (state == STATE_RADIO_IRQ_ON_ISR);
335 u32 reg; 430 u32 reg;
431 unsigned long flags;
336 432
337 /* 433 /*
338 * When interrupts are being enabled, the interrupt registers 434 * When interrupts are being enabled, the interrupt registers
339 * should clear the register to assure a clean state. 435 * should clear the register to assure a clean state.
340 */ 436 */
341 if (state == STATE_RADIO_IRQ_ON) { 437 if (state == STATE_RADIO_IRQ_ON) {
342 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg); 438 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
343 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg); 439 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
440
441 /*
442 * Enable tasklets. The beacon related tasklets are
443 * enabled when the beacon queue is started.
444 */
445 tasklet_enable(&rt2x00dev->txstatus_tasklet);
446 tasklet_enable(&rt2x00dev->rxdone_tasklet);
447 tasklet_enable(&rt2x00dev->autowake_tasklet);
344 } 448 }
345 449
346 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg); 450 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
347 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask); 451 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
348 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask); 452 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, 0);
453 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, 0);
349 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask); 454 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
350 rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask); 455 rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, 0);
351 rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask); 456 rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, 0);
352 rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask); 457 rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, 0);
353 rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask); 458 rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, 0);
354 rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask); 459 rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, 0);
355 rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask); 460 rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, 0);
356 rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask); 461 rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, 0);
357 rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask); 462 rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, 0);
358 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask); 463 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
359 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask); 464 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
360 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask); 465 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
361 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask); 466 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
362 rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask); 467 rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, 0);
363 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask); 468 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, 0);
364 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask); 469 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, 0);
365 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg); 470 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
471 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
472
473 if (state == STATE_RADIO_IRQ_OFF) {
474 /*
475 * Ensure that all tasklets are finished before
476 * disabling the interrupts.
477 */
478 tasklet_disable(&rt2x00dev->txstatus_tasklet);
479 tasklet_disable(&rt2x00dev->rxdone_tasklet);
480 tasklet_disable(&rt2x00dev->autowake_tasklet);
481 }
366} 482}
367 483
368static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev) 484static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
@@ -372,7 +488,7 @@ static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
372 /* 488 /*
373 * Reset DMA indexes 489 * Reset DMA indexes
374 */ 490 */
375 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg); 491 rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
376 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1); 492 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
377 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1); 493 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
378 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1); 494 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
@@ -380,130 +496,60 @@ static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
380 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1); 496 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
381 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1); 497 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
382 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1); 498 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
383 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg); 499 rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
384 500
385 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f); 501 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
386 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00); 502 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
387 503
388 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 504 if (rt2x00_rt(rt2x00dev, RT5390)) {
505 rt2x00pci_register_read(rt2x00dev, AUX_CTRL, &reg);
506 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
507 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
508 rt2x00pci_register_write(rt2x00dev, AUX_CTRL, reg);
509 }
389 510
390 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 511 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
512
513 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
391 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1); 514 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
392 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1); 515 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
393 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 516 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
394 517
395 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); 518 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
396 519
397 return 0; 520 return 0;
398} 521}
399 522
400static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev) 523static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
401{ 524{
402 u32 reg;
403 u16 word;
404
405 /*
406 * Initialize all registers.
407 */
408 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) || 525 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
409 rt2800pci_init_queues(rt2x00dev) || 526 rt2800pci_init_queues(rt2x00dev)))
410 rt2800_init_registers(rt2x00dev) ||
411 rt2800_wait_wpdma_ready(rt2x00dev) ||
412 rt2800_init_bbp(rt2x00dev) ||
413 rt2800_init_rfcsr(rt2x00dev)))
414 return -EIO; 527 return -EIO;
415 528
416 /* 529 return rt2800_enable_radio(rt2x00dev);
417 * Send signal to firmware during boot time.
418 */
419 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
420
421 /*
422 * Enable RX.
423 */
424 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
425 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
426 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
427 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
428
429 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
430 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
431 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
432 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
433 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
434 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
435
436 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
437 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
438 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
439 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
440
441 /*
442 * Initialize LED control
443 */
444 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
445 rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
446 word & 0xff, (word >> 8) & 0xff);
447
448 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
449 rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
450 word & 0xff, (word >> 8) & 0xff);
451
452 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
453 rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
454 word & 0xff, (word >> 8) & 0xff);
455
456 return 0;
457} 530}
458 531
459static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev) 532static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
460{ 533{
461 u32 reg; 534 if (rt2x00_is_soc(rt2x00dev)) {
462 535 rt2800_disable_radio(rt2x00dev);
463 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 536 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
464 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 537 rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
465 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 538 }
466 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
467 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
468 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
469 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
470
471 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
472 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
473 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
474
475 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
476
477 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
478 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
479 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
480 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
481 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
482 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
483 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
484 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
485 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
486
487 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
488 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
489
490 /* Wait for DMA, ignore error */
491 rt2800_wait_wpdma_ready(rt2x00dev);
492} 539}
493 540
494static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev, 541static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
495 enum dev_state state) 542 enum dev_state state)
496{ 543{
497 /*
498 * Always put the device to sleep (even when we intend to wakeup!)
499 * if the device is booting and wasn't asleep it will return
500 * failure when attempting to wakeup.
501 */
502 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
503
504 if (state == STATE_AWAKE) { 544 if (state == STATE_AWAKE) {
505 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0); 545 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0x02);
506 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP); 546 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
547 } else if (state == STATE_SLEEP) {
548 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
549 0xffffffff);
550 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID,
551 0xffffffff);
552 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0x01, 0xff, 0x01);
507 } 553 }
508 554
509 return 0; 555 return 0;
@@ -533,16 +579,8 @@ static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
533 rt2800pci_disable_radio(rt2x00dev); 579 rt2800pci_disable_radio(rt2x00dev);
534 rt2800pci_set_state(rt2x00dev, STATE_SLEEP); 580 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
535 break; 581 break;
536 case STATE_RADIO_RX_ON:
537 case STATE_RADIO_RX_ON_LINK:
538 case STATE_RADIO_RX_OFF:
539 case STATE_RADIO_RX_OFF_LINK:
540 rt2800pci_toggle_rx(rt2x00dev, state);
541 break;
542 case STATE_RADIO_IRQ_ON: 582 case STATE_RADIO_IRQ_ON:
543 case STATE_RADIO_IRQ_ON_ISR:
544 case STATE_RADIO_IRQ_OFF: 583 case STATE_RADIO_IRQ_OFF:
545 case STATE_RADIO_IRQ_OFF_ISR:
546 rt2800pci_toggle_irq(rt2x00dev, state); 584 rt2800pci_toggle_irq(rt2x00dev, state);
547 break; 585 break;
548 case STATE_DEEP_SLEEP: 586 case STATE_DEEP_SLEEP:
@@ -566,21 +604,16 @@ static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
566/* 604/*
567 * TX descriptor initialization 605 * TX descriptor initialization
568 */ 606 */
569static void rt2800pci_write_tx_data(struct queue_entry* entry, 607static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
570 struct txentry_desc *txdesc)
571{ 608{
572 __le32 *txwi = (__le32 *) entry->skb->data; 609 return (__le32 *) entry->skb->data;
573
574 rt2800_write_txwi(txwi, txdesc);
575} 610}
576 611
577 612static void rt2800pci_write_tx_desc(struct queue_entry *entry,
578static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
579 struct sk_buff *skb,
580 struct txentry_desc *txdesc) 613 struct txentry_desc *txdesc)
581{ 614{
582 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 615 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
583 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data; 616 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
584 __le32 *txd = entry_priv->desc; 617 __le32 *txd = entry_priv->desc;
585 u32 word; 618 u32 word;
586 619
@@ -600,7 +633,7 @@ static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
600 rt2x00_desc_write(txd, 0, word); 633 rt2x00_desc_write(txd, 0, word);
601 634
602 rt2x00_desc_read(txd, 1, &word); 635 rt2x00_desc_read(txd, 1, &word);
603 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len); 636 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
604 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1, 637 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
605 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); 638 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
606 rt2x00_set_field32(&word, TXD_W1_BURST, 639 rt2x00_set_field32(&word, TXD_W1_BURST,
@@ -629,53 +662,11 @@ static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
629} 662}
630 663
631/* 664/*
632 * TX data initialization
633 */
634static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
635 const enum data_queue_qid queue_idx)
636{
637 struct data_queue *queue;
638 unsigned int idx, qidx = 0;
639
640 if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
641 return;
642
643 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
644 idx = queue->index[Q_INDEX];
645
646 if (queue_idx == QID_MGMT)
647 qidx = 5;
648 else
649 qidx = queue_idx;
650
651 rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
652}
653
654static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
655 const enum data_queue_qid qid)
656{
657 u32 reg;
658
659 if (qid == QID_BEACON) {
660 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
661 return;
662 }
663
664 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
665 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
666 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
667 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
668 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
669 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
670}
671
672/*
673 * RX control handlers 665 * RX control handlers
674 */ 666 */
675static void rt2800pci_fill_rxdone(struct queue_entry *entry, 667static void rt2800pci_fill_rxdone(struct queue_entry *entry,
676 struct rxdone_entry_desc *rxdesc) 668 struct rxdone_entry_desc *rxdesc)
677{ 669{
678 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
679 struct queue_entry_priv_pci *entry_priv = entry->priv_data; 670 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
680 __le32 *rxd = entry_priv->desc; 671 __le32 *rxd = entry_priv->desc;
681 u32 word; 672 u32 word;
@@ -701,6 +692,12 @@ static void rt2800pci_fill_rxdone(struct queue_entry *entry,
701 */ 692 */
702 rxdesc->flags |= RX_FLAG_IV_STRIPPED; 693 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
703 694
695 /*
696 * The hardware has already checked the Michael Mic and has
697 * stripped it from the frame. Signal this to mac80211.
698 */
699 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
700
704 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS) 701 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
705 rxdesc->flags |= RX_FLAG_DECRYPTED; 702 rxdesc->flags |= RX_FLAG_DECRYPTED;
706 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC) 703 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
@@ -717,179 +714,177 @@ static void rt2800pci_fill_rxdone(struct queue_entry *entry,
717 * Process the RXWI structure that is at the start of the buffer. 714 * Process the RXWI structure that is at the start of the buffer.
718 */ 715 */
719 rt2800_process_rxwi(entry, rxdesc); 716 rt2800_process_rxwi(entry, rxdesc);
720
721 /*
722 * Set RX IDX in register to inform hardware that we have handled
723 * this entry and it is available for reuse again.
724 */
725 rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
726} 717}
727 718
728/* 719/*
729 * Interrupt functions. 720 * Interrupt functions.
730 */ 721 */
731static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev) 722static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
723{
724 struct ieee80211_conf conf = { .flags = 0 };
725 struct rt2x00lib_conf libconf = { .conf = &conf };
726
727 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
728}
729
730static bool rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
732{ 731{
733 struct data_queue *queue; 732 struct data_queue *queue;
734 struct queue_entry *entry; 733 struct queue_entry *entry;
735 __le32 *txwi; 734 u32 status;
736 struct txdone_entry_desc txdesc; 735 u8 qid;
737 u32 word; 736 int max_tx_done = 16;
738 u32 reg;
739 int wcid, ack, pid, tx_wcid, tx_ack, tx_pid;
740 u16 mcs, real_mcs;
741 int i;
742 737
743 /* 738 while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
744 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO 739 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
745 * at most X times and also stop processing once the TX_STA_FIFO_VALID 740 if (unlikely(qid >= QID_RX)) {
746 * flag is not set anymore. 741 /*
747 * 742 * Unknown queue, this shouldn't happen. Just drop
748 * The legacy drivers use X=TX_RING_SIZE but state in a comment 743 * this tx status.
749 * that the TX_STA_FIFO stack has a size of 16. We stick to our 744 */
750 * tx ring size for now. 745 WARNING(rt2x00dev, "Got TX status report with "
751 */ 746 "unexpected pid %u, dropping\n", qid);
752 for (i = 0; i < TX_ENTRIES; i++) {
753 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
754 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
755 break; 747 break;
748 }
756 749
757 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID); 750 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
758 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED); 751 if (unlikely(queue == NULL)) {
759 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
760
761 /*
762 * Skip this entry when it contains an invalid
763 * queue identication number.
764 */
765 if (pid <= 0 || pid > QID_RX)
766 continue;
767
768 queue = rt2x00queue_get_queue(rt2x00dev, pid - 1);
769 if (unlikely(!queue))
770 continue;
771
772 /*
773 * Inside each queue, we process each entry in a chronological
774 * order. We first check that the queue is not empty.
775 */
776 if (rt2x00queue_empty(queue))
777 continue;
778 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
779
780 /* Check if we got a match by looking at WCID/ACK/PID
781 * fields */
782 txwi = (__le32 *) entry->skb->data;
783
784 rt2x00_desc_read(txwi, 1, &word);
785 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
786 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK);
787 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID);
788
789 if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid))
790 WARNING(rt2x00dev, "invalid TX_STA_FIFO content\n");
791
792 /*
793 * Obtain the status about this packet.
794 */
795 txdesc.flags = 0;
796 rt2x00_desc_read(txwi, 0, &word);
797 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
798 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
799
800 /*
801 * Ralink has a retry mechanism using a global fallback
802 * table. We setup this fallback table to try the immediate
803 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
804 * always contains the MCS used for the last transmission, be
805 * it successful or not.
806 */
807 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS)) {
808 /* 752 /*
809 * Transmission succeeded. The number of retries is 753 * The queue is NULL, this shouldn't happen. Stop
810 * mcs - real_mcs 754 * processing here and drop the tx status
811 */ 755 */
812 __set_bit(TXDONE_SUCCESS, &txdesc.flags); 756 WARNING(rt2x00dev, "Got TX status for an unavailable "
813 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0); 757 "queue %u, dropping\n", qid);
814 } else { 758 break;
759 }
760
761 if (unlikely(rt2x00queue_empty(queue))) {
815 /* 762 /*
816 * Transmission failed. The number of retries is 763 * The queue is empty. Stop processing here
817 * always 7 in this case (for a total number of 8 764 * and drop the tx status.
818 * frames sent).
819 */ 765 */
820 __set_bit(TXDONE_FAILURE, &txdesc.flags); 766 WARNING(rt2x00dev, "Got TX status for an empty "
821 txdesc.retry = 7; 767 "queue %u, dropping\n", qid);
768 break;
822 } 769 }
823 770
824 /* 771 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
825 * the frame was retried at least once 772 rt2800_txdone_entry(entry, status);
826 * -> hw used fallback rates
827 */
828 if (txdesc.retry)
829 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
830 773
831 rt2x00lib_txdone(entry, &txdesc); 774 if (--max_tx_done == 0)
775 break;
832 } 776 }
777
778 return !max_tx_done;
833} 779}
834 780
835static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev) 781static inline void rt2800pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
782 struct rt2x00_field32 irq_field)
836{ 783{
837 struct ieee80211_conf conf = { .flags = 0 }; 784 u32 reg;
838 struct rt2x00lib_conf libconf = { .conf = &conf };
839 785
840 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS); 786 /*
787 * Enable a single interrupt. The interrupt mask register
788 * access needs locking.
789 */
790 spin_lock_irq(&rt2x00dev->irqmask_lock);
791 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
792 rt2x00_set_field32(&reg, irq_field, 1);
793 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
794 spin_unlock_irq(&rt2x00dev->irqmask_lock);
841} 795}
842 796
843static irqreturn_t rt2800pci_interrupt_thread(int irq, void *dev_instance) 797static void rt2800pci_txstatus_tasklet(unsigned long data)
844{ 798{
845 struct rt2x00_dev *rt2x00dev = dev_instance; 799 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
846 u32 reg = rt2x00dev->irqvalue[0]; 800 if (rt2800pci_txdone(rt2x00dev))
801 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
847 802
848 /* 803 /*
849 * 1 - Pre TBTT interrupt. 804 * No need to enable the tx status interrupt here as we always
805 * leave it enabled to minimize the possibility of a tx status
806 * register overflow. See comment in interrupt handler.
850 */ 807 */
851 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT)) 808}
852 rt2x00lib_pretbtt(rt2x00dev);
853 809
854 /* 810static void rt2800pci_pretbtt_tasklet(unsigned long data)
855 * 2 - Beacondone interrupt. 811{
856 */ 812 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
857 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT)) 813 rt2x00lib_pretbtt(rt2x00dev);
858 rt2x00lib_beacondone(rt2x00dev); 814 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_PRE_TBTT);
815}
859 816
860 /* 817static void rt2800pci_tbtt_tasklet(unsigned long data)
861 * 3 - Rx ring done interrupt. 818{
862 */ 819 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
863 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE)) 820 rt2x00lib_beacondone(rt2x00dev);
864 rt2x00pci_rxdone(rt2x00dev); 821 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TBTT);
822}
865 823
866 /* 824static void rt2800pci_rxdone_tasklet(unsigned long data)
867 * 4 - Tx done interrupt. 825{
868 */ 826 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
869 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) 827 if (rt2x00pci_rxdone(rt2x00dev))
870 rt2800pci_txdone(rt2x00dev); 828 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
829 else
830 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
831}
832
833static void rt2800pci_autowake_tasklet(unsigned long data)
834{
835 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
836 rt2800pci_wakeup(rt2x00dev);
837 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_AUTO_WAKEUP);
838}
839
840static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
841{
842 u32 status;
843 int i;
871 844
872 /* 845 /*
873 * 5 - Auto wakeup interrupt. 846 * The TX_FIFO_STATUS interrupt needs special care. We should
847 * read TX_STA_FIFO but we should do it immediately as otherwise
848 * the register can overflow and we would lose status reports.
849 *
850 * Hence, read the TX_STA_FIFO register and copy all tx status
851 * reports into a kernel FIFO which is handled in the txstatus
852 * tasklet. We use a tasklet to process the tx status reports
853 * because we can schedule the tasklet multiple times (when the
854 * interrupt fires again during tx status processing).
855 *
856 * Furthermore we don't disable the TX_FIFO_STATUS
857 * interrupt here but leave it enabled so that the TX_STA_FIFO
858 * can also be read while the tx status tasklet gets executed.
859 *
860 * Since we have only one producer and one consumer we don't
861 * need to lock the kfifo.
874 */ 862 */
875 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP)) 863 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
876 rt2800pci_wakeup(rt2x00dev); 864 rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &status);
877 865
878 /* Enable interrupts again. */ 866 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
879 rt2x00dev->ops->lib->set_device_state(rt2x00dev, 867 break;
880 STATE_RADIO_IRQ_ON_ISR);
881 868
882 return IRQ_HANDLED; 869 if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
870 WARNING(rt2x00dev, "TX status FIFO overrun,"
871 "drop tx status report.\n");
872 break;
873 }
874 }
875
876 /* Schedule the tasklet for processing the tx status. */
877 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
883} 878}
884 879
885static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance) 880static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
886{ 881{
887 struct rt2x00_dev *rt2x00dev = dev_instance; 882 struct rt2x00_dev *rt2x00dev = dev_instance;
888 u32 reg; 883 u32 reg, mask;
889 884
890 /* Read status and ACK all interrupts */ 885 /* Read status and ACK all interrupts */
891 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg); 886 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
892 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg); 887 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
893 888
894 if (!reg) 889 if (!reg)
895 return IRQ_NONE; 890 return IRQ_NONE;
@@ -897,15 +892,44 @@ static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
897 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 892 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
898 return IRQ_HANDLED; 893 return IRQ_HANDLED;
899 894
900 /* Store irqvalue for use in the interrupt thread. */ 895 /*
901 rt2x00dev->irqvalue[0] = reg; 896 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
897 * for interrupts and interrupt masks we can just use the value of
898 * INT_SOURCE_CSR to create the interrupt mask.
899 */
900 mask = ~reg;
902 901
903 /* Disable interrupts, will be enabled again in the interrupt thread. */ 902 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {
904 rt2x00dev->ops->lib->set_device_state(rt2x00dev, 903 rt2800pci_txstatus_interrupt(rt2x00dev);
905 STATE_RADIO_IRQ_OFF_ISR); 904 /*
905 * Never disable the TX_FIFO_STATUS interrupt.
906 */
907 rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
908 }
906 909
910 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
911 tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);
907 912
908 return IRQ_WAKE_THREAD; 913 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
914 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
915
916 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
917 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
918
919 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
920 tasklet_schedule(&rt2x00dev->autowake_tasklet);
921
922 /*
923 * Disable all interrupts for which a tasklet was scheduled right now,
924 * the tasklet will reenable the appropriate interrupts.
925 */
926 spin_lock(&rt2x00dev->irqmask_lock);
927 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
928 reg &= mask;
929 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
930 spin_unlock(&rt2x00dev->irqmask_lock);
931
932 return IRQ_HANDLED;
909} 933}
910 934
911/* 935/*
@@ -952,25 +976,28 @@ static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
952 * This device has multiple filters for control frames 976 * This device has multiple filters for control frames
953 * and has a separate filter for PS Poll frames. 977 * and has a separate filter for PS Poll frames.
954 */ 978 */
955 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags); 979 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
956 __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags); 980 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
957 981
958 /* 982 /*
959 * This device has a pre tbtt interrupt and thus fetches 983 * This device has a pre tbtt interrupt and thus fetches
960 * a new beacon directly prior to transmission. 984 * a new beacon directly prior to transmission.
961 */ 985 */
962 __set_bit(DRIVER_SUPPORT_PRE_TBTT_INTERRUPT, &rt2x00dev->flags); 986 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
963 987
964 /* 988 /*
965 * This device requires firmware. 989 * This device requires firmware.
966 */ 990 */
967 if (!rt2x00_is_soc(rt2x00dev)) 991 if (!rt2x00_is_soc(rt2x00dev))
968 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags); 992 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
969 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags); 993 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
970 __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags); 994 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
995 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
996 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
971 if (!modparam_nohwcrypt) 997 if (!modparam_nohwcrypt)
972 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags); 998 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
973 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags); 999 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
1000 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
974 1001
975 /* 1002 /*
976 * Set the rssi offset. 1003 * Set the rssi offset.
@@ -999,6 +1026,9 @@ static const struct ieee80211_ops rt2800pci_mac80211_ops = {
999 .get_tsf = rt2800_get_tsf, 1026 .get_tsf = rt2800_get_tsf,
1000 .rfkill_poll = rt2x00mac_rfkill_poll, 1027 .rfkill_poll = rt2x00mac_rfkill_poll,
1001 .ampdu_action = rt2800_ampdu_action, 1028 .ampdu_action = rt2800_ampdu_action,
1029 .flush = rt2x00mac_flush,
1030 .get_survey = rt2800_get_survey,
1031 .get_ringparam = rt2x00mac_get_ringparam,
1002}; 1032};
1003 1033
1004static const struct rt2800_ops rt2800pci_rt2800_ops = { 1034static const struct rt2800_ops rt2800pci_rt2800_ops = {
@@ -1011,11 +1041,16 @@ static const struct rt2800_ops rt2800pci_rt2800_ops = {
1011 .regbusy_read = rt2x00pci_regbusy_read, 1041 .regbusy_read = rt2x00pci_regbusy_read,
1012 .drv_write_firmware = rt2800pci_write_firmware, 1042 .drv_write_firmware = rt2800pci_write_firmware,
1013 .drv_init_registers = rt2800pci_init_registers, 1043 .drv_init_registers = rt2800pci_init_registers,
1044 .drv_get_txwi = rt2800pci_get_txwi,
1014}; 1045};
1015 1046
1016static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = { 1047static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1017 .irq_handler = rt2800pci_interrupt, 1048 .irq_handler = rt2800pci_interrupt,
1018 .irq_handler_thread = rt2800pci_interrupt_thread, 1049 .txstatus_tasklet = rt2800pci_txstatus_tasklet,
1050 .pretbtt_tasklet = rt2800pci_pretbtt_tasklet,
1051 .tbtt_tasklet = rt2800pci_tbtt_tasklet,
1052 .rxdone_tasklet = rt2800pci_rxdone_tasklet,
1053 .autowake_tasklet = rt2800pci_autowake_tasklet,
1019 .probe_hw = rt2800pci_probe_hw, 1054 .probe_hw = rt2800pci_probe_hw,
1020 .get_firmware_name = rt2800pci_get_firmware_name, 1055 .get_firmware_name = rt2800pci_get_firmware_name,
1021 .check_firmware = rt2800_check_firmware, 1056 .check_firmware = rt2800_check_firmware,
@@ -1029,11 +1064,15 @@ static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1029 .link_stats = rt2800_link_stats, 1064 .link_stats = rt2800_link_stats,
1030 .reset_tuner = rt2800_reset_tuner, 1065 .reset_tuner = rt2800_reset_tuner,
1031 .link_tuner = rt2800_link_tuner, 1066 .link_tuner = rt2800_link_tuner,
1067 .gain_calibration = rt2800_gain_calibration,
1068 .start_queue = rt2800pci_start_queue,
1069 .kick_queue = rt2800pci_kick_queue,
1070 .stop_queue = rt2800pci_stop_queue,
1071 .flush_queue = rt2x00pci_flush_queue,
1032 .write_tx_desc = rt2800pci_write_tx_desc, 1072 .write_tx_desc = rt2800pci_write_tx_desc,
1033 .write_tx_data = rt2800pci_write_tx_data, 1073 .write_tx_data = rt2800_write_tx_data,
1034 .write_beacon = rt2800_write_beacon, 1074 .write_beacon = rt2800_write_beacon,
1035 .kick_tx_queue = rt2800pci_kick_tx_queue, 1075 .clear_beacon = rt2800_clear_beacon,
1036 .kill_tx_queue = rt2800pci_kill_tx_queue,
1037 .fill_rxdone = rt2800pci_fill_rxdone, 1076 .fill_rxdone = rt2800pci_fill_rxdone,
1038 .config_shared_key = rt2800_config_shared_key, 1077 .config_shared_key = rt2800_config_shared_key,
1039 .config_pairwise_key = rt2800_config_pairwise_key, 1078 .config_pairwise_key = rt2800_config_pairwise_key,
@@ -1045,21 +1084,21 @@ static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1045}; 1084};
1046 1085
1047static const struct data_queue_desc rt2800pci_queue_rx = { 1086static const struct data_queue_desc rt2800pci_queue_rx = {
1048 .entry_num = RX_ENTRIES, 1087 .entry_num = 128,
1049 .data_size = AGGREGATION_SIZE, 1088 .data_size = AGGREGATION_SIZE,
1050 .desc_size = RXD_DESC_SIZE, 1089 .desc_size = RXD_DESC_SIZE,
1051 .priv_size = sizeof(struct queue_entry_priv_pci), 1090 .priv_size = sizeof(struct queue_entry_priv_pci),
1052}; 1091};
1053 1092
1054static const struct data_queue_desc rt2800pci_queue_tx = { 1093static const struct data_queue_desc rt2800pci_queue_tx = {
1055 .entry_num = TX_ENTRIES, 1094 .entry_num = 64,
1056 .data_size = AGGREGATION_SIZE, 1095 .data_size = AGGREGATION_SIZE,
1057 .desc_size = TXD_DESC_SIZE, 1096 .desc_size = TXD_DESC_SIZE,
1058 .priv_size = sizeof(struct queue_entry_priv_pci), 1097 .priv_size = sizeof(struct queue_entry_priv_pci),
1059}; 1098};
1060 1099
1061static const struct data_queue_desc rt2800pci_queue_bcn = { 1100static const struct data_queue_desc rt2800pci_queue_bcn = {
1062 .entry_num = 8 * BEACON_ENTRIES, 1101 .entry_num = 8,
1063 .data_size = 0, /* No DMA required for beacons */ 1102 .data_size = 0, /* No DMA required for beacons */
1064 .desc_size = TXWI_DESC_SIZE, 1103 .desc_size = TXWI_DESC_SIZE,
1065 .priv_size = sizeof(struct queue_entry_priv_pci), 1104 .priv_size = sizeof(struct queue_entry_priv_pci),
@@ -1087,48 +1126,54 @@ static const struct rt2x00_ops rt2800pci_ops = {
1087/* 1126/*
1088 * RT2800pci module information. 1127 * RT2800pci module information.
1089 */ 1128 */
1090#ifdef CONFIG_RT2800PCI_PCI 1129#ifdef CONFIG_PCI
1091static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = { 1130static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1092 { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1131 { PCI_DEVICE(0x1814, 0x0601) },
1093 { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1132 { PCI_DEVICE(0x1814, 0x0681) },
1094 { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1133 { PCI_DEVICE(0x1814, 0x0701) },
1095 { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1134 { PCI_DEVICE(0x1814, 0x0781) },
1096 { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1135 { PCI_DEVICE(0x1814, 0x3090) },
1097 { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1136 { PCI_DEVICE(0x1814, 0x3091) },
1098 { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1137 { PCI_DEVICE(0x1814, 0x3092) },
1099 { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1138 { PCI_DEVICE(0x1432, 0x7708) },
1100 { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1139 { PCI_DEVICE(0x1432, 0x7727) },
1101 { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1140 { PCI_DEVICE(0x1432, 0x7728) },
1102 { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1141 { PCI_DEVICE(0x1432, 0x7738) },
1103 { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1142 { PCI_DEVICE(0x1432, 0x7748) },
1104#ifdef CONFIG_RT2800PCI_RT30XX 1143 { PCI_DEVICE(0x1432, 0x7758) },
1105 { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1144 { PCI_DEVICE(0x1432, 0x7768) },
1106 { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1145 { PCI_DEVICE(0x1462, 0x891a) },
1107 { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1146 { PCI_DEVICE(0x1a3b, 0x1059) },
1108 { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1147#ifdef CONFIG_RT2800PCI_RT33XX
1148 { PCI_DEVICE(0x1814, 0x3390) },
1109#endif 1149#endif
1110#ifdef CONFIG_RT2800PCI_RT35XX 1150#ifdef CONFIG_RT2800PCI_RT35XX
1111 { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1151 { PCI_DEVICE(0x1432, 0x7711) },
1112 { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1152 { PCI_DEVICE(0x1432, 0x7722) },
1113 { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1153 { PCI_DEVICE(0x1814, 0x3060) },
1114 { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1154 { PCI_DEVICE(0x1814, 0x3062) },
1115 { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1155 { PCI_DEVICE(0x1814, 0x3562) },
1156 { PCI_DEVICE(0x1814, 0x3592) },
1157 { PCI_DEVICE(0x1814, 0x3593) },
1158#endif
1159#ifdef CONFIG_RT2800PCI_RT53XX
1160 { PCI_DEVICE(0x1814, 0x5390) },
1116#endif 1161#endif
1117 { 0, } 1162 { 0, }
1118}; 1163};
1119#endif /* CONFIG_RT2800PCI_PCI */ 1164#endif /* CONFIG_PCI */
1120 1165
1121MODULE_AUTHOR(DRV_PROJECT); 1166MODULE_AUTHOR(DRV_PROJECT);
1122MODULE_VERSION(DRV_VERSION); 1167MODULE_VERSION(DRV_VERSION);
1123MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver."); 1168MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1124MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards"); 1169MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1125#ifdef CONFIG_RT2800PCI_PCI 1170#ifdef CONFIG_PCI
1126MODULE_FIRMWARE(FIRMWARE_RT2860); 1171MODULE_FIRMWARE(FIRMWARE_RT2860);
1127MODULE_DEVICE_TABLE(pci, rt2800pci_device_table); 1172MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1128#endif /* CONFIG_RT2800PCI_PCI */ 1173#endif /* CONFIG_PCI */
1129MODULE_LICENSE("GPL"); 1174MODULE_LICENSE("GPL");
1130 1175
1131#ifdef CONFIG_RT2800PCI_SOC 1176#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1132static int rt2800soc_probe(struct platform_device *pdev) 1177static int rt2800soc_probe(struct platform_device *pdev)
1133{ 1178{
1134 return rt2x00soc_probe(pdev, &rt2800pci_ops); 1179 return rt2x00soc_probe(pdev, &rt2800pci_ops);
@@ -1145,32 +1190,38 @@ static struct platform_driver rt2800soc_driver = {
1145 .suspend = rt2x00soc_suspend, 1190 .suspend = rt2x00soc_suspend,
1146 .resume = rt2x00soc_resume, 1191 .resume = rt2x00soc_resume,
1147}; 1192};
1148#endif /* CONFIG_RT2800PCI_SOC */ 1193#endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
1194
1195#ifdef CONFIG_PCI
1196static int rt2800pci_probe(struct pci_dev *pci_dev,
1197 const struct pci_device_id *id)
1198{
1199 return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
1200}
1149 1201
1150#ifdef CONFIG_RT2800PCI_PCI
1151static struct pci_driver rt2800pci_driver = { 1202static struct pci_driver rt2800pci_driver = {
1152 .name = KBUILD_MODNAME, 1203 .name = KBUILD_MODNAME,
1153 .id_table = rt2800pci_device_table, 1204 .id_table = rt2800pci_device_table,
1154 .probe = rt2x00pci_probe, 1205 .probe = rt2800pci_probe,
1155 .remove = __devexit_p(rt2x00pci_remove), 1206 .remove = __devexit_p(rt2x00pci_remove),
1156 .suspend = rt2x00pci_suspend, 1207 .suspend = rt2x00pci_suspend,
1157 .resume = rt2x00pci_resume, 1208 .resume = rt2x00pci_resume,
1158}; 1209};
1159#endif /* CONFIG_RT2800PCI_PCI */ 1210#endif /* CONFIG_PCI */
1160 1211
1161static int __init rt2800pci_init(void) 1212static int __init rt2800pci_init(void)
1162{ 1213{
1163 int ret = 0; 1214 int ret = 0;
1164 1215
1165#ifdef CONFIG_RT2800PCI_SOC 1216#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1166 ret = platform_driver_register(&rt2800soc_driver); 1217 ret = platform_driver_register(&rt2800soc_driver);
1167 if (ret) 1218 if (ret)
1168 return ret; 1219 return ret;
1169#endif 1220#endif
1170#ifdef CONFIG_RT2800PCI_PCI 1221#ifdef CONFIG_PCI
1171 ret = pci_register_driver(&rt2800pci_driver); 1222 ret = pci_register_driver(&rt2800pci_driver);
1172 if (ret) { 1223 if (ret) {
1173#ifdef CONFIG_RT2800PCI_SOC 1224#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1174 platform_driver_unregister(&rt2800soc_driver); 1225 platform_driver_unregister(&rt2800soc_driver);
1175#endif 1226#endif
1176 return ret; 1227 return ret;
@@ -1182,10 +1233,10 @@ static int __init rt2800pci_init(void)
1182 1233
1183static void __exit rt2800pci_exit(void) 1234static void __exit rt2800pci_exit(void)
1184{ 1235{
1185#ifdef CONFIG_RT2800PCI_PCI 1236#ifdef CONFIG_PCI
1186 pci_unregister_driver(&rt2800pci_driver); 1237 pci_unregister_driver(&rt2800pci_driver);
1187#endif 1238#endif
1188#ifdef CONFIG_RT2800PCI_SOC 1239#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1189 platform_driver_unregister(&rt2800soc_driver); 1240 platform_driver_unregister(&rt2800soc_driver);
1190#endif 1241#endif
1191} 1242}
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-10 13:39:18 -0400