1 files changed, 474 insertions, 94 deletions

diff --git a/drivers/net/wireless/rt2x00/rt2800.h b/drivers/net/wireless/rt2x00/rt2800.h
index ed4ebcdde7c9..f67bc9b31b28 100644
--- a/drivers/net/wireless/rt2x00/rt2800.h
+++ b/drivers/net/wireless/rt2x00/rt2800.h
@@ -1,5 +1,6 @@
 /*
-        Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
+        Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
+        Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
         Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
         Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
         Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
@@ -45,7 +46,13 @@
  * RF2020 2.4G B/G
  * RF3021 2.4G 1T2R
  * RF3022 2.4G 2T2R
- * RF3052 2.4G 2T2R
+ * RF3052 2.4G/5G 2T2R
+ * RF2853 2.4G/5G 3T3R
+ * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390)
+ * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392)
+ * RF3853 2.4G/5G 3T3R(RT3883/RT3563/RT3573/RT3593/RT3662)
+ * RF5370 2.4G 1T1R
+ * RF5390 2.4G 1T1R
  */
 #define RF2820                          0x0001
 #define RF2850                          0x0002
@@ -56,7 +63,12 @@
 #define RF3021                          0x0007
 #define RF3022                          0x0008
 #define RF3052                          0x0009
+#define RF2853                          0x000a
 #define RF3320                          0x000b
+#define RF3322                          0x000c
+#define RF3853                          0x000d
+#define RF5370                          0x5370
+#define RF5390                          0x5390
 
 /*
  * Chipset revisions.
@@ -69,6 +81,7 @@
 #define REV_RT3071E                     0x0211
 #define REV_RT3090E                     0x0211
 #define REV_RT3390E                     0x0211
+#define REV_RT5390F                     0x0502
 
 /*
  * Signal information.
@@ -113,6 +126,13 @@
 #define E2PROM_CSR_RELOAD               FIELD32(0x00000080)
 
 /*
+ * AUX_CTRL: Aux/PCI-E related configuration
+ */
+#define AUX_CTRL                        0x10c
+#define AUX_CTRL_WAKE_PCIE_EN           FIELD32(0x00000002)
+#define AUX_CTRL_FORCE_PCIE_CLK         FIELD32(0x00000400)
+
+/*
  * OPT_14: Unknown register used by rt3xxx devices.
  */
 #define OPT_14_CSR                      0x0114
@@ -205,10 +225,10 @@
 
 /*
  * WMM_AIFSN_CFG: Aifsn for each EDCA AC
- * AIFSN0: AC_BE
- * AIFSN1: AC_BK
- * AIFSN2: AC_VI
- * AIFSN3: AC_VO
+ * AIFSN0: AC_VO
+ * AIFSN1: AC_VI
+ * AIFSN2: AC_BE
+ * AIFSN3: AC_BK
  */
 #define WMM_AIFSN_CFG                   0x0214
 #define WMM_AIFSN_CFG_AIFSN0            FIELD32(0x0000000f)
@@ -218,10 +238,10 @@
 
 /*
  * WMM_CWMIN_CSR: CWmin for each EDCA AC
- * CWMIN0: AC_BE
- * CWMIN1: AC_BK
- * CWMIN2: AC_VI
- * CWMIN3: AC_VO
+ * CWMIN0: AC_VO
+ * CWMIN1: AC_VI
+ * CWMIN2: AC_BE
+ * CWMIN3: AC_BK
  */
 #define WMM_CWMIN_CFG                   0x0218
 #define WMM_CWMIN_CFG_CWMIN0            FIELD32(0x0000000f)
@@ -231,10 +251,10 @@
 
 /*
  * WMM_CWMAX_CSR: CWmax for each EDCA AC
- * CWMAX0: AC_BE
- * CWMAX1: AC_BK
- * CWMAX2: AC_VI
- * CWMAX3: AC_VO
+ * CWMAX0: AC_VO
+ * CWMAX1: AC_VI
+ * CWMAX2: AC_BE
+ * CWMAX3: AC_BK
  */
 #define WMM_CWMAX_CFG                   0x021c
 #define WMM_CWMAX_CFG_CWMAX0            FIELD32(0x0000000f)
@@ -243,18 +263,18 @@
 #define WMM_CWMAX_CFG_CWMAX3            FIELD32(0x0000f000)
 
 /*
- * AC_TXOP0: AC_BK/AC_BE TXOP register
- * AC0TXOP: AC_BK in unit of 32us
- * AC1TXOP: AC_BE in unit of 32us
+ * AC_TXOP0: AC_VO/AC_VI TXOP register
+ * AC0TXOP: AC_VO in unit of 32us
+ * AC1TXOP: AC_VI in unit of 32us
  */
 #define WMM_TXOP0_CFG                   0x0220
 #define WMM_TXOP0_CFG_AC0TXOP           FIELD32(0x0000ffff)
 #define WMM_TXOP0_CFG_AC1TXOP           FIELD32(0xffff0000)
 
 /*
- * AC_TXOP1: AC_VO/AC_VI TXOP register
- * AC2TXOP: AC_VI in unit of 32us
- * AC3TXOP: AC_VO in unit of 32us
+ * AC_TXOP1: AC_BE/AC_BK TXOP register
+ * AC2TXOP: AC_BE in unit of 32us
+ * AC3TXOP: AC_BK in unit of 32us
  */
 #define WMM_TXOP1_CFG                   0x0224
 #define WMM_TXOP1_CFG_AC2TXOP           FIELD32(0x0000ffff)
@@ -262,6 +282,7 @@
 
 /*
  * GPIO_CTRL_CFG:
+ * GPIOD: GPIO direction, 0: Output, 1: Input
  */
 #define GPIO_CTRL_CFG                   0x0228
 #define GPIO_CTRL_CFG_BIT0              FIELD32(0x00000001)
@@ -272,7 +293,14 @@
 #define GPIO_CTRL_CFG_BIT5              FIELD32(0x00000020)
 #define GPIO_CTRL_CFG_BIT6              FIELD32(0x00000040)
 #define GPIO_CTRL_CFG_BIT7              FIELD32(0x00000080)
-#define GPIO_CTRL_CFG_BIT8              FIELD32(0x00000100)
+#define GPIO_CTRL_CFG_GPIOD_BIT0        FIELD32(0x00000100)
+#define GPIO_CTRL_CFG_GPIOD_BIT1        FIELD32(0x00000200)
+#define GPIO_CTRL_CFG_GPIOD_BIT2        FIELD32(0x00000400)
+#define GPIO_CTRL_CFG_GPIOD_BIT3        FIELD32(0x00000800)
+#define GPIO_CTRL_CFG_GPIOD_BIT4        FIELD32(0x00001000)
+#define GPIO_CTRL_CFG_GPIOD_BIT5        FIELD32(0x00002000)
+#define GPIO_CTRL_CFG_GPIOD_BIT6        FIELD32(0x00004000)
+#define GPIO_CTRL_CFG_GPIOD_BIT7        FIELD32(0x00008000)
 
 /*
  * MCU_CMD_CFG
@@ -280,7 +308,7 @@
 #define MCU_CMD_CFG                     0x022c
 
 /*
- * AC_BK register offsets
+ * AC_VO register offsets
  */
 #define TX_BASE_PTR0                    0x0230
 #define TX_MAX_CNT0                     0x0234
@@ -288,7 +316,7 @@
 #define TX_DTX_IDX0                     0x023c
 
 /*
- * AC_BE register offsets
+ * AC_VI register offsets
  */
 #define TX_BASE_PTR1                    0x0240
 #define TX_MAX_CNT1                     0x0244
@@ -296,7 +324,7 @@
 #define TX_DTX_IDX1                     0x024c
 
 /*
- * AC_VI register offsets
+ * AC_BE register offsets
  */
 #define TX_BASE_PTR2                    0x0250
 #define TX_MAX_CNT2                     0x0254
@@ -304,7 +332,7 @@
 #define TX_DTX_IDX2                     0x025c
 
 /*
- * AC_VO register offsets
+ * AC_BK register offsets
  */
 #define TX_BASE_PTR3                    0x0260
 #define TX_MAX_CNT3                     0x0264
@@ -364,8 +392,12 @@
 
 /*
  * US_CYC_CNT
+ * BT_MODE_EN: Bluetooth mode enable
+ * CLOCK CYCLE: Clock cycle count in 1us.
+ * PCI:0x21, PCIE:0x7d, USB:0x1e
  */
 #define US_CYC_CNT                      0x02a4
+#define US_CYC_CNT_BT_MODE_EN           FIELD32(0x00000100)
 #define US_CYC_CNT_CLOCK_CYCLE          FIELD32(0x000000ff)
 
 /*
@@ -411,10 +443,22 @@
 #define BCN_OFFSET1_BCN7                FIELD32(0xff000000)
 
 /*
- * PBF registers
- * Most are for debug. Driver doesn't touch PBF register.
+ * TXRXQ_PCNT: PBF register
+ * PCNT_TX0Q: Page count for TX hardware queue 0
+ * PCNT_TX1Q: Page count for TX hardware queue 1
+ * PCNT_TX2Q: Page count for TX hardware queue 2
+ * PCNT_RX0Q: Page count for RX hardware queue
  */
 #define TXRXQ_PCNT                      0x0438
+#define TXRXQ_PCNT_TX0Q                 FIELD32(0x000000ff)
+#define TXRXQ_PCNT_TX1Q                 FIELD32(0x0000ff00)
+#define TXRXQ_PCNT_TX2Q                 FIELD32(0x00ff0000)
+#define TXRXQ_PCNT_RX0Q                 FIELD32(0xff000000)
+
+/*
+ * PBF register
+ * Debug. Driver doesn't touch PBF register.
+ */
 #define PBF_DBG                         0x043c
 
 /*
@@ -422,7 +466,7 @@
  */
 #define RF_CSR_CFG                      0x0500
 #define RF_CSR_CFG_DATA                 FIELD32(0x000000ff)
-#define RF_CSR_CFG_REGNUM               FIELD32(0x00001f00)
+#define RF_CSR_CFG_REGNUM               FIELD32(0x00003f00)
 #define RF_CSR_CFG_WRITE                FIELD32(0x00010000)
 #define RF_CSR_CFG_BUSY                 FIELD32(0x00020000)
 
@@ -574,7 +618,7 @@
  * READ_CONTROL: 0 write BBP, 1 read BBP
  * BUSY: ASIC is busy executing BBP commands
  * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
- * BBP_RW_MODE: 0 serial, 1 paralell
+ * BBP_RW_MODE: 0 serial, 1 parallel
  */
 #define BBP_CSR_CFG                     0x101c
 #define BBP_CSR_CFG_VALUE               FIELD32(0x000000ff)
@@ -639,6 +683,18 @@
 #define LED_CFG_LED_POLAR               FIELD32(0x40000000)
 
 /*
+ * AMPDU_BA_WINSIZE: Force BlockAck window size
+ * FORCE_WINSIZE_ENABLE:
+ *   0: Disable forcing of BlockAck window size
+ *   1: Enable forcing of BlockAck window size, overwrites values BlockAck
+ *      window size values in the TXWI
+ * FORCE_WINSIZE: BlockAck window size
+ */
+#define AMPDU_BA_WINSIZE                0x1040
+#define AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE FIELD32(0x00000020)
+#define AMPDU_BA_WINSIZE_FORCE_WINSIZE  FIELD32(0x0000001f)
+
+/*
  * XIFS_TIME_CFG: MAC timing
  * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
  * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
@@ -673,8 +729,18 @@
 
 /*
  * CH_TIME_CFG: count as channel busy
+ * EIFS_BUSY: Count EIFS as channel busy
+ * NAV_BUSY: Count NAS as channel busy
+ * RX_BUSY: Count RX as channel busy
+ * TX_BUSY: Count TX as channel busy
+ * TMR_EN: Enable channel statistics timer
  */
 #define CH_TIME_CFG                     0x110c
+#define CH_TIME_CFG_EIFS_BUSY           FIELD32(0x00000010)
+#define CH_TIME_CFG_NAV_BUSY            FIELD32(0x00000008)
+#define CH_TIME_CFG_RX_BUSY             FIELD32(0x00000004)
+#define CH_TIME_CFG_TX_BUSY             FIELD32(0x00000002)
+#define CH_TIME_CFG_TMR_EN              FIELD32(0x00000001)
 
 /*
  * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
@@ -698,8 +764,14 @@
 
 /*
  * TBTT_SYNC_CFG:
+ * BCN_AIFSN: Beacon AIFSN after TBTT interrupt in slots
+ * BCN_CWMIN: Beacon CWMin after TBTT interrupt in slots
  */
 #define TBTT_SYNC_CFG                   0x1118
+#define TBTT_SYNC_CFG_TBTT_ADJUST       FIELD32(0x000000ff)
+#define TBTT_SYNC_CFG_BCN_EXP_WIN       FIELD32(0x0000ff00)
+#define TBTT_SYNC_CFG_BCN_AIFSN         FIELD32(0x000f0000)
+#define TBTT_SYNC_CFG_BCN_CWMIN         FIELD32(0x00f00000)
 
 /*
  * TSF_TIMER_DW0: Local lsb TSF timer, read-only
@@ -735,16 +807,21 @@
 #define INT_TIMER_EN_GP_TIMER           FIELD32(0x00000002)
 
 /*
- * CH_IDLE_STA: channel idle time
+ * CH_IDLE_STA: channel idle time (in us)
  */
 #define CH_IDLE_STA                     0x1130
 
 /*
- * CH_BUSY_STA: channel busy time
+ * CH_BUSY_STA: channel busy time on primary channel (in us)
  */
 #define CH_BUSY_STA                     0x1134
 
 /*
+ * CH_BUSY_STA_SEC: channel busy time on secondary channel in HT40 mode (in us)
+ */
+#define CH_BUSY_STA_SEC                 0x1138
+
+/*
  * MAC_STATUS_CFG:
  * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
  *      if 1 or higher one of the 2 registers is busy.
@@ -936,8 +1013,31 @@
 
 /*
  * TXOP_CTRL_CFG:
+ * TIMEOUT_TRUN_EN: Enable/Disable TXOP timeout truncation
+ * AC_TRUN_EN: Enable/Disable truncation for AC change
+ * TXRATEGRP_TRUN_EN: Enable/Disable truncation for TX rate group change
+ * USER_MODE_TRUN_EN: Enable/Disable truncation for user TXOP mode
+ * MIMO_PS_TRUN_EN: Enable/Disable truncation for MIMO PS RTS/CTS
+ * RESERVED_TRUN_EN: Reserved
+ * LSIG_TXOP_EN: Enable/Disable L-SIG TXOP protection
+ * EXT_CCA_EN: Enable/Disable extension channel CCA reference (Defer 40Mhz
+ *             transmissions if extension CCA is clear).
+ * EXT_CCA_DLY: Extension CCA signal delay time (unit: us)
+ * EXT_CWMIN: CwMin for extension channel backoff
+ *            0: Disabled
+ *
  */
 #define TXOP_CTRL_CFG                   0x1340
+#define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN   FIELD32(0x00000001)
+#define TXOP_CTRL_CFG_AC_TRUN_EN        FIELD32(0x00000002)
+#define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN FIELD32(0x00000004)
+#define TXOP_CTRL_CFG_USER_MODE_TRUN_EN FIELD32(0x00000008)
+#define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN   FIELD32(0x00000010)
+#define TXOP_CTRL_CFG_RESERVED_TRUN_EN  FIELD32(0x00000020)
+#define TXOP_CTRL_CFG_LSIG_TXOP_EN      FIELD32(0x00000040)
+#define TXOP_CTRL_CFG_EXT_CCA_EN        FIELD32(0x00000080)
+#define TXOP_CTRL_CFG_EXT_CCA_DLY       FIELD32(0x0000ff00)
+#define TXOP_CTRL_CFG_EXT_CWMIN         FIELD32(0x000f0000)
 
 /*
  * TX_RTS_CFG:
@@ -1056,8 +1156,8 @@
  * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
  * PROTECT_CTRL: Protection control frame type for CCK TX
  *               0:none, 1:RTS/CTS, 2:CTS-to-self
- * PROTECT_NAV: TXOP protection type for CCK TX
- *              0:none, 1:ShortNAVprotect, 2:LongNAVProtect
+ * PROTECT_NAV_SHORT: TXOP protection type for CCK TX with short NAV
+ * PROTECT_NAV_LONG: TXOP protection type for CCK TX with long NAV
  * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
  * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
  * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
@@ -1069,7 +1169,8 @@
 #define CCK_PROT_CFG                    0x1364
 #define CCK_PROT_CFG_PROTECT_RATE       FIELD32(0x0000ffff)
 #define CCK_PROT_CFG_PROTECT_CTRL       FIELD32(0x00030000)
-#define CCK_PROT_CFG_PROTECT_NAV        FIELD32(0x000c0000)
+#define CCK_PROT_CFG_PROTECT_NAV_SHORT  FIELD32(0x00040000)
+#define CCK_PROT_CFG_PROTECT_NAV_LONG   FIELD32(0x00080000)
 #define CCK_PROT_CFG_TX_OP_ALLOW_CCK    FIELD32(0x00100000)
 #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM   FIELD32(0x00200000)
 #define CCK_PROT_CFG_TX_OP_ALLOW_MM20   FIELD32(0x00400000)
@@ -1084,7 +1185,8 @@
 #define OFDM_PROT_CFG                   0x1368
 #define OFDM_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
 #define OFDM_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
-#define OFDM_PROT_CFG_PROTECT_NAV       FIELD32(0x000c0000)
+#define OFDM_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
+#define OFDM_PROT_CFG_PROTECT_NAV_LONG  FIELD32(0x00080000)
 #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
 #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
@@ -1099,7 +1201,8 @@
 #define MM20_PROT_CFG                   0x136c
 #define MM20_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
 #define MM20_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
-#define MM20_PROT_CFG_PROTECT_NAV       FIELD32(0x000c0000)
+#define MM20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
+#define MM20_PROT_CFG_PROTECT_NAV_LONG  FIELD32(0x00080000)
 #define MM20_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
 #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
 #define MM20_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
@@ -1114,7 +1217,8 @@
 #define MM40_PROT_CFG                   0x1370
 #define MM40_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
 #define MM40_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
-#define MM40_PROT_CFG_PROTECT_NAV       FIELD32(0x000c0000)
+#define MM40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
+#define MM40_PROT_CFG_PROTECT_NAV_LONG  FIELD32(0x00080000)
 #define MM40_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
 #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
 #define MM40_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
@@ -1129,7 +1233,8 @@
 #define GF20_PROT_CFG                   0x1374
 #define GF20_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
 #define GF20_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
-#define GF20_PROT_CFG_PROTECT_NAV       FIELD32(0x000c0000)
+#define GF20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
+#define GF20_PROT_CFG_PROTECT_NAV_LONG  FIELD32(0x00080000)
 #define GF20_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
 #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
 #define GF20_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
@@ -1144,7 +1249,8 @@
 #define GF40_PROT_CFG                   0x1378
 #define GF40_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
 #define GF40_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
-#define GF40_PROT_CFG_PROTECT_NAV       FIELD32(0x000c0000)
+#define GF40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
+#define GF40_PROT_CFG_PROTECT_NAV_LONG  FIELD32(0x00080000)
 #define GF40_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
 #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
 #define GF40_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
@@ -1318,11 +1424,34 @@
 #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
 
 /*
- * TX_STA_FIFO: TX Result for specific PID status fifo register
+ * TX_STA_FIFO: TX Result for specific PID status fifo register.
+ *
+ * This register is implemented as FIFO with 16 entries in the HW. Each
+ * register read fetches the next tx result. If the FIFO is full because
+ * it wasn't read fast enough after the according interrupt (TX_FIFO_STATUS)
+ * triggered, the hw seems to simply drop further tx results.
+ *
+ * VALID: 1: this tx result is valid
+ *        0: no valid tx result -> driver should stop reading
+ * PID_TYPE: The PID latched from the PID field in the TXWI, can be used
+ *           to match a frame with its tx result (even though the PID is
+ *           only 4 bits wide).
+ * PID_QUEUE: Part of PID_TYPE, this is the queue index number (0-3)
+ * PID_ENTRY: Part of PID_TYPE, this is the queue entry index number (1-3)
+ *            This identification number is calculated by ((idx % 3) + 1).
+ * TX_SUCCESS: Indicates tx success (1) or failure (0)
+ * TX_AGGRE: Indicates if the frame was part of an aggregate (1) or not (0)
+ * TX_ACK_REQUIRED: Indicates if the frame needed to get ack'ed (1) or not (0)
+ * WCID: The wireless client ID.
+ * MCS: The tx rate used during the last transmission of this frame, be it
+ *      successful or not.
+ * PHYMODE: The phymode used for the transmission.
  */
 #define TX_STA_FIFO                     0x1718
 #define TX_STA_FIFO_VALID               FIELD32(0x00000001)
 #define TX_STA_FIFO_PID_TYPE            FIELD32(0x0000001e)
+#define TX_STA_FIFO_PID_QUEUE           FIELD32(0x00000006)
+#define TX_STA_FIFO_PID_ENTRY           FIELD32(0x00000018)
 #define TX_STA_FIFO_TX_SUCCESS          FIELD32(0x00000020)
 #define TX_STA_FIFO_TX_AGGRE            FIELD32(0x00000040)
 #define TX_STA_FIFO_TX_ACK_REQUIRED     FIELD32(0x00000080)
@@ -1405,6 +1534,24 @@
 
 /*
  * Security key table memory.
+ *
+ * The pairwise key table shares some memory with the beacon frame
+ * buffers 6 and 7. That basically means that when beacon 6 & 7
+ * are used we should only use the reduced pairwise key table which
+ * has a maximum of 222 entries.
+ *
+ * ---------------------------------------------
+ * |0x4000 | Pairwise Key   | Reduced Pairwise |
+ * |       | Table          | Key Table        |
+ * |       | Size: 256 * 32 | Size: 222 * 32   |
+ * |0x5BC0 |                |-------------------
+ * |       |                | Beacon 6         |
+ * |0x5DC0 |                |-------------------
+ * |       |                | Beacon 7         |
+ * |0x5FC0 |                |-------------------
+ * |0x5FFF |                |
+ * --------------------------
+ *
  * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
  * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
  * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
@@ -1420,17 +1567,17 @@
 #define SHARED_KEY_MODE_BASE            0x7000
 
 #define MAC_WCID_ENTRY(__idx) \
-        ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
+        (MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)))
 #define PAIRWISE_KEY_ENTRY(__idx) \
-        ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
+        (PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
 #define MAC_IVEIV_ENTRY(__idx) \
-        ( MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)) )
+        (MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)))
 #define MAC_WCID_ATTR_ENTRY(__idx) \
-        ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
+        (MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)))
 #define SHARED_KEY_ENTRY(__idx) \
-        ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
+        (SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
 #define SHARED_KEY_MODE_ENTRY(__idx) \
-        ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
+        (SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)))
 
 struct mac_wcid_entry {
         u8 mac[6];
@@ -1554,7 +1701,8 @@ struct mac_iveiv_entry {
  * 2. Extract memory from FCE table for BCN 4~5
  * 3. Extract memory from Pair-wise key table for BCN 6~7
  *    It occupied those memory of wcid 238~253 for BCN 6
- *    and wcid 222~237 for BCN 7
+ *    and wcid 222~237 for BCN 7 (see Security key table memory
+ *    for more info).
  *
  * IMPORTANT NOTE: Not sure why legacy driver does this,
  * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
@@ -1569,9 +1717,9 @@ struct mac_iveiv_entry {
 #define HW_BEACON_BASE7                 0x5bc0
 
 #define HW_BEACON_OFFSET(__index) \
-        ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
-          (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
-          (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
+        (((__index) < 4) ? (HW_BEACON_BASE0 + (__index * 0x0200)) : \
+          (((__index) < 6) ? (HW_BEACON_BASE4 + ((__index - 4) * 0x0200)) : \
+          (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))))
 
 /*
  * BBP registers.
@@ -1579,11 +1727,14 @@ struct mac_iveiv_entry {
  */
 
 /*
- * BBP 1: TX Antenna & Power
- * POWER: 0 - normal, 1 - drop tx power by 6dBm, 2 - drop tx power by 12dBm,
- *      3 - increase tx power by 6dBm
+ * BBP 1: TX Antenna & Power Control
+ * POWER_CTRL:
+ * 0 - normal,
+ * 1 - drop tx power by 6dBm,
+ * 2 - drop tx power by 12dBm,
+ * 3 - increase tx power by 6dBm
  */
-#define BBP1_TX_POWER                   FIELD8(0x07)
+#define BBP1_TX_POWER_CTRL              FIELD8(0x07)
 #define BBP1_TX_ANTENNA                 FIELD8(0x18)
 
 /*
@@ -1597,6 +1748,13 @@ struct mac_iveiv_entry {
  */
 #define BBP4_TX_BF                      FIELD8(0x01)
 #define BBP4_BANDWIDTH                  FIELD8(0x18)
+#define BBP4_MAC_IF_CTRL                FIELD8(0x40)
+
+/*
+ * BBP 109
+ */
+#define BBP109_TX0_POWER                FIELD8(0x0f)
+#define BBP109_TX1_POWER                FIELD8(0xf0)
 
 /*
  * BBP 138: Unknown
@@ -1607,6 +1765,11 @@ struct mac_iveiv_entry {
 #define BBP138_TX_DAC2                  FIELD8(0x40)
 
 /*
+ * BBP 152: Rx Ant
+ */
+#define BBP152_RX_DEFAULT_ANT           FIELD8(0x80)
+
+/*
  * RFCSR registers
  * The wordsize of the RFCSR is 8 bits.
  */
@@ -1615,12 +1778,18 @@ struct mac_iveiv_entry {
  * RFCSR 1:
  */
 #define RFCSR1_RF_BLOCK_EN              FIELD8(0x01)
+#define RFCSR1_PLL_PD                   FIELD8(0x02)
 #define RFCSR1_RX0_PD                   FIELD8(0x04)
 #define RFCSR1_TX0_PD                   FIELD8(0x08)
 #define RFCSR1_RX1_PD                   FIELD8(0x10)
 #define RFCSR1_TX1_PD                   FIELD8(0x20)
 
 /*
+ * RFCSR 2:
+ */
+#define RFCSR2_RESCAL_EN                FIELD8(0x80)
+
+/*
  * RFCSR 6:
  */
 #define RFCSR6_R1                       FIELD8(0x03)
@@ -1632,6 +1801,11 @@ struct mac_iveiv_entry {
 #define RFCSR7_RF_TUNING                FIELD8(0x01)
 
 /*
+ * RFCSR 11:
+ */
+#define RFCSR11_R                       FIELD8(0x03)
+
+/*
  * RFCSR 12:
  */
 #define RFCSR12_TX_POWER                FIELD8(0x1f)
@@ -1652,6 +1826,7 @@ struct mac_iveiv_entry {
 #define RFCSR17_TXMIXER_GAIN            FIELD8(0x07)
 #define RFCSR17_TX_LO1_EN               FIELD8(0x08)
 #define RFCSR17_R                       FIELD8(0x20)
+#define RFCSR17_CODE                   FIELD8(0x7f)
 
 /*
  * RFCSR 20:
@@ -1684,9 +1859,33 @@ struct mac_iveiv_entry {
 /*
  * RFCSR 30:
  */
+#define RFCSR30_TX_H20M                 FIELD8(0x02)
+#define RFCSR30_RX_H20M                 FIELD8(0x04)
+#define RFCSR30_RX_VCM                  FIELD8(0x18)
 #define RFCSR30_RF_CALIBRATION          FIELD8(0x80)
 
 /*
+ * RFCSR 31:
+ */
+#define RFCSR31_RX_AGC_FC               FIELD8(0x1f)
+#define RFCSR31_RX_H20M                 FIELD8(0x20)
+
+/*
+ * RFCSR 38:
+ */
+#define RFCSR38_RX_LO1_EN               FIELD8(0x20)
+
+/*
+ * RFCSR 39:
+ */
+#define RFCSR39_RX_LO2_EN               FIELD8(0x80)
+
+/*
+ * RFCSR 49:
+ */
+#define RFCSR49_TX                      FIELD8(0x3f)
+
+/*
  * RF registers
  */
 
@@ -1719,6 +1918,11 @@ struct mac_iveiv_entry {
  */
 
 /*
+ * Chip ID
+ */
+#define EEPROM_CHIP_ID                  0x0000
+
+/*
  * EEPROM Version
  */
 #define EEPROM_VERSION                  0x0001
@@ -1739,32 +1943,51 @@ struct mac_iveiv_entry {
 #define EEPROM_MAC_ADDR_BYTE5           FIELD16(0xff00)
 
 /*
- * EEPROM ANTENNA config
+ * EEPROM NIC Configuration 0
  * RXPATH: 1: 1R, 2: 2R, 3: 3R
- * TXPATH: 1: 1T, 2: 2T
- */
-#define EEPROM_ANTENNA                  0x001a
-#define EEPROM_ANTENNA_RXPATH           FIELD16(0x000f)
-#define EEPROM_ANTENNA_TXPATH           FIELD16(0x00f0)
-#define EEPROM_ANTENNA_RF_TYPE          FIELD16(0x0f00)
-
-/*
- * EEPROM NIC config
- * CARDBUS_ACCEL: 0 - enable, 1 - disable
- */
-#define EEPROM_NIC                      0x001b
-#define EEPROM_NIC_HW_RADIO             FIELD16(0x0001)
-#define EEPROM_NIC_DYNAMIC_TX_AGC       FIELD16(0x0002)
-#define EEPROM_NIC_EXTERNAL_LNA_BG      FIELD16(0x0004)
-#define EEPROM_NIC_EXTERNAL_LNA_A       FIELD16(0x0008)
-#define EEPROM_NIC_CARDBUS_ACCEL        FIELD16(0x0010)
-#define EEPROM_NIC_BW40M_SB_BG          FIELD16(0x0020)
-#define EEPROM_NIC_BW40M_SB_A           FIELD16(0x0040)
-#define EEPROM_NIC_WPS_PBC              FIELD16(0x0080)
-#define EEPROM_NIC_BW40M_BG             FIELD16(0x0100)
-#define EEPROM_NIC_BW40M_A              FIELD16(0x0200)
-#define EEPROM_NIC_ANT_DIVERSITY        FIELD16(0x0800)
-#define EEPROM_NIC_DAC_TEST             FIELD16(0x8000)
+ * TXPATH: 1: 1T, 2: 2T, 3: 3T
+ * RF_TYPE: RFIC type
+ */
+#define EEPROM_NIC_CONF0                0x001a
+#define EEPROM_NIC_CONF0_RXPATH         FIELD16(0x000f)
+#define EEPROM_NIC_CONF0_TXPATH         FIELD16(0x00f0)
+#define EEPROM_NIC_CONF0_RF_TYPE                FIELD16(0x0f00)
+
+/*
+ * EEPROM NIC Configuration 1
+ * HW_RADIO: 0: disable, 1: enable
+ * EXTERNAL_TX_ALC: 0: disable, 1: enable
+ * EXTERNAL_LNA_2G: 0: disable, 1: enable
+ * EXTERNAL_LNA_5G: 0: disable, 1: enable
+ * CARDBUS_ACCEL: 0: enable, 1: disable
+ * BW40M_SB_2G: 0: disable, 1: enable
+ * BW40M_SB_5G: 0: disable, 1: enable
+ * WPS_PBC: 0: disable, 1: enable
+ * BW40M_2G: 0: enable, 1: disable
+ * BW40M_5G: 0: enable, 1: disable
+ * BROADBAND_EXT_LNA: 0: disable, 1: enable
+ * ANT_DIVERSITY: 00: Disable, 01: Diversity,
+ *                                10: Main antenna, 11: Aux antenna
+ * INTERNAL_TX_ALC: 0: disable, 1: enable
+ * BT_COEXIST: 0: disable, 1: enable
+ * DAC_TEST: 0: disable, 1: enable
+ */
+#define EEPROM_NIC_CONF1                0x001b
+#define EEPROM_NIC_CONF1_HW_RADIO               FIELD16(0x0001)
+#define EEPROM_NIC_CONF1_EXTERNAL_TX_ALC                FIELD16(0x0002)
+#define EEPROM_NIC_CONF1_EXTERNAL_LNA_2G                FIELD16(0x0004)
+#define EEPROM_NIC_CONF1_EXTERNAL_LNA_5G                FIELD16(0x0008)
+#define EEPROM_NIC_CONF1_CARDBUS_ACCEL          FIELD16(0x0010)
+#define EEPROM_NIC_CONF1_BW40M_SB_2G            FIELD16(0x0020)
+#define EEPROM_NIC_CONF1_BW40M_SB_5G            FIELD16(0x0040)
+#define EEPROM_NIC_CONF1_WPS_PBC                FIELD16(0x0080)
+#define EEPROM_NIC_CONF1_BW40M_2G               FIELD16(0x0100)
+#define EEPROM_NIC_CONF1_BW40M_5G               FIELD16(0x0200)
+#define EEPROM_NIC_CONF1_BROADBAND_EXT_LNA              FIELD16(0x400)
+#define EEPROM_NIC_CONF1_ANT_DIVERSITY          FIELD16(0x1800)
+#define EEPROM_NIC_CONF1_INTERNAL_TX_ALC                FIELD16(0x2000)
+#define EEPROM_NIC_CONF1_BT_COEXIST             FIELD16(0x4000)
+#define EEPROM_NIC_CONF1_DAC_TEST               FIELD16(0x8000)
 
 /*
  * EEPROM frequency
@@ -1786,9 +2009,9 @@ struct mac_iveiv_entry {
  * POLARITY_GPIO_4: Polarity GPIO4 setting.
  * LED_MODE: Led mode.
  */
-#define EEPROM_LED1                     0x001e
-#define EEPROM_LED2                     0x001f
-#define EEPROM_LED3                     0x0020
+#define EEPROM_LED_AG_CONF              0x001e
+#define EEPROM_LED_ACT_CONF             0x001f
+#define EEPROM_LED_POLARITY             0x0020
 #define EEPROM_LED_POLARITY_RDY_BG      FIELD16(0x0001)
 #define EEPROM_LED_POLARITY_RDY_A       FIELD16(0x0002)
 #define EEPROM_LED_POLARITY_ACT         FIELD16(0x0004)
@@ -1800,6 +2023,17 @@ struct mac_iveiv_entry {
 #define EEPROM_LED_LED_MODE             FIELD16(0x1f00)
 
 /*
+ * EEPROM NIC Configuration 2
+ * RX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
+ * TX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
+ * CRYSTAL: 00: Reserved, 01: One crystal, 10: Two crystal, 11: Reserved
+ */
+#define EEPROM_NIC_CONF2                0x0021
+#define EEPROM_NIC_CONF2_RX_STREAM              FIELD16(0x000f)
+#define EEPROM_NIC_CONF2_TX_STREAM              FIELD16(0x00f0)
+#define EEPROM_NIC_CONF2_CRYSTAL                FIELD16(0x0600)
+
+/*
  * EEPROM LNA
  */
 #define EEPROM_LNA                      0x0022
@@ -1841,16 +2075,26 @@ struct mac_iveiv_entry {
 #define EEPROM_RSSI_A2_LNA_A2           FIELD16(0xff00)
 
 /*
+ * EEPROM EIRP Maximum TX power values(unit: dbm)
+ */
+#define EEPROM_EIRP_MAX_TX_POWER        0x0027
+#define EEPROM_EIRP_MAX_TX_POWER_2GHZ   FIELD16(0x00ff)
+#define EEPROM_EIRP_MAX_TX_POWER_5GHZ   FIELD16(0xff00)
+
+/*
  * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
- *      This is delta in 40MHZ.
- * VALUE: Tx Power dalta value (MAX=4)
+ * This is delta in 40MHZ.
+ * VALUE: Tx Power dalta value, MAX=4(unit: dbm)
  * TYPE: 1: Plus the delta value, 0: minus the delta value
- * TXPOWER: Enable:
+ * ENABLE: enable tx power compensation for 40BW
  */
 #define EEPROM_TXPOWER_DELTA            0x0028
-#define EEPROM_TXPOWER_DELTA_VALUE      FIELD16(0x003f)
-#define EEPROM_TXPOWER_DELTA_TYPE       FIELD16(0x0040)
-#define EEPROM_TXPOWER_DELTA_TXPOWER    FIELD16(0x0080)
+#define EEPROM_TXPOWER_DELTA_VALUE_2G   FIELD16(0x003f)
+#define EEPROM_TXPOWER_DELTA_TYPE_2G    FIELD16(0x0040)
+#define EEPROM_TXPOWER_DELTA_ENABLE_2G  FIELD16(0x0080)
+#define EEPROM_TXPOWER_DELTA_VALUE_5G   FIELD16(0x3f00)
+#define EEPROM_TXPOWER_DELTA_TYPE_5G    FIELD16(0x4000)
+#define EEPROM_TXPOWER_DELTA_ENABLE_5G  FIELD16(0x8000)
 
 /*
  * EEPROM TXPOWER 802.11BG
@@ -1862,6 +2106,59 @@ struct mac_iveiv_entry {
 #define EEPROM_TXPOWER_BG_2             FIELD16(0xff00)
 
 /*
+ * EEPROM temperature compensation boundaries 802.11BG
+ * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
+ *         reduced by (agc_step * -4)
+ * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
+ *         reduced by (agc_step * -3)
+ */
+#define EEPROM_TSSI_BOUND_BG1           0x0037
+#define EEPROM_TSSI_BOUND_BG1_MINUS4    FIELD16(0x00ff)
+#define EEPROM_TSSI_BOUND_BG1_MINUS3    FIELD16(0xff00)
+
+/*
+ * EEPROM temperature compensation boundaries 802.11BG
+ * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
+ *         reduced by (agc_step * -2)
+ * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
+ *         reduced by (agc_step * -1)
+ */
+#define EEPROM_TSSI_BOUND_BG2           0x0038
+#define EEPROM_TSSI_BOUND_BG2_MINUS2    FIELD16(0x00ff)
+#define EEPROM_TSSI_BOUND_BG2_MINUS1    FIELD16(0xff00)
+
+/*
+ * EEPROM temperature compensation boundaries 802.11BG
+ * REF: Reference TSSI value, no tx power changes needed
+ * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
+ *        increased by (agc_step * 1)
+ */
+#define EEPROM_TSSI_BOUND_BG3           0x0039
+#define EEPROM_TSSI_BOUND_BG3_REF       FIELD16(0x00ff)
+#define EEPROM_TSSI_BOUND_BG3_PLUS1     FIELD16(0xff00)
+
+/*
+ * EEPROM temperature compensation boundaries 802.11BG
+ * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
+ *        increased by (agc_step * 2)
+ * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
+ *        increased by (agc_step * 3)
+ */
+#define EEPROM_TSSI_BOUND_BG4           0x003a
+#define EEPROM_TSSI_BOUND_BG4_PLUS2     FIELD16(0x00ff)
+#define EEPROM_TSSI_BOUND_BG4_PLUS3     FIELD16(0xff00)
+
+/*
+ * EEPROM temperature compensation boundaries 802.11BG
+ * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
+ *        increased by (agc_step * 4)
+ * AGC_STEP: Temperature compensation step.
+ */
+#define EEPROM_TSSI_BOUND_BG5           0x003b
+#define EEPROM_TSSI_BOUND_BG5_PLUS4     FIELD16(0x00ff)
+#define EEPROM_TSSI_BOUND_BG5_AGC_STEP  FIELD16(0xff00)
+
+/*
  * EEPROM TXPOWER 802.11A
  */
 #define EEPROM_TXPOWER_A1               0x003c
@@ -1871,6 +2168,59 @@ struct mac_iveiv_entry {
 #define EEPROM_TXPOWER_A_2              FIELD16(0xff00)
 
 /*
+ * EEPROM temperature compensation boundaries 802.11A
+ * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
+ *         reduced by (agc_step * -4)
+ * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
+ *         reduced by (agc_step * -3)
+ */
+#define EEPROM_TSSI_BOUND_A1            0x006a
+#define EEPROM_TSSI_BOUND_A1_MINUS4     FIELD16(0x00ff)
+#define EEPROM_TSSI_BOUND_A1_MINUS3     FIELD16(0xff00)
+
+/*
+ * EEPROM temperature compensation boundaries 802.11A
+ * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
+ *         reduced by (agc_step * -2)
+ * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
+ *         reduced by (agc_step * -1)
+ */
+#define EEPROM_TSSI_BOUND_A2            0x006b
+#define EEPROM_TSSI_BOUND_A2_MINUS2     FIELD16(0x00ff)
+#define EEPROM_TSSI_BOUND_A2_MINUS1     FIELD16(0xff00)
+
+/*
+ * EEPROM temperature compensation boundaries 802.11A
+ * REF: Reference TSSI value, no tx power changes needed
+ * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
+ *        increased by (agc_step * 1)
+ */
+#define EEPROM_TSSI_BOUND_A3            0x006c
+#define EEPROM_TSSI_BOUND_A3_REF        FIELD16(0x00ff)
+#define EEPROM_TSSI_BOUND_A3_PLUS1      FIELD16(0xff00)
+
+/*
+ * EEPROM temperature compensation boundaries 802.11A
+ * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
+ *        increased by (agc_step * 2)
+ * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
+ *        increased by (agc_step * 3)
+ */
+#define EEPROM_TSSI_BOUND_A4            0x006d
+#define EEPROM_TSSI_BOUND_A4_PLUS2      FIELD16(0x00ff)
+#define EEPROM_TSSI_BOUND_A4_PLUS3      FIELD16(0xff00)
+
+/*
+ * EEPROM temperature compensation boundaries 802.11A
+ * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
+ *        increased by (agc_step * 4)
+ * AGC_STEP: Temperature compensation step.
+ */
+#define EEPROM_TSSI_BOUND_A5            0x006e
+#define EEPROM_TSSI_BOUND_A5_PLUS4      FIELD16(0x00ff)
+#define EEPROM_TSSI_BOUND_A5_AGC_STEP   FIELD16(0xff00)
+
+/*
  * EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode
  */
 #define EEPROM_TXPOWER_BYRATE           0x006f
@@ -1898,11 +2248,12 @@ struct mac_iveiv_entry {
 #define MCU_CURRENT                     0x36
 #define MCU_LED                         0x50
 #define MCU_LED_STRENGTH                0x51
-#define MCU_LED_1                       0x52
-#define MCU_LED_2                       0x53
-#define MCU_LED_3                       0x54
+#define MCU_LED_AG_CONF         0x52
+#define MCU_LED_ACT_CONF                0x53
+#define MCU_LED_LED_POLARITY            0x54
 #define MCU_RADAR                       0x60
 #define MCU_BOOT_SIGNAL                 0x72
+#define MCU_ANT_SELECT                  0X73
 #define MCU_BBP_SIGNAL                  0x80
 #define MCU_POWER_SAVE                  0x83
 
@@ -1914,8 +2265,8 @@ struct mac_iveiv_entry {
 /*
  * DMA descriptor defines.
  */
-#define TXWI_DESC_SIZE                  ( 4 * sizeof(__le32) )
-#define RXWI_DESC_SIZE                  ( 4 * sizeof(__le32) )
+#define TXWI_DESC_SIZE                  (4 * sizeof(__le32))
+#define RXWI_DESC_SIZE                  (4 * sizeof(__le32))
 
 /*
  * TX WI structure
@@ -1926,8 +2277,17 @@ struct mac_iveiv_entry {
  * FRAG: 1 To inform TKIP engine this is a fragment.
  * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
  * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
- * BW: Channel bandwidth 20MHz or 40 MHz
+ * BW: Channel bandwidth 0:20MHz, 1:40 MHz (for legacy rates this will
+ *     duplicate the frame to both channels).
  * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
+ * AMPDU: 1: this frame is eligible for AMPDU aggregation, the hw will
+ *        aggregate consecutive frames with the same RA and QoS TID. If
+ *        a frame A with the same RA and QoS TID but AMPDU=0 is queued
+ *        directly after a frame B with AMPDU=1, frame A might still
+ *        get aggregated into the AMPDU started by frame B. So, setting
+ *        AMPDU to 0 does _not_ necessarily mean the frame is sent as
+ *        MPDU, it can still end up in an AMPDU if the previous frame
+ *        was tagged as AMPDU.
  */
 #define TXWI_W0_FRAG                    FIELD32(0x00000001)
 #define TXWI_W0_MIMO_PS                 FIELD32(0x00000002)
@@ -1945,6 +2305,19 @@ struct mac_iveiv_entry {
 
 /*
  * Word1
+ * ACK: 0: No Ack needed, 1: Ack needed
+ * NSEQ: 0: Don't assign hw sequence number, 1: Assign hw sequence number
+ * BW_WIN_SIZE: BA windows size of the recipient
+ * WIRELESS_CLI_ID: Client ID for WCID table access
+ * MPDU_TOTAL_BYTE_COUNT: Length of 802.11 frame
+ * PACKETID: Will be latched into the TX_STA_FIFO register once the according
+ *           frame was processed. If multiple frames are aggregated together
+ *           (AMPDU==1) the reported tx status will always contain the packet
+ *           id of the first frame. 0: Don't report tx status for this frame.
+ * PACKETID_QUEUE: Part of PACKETID, This is the queue index (0-3)
+ * PACKETID_ENTRY: Part of PACKETID, THis is the queue entry index (1-3)
+ *                 This identification number is calculated by ((idx % 3) + 1).
+ *                 The (+1) is required to prevent PACKETID to become 0.
  */
 #define TXWI_W1_ACK                     FIELD32(0x00000001)
 #define TXWI_W1_NSEQ                    FIELD32(0x00000002)
@@ -1952,6 +2325,8 @@ struct mac_iveiv_entry {
 #define TXWI_W1_WIRELESS_CLI_ID         FIELD32(0x0000ff00)
 #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT   FIELD32(0x0fff0000)
 #define TXWI_W1_PACKETID                FIELD32(0xf0000000)
+#define TXWI_W1_PACKETID_QUEUE          FIELD32(0x30000000)
+#define TXWI_W1_PACKETID_ENTRY          FIELD32(0xc0000000)
 
 /*
  * Word2
@@ -2023,4 +2398,9 @@ struct mac_iveiv_entry {
 #define TXPOWER_A_TO_DEV(__txpower) \
         clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
 
+/*
+ *  Board's maximun TX power limitation
+ */
+#define EIRP_MAX_TX_POWER_LIMIT 0x50
+
 #endif /* RT2800_H */