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path: root/drivers/net/wireless/rt2x00/rt61pci.c
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Diffstat (limited to 'drivers/net/wireless/rt2x00/rt61pci.c')
-rw-r--r--drivers/net/wireless/rt2x00/rt61pci.c573
1 files changed, 377 insertions, 196 deletions
diff --git a/drivers/net/wireless/rt2x00/rt61pci.c b/drivers/net/wireless/rt2x00/rt61pci.c
index e539c6cb636f..9d35ec16a3a5 100644
--- a/drivers/net/wireless/rt2x00/rt61pci.c
+++ b/drivers/net/wireless/rt2x00/rt61pci.c
@@ -551,26 +551,14 @@ static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
551 struct rt2x00intf_conf *conf, 551 struct rt2x00intf_conf *conf,
552 const unsigned int flags) 552 const unsigned int flags)
553{ 553{
554 unsigned int beacon_base;
555 u32 reg; 554 u32 reg;
556 555
557 if (flags & CONFIG_UPDATE_TYPE) { 556 if (flags & CONFIG_UPDATE_TYPE) {
558 /* 557 /*
559 * Clear current synchronisation setup.
560 * For the Beacon base registers, we only need to clear
561 * the first byte since that byte contains the VALID and OWNER
562 * bits which (when set to 0) will invalidate the entire beacon.
563 */
564 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
565 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
566
567 /*
568 * Enable synchronisation. 558 * Enable synchronisation.
569 */ 559 */
570 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg); 560 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
571 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
572 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync); 561 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
573 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
574 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); 562 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
575 } 563 }
576 564
@@ -594,7 +582,8 @@ static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
594} 582}
595 583
596static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev, 584static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
597 struct rt2x00lib_erp *erp) 585 struct rt2x00lib_erp *erp,
586 u32 changed)
598{ 587{
599 u32 reg; 588 u32 reg;
600 589
@@ -603,28 +592,36 @@ static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
603 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); 592 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
604 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); 593 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
605 594
606 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg); 595 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
607 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1); 596 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
608 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE, 597 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
609 !!erp->short_preamble); 598 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
610 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg); 599 !!erp->short_preamble);
600 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
601 }
611 602
612 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates); 603 if (changed & BSS_CHANGED_BASIC_RATES)
604 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5,
605 erp->basic_rates);
613 606
614 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg); 607 if (changed & BSS_CHANGED_BEACON_INT) {
615 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 608 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
616 erp->beacon_int * 16); 609 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
617 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); 610 erp->beacon_int * 16);
611 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
612 }
618 613
619 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg); 614 if (changed & BSS_CHANGED_ERP_SLOT) {
620 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time); 615 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
621 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg); 616 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
617 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
622 618
623 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg); 619 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
624 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs); 620 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
625 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); 621 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
626 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs); 622 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
627 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg); 623 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
624 }
628} 625}
629 626
630static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev, 627static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
@@ -686,7 +683,7 @@ static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
686 683
687 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529)); 684 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529));
688 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 685 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
689 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)); 686 !test_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags));
690 687
691 /* 688 /*
692 * Configure the RX antenna. 689 * Configure the RX antenna.
@@ -814,10 +811,10 @@ static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
814 811
815 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { 812 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
816 sel = antenna_sel_a; 813 sel = antenna_sel_a;
817 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags); 814 lna = test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
818 } else { 815 } else {
819 sel = antenna_sel_bg; 816 sel = antenna_sel_bg;
820 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags); 817 lna = test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
821 } 818 }
822 819
823 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++) 820 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
@@ -837,7 +834,7 @@ static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
837 else if (rt2x00_rf(rt2x00dev, RF2527)) 834 else if (rt2x00_rf(rt2x00dev, RF2527))
838 rt61pci_config_antenna_2x(rt2x00dev, ant); 835 rt61pci_config_antenna_2x(rt2x00dev, ant);
839 else if (rt2x00_rf(rt2x00dev, RF2529)) { 836 else if (rt2x00_rf(rt2x00dev, RF2529)) {
840 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) 837 if (test_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags))
841 rt61pci_config_antenna_2x(rt2x00dev, ant); 838 rt61pci_config_antenna_2x(rt2x00dev, ant);
842 else 839 else
843 rt61pci_config_antenna_2529(rt2x00dev, ant); 840 rt61pci_config_antenna_2529(rt2x00dev, ant);
@@ -851,13 +848,13 @@ static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
851 short lna_gain = 0; 848 short lna_gain = 0;
852 849
853 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) { 850 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
854 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) 851 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags))
855 lna_gain += 14; 852 lna_gain += 14;
856 853
857 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom); 854 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
858 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1); 855 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
859 } else { 856 } else {
860 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) 857 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
861 lna_gain += 14; 858 lna_gain += 14;
862 859
863 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom); 860 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
@@ -1050,17 +1047,17 @@ static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1050 /* 1047 /*
1051 * Determine r17 bounds. 1048 * Determine r17 bounds.
1052 */ 1049 */
1053 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) { 1050 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1054 low_bound = 0x28; 1051 low_bound = 0x28;
1055 up_bound = 0x48; 1052 up_bound = 0x48;
1056 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) { 1053 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags)) {
1057 low_bound += 0x10; 1054 low_bound += 0x10;
1058 up_bound += 0x10; 1055 up_bound += 0x10;
1059 } 1056 }
1060 } else { 1057 } else {
1061 low_bound = 0x20; 1058 low_bound = 0x20;
1062 up_bound = 0x40; 1059 up_bound = 0x40;
1063 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) { 1060 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags)) {
1064 low_bound += 0x10; 1061 low_bound += 0x10;
1065 up_bound += 0x10; 1062 up_bound += 0x10;
1066 } 1063 }
@@ -1131,6 +1128,116 @@ dynamic_cca_tune:
1131} 1128}
1132 1129
1133/* 1130/*
1131 * Queue handlers.
1132 */
1133static void rt61pci_start_queue(struct data_queue *queue)
1134{
1135 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1136 u32 reg;
1137
1138 switch (queue->qid) {
1139 case QID_RX:
1140 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1141 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1142 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1143 break;
1144 case QID_BEACON:
1145 /*
1146 * Allow the tbtt tasklet to be scheduled.
1147 */
1148 tasklet_enable(&rt2x00dev->tbtt_tasklet);
1149
1150 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1151 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1152 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1153 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1154 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1155 break;
1156 default:
1157 break;
1158 }
1159}
1160
1161static void rt61pci_kick_queue(struct data_queue *queue)
1162{
1163 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1164 u32 reg;
1165
1166 switch (queue->qid) {
1167 case QID_AC_VO:
1168 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1169 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, 1);
1170 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1171 break;
1172 case QID_AC_VI:
1173 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1174 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, 1);
1175 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1176 break;
1177 case QID_AC_BE:
1178 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1179 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, 1);
1180 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1181 break;
1182 case QID_AC_BK:
1183 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1184 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, 1);
1185 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1186 break;
1187 default:
1188 break;
1189 }
1190}
1191
1192static void rt61pci_stop_queue(struct data_queue *queue)
1193{
1194 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1195 u32 reg;
1196
1197 switch (queue->qid) {
1198 case QID_AC_VO:
1199 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1200 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1201 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1202 break;
1203 case QID_AC_VI:
1204 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1205 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1206 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1207 break;
1208 case QID_AC_BE:
1209 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1210 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1211 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1212 break;
1213 case QID_AC_BK:
1214 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1215 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1216 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1217 break;
1218 case QID_RX:
1219 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1220 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1);
1221 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1222 break;
1223 case QID_BEACON:
1224 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1225 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1226 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1227 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1228 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1229
1230 /*
1231 * Wait for possibly running tbtt tasklets.
1232 */
1233 tasklet_disable(&rt2x00dev->tbtt_tasklet);
1234 break;
1235 default:
1236 break;
1237 }
1238}
1239
1240/*
1134 * Firmware functions 1241 * Firmware functions
1135 */ 1242 */
1136static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev) 1243static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
@@ -1607,24 +1714,12 @@ static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1607/* 1714/*
1608 * Device state switch handlers. 1715 * Device state switch handlers.
1609 */ 1716 */
1610static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1611 enum dev_state state)
1612{
1613 u32 reg;
1614
1615 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1616 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1617 (state == STATE_RADIO_RX_OFF) ||
1618 (state == STATE_RADIO_RX_OFF_LINK));
1619 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1620}
1621
1622static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev, 1717static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1623 enum dev_state state) 1718 enum dev_state state)
1624{ 1719{
1625 int mask = (state == STATE_RADIO_IRQ_OFF) || 1720 int mask = (state == STATE_RADIO_IRQ_OFF);
1626 (state == STATE_RADIO_IRQ_OFF_ISR);
1627 u32 reg; 1721 u32 reg;
1722 unsigned long flags;
1628 1723
1629 /* 1724 /*
1630 * When interrupts are being enabled, the interrupt registers 1725 * When interrupts are being enabled, the interrupt registers
@@ -1636,15 +1731,25 @@ static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1636 1731
1637 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg); 1732 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1638 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg); 1733 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1734
1735 /*
1736 * Enable tasklets.
1737 */
1738 tasklet_enable(&rt2x00dev->txstatus_tasklet);
1739 tasklet_enable(&rt2x00dev->rxdone_tasklet);
1740 tasklet_enable(&rt2x00dev->autowake_tasklet);
1639 } 1741 }
1640 1742
1641 /* 1743 /*
1642 * Only toggle the interrupts bits we are going to use. 1744 * Only toggle the interrupts bits we are going to use.
1643 * Non-checked interrupt bits are disabled by default. 1745 * Non-checked interrupt bits are disabled by default.
1644 */ 1746 */
1747 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
1748
1645 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg); 1749 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1646 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask); 1750 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1647 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask); 1751 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1752 rt2x00_set_field32(&reg, INT_MASK_CSR_BEACON_DONE, mask);
1648 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask); 1753 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1649 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff); 1754 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1650 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg); 1755 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
@@ -1658,7 +1763,19 @@ static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1658 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask); 1763 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1659 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask); 1764 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1660 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask); 1765 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1766 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_TWAKEUP, mask);
1661 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); 1767 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1768
1769 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
1770
1771 if (state == STATE_RADIO_IRQ_OFF) {
1772 /*
1773 * Ensure that all tasklets are finished.
1774 */
1775 tasklet_disable(&rt2x00dev->txstatus_tasklet);
1776 tasklet_disable(&rt2x00dev->rxdone_tasklet);
1777 tasklet_disable(&rt2x00dev->autowake_tasklet);
1778 }
1662} 1779}
1663 1780
1664static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev) 1781static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
@@ -1733,16 +1850,8 @@ static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1733 case STATE_RADIO_OFF: 1850 case STATE_RADIO_OFF:
1734 rt61pci_disable_radio(rt2x00dev); 1851 rt61pci_disable_radio(rt2x00dev);
1735 break; 1852 break;
1736 case STATE_RADIO_RX_ON:
1737 case STATE_RADIO_RX_ON_LINK:
1738 case STATE_RADIO_RX_OFF:
1739 case STATE_RADIO_RX_OFF_LINK:
1740 rt61pci_toggle_rx(rt2x00dev, state);
1741 break;
1742 case STATE_RADIO_IRQ_ON: 1853 case STATE_RADIO_IRQ_ON:
1743 case STATE_RADIO_IRQ_ON_ISR:
1744 case STATE_RADIO_IRQ_OFF: 1854 case STATE_RADIO_IRQ_OFF:
1745 case STATE_RADIO_IRQ_OFF_ISR:
1746 rt61pci_toggle_irq(rt2x00dev, state); 1855 rt61pci_toggle_irq(rt2x00dev, state);
1747 break; 1856 break;
1748 case STATE_DEEP_SLEEP: 1857 case STATE_DEEP_SLEEP:
@@ -1766,12 +1875,11 @@ static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1766/* 1875/*
1767 * TX descriptor initialization 1876 * TX descriptor initialization
1768 */ 1877 */
1769static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, 1878static void rt61pci_write_tx_desc(struct queue_entry *entry,
1770 struct sk_buff *skb,
1771 struct txentry_desc *txdesc) 1879 struct txentry_desc *txdesc)
1772{ 1880{
1773 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 1881 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1774 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data; 1882 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1775 __le32 *txd = entry_priv->desc; 1883 __le32 *txd = entry_priv->desc;
1776 u32 word; 1884 u32 word;
1777 1885
@@ -1779,10 +1887,10 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1779 * Start writing the descriptor words. 1887 * Start writing the descriptor words.
1780 */ 1888 */
1781 rt2x00_desc_read(txd, 1, &word); 1889 rt2x00_desc_read(txd, 1, &word);
1782 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue); 1890 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid);
1783 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs); 1891 rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs);
1784 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min); 1892 rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
1785 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max); 1893 rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
1786 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset); 1894 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1787 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1895 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1788 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); 1896 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
@@ -1790,10 +1898,12 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1790 rt2x00_desc_write(txd, 1, word); 1898 rt2x00_desc_write(txd, 1, word);
1791 1899
1792 rt2x00_desc_read(txd, 2, &word); 1900 rt2x00_desc_read(txd, 2, &word);
1793 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal); 1901 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal);
1794 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service); 1902 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service);
1795 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low); 1903 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW,
1796 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high); 1904 txdesc->u.plcp.length_low);
1905 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH,
1906 txdesc->u.plcp.length_high);
1797 rt2x00_desc_write(txd, 2, word); 1907 rt2x00_desc_write(txd, 2, word);
1798 1908
1799 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) { 1909 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
@@ -1802,15 +1912,15 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1802 } 1912 }
1803 1913
1804 rt2x00_desc_read(txd, 5, &word); 1914 rt2x00_desc_read(txd, 5, &word);
1805 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid); 1915 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
1806 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, 1916 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1807 skbdesc->entry->entry_idx); 1917 skbdesc->entry->entry_idx);
1808 rt2x00_set_field32(&word, TXD_W5_TX_POWER, 1918 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1809 TXPOWER_TO_DEV(rt2x00dev->tx_power)); 1919 TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power));
1810 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1); 1920 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1811 rt2x00_desc_write(txd, 5, word); 1921 rt2x00_desc_write(txd, 5, word);
1812 1922
1813 if (txdesc->queue != QID_BEACON) { 1923 if (entry->queue->qid != QID_BEACON) {
1814 rt2x00_desc_read(txd, 6, &word); 1924 rt2x00_desc_read(txd, 6, &word);
1815 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS, 1925 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1816 skbdesc->skb_dma); 1926 skbdesc->skb_dma);
@@ -1838,7 +1948,7 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1838 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 1948 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1839 rt2x00_set_field32(&word, TXD_W0_OFDM, 1949 rt2x00_set_field32(&word, TXD_W0_OFDM,
1840 (txdesc->rate_mode == RATE_MODE_OFDM)); 1950 (txdesc->rate_mode == RATE_MODE_OFDM));
1841 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); 1951 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1842 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 1952 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1843 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); 1953 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1844 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 1954 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
@@ -1856,8 +1966,8 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1856 * Register descriptor details in skb frame descriptor. 1966 * Register descriptor details in skb frame descriptor.
1857 */ 1967 */
1858 skbdesc->desc = txd; 1968 skbdesc->desc = txd;
1859 skbdesc->desc_len = 1969 skbdesc->desc_len = (entry->queue->qid == QID_BEACON) ? TXINFO_SIZE :
1860 (txdesc->queue == QID_BEACON) ? TXINFO_SIZE : TXD_DESC_SIZE; 1970 TXD_DESC_SIZE;
1861} 1971}
1862 1972
1863/* 1973/*
@@ -1869,20 +1979,22 @@ static void rt61pci_write_beacon(struct queue_entry *entry,
1869 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1979 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1870 struct queue_entry_priv_pci *entry_priv = entry->priv_data; 1980 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1871 unsigned int beacon_base; 1981 unsigned int beacon_base;
1872 u32 reg; 1982 unsigned int padding_len;
1983 u32 orig_reg, reg;
1873 1984
1874 /* 1985 /*
1875 * Disable beaconing while we are reloading the beacon data, 1986 * Disable beaconing while we are reloading the beacon data,
1876 * otherwise we might be sending out invalid data. 1987 * otherwise we might be sending out invalid data.
1877 */ 1988 */
1878 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg); 1989 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1990 orig_reg = reg;
1879 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0); 1991 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1880 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); 1992 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1881 1993
1882 /* 1994 /*
1883 * Write the TX descriptor for the beacon. 1995 * Write the TX descriptor for the beacon.
1884 */ 1996 */
1885 rt61pci_write_tx_desc(rt2x00dev, entry->skb, txdesc); 1997 rt61pci_write_tx_desc(entry, txdesc);
1886 1998
1887 /* 1999 /*
1888 * Dump beacon to userspace through debugfs. 2000 * Dump beacon to userspace through debugfs.
@@ -1890,13 +2002,23 @@ static void rt61pci_write_beacon(struct queue_entry *entry,
1890 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb); 2002 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1891 2003
1892 /* 2004 /*
1893 * Write entire beacon with descriptor to register. 2005 * Write entire beacon with descriptor and padding to register.
1894 */ 2006 */
2007 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
2008 if (padding_len && skb_pad(entry->skb, padding_len)) {
2009 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
2010 /* skb freed by skb_pad() on failure */
2011 entry->skb = NULL;
2012 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, orig_reg);
2013 return;
2014 }
2015
1895 beacon_base = HW_BEACON_OFFSET(entry->entry_idx); 2016 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1896 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base, 2017 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
1897 entry_priv->desc, TXINFO_SIZE); 2018 entry_priv->desc, TXINFO_SIZE);
1898 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE, 2019 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE,
1899 entry->skb->data, entry->skb->len); 2020 entry->skb->data,
2021 entry->skb->len + padding_len);
1900 2022
1901 /* 2023 /*
1902 * Enable beaconing again. 2024 * Enable beaconing again.
@@ -1906,8 +2028,6 @@ static void rt61pci_write_beacon(struct queue_entry *entry,
1906 */ 2028 */
1907 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008); 2029 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1908 2030
1909 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1910 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1911 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1); 2031 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1912 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); 2032 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1913 2033
@@ -1918,35 +2038,30 @@ static void rt61pci_write_beacon(struct queue_entry *entry,
1918 entry->skb = NULL; 2038 entry->skb = NULL;
1919} 2039}
1920 2040
1921static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, 2041static void rt61pci_clear_beacon(struct queue_entry *entry)
1922 const enum data_queue_qid queue)
1923{ 2042{
2043 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1924 u32 reg; 2044 u32 reg;
1925 2045
1926 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg); 2046 /*
1927 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE)); 2047 * Disable beaconing while we are reloading the beacon data,
1928 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK)); 2048 * otherwise we might be sending out invalid data.
1929 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI)); 2049 */
1930 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO)); 2050 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1931 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); 2051 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1932} 2052 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1933
1934static void rt61pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1935 const enum data_queue_qid qid)
1936{
1937 u32 reg;
1938 2053
1939 if (qid == QID_BEACON) { 2054 /*
1940 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0); 2055 * Clear beacon.
1941 return; 2056 */
1942 } 2057 rt2x00pci_register_write(rt2x00dev,
2058 HW_BEACON_OFFSET(entry->entry_idx), 0);
1943 2059
1944 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg); 2060 /*
1945 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, (qid == QID_AC_BE)); 2061 * Enable beaconing again.
1946 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, (qid == QID_AC_BK)); 2062 */
1947 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, (qid == QID_AC_VI)); 2063 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1948 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, (qid == QID_AC_VO)); 2064 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1949 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1950} 2065}
1951 2066
1952/* 2067/*
@@ -1972,7 +2087,7 @@ static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1972 return 0; 2087 return 0;
1973 } 2088 }
1974 2089
1975 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) { 2090 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1976 if (lna == 3 || lna == 2) 2091 if (lna == 3 || lna == 2)
1977 offset += 10; 2092 offset += 10;
1978 } 2093 }
@@ -2013,9 +2128,8 @@ static void rt61pci_fill_rxdone(struct queue_entry *entry,
2013 rxdesc->flags |= RX_FLAG_IV_STRIPPED; 2128 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2014 2129
2015 /* 2130 /*
2016 * FIXME: Legacy driver indicates that the frame does 2131 * The hardware has already checked the Michael Mic and has
2017 * contain the Michael Mic. Unfortunately, in rt2x00 2132 * stripped it from the frame. Signal this to mac80211.
2018 * the MIC seems to be missing completely...
2019 */ 2133 */
2020 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED; 2134 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
2021 2135
@@ -2068,7 +2182,7 @@ static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2068 * that the TX_STA_FIFO stack has a size of 16. We stick to our 2182 * that the TX_STA_FIFO stack has a size of 16. We stick to our
2069 * tx ring size for now. 2183 * tx ring size for now.
2070 */ 2184 */
2071 for (i = 0; i < TX_ENTRIES; i++) { 2185 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
2072 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg); 2186 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
2073 if (!rt2x00_get_field32(reg, STA_CSR4_VALID)) 2187 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2074 break; 2188 break;
@@ -2078,7 +2192,7 @@ static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2078 * queue identication number. 2192 * queue identication number.
2079 */ 2193 */
2080 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE); 2194 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
2081 queue = rt2x00queue_get_queue(rt2x00dev, type); 2195 queue = rt2x00queue_get_tx_queue(rt2x00dev, type);
2082 if (unlikely(!queue)) 2196 if (unlikely(!queue))
2083 continue; 2197 continue;
2084 2198
@@ -2107,11 +2221,7 @@ static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2107 "TX status report missed for entry %d\n", 2221 "TX status report missed for entry %d\n",
2108 entry_done->entry_idx); 2222 entry_done->entry_idx);
2109 2223
2110 txdesc.flags = 0; 2224 rt2x00lib_txdone_noinfo(entry_done, TXDONE_UNKNOWN);
2111 __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
2112 txdesc.retry = 0;
2113
2114 rt2x00lib_txdone(entry_done, &txdesc);
2115 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 2225 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2116 } 2226 }
2117 2227
@@ -2150,61 +2260,79 @@ static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev)
2150 rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS); 2260 rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
2151} 2261}
2152 2262
2153static irqreturn_t rt61pci_interrupt_thread(int irq, void *dev_instance) 2263static inline void rt61pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
2264 struct rt2x00_field32 irq_field)
2154{ 2265{
2155 struct rt2x00_dev *rt2x00dev = dev_instance; 2266 u32 reg;
2156 u32 reg = rt2x00dev->irqvalue[0];
2157 u32 reg_mcu = rt2x00dev->irqvalue[1];
2158 2267
2159 /* 2268 /*
2160 * Handle interrupts, walk through all bits 2269 * Enable a single interrupt. The interrupt mask register
2161 * and run the tasks, the bits are checked in order of 2270 * access needs locking.
2162 * priority.
2163 */ 2271 */
2272 spin_lock_irq(&rt2x00dev->irqmask_lock);
2164 2273
2165 /* 2274 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
2166 * 1 - Rx ring done interrupt. 2275 rt2x00_set_field32(&reg, irq_field, 0);
2167 */ 2276 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
2168 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2169 rt2x00pci_rxdone(rt2x00dev);
2170 2277
2171 /* 2278 spin_unlock_irq(&rt2x00dev->irqmask_lock);
2172 * 2 - Tx ring done interrupt. 2279}
2173 */
2174 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2175 rt61pci_txdone(rt2x00dev);
2176 2280
2177 /* 2281static void rt61pci_enable_mcu_interrupt(struct rt2x00_dev *rt2x00dev,
2178 * 3 - Handle MCU command done. 2282 struct rt2x00_field32 irq_field)
2179 */ 2283{
2180 if (reg_mcu) 2284 u32 reg;
2181 rt2x00pci_register_write(rt2x00dev,
2182 M2H_CMD_DONE_CSR, 0xffffffff);
2183 2285
2184 /* 2286 /*
2185 * 4 - MCU Autowakeup interrupt. 2287 * Enable a single MCU interrupt. The interrupt mask register
2288 * access needs locking.
2186 */ 2289 */
2187 if (rt2x00_get_field32(reg_mcu, MCU_INT_SOURCE_CSR_TWAKEUP)) 2290 spin_lock_irq(&rt2x00dev->irqmask_lock);
2188 rt61pci_wakeup(rt2x00dev);
2189 2291
2190 /* 2292 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
2191 * 5 - Beacon done interrupt. 2293 rt2x00_set_field32(&reg, irq_field, 0);
2192 */ 2294 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
2193 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE))
2194 rt2x00lib_beacondone(rt2x00dev);
2195 2295
2196 /* Enable interrupts again. */ 2296 spin_unlock_irq(&rt2x00dev->irqmask_lock);
2197 rt2x00dev->ops->lib->set_device_state(rt2x00dev, 2297}
2198 STATE_RADIO_IRQ_ON_ISR); 2298
2199 return IRQ_HANDLED; 2299static void rt61pci_txstatus_tasklet(unsigned long data)
2300{
2301 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2302 rt61pci_txdone(rt2x00dev);
2303 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TXDONE);
2304}
2305
2306static void rt61pci_tbtt_tasklet(unsigned long data)
2307{
2308 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2309 rt2x00lib_beacondone(rt2x00dev);
2310 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_BEACON_DONE);
2311}
2312
2313static void rt61pci_rxdone_tasklet(unsigned long data)
2314{
2315 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2316 if (rt2x00pci_rxdone(rt2x00dev))
2317 rt2x00pci_rxdone(rt2x00dev);
2318 else
2319 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RXDONE);
2200} 2320}
2201 2321
2322static void rt61pci_autowake_tasklet(unsigned long data)
2323{
2324 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2325 rt61pci_wakeup(rt2x00dev);
2326 rt2x00pci_register_write(rt2x00dev,
2327 M2H_CMD_DONE_CSR, 0xffffffff);
2328 rt61pci_enable_mcu_interrupt(rt2x00dev, MCU_INT_MASK_CSR_TWAKEUP);
2329}
2202 2330
2203static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance) 2331static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2204{ 2332{
2205 struct rt2x00_dev *rt2x00dev = dev_instance; 2333 struct rt2x00_dev *rt2x00dev = dev_instance;
2206 u32 reg_mcu; 2334 u32 reg_mcu, mask_mcu;
2207 u32 reg; 2335 u32 reg, mask;
2208 2336
2209 /* 2337 /*
2210 * Get the interrupt sources & saved to local variable. 2338 * Get the interrupt sources & saved to local variable.
@@ -2222,14 +2350,46 @@ static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2222 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 2350 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2223 return IRQ_HANDLED; 2351 return IRQ_HANDLED;
2224 2352
2225 /* Store irqvalues for use in the interrupt thread. */ 2353 /*
2226 rt2x00dev->irqvalue[0] = reg; 2354 * Schedule tasklets for interrupt handling.
2227 rt2x00dev->irqvalue[1] = reg_mcu; 2355 */
2356 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2357 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
2358
2359 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2360 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
2361
2362 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE))
2363 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
2364
2365 if (rt2x00_get_field32(reg_mcu, MCU_INT_SOURCE_CSR_TWAKEUP))
2366 tasklet_schedule(&rt2x00dev->autowake_tasklet);
2367
2368 /*
2369 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
2370 * for interrupts and interrupt masks we can just use the value of
2371 * INT_SOURCE_CSR to create the interrupt mask.
2372 */
2373 mask = reg;
2374 mask_mcu = reg_mcu;
2375
2376 /*
2377 * Disable all interrupts for which a tasklet was scheduled right now,
2378 * the tasklet will reenable the appropriate interrupts.
2379 */
2380 spin_lock(&rt2x00dev->irqmask_lock);
2381
2382 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
2383 reg |= mask;
2384 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
2385
2386 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
2387 reg |= mask_mcu;
2388 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
2389
2390 spin_unlock(&rt2x00dev->irqmask_lock);
2228 2391
2229 /* Disable interrupts, will be enabled again in the interrupt thread. */ 2392 return IRQ_HANDLED;
2230 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
2231 STATE_RADIO_IRQ_OFF_ISR);
2232 return IRQ_WAKE_THREAD;
2233} 2393}
2234 2394
2235/* 2395/*
@@ -2377,7 +2537,7 @@ static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2377 * Determine number of antennas. 2537 * Determine number of antennas.
2378 */ 2538 */
2379 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2) 2539 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2380 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags); 2540 __set_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags);
2381 2541
2382 /* 2542 /*
2383 * Identify default antenna configuration. 2543 * Identify default antenna configuration.
@@ -2391,20 +2551,20 @@ static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2391 * Read the Frame type. 2551 * Read the Frame type.
2392 */ 2552 */
2393 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE)) 2553 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2394 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags); 2554 __set_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags);
2395 2555
2396 /* 2556 /*
2397 * Detect if this device has a hardware controlled radio. 2557 * Detect if this device has a hardware controlled radio.
2398 */ 2558 */
2399 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) 2559 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2400 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags); 2560 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
2401 2561
2402 /* 2562 /*
2403 * Read frequency offset and RF programming sequence. 2563 * Read frequency offset and RF programming sequence.
2404 */ 2564 */
2405 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); 2565 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2406 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ)) 2566 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2407 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags); 2567 __set_bit(CAPABILITY_RF_SEQUENCE, &rt2x00dev->cap_flags);
2408 2568
2409 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); 2569 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2410 2570
@@ -2414,9 +2574,9 @@ static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2414 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); 2574 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2415 2575
2416 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A)) 2576 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2417 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags); 2577 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
2418 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG)) 2578 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2419 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags); 2579 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
2420 2580
2421 /* 2581 /*
2422 * When working with a RF2529 chip without double antenna, 2582 * When working with a RF2529 chip without double antenna,
@@ -2424,7 +2584,7 @@ static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2424 * eeprom word. 2584 * eeprom word.
2425 */ 2585 */
2426 if (rt2x00_rf(rt2x00dev, RF2529) && 2586 if (rt2x00_rf(rt2x00dev, RF2529) &&
2427 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) { 2587 !test_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags)) {
2428 rt2x00dev->default_ant.rx = 2588 rt2x00dev->default_ant.rx =
2429 ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED); 2589 ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED);
2430 rt2x00dev->default_ant.tx = 2590 rt2x00dev->default_ant.tx =
@@ -2624,12 +2784,13 @@ static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2624 * As rt61 has a global fallback table we cannot specify 2784 * As rt61 has a global fallback table we cannot specify
2625 * more then one tx rate per frame but since the hw will 2785 * more then one tx rate per frame but since the hw will
2626 * try several rates (based on the fallback table) we should 2786 * try several rates (based on the fallback table) we should
2627 * still initialize max_rates to the maximum number of rates 2787 * initialize max_report_rates to the maximum number of rates
2628 * we are going to try. Otherwise mac80211 will truncate our 2788 * we are going to try. Otherwise mac80211 will truncate our
2629 * reported tx rates and the rc algortihm will end up with 2789 * reported tx rates and the rc algortihm will end up with
2630 * incorrect data. 2790 * incorrect data.
2631 */ 2791 */
2632 rt2x00dev->hw->max_rates = 7; 2792 rt2x00dev->hw->max_rates = 1;
2793 rt2x00dev->hw->max_report_rates = 7;
2633 rt2x00dev->hw->max_rate_tries = 1; 2794 rt2x00dev->hw->max_rate_tries = 1;
2634 2795
2635 /* 2796 /*
@@ -2638,7 +2799,7 @@ static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2638 spec->supported_bands = SUPPORT_BAND_2GHZ; 2799 spec->supported_bands = SUPPORT_BAND_2GHZ;
2639 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; 2800 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2640 2801
2641 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) { 2802 if (!test_bit(CAPABILITY_RF_SEQUENCE, &rt2x00dev->cap_flags)) {
2642 spec->num_channels = 14; 2803 spec->num_channels = 14;
2643 spec->channels = rf_vals_noseq; 2804 spec->channels = rf_vals_noseq;
2644 } else { 2805 } else {
@@ -2654,20 +2815,24 @@ static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2654 /* 2815 /*
2655 * Create channel information array 2816 * Create channel information array
2656 */ 2817 */
2657 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL); 2818 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
2658 if (!info) 2819 if (!info)
2659 return -ENOMEM; 2820 return -ENOMEM;
2660 2821
2661 spec->channels_info = info; 2822 spec->channels_info = info;
2662 2823
2663 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START); 2824 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2664 for (i = 0; i < 14; i++) 2825 for (i = 0; i < 14; i++) {
2665 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]); 2826 info[i].max_power = MAX_TXPOWER;
2827 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2828 }
2666 2829
2667 if (spec->num_channels > 14) { 2830 if (spec->num_channels > 14) {
2668 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START); 2831 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2669 for (i = 14; i < spec->num_channels; i++) 2832 for (i = 14; i < spec->num_channels; i++) {
2670 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]); 2833 info[i].max_power = MAX_TXPOWER;
2834 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2835 }
2671 } 2836 }
2672 2837
2673 return 0; 2838 return 0;
@@ -2704,16 +2869,16 @@ static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2704 * This device has multiple filters for control frames, 2869 * This device has multiple filters for control frames,
2705 * but has no a separate filter for PS Poll frames. 2870 * but has no a separate filter for PS Poll frames.
2706 */ 2871 */
2707 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags); 2872 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
2708 2873
2709 /* 2874 /*
2710 * This device requires firmware and DMA mapped skbs. 2875 * This device requires firmware and DMA mapped skbs.
2711 */ 2876 */
2712 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags); 2877 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
2713 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags); 2878 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
2714 if (!modparam_nohwcrypt) 2879 if (!modparam_nohwcrypt)
2715 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags); 2880 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
2716 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags); 2881 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
2717 2882
2718 /* 2883 /*
2719 * Set the rssi offset. 2884 * Set the rssi offset.
@@ -2753,7 +2918,7 @@ static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2753 if (queue_idx >= 4) 2918 if (queue_idx >= 4)
2754 return 0; 2919 return 0;
2755 2920
2756 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); 2921 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2757 2922
2758 /* Update WMM TXOP register */ 2923 /* Update WMM TXOP register */
2759 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2))); 2924 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
@@ -2813,11 +2978,18 @@ static const struct ieee80211_ops rt61pci_mac80211_ops = {
2813 .conf_tx = rt61pci_conf_tx, 2978 .conf_tx = rt61pci_conf_tx,
2814 .get_tsf = rt61pci_get_tsf, 2979 .get_tsf = rt61pci_get_tsf,
2815 .rfkill_poll = rt2x00mac_rfkill_poll, 2980 .rfkill_poll = rt2x00mac_rfkill_poll,
2981 .flush = rt2x00mac_flush,
2982 .set_antenna = rt2x00mac_set_antenna,
2983 .get_antenna = rt2x00mac_get_antenna,
2984 .get_ringparam = rt2x00mac_get_ringparam,
2816}; 2985};
2817 2986
2818static const struct rt2x00lib_ops rt61pci_rt2x00_ops = { 2987static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2819 .irq_handler = rt61pci_interrupt, 2988 .irq_handler = rt61pci_interrupt,
2820 .irq_handler_thread = rt61pci_interrupt_thread, 2989 .txstatus_tasklet = rt61pci_txstatus_tasklet,
2990 .tbtt_tasklet = rt61pci_tbtt_tasklet,
2991 .rxdone_tasklet = rt61pci_rxdone_tasklet,
2992 .autowake_tasklet = rt61pci_autowake_tasklet,
2821 .probe_hw = rt61pci_probe_hw, 2993 .probe_hw = rt61pci_probe_hw,
2822 .get_firmware_name = rt61pci_get_firmware_name, 2994 .get_firmware_name = rt61pci_get_firmware_name,
2823 .check_firmware = rt61pci_check_firmware, 2995 .check_firmware = rt61pci_check_firmware,
@@ -2831,10 +3003,13 @@ static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2831 .link_stats = rt61pci_link_stats, 3003 .link_stats = rt61pci_link_stats,
2832 .reset_tuner = rt61pci_reset_tuner, 3004 .reset_tuner = rt61pci_reset_tuner,
2833 .link_tuner = rt61pci_link_tuner, 3005 .link_tuner = rt61pci_link_tuner,
3006 .start_queue = rt61pci_start_queue,
3007 .kick_queue = rt61pci_kick_queue,
3008 .stop_queue = rt61pci_stop_queue,
3009 .flush_queue = rt2x00pci_flush_queue,
2834 .write_tx_desc = rt61pci_write_tx_desc, 3010 .write_tx_desc = rt61pci_write_tx_desc,
2835 .write_beacon = rt61pci_write_beacon, 3011 .write_beacon = rt61pci_write_beacon,
2836 .kick_tx_queue = rt61pci_kick_tx_queue, 3012 .clear_beacon = rt61pci_clear_beacon,
2837 .kill_tx_queue = rt61pci_kill_tx_queue,
2838 .fill_rxdone = rt61pci_fill_rxdone, 3013 .fill_rxdone = rt61pci_fill_rxdone,
2839 .config_shared_key = rt61pci_config_shared_key, 3014 .config_shared_key = rt61pci_config_shared_key,
2840 .config_pairwise_key = rt61pci_config_pairwise_key, 3015 .config_pairwise_key = rt61pci_config_pairwise_key,
@@ -2846,21 +3021,21 @@ static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2846}; 3021};
2847 3022
2848static const struct data_queue_desc rt61pci_queue_rx = { 3023static const struct data_queue_desc rt61pci_queue_rx = {
2849 .entry_num = RX_ENTRIES, 3024 .entry_num = 32,
2850 .data_size = DATA_FRAME_SIZE, 3025 .data_size = DATA_FRAME_SIZE,
2851 .desc_size = RXD_DESC_SIZE, 3026 .desc_size = RXD_DESC_SIZE,
2852 .priv_size = sizeof(struct queue_entry_priv_pci), 3027 .priv_size = sizeof(struct queue_entry_priv_pci),
2853}; 3028};
2854 3029
2855static const struct data_queue_desc rt61pci_queue_tx = { 3030static const struct data_queue_desc rt61pci_queue_tx = {
2856 .entry_num = TX_ENTRIES, 3031 .entry_num = 32,
2857 .data_size = DATA_FRAME_SIZE, 3032 .data_size = DATA_FRAME_SIZE,
2858 .desc_size = TXD_DESC_SIZE, 3033 .desc_size = TXD_DESC_SIZE,
2859 .priv_size = sizeof(struct queue_entry_priv_pci), 3034 .priv_size = sizeof(struct queue_entry_priv_pci),
2860}; 3035};
2861 3036
2862static const struct data_queue_desc rt61pci_queue_bcn = { 3037static const struct data_queue_desc rt61pci_queue_bcn = {
2863 .entry_num = 4 * BEACON_ENTRIES, 3038 .entry_num = 4,
2864 .data_size = 0, /* No DMA required for beacons */ 3039 .data_size = 0, /* No DMA required for beacons */
2865 .desc_size = TXINFO_SIZE, 3040 .desc_size = TXINFO_SIZE,
2866 .priv_size = sizeof(struct queue_entry_priv_pci), 3041 .priv_size = sizeof(struct queue_entry_priv_pci),
@@ -2889,11 +3064,11 @@ static const struct rt2x00_ops rt61pci_ops = {
2889 */ 3064 */
2890static DEFINE_PCI_DEVICE_TABLE(rt61pci_device_table) = { 3065static DEFINE_PCI_DEVICE_TABLE(rt61pci_device_table) = {
2891 /* RT2561s */ 3066 /* RT2561s */
2892 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) }, 3067 { PCI_DEVICE(0x1814, 0x0301) },
2893 /* RT2561 v2 */ 3068 /* RT2561 v2 */
2894 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) }, 3069 { PCI_DEVICE(0x1814, 0x0302) },
2895 /* RT2661 */ 3070 /* RT2661 */
2896 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) }, 3071 { PCI_DEVICE(0x1814, 0x0401) },
2897 { 0, } 3072 { 0, }
2898}; 3073};
2899 3074
@@ -2908,10 +3083,16 @@ MODULE_FIRMWARE(FIRMWARE_RT2561s);
2908MODULE_FIRMWARE(FIRMWARE_RT2661); 3083MODULE_FIRMWARE(FIRMWARE_RT2661);
2909MODULE_LICENSE("GPL"); 3084MODULE_LICENSE("GPL");
2910 3085
3086static int rt61pci_probe(struct pci_dev *pci_dev,
3087 const struct pci_device_id *id)
3088{
3089 return rt2x00pci_probe(pci_dev, &rt61pci_ops);
3090}
3091
2911static struct pci_driver rt61pci_driver = { 3092static struct pci_driver rt61pci_driver = {
2912 .name = KBUILD_MODNAME, 3093 .name = KBUILD_MODNAME,
2913 .id_table = rt61pci_device_table, 3094 .id_table = rt61pci_device_table,
2914 .probe = rt2x00pci_probe, 3095 .probe = rt61pci_probe,
2915 .remove = __devexit_p(rt2x00pci_remove), 3096 .remove = __devexit_p(rt2x00pci_remove),
2916 .suspend = rt2x00pci_suspend, 3097 .suspend = rt2x00pci_suspend,
2917 .resume = rt2x00pci_resume, 3098 .resume = rt2x00pci_resume,
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-09 13:52:48 -0400