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-rw-r--r--arch/arm/boot/dts/Makefile109
-rw-r--r--arch/arm/boot/dts/am335x-bone.dts58
-rw-r--r--arch/arm/boot/dts/am335x-evm.dts126
-rw-r--r--arch/arm/boot/dts/am335x-evmsk.dts250
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi203
-rw-r--r--arch/arm/boot/dts/animeo_ip.dts178
-rw-r--r--arch/arm/boot/dts/armada-370-db.dts25
-rw-r--r--arch/arm/boot/dts/armada-370-mirabox.dts56
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi69
-rw-r--r--arch/arm/boot/dts/armada-370.dtsi57
-rw-r--r--arch/arm/boot/dts/armada-xp-db.dts44
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78230.dtsi19
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78260.dtsi27
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78460.dtsi42
-rw-r--r--arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts125
-rw-r--r--arch/arm/boot/dts/armada-xp.dtsi89
-rw-r--r--arch/arm/boot/dts/at91rm9200.dtsi349
-rw-r--r--arch/arm/boot/dts/at91rm9200ek.dts79
-rw-r--r--arch/arm/boot/dts/at91sam9260.dtsi327
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi357
-rw-r--r--arch/arm/boot/dts/at91sam9263ek.dts29
-rw-r--r--arch/arm/boot/dts/at91sam9g15.dtsi28
-rw-r--r--arch/arm/boot/dts/at91sam9g15ek.dts16
-rw-r--r--arch/arm/boot/dts/at91sam9g20ek_2mmc.dts26
-rw-r--r--arch/arm/boot/dts/at91sam9g20ek_common.dtsi62
-rw-r--r--arch/arm/boot/dts/at91sam9g25.dtsi28
-rw-r--r--arch/arm/boot/dts/at91sam9g25ek.dts49
-rw-r--r--arch/arm/boot/dts/at91sam9g35.dtsi28
-rw-r--r--arch/arm/boot/dts/at91sam9g35ek.dts16
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi359
-rw-r--r--arch/arm/boot/dts/at91sam9m10g45ek.dts48
-rw-r--r--arch/arm/boot/dts/at91sam9n12.dtsi251
-rw-r--r--arch/arm/boot/dts/at91sam9n12ek.dts22
-rw-r--r--arch/arm/boot/dts/at91sam9x25.dtsi49
-rw-r--r--arch/arm/boot/dts/at91sam9x25ek.dts16
-rw-r--r--arch/arm/boot/dts/at91sam9x35.dtsi28
-rw-r--r--arch/arm/boot/dts/at91sam9x35ek.dts16
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi294
-rw-r--r--arch/arm/boot/dts/at91sam9x5ek.dtsi101
-rw-r--r--arch/arm/boot/dts/bcm11351-brt.dts30
-rw-r--r--arch/arm/boot/dts/bcm11351.dtsi50
-rw-r--r--arch/arm/boot/dts/bcm2835-rpi-b.dts15
-rw-r--r--arch/arm/boot/dts/bcm2835.dtsi28
-rw-r--r--arch/arm/boot/dts/ccu9540.dts72
-rw-r--r--arch/arm/boot/dts/cros5250-common.dtsi184
-rw-r--r--arch/arm/boot/dts/da850-enbw-cmc.dts30
-rw-r--r--arch/arm/boot/dts/da850-evm.dts28
-rw-r--r--arch/arm/boot/dts/da850.dtsi60
-rw-r--r--arch/arm/boot/dts/dbx5x0.dtsi102
-rw-r--r--arch/arm/boot/dts/dove-cubox.dts10
-rw-r--r--arch/arm/boot/dts/dove.dtsi82
-rw-r--r--arch/arm/boot/dts/ecx-2000.dts108
-rw-r--r--arch/arm/boot/dts/ecx-common.dtsi237
-rw-r--r--arch/arm/boot/dts/evk-pro3.dts12
-rw-r--r--arch/arm/boot/dts/exynos4.dtsi60
-rw-r--r--arch/arm/boot/dts/exynos4210-origen.dts70
-rw-r--r--arch/arm/boot/dts/exynos4210-pinctrl.dtsi334
-rw-r--r--arch/arm/boot/dts/exynos4210-smdkv310.dts18
-rw-r--r--arch/arm/boot/dts/exynos4210-trats.dts87
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi249
-rw-r--r--arch/arm/boot/dts/exynos4212.dtsi28
-rw-r--r--arch/arm/boot/dts/exynos4412-smdk4412.dts45
-rw-r--r--arch/arm/boot/dts/exynos4412.dtsi28
-rw-r--r--arch/arm/boot/dts/exynos4x12-pinctrl.dtsi965
-rw-r--r--arch/arm/boot/dts/exynos4x12.dtsi69
-rw-r--r--arch/arm/boot/dts/exynos5250-smdk5250.dts56
-rw-r--r--arch/arm/boot/dts/exynos5250-snow.dts43
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi87
-rw-r--r--arch/arm/boot/dts/exynos5440-ssdk5440.dts46
-rw-r--r--arch/arm/boot/dts/exynos5440.dtsi159
-rw-r--r--arch/arm/boot/dts/highbank.dts232
-rw-r--r--arch/arm/boot/dts/href.dtsi273
-rw-r--r--arch/arm/boot/dts/hrefprev60.dts48
-rw-r--r--arch/arm/boot/dts/hrefv60plus.dts217
-rw-r--r--arch/arm/boot/dts/imx23-olinuxino.dts25
-rw-r--r--arch/arm/boot/dts/imx23.dtsi13
-rw-r--r--arch/arm/boot/dts/imx25-karo-tx25.dts44
-rw-r--r--arch/arm/boot/dts/imx25.dtsi515
-rw-r--r--arch/arm/boot/dts/imx27-3ds.dts12
-rw-r--r--arch/arm/boot/dts/imx27-apf27.dts89
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycore.dts13
-rw-r--r--arch/arm/boot/dts/imx27.dtsi20
-rw-r--r--arch/arm/boot/dts/imx28-apf28.dts85
-rw-r--r--arch/arm/boot/dts/imx28-apf28dev.dts154
-rw-r--r--arch/arm/boot/dts/imx28-cfa10036.dts46
-rw-r--r--arch/arm/boot/dts/imx28-cfa10049.dts57
-rw-r--r--arch/arm/boot/dts/imx28-evk.dts13
-rw-r--r--arch/arm/boot/dts/imx28-sps1.dts169
-rw-r--r--arch/arm/boot/dts/imx28.dtsi36
-rw-r--r--arch/arm/boot/dts/imx31-bug.dts2
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts16
-rw-r--r--arch/arm/boot/dts/imx51.dtsi171
-rw-r--r--arch/arm/boot/dts/imx53-qsb.dts62
-rw-r--r--arch/arm/boot/dts/imx53.dtsi171
-rw-r--r--arch/arm/boot/dts/imx6q-sabreauto.dts64
-rw-r--r--arch/arm/boot/dts/imx6q-sabresd.dts18
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi159
-rw-r--r--arch/arm/boot/dts/integratorap.dts5
-rw-r--r--arch/arm/boot/dts/integratorcp.dts5
-rw-r--r--arch/arm/boot/dts/kirkwood-6281.dtsi44
-rw-r--r--arch/arm/boot/dts/kirkwood-6282.dtsi46
-rw-r--r--arch/arm/boot/dts/kirkwood-98dx4122.dtsi31
-rw-r--r--arch/arm/boot/dts/kirkwood-dnskw.dtsi140
-rw-r--r--arch/arm/boot/dts/kirkwood-dockstar.dts37
-rw-r--r--arch/arm/boot/dts/kirkwood-dreamplug.dts21
-rw-r--r--arch/arm/boot/dts/kirkwood-goflexnet.dts73
-rw-r--r--arch/arm/boot/dts/kirkwood-ib62x0.dts40
-rw-r--r--arch/arm/boot/dts/kirkwood-iconnect.dts51
-rw-r--r--arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts89
-rw-r--r--arch/arm/boot/dts/kirkwood-is2.dts30
-rw-r--r--arch/arm/boot/dts/kirkwood-km_kirkwood.dts17
-rw-r--r--arch/arm/boot/dts/kirkwood-lsxl.dtsi106
-rw-r--r--arch/arm/boot/dts/kirkwood-mplcec4.dts178
-rw-r--r--arch/arm/boot/dts/kirkwood-ns2-common.dtsi63
-rw-r--r--arch/arm/boot/dts/kirkwood-ns2.dts30
-rw-r--r--arch/arm/boot/dts/kirkwood-ns2lite.dts30
-rw-r--r--arch/arm/boot/dts/kirkwood-ns2max.dts49
-rw-r--r--arch/arm/boot/dts/kirkwood-ns2mini.dts49
-rw-r--r--arch/arm/boot/dts/kirkwood-nsa310.dts144
-rw-r--r--arch/arm/boot/dts/kirkwood-openblocks_a6.dts98
-rw-r--r--arch/arm/boot/dts/kirkwood-topkick.dts102
-rw-r--r--arch/arm/boot/dts/kirkwood-ts219-6281.dts31
-rw-r--r--arch/arm/boot/dts/kirkwood-ts219-6282.dts31
-rw-r--r--arch/arm/boot/dts/kirkwood.dtsi80
-rw-r--r--arch/arm/boot/dts/lpc32xx.dtsi7
-rw-r--r--arch/arm/boot/dts/omap2.dtsi86
-rw-r--r--arch/arm/boot/dts/omap2420-h4.dts2
-rw-r--r--arch/arm/boot/dts/omap2420.dtsi16
-rw-r--r--arch/arm/boot/dts/omap2430.dtsi19
-rw-r--r--arch/arm/boot/dts/omap3-beagle-xm.dts6
-rw-r--r--arch/arm/boot/dts/omap3-beagle.dts67
-rw-r--r--arch/arm/boot/dts/omap3.dtsi107
-rw-r--r--arch/arm/boot/dts/omap4-panda-a4.dts17
-rw-r--r--arch/arm/boot/dts/omap4-panda-es.dts (renamed from arch/arm/boot/dts/omap4-pandaES.dts)9
-rw-r--r--arch/arm/boot/dts/omap4-panda.dts22
-rw-r--r--arch/arm/boot/dts/omap4-sdp-es23plus.dts17
-rw-r--r--arch/arm/boot/dts/omap4-sdp.dts22
-rw-r--r--arch/arm/boot/dts/omap4-var-som.dts (renamed from arch/arm/boot/dts/omap4-var_som.dts)0
-rw-r--r--arch/arm/boot/dts/omap4.dtsi105
-rw-r--r--arch/arm/boot/dts/omap5-evm.dts13
-rw-r--r--arch/arm/boot/dts/omap5.dtsi178
-rw-r--r--arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts55
-rw-r--r--arch/arm/boot/dts/orion5x.dtsi98
-rw-r--r--arch/arm/boot/dts/pm9g45.dts165
-rw-r--r--arch/arm/boot/dts/samsung_k3pe0e000b.dtsi67
-rw-r--r--arch/arm/boot/dts/sh7372-mackerel.dts (renamed from arch/arm/boot/dts/sh7377.dtsi)13
-rw-r--r--arch/arm/boot/dts/snowball.dts171
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi10
-rw-r--r--arch/arm/boot/dts/spear1310-evb.dts165
-rw-r--r--arch/arm/boot/dts/spear1310.dtsi55
-rw-r--r--arch/arm/boot/dts/spear1340-evb.dts257
-rw-r--r--arch/arm/boot/dts/spear1340.dtsi87
-rw-r--r--arch/arm/boot/dts/spear13xx.dtsi82
-rw-r--r--arch/arm/boot/dts/spear300-evb.dts20
-rw-r--r--arch/arm/boot/dts/spear300.dtsi22
-rw-r--r--arch/arm/boot/dts/spear310-evb.dts30
-rw-r--r--arch/arm/boot/dts/spear310.dtsi48
-rw-r--r--arch/arm/boot/dts/spear320-evb.dts39
-rw-r--r--arch/arm/boot/dts/spear320-hmi.dts305
-rw-r--r--arch/arm/boot/dts/spear320.dtsi70
-rw-r--r--arch/arm/boot/dts/spear3xx.dtsi5
-rw-r--r--arch/arm/boot/dts/spear600-evb.dts46
-rw-r--r--arch/arm/boot/dts/spear600.dtsi24
-rw-r--r--arch/arm/boot/dts/stuib.dtsi78
-rw-r--r--arch/arm/boot/dts/sun4i-a10-cubieboard.dts38
-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi19
-rw-r--r--arch/arm/boot/dts/sun5i-a13-olinuxino.dts30
-rw-r--r--arch/arm/boot/dts/sun5i-a13.dtsi20
-rw-r--r--arch/arm/boot/dts/sunxi.dtsi80
-rw-r--r--arch/arm/boot/dts/tegra20-harmony.dts84
-rw-r--r--arch/arm/boot/dts/tegra20-paz00.dts59
-rw-r--r--arch/arm/boot/dts/tegra20-plutux.dts6
-rw-r--r--arch/arm/boot/dts/tegra20-seaboard.dts69
-rw-r--r--arch/arm/boot/dts/tegra20-tamonten.dtsi147
-rw-r--r--arch/arm/boot/dts/tegra20-tec.dts9
-rw-r--r--arch/arm/boot/dts/tegra20-trimslice.dts54
-rw-r--r--arch/arm/boot/dts/tegra20-ventana.dts149
-rw-r--r--arch/arm/boot/dts/tegra20-whistler.dts136
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi167
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu-a02.dts6
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu-a04.dts6
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dtsi84
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi183
-rw-r--r--arch/arm/boot/dts/twl4030.dtsi31
-rw-r--r--arch/arm/boot/dts/twl6030.dtsi5
-rw-r--r--arch/arm/boot/dts/u9540.dts72
-rw-r--r--arch/arm/boot/dts/vexpress-v2m-rs1.dtsi146
-rw-r--r--arch/arm/boot/dts/vexpress-v2m.dtsi146
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts121
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts186
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca5s.dts84
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca9.dts136
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi166
-rw-r--r--arch/arm/boot/dts/zynq-ep107.dts52
-rw-r--r--arch/arm/boot/dts/zynq-zc702.dts44
195 files changed, 15237 insertions, 1694 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f37cf9fa5fa0..5ebb44fe826a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1,30 +1,53 @@
1ifeq ($(CONFIG_OF),y) 1ifeq ($(CONFIG_OF),y)
2 2
3dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb \ 3# Keep at91 dtb files sorted alphabetically for each SoC
4 at91sam9263ek.dtb \ 4# rm9200
5 at91sam9g20ek_2mmc.dtb \ 5dtb-$(CONFIG_ARCH_AT91) += at91rm9200ek.dtb
6 at91sam9g20ek.dtb \ 6# sam9260
7 at91sam9g25ek.dtb \ 7dtb-$(CONFIG_ARCH_AT91) += animeo_ip.dtb
8 at91sam9m10g45ek.dtb \ 8dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb
9 at91sam9n12ek.dtb \ 9dtb-$(CONFIG_ARCH_AT91) += ethernut5.dtb
10 ethernut5.dtb \ 10dtb-$(CONFIG_ARCH_AT91) += evk-pro3.dtb
11 evk-pro3.dtb \ 11dtb-$(CONFIG_ARCH_AT91) += tny_a9260.dtb
12 kizbox.dtb \ 12dtb-$(CONFIG_ARCH_AT91) += usb_a9260.dtb
13 tny_a9260.dtb \ 13# sam9263
14 tny_a9263.dtb \ 14dtb-$(CONFIG_ARCH_AT91) += at91sam9263ek.dtb
15 tny_a9g20.dtb \ 15dtb-$(CONFIG_ARCH_AT91) += tny_a9263.dtb
16 usb_a9260.dtb \ 16dtb-$(CONFIG_ARCH_AT91) += usb_a9263.dtb
17 usb_a9263.dtb \ 17# sam9g20
18 usb_a9g20.dtb 18dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek.dtb
19dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek_2mmc.dtb
20dtb-$(CONFIG_ARCH_AT91) += kizbox.dtb
21dtb-$(CONFIG_ARCH_AT91) += tny_a9g20.dtb
22dtb-$(CONFIG_ARCH_AT91) += usb_a9g20.dtb
23# sam9g45
24dtb-$(CONFIG_ARCH_AT91) += at91sam9m10g45ek.dtb
25dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb
26# sam9n12
27dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb
28# sam9x5
29dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb
30dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb
31dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb
32dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb
33dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb
34
19dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb 35dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
36dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb
37dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
38 da850-evm.dtb
20dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \ 39dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
21 dove-cubox.dtb \ 40 dove-cubox.dtb \
22 dove-dove-db.dtb 41 dove-dove-db.dtb
23dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ 42dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
24 exynos4210-smdkv310.dtb \ 43 exynos4210-smdkv310.dtb \
25 exynos4210-trats.dtb \ 44 exynos4210-trats.dtb \
26 exynos5250-smdk5250.dtb 45 exynos4412-smdk4412.dtb \
27dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb 46 exynos5250-smdk5250.dtb \
47 exynos5250-snow.dtb \
48 exynos5440-ssdk5440.dtb
49dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
50 ecx-2000.dtb
28dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \ 51dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
29 integratorcp.dtb 52 integratorcp.dtb
30dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb 53dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
@@ -36,54 +59,80 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
36 kirkwood-ib62x0.dtb \ 59 kirkwood-ib62x0.dtb \
37 kirkwood-iconnect.dtb \ 60 kirkwood-iconnect.dtb \
38 kirkwood-iomega_ix2_200.dtb \ 61 kirkwood-iomega_ix2_200.dtb \
62 kirkwood-is2.dtb \
39 kirkwood-km_kirkwood.dtb \ 63 kirkwood-km_kirkwood.dtb \
40 kirkwood-lschlv2.dtb \ 64 kirkwood-lschlv2.dtb \
41 kirkwood-lsxhl.dtb \ 65 kirkwood-lsxhl.dtb \
66 kirkwood-mplcec4.dtb \
67 kirkwood-ns2.dtb \
68 kirkwood-ns2lite.dtb \
69 kirkwood-ns2max.dtb \
70 kirkwood-ns2mini.dtb \
71 kirkwood-nsa310.dtb \
72 kirkwood-topkick.dtb \
42 kirkwood-ts219-6281.dtb \ 73 kirkwood-ts219-6281.dtb \
43 kirkwood-ts219-6282.dtb 74 kirkwood-ts219-6282.dtb \
75 kirkwood-openblocks_a6.dtb
44dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \ 76dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \
45 msm8960-cdp.dtb 77 msm8960-cdp.dtb
46dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ 78dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
47 armada-xp-db.dtb 79 armada-370-mirabox.dtb \
80 armada-xp-db.dtb \
81 armada-xp-openblocks-ax3-4.dtb
48dtb-$(CONFIG_ARCH_MXC) += imx51-babbage.dtb \ 82dtb-$(CONFIG_ARCH_MXC) += imx51-babbage.dtb \
49 imx53-ard.dtb \ 83 imx53-ard.dtb \
50 imx53-evk.dtb \ 84 imx53-evk.dtb \
51 imx53-qsb.dtb \ 85 imx53-qsb.dtb \
52 imx53-smd.dtb \ 86 imx53-smd.dtb \
53 imx6q-arm2.dtb \ 87 imx6q-arm2.dtb \
88 imx6q-sabreauto.dtb \
54 imx6q-sabrelite.dtb \ 89 imx6q-sabrelite.dtb \
55 imx6q-sabresd.dtb 90 imx6q-sabresd.dtb
56dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ 91dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
57 imx23-olinuxino.dtb \ 92 imx23-olinuxino.dtb \
58 imx23-stmp378x_devb.dtb \ 93 imx23-stmp378x_devb.dtb \
94 imx28-apf28.dtb \
95 imx28-apf28dev.dtb \
59 imx28-apx4devkit.dtb \ 96 imx28-apx4devkit.dtb \
60 imx28-cfa10036.dtb \ 97 imx28-cfa10036.dtb \
61 imx28-cfa10049.dtb \ 98 imx28-cfa10049.dtb \
62 imx28-evk.dtb \ 99 imx28-evk.dtb \
63 imx28-m28evk.dtb \ 100 imx28-m28evk.dtb \
101 imx28-sps1.dtb \
64 imx28-tx28.dtb 102 imx28-tx28.dtb
65dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ 103dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
104 omap3-beagle.dtb \
66 omap3-beagle-xm.dtb \ 105 omap3-beagle-xm.dtb \
67 omap3-evm.dtb \ 106 omap3-evm.dtb \
68 omap3-tobi.dtb \ 107 omap3-tobi.dtb \
69 omap4-panda.dtb \ 108 omap4-panda.dtb \
70 omap4-pandaES.dtb \ 109 omap4-panda-a4.dtb \
71 omap4-var_som.dtb \ 110 omap4-panda-es.dtb \
111 omap4-var-som.dtb \
72 omap4-sdp.dtb \ 112 omap4-sdp.dtb \
73 omap5-evm.dtb \ 113 omap5-evm.dtb \
74 am335x-evm.dtb \ 114 am335x-evm.dtb \
115 am335x-evmsk.dtb \
75 am335x-bone.dtb 116 am335x-bone.dtb
117dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
76dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb 118dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
77dtb-$(CONFIG_ARCH_U8500) += snowball.dtb 119dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
120 hrefprev60.dtb \
121 hrefv60plus.dtb \
122 ccu9540.dtb
78dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ 123dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
79 r8a7740-armadillo800eva.dtb \ 124 r8a7740-armadillo800eva.dtb \
80 sh73a0-kzm9g.dtb 125 sh73a0-kzm9g.dtb \
126 sh7372-mackerel.dtb
81dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \ 127dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
82 spear1340-evb.dtb 128 spear1340-evb.dtb
83dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \ 129dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
84 spear310-evb.dtb \ 130 spear310-evb.dtb \
85 spear320-evb.dtb 131 spear320-evb.dtb \
132 spear320-hmi.dtb
86dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb 133dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
134dtb-$(CONFIG_ARCH_SUNXI) += sun4i-a10-cubieboard.dtb \
135 sun5i-a13-olinuxino.dtb
87dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ 136dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
88 tegra20-medcom-wide.dtb \ 137 tegra20-medcom-wide.dtb \
89 tegra20-paz00.dtb \ 138 tegra20-paz00.dtb \
@@ -103,5 +152,15 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
103dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \ 152dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
104 wm8505-ref.dtb \ 153 wm8505-ref.dtb \
105 wm8650-mid.dtb 154 wm8650-mid.dtb
155dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb
106 156
157targets += dtbs
158targets += $(dtb-y)
107endif 159endif
160
161# *.dtb used to be generated in the directory above. Clean out the
162# old build results so people don't accidentally use them.
163dtbs: $(addprefix $(obj)/, $(dtb-y))
164 $(Q)rm -f $(obj)/../*.dtb
165
166clean-files := *.dtb
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index c634f87e230e..11b240c5d323 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -13,11 +13,31 @@
13 model = "TI AM335x BeagleBone"; 13 model = "TI AM335x BeagleBone";
14 compatible = "ti,am335x-bone", "ti,am33xx"; 14 compatible = "ti,am335x-bone", "ti,am33xx";
15 15
16 cpus {
17 cpu@0 {
18 cpu0-supply = <&dcdc2_reg>;
19 };
20 };
21
16 memory { 22 memory {
17 device_type = "memory"; 23 device_type = "memory";
18 reg = <0x80000000 0x10000000>; /* 256 MB */ 24 reg = <0x80000000 0x10000000>; /* 256 MB */
19 }; 25 };
20 26
27 am33xx_pinmux: pinmux@44e10800 {
28 pinctrl-names = "default";
29 pinctrl-0 = <&user_leds_s0>;
30
31 user_leds_s0: user_leds_s0 {
32 pinctrl-single,pins = <
33 0x54 0x7 /* gpmc_a5.gpio1_21, OUTPUT | MODE7 */
34 0x58 0x17 /* gpmc_a6.gpio1_22, OUTPUT_PULLUP | MODE7 */
35 0x5c 0x7 /* gpmc_a7.gpio1_23, OUTPUT | MODE7 */
36 0x60 0x17 /* gpmc_a8.gpio1_24, OUTPUT_PULLUP | MODE7 */
37 >;
38 };
39 };
40
21 ocp { 41 ocp {
22 uart1: serial@44e09000 { 42 uart1: serial@44e09000 {
23 status = "okay"; 43 status = "okay";
@@ -33,6 +53,36 @@
33 53
34 }; 54 };
35 }; 55 };
56
57 leds {
58 compatible = "gpio-leds";
59
60 led@2 {
61 label = "beaglebone:green:heartbeat";
62 gpios = <&gpio2 21 0>;
63 linux,default-trigger = "heartbeat";
64 default-state = "off";
65 };
66
67 led@3 {
68 label = "beaglebone:green:mmc0";
69 gpios = <&gpio2 22 0>;
70 linux,default-trigger = "mmc0";
71 default-state = "off";
72 };
73
74 led@4 {
75 label = "beaglebone:green:usr2";
76 gpios = <&gpio2 23 0>;
77 default-state = "off";
78 };
79
80 led@5 {
81 label = "beaglebone:green:usr3";
82 gpios = <&gpio2 24 0>;
83 default-state = "off";
84 };
85 };
36}; 86};
37 87
38/include/ "tps65217.dtsi" 88/include/ "tps65217.dtsi"
@@ -78,3 +128,11 @@
78 }; 128 };
79 }; 129 };
80}; 130};
131
132&cpsw_emac0 {
133 phy_id = <&davinci_mdio>, <0>;
134};
135
136&cpsw_emac1 {
137 phy_id = <&davinci_mdio>, <1>;
138};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 185d6325a458..d6496440fcea 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -13,11 +13,39 @@
13 model = "TI AM335x EVM"; 13 model = "TI AM335x EVM";
14 compatible = "ti,am335x-evm", "ti,am33xx"; 14 compatible = "ti,am335x-evm", "ti,am33xx";
15 15
16 cpus {
17 cpu@0 {
18 cpu0-supply = <&vdd1_reg>;
19 };
20 };
21
16 memory { 22 memory {
17 device_type = "memory"; 23 device_type = "memory";
18 reg = <0x80000000 0x10000000>; /* 256 MB */ 24 reg = <0x80000000 0x10000000>; /* 256 MB */
19 }; 25 };
20 26
27 am33xx_pinmux: pinmux@44e10800 {
28 pinctrl-names = "default";
29 pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0>;
30
31 matrix_keypad_s0: matrix_keypad_s0 {
32 pinctrl-single,pins = <
33 0x54 0x7 /* gpmc_a5.gpio1_21, OUTPUT | MODE7 */
34 0x58 0x7 /* gpmc_a6.gpio1_22, OUTPUT | MODE7 */
35 0x64 0x27 /* gpmc_a9.gpio1_25, INPUT | MODE7 */
36 0x68 0x27 /* gpmc_a10.gpio1_26, INPUT | MODE7 */
37 0x6c 0x27 /* gpmc_a11.gpio1_27, INPUT | MODE7 */
38 >;
39 };
40
41 volume_keys_s0: volume_keys_s0 {
42 pinctrl-single,pins = <
43 0x150 0x27 /* spi0_sclk.gpio0_2, INPUT | MODE7 */
44 0x154 0x27 /* spi0_d0.gpio0_3, INPUT | MODE7 */
45 >;
46 };
47 };
48
21 ocp { 49 ocp {
22 uart1: serial@44e09000 { 50 uart1: serial@44e09000 {
23 status = "okay"; 51 status = "okay";
@@ -31,6 +59,49 @@
31 reg = <0x2d>; 59 reg = <0x2d>;
32 }; 60 };
33 }; 61 };
62
63 i2c2: i2c@4802a000 {
64 status = "okay";
65 clock-frequency = <100000>;
66
67 lis331dlh: lis331dlh@18 {
68 compatible = "st,lis331dlh", "st,lis3lv02d";
69 reg = <0x18>;
70 Vdd-supply = <&lis3_reg>;
71 Vdd_IO-supply = <&lis3_reg>;
72
73 st,click-single-x;
74 st,click-single-y;
75 st,click-single-z;
76 st,click-thresh-x = <10>;
77 st,click-thresh-y = <10>;
78 st,click-thresh-z = <10>;
79 st,irq1-click;
80 st,irq2-click;
81 st,wakeup-x-lo;
82 st,wakeup-x-hi;
83 st,wakeup-y-lo;
84 st,wakeup-y-hi;
85 st,wakeup-z-lo;
86 st,wakeup-z-hi;
87 st,min-limit-x = <120>;
88 st,min-limit-y = <120>;
89 st,min-limit-z = <140>;
90 st,max-limit-x = <550>;
91 st,max-limit-y = <550>;
92 st,max-limit-z = <750>;
93 };
94
95 tsl2550: tsl2550@39 {
96 compatible = "taos,tsl2550";
97 reg = <0x39>;
98 };
99
100 tmp275: tmp275@48 {
101 compatible = "ti,tmp275";
102 reg = <0x48>;
103 };
104 };
34 }; 105 };
35 106
36 vbat: fixedregulator@0 { 107 vbat: fixedregulator@0 {
@@ -40,6 +111,53 @@
40 regulator-max-microvolt = <5000000>; 111 regulator-max-microvolt = <5000000>;
41 regulator-boot-on; 112 regulator-boot-on;
42 }; 113 };
114
115 lis3_reg: fixedregulator@1 {
116 compatible = "regulator-fixed";
117 regulator-name = "lis3_reg";
118 regulator-boot-on;
119 };
120
121 matrix_keypad: matrix_keypad@0 {
122 compatible = "gpio-matrix-keypad";
123 debounce-delay-ms = <5>;
124 col-scan-delay-us = <2>;
125
126 row-gpios = <&gpio2 25 0 /* Bank1, pin25 */
127 &gpio2 26 0 /* Bank1, pin26 */
128 &gpio2 27 0>; /* Bank1, pin27 */
129
130 col-gpios = <&gpio2 21 0 /* Bank1, pin21 */
131 &gpio2 22 0>; /* Bank1, pin22 */
132
133 linux,keymap = <0x0000008b /* MENU */
134 0x0100009e /* BACK */
135 0x02000069 /* LEFT */
136 0x0001006a /* RIGHT */
137 0x0101001c /* ENTER */
138 0x0201006c>; /* DOWN */
139 };
140
141 gpio_keys: volume_keys@0 {
142 compatible = "gpio-keys";
143 #address-cells = <1>;
144 #size-cells = <0>;
145 autorepeat;
146
147 switch@9 {
148 label = "volume-up";
149 linux,code = <115>;
150 gpios = <&gpio1 2 1>;
151 gpio-key,wakeup;
152 };
153
154 switch@10 {
155 label = "volume-down";
156 linux,code = <114>;
157 gpios = <&gpio1 3 1>;
158 gpio-key,wakeup;
159 };
160 };
43}; 161};
44 162
45/include/ "tps65910.dtsi" 163/include/ "tps65910.dtsi"
@@ -118,3 +236,11 @@
118 }; 236 };
119 }; 237 };
120}; 238};
239
240&cpsw_emac0 {
241 phy_id = <&davinci_mdio>, <0>;
242};
243
244&cpsw_emac1 {
245 phy_id = <&davinci_mdio>, <1>;
246};
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
new file mode 100644
index 000000000000..f5a6162a4ff2
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -0,0 +1,250 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * AM335x Starter Kit
11 * http://www.ti.com/tool/tmdssk3358
12 */
13
14/dts-v1/;
15
16/include/ "am33xx.dtsi"
17
18/ {
19 model = "TI AM335x EVM-SK";
20 compatible = "ti,am335x-evmsk", "ti,am33xx";
21
22 cpus {
23 cpu@0 {
24 cpu0-supply = <&vdd1_reg>;
25 };
26 };
27
28 memory {
29 device_type = "memory";
30 reg = <0x80000000 0x10000000>; /* 256 MB */
31 };
32
33 am33xx_pinmux: pinmux@44e10800 {
34 pinctrl-names = "default";
35 pinctrl-0 = <&user_leds_s0 &gpio_keys_s0>;
36
37 user_leds_s0: user_leds_s0 {
38 pinctrl-single,pins = <
39 0x10 0x7 /* gpmc_ad4.gpio1_4, OUTPUT | MODE7 */
40 0x14 0x7 /* gpmc_ad5.gpio1_5, OUTPUT | MODE7 */
41 0x18 0x7 /* gpmc_ad6.gpio1_6, OUTPUT | MODE7 */
42 0x1c 0x7 /* gpmc_ad7.gpio1_7, OUTPUT | MODE7 */
43 >;
44 };
45
46 gpio_keys_s0: gpio_keys_s0 {
47 pinctrl-single,pins = <
48 0x94 0x27 /* gpmc_oen_ren.gpio2_3, INPUT | MODE7 */
49 0x90 0x27 /* gpmc_advn_ale.gpio2_2, INPUT | MODE7 */
50 0x70 0x27 /* gpmc_wait0.gpio0_30, INPUT | MODE7 */
51 0x9c 0x27 /* gpmc_ben0_cle.gpio2_5, INPUT | MODE7 */
52 >;
53 };
54 };
55
56 ocp {
57 uart1: serial@44e09000 {
58 status = "okay";
59 };
60
61 i2c1: i2c@44e0b000 {
62 status = "okay";
63 clock-frequency = <400000>;
64
65 tps: tps@2d {
66 reg = <0x2d>;
67 };
68
69 lis331dlh: lis331dlh@18 {
70 compatible = "st,lis331dlh", "st,lis3lv02d";
71 reg = <0x18>;
72 Vdd-supply = <&lis3_reg>;
73 Vdd_IO-supply = <&lis3_reg>;
74
75 st,click-single-x;
76 st,click-single-y;
77 st,click-single-z;
78 st,click-thresh-x = <10>;
79 st,click-thresh-y = <10>;
80 st,click-thresh-z = <10>;
81 st,irq1-click;
82 st,irq2-click;
83 st,wakeup-x-lo;
84 st,wakeup-x-hi;
85 st,wakeup-y-lo;
86 st,wakeup-y-hi;
87 st,wakeup-z-lo;
88 st,wakeup-z-hi;
89 st,min-limit-x = <120>;
90 st,min-limit-y = <120>;
91 st,min-limit-z = <140>;
92 st,max-limit-x = <550>;
93 st,max-limit-y = <550>;
94 st,max-limit-z = <750>;
95 };
96 };
97 };
98
99 vbat: fixedregulator@0 {
100 compatible = "regulator-fixed";
101 regulator-name = "vbat";
102 regulator-min-microvolt = <5000000>;
103 regulator-max-microvolt = <5000000>;
104 regulator-boot-on;
105 };
106
107 lis3_reg: fixedregulator@1 {
108 compatible = "regulator-fixed";
109 regulator-name = "lis3_reg";
110 regulator-boot-on;
111 };
112
113 leds {
114 compatible = "gpio-leds";
115
116 led@1 {
117 label = "evmsk:green:usr0";
118 gpios = <&gpio2 4 0>;
119 default-state = "off";
120 };
121
122 led@2 {
123 label = "evmsk:green:usr1";
124 gpios = <&gpio2 5 0>;
125 default-state = "off";
126 };
127
128 led@3 {
129 label = "evmsk:green:mmc0";
130 gpios = <&gpio2 6 0>;
131 linux,default-trigger = "mmc0";
132 default-state = "off";
133 };
134
135 led@4 {
136 label = "evmsk:green:heartbeat";
137 gpios = <&gpio2 7 0>;
138 linux,default-trigger = "heartbeat";
139 default-state = "off";
140 };
141 };
142
143 gpio_buttons: gpio_buttons@0 {
144 compatible = "gpio-keys";
145 #address-cells = <1>;
146 #size-cells = <0>;
147
148 switch@1 {
149 label = "button0";
150 linux,code = <0x100>;
151 gpios = <&gpio3 3 0>;
152 };
153
154 switch@2 {
155 label = "button1";
156 linux,code = <0x101>;
157 gpios = <&gpio3 2 0>;
158 };
159
160 switch@3 {
161 label = "button2";
162 linux,code = <0x102>;
163 gpios = <&gpio1 30 0>;
164 gpio-key,wakeup;
165 };
166
167 switch@4 {
168 label = "button3";
169 linux,code = <0x103>;
170 gpios = <&gpio3 5 0>;
171 };
172 };
173};
174
175/include/ "tps65910.dtsi"
176
177&tps {
178 vcc1-supply = <&vbat>;
179 vcc2-supply = <&vbat>;
180 vcc3-supply = <&vbat>;
181 vcc4-supply = <&vbat>;
182 vcc5-supply = <&vbat>;
183 vcc6-supply = <&vbat>;
184 vcc7-supply = <&vbat>;
185 vccio-supply = <&vbat>;
186
187 regulators {
188 vrtc_reg: regulator@0 {
189 regulator-always-on;
190 };
191
192 vio_reg: regulator@1 {
193 regulator-always-on;
194 };
195
196 vdd1_reg: regulator@2 {
197 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
198 regulator-name = "vdd_mpu";
199 regulator-min-microvolt = <912500>;
200 regulator-max-microvolt = <1312500>;
201 regulator-boot-on;
202 regulator-always-on;
203 };
204
205 vdd2_reg: regulator@3 {
206 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
207 regulator-name = "vdd_core";
208 regulator-min-microvolt = <912500>;
209 regulator-max-microvolt = <1150000>;
210 regulator-boot-on;
211 regulator-always-on;
212 };
213
214 vdd3_reg: regulator@4 {
215 regulator-always-on;
216 };
217
218 vdig1_reg: regulator@5 {
219 regulator-always-on;
220 };
221
222 vdig2_reg: regulator@6 {
223 regulator-always-on;
224 };
225
226 vpll_reg: regulator@7 {
227 regulator-always-on;
228 };
229
230 vdac_reg: regulator@8 {
231 regulator-always-on;
232 };
233
234 vaux1_reg: regulator@9 {
235 regulator-always-on;
236 };
237
238 vaux2_reg: regulator@10 {
239 regulator-always-on;
240 };
241
242 vaux33_reg: regulator@11 {
243 regulator-always-on;
244 };
245
246 vmmc_reg: regulator@12 {
247 regulator-always-on;
248 };
249 };
250};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index bb31bff01998..c2f14e875eb6 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -12,6 +12,7 @@
12 12
13/ { 13/ {
14 compatible = "ti,am33xx"; 14 compatible = "ti,am33xx";
15 interrupt-parent = <&intc>;
15 16
16 aliases { 17 aliases {
17 serial0 = &uart1; 18 serial0 = &uart1;
@@ -25,6 +26,21 @@
25 cpus { 26 cpus {
26 cpu@0 { 27 cpu@0 {
27 compatible = "arm,cortex-a8"; 28 compatible = "arm,cortex-a8";
29
30 /*
31 * To consider voltage drop between PMIC and SoC,
32 * tolerance value is reduced to 2% from 4% and
33 * voltage value is increased as a precaution.
34 */
35 operating-points = <
36 /* kHz uV */
37 720000 1285000
38 600000 1225000
39 500000 1125000
40 275000 1125000
41 >;
42 voltage-tolerance = <2>; /* 2 percentage */
43 clock-latency = <300000>; /* From omap-cpufreq driver */
28 }; 44 };
29 }; 45 };
30 46
@@ -40,6 +56,15 @@
40 }; 56 };
41 }; 57 };
42 58
59 am33xx_pinmux: pinmux@44e10800 {
60 compatible = "pinctrl-single";
61 reg = <0x44e10800 0x0238>;
62 #address-cells = <1>;
63 #size-cells = <0>;
64 pinctrl-single,register-width = <32>;
65 pinctrl-single,function-mask = <0x7f>;
66 };
67
43 /* 68 /*
44 * XXX: Use a flat representation of the AM33XX interconnect. 69 * XXX: Use a flat representation of the AM33XX interconnect.
45 * The real AM33XX interconnect network is quite complex.Since 70 * The real AM33XX interconnect network is quite complex.Since
@@ -70,7 +95,6 @@
70 interrupt-controller; 95 interrupt-controller;
71 #interrupt-cells = <1>; 96 #interrupt-cells = <1>;
72 reg = <0x44e07000 0x1000>; 97 reg = <0x44e07000 0x1000>;
73 interrupt-parent = <&intc>;
74 interrupts = <96>; 98 interrupts = <96>;
75 }; 99 };
76 100
@@ -82,7 +106,6 @@
82 interrupt-controller; 106 interrupt-controller;
83 #interrupt-cells = <1>; 107 #interrupt-cells = <1>;
84 reg = <0x4804c000 0x1000>; 108 reg = <0x4804c000 0x1000>;
85 interrupt-parent = <&intc>;
86 interrupts = <98>; 109 interrupts = <98>;
87 }; 110 };
88 111
@@ -94,7 +117,6 @@
94 interrupt-controller; 117 interrupt-controller;
95 #interrupt-cells = <1>; 118 #interrupt-cells = <1>;
96 reg = <0x481ac000 0x1000>; 119 reg = <0x481ac000 0x1000>;
97 interrupt-parent = <&intc>;
98 interrupts = <32>; 120 interrupts = <32>;
99 }; 121 };
100 122
@@ -106,7 +128,6 @@
106 interrupt-controller; 128 interrupt-controller;
107 #interrupt-cells = <1>; 129 #interrupt-cells = <1>;
108 reg = <0x481ae000 0x1000>; 130 reg = <0x481ae000 0x1000>;
109 interrupt-parent = <&intc>;
110 interrupts = <62>; 131 interrupts = <62>;
111 }; 132 };
112 133
@@ -115,7 +136,6 @@
115 ti,hwmods = "uart1"; 136 ti,hwmods = "uart1";
116 clock-frequency = <48000000>; 137 clock-frequency = <48000000>;
117 reg = <0x44e09000 0x2000>; 138 reg = <0x44e09000 0x2000>;
118 interrupt-parent = <&intc>;
119 interrupts = <72>; 139 interrupts = <72>;
120 status = "disabled"; 140 status = "disabled";
121 }; 141 };
@@ -125,7 +145,6 @@
125 ti,hwmods = "uart2"; 145 ti,hwmods = "uart2";
126 clock-frequency = <48000000>; 146 clock-frequency = <48000000>;
127 reg = <0x48022000 0x2000>; 147 reg = <0x48022000 0x2000>;
128 interrupt-parent = <&intc>;
129 interrupts = <73>; 148 interrupts = <73>;
130 status = "disabled"; 149 status = "disabled";
131 }; 150 };
@@ -135,7 +154,6 @@
135 ti,hwmods = "uart3"; 154 ti,hwmods = "uart3";
136 clock-frequency = <48000000>; 155 clock-frequency = <48000000>;
137 reg = <0x48024000 0x2000>; 156 reg = <0x48024000 0x2000>;
138 interrupt-parent = <&intc>;
139 interrupts = <74>; 157 interrupts = <74>;
140 status = "disabled"; 158 status = "disabled";
141 }; 159 };
@@ -145,7 +163,6 @@
145 ti,hwmods = "uart4"; 163 ti,hwmods = "uart4";
146 clock-frequency = <48000000>; 164 clock-frequency = <48000000>;
147 reg = <0x481a6000 0x2000>; 165 reg = <0x481a6000 0x2000>;
148 interrupt-parent = <&intc>;
149 interrupts = <44>; 166 interrupts = <44>;
150 status = "disabled"; 167 status = "disabled";
151 }; 168 };
@@ -155,7 +172,6 @@
155 ti,hwmods = "uart5"; 172 ti,hwmods = "uart5";
156 clock-frequency = <48000000>; 173 clock-frequency = <48000000>;
157 reg = <0x481a8000 0x2000>; 174 reg = <0x481a8000 0x2000>;
158 interrupt-parent = <&intc>;
159 interrupts = <45>; 175 interrupts = <45>;
160 status = "disabled"; 176 status = "disabled";
161 }; 177 };
@@ -165,7 +181,6 @@
165 ti,hwmods = "uart6"; 181 ti,hwmods = "uart6";
166 clock-frequency = <48000000>; 182 clock-frequency = <48000000>;
167 reg = <0x481aa000 0x2000>; 183 reg = <0x481aa000 0x2000>;
168 interrupt-parent = <&intc>;
169 interrupts = <46>; 184 interrupts = <46>;
170 status = "disabled"; 185 status = "disabled";
171 }; 186 };
@@ -176,7 +191,6 @@
176 #size-cells = <0>; 191 #size-cells = <0>;
177 ti,hwmods = "i2c1"; 192 ti,hwmods = "i2c1";
178 reg = <0x44e0b000 0x1000>; 193 reg = <0x44e0b000 0x1000>;
179 interrupt-parent = <&intc>;
180 interrupts = <70>; 194 interrupts = <70>;
181 status = "disabled"; 195 status = "disabled";
182 }; 196 };
@@ -187,7 +201,6 @@
187 #size-cells = <0>; 201 #size-cells = <0>;
188 ti,hwmods = "i2c2"; 202 ti,hwmods = "i2c2";
189 reg = <0x4802a000 0x1000>; 203 reg = <0x4802a000 0x1000>;
190 interrupt-parent = <&intc>;
191 interrupts = <71>; 204 interrupts = <71>;
192 status = "disabled"; 205 status = "disabled";
193 }; 206 };
@@ -198,7 +211,6 @@
198 #size-cells = <0>; 211 #size-cells = <0>;
199 ti,hwmods = "i2c3"; 212 ti,hwmods = "i2c3";
200 reg = <0x4819c000 0x1000>; 213 reg = <0x4819c000 0x1000>;
201 interrupt-parent = <&intc>;
202 interrupts = <30>; 214 interrupts = <30>;
203 status = "disabled"; 215 status = "disabled";
204 }; 216 };
@@ -207,8 +219,171 @@
207 compatible = "ti,omap3-wdt"; 219 compatible = "ti,omap3-wdt";
208 ti,hwmods = "wd_timer2"; 220 ti,hwmods = "wd_timer2";
209 reg = <0x44e35000 0x1000>; 221 reg = <0x44e35000 0x1000>;
210 interrupt-parent = <&intc>;
211 interrupts = <91>; 222 interrupts = <91>;
212 }; 223 };
224
225 dcan0: d_can@481cc000 {
226 compatible = "bosch,d_can";
227 ti,hwmods = "d_can0";
228 reg = <0x481cc000 0x2000>;
229 interrupts = <52>;
230 status = "disabled";
231 };
232
233 dcan1: d_can@481d0000 {
234 compatible = "bosch,d_can";
235 ti,hwmods = "d_can1";
236 reg = <0x481d0000 0x2000>;
237 interrupts = <55>;
238 status = "disabled";
239 };
240
241 timer1: timer@44e31000 {
242 compatible = "ti,omap2-timer";
243 reg = <0x44e31000 0x400>;
244 interrupts = <67>;
245 ti,hwmods = "timer1";
246 ti,timer-alwon;
247 };
248
249 timer2: timer@48040000 {
250 compatible = "ti,omap2-timer";
251 reg = <0x48040000 0x400>;
252 interrupts = <68>;
253 ti,hwmods = "timer2";
254 };
255
256 timer3: timer@48042000 {
257 compatible = "ti,omap2-timer";
258 reg = <0x48042000 0x400>;
259 interrupts = <69>;
260 ti,hwmods = "timer3";
261 };
262
263 timer4: timer@48044000 {
264 compatible = "ti,omap2-timer";
265 reg = <0x48044000 0x400>;
266 interrupts = <92>;
267 ti,hwmods = "timer4";
268 ti,timer-pwm;
269 };
270
271 timer5: timer@48046000 {
272 compatible = "ti,omap2-timer";
273 reg = <0x48046000 0x400>;
274 interrupts = <93>;
275 ti,hwmods = "timer5";
276 ti,timer-pwm;
277 };
278
279 timer6: timer@48048000 {
280 compatible = "ti,omap2-timer";
281 reg = <0x48048000 0x400>;
282 interrupts = <94>;
283 ti,hwmods = "timer6";
284 ti,timer-pwm;
285 };
286
287 timer7: timer@4804a000 {
288 compatible = "ti,omap2-timer";
289 reg = <0x4804a000 0x400>;
290 interrupts = <95>;
291 ti,hwmods = "timer7";
292 ti,timer-pwm;
293 };
294
295 rtc@44e3e000 {
296 compatible = "ti,da830-rtc";
297 reg = <0x44e3e000 0x1000>;
298 interrupts = <75
299 76>;
300 ti,hwmods = "rtc";
301 };
302
303 spi0: spi@48030000 {
304 compatible = "ti,omap4-mcspi";
305 #address-cells = <1>;
306 #size-cells = <0>;
307 reg = <0x48030000 0x400>;
308 interrupt = <65>;
309 ti,spi-num-cs = <2>;
310 ti,hwmods = "spi0";
311 status = "disabled";
312 };
313
314 spi1: spi@481a0000 {
315 compatible = "ti,omap4-mcspi";
316 #address-cells = <1>;
317 #size-cells = <0>;
318 reg = <0x481a0000 0x400>;
319 interrupt = <125>;
320 ti,spi-num-cs = <2>;
321 ti,hwmods = "spi1";
322 status = "disabled";
323 };
324
325 usb@47400000 {
326 compatible = "ti,musb-am33xx";
327 reg = <0x47400000 0x1000 /* usbss */
328 0x47401000 0x800 /* musb instance 0 */
329 0x47401800 0x800>; /* musb instance 1 */
330 interrupts = <17 /* usbss */
331 18 /* musb instance 0 */
332 19>; /* musb instance 1 */
333 multipoint = <1>;
334 num-eps = <16>;
335 ram-bits = <12>;
336 port0-mode = <3>;
337 port1-mode = <3>;
338 power = <250>;
339 ti,hwmods = "usb_otg_hs";
340 };
341
342 mac: ethernet@4a100000 {
343 compatible = "ti,cpsw";
344 ti,hwmods = "cpgmac0";
345 cpdma_channels = <8>;
346 ale_entries = <1024>;
347 bd_ram_size = <0x2000>;
348 no_bd_ram = <0>;
349 rx_descs = <64>;
350 mac_control = <0x20>;
351 slaves = <2>;
352 cpts_active_slave = <0>;
353 cpts_clock_mult = <0x80000000>;
354 cpts_clock_shift = <29>;
355 reg = <0x4a100000 0x800
356 0x4a101200 0x100>;
357 #address-cells = <1>;
358 #size-cells = <1>;
359 interrupt-parent = <&intc>;
360 /*
361 * c0_rx_thresh_pend
362 * c0_rx_pend
363 * c0_tx_pend
364 * c0_misc_pend
365 */
366 interrupts = <40 41 42 43>;
367 ranges;
368
369 davinci_mdio: mdio@4a101000 {
370 compatible = "ti,davinci_mdio";
371 #address-cells = <1>;
372 #size-cells = <0>;
373 ti,hwmods = "davinci_mdio";
374 bus_freq = <1000000>;
375 reg = <0x4a101000 0x100>;
376 };
377
378 cpsw_emac0: slave@4a100200 {
379 /* Filled in by U-Boot */
380 mac-address = [ 00 00 00 00 00 00 ];
381 };
382
383 cpsw_emac1: slave@4a100300 {
384 /* Filled in by U-Boot */
385 mac-address = [ 00 00 00 00 00 00 ];
386 };
387 };
213 }; 388 };
214}; 389};
diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts
new file mode 100644
index 000000000000..74d92cd29d87
--- /dev/null
+++ b/arch/arm/boot/dts/animeo_ip.dts
@@ -0,0 +1,178 @@
1/*
2 * animeo_ip.dts - Device Tree file for Somfy Animeo IP Boards
3 *
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2 only.
7 */
8
9/dts-v1/;
10/include/ "at91sam9260.dtsi"
11
12/ {
13 model = "Somfy Animeo IP";
14 compatible = "somfy,animeo-ip", "atmel,at91sam9260", "atmel,at91sam9";
15
16 aliases {
17 serial0 = &usart1;
18 serial1 = &usart2;
19 serial2 = &usart0;
20 serial3 = &dbgu;
21 serial4 = &usart3;
22 serial5 = &uart0;
23 serial6 = &uart1;
24 };
25
26 chosen {
27 linux,stdout-path = &usart2;
28 };
29
30 memory {
31 reg = <0x20000000 0x4000000>;
32 };
33
34 clocks {
35 #address-cells = <1>;
36 #size-cells = <1>;
37 ranges;
38
39 main_clock: clock@0 {
40 compatible = "atmel,osc", "fixed-clock";
41 clock-frequency = <18432000>;
42 };
43 };
44
45 ahb {
46 apb {
47 usart0: serial@fffb0000 {
48 pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts>;
49 linux,rs485-enabled-at-boot-time;
50 status = "okay";
51 };
52
53 usart1: serial@fffb4000 {
54 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts>;
55 linux,rs485-enabled-at-boot-time;
56 status = "okay";
57 };
58
59 usart2: serial@fffb8000 {
60 pinctrl-0 = <&pinctrl_usart2>;
61 status = "okay";
62 };
63
64 macb0: ethernet@fffc4000 {
65 pinctrl-0 = <&pinctrl_macb_rmii &pinctrl_macb_rmii_mii>;
66 phy-mode = "mii";
67 status = "okay";
68 };
69
70 mmc0: mmc@fffa8000 {
71 pinctrl-0 = <&pinctrl_mmc0_clk
72 &pinctrl_mmc0_slot1_cmd_dat0
73 &pinctrl_mmc0_slot1_dat1_3>;
74 status = "okay";
75
76 slot@1 {
77 reg = <1>;
78 bus-width = <4>;
79 };
80 };
81 };
82
83 nand0: nand@40000000 {
84 nand-bus-width = <8>;
85 nand-ecc-mode = "soft";
86 nand-on-flash-bbt;
87 status = "okay";
88
89 at91bootstrap@0 {
90 label = "at91bootstrap";
91 reg = <0x0 0x8000>;
92 };
93
94 barebox@8000 {
95 label = "barebox";
96 reg = <0x8000 0x40000>;
97 };
98
99 bareboxenv@48000 {
100 label = "bareboxenv";
101 reg = <0x48000 0x8000>;
102 };
103
104 user_block@0x50000 {
105 label = "user_block";
106 reg = <0x50000 0xb0000>;
107 };
108
109 kernel@100000 {
110 label = "kernel";
111 reg = <0x100000 0x1b0000>;
112 };
113
114 root@2b0000 {
115 label = "root";
116 reg = <0x2b0000 0x1D50000>;
117 };
118 };
119
120 usb0: ohci@00500000 {
121 num-ports = <2>;
122 atmel,vbus-gpio = <&pioB 15 1>;
123 status = "okay";
124 };
125 };
126
127 leds {
128 compatible = "gpio-leds";
129
130 power_green {
131 label = "power_green";
132 gpios = <&pioC 17 0>;
133 linux,default-trigger = "heartbeat";
134 };
135
136 power_red {
137 label = "power_red";
138 gpios = <&pioA 2 0>;
139 };
140
141 tx_green {
142 label = "tx_green";
143 gpios = <&pioC 19 0>;
144 };
145
146 tx_red {
147 label = "tx_red";
148 gpios = <&pioC 18 0>;
149 };
150 };
151
152 gpio_keys {
153 compatible = "gpio-keys";
154 #address-cells = <1>;
155 #size-cells = <0>;
156
157 keyswitch_in {
158 label = "keyswitch_in";
159 gpios = <&pioB 1 0>;
160 linux,code = <28>;
161 gpio-key,wakeup;
162 };
163
164 error_in {
165 label = "error_in";
166 gpios = <&pioB 2 0>;
167 linux,code = <29>;
168 gpio-key,wakeup;
169 };
170
171 btn {
172 label = "btn";
173 gpios = <&pioC 23 0>;
174 linux,code = <31>;
175 gpio-key,wakeup;
176 };
177 };
178};
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index fffd5c2a3041..00044026ef1f 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -34,9 +34,30 @@
34 clock-frequency = <200000000>; 34 clock-frequency = <200000000>;
35 status = "okay"; 35 status = "okay";
36 }; 36 };
37 timer@d0020300 { 37 sata@d00a0000 {
38 clock-frequency = <600000000>; 38 nr-ports = <2>;
39 status = "okay"; 39 status = "okay";
40 }; 40 };
41
42 mdio {
43 phy0: ethernet-phy@0 {
44 reg = <0>;
45 };
46
47 phy1: ethernet-phy@1 {
48 reg = <1>;
49 };
50 };
51
52 ethernet@d0070000 {
53 status = "okay";
54 phy = <&phy0>;
55 phy-mode = "rgmii-id";
56 };
57 ethernet@d0074000 {
58 status = "okay";
59 phy = <&phy1>;
60 phy-mode = "rgmii-id";
61 };
41 }; 62 };
42}; 63};
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
new file mode 100644
index 000000000000..3b4071336599
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -0,0 +1,56 @@
1/*
2 * Device Tree file for Globalscale Mirabox
3 *
4 * Gregory CLEMENT <gregory.clement@free-electrons.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11/dts-v1/;
12/include/ "armada-370.dtsi"
13
14/ {
15 model = "Globalscale Mirabox";
16 compatible = "globalscale,mirabox", "marvell,armada370", "marvell,armada-370-xp";
17
18 chosen {
19 bootargs = "console=ttyS0,115200 earlyprintk";
20 };
21
22 memory {
23 device_type = "memory";
24 reg = <0x00000000 0x20000000>; /* 512 MB */
25 };
26
27 soc {
28 serial@d0012000 {
29 clock-frequency = <200000000>;
30 status = "okay";
31 };
32 timer@d0020300 {
33 clock-frequency = <600000000>;
34 status = "okay";
35 };
36 mdio {
37 phy0: ethernet-phy@0 {
38 reg = <0>;
39 };
40
41 phy1: ethernet-phy@1 {
42 reg = <1>;
43 };
44 };
45 ethernet@d0070000 {
46 status = "okay";
47 phy = <&phy0>;
48 phy-mode = "rgmii-id";
49 };
50 ethernet@d0074000 {
51 status = "okay";
52 phy = <&phy1>;
53 phy-mode = "rgmii-id";
54 };
55 };
56};
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 16cc82cdaa81..4c0abe85405f 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -20,7 +20,7 @@
20 20
21/ { 21/ {
22 model = "Marvell Armada 370 and XP SoC"; 22 model = "Marvell Armada 370 and XP SoC";
23 compatible = "marvell,armada_370_xp"; 23 compatible = "marvell,armada-370-xp";
24 24
25 cpus { 25 cpus {
26 cpu@0 { 26 cpu@0 {
@@ -36,6 +36,12 @@
36 interrupt-controller; 36 interrupt-controller;
37 }; 37 };
38 38
39 coherency-fabric@d0020200 {
40 compatible = "marvell,coherency-fabric";
41 reg = <0xd0020200 0xb0>,
42 <0xd0021810 0x1c>;
43 };
44
39 soc { 45 soc {
40 #address-cells = <1>; 46 #address-cells = <1>;
41 #size-cells = <1>; 47 #size-cells = <1>;
@@ -44,17 +50,19 @@
44 ranges; 50 ranges;
45 51
46 serial@d0012000 { 52 serial@d0012000 {
47 compatible = "ns16550"; 53 compatible = "snps,dw-apb-uart";
48 reg = <0xd0012000 0x100>; 54 reg = <0xd0012000 0x100>;
49 reg-shift = <2>; 55 reg-shift = <2>;
50 interrupts = <41>; 56 interrupts = <41>;
57 reg-io-width = <4>;
51 status = "disabled"; 58 status = "disabled";
52 }; 59 };
53 serial@d0012100 { 60 serial@d0012100 {
54 compatible = "ns16550"; 61 compatible = "snps,dw-apb-uart";
55 reg = <0xd0012100 0x100>; 62 reg = <0xd0012100 0x100>;
56 reg-shift = <2>; 63 reg-shift = <2>;
57 interrupts = <42>; 64 interrupts = <42>;
65 reg-io-width = <4>;
58 status = "disabled"; 66 status = "disabled";
59 }; 67 };
60 68
@@ -62,12 +70,67 @@
62 compatible = "marvell,armada-370-xp-timer"; 70 compatible = "marvell,armada-370-xp-timer";
63 reg = <0xd0020300 0x30>; 71 reg = <0xd0020300 0x30>;
64 interrupts = <37>, <38>, <39>, <40>; 72 interrupts = <37>, <38>, <39>, <40>;
73 clocks = <&coreclk 2>;
65 }; 74 };
66 75
67 addr-decoding@d0020000 { 76 addr-decoding@d0020000 {
68 compatible = "marvell,armada-addr-decoding-controller"; 77 compatible = "marvell,armada-addr-decoding-controller";
69 reg = <0xd0020000 0x258>; 78 reg = <0xd0020000 0x258>;
70 }; 79 };
80
81 sata@d00a0000 {
82 compatible = "marvell,orion-sata";
83 reg = <0xd00a0000 0x2400>;
84 interrupts = <55>;
85 clocks = <&gateclk 15>, <&gateclk 30>;
86 clock-names = "0", "1";
87 status = "disabled";
88 };
89
90 mdio {
91 #address-cells = <1>;
92 #size-cells = <0>;
93 compatible = "marvell,orion-mdio";
94 reg = <0xd0072004 0x4>;
95 };
96
97 ethernet@d0070000 {
98 compatible = "marvell,armada-370-neta";
99 reg = <0xd0070000 0x2500>;
100 interrupts = <8>;
101 clocks = <&gateclk 4>;
102 status = "disabled";
103 };
104
105 ethernet@d0074000 {
106 compatible = "marvell,armada-370-neta";
107 reg = <0xd0074000 0x2500>;
108 interrupts = <10>;
109 clocks = <&gateclk 3>;
110 status = "disabled";
111 };
112
113 i2c0: i2c@d0011000 {
114 compatible = "marvell,mv64xxx-i2c";
115 reg = <0xd0011000 0x20>;
116 #address-cells = <1>;
117 #size-cells = <0>;
118 interrupts = <31>;
119 timeout-ms = <1000>;
120 clocks = <&coreclk 0>;
121 status = "disabled";
122 };
123
124 i2c1: i2c@d0011100 {
125 compatible = "marvell,mv64xxx-i2c";
126 reg = <0xd0011100 0x20>;
127 #address-cells = <1>;
128 #size-cells = <0>;
129 interrupts = <32>;
130 timeout-ms = <1000>;
131 clocks = <&coreclk 0>;
132 status = "disabled";
133 };
71 }; 134 };
72}; 135};
73 136
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 2069151afe01..636cf7d4009e 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -20,6 +20,12 @@
20/ { 20/ {
21 model = "Marvell Armada 370 family SoC"; 21 model = "Marvell Armada 370 family SoC";
22 compatible = "marvell,armada370", "marvell,armada-370-xp"; 22 compatible = "marvell,armada370", "marvell,armada-370-xp";
23 L2: l2-cache {
24 compatible = "marvell,aurora-outer-cache";
25 reg = <0xd0008000 0x1000>;
26 cache-id-part = <0x100>;
27 wt-override;
28 };
23 29
24 aliases { 30 aliases {
25 gpio0 = &gpio0; 31 gpio0 = &gpio0;
@@ -75,5 +81,56 @@
75 #interrupts-cells = <2>; 81 #interrupts-cells = <2>;
76 interrupts = <91>; 82 interrupts = <91>;
77 }; 83 };
84
85 coreclk: mvebu-sar@d0018230 {
86 compatible = "marvell,armada-370-core-clock";
87 reg = <0xd0018230 0x08>;
88 #clock-cells = <1>;
89 };
90
91 gateclk: clock-gating-control@d0018220 {
92 compatible = "marvell,armada-370-gating-clock";
93 reg = <0xd0018220 0x4>;
94 clocks = <&coreclk 0>;
95 #clock-cells = <1>;
96 };
97
98 xor@d0060800 {
99 compatible = "marvell,orion-xor";
100 reg = <0xd0060800 0x100
101 0xd0060A00 0x100>;
102 status = "okay";
103
104 xor00 {
105 interrupts = <51>;
106 dmacap,memcpy;
107 dmacap,xor;
108 };
109 xor01 {
110 interrupts = <52>;
111 dmacap,memcpy;
112 dmacap,xor;
113 dmacap,memset;
114 };
115 };
116
117 xor@d0060900 {
118 compatible = "marvell,orion-xor";
119 reg = <0xd0060900 0x100
120 0xd0060b00 0x100>;
121 status = "okay";
122
123 xor10 {
124 interrupts = <94>;
125 dmacap,memcpy;
126 dmacap,xor;
127 };
128 xor11 {
129 interrupts = <95>;
130 dmacap,memcpy;
131 dmacap,xor;
132 dmacap,memset;
133 };
134 };
78 }; 135 };
79}; 136};
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index b1fc728515e9..8e53b25b5508 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -46,5 +46,49 @@
46 clock-frequency = <250000000>; 46 clock-frequency = <250000000>;
47 status = "okay"; 47 status = "okay";
48 }; 48 };
49
50 sata@d00a0000 {
51 nr-ports = <2>;
52 status = "okay";
53 };
54
55 mdio {
56 phy0: ethernet-phy@0 {
57 reg = <0>;
58 };
59
60 phy1: ethernet-phy@1 {
61 reg = <1>;
62 };
63
64 phy2: ethernet-phy@2 {
65 reg = <25>;
66 };
67
68 phy3: ethernet-phy@3 {
69 reg = <27>;
70 };
71 };
72
73 ethernet@d0070000 {
74 status = "okay";
75 phy = <&phy0>;
76 phy-mode = "rgmii-id";
77 };
78 ethernet@d0074000 {
79 status = "okay";
80 phy = <&phy1>;
81 phy-mode = "rgmii-id";
82 };
83 ethernet@d0030000 {
84 status = "okay";
85 phy = <&phy2>;
86 phy-mode = "sgmii";
87 };
88 ethernet@d0034000 {
89 status = "okay";
90 phy = <&phy3>;
91 phy-mode = "sgmii";
92 };
49 }; 93 };
50}; 94};
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index ea355192be6f..271855a6e224 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -24,6 +24,25 @@
24 gpio1 = &gpio1; 24 gpio1 = &gpio1;
25 }; 25 };
26 26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu@0 {
32 device_type = "cpu";
33 compatible = "marvell,sheeva-v7";
34 reg = <0>;
35 clocks = <&cpuclk 0>;
36 };
37
38 cpu@1 {
39 device_type = "cpu";
40 compatible = "marvell,sheeva-v7";
41 reg = <1>;
42 clocks = <&cpuclk 1>;
43 };
44 };
45
27 soc { 46 soc {
28 pinctrl { 47 pinctrl {
29 compatible = "marvell,mv78230-pinctrl"; 48 compatible = "marvell,mv78230-pinctrl";
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 2057863f3dfa..1c1937dbce73 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -25,6 +25,25 @@
25 gpio2 = &gpio2; 25 gpio2 = &gpio2;
26 }; 26 };
27 27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 cpu@0 {
33 device_type = "cpu";
34 compatible = "marvell,sheeva-v7";
35 reg = <0>;
36 clocks = <&cpuclk 0>;
37 };
38
39 cpu@1 {
40 device_type = "cpu";
41 compatible = "marvell,sheeva-v7";
42 reg = <1>;
43 clocks = <&cpuclk 1>;
44 };
45 };
46
28 soc { 47 soc {
29 pinctrl { 48 pinctrl {
30 compatible = "marvell,mv78260-pinctrl"; 49 compatible = "marvell,mv78260-pinctrl";
@@ -66,5 +85,13 @@
66 #interrupts-cells = <2>; 85 #interrupts-cells = <2>;
67 interrupts = <24>; 86 interrupts = <24>;
68 }; 87 };
88
89 ethernet@d0034000 {
90 compatible = "marvell,armada-370-neta";
91 reg = <0xd0034000 0x2500>;
92 interrupts = <14>;
93 clocks = <&gateclk 1>;
94 status = "disabled";
95 };
69 }; 96 };
70}; 97};
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index ffac98373792..4905cf3a5ef8 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -25,6 +25,40 @@
25 gpio2 = &gpio2; 25 gpio2 = &gpio2;
26 }; 26 };
27 27
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu@0 {
34 device_type = "cpu";
35 compatible = "marvell,sheeva-v7";
36 reg = <0>;
37 clocks = <&cpuclk 0>;
38 };
39
40 cpu@1 {
41 device_type = "cpu";
42 compatible = "marvell,sheeva-v7";
43 reg = <1>;
44 clocks = <&cpuclk 1>;
45 };
46
47 cpu@2 {
48 device_type = "cpu";
49 compatible = "marvell,sheeva-v7";
50 reg = <2>;
51 clocks = <&cpuclk 2>;
52 };
53
54 cpu@3 {
55 device_type = "cpu";
56 compatible = "marvell,sheeva-v7";
57 reg = <3>;
58 clocks = <&cpuclk 3>;
59 };
60 };
61
28 soc { 62 soc {
29 pinctrl { 63 pinctrl {
30 compatible = "marvell,mv78460-pinctrl"; 64 compatible = "marvell,mv78460-pinctrl";
@@ -66,5 +100,13 @@
66 #interrupts-cells = <2>; 100 #interrupts-cells = <2>;
67 interrupts = <24>; 101 interrupts = <24>;
68 }; 102 };
103
104 ethernet@d0034000 {
105 compatible = "marvell,armada-370-neta";
106 reg = <0xd0034000 0x2500>;
107 interrupts = <14>;
108 clocks = <&gateclk 1>;
109 status = "disabled";
110 };
69 }; 111 };
70 }; 112 };
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
new file mode 100644
index 000000000000..b42652fd3d8c
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -0,0 +1,125 @@
1/*
2 * Device Tree file for OpenBlocks AX3-4 board
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13/dts-v1/;
14/include/ "armada-xp-mv78260.dtsi"
15
16/ {
17 model = "PlatHome OpenBlocks AX3-4 board";
18 compatible = "plathome,openblocks-ax3-4", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
19
20 chosen {
21 bootargs = "console=ttyS0,115200 earlyprintk";
22 };
23
24 memory {
25 device_type = "memory";
26 reg = <0x00000000 0xC0000000>; /* 3 GB */
27 };
28
29 soc {
30 serial@d0012000 {
31 clock-frequency = <250000000>;
32 status = "okay";
33 };
34 serial@d0012100 {
35 clock-frequency = <250000000>;
36 status = "okay";
37 };
38 pinctrl {
39 led_pins: led-pins-0 {
40 marvell,pins = "mpp49", "mpp51", "mpp53";
41 marvell,function = "gpio";
42 };
43 };
44 leds {
45 compatible = "gpio-leds";
46 pinctrl-names = "default";
47 pinctrl-0 = <&led_pins>;
48
49 red_led {
50 label = "red_led";
51 gpios = <&gpio1 17 1>;
52 default-state = "off";
53 };
54
55 yellow_led {
56 label = "yellow_led";
57 gpios = <&gpio1 19 1>;
58 default-state = "off";
59 };
60
61 green_led {
62 label = "green_led";
63 gpios = <&gpio1 21 1>;
64 default-state = "off";
65 linux,default-trigger = "heartbeat";
66 };
67 };
68
69 mdio {
70 phy0: ethernet-phy@0 {
71 reg = <0>;
72 };
73
74 phy1: ethernet-phy@1 {
75 reg = <1>;
76 };
77
78 phy2: ethernet-phy@2 {
79 reg = <2>;
80 };
81
82 phy3: ethernet-phy@3 {
83 reg = <3>;
84 };
85 };
86
87 ethernet@d0070000 {
88 status = "okay";
89 phy = <&phy0>;
90 phy-mode = "sgmii";
91 };
92 ethernet@d0074000 {
93 status = "okay";
94 phy = <&phy1>;
95 phy-mode = "sgmii";
96 };
97 ethernet@d0030000 {
98 status = "okay";
99 phy = <&phy2>;
100 phy-mode = "sgmii";
101 };
102 ethernet@d0034000 {
103 status = "okay";
104 phy = <&phy3>;
105 phy-mode = "sgmii";
106 };
107 i2c@d0011000 {
108 status = "okay";
109 clock-frequency = <400000>;
110 };
111 i2c@d0011100 {
112 status = "okay";
113 clock-frequency = <400000>;
114
115 s35390a: s35390a@30 {
116 compatible = "s35390a";
117 reg = <0x30>;
118 };
119 };
120 sata@d00a0000 {
121 nr-ports = <2>;
122 status = "okay";
123 };
124 };
125};
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 71d6b5d0daf1..2e37ef101c90 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -22,24 +22,39 @@
22 model = "Marvell Armada XP family SoC"; 22 model = "Marvell Armada XP family SoC";
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp"; 23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
24 24
25 L2: l2-cache {
26 compatible = "marvell,aurora-system-cache";
27 reg = <0xd0008000 0x1000>;
28 cache-id-part = <0x100>;
29 wt-override;
30 };
31
25 mpic: interrupt-controller@d0020000 { 32 mpic: interrupt-controller@d0020000 {
26 reg = <0xd0020a00 0x1d0>, 33 reg = <0xd0020a00 0x1d0>,
27 <0xd0021870 0x58>; 34 <0xd0021070 0x58>;
35 };
36
37 armada-370-xp-pmsu@d0022000 {
38 compatible = "marvell,armada-370-xp-pmsu";
39 reg = <0xd0022100 0x430>,
40 <0xd0020800 0x20>;
28 }; 41 };
29 42
30 soc { 43 soc {
31 serial@d0012200 { 44 serial@d0012200 {
32 compatible = "ns16550"; 45 compatible = "snps,dw-apb-uart";
33 reg = <0xd0012200 0x100>; 46 reg = <0xd0012200 0x100>;
34 reg-shift = <2>; 47 reg-shift = <2>;
35 interrupts = <43>; 48 interrupts = <43>;
49 reg-io-width = <4>;
36 status = "disabled"; 50 status = "disabled";
37 }; 51 };
38 serial@d0012300 { 52 serial@d0012300 {
39 compatible = "ns16550"; 53 compatible = "snps,dw-apb-uart";
40 reg = <0xd0012300 0x100>; 54 reg = <0xd0012300 0x100>;
41 reg-shift = <2>; 55 reg-shift = <2>;
42 interrupts = <44>; 56 interrupts = <44>;
57 reg-io-width = <4>;
43 status = "disabled"; 58 status = "disabled";
44 }; 59 };
45 60
@@ -47,9 +62,77 @@
47 marvell,timer-25Mhz; 62 marvell,timer-25Mhz;
48 }; 63 };
49 64
65 coreclk: mvebu-sar@d0018230 {
66 compatible = "marvell,armada-xp-core-clock";
67 reg = <0xd0018230 0x08>;
68 #clock-cells = <1>;
69 };
70
71 cpuclk: clock-complex@d0018700 {
72 #clock-cells = <1>;
73 compatible = "marvell,armada-xp-cpu-clock";
74 reg = <0xd0018700 0xA0>;
75 clocks = <&coreclk 1>;
76 };
77
78 gateclk: clock-gating-control@d0018220 {
79 compatible = "marvell,armada-xp-gating-clock";
80 reg = <0xd0018220 0x4>;
81 clocks = <&coreclk 0>;
82 #clock-cells = <1>;
83 };
84
50 system-controller@d0018200 { 85 system-controller@d0018200 {
51 compatible = "marvell,armada-370-xp-system-controller"; 86 compatible = "marvell,armada-370-xp-system-controller";
52 reg = <0xd0018200 0x500>; 87 reg = <0xd0018200 0x500>;
53 }; 88 };
89
90 ethernet@d0030000 {
91 compatible = "marvell,armada-370-neta";
92 reg = <0xd0030000 0x2500>;
93 interrupts = <12>;
94 clocks = <&gateclk 2>;
95 status = "disabled";
96 };
97
98 xor@d0060900 {
99 compatible = "marvell,orion-xor";
100 reg = <0xd0060900 0x100
101 0xd0060b00 0x100>;
102 clocks = <&gateclk 22>;
103 status = "okay";
104
105 xor10 {
106 interrupts = <51>;
107 dmacap,memcpy;
108 dmacap,xor;
109 };
110 xor11 {
111 interrupts = <52>;
112 dmacap,memcpy;
113 dmacap,xor;
114 dmacap,memset;
115 };
116 };
117
118 xor@d00f0900 {
119 compatible = "marvell,orion-xor";
120 reg = <0xd00F0900 0x100
121 0xd00F0B00 0x100>;
122 clocks = <&gateclk 28>;
123 status = "okay";
124
125 xor00 {
126 interrupts = <94>;
127 dmacap,memcpy;
128 dmacap,xor;
129 };
130 xor01 {
131 interrupts = <95>;
132 dmacap,memcpy;
133 dmacap,xor;
134 dmacap,memset;
135 };
136 };
54 }; 137 };
55}; 138};
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
new file mode 100644
index 000000000000..e154f242c680
--- /dev/null
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -0,0 +1,349 @@
1/*
2 * at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC
3 *
4 * Copyright (C) 2011 Atmel,
5 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
6 * 2012 Joachim Eastwood <manabian@gmail.com>
7 *
8 * Based on at91sam9260.dtsi
9 *
10 * Licensed under GPLv2 or later.
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 model = "Atmel AT91RM9200 family SoC";
17 compatible = "atmel,at91rm9200";
18 interrupt-parent = <&aic>;
19
20 aliases {
21 serial0 = &dbgu;
22 serial1 = &usart0;
23 serial2 = &usart1;
24 serial3 = &usart2;
25 serial4 = &usart3;
26 gpio0 = &pioA;
27 gpio1 = &pioB;
28 gpio2 = &pioC;
29 gpio3 = &pioD;
30 tcb0 = &tcb0;
31 tcb1 = &tcb1;
32 };
33 cpus {
34 cpu@0 {
35 compatible = "arm,arm920t";
36 };
37 };
38
39 memory {
40 reg = <0x20000000 0x04000000>;
41 };
42
43 ahb {
44 compatible = "simple-bus";
45 #address-cells = <1>;
46 #size-cells = <1>;
47 ranges;
48
49 apb {
50 compatible = "simple-bus";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 ranges;
54
55 aic: interrupt-controller@fffff000 {
56 #interrupt-cells = <3>;
57 compatible = "atmel,at91rm9200-aic";
58 interrupt-controller;
59 reg = <0xfffff000 0x200>;
60 atmel,external-irqs = <25 26 27 28 29 30 31>;
61 };
62
63 ramc0: ramc@ffffff00 {
64 compatible = "atmel,at91rm9200-sdramc";
65 reg = <0xffffff00 0x100>;
66 };
67
68 pmc: pmc@fffffc00 {
69 compatible = "atmel,at91rm9200-pmc";
70 reg = <0xfffffc00 0x100>;
71 };
72
73 st: timer@fffffd00 {
74 compatible = "atmel,at91rm9200-st";
75 reg = <0xfffffd00 0x100>;
76 interrupts = <1 4 7>;
77 };
78
79 tcb0: timer@fffa0000 {
80 compatible = "atmel,at91rm9200-tcb";
81 reg = <0xfffa0000 0x100>;
82 interrupts = <17 4 0 18 4 0 19 4 0>;
83 };
84
85 tcb1: timer@fffa4000 {
86 compatible = "atmel,at91rm9200-tcb";
87 reg = <0xfffa4000 0x100>;
88 interrupts = <20 4 0 21 4 0 22 4 0>;
89 };
90
91 pinctrl@fffff400 {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
95 ranges = <0xfffff400 0xfffff400 0x800>;
96
97 atmel,mux-mask = <
98 /* A B */
99 0xffffffff 0xffffffff /* pioA */
100 0xffffffff 0x083fffff /* pioB */
101 0xffff3fff 0x00000000 /* pioC */
102 0x03ff87ff 0x0fffff80 /* pioD */
103 >;
104
105 /* shared pinctrl settings */
106 dbgu {
107 pinctrl_dbgu: dbgu-0 {
108 atmel,pins =
109 <0 30 0x1 0x0 /* PA30 periph A */
110 0 31 0x1 0x1>; /* PA31 periph with pullup */
111 };
112 };
113
114 uart0 {
115 pinctrl_uart0: uart0-0 {
116 atmel,pins =
117 <0 17 0x1 0x0 /* PA17 periph A */
118 0 18 0x1 0x0>; /* PA18 periph A */
119 };
120
121 pinctrl_uart0_rts: uart0_rts-0 {
122 atmel,pins =
123 <0 20 0x1 0x0>; /* PA20 periph A */
124 };
125
126 pinctrl_uart0_cts: uart0_cts-0 {
127 atmel,pins =
128 <0 21 0x1 0x0>; /* PA21 periph A */
129 };
130 };
131
132 uart1 {
133 pinctrl_uart1: uart1-0 {
134 atmel,pins =
135 <1 20 0x1 0x1 /* PB20 periph A with pullup */
136 1 21 0x1 0x0>; /* PB21 periph A */
137 };
138
139 pinctrl_uart1_rts: uart1_rts-0 {
140 atmel,pins =
141 <1 24 0x1 0x0>; /* PB24 periph A */
142 };
143
144 pinctrl_uart1_cts: uart1_cts-0 {
145 atmel,pins =
146 <1 26 0x1 0x0>; /* PB26 periph A */
147 };
148
149 pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 {
150 atmel,pins =
151 <1 19 0x1 0x0 /* PB19 periph A */
152 1 25 0x1 0x0>; /* PB25 periph A */
153 };
154
155 pinctrl_uart1_dcd: uart1_dcd-0 {
156 atmel,pins =
157 <1 23 0x1 0x0>; /* PB23 periph A */
158 };
159
160 pinctrl_uart1_ri: uart1_ri-0 {
161 atmel,pins =
162 <1 18 0x1 0x0>; /* PB18 periph A */
163 };
164 };
165
166 uart2 {
167 pinctrl_uart2: uart2-0 {
168 atmel,pins =
169 <0 22 0x1 0x0 /* PA22 periph A */
170 0 23 0x1 0x1>; /* PA23 periph A with pullup */
171 };
172
173 pinctrl_uart2_rts: uart2_rts-0 {
174 atmel,pins =
175 <0 30 0x2 0x0>; /* PA30 periph B */
176 };
177
178 pinctrl_uart2_cts: uart2_cts-0 {
179 atmel,pins =
180 <0 31 0x2 0x0>; /* PA31 periph B */
181 };
182 };
183
184 uart3 {
185 pinctrl_uart3: uart3-0 {
186 atmel,pins =
187 <0 5 0x2 0x1 /* PA5 periph B with pullup */
188 0 6 0x2 0x0>; /* PA6 periph B */
189 };
190
191 pinctrl_uart3_rts: uart3_rts-0 {
192 atmel,pins =
193 <1 0 0x2 0x0>; /* PB0 periph B */
194 };
195
196 pinctrl_uart3_cts: uart3_cts-0 {
197 atmel,pins =
198 <1 1 0x2 0x0>; /* PB1 periph B */
199 };
200 };
201
202 nand {
203 pinctrl_nand: nand-0 {
204 atmel,pins =
205 <2 2 0x0 0x1 /* PC2 gpio RDY pin pull_up */
206 1 1 0x0 0x1>; /* PB1 gpio CD pin pull_up */
207 };
208 };
209
210 pioA: gpio@fffff400 {
211 compatible = "atmel,at91rm9200-gpio";
212 reg = <0xfffff400 0x200>;
213 interrupts = <2 4 1>;
214 #gpio-cells = <2>;
215 gpio-controller;
216 interrupt-controller;
217 #interrupt-cells = <2>;
218 };
219
220 pioB: gpio@fffff600 {
221 compatible = "atmel,at91rm9200-gpio";
222 reg = <0xfffff600 0x200>;
223 interrupts = <3 4 1>;
224 #gpio-cells = <2>;
225 gpio-controller;
226 interrupt-controller;
227 #interrupt-cells = <2>;
228 };
229
230 pioC: gpio@fffff800 {
231 compatible = "atmel,at91rm9200-gpio";
232 reg = <0xfffff800 0x200>;
233 interrupts = <4 4 1>;
234 #gpio-cells = <2>;
235 gpio-controller;
236 interrupt-controller;
237 #interrupt-cells = <2>;
238 };
239
240 pioD: gpio@fffffa00 {
241 compatible = "atmel,at91rm9200-gpio";
242 reg = <0xfffffa00 0x200>;
243 interrupts = <5 4 1>;
244 #gpio-cells = <2>;
245 gpio-controller;
246 interrupt-controller;
247 #interrupt-cells = <2>;
248 };
249 };
250
251 dbgu: serial@fffff200 {
252 compatible = "atmel,at91rm9200-usart";
253 reg = <0xfffff200 0x200>;
254 interrupts = <1 4 7>;
255 pinctrl-names = "default";
256 pinctrl-0 = <&pinctrl_dbgu>;
257 status = "disabled";
258 };
259
260 usart0: serial@fffc0000 {
261 compatible = "atmel,at91rm9200-usart";
262 reg = <0xfffc0000 0x200>;
263 interrupts = <6 4 5>;
264 atmel,use-dma-rx;
265 atmel,use-dma-tx;
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_uart0>;
268 status = "disabled";
269 };
270
271 usart1: serial@fffc4000 {
272 compatible = "atmel,at91rm9200-usart";
273 reg = <0xfffc4000 0x200>;
274 interrupts = <7 4 5>;
275 atmel,use-dma-rx;
276 atmel,use-dma-tx;
277 pinctrl-names = "default";
278 pinctrl-0 = <&pinctrl_uart1>;
279 status = "disabled";
280 };
281
282 usart2: serial@fffc8000 {
283 compatible = "atmel,at91rm9200-usart";
284 reg = <0xfffc8000 0x200>;
285 interrupts = <8 4 5>;
286 atmel,use-dma-rx;
287 atmel,use-dma-tx;
288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_uart2>;
290 status = "disabled";
291 };
292
293 usart3: serial@fffcc000 {
294 compatible = "atmel,at91rm9200-usart";
295 reg = <0xfffcc000 0x200>;
296 interrupts = <23 4 5>;
297 atmel,use-dma-rx;
298 atmel,use-dma-tx;
299 pinctrl-names = "default";
300 pinctrl-0 = <&pinctrl_uart3>;
301 status = "disabled";
302 };
303
304 usb1: gadget@fffb0000 {
305 compatible = "atmel,at91rm9200-udc";
306 reg = <0xfffb0000 0x4000>;
307 interrupts = <11 4 2>;
308 status = "disabled";
309 };
310 };
311
312 nand0: nand@40000000 {
313 compatible = "atmel,at91rm9200-nand";
314 #address-cells = <1>;
315 #size-cells = <1>;
316 reg = <0x40000000 0x10000000>;
317 atmel,nand-addr-offset = <21>;
318 atmel,nand-cmd-offset = <22>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&pinctrl_nand>;
321 nand-ecc-mode = "soft";
322 gpios = <&pioC 2 0
323 0
324 &pioB 1 0
325 >;
326 status = "disabled";
327 };
328
329 usb0: ohci@00300000 {
330 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
331 reg = <0x00300000 0x100000>;
332 interrupts = <23 4 2>;
333 status = "disabled";
334 };
335 };
336
337 i2c@0 {
338 compatible = "i2c-gpio";
339 gpios = <&pioA 23 0 /* sda */
340 &pioA 24 0 /* scl */
341 >;
342 i2c-gpio,sda-open-drain;
343 i2c-gpio,scl-open-drain;
344 i2c-gpio,delay-us = <2>; /* ~100 kHz */
345 #address-cells = <1>;
346 #size-cells = <0>;
347 status = "disabled";
348 };
349};
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts
new file mode 100644
index 000000000000..8aa48931e0a2
--- /dev/null
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -0,0 +1,79 @@
1/*
2 * at91rm9200ek.dts - Device Tree file for Atmel AT91RM9200 evaluation kit
3 *
4 * Copyright (C) 2012 Joachim Eastwood <manabian@gmail.com>
5 *
6 * Licensed under GPLv2 only
7 */
8/dts-v1/;
9/include/ "at91rm9200.dtsi"
10
11/ {
12 model = "Atmel AT91RM9200 evaluation kit";
13 compatible = "atmel,at91rm9200ek", "atmel,at91rm9200";
14
15 memory {
16 reg = <0x20000000 0x4000000>;
17 };
18
19 clocks {
20 #address-cells = <1>;
21 #size-cells = <1>;
22 ranges;
23
24 main_clock: clock@0 {
25 compatible = "atmel,osc", "fixed-clock";
26 clock-frequency = <18432000>;
27 };
28 };
29
30 ahb {
31 apb {
32 dbgu: serial@fffff200 {
33 status = "okay";
34 };
35
36 usart1: serial@fffc4000 {
37 pinctrl-0 =
38 <&pinctrl_uart1
39 &pinctrl_uart1_rts
40 &pinctrl_uart1_cts
41 &pinctrl_uart1_dtr_dsr
42 &pinctrl_uart1_dcd
43 &pinctrl_uart1_ri>;
44 status = "okay";
45 };
46
47 usb1: gadget@fffb0000 {
48 atmel,vbus-gpio = <&pioD 4 0>;
49 status = "okay";
50 };
51 };
52
53 usb0: ohci@00300000 {
54 num-ports = <2>;
55 status = "okay";
56 };
57 };
58
59 leds {
60 compatible = "gpio-leds";
61
62 ds2 {
63 label = "green";
64 gpios = <&pioB 0 0x1>;
65 linux,default-trigger = "mmc0";
66 };
67
68 ds4 {
69 label = "yellow";
70 gpios = <&pioB 1 0x1>;
71 linux,default-trigger = "heartbeat";
72 };
73
74 ds6 {
75 label = "red";
76 gpios = <&pioB 2 0x1>;
77 };
78 };
79};
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index d410581a5a85..cb7bcc51608d 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -21,14 +21,15 @@
21 serial2 = &usart1; 21 serial2 = &usart1;
22 serial3 = &usart2; 22 serial3 = &usart2;
23 serial4 = &usart3; 23 serial4 = &usart3;
24 serial5 = &usart4; 24 serial5 = &uart0;
25 serial6 = &usart5; 25 serial6 = &uart1;
26 gpio0 = &pioA; 26 gpio0 = &pioA;
27 gpio1 = &pioB; 27 gpio1 = &pioB;
28 gpio2 = &pioC; 28 gpio2 = &pioC;
29 tcb0 = &tcb0; 29 tcb0 = &tcb0;
30 tcb1 = &tcb1; 30 tcb1 = &tcb1;
31 i2c0 = &i2c0; 31 i2c0 = &i2c0;
32 ssc0 = &ssc0;
32 }; 33 };
33 cpus { 34 cpus {
34 cpu@0 { 35 cpu@0 {
@@ -98,40 +99,266 @@
98 interrupts = <26 4 0 27 4 0 28 4 0>; 99 interrupts = <26 4 0 27 4 0 28 4 0>;
99 }; 100 };
100 101
101 pioA: gpio@fffff400 { 102 pinctrl@fffff400 {
102 compatible = "atmel,at91rm9200-gpio"; 103 #address-cells = <1>;
103 reg = <0xfffff400 0x100>; 104 #size-cells = <1>;
104 interrupts = <2 4 1>; 105 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
105 #gpio-cells = <2>; 106 ranges = <0xfffff400 0xfffff400 0x600>;
106 gpio-controller; 107
107 interrupt-controller; 108 atmel,mux-mask = <
108 #interrupt-cells = <2>; 109 /* A B */
109 }; 110 0xffffffff 0xffc00c3b /* pioA */
111 0xffffffff 0x7fff3ccf /* pioB */
112 0xffffffff 0x007fffff /* pioC */
113 >;
114
115 /* shared pinctrl settings */
116 dbgu {
117 pinctrl_dbgu: dbgu-0 {
118 atmel,pins =
119 <1 14 0x1 0x0 /* PB14 periph A */
120 1 15 0x1 0x1>; /* PB15 periph with pullup */
121 };
122 };
110 123
111 pioB: gpio@fffff600 { 124 usart0 {
112 compatible = "atmel,at91rm9200-gpio"; 125 pinctrl_usart0: usart0-0 {
113 reg = <0xfffff600 0x100>; 126 atmel,pins =
114 interrupts = <3 4 1>; 127 <1 4 0x1 0x0 /* PB4 periph A */
115 #gpio-cells = <2>; 128 1 5 0x1 0x0>; /* PB5 periph A */
116 gpio-controller; 129 };
117 interrupt-controller; 130
118 #interrupt-cells = <2>; 131 pinctrl_usart0_rts: usart0_rts-0 {
119 }; 132 atmel,pins =
133 <1 26 0x1 0x0>; /* PB26 periph A */
134 };
135
136 pinctrl_usart0_cts: usart0_cts-0 {
137 atmel,pins =
138 <1 27 0x1 0x0>; /* PB27 periph A */
139 };
140
141 pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
142 atmel,pins =
143 <1 24 0x1 0x0 /* PB24 periph A */
144 1 22 0x1 0x0>; /* PB22 periph A */
145 };
146
147 pinctrl_usart0_dcd: usart0_dcd-0 {
148 atmel,pins =
149 <1 23 0x1 0x0>; /* PB23 periph A */
150 };
151
152 pinctrl_usart0_ri: usart0_ri-0 {
153 atmel,pins =
154 <1 25 0x1 0x0>; /* PB25 periph A */
155 };
156 };
120 157
121 pioC: gpio@fffff800 { 158 usart1 {
122 compatible = "atmel,at91rm9200-gpio"; 159 pinctrl_usart1: usart1-0 {
123 reg = <0xfffff800 0x100>; 160 atmel,pins =
124 interrupts = <4 4 1>; 161 <2 6 0x1 0x1 /* PB6 periph A with pullup */
125 #gpio-cells = <2>; 162 2 7 0x1 0x0>; /* PB7 periph A */
126 gpio-controller; 163 };
127 interrupt-controller; 164
128 #interrupt-cells = <2>; 165 pinctrl_usart1_rts: usart1_rts-0 {
166 atmel,pins =
167 <1 28 0x1 0x0>; /* PB28 periph A */
168 };
169
170 pinctrl_usart1_cts: usart1_cts-0 {
171 atmel,pins =
172 <1 29 0x1 0x0>; /* PB29 periph A */
173 };
174 };
175
176 usart2 {
177 pinctrl_usart2: usart2-0 {
178 atmel,pins =
179 <1 8 0x1 0x1 /* PB8 periph A with pullup */
180 1 9 0x1 0x0>; /* PB9 periph A */
181 };
182
183 pinctrl_usart2_rts: usart2_rts-0 {
184 atmel,pins =
185 <0 4 0x1 0x0>; /* PA4 periph A */
186 };
187
188 pinctrl_usart2_cts: usart2_cts-0 {
189 atmel,pins =
190 <0 5 0x1 0x0>; /* PA5 periph A */
191 };
192 };
193
194 usart3 {
195 pinctrl_usart3: usart3-0 {
196 atmel,pins =
197 <2 10 0x1 0x1 /* PB10 periph A with pullup */
198 2 11 0x1 0x0>; /* PB11 periph A */
199 };
200
201 pinctrl_usart3_rts: usart3_rts-0 {
202 atmel,pins =
203 <3 8 0x2 0x0>; /* PB8 periph B */
204 };
205
206 pinctrl_usart3_cts: usart3_cts-0 {
207 atmel,pins =
208 <3 10 0x2 0x0>; /* PB10 periph B */
209 };
210 };
211
212 uart0 {
213 pinctrl_uart0: uart0-0 {
214 atmel,pins =
215 <0 31 0x2 0x1 /* PA31 periph B with pullup */
216 0 30 0x2 0x0>; /* PA30 periph B */
217 };
218 };
219
220 uart1 {
221 pinctrl_uart1: uart1-0 {
222 atmel,pins =
223 <2 12 0x1 0x1 /* PB12 periph A with pullup */
224 2 13 0x1 0x0>; /* PB13 periph A */
225 };
226 };
227
228 nand {
229 pinctrl_nand: nand-0 {
230 atmel,pins =
231 <2 13 0x0 0x1 /* PC13 gpio RDY pin pull_up */
232 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
233 };
234 };
235
236 macb {
237 pinctrl_macb_rmii: macb_rmii-0 {
238 atmel,pins =
239 <0 12 0x1 0x0 /* PA12 periph A */
240 0 13 0x1 0x0 /* PA13 periph A */
241 0 14 0x1 0x0 /* PA14 periph A */
242 0 15 0x1 0x0 /* PA15 periph A */
243 0 16 0x1 0x0 /* PA16 periph A */
244 0 17 0x1 0x0 /* PA17 periph A */
245 0 18 0x1 0x0 /* PA18 periph A */
246 0 19 0x1 0x0 /* PA19 periph A */
247 0 20 0x1 0x0 /* PA20 periph A */
248 0 21 0x1 0x0>; /* PA21 periph A */
249 };
250
251 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
252 atmel,pins =
253 <0 22 0x2 0x0 /* PA22 periph B */
254 0 23 0x2 0x0 /* PA23 periph B */
255 0 24 0x2 0x0 /* PA24 periph B */
256 0 25 0x2 0x0 /* PA25 periph B */
257 0 26 0x2 0x0 /* PA26 periph B */
258 0 27 0x2 0x0 /* PA27 periph B */
259 0 28 0x2 0x0 /* PA28 periph B */
260 0 29 0x2 0x0>; /* PA29 periph B */
261 };
262
263 pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 {
264 atmel,pins =
265 <0 10 0x2 0x0 /* PA10 periph B */
266 0 11 0x2 0x0 /* PA11 periph B */
267 0 24 0x2 0x0 /* PA24 periph B */
268 0 25 0x2 0x0 /* PA25 periph B */
269 0 26 0x2 0x0 /* PA26 periph B */
270 0 27 0x2 0x0 /* PA27 periph B */
271 0 28 0x2 0x0 /* PA28 periph B */
272 0 29 0x2 0x0>; /* PA29 periph B */
273 };
274 };
275
276 mmc0 {
277 pinctrl_mmc0_clk: mmc0_clk-0 {
278 atmel,pins =
279 <0 8 0x1 0x0>; /* PA8 periph A */
280 };
281
282 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
283 atmel,pins =
284 <0 7 0x1 0x1 /* PA7 periph A with pullup */
285 0 6 0x1 0x1>; /* PA6 periph A with pullup */
286 };
287
288 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
289 atmel,pins =
290 <0 9 0x1 0x1 /* PA9 periph A with pullup */
291 0 10 0x1 0x1 /* PA10 periph A with pullup */
292 0 11 0x1 0x1>; /* PA11 periph A with pullup */
293 };
294
295 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
296 atmel,pins =
297 <0 1 0x2 0x1 /* PA1 periph B with pullup */
298 0 0 0x2 0x1>; /* PA0 periph B with pullup */
299 };
300
301 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
302 atmel,pins =
303 <0 5 0x2 0x1 /* PA5 periph B with pullup */
304 0 4 0x2 0x1 /* PA4 periph B with pullup */
305 0 3 0x2 0x1>; /* PA3 periph B with pullup */
306 };
307 };
308
309 ssc0 {
310 pinctrl_ssc0_tx: ssc0_tx-0 {
311 atmel,pins =
312 <1 16 0x1 0x0 /* PB16 periph A */
313 1 17 0x1 0x0 /* PB17 periph A */
314 1 18 0x1 0x0>; /* PB18 periph A */
315 };
316
317 pinctrl_ssc0_rx: ssc0_rx-0 {
318 atmel,pins =
319 <1 19 0x1 0x0 /* PB19 periph A */
320 1 20 0x1 0x0 /* PB20 periph A */
321 1 21 0x1 0x0>; /* PB21 periph A */
322 };
323 };
324
325 pioA: gpio@fffff400 {
326 compatible = "atmel,at91rm9200-gpio";
327 reg = <0xfffff400 0x200>;
328 interrupts = <2 4 1>;
329 #gpio-cells = <2>;
330 gpio-controller;
331 interrupt-controller;
332 #interrupt-cells = <2>;
333 };
334
335 pioB: gpio@fffff600 {
336 compatible = "atmel,at91rm9200-gpio";
337 reg = <0xfffff600 0x200>;
338 interrupts = <3 4 1>;
339 #gpio-cells = <2>;
340 gpio-controller;
341 interrupt-controller;
342 #interrupt-cells = <2>;
343 };
344
345 pioC: gpio@fffff800 {
346 compatible = "atmel,at91rm9200-gpio";
347 reg = <0xfffff800 0x200>;
348 interrupts = <4 4 1>;
349 #gpio-cells = <2>;
350 gpio-controller;
351 interrupt-controller;
352 #interrupt-cells = <2>;
353 };
129 }; 354 };
130 355
131 dbgu: serial@fffff200 { 356 dbgu: serial@fffff200 {
132 compatible = "atmel,at91sam9260-usart"; 357 compatible = "atmel,at91sam9260-usart";
133 reg = <0xfffff200 0x200>; 358 reg = <0xfffff200 0x200>;
134 interrupts = <1 4 7>; 359 interrupts = <1 4 7>;
360 pinctrl-names = "default";
361 pinctrl-0 = <&pinctrl_dbgu>;
135 status = "disabled"; 362 status = "disabled";
136 }; 363 };
137 364
@@ -141,6 +368,8 @@
141 interrupts = <6 4 5>; 368 interrupts = <6 4 5>;
142 atmel,use-dma-rx; 369 atmel,use-dma-rx;
143 atmel,use-dma-tx; 370 atmel,use-dma-tx;
371 pinctrl-names = "default";
372 pinctrl-0 = <&pinctrl_usart0>;
144 status = "disabled"; 373 status = "disabled";
145 }; 374 };
146 375
@@ -150,6 +379,8 @@
150 interrupts = <7 4 5>; 379 interrupts = <7 4 5>;
151 atmel,use-dma-rx; 380 atmel,use-dma-rx;
152 atmel,use-dma-tx; 381 atmel,use-dma-tx;
382 pinctrl-names = "default";
383 pinctrl-0 = <&pinctrl_usart1>;
153 status = "disabled"; 384 status = "disabled";
154 }; 385 };
155 386
@@ -159,6 +390,8 @@
159 interrupts = <8 4 5>; 390 interrupts = <8 4 5>;
160 atmel,use-dma-rx; 391 atmel,use-dma-rx;
161 atmel,use-dma-tx; 392 atmel,use-dma-tx;
393 pinctrl-names = "default";
394 pinctrl-0 = <&pinctrl_usart2>;
162 status = "disabled"; 395 status = "disabled";
163 }; 396 };
164 397
@@ -168,24 +401,30 @@
168 interrupts = <23 4 5>; 401 interrupts = <23 4 5>;
169 atmel,use-dma-rx; 402 atmel,use-dma-rx;
170 atmel,use-dma-tx; 403 atmel,use-dma-tx;
404 pinctrl-names = "default";
405 pinctrl-0 = <&pinctrl_usart3>;
171 status = "disabled"; 406 status = "disabled";
172 }; 407 };
173 408
174 usart4: serial@fffd4000 { 409 uart0: serial@fffd4000 {
175 compatible = "atmel,at91sam9260-usart"; 410 compatible = "atmel,at91sam9260-usart";
176 reg = <0xfffd4000 0x200>; 411 reg = <0xfffd4000 0x200>;
177 interrupts = <24 4 5>; 412 interrupts = <24 4 5>;
178 atmel,use-dma-rx; 413 atmel,use-dma-rx;
179 atmel,use-dma-tx; 414 atmel,use-dma-tx;
415 pinctrl-names = "default";
416 pinctrl-0 = <&pinctrl_uart0>;
180 status = "disabled"; 417 status = "disabled";
181 }; 418 };
182 419
183 usart5: serial@fffd8000 { 420 uart1: serial@fffd8000 {
184 compatible = "atmel,at91sam9260-usart"; 421 compatible = "atmel,at91sam9260-usart";
185 reg = <0xfffd8000 0x200>; 422 reg = <0xfffd8000 0x200>;
186 interrupts = <25 4 5>; 423 interrupts = <25 4 5>;
187 atmel,use-dma-rx; 424 atmel,use-dma-rx;
188 atmel,use-dma-tx; 425 atmel,use-dma-tx;
426 pinctrl-names = "default";
427 pinctrl-0 = <&pinctrl_uart1>;
189 status = "disabled"; 428 status = "disabled";
190 }; 429 };
191 430
@@ -193,6 +432,8 @@
193 compatible = "cdns,at32ap7000-macb", "cdns,macb"; 432 compatible = "cdns,at32ap7000-macb", "cdns,macb";
194 reg = <0xfffc4000 0x100>; 433 reg = <0xfffc4000 0x100>;
195 interrupts = <21 4 3>; 434 interrupts = <21 4 3>;
435 pinctrl-names = "default";
436 pinctrl-0 = <&pinctrl_macb_rmii>;
196 status = "disabled"; 437 status = "disabled";
197 }; 438 };
198 439
@@ -212,6 +453,24 @@
212 status = "disabled"; 453 status = "disabled";
213 }; 454 };
214 455
456 mmc0: mmc@fffa8000 {
457 compatible = "atmel,hsmci";
458 reg = <0xfffa8000 0x600>;
459 interrupts = <9 4 0>;
460 #address-cells = <1>;
461 #size-cells = <0>;
462 status = "disabled";
463 };
464
465 ssc0: ssc@fffbc000 {
466 compatible = "atmel,at91rm9200-ssc";
467 reg = <0xfffbc000 0x4000>;
468 interrupts = <14 4 5>;
469 pinctrl-names = "default";
470 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
471 status = "disabled";
472 };
473
215 adc0: adc@fffe0000 { 474 adc0: adc@fffe0000 {
216 compatible = "atmel,at91sam9260-adc"; 475 compatible = "atmel,at91sam9260-adc";
217 reg = <0xfffe0000 0x100>; 476 reg = <0xfffe0000 0x100>;
@@ -246,6 +505,12 @@
246 trigger-external; 505 trigger-external;
247 }; 506 };
248 }; 507 };
508
509 watchdog@fffffd40 {
510 compatible = "atmel,at91sam9260-wdt";
511 reg = <0xfffffd40 0x10>;
512 status = "disabled";
513 };
249 }; 514 };
250 515
251 nand0: nand@40000000 { 516 nand0: nand@40000000 {
@@ -257,6 +522,8 @@
257 >; 522 >;
258 atmel,nand-addr-offset = <21>; 523 atmel,nand-addr-offset = <21>;
259 atmel,nand-cmd-offset = <22>; 524 atmel,nand-cmd-offset = <22>;
525 pinctrl-names = "default";
526 pinctrl-0 = <&pinctrl_nand>;
260 gpios = <&pioC 13 0 527 gpios = <&pioC 13 0
261 &pioC 14 0 528 &pioC 14 0
262 0 529 0
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 3e6e5c1abbf3..271d4de026e9 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -25,6 +25,8 @@
25 gpio4 = &pioE; 25 gpio4 = &pioE;
26 tcb0 = &tcb0; 26 tcb0 = &tcb0;
27 i2c0 = &i2c0; 27 i2c0 = &i2c0;
28 ssc0 = &ssc0;
29 ssc1 = &ssc1;
28 }; 30 };
29 cpus { 31 cpus {
30 cpu@0 { 32 cpu@0 {
@@ -89,60 +91,275 @@
89 reg = <0xfffffd10 0x10>; 91 reg = <0xfffffd10 0x10>;
90 }; 92 };
91 93
92 pioA: gpio@fffff200 { 94 pinctrl@fffff200 {
93 compatible = "atmel,at91rm9200-gpio"; 95 #address-cells = <1>;
94 reg = <0xfffff200 0x100>; 96 #size-cells = <1>;
95 interrupts = <2 4 1>; 97 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
96 #gpio-cells = <2>; 98 ranges = <0xfffff200 0xfffff200 0xa00>;
97 gpio-controller;
98 interrupt-controller;
99 #interrupt-cells = <2>;
100 };
101 99
102 pioB: gpio@fffff400 { 100 atmel,mux-mask = <
103 compatible = "atmel,at91rm9200-gpio"; 101 /* A B */
104 reg = <0xfffff400 0x100>; 102 0xfffffffb 0xffffe07f /* pioA */
105 interrupts = <3 4 1>; 103 0x0007ffff 0x39072fff /* pioB */
106 #gpio-cells = <2>; 104 0xffffffff 0x3ffffff8 /* pioC */
107 gpio-controller; 105 0xfffffbff 0xffffffff /* pioD */
108 interrupt-controller; 106 0xffe00fff 0xfbfcff00 /* pioE */
109 #interrupt-cells = <2>; 107 >;
110 };
111 108
112 pioC: gpio@fffff600 { 109 /* shared pinctrl settings */
113 compatible = "atmel,at91rm9200-gpio"; 110 dbgu {
114 reg = <0xfffff600 0x100>; 111 pinctrl_dbgu: dbgu-0 {
115 interrupts = <4 4 1>; 112 atmel,pins =
116 #gpio-cells = <2>; 113 <2 30 0x1 0x0 /* PC30 periph A */
117 gpio-controller; 114 2 31 0x1 0x1>; /* PC31 periph with pullup */
118 interrupt-controller; 115 };
119 #interrupt-cells = <2>; 116 };
120 };
121 117
122 pioD: gpio@fffff800 { 118 usart0 {
123 compatible = "atmel,at91rm9200-gpio"; 119 pinctrl_usart0: usart0-0 {
124 reg = <0xfffff800 0x100>; 120 atmel,pins =
125 interrupts = <4 4 1>; 121 <0 26 0x1 0x1 /* PA26 periph A with pullup */
126 #gpio-cells = <2>; 122 0 27 0x1 0x0>; /* PA27 periph A */
127 gpio-controller; 123 };
128 interrupt-controller;
129 #interrupt-cells = <2>;
130 };
131 124
132 pioE: gpio@fffffa00 { 125 pinctrl_usart0_rts: usart0_rts-0 {
133 compatible = "atmel,at91rm9200-gpio"; 126 atmel,pins =
134 reg = <0xfffffa00 0x100>; 127 <0 28 0x1 0x0>; /* PA28 periph A */
135 interrupts = <4 4 1>; 128 };
136 #gpio-cells = <2>; 129
137 gpio-controller; 130 pinctrl_usart0_cts: usart0_cts-0 {
138 interrupt-controller; 131 atmel,pins =
139 #interrupt-cells = <2>; 132 <0 29 0x1 0x0>; /* PA29 periph A */
133 };
134 };
135
136 usart1 {
137 pinctrl_usart1: usart1-0 {
138 atmel,pins =
139 <3 0 0x1 0x1 /* PD0 periph A with pullup */
140 3 1 0x1 0x0>; /* PD1 periph A */
141 };
142
143 pinctrl_usart1_rts: usart1_rts-0 {
144 atmel,pins =
145 <3 7 0x2 0x0>; /* PD7 periph B */
146 };
147
148 pinctrl_usart1_cts: usart1_cts-0 {
149 atmel,pins =
150 <3 8 0x2 0x0>; /* PD8 periph B */
151 };
152 };
153
154 usart2 {
155 pinctrl_usart2: usart2-0 {
156 atmel,pins =
157 <3 2 0x1 0x1 /* PD2 periph A with pullup */
158 3 3 0x1 0x0>; /* PD3 periph A */
159 };
160
161 pinctrl_usart2_rts: usart2_rts-0 {
162 atmel,pins =
163 <3 5 0x2 0x0>; /* PD5 periph B */
164 };
165
166 pinctrl_usart2_cts: usart2_cts-0 {
167 atmel,pins =
168 <4 6 0x2 0x0>; /* PD6 periph B */
169 };
170 };
171
172 nand {
173 pinctrl_nand: nand-0 {
174 atmel,pins =
175 <0 22 0x0 0x1 /* PA22 gpio RDY pin pull_up*/
176 3 15 0x0 0x1>; /* PD15 gpio enable pin pull_up */
177 };
178 };
179
180 macb {
181 pinctrl_macb_rmii: macb_rmii-0 {
182 atmel,pins =
183 <2 25 0x2 0x0 /* PC25 periph B */
184 4 21 0x1 0x0 /* PE21 periph A */
185 4 23 0x1 0x0 /* PE23 periph A */
186 4 24 0x1 0x0 /* PE24 periph A */
187 4 25 0x1 0x0 /* PE25 periph A */
188 4 26 0x1 0x0 /* PE26 periph A */
189 4 27 0x1 0x0 /* PE27 periph A */
190 4 28 0x1 0x0 /* PE28 periph A */
191 4 29 0x1 0x0 /* PE29 periph A */
192 4 30 0x1 0x0>; /* PE30 periph A */
193 };
194
195 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
196 atmel,pins =
197 <2 20 0x2 0x0 /* PC20 periph B */
198 2 21 0x2 0x0 /* PC21 periph B */
199 2 22 0x2 0x0 /* PC22 periph B */
200 2 23 0x2 0x0 /* PC23 periph B */
201 2 24 0x2 0x0 /* PC24 periph B */
202 2 25 0x2 0x0 /* PC25 periph B */
203 2 27 0x2 0x0 /* PC27 periph B */
204 4 22 0x2 0x0>; /* PE22 periph B */
205 };
206 };
207
208 mmc0 {
209 pinctrl_mmc0_clk: mmc0_clk-0 {
210 atmel,pins =
211 <0 12 0x1 0x0>; /* PA12 periph A */
212 };
213
214 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
215 atmel,pins =
216 <0 1 0x1 0x1 /* PA1 periph A with pullup */
217 0 0 0x1 0x1>; /* PA0 periph A with pullup */
218 };
219
220 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
221 atmel,pins =
222 <0 3 0x1 0x1 /* PA3 periph A with pullup */
223 0 4 0x1 0x1 /* PA4 periph A with pullup */
224 0 5 0x1 0x1>; /* PA5 periph A with pullup */
225 };
226
227 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
228 atmel,pins =
229 <0 16 0x1 0x1 /* PA16 periph A with pullup */
230 0 17 0x1 0x1>; /* PA17 periph A with pullup */
231 };
232
233 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
234 atmel,pins =
235 <0 18 0x1 0x1 /* PA18 periph A with pullup */
236 0 19 0x1 0x1 /* PA19 periph A with pullup */
237 0 20 0x1 0x1>; /* PA20 periph A with pullup */
238 };
239 };
240
241 mmc1 {
242 pinctrl_mmc1_clk: mmc1_clk-0 {
243 atmel,pins =
244 <0 6 0x1 0x0>; /* PA6 periph A */
245 };
246
247 pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 {
248 atmel,pins =
249 <0 7 0x1 0x1 /* PA7 periph A with pullup */
250 0 8 0x1 0x1>; /* PA8 periph A with pullup */
251 };
252
253 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
254 atmel,pins =
255 <0 9 0x1 0x1 /* PA9 periph A with pullup */
256 0 10 0x1 0x1 /* PA10 periph A with pullup */
257 0 11 0x1 0x1>; /* PA11 periph A with pullup */
258 };
259
260 pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 {
261 atmel,pins =
262 <0 21 0x1 0x1 /* PA21 periph A with pullup */
263 0 22 0x1 0x1>; /* PA22 periph A with pullup */
264 };
265
266 pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 {
267 atmel,pins =
268 <0 23 0x1 0x1 /* PA23 periph A with pullup */
269 0 24 0x1 0x1 /* PA24 periph A with pullup */
270 0 25 0x1 0x1>; /* PA25 periph A with pullup */
271 };
272 };
273
274 ssc0 {
275 pinctrl_ssc0_tx: ssc0_tx-0 {
276 atmel,pins =
277 <1 0 0x2 0x0 /* PB0 periph B */
278 1 1 0x2 0x0 /* PB1 periph B */
279 1 2 0x2 0x0>; /* PB2 periph B */
280 };
281
282 pinctrl_ssc0_rx: ssc0_rx-0 {
283 atmel,pins =
284 <1 3 0x2 0x0 /* PB3 periph B */
285 1 4 0x2 0x0 /* PB4 periph B */
286 1 5 0x2 0x0>; /* PB5 periph B */
287 };
288 };
289
290 ssc1 {
291 pinctrl_ssc1_tx: ssc1_tx-0 {
292 atmel,pins =
293 <1 6 0x1 0x0 /* PB6 periph A */
294 1 7 0x1 0x0 /* PB7 periph A */
295 1 8 0x1 0x0>; /* PB8 periph A */
296 };
297
298 pinctrl_ssc1_rx: ssc1_rx-0 {
299 atmel,pins =
300 <1 9 0x1 0x0 /* PB9 periph A */
301 1 10 0x1 0x0 /* PB10 periph A */
302 1 11 0x1 0x0>; /* PB11 periph A */
303 };
304 };
305
306 pioA: gpio@fffff200 {
307 compatible = "atmel,at91rm9200-gpio";
308 reg = <0xfffff200 0x200>;
309 interrupts = <2 4 1>;
310 #gpio-cells = <2>;
311 gpio-controller;
312 interrupt-controller;
313 #interrupt-cells = <2>;
314 };
315
316 pioB: gpio@fffff400 {
317 compatible = "atmel,at91rm9200-gpio";
318 reg = <0xfffff400 0x200>;
319 interrupts = <3 4 1>;
320 #gpio-cells = <2>;
321 gpio-controller;
322 interrupt-controller;
323 #interrupt-cells = <2>;
324 };
325
326 pioC: gpio@fffff600 {
327 compatible = "atmel,at91rm9200-gpio";
328 reg = <0xfffff600 0x200>;
329 interrupts = <4 4 1>;
330 #gpio-cells = <2>;
331 gpio-controller;
332 interrupt-controller;
333 #interrupt-cells = <2>;
334 };
335
336 pioD: gpio@fffff800 {
337 compatible = "atmel,at91rm9200-gpio";
338 reg = <0xfffff800 0x200>;
339 interrupts = <4 4 1>;
340 #gpio-cells = <2>;
341 gpio-controller;
342 interrupt-controller;
343 #interrupt-cells = <2>;
344 };
345
346 pioE: gpio@fffffa00 {
347 compatible = "atmel,at91rm9200-gpio";
348 reg = <0xfffffa00 0x200>;
349 interrupts = <4 4 1>;
350 #gpio-cells = <2>;
351 gpio-controller;
352 interrupt-controller;
353 #interrupt-cells = <2>;
354 };
140 }; 355 };
141 356
142 dbgu: serial@ffffee00 { 357 dbgu: serial@ffffee00 {
143 compatible = "atmel,at91sam9260-usart"; 358 compatible = "atmel,at91sam9260-usart";
144 reg = <0xffffee00 0x200>; 359 reg = <0xffffee00 0x200>;
145 interrupts = <1 4 7>; 360 interrupts = <1 4 7>;
361 pinctrl-names = "default";
362 pinctrl-0 = <&pinctrl_dbgu>;
146 status = "disabled"; 363 status = "disabled";
147 }; 364 };
148 365
@@ -152,6 +369,8 @@
152 interrupts = <7 4 5>; 369 interrupts = <7 4 5>;
153 atmel,use-dma-rx; 370 atmel,use-dma-rx;
154 atmel,use-dma-tx; 371 atmel,use-dma-tx;
372 pinctrl-names = "default";
373 pinctrl-0 = <&pinctrl_usart0>;
155 status = "disabled"; 374 status = "disabled";
156 }; 375 };
157 376
@@ -161,6 +380,8 @@
161 interrupts = <8 4 5>; 380 interrupts = <8 4 5>;
162 atmel,use-dma-rx; 381 atmel,use-dma-rx;
163 atmel,use-dma-tx; 382 atmel,use-dma-tx;
383 pinctrl-names = "default";
384 pinctrl-0 = <&pinctrl_usart1>;
164 status = "disabled"; 385 status = "disabled";
165 }; 386 };
166 387
@@ -170,6 +391,26 @@
170 interrupts = <9 4 5>; 391 interrupts = <9 4 5>;
171 atmel,use-dma-rx; 392 atmel,use-dma-rx;
172 atmel,use-dma-tx; 393 atmel,use-dma-tx;
394 pinctrl-names = "default";
395 pinctrl-0 = <&pinctrl_usart2>;
396 status = "disabled";
397 };
398
399 ssc0: ssc@fff98000 {
400 compatible = "atmel,at91rm9200-ssc";
401 reg = <0xfff98000 0x4000>;
402 interrupts = <16 4 5>;
403 pinctrl-names = "default";
404 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
405 status = "disabled";
406 };
407
408 ssc1: ssc@fff9c000 {
409 compatible = "atmel,at91rm9200-ssc";
410 reg = <0xfff9c000 0x4000>;
411 interrupts = <17 4 5>;
412 pinctrl-names = "default";
413 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
173 status = "disabled"; 414 status = "disabled";
174 }; 415 };
175 416
@@ -177,6 +418,8 @@
177 compatible = "cdns,at32ap7000-macb", "cdns,macb"; 418 compatible = "cdns,at32ap7000-macb", "cdns,macb";
178 reg = <0xfffbc000 0x100>; 419 reg = <0xfffbc000 0x100>;
179 interrupts = <21 4 3>; 420 interrupts = <21 4 3>;
421 pinctrl-names = "default";
422 pinctrl-0 = <&pinctrl_macb_rmii>;
180 status = "disabled"; 423 status = "disabled";
181 }; 424 };
182 425
@@ -195,6 +438,30 @@
195 #size-cells = <0>; 438 #size-cells = <0>;
196 status = "disabled"; 439 status = "disabled";
197 }; 440 };
441
442 mmc0: mmc@fff80000 {
443 compatible = "atmel,hsmci";
444 reg = <0xfff80000 0x600>;
445 interrupts = <10 4 0>;
446 #address-cells = <1>;
447 #size-cells = <0>;
448 status = "disabled";
449 };
450
451 mmc1: mmc@fff84000 {
452 compatible = "atmel,hsmci";
453 reg = <0xfff84000 0x600>;
454 interrupts = <11 4 0>;
455 #address-cells = <1>;
456 #size-cells = <0>;
457 status = "disabled";
458 };
459
460 watchdog@fffffd40 {
461 compatible = "atmel,at91sam9260-wdt";
462 reg = <0xfffffd40 0x10>;
463 status = "disabled";
464 };
198 }; 465 };
199 466
200 nand0: nand@40000000 { 467 nand0: nand@40000000 {
@@ -206,6 +473,8 @@
206 >; 473 >;
207 atmel,nand-addr-offset = <21>; 474 atmel,nand-addr-offset = <21>;
208 atmel,nand-cmd-offset = <22>; 475 atmel,nand-cmd-offset = <22>;
476 pinctrl-names = "default";
477 pinctrl-0 = <&pinctrl_nand>;
209 gpios = <&pioA 22 0 478 gpios = <&pioA 22 0
210 &pioD 15 0 479 &pioD 15 0
211 0 480 0
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index f86ac4b609fc..1eb08728f527 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -38,6 +38,10 @@
38 }; 38 };
39 39
40 usart0: serial@fff8c000 { 40 usart0: serial@fff8c000 {
41 pinctrl-0 = <
42 &pinctrl_usart0
43 &pinctrl_usart0_rts
44 &pinctrl_usart0_cts>;
41 status = "okay"; 45 status = "okay";
42 }; 46 };
43 47
@@ -50,6 +54,31 @@
50 atmel,vbus-gpio = <&pioA 25 0>; 54 atmel,vbus-gpio = <&pioA 25 0>;
51 status = "okay"; 55 status = "okay";
52 }; 56 };
57
58 mmc0: mmc@fff80000 {
59 pinctrl-0 = <
60 &pinctrl_board_mmc0
61 &pinctrl_mmc0_clk
62 &pinctrl_mmc0_slot0_cmd_dat0
63 &pinctrl_mmc0_slot0_dat1_3>;
64 status = "okay";
65 slot@0 {
66 reg = <0>;
67 bus-width = <4>;
68 cd-gpios = <&pioE 18 0>;
69 wp-gpios = <&pioE 19 0>;
70 };
71 };
72
73 pinctrl@fffff200 {
74 mmc0 {
75 pinctrl_board_mmc0: mmc0-board {
76 atmel,pins =
77 <5 18 0x0 0x5 /* PE18 gpio CD pin pull up and deglitch */
78 5 19 0x0 0x1>; /* PE19 gpio WP pin pull up */
79 };
80 };
81 };
53 }; 82 };
54 83
55 nand0: nand@40000000 { 84 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/at91sam9g15.dtsi
new file mode 100644
index 000000000000..fbe7a7089c2a
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g15.dtsi
@@ -0,0 +1,28 @@
1/*
2 * at91sam9g15.dtsi - Device Tree Include file for AT91SAM9G15 SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/include/ "at91sam9x5.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9G15 SoC";
13 compatible = "atmel, at91sam9g15, atmel,at91sam9x5";
14
15 ahb {
16 apb {
17 pinctrl@fffff400 {
18 atmel,mux-mask = <
19 /* A B C */
20 0xffffffff 0xffe0399f 0x00000000 /* pioA */
21 0x00040000 0x00047e3f 0x00000000 /* pioB */
22 0xfdffffff 0x00000000 0xb83fffff /* pioC */
23 0x003fffff 0x003f8000 0x00000000 /* pioD */
24 >;
25 };
26 };
27 };
28};
diff --git a/arch/arm/boot/dts/at91sam9g15ek.dts b/arch/arm/boot/dts/at91sam9g15ek.dts
new file mode 100644
index 000000000000..86dd3f6d938f
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g15ek.dts
@@ -0,0 +1,16 @@
1/*
2 * at91sam9g15ek.dts - Device Tree file for AT91SAM9G15-EK board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9g15.dtsi"
11/include/ "at91sam9x5ek.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9G25-EK";
15 compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16};
diff --git a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
index f1b2e148ac8c..66467b113126 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
+++ b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
@@ -12,6 +12,32 @@
12 model = "Atmel at91sam9g20ek 2 mmc"; 12 model = "Atmel at91sam9g20ek 2 mmc";
13 compatible = "atmel,at91sam9g20ek_2mmc", "atmel,at91sam9g20", "atmel,at91sam9"; 13 compatible = "atmel,at91sam9g20ek_2mmc", "atmel,at91sam9g20", "atmel,at91sam9";
14 14
15 ahb {
16 apb{
17 mmc0: mmc@fffa8000 {
18 /* clk already mux wuth slot0 */
19 pinctrl-0 = <
20 &pinctrl_board_mmc0_slot0
21 &pinctrl_mmc0_slot0_cmd_dat0
22 &pinctrl_mmc0_slot0_dat1_3>;
23 slot@0 {
24 reg = <0>;
25 bus-width = <4>;
26 cd-gpios = <&pioC 2 0>;
27 };
28 };
29
30 pinctrl@fffff400 {
31 mmc0_slot0 {
32 pinctrl_board_mmc0_slot0: mmc0_slot0-board {
33 atmel,pins =
34 <2 2 0x0 0x5>; /* PC2 gpio CD pin pull up and deglitch */
35 };
36 };
37 };
38 };
39 };
40
15 leds { 41 leds {
16 compatible = "gpio-leds"; 42 compatible = "gpio-leds";
17 43
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index e6391a4e6649..da15e83e7f17 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -30,11 +30,28 @@
30 30
31 ahb { 31 ahb {
32 apb { 32 apb {
33 pinctrl@fffff400 {
34 board {
35 pinctrl_pck0_as_mck: pck0_as_mck {
36 atmel,pins =
37 <2 1 0x2 0x0>; /* PC1 periph B */
38 };
39
40 };
41 };
42
33 dbgu: serial@fffff200 { 43 dbgu: serial@fffff200 {
34 status = "okay"; 44 status = "okay";
35 }; 45 };
36 46
37 usart0: serial@fffb0000 { 47 usart0: serial@fffb0000 {
48 pinctrl-0 =
49 <&pinctrl_usart0
50 &pinctrl_usart0_rts
51 &pinctrl_usart0_cts
52 &pinctrl_usart0_dtr_dsr
53 &pinctrl_usart0_dcd
54 &pinctrl_usart0_ri>;
38 status = "okay"; 55 status = "okay";
39 }; 56 };
40 57
@@ -51,6 +68,34 @@
51 atmel,vbus-gpio = <&pioC 5 0>; 68 atmel,vbus-gpio = <&pioC 5 0>;
52 status = "okay"; 69 status = "okay";
53 }; 70 };
71
72 mmc0: mmc@fffa8000 {
73 pinctrl-0 = <
74 &pinctrl_board_mmc0_slot1
75 &pinctrl_mmc0_clk
76 &pinctrl_mmc0_slot1_cmd_dat0
77 &pinctrl_mmc0_slot1_dat1_3>;
78 status = "okay";
79 slot@1 {
80 reg = <1>;
81 bus-width = <4>;
82 cd-gpios = <&pioC 9 0>;
83 };
84 };
85
86 pinctrl@fffff400 {
87 mmc0_slot1 {
88 pinctrl_board_mmc0_slot1: mmc0_slot1-board {
89 atmel,pins =
90 <2 9 0x0 0x5>; /* PC9 gpio CD pin pull up and deglitch */
91 };
92 };
93 };
94
95 ssc0: ssc@fffbc000 {
96 status = "okay";
97 pinctrl-0 = <&pinctrl_ssc0_tx>;
98 };
54 }; 99 };
55 100
56 nand0: nand@40000000 { 101 nand0: nand@40000000 {
@@ -114,7 +159,7 @@
114 reg = <0x50>; 159 reg = <0x50>;
115 }; 160 };
116 161
117 wm8731@1b { 162 wm8731: wm8731@1b {
118 compatible = "wm8731"; 163 compatible = "wm8731";
119 reg = <0x1b>; 164 reg = <0x1b>;
120 }; 165 };
@@ -139,4 +184,19 @@
139 gpio-key,wakeup; 184 gpio-key,wakeup;
140 }; 185 };
141 }; 186 };
187
188 sound {
189 compatible = "atmel,at91sam9g20ek-wm8731-audio";
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_pck0_as_mck>;
192
193 atmel,model = "wm8731 @ AT91SAMG20EK";
194
195 atmel,audio-routing =
196 "Ext Spk", "LHPOUT",
197 "Int Mic", "MICIN";
198
199 atmel,ssc-controller = <&ssc0>;
200 atmel,audio-codec = <&wm8731>;
201 };
142}; 202};
diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi
new file mode 100644
index 000000000000..05a718fb83c4
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g25.dtsi
@@ -0,0 +1,28 @@
1/*
2 * at91sam9g25.dtsi - Device Tree Include file for AT91SAM9G25 SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/include/ "at91sam9x5.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9G25 SoC";
13 compatible = "atmel, at91sam9g25, atmel,at91sam9x5";
14
15 ahb {
16 apb {
17 pinctrl@fffff400 {
18 atmel,mux-mask = <
19 /* A B C */
20 0xffffffff 0xffe0399f 0xc000001c /* pioA */
21 0x0007ffff 0x8000fe3f 0x00000000 /* pioB */
22 0x80000000 0x07c0ffff 0xb83fffff /* pioC */
23 0x003fffff 0x003f8000 0x00000000 /* pioD */
24 >;
25 };
26 };
27 };
28};
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index 877c08f06763..c5ab16fba059 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -7,55 +7,10 @@
7 * Licensed under GPLv2 or later. 7 * Licensed under GPLv2 or later.
8 */ 8 */
9/dts-v1/; 9/dts-v1/;
10/include/ "at91sam9x5.dtsi" 10/include/ "at91sam9g25.dtsi"
11/include/ "at91sam9x5cm.dtsi" 11/include/ "at91sam9x5ek.dtsi"
12 12
13/ { 13/ {
14 model = "Atmel AT91SAM9G25-EK"; 14 model = "Atmel AT91SAM9G25-EK";
15 compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; 15 compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16
17 chosen {
18 bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
19 };
20
21 ahb {
22 apb {
23 dbgu: serial@fffff200 {
24 status = "okay";
25 };
26
27 usart0: serial@f801c000 {
28 status = "okay";
29 };
30
31 macb0: ethernet@f802c000 {
32 phy-mode = "rmii";
33 status = "okay";
34 };
35
36 i2c0: i2c@f8010000 {
37 status = "okay";
38 };
39
40 i2c1: i2c@f8014000 {
41 status = "okay";
42 };
43
44 i2c2: i2c@f8018000 {
45 status = "okay";
46 };
47 };
48
49 usb0: ohci@00600000 {
50 status = "okay";
51 num-ports = <2>;
52 atmel,vbus-gpio = <&pioD 19 1
53 &pioD 20 1
54 >;
55 };
56
57 usb1: ehci@00700000 {
58 status = "okay";
59 };
60 };
61}; 16};
diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi
new file mode 100644
index 000000000000..f9d14a722794
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g35.dtsi
@@ -0,0 +1,28 @@
1/*
2 * at91sam9g35.dtsi - Device Tree Include file for AT91SAM9G35 SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/include/ "at91sam9x5.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9G35 SoC";
13 compatible = "atmel, at91sam9g35, atmel,at91sam9x5";
14
15 ahb {
16 apb {
17 pinctrl@fffff400 {
18 atmel,mux-mask = <
19 /* A B C */
20 0xffffffff 0xffe0399f 0xc000000c /* pioA */
21 0x000406ff 0x00047e3f 0x00000000 /* pioB */
22 0xfdffffff 0x00000000 0xb83fffff /* pioC */
23 0x003fffff 0x003f8000 0x00000000 /* pioD */
24 >;
25 };
26 };
27 };
28};
diff --git a/arch/arm/boot/dts/at91sam9g35ek.dts b/arch/arm/boot/dts/at91sam9g35ek.dts
new file mode 100644
index 000000000000..95944bdd798d
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g35ek.dts
@@ -0,0 +1,16 @@
1/*
2 * at91sam9g35ek.dts - Device Tree file for AT91SAM9G35-EK board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9g35.dtsi"
11/include/ "at91sam9x5ek.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9G35-EK";
15 compatible = "atmel,at91sam9g35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 3add030d61f8..6b1d4cab24c2 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -31,6 +31,8 @@
31 tcb1 = &tcb1; 31 tcb1 = &tcb1;
32 i2c0 = &i2c0; 32 i2c0 = &i2c0;
33 i2c1 = &i2c1; 33 i2c1 = &i2c1;
34 ssc0 = &ssc0;
35 ssc1 = &ssc1;
34 }; 36 };
35 cpus { 37 cpus {
36 cpu@0 { 38 cpu@0 {
@@ -108,60 +110,275 @@
108 interrupts = <21 4 0>; 110 interrupts = <21 4 0>;
109 }; 111 };
110 112
111 pioA: gpio@fffff200 { 113 pinctrl@fffff200 {
112 compatible = "atmel,at91rm9200-gpio"; 114 #address-cells = <1>;
113 reg = <0xfffff200 0x100>; 115 #size-cells = <1>;
114 interrupts = <2 4 1>; 116 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
115 #gpio-cells = <2>; 117 ranges = <0xfffff200 0xfffff200 0xa00>;
116 gpio-controller; 118
117 interrupt-controller; 119 atmel,mux-mask = <
118 #interrupt-cells = <2>; 120 /* A B */
119 }; 121 0xffffffff 0xffc003ff /* pioA */
122 0xffffffff 0x800f8f00 /* pioB */
123 0xffffffff 0x00000e00 /* pioC */
124 0xffffffff 0xff0c1381 /* pioD */
125 0xffffffff 0x81ffff81 /* pioE */
126 >;
127
128 /* shared pinctrl settings */
129 dbgu {
130 pinctrl_dbgu: dbgu-0 {
131 atmel,pins =
132 <1 12 0x1 0x0 /* PB12 periph A */
133 1 13 0x1 0x0>; /* PB13 periph A */
134 };
135 };
120 136
121 pioB: gpio@fffff400 { 137 usart0 {
122 compatible = "atmel,at91rm9200-gpio"; 138 pinctrl_usart0: usart0-0 {
123 reg = <0xfffff400 0x100>; 139 atmel,pins =
124 interrupts = <3 4 1>; 140 <1 19 0x1 0x1 /* PB19 periph A with pullup */
125 #gpio-cells = <2>; 141 1 18 0x1 0x0>; /* PB18 periph A */
126 gpio-controller; 142 };
127 interrupt-controller; 143
128 #interrupt-cells = <2>; 144 pinctrl_usart0_rts: usart0_rts-0 {
129 }; 145 atmel,pins =
146 <1 17 0x2 0x0>; /* PB17 periph B */
147 };
148
149 pinctrl_usart0_cts: usart0_cts-0 {
150 atmel,pins =
151 <1 15 0x2 0x0>; /* PB15 periph B */
152 };
153 };
130 154
131 pioC: gpio@fffff600 { 155 uart1 {
132 compatible = "atmel,at91rm9200-gpio"; 156 pinctrl_usart1: usart1-0 {
133 reg = <0xfffff600 0x100>; 157 atmel,pins =
134 interrupts = <4 4 1>; 158 <1 4 0x1 0x1 /* PB4 periph A with pullup */
135 #gpio-cells = <2>; 159 1 5 0x1 0x0>; /* PB5 periph A */
136 gpio-controller; 160 };
137 interrupt-controller; 161
138 #interrupt-cells = <2>; 162 pinctrl_usart1_rts: usart1_rts-0 {
139 }; 163 atmel,pins =
164 <3 16 0x1 0x0>; /* PD16 periph A */
165 };
166
167 pinctrl_usart1_cts: usart1_cts-0 {
168 atmel,pins =
169 <3 17 0x1 0x0>; /* PD17 periph A */
170 };
171 };
140 172
141 pioD: gpio@fffff800 { 173 usart2 {
142 compatible = "atmel,at91rm9200-gpio"; 174 pinctrl_usart2: usart2-0 {
143 reg = <0xfffff800 0x100>; 175 atmel,pins =
144 interrupts = <5 4 1>; 176 <1 6 0x1 0x1 /* PB6 periph A with pullup */
145 #gpio-cells = <2>; 177 1 7 0x1 0x0>; /* PB7 periph A */
146 gpio-controller; 178 };
147 interrupt-controller; 179
148 #interrupt-cells = <2>; 180 pinctrl_usart2_rts: usart2_rts-0 {
149 }; 181 atmel,pins =
182 <2 9 0x2 0x0>; /* PC9 periph B */
183 };
184
185 pinctrl_usart2_cts: usart2_cts-0 {
186 atmel,pins =
187 <2 11 0x2 0x0>; /* PC11 periph B */
188 };
189 };
150 190
151 pioE: gpio@fffffa00 { 191 usart3 {
152 compatible = "atmel,at91rm9200-gpio"; 192 pinctrl_usart3: usart3-0 {
153 reg = <0xfffffa00 0x100>; 193 atmel,pins =
154 interrupts = <5 4 1>; 194 <1 8 0x1 0x1 /* PB9 periph A with pullup */
155 #gpio-cells = <2>; 195 1 9 0x1 0x0>; /* PB8 periph A */
156 gpio-controller; 196 };
157 interrupt-controller; 197
158 #interrupt-cells = <2>; 198 pinctrl_usart3_rts: usart3_rts-0 {
199 atmel,pins =
200 <0 23 0x2 0x0>; /* PA23 periph B */
201 };
202
203 pinctrl_usart3_cts: usart3_cts-0 {
204 atmel,pins =
205 <0 24 0x2 0x0>; /* PA24 periph B */
206 };
207 };
208
209 nand {
210 pinctrl_nand: nand-0 {
211 atmel,pins =
212 <2 8 0x0 0x1 /* PC8 gpio RDY pin pull_up*/
213 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
214 };
215 };
216
217 macb {
218 pinctrl_macb_rmii: macb_rmii-0 {
219 atmel,pins =
220 <0 10 0x1 0x0 /* PA10 periph A */
221 0 11 0x1 0x0 /* PA11 periph A */
222 0 12 0x1 0x0 /* PA12 periph A */
223 0 13 0x1 0x0 /* PA13 periph A */
224 0 14 0x1 0x0 /* PA14 periph A */
225 0 15 0x1 0x0 /* PA15 periph A */
226 0 16 0x1 0x0 /* PA16 periph A */
227 0 17 0x1 0x0 /* PA17 periph A */
228 0 18 0x1 0x0 /* PA18 periph A */
229 0 19 0x1 0x0>; /* PA19 periph A */
230 };
231
232 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
233 atmel,pins =
234 <0 6 0x2 0x0 /* PA6 periph B */
235 0 7 0x2 0x0 /* PA7 periph B */
236 0 8 0x2 0x0 /* PA8 periph B */
237 0 9 0x2 0x0 /* PA9 periph B */
238 0 27 0x2 0x0 /* PA27 periph B */
239 0 28 0x2 0x0 /* PA28 periph B */
240 0 29 0x2 0x0 /* PA29 periph B */
241 0 30 0x2 0x0>; /* PA30 periph B */
242 };
243 };
244
245 mmc0 {
246 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
247 atmel,pins =
248 <0 0 0x1 0x0 /* PA0 periph A */
249 0 1 0x1 0x1 /* PA1 periph A with pullup */
250 0 2 0x1 0x1>; /* PA2 periph A with pullup */
251 };
252
253 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
254 atmel,pins =
255 <0 3 0x1 0x1 /* PA3 periph A with pullup */
256 0 4 0x1 0x1 /* PA4 periph A with pullup */
257 0 5 0x1 0x1>; /* PA5 periph A with pullup */
258 };
259
260 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
261 atmel,pins =
262 <0 6 0x1 0x1 /* PA6 periph A with pullup */
263 0 7 0x1 0x1 /* PA7 periph A with pullup */
264 0 8 0x1 0x1 /* PA8 periph A with pullup */
265 0 9 0x1 0x1>; /* PA9 periph A with pullup */
266 };
267 };
268
269 mmc1 {
270 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
271 atmel,pins =
272 <0 31 0x1 0x0 /* PA31 periph A */
273 0 22 0x1 0x1 /* PA22 periph A with pullup */
274 0 23 0x1 0x1>; /* PA23 periph A with pullup */
275 };
276
277 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
278 atmel,pins =
279 <0 24 0x1 0x1 /* PA24 periph A with pullup */
280 0 25 0x1 0x1 /* PA25 periph A with pullup */
281 0 26 0x1 0x1>; /* PA26 periph A with pullup */
282 };
283
284 pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
285 atmel,pins =
286 <0 27 0x1 0x1 /* PA27 periph A with pullup */
287 0 28 0x1 0x1 /* PA28 periph A with pullup */
288 0 29 0x1 0x1 /* PA29 periph A with pullup */
289 0 20 0x1 0x1>; /* PA30 periph A with pullup */
290 };
291 };
292
293 ssc0 {
294 pinctrl_ssc0_tx: ssc0_tx-0 {
295 atmel,pins =
296 <3 0 0x1 0x0 /* PD0 periph A */
297 3 1 0x1 0x0 /* PD1 periph A */
298 3 2 0x1 0x0>; /* PD2 periph A */
299 };
300
301 pinctrl_ssc0_rx: ssc0_rx-0 {
302 atmel,pins =
303 <3 3 0x1 0x0 /* PD3 periph A */
304 3 4 0x1 0x0 /* PD4 periph A */
305 3 5 0x1 0x0>; /* PD5 periph A */
306 };
307 };
308
309 ssc1 {
310 pinctrl_ssc1_tx: ssc1_tx-0 {
311 atmel,pins =
312 <3 10 0x1 0x0 /* PD10 periph A */
313 3 11 0x1 0x0 /* PD11 periph A */
314 3 12 0x1 0x0>; /* PD12 periph A */
315 };
316
317 pinctrl_ssc1_rx: ssc1_rx-0 {
318 atmel,pins =
319 <3 13 0x1 0x0 /* PD13 periph A */
320 3 14 0x1 0x0 /* PD14 periph A */
321 3 15 0x1 0x0>; /* PD15 periph A */
322 };
323 };
324
325 pioA: gpio@fffff200 {
326 compatible = "atmel,at91rm9200-gpio";
327 reg = <0xfffff200 0x200>;
328 interrupts = <2 4 1>;
329 #gpio-cells = <2>;
330 gpio-controller;
331 interrupt-controller;
332 #interrupt-cells = <2>;
333 };
334
335 pioB: gpio@fffff400 {
336 compatible = "atmel,at91rm9200-gpio";
337 reg = <0xfffff400 0x200>;
338 interrupts = <3 4 1>;
339 #gpio-cells = <2>;
340 gpio-controller;
341 interrupt-controller;
342 #interrupt-cells = <2>;
343 };
344
345 pioC: gpio@fffff600 {
346 compatible = "atmel,at91rm9200-gpio";
347 reg = <0xfffff600 0x200>;
348 interrupts = <4 4 1>;
349 #gpio-cells = <2>;
350 gpio-controller;
351 interrupt-controller;
352 #interrupt-cells = <2>;
353 };
354
355 pioD: gpio@fffff800 {
356 compatible = "atmel,at91rm9200-gpio";
357 reg = <0xfffff800 0x200>;
358 interrupts = <5 4 1>;
359 #gpio-cells = <2>;
360 gpio-controller;
361 interrupt-controller;
362 #interrupt-cells = <2>;
363 };
364
365 pioE: gpio@fffffa00 {
366 compatible = "atmel,at91rm9200-gpio";
367 reg = <0xfffffa00 0x200>;
368 interrupts = <5 4 1>;
369 #gpio-cells = <2>;
370 gpio-controller;
371 interrupt-controller;
372 #interrupt-cells = <2>;
373 };
159 }; 374 };
160 375
161 dbgu: serial@ffffee00 { 376 dbgu: serial@ffffee00 {
162 compatible = "atmel,at91sam9260-usart"; 377 compatible = "atmel,at91sam9260-usart";
163 reg = <0xffffee00 0x200>; 378 reg = <0xffffee00 0x200>;
164 interrupts = <1 4 7>; 379 interrupts = <1 4 7>;
380 pinctrl-names = "default";
381 pinctrl-0 = <&pinctrl_dbgu>;
165 status = "disabled"; 382 status = "disabled";
166 }; 383 };
167 384
@@ -171,6 +388,8 @@
171 interrupts = <7 4 5>; 388 interrupts = <7 4 5>;
172 atmel,use-dma-rx; 389 atmel,use-dma-rx;
173 atmel,use-dma-tx; 390 atmel,use-dma-tx;
391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_usart0>;
174 status = "disabled"; 393 status = "disabled";
175 }; 394 };
176 395
@@ -180,6 +399,8 @@
180 interrupts = <8 4 5>; 399 interrupts = <8 4 5>;
181 atmel,use-dma-rx; 400 atmel,use-dma-rx;
182 atmel,use-dma-tx; 401 atmel,use-dma-tx;
402 pinctrl-names = "default";
403 pinctrl-0 = <&pinctrl_usart1>;
183 status = "disabled"; 404 status = "disabled";
184 }; 405 };
185 406
@@ -189,6 +410,8 @@
189 interrupts = <9 4 5>; 410 interrupts = <9 4 5>;
190 atmel,use-dma-rx; 411 atmel,use-dma-rx;
191 atmel,use-dma-tx; 412 atmel,use-dma-tx;
413 pinctrl-names = "default";
414 pinctrl-0 = <&pinctrl_usart2>;
192 status = "disabled"; 415 status = "disabled";
193 }; 416 };
194 417
@@ -198,6 +421,8 @@
198 interrupts = <10 4 5>; 421 interrupts = <10 4 5>;
199 atmel,use-dma-rx; 422 atmel,use-dma-rx;
200 atmel,use-dma-tx; 423 atmel,use-dma-tx;
424 pinctrl-names = "default";
425 pinctrl-0 = <&pinctrl_usart3>;
201 status = "disabled"; 426 status = "disabled";
202 }; 427 };
203 428
@@ -205,6 +430,8 @@
205 compatible = "cdns,at32ap7000-macb", "cdns,macb"; 430 compatible = "cdns,at32ap7000-macb", "cdns,macb";
206 reg = <0xfffbc000 0x100>; 431 reg = <0xfffbc000 0x100>;
207 interrupts = <25 4 3>; 432 interrupts = <25 4 3>;
433 pinctrl-names = "default";
434 pinctrl-0 = <&pinctrl_macb_rmii>;
208 status = "disabled"; 435 status = "disabled";
209 }; 436 };
210 437
@@ -226,6 +453,24 @@
226 status = "disabled"; 453 status = "disabled";
227 }; 454 };
228 455
456 ssc0: ssc@fff9c000 {
457 compatible = "atmel,at91sam9g45-ssc";
458 reg = <0xfff9c000 0x4000>;
459 interrupts = <16 4 5>;
460 pinctrl-names = "default";
461 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
462 status = "disabled";
463 };
464
465 ssc1: ssc@fffa0000 {
466 compatible = "atmel,at91sam9g45-ssc";
467 reg = <0xfffa0000 0x4000>;
468 interrupts = <17 4 5>;
469 pinctrl-names = "default";
470 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
471 status = "disabled";
472 };
473
229 adc0: adc@fffb0000 { 474 adc0: adc@fffb0000 {
230 compatible = "atmel,at91sam9260-adc"; 475 compatible = "atmel,at91sam9260-adc";
231 reg = <0xfffb0000 0x100>; 476 reg = <0xfffb0000 0x100>;
@@ -262,6 +507,30 @@
262 trigger-value = <0x6>; 507 trigger-value = <0x6>;
263 }; 508 };
264 }; 509 };
510
511 mmc0: mmc@fff80000 {
512 compatible = "atmel,hsmci";
513 reg = <0xfff80000 0x600>;
514 interrupts = <11 4 0>;
515 #address-cells = <1>;
516 #size-cells = <0>;
517 status = "disabled";
518 };
519
520 mmc1: mmc@fffd0000 {
521 compatible = "atmel,hsmci";
522 reg = <0xfffd0000 0x600>;
523 interrupts = <29 4 0>;
524 #address-cells = <1>;
525 #size-cells = <0>;
526 status = "disabled";
527 };
528
529 watchdog@fffffd40 {
530 compatible = "atmel,at91sam9260-wdt";
531 reg = <0xfffffd40 0x10>;
532 status = "disabled";
533 };
265 }; 534 };
266 535
267 nand0: nand@40000000 { 536 nand0: nand@40000000 {
@@ -273,6 +542,8 @@
273 >; 542 >;
274 atmel,nand-addr-offset = <21>; 543 atmel,nand-addr-offset = <21>;
275 atmel,nand-cmd-offset = <22>; 544 atmel,nand-cmd-offset = <22>;
545 pinctrl-names = "default";
546 pinctrl-0 = <&pinctrl_nand>;
276 gpios = <&pioC 8 0 547 gpios = <&pioC 8 0
277 &pioC 14 0 548 &pioC 14 0
278 0 549 0
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 15e1dd43f625..20c31913c270 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -39,6 +39,10 @@
39 }; 39 };
40 40
41 usart1: serial@fff90000 { 41 usart1: serial@fff90000 {
42 pinctrl-0 =
43 <&pinctrl_usart1
44 &pinctrl_usart1_rts
45 &pinctrl_usart1_cts>;
42 status = "okay"; 46 status = "okay";
43 }; 47 };
44 48
@@ -54,6 +58,50 @@
54 i2c1: i2c@fff88000 { 58 i2c1: i2c@fff88000 {
55 status = "okay"; 59 status = "okay";
56 }; 60 };
61
62 mmc0: mmc@fff80000 {
63 pinctrl-0 = <
64 &pinctrl_board_mmc0
65 &pinctrl_mmc0_slot0_clk_cmd_dat0
66 &pinctrl_mmc0_slot0_dat1_3>;
67 status = "okay";
68 slot@0 {
69 reg = <0>;
70 bus-width = <4>;
71 cd-gpios = <&pioD 10 0>;
72 };
73 };
74
75 mmc1: mmc@fffd0000 {
76 pinctrl-0 = <
77 &pinctrl_board_mmc1
78 &pinctrl_mmc1_slot0_clk_cmd_dat0
79 &pinctrl_mmc1_slot0_dat1_3>;
80 status = "okay";
81 slot@0 {
82 reg = <0>;
83 bus-width = <4>;
84 cd-gpios = <&pioD 11 0>;
85 wp-gpios = <&pioD 29 0>;
86 };
87 };
88
89 pinctrl@fffff200 {
90 mmc0 {
91 pinctrl_board_mmc0: mmc0-board {
92 atmel,pins =
93 <3 10 0x0 0x5>; /* PD10 gpio CD pin pull up and deglitch */
94 };
95 };
96
97 mmc1 {
98 pinctrl_board_mmc1: mmc1-board {
99 atmel,pins =
100 <3 11 0x0 0x5 /* PD11 gpio CD pin pull up and deglitch */
101 3 29 0x0 0x1>; /* PD29 gpio WP pin pull up */
102 };
103 };
104 };
57 }; 105 };
58 106
59 nand0: nand@40000000 { 107 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 82508d68aa7e..80e29c605d4e 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -28,6 +28,7 @@
28 tcb1 = &tcb1; 28 tcb1 = &tcb1;
29 i2c0 = &i2c0; 29 i2c0 = &i2c0;
30 i2c1 = &i2c1; 30 i2c1 = &i2c1;
31 ssc0 = &ssc0;
31 }; 32 };
32 cpus { 33 cpus {
33 cpu@0 { 34 cpu@0 {
@@ -84,6 +85,15 @@
84 reg = <0xfffffe10 0x10>; 85 reg = <0xfffffe10 0x10>;
85 }; 86 };
86 87
88 mmc0: mmc@f0008000 {
89 compatible = "atmel,hsmci";
90 reg = <0xf0008000 0x600>;
91 interrupts = <12 4 0>;
92 #address-cells = <1>;
93 #size-cells = <0>;
94 status = "disabled";
95 };
96
87 tcb0: timer@f8008000 { 97 tcb0: timer@f8008000 {
88 compatible = "atmel,at91sam9x5-tcb"; 98 compatible = "atmel,at91sam9x5-tcb";
89 reg = <0xf8008000 0x100>; 99 reg = <0xf8008000 0x100>;
@@ -102,50 +112,211 @@
102 interrupts = <20 4 0>; 112 interrupts = <20 4 0>;
103 }; 113 };
104 114
105 pioA: gpio@fffff400 { 115 pinctrl@fffff400 {
106 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 116 #address-cells = <1>;
107 reg = <0xfffff400 0x100>; 117 #size-cells = <1>;
108 interrupts = <2 4 1>; 118 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
109 #gpio-cells = <2>; 119 ranges = <0xfffff400 0xfffff400 0x800>;
110 gpio-controller;
111 interrupt-controller;
112 #interrupt-cells = <2>;
113 };
114 120
115 pioB: gpio@fffff600 { 121 atmel,mux-mask = <
116 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 122 /* A B C */
117 reg = <0xfffff600 0x100>; 123 0xffffffff 0xffe07983 0x00000000 /* pioA */
118 interrupts = <2 4 1>; 124 0x00040000 0x00047e0f 0x00000000 /* pioB */
119 #gpio-cells = <2>; 125 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
120 gpio-controller; 126 0x003fffff 0x003f8000 0x00000000 /* pioD */
121 interrupt-controller; 127 >;
122 #interrupt-cells = <2>;
123 };
124 128
125 pioC: gpio@fffff800 { 129 /* shared pinctrl settings */
126 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 130 dbgu {
127 reg = <0xfffff800 0x100>; 131 pinctrl_dbgu: dbgu-0 {
128 interrupts = <3 4 1>; 132 atmel,pins =
129 #gpio-cells = <2>; 133 <0 9 0x1 0x0 /* PA9 periph A */
130 gpio-controller; 134 0 10 0x1 0x1>; /* PA10 periph with pullup */
131 interrupt-controller; 135 };
132 #interrupt-cells = <2>; 136 };
133 };
134 137
135 pioD: gpio@fffffa00 { 138 usart0 {
136 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 139 pinctrl_usart0: usart0-0 {
137 reg = <0xfffffa00 0x100>; 140 atmel,pins =
138 interrupts = <3 4 1>; 141 <0 1 0x1 0x1 /* PA1 periph A with pullup */
139 #gpio-cells = <2>; 142 0 0 0x1 0x0>; /* PA0 periph A */
140 gpio-controller; 143 };
141 interrupt-controller; 144
142 #interrupt-cells = <2>; 145 pinctrl_usart0_rts: usart0_rts-0 {
146 atmel,pins =
147 <0 2 0x1 0x0>; /* PA2 periph A */
148 };
149
150 pinctrl_usart0_cts: usart0_cts-0 {
151 atmel,pins =
152 <0 3 0x1 0x0>; /* PA3 periph A */
153 };
154 };
155
156 usart1 {
157 pinctrl_usart1: usart1-0 {
158 atmel,pins =
159 <0 6 0x1 0x1 /* PA6 periph A with pullup */
160 0 5 0x1 0x0>; /* PA5 periph A */
161 };
162 };
163
164 usart2 {
165 pinctrl_usart2: usart2-0 {
166 atmel,pins =
167 <0 8 0x1 0x1 /* PA8 periph A with pullup */
168 0 7 0x1 0x0>; /* PA7 periph A */
169 };
170
171 pinctrl_usart2_rts: usart2_rts-0 {
172 atmel,pins =
173 <1 0 0x2 0x0>; /* PB0 periph B */
174 };
175
176 pinctrl_usart2_cts: usart2_cts-0 {
177 atmel,pins =
178 <1 1 0x2 0x0>; /* PB1 periph B */
179 };
180 };
181
182 usart3 {
183 pinctrl_usart3: usart3-0 {
184 atmel,pins =
185 <2 23 0x2 0x1 /* PC23 periph B with pullup */
186 2 22 0x2 0x0>; /* PC22 periph B */
187 };
188
189 pinctrl_usart3_rts: usart3_rts-0 {
190 atmel,pins =
191 <2 24 0x2 0x0>; /* PC24 periph B */
192 };
193
194 pinctrl_usart3_cts: usart3_cts-0 {
195 atmel,pins =
196 <2 25 0x2 0x0>; /* PC25 periph B */
197 };
198 };
199
200 uart0 {
201 pinctrl_uart0: uart0-0 {
202 atmel,pins =
203 <2 9 0x3 0x1 /* PC9 periph C with pullup */
204 2 8 0x3 0x0>; /* PC8 periph C */
205 };
206 };
207
208 uart1 {
209 pinctrl_uart1: uart1-0 {
210 atmel,pins =
211 <2 16 0x3 0x1 /* PC17 periph C with pullup */
212 2 17 0x3 0x0>; /* PC16 periph C */
213 };
214 };
215
216 nand {
217 pinctrl_nand: nand-0 {
218 atmel,pins =
219 <3 5 0x0 0x1 /* PD5 gpio RDY pin pull_up*/
220 3 4 0x0 0x1>; /* PD4 gpio enable pin pull_up */
221 };
222 };
223
224 mmc0 {
225 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
226 atmel,pins =
227 <0 17 0x1 0x0 /* PA17 periph A */
228 0 16 0x1 0x1 /* PA16 periph A with pullup */
229 0 15 0x1 0x1>; /* PA15 periph A with pullup */
230 };
231
232 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
233 atmel,pins =
234 <0 18 0x1 0x1 /* PA18 periph A with pullup */
235 0 19 0x1 0x1 /* PA19 periph A with pullup */
236 0 20 0x1 0x1>; /* PA20 periph A with pullup */
237 };
238
239 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
240 atmel,pins =
241 <0 11 0x2 0x1 /* PA11 periph B with pullup */
242 0 12 0x2 0x1 /* PA12 periph B with pullup */
243 0 13 0x2 0x1 /* PA13 periph B with pullup */
244 0 14 0x2 0x1>; /* PA14 periph B with pullup */
245 };
246 };
247
248 ssc0 {
249 pinctrl_ssc0_tx: ssc0_tx-0 {
250 atmel,pins =
251 <0 24 0x2 0x0 /* PA24 periph B */
252 0 25 0x2 0x0 /* PA25 periph B */
253 0 26 0x2 0x0>; /* PA26 periph B */
254 };
255
256 pinctrl_ssc0_rx: ssc0_rx-0 {
257 atmel,pins =
258 <0 27 0x2 0x0 /* PA27 periph B */
259 0 28 0x2 0x0 /* PA28 periph B */
260 0 29 0x2 0x0>; /* PA29 periph B */
261 };
262 };
263
264 pioA: gpio@fffff400 {
265 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
266 reg = <0xfffff400 0x200>;
267 interrupts = <2 4 1>;
268 #gpio-cells = <2>;
269 gpio-controller;
270 interrupt-controller;
271 #interrupt-cells = <2>;
272 };
273
274 pioB: gpio@fffff600 {
275 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
276 reg = <0xfffff600 0x200>;
277 interrupts = <2 4 1>;
278 #gpio-cells = <2>;
279 gpio-controller;
280 interrupt-controller;
281 #interrupt-cells = <2>;
282 };
283
284 pioC: gpio@fffff800 {
285 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
286 reg = <0xfffff800 0x200>;
287 interrupts = <3 4 1>;
288 #gpio-cells = <2>;
289 gpio-controller;
290 interrupt-controller;
291 #interrupt-cells = <2>;
292 };
293
294 pioD: gpio@fffffa00 {
295 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
296 reg = <0xfffffa00 0x200>;
297 interrupts = <3 4 1>;
298 #gpio-cells = <2>;
299 gpio-controller;
300 interrupt-controller;
301 #interrupt-cells = <2>;
302 };
143 }; 303 };
144 304
145 dbgu: serial@fffff200 { 305 dbgu: serial@fffff200 {
146 compatible = "atmel,at91sam9260-usart"; 306 compatible = "atmel,at91sam9260-usart";
147 reg = <0xfffff200 0x200>; 307 reg = <0xfffff200 0x200>;
148 interrupts = <1 4 7>; 308 interrupts = <1 4 7>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&pinctrl_dbgu>;
311 status = "disabled";
312 };
313
314 ssc0: ssc@f0010000 {
315 compatible = "atmel,at91sam9g45-ssc";
316 reg = <0xf0010000 0x4000>;
317 interrupts = <28 4 5>;
318 pinctrl-names = "default";
319 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
149 status = "disabled"; 320 status = "disabled";
150 }; 321 };
151 322
@@ -155,6 +326,8 @@
155 interrupts = <5 4 5>; 326 interrupts = <5 4 5>;
156 atmel,use-dma-rx; 327 atmel,use-dma-rx;
157 atmel,use-dma-tx; 328 atmel,use-dma-tx;
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_usart0>;
158 status = "disabled"; 331 status = "disabled";
159 }; 332 };
160 333
@@ -164,6 +337,8 @@
164 interrupts = <6 4 5>; 337 interrupts = <6 4 5>;
165 atmel,use-dma-rx; 338 atmel,use-dma-rx;
166 atmel,use-dma-tx; 339 atmel,use-dma-tx;
340 pinctrl-names = "default";
341 pinctrl-0 = <&pinctrl_usart1>;
167 status = "disabled"; 342 status = "disabled";
168 }; 343 };
169 344
@@ -173,6 +348,8 @@
173 interrupts = <7 4 5>; 348 interrupts = <7 4 5>;
174 atmel,use-dma-rx; 349 atmel,use-dma-rx;
175 atmel,use-dma-tx; 350 atmel,use-dma-tx;
351 pinctrl-names = "default";
352 pinctrl-0 = <&pinctrl_usart2>;
176 status = "disabled"; 353 status = "disabled";
177 }; 354 };
178 355
@@ -182,6 +359,8 @@
182 interrupts = <8 4 5>; 359 interrupts = <8 4 5>;
183 atmel,use-dma-rx; 360 atmel,use-dma-rx;
184 atmel,use-dma-tx; 361 atmel,use-dma-tx;
362 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_usart3>;
185 status = "disabled"; 364 status = "disabled";
186 }; 365 };
187 366
@@ -215,6 +394,8 @@
215 >; 394 >;
216 atmel,nand-addr-offset = <21>; 395 atmel,nand-addr-offset = <21>;
217 atmel,nand-cmd-offset = <22>; 396 atmel,nand-cmd-offset = <22>;
397 pinctrl-names = "default";
398 pinctrl-0 = <&pinctrl_nand>;
218 gpios = <&pioD 5 0 399 gpios = <&pioD 5 0
219 &pioD 4 0 400 &pioD 4 0
220 0 401 0
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index 912b2c283d6f..0376bf4fd66b 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -45,6 +45,28 @@
45 i2c1: i2c@f8014000 { 45 i2c1: i2c@f8014000 {
46 status = "okay"; 46 status = "okay";
47 }; 47 };
48
49 mmc0: mmc@f0008000 {
50 pinctrl-0 = <
51 &pinctrl_board_mmc0
52 &pinctrl_mmc0_slot0_clk_cmd_dat0
53 &pinctrl_mmc0_slot0_dat1_3>;
54 status = "okay";
55 slot@0 {
56 reg = <0>;
57 bus-width = <4>;
58 cd-gpios = <&pioA 7 0>;
59 };
60 };
61
62 pinctrl@fffff400 {
63 mmc0 {
64 pinctrl_board_mmc0: mmc0-board {
65 atmel,pins =
66 <0 7 0x0 0x5>; /* PA7 gpio CD pin pull up and deglitch */
67 };
68 };
69 };
48 }; 70 };
49 71
50 nand0: nand@40000000 { 72 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi
new file mode 100644
index 000000000000..54eb33ba6d22
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x25.dtsi
@@ -0,0 +1,49 @@
1/*
2 * at91sam9x25.dtsi - Device Tree Include file for AT91SAM9X25 SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/include/ "at91sam9x5.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9X25 SoC";
13 compatible = "atmel, at91sam9x25, atmel,at91sam9x5";
14
15 ahb {
16 apb {
17 pinctrl@fffff400 {
18 atmel,mux-mask = <
19 /* A B C */
20 0xffffffff 0xffe03fff 0xc000001c /* pioA */
21 0x0007ffff 0x00047e3f 0x00000000 /* pioB */
22 0x80000000 0xfffd0000 0xb83fffff /* pioC */
23 0x003fffff 0x003f8000 0x00000000 /* pioD */
24 >;
25
26 macb1 {
27 pinctrl_macb1_rmii: macb1_rmii-0 {
28 atmel,pins =
29 <2 16 0x2 0x0 /* PC16 periph B */
30 2 18 0x2 0x0 /* PC18 periph B */
31 2 19 0x2 0x0 /* PC19 periph B */
32 2 20 0x2 0x0 /* PC20 periph B */
33 2 21 0x2 0x0 /* PC21 periph B */
34 2 27 0x2 0x0 /* PC27 periph B */
35 2 28 0x2 0x0 /* PC28 periph B */
36 2 29 0x2 0x0 /* PC29 periph B */
37 2 30 0x2 0x0 /* PC30 periph B */
38 2 31 0x2 0x0>; /* PC31 periph B */
39 };
40 };
41 };
42
43 macb1: ethernet@f8030000 {
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_macb1_rmii>;
46 };
47 };
48 };
49};
diff --git a/arch/arm/boot/dts/at91sam9x25ek.dts b/arch/arm/boot/dts/at91sam9x25ek.dts
new file mode 100644
index 000000000000..af907eaa1f25
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x25ek.dts
@@ -0,0 +1,16 @@
1/*
2 * at91sam9x25ek.dts - Device Tree file for AT91SAM9X25-EK board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9x25.dtsi"
11/include/ "at91sam9x5ek.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9G25-EK";
15 compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16};
diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi
new file mode 100644
index 000000000000..fb102d6126ce
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x35.dtsi
@@ -0,0 +1,28 @@
1/*
2 * at91sam9x35.dtsi - Device Tree Include file for AT91SAM9X35 SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/include/ "at91sam9x5.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9X35 SoC";
13 compatible = "atmel, at91sam9x35, atmel,at91sam9x5";
14
15 ahb {
16 apb {
17 pinctrl@fffff400 {
18 atmel,mux-mask = <
19 /* A B C */
20 0xffffffff 0xffe03fff 0xc000000c /* pioA */
21 0x000406ff 0x00047e3f 0x00000000 /* pioB */
22 0xfdffffff 0x00000000 0xb83fffff /* pioC */
23 0x003fffff 0x003f8000 0x00000000 /* pioD */
24 >;
25 };
26 };
27 };
28};
diff --git a/arch/arm/boot/dts/at91sam9x35ek.dts b/arch/arm/boot/dts/at91sam9x35ek.dts
new file mode 100644
index 000000000000..5ccb607b5414
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x35ek.dts
@@ -0,0 +1,16 @@
1/*
2 * at91sam9x35ek.dts - Device Tree file for AT91SAM9X35-EK board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9x35.dtsi"
11/include/ "at91sam9x5ek.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9X35-EK";
15 compatible = "atmel,at91sam9x35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 03fc136421c5..3a47cf952146 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -30,6 +30,7 @@
30 i2c0 = &i2c0; 30 i2c0 = &i2c0;
31 i2c1 = &i2c1; 31 i2c1 = &i2c1;
32 i2c2 = &i2c2; 32 i2c2 = &i2c2;
33 ssc0 = &ssc0;
33 }; 34 };
34 cpus { 35 cpus {
35 cpu@0 { 36 cpu@0 {
@@ -111,50 +112,269 @@
111 interrupts = <21 4 0>; 112 interrupts = <21 4 0>;
112 }; 113 };
113 114
114 pioA: gpio@fffff400 { 115 pinctrl@fffff400 {
115 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 116 #address-cells = <1>;
116 reg = <0xfffff400 0x100>; 117 #size-cells = <1>;
117 interrupts = <2 4 1>; 118 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
118 #gpio-cells = <2>; 119 ranges = <0xfffff400 0xfffff400 0x800>;
119 gpio-controller; 120
120 interrupt-controller; 121 /* shared pinctrl settings */
121 #interrupt-cells = <2>; 122 dbgu {
123 pinctrl_dbgu: dbgu-0 {
124 atmel,pins =
125 <0 9 0x1 0x0 /* PA9 periph A */
126 0 10 0x1 0x1>; /* PA10 periph A with pullup */
127 };
128 };
129
130 usart0 {
131 pinctrl_usart0: usart0-0 {
132 atmel,pins =
133 <0 0 0x1 0x1 /* PA0 periph A with pullup */
134 0 1 0x1 0x0>; /* PA1 periph A */
135 };
136
137 pinctrl_usart0_rts: usart0_rts-0 {
138 atmel,pins =
139 <0 2 0x1 0x0>; /* PA2 periph A */
140 };
141
142 pinctrl_usart0_cts: usart0_cts-0 {
143 atmel,pins =
144 <0 3 0x1 0x0>; /* PA3 periph A */
145 };
146 };
147
148 usart1 {
149 pinctrl_usart1: usart1-0 {
150 atmel,pins =
151 <0 5 0x1 0x1 /* PA5 periph A with pullup */
152 0 6 0x1 0x0>; /* PA6 periph A */
153 };
154
155 pinctrl_usart1_rts: usart1_rts-0 {
156 atmel,pins =
157 <3 27 0x3 0x0>; /* PC27 periph C */
158 };
159
160 pinctrl_usart1_cts: usart1_cts-0 {
161 atmel,pins =
162 <3 28 0x3 0x0>; /* PC28 periph C */
163 };
164 };
165
166 usart2 {
167 pinctrl_usart2: usart2-0 {
168 atmel,pins =
169 <0 7 0x1 0x1 /* PA7 periph A with pullup */
170 0 8 0x1 0x0>; /* PA8 periph A */
171 };
172
173 pinctrl_uart2_rts: uart2_rts-0 {
174 atmel,pins =
175 <0 0 0x2 0x0>; /* PB0 periph B */
176 };
177
178 pinctrl_uart2_cts: uart2_cts-0 {
179 atmel,pins =
180 <0 1 0x2 0x0>; /* PB1 periph B */
181 };
182 };
183
184 usart3 {
185 pinctrl_uart3: usart3-0 {
186 atmel,pins =
187 <3 23 0x2 0x1 /* PC22 periph B with pullup */
188 3 23 0x2 0x0>; /* PC23 periph B */
189 };
190
191 pinctrl_usart3_rts: usart3_rts-0 {
192 atmel,pins =
193 <3 24 0x2 0x0>; /* PC24 periph B */
194 };
195
196 pinctrl_usart3_cts: usart3_cts-0 {
197 atmel,pins =
198 <3 25 0x2 0x0>; /* PC25 periph B */
199 };
200 };
201
202 uart0 {
203 pinctrl_uart0: uart0-0 {
204 atmel,pins =
205 <3 8 0x3 0x0 /* PC8 periph C */
206 3 9 0x3 0x1>; /* PC9 periph C with pullup */
207 };
208 };
209
210 uart1 {
211 pinctrl_uart1: uart1-0 {
212 atmel,pins =
213 <3 16 0x3 0x0 /* PC16 periph C */
214 3 17 0x3 0x1>; /* PC17 periph C with pullup */
215 };
216 };
217
218 nand {
219 pinctrl_nand: nand-0 {
220 atmel,pins =
221 <3 4 0x0 0x1 /* PD5 gpio RDY pin pull_up */
222 3 5 0x0 0x1>; /* PD4 gpio enable pin pull_up */
223 };
224 };
225
226 macb0 {
227 pinctrl_macb0_rmii: macb0_rmii-0 {
228 atmel,pins =
229 <1 0 0x1 0x0 /* PB0 periph A */
230 1 1 0x1 0x0 /* PB1 periph A */
231 1 2 0x1 0x0 /* PB2 periph A */
232 1 3 0x1 0x0 /* PB3 periph A */
233 1 4 0x1 0x0 /* PB4 periph A */
234 1 5 0x1 0x0 /* PB5 periph A */
235 1 6 0x1 0x0 /* PB6 periph A */
236 1 7 0x1 0x0 /* PB7 periph A */
237 1 9 0x1 0x0 /* PB9 periph A */
238 1 10 0x1 0x0>; /* PB10 periph A */
239 };
240
241 pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
242 atmel,pins =
243 <1 8 0x1 0x0 /* PA8 periph A */
244 1 11 0x1 0x0 /* PA11 periph A */
245 1 12 0x1 0x0 /* PA12 periph A */
246 1 13 0x1 0x0 /* PA13 periph A */
247 1 14 0x1 0x0 /* PA14 periph A */
248 1 15 0x1 0x0 /* PA15 periph A */
249 1 16 0x1 0x0 /* PA16 periph A */
250 1 17 0x1 0x0>; /* PA17 periph A */
251 };
252 };
253
254 mmc0 {
255 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
256 atmel,pins =
257 <0 17 0x1 0x0 /* PA17 periph A */
258 0 16 0x1 0x1 /* PA16 periph A with pullup */
259 0 15 0x1 0x1>; /* PA15 periph A with pullup */
260 };
261
262 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
263 atmel,pins =
264 <0 18 0x1 0x1 /* PA18 periph A with pullup */
265 0 19 0x1 0x1 /* PA19 periph A with pullup */
266 0 20 0x1 0x1>; /* PA20 periph A with pullup */
267 };
268 };
269
270 mmc1 {
271 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
272 atmel,pins =
273 <0 13 0x2 0x0 /* PA13 periph B */
274 0 12 0x2 0x1 /* PA12 periph B with pullup */
275 0 11 0x2 0x1>; /* PA11 periph B with pullup */
276 };
277
278 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
279 atmel,pins =
280 <0 2 0x2 0x1 /* PA2 periph B with pullup */
281 0 3 0x2 0x1 /* PA3 periph B with pullup */
282 0 4 0x2 0x1>; /* PA4 periph B with pullup */
283 };
284 };
285
286 ssc0 {
287 pinctrl_ssc0_tx: ssc0_tx-0 {
288 atmel,pins =
289 <0 24 0x2 0x0 /* PA24 periph B */
290 0 25 0x2 0x0 /* PA25 periph B */
291 0 26 0x2 0x0>; /* PA26 periph B */
292 };
293
294 pinctrl_ssc0_rx: ssc0_rx-0 {
295 atmel,pins =
296 <0 27 0x2 0x0 /* PA27 periph B */
297 0 28 0x2 0x0 /* PA28 periph B */
298 0 29 0x2 0x0>; /* PA29 periph B */
299 };
300 };
301
302 pioA: gpio@fffff400 {
303 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
304 reg = <0xfffff400 0x200>;
305 interrupts = <2 4 1>;
306 #gpio-cells = <2>;
307 gpio-controller;
308 interrupt-controller;
309 #interrupt-cells = <2>;
310 };
311
312 pioB: gpio@fffff600 {
313 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
314 reg = <0xfffff600 0x200>;
315 interrupts = <2 4 1>;
316 #gpio-cells = <2>;
317 gpio-controller;
318 #gpio-lines = <19>;
319 interrupt-controller;
320 #interrupt-cells = <2>;
321 };
322
323 pioC: gpio@fffff800 {
324 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
325 reg = <0xfffff800 0x200>;
326 interrupts = <3 4 1>;
327 #gpio-cells = <2>;
328 gpio-controller;
329 interrupt-controller;
330 #interrupt-cells = <2>;
331 };
332
333 pioD: gpio@fffffa00 {
334 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
335 reg = <0xfffffa00 0x200>;
336 interrupts = <3 4 1>;
337 #gpio-cells = <2>;
338 gpio-controller;
339 #gpio-lines = <22>;
340 interrupt-controller;
341 #interrupt-cells = <2>;
342 };
122 }; 343 };
123 344
124 pioB: gpio@fffff600 { 345 ssc0: ssc@f0010000 {
125 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 346 compatible = "atmel,at91sam9g45-ssc";
126 reg = <0xfffff600 0x100>; 347 reg = <0xf0010000 0x4000>;
127 interrupts = <2 4 1>; 348 interrupts = <28 4 5>;
128 #gpio-cells = <2>; 349 pinctrl-names = "default";
129 gpio-controller; 350 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
130 interrupt-controller; 351 status = "disabled";
131 #interrupt-cells = <2>;
132 }; 352 };
133 353
134 pioC: gpio@fffff800 { 354 mmc0: mmc@f0008000 {
135 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 355 compatible = "atmel,hsmci";
136 reg = <0xfffff800 0x100>; 356 reg = <0xf0008000 0x600>;
137 interrupts = <3 4 1>; 357 interrupts = <12 4 0>;
138 #gpio-cells = <2>; 358 #address-cells = <1>;
139 gpio-controller; 359 #size-cells = <0>;
140 interrupt-controller; 360 status = "disabled";
141 #interrupt-cells = <2>;
142 }; 361 };
143 362
144 pioD: gpio@fffffa00 { 363 mmc1: mmc@f000c000 {
145 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 364 compatible = "atmel,hsmci";
146 reg = <0xfffffa00 0x100>; 365 reg = <0xf000c000 0x600>;
147 interrupts = <3 4 1>; 366 interrupts = <26 4 0>;
148 #gpio-cells = <2>; 367 #address-cells = <1>;
149 gpio-controller; 368 #size-cells = <0>;
150 interrupt-controller; 369 status = "disabled";
151 #interrupt-cells = <2>;
152 }; 370 };
153 371
154 dbgu: serial@fffff200 { 372 dbgu: serial@fffff200 {
155 compatible = "atmel,at91sam9260-usart"; 373 compatible = "atmel,at91sam9260-usart";
156 reg = <0xfffff200 0x200>; 374 reg = <0xfffff200 0x200>;
157 interrupts = <1 4 7>; 375 interrupts = <1 4 7>;
376 pinctrl-names = "default";
377 pinctrl-0 = <&pinctrl_dbgu>;
158 status = "disabled"; 378 status = "disabled";
159 }; 379 };
160 380
@@ -164,6 +384,8 @@
164 interrupts = <5 4 5>; 384 interrupts = <5 4 5>;
165 atmel,use-dma-rx; 385 atmel,use-dma-rx;
166 atmel,use-dma-tx; 386 atmel,use-dma-tx;
387 pinctrl-names = "default";
388 pinctrl-0 = <&pinctrl_usart0>;
167 status = "disabled"; 389 status = "disabled";
168 }; 390 };
169 391
@@ -173,6 +395,8 @@
173 interrupts = <6 4 5>; 395 interrupts = <6 4 5>;
174 atmel,use-dma-rx; 396 atmel,use-dma-rx;
175 atmel,use-dma-tx; 397 atmel,use-dma-tx;
398 pinctrl-names = "default";
399 pinctrl-0 = <&pinctrl_usart1>;
176 status = "disabled"; 400 status = "disabled";
177 }; 401 };
178 402
@@ -182,6 +406,8 @@
182 interrupts = <7 4 5>; 406 interrupts = <7 4 5>;
183 atmel,use-dma-rx; 407 atmel,use-dma-rx;
184 atmel,use-dma-tx; 408 atmel,use-dma-tx;
409 pinctrl-names = "default";
410 pinctrl-0 = <&pinctrl_usart2>;
185 status = "disabled"; 411 status = "disabled";
186 }; 412 };
187 413
@@ -189,6 +415,8 @@
189 compatible = "cdns,at32ap7000-macb", "cdns,macb"; 415 compatible = "cdns,at32ap7000-macb", "cdns,macb";
190 reg = <0xf802c000 0x100>; 416 reg = <0xf802c000 0x100>;
191 interrupts = <24 4 3>; 417 interrupts = <24 4 3>;
418 pinctrl-names = "default";
419 pinctrl-0 = <&pinctrl_macb0_rmii>;
192 status = "disabled"; 420 status = "disabled";
193 }; 421 };
194 422
@@ -273,6 +501,8 @@
273 >; 501 >;
274 atmel,nand-addr-offset = <21>; 502 atmel,nand-addr-offset = <21>;
275 atmel,nand-cmd-offset = <22>; 503 atmel,nand-cmd-offset = <22>;
504 pinctrl-names = "default";
505 pinctrl-0 = <&pinctrl_nand>;
276 gpios = <&pioD 5 0 506 gpios = <&pioD 5 0
277 &pioD 4 0 507 &pioD 4 0
278 0 508 0
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
new file mode 100644
index 000000000000..8a7cf1d9cf5d
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -0,0 +1,101 @@
1/*
2 * at91sam9x5ek.dtsi - Device Tree file for AT91SAM9x5CM Base board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/include/ "at91sam9x5cm.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9X5-EK";
13 compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
14
15 chosen {
16 bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
17 };
18
19 ahb {
20 apb {
21 mmc0: mmc@f0008000 {
22 pinctrl-0 = <
23 &pinctrl_board_mmc0
24 &pinctrl_mmc0_slot0_clk_cmd_dat0
25 &pinctrl_mmc0_slot0_dat1_3>;
26 status = "okay";
27 slot@0 {
28 reg = <0>;
29 bus-width = <4>;
30 cd-gpios = <&pioD 15 0>;
31 };
32 };
33
34 mmc1: mmc@f000c000 {
35 pinctrl-0 = <
36 &pinctrl_board_mmc1
37 &pinctrl_mmc1_slot0_clk_cmd_dat0
38 &pinctrl_mmc1_slot0_dat1_3>;
39 status = "okay";
40 slot@0 {
41 reg = <0>;
42 bus-width = <4>;
43 cd-gpios = <&pioD 14 0>;
44 };
45 };
46
47 dbgu: serial@fffff200 {
48 status = "okay";
49 };
50
51 usart0: serial@f801c000 {
52 status = "okay";
53 };
54
55 macb0: ethernet@f802c000 {
56 phy-mode = "rmii";
57 status = "okay";
58 };
59
60 i2c0: i2c@f8010000 {
61 status = "okay";
62 };
63
64 i2c1: i2c@f8014000 {
65 status = "okay";
66 };
67
68 i2c2: i2c@f8018000 {
69 status = "okay";
70 };
71
72 pinctrl@fffff400 {
73 mmc0 {
74 pinctrl_board_mmc0: mmc0-board {
75 atmel,pins =
76 <3 15 0x0 0x5>; /* PD15 gpio CD pin pull up and deglitch */
77 };
78 };
79
80 mmc1 {
81 pinctrl_board_mmc1: mmc1-board {
82 atmel,pins =
83 <3 14 0x0 0x5>; /* PD14 gpio CD pin pull up and deglitch */
84 };
85 };
86 };
87 };
88
89 usb0: ohci@00600000 {
90 status = "okay";
91 num-ports = <2>;
92 atmel,vbus-gpio = <&pioD 19 1
93 &pioD 20 1
94 >;
95 };
96
97 usb1: ehci@00700000 {
98 status = "okay";
99 };
100 };
101};
diff --git a/arch/arm/boot/dts/bcm11351-brt.dts b/arch/arm/boot/dts/bcm11351-brt.dts
new file mode 100644
index 000000000000..248067cf7069
--- /dev/null
+++ b/arch/arm/boot/dts/bcm11351-brt.dts
@@ -0,0 +1,30 @@
1/*
2 * Copyright (C) 2012 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14/dts-v1/;
15
16/include/ "bcm11351.dtsi"
17
18/ {
19 model = "BCM11351 BRT board";
20 compatible = "bcm,bcm11351-brt", "bcm,bcm11351";
21
22 memory {
23 reg = <0x80000000 0x40000000>; /* 1 GB */
24 };
25
26 uart@3e000000 {
27 status = "okay";
28 };
29
30};
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
new file mode 100644
index 000000000000..ad135885bd2a
--- /dev/null
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -0,0 +1,50 @@
1/*
2 * Copyright (C) 2012 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 model = "BCM11351 SoC";
18 compatible = "bcm,bcm11351";
19 interrupt-parent = <&gic>;
20
21 chosen {
22 bootargs = "console=ttyS0,115200n8";
23 };
24
25 gic: interrupt-controller@3ff00100 {
26 compatible = "arm,cortex-a9-gic";
27 #interrupt-cells = <3>;
28 #address-cells = <0>;
29 interrupt-controller;
30 reg = <0x3ff01000 0x1000>,
31 <0x3ff00100 0x100>;
32 };
33
34 uart@3e000000 {
35 compatible = "bcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
36 status = "disabled";
37 reg = <0x3e000000 0x1000>;
38 clock-frequency = <13000000>;
39 interrupts = <0x0 67 0x4>;
40 reg-shift = <2>;
41 reg-io-width = <4>;
42 };
43
44 L2: l2-cache {
45 compatible = "arm,pl310-cache";
46 reg = <0x3ff20000 0x1000>;
47 cache-unified;
48 cache-level = <2>;
49 };
50};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
index 7dd860f83f96..9b72054a0bc0 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -10,3 +10,18 @@
10 reg = <0 0x10000000>; 10 reg = <0 0x10000000>;
11 }; 11 };
12}; 12};
13
14&gpio {
15 pinctrl-names = "default";
16 pinctrl-0 = <&alt0 &alt3>;
17
18 alt0: alt0 {
19 brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11 14 15 40 45>;
20 brcm,function = <4>; /* alt0 */
21 };
22
23 alt3: alt3 {
24 brcm,pins = <48 49 50 51 52 53>;
25 brcm,function = <7>; /* alt3 */
26 };
27};
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index 0b619398532c..8917550fd1bb 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -29,11 +29,39 @@
29 #interrupt-cells = <2>; 29 #interrupt-cells = <2>;
30 }; 30 };
31 31
32 watchdog {
33 compatible = "brcm,bcm2835-pm-wdt";
34 reg = <0x7e100000 0x28>;
35 };
36
32 uart@20201000 { 37 uart@20201000 {
33 compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell"; 38 compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
34 reg = <0x7e201000 0x1000>; 39 reg = <0x7e201000 0x1000>;
35 interrupts = <2 25>; 40 interrupts = <2 25>;
36 clock-frequency = <3000000>; 41 clock-frequency = <3000000>;
37 }; 42 };
43
44 gpio: gpio {
45 compatible = "brcm,bcm2835-gpio";
46 reg = <0x7e200000 0xb4>;
47 /*
48 * The GPIO IP block is designed for 3 banks of GPIOs.
49 * Each bank has a GPIO interrupt for itself.
50 * There is an overall "any bank" interrupt.
51 * In order, these are GIC interrupts 17, 18, 19, 20.
52 * Since the BCM2835 only has 2 banks, the 2nd bank
53 * interrupt output appears to be mirrored onto the
54 * 3rd bank's interrupt signal.
55 * So, a bank0 interrupt shows up on 17, 20, and
56 * a bank1 interrupt shows up on 18, 19, 20!
57 */
58 interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
59
60 gpio-controller;
61 #gpio-cells = <2>;
62
63 interrupt-controller;
64 #interrupt-cells = <2>;
65 };
38 }; 66 };
39}; 67};
diff --git a/arch/arm/boot/dts/ccu9540.dts b/arch/arm/boot/dts/ccu9540.dts
new file mode 100644
index 000000000000..04305463f00d
--- /dev/null
+++ b/arch/arm/boot/dts/ccu9540.dts
@@ -0,0 +1,72 @@
1/*
2 * Copyright 2012 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "dbx5x0.dtsi"
14
15/ {
16 model = "ST-Ericsson CCU9540 platform with Device Tree";
17 compatible = "st-ericsson,ccu9540", "st-ericsson,u9540";
18
19 memory {
20 reg = <0x00000000 0x20000000>;
21 };
22
23 soc-u9500 {
24 uart@80120000 {
25 status = "okay";
26 };
27
28 uart@80121000 {
29 status = "okay";
30 };
31
32 uart@80007000 {
33 status = "okay";
34 };
35
36 // External Micro SD slot
37 sdi0_per1@80126000 {
38 arm,primecell-periphid = <0x10480180>;
39 max-frequency = <100000000>;
40 bus-width = <4>;
41 mmc-cap-sd-highspeed;
42 mmc-cap-mmc-highspeed;
43 vmmc-supply = <&ab8500_ldo_aux3_reg>;
44
45 cd-gpios = <&gpio7 6 0x4>; // 230
46 cd-inverted;
47
48 status = "okay";
49 };
50
51
52 // WLAN SDIO channel
53 sdi1_per2@80118000 {
54 arm,primecell-periphid = <0x10480180>;
55 max-frequency = <50000000>;
56 bus-width = <4>;
57
58 status = "okay";
59 };
60
61 // On-board eMMC
62 sdi4_per2@80114000 {
63 arm,primecell-periphid = <0x10480180>;
64 max-frequency = <100000000>;
65 bus-width = <8>;
66 mmc-cap-mmc-highspeed;
67 vmmc-supply = <&ab8500_ldo_aux2_reg>;
68
69 status = "okay";
70 };
71 };
72};
diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi
new file mode 100644
index 000000000000..fddd17417433
--- /dev/null
+++ b/arch/arm/boot/dts/cros5250-common.dtsi
@@ -0,0 +1,184 @@
1/*
2 * Common device tree include for all Exynos 5250 boards based off of Daisy.
3 *
4 * Copyright (c) 2012 Google, Inc
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11/ {
12 aliases {
13 };
14
15 memory {
16 reg = <0x40000000 0x80000000>;
17 };
18
19 chosen {
20 };
21
22 i2c@12C60000 {
23 samsung,i2c-sda-delay = <100>;
24 samsung,i2c-max-bus-freq = <378000>;
25 gpios = <&gpb3 0 2 3 0>,
26 <&gpb3 1 2 3 0>;
27 };
28
29 i2c@12C70000 {
30 samsung,i2c-sda-delay = <100>;
31 samsung,i2c-max-bus-freq = <378000>;
32 gpios = <&gpb3 2 2 3 0>,
33 <&gpb3 3 2 3 0>;
34 };
35
36 i2c@12C80000 {
37 samsung,i2c-sda-delay = <100>;
38 samsung,i2c-max-bus-freq = <66000>;
39
40 /*
41 * Disabled pullups since external part has its own pullups and
42 * double-pulling gets us out of spec in some cases.
43 */
44 gpios = <&gpa0 6 3 0 0>,
45 <&gpa0 7 3 0 0>;
46
47 hdmiddc@50 {
48 compatible = "samsung,exynos5-hdmiddc";
49 reg = <0x50>;
50 };
51 };
52
53 i2c@12C90000 {
54 samsung,i2c-sda-delay = <100>;
55 samsung,i2c-max-bus-freq = <66000>;
56 gpios = <&gpa1 2 3 3 0>,
57 <&gpa1 3 3 3 0>;
58 };
59
60 i2c@12CA0000 {
61 status = "disabled";
62 };
63
64 i2c@12CB0000 {
65 samsung,i2c-sda-delay = <100>;
66 samsung,i2c-max-bus-freq = <66000>;
67 gpios = <&gpa2 2 3 3 0>,
68 <&gpa2 3 3 3 0>;
69 };
70
71 i2c@12CC0000 {
72 status = "disabled";
73 };
74
75 i2c@12CD0000 {
76 samsung,i2c-sda-delay = <100>;
77 samsung,i2c-max-bus-freq = <66000>;
78 gpios = <&gpb2 2 3 3 0>,
79 <&gpb2 3 3 3 0>;
80 };
81
82 i2c@12CE0000 {
83 samsung,i2c-sda-delay = <100>;
84 samsung,i2c-max-bus-freq = <378000>;
85
86 hdmiphy@38 {
87 compatible = "samsung,exynos5-hdmiphy";
88 reg = <0x38>;
89 };
90 };
91
92 dwmmc0@12200000 {
93 num-slots = <1>;
94 supports-highspeed;
95 broken-cd;
96 fifo-depth = <0x80>;
97 card-detect-delay = <200>;
98 samsung,dw-mshc-ciu-div = <3>;
99 samsung,dw-mshc-sdr-timing = <2 3 3>;
100 samsung,dw-mshc-ddr-timing = <1 2 3>;
101
102 slot@0 {
103 reg = <0>;
104 bus-width = <8>;
105 gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
106 <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
107 <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,
108 <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
109 <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;
110 };
111 };
112
113 dwmmc1@12210000 {
114 status = "disabled";
115 };
116
117 dwmmc2@12220000 {
118 num-slots = <1>;
119 supports-highspeed;
120 fifo-depth = <0x80>;
121 card-detect-delay = <200>;
122 samsung,dw-mshc-ciu-div = <3>;
123 samsung,dw-mshc-sdr-timing = <2 3 3>;
124 samsung,dw-mshc-ddr-timing = <1 2 3>;
125
126 slot@0 {
127 reg = <0>;
128 bus-width = <4>;
129 samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
130 wp-gpios = <&gpc2 1 0 0 3>;
131 gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
132 <&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
133 <&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>;
134 };
135 };
136
137 dwmmc3@12230000 {
138 num-slots = <1>;
139 supports-highspeed;
140 broken-cd;
141 fifo-depth = <0x80>;
142 card-detect-delay = <200>;
143 samsung,dw-mshc-ciu-div = <3>;
144 samsung,dw-mshc-sdr-timing = <2 3 3>;
145 samsung,dw-mshc-ddr-timing = <1 2 3>;
146
147 slot@0 {
148 reg = <0>;
149 bus-width = <4>;
150 /* See board-specific dts files for GPIOs */
151 };
152 };
153
154 spi_0: spi@12d20000 {
155 status = "disabled";
156 };
157
158 spi_1: spi@12d30000 {
159 gpios = <&gpa2 4 2 3 0>,
160 <&gpa2 6 2 3 0>,
161 <&gpa2 7 2 3 0>;
162 samsung,spi-src-clk = <0>;
163 num-cs = <1>;
164 };
165
166 spi_2: spi@12d40000 {
167 status = "disabled";
168 };
169
170 hdmi {
171 hpd-gpio = <&gpx3 7 0xf 1 3>;
172 };
173
174 gpio-keys {
175 compatible = "gpio-keys";
176
177 power {
178 label = "Power";
179 gpios = <&gpx1 3 0 0x10000 0>;
180 linux,code = <116>; /* KEY_POWER */
181 gpio-key,wakeup;
182 };
183 };
184};
diff --git a/arch/arm/boot/dts/da850-enbw-cmc.dts b/arch/arm/boot/dts/da850-enbw-cmc.dts
new file mode 100644
index 000000000000..422fdb3fcfc1
--- /dev/null
+++ b/arch/arm/boot/dts/da850-enbw-cmc.dts
@@ -0,0 +1,30 @@
1/*
2 * Device Tree for AM1808 EnBW CMC board
3 *
4 * Copyright 2012 DENX Software Engineering GmbH
5 * Heiko Schocher <hs@denx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12/dts-v1/;
13/include/ "da850.dtsi"
14
15/ {
16 compatible = "enbw,cmc", "ti,da850";
17 model = "EnBW CMC";
18
19 soc {
20 serial0: serial@1c42000 {
21 status = "okay";
22 };
23 serial1: serial@1d0c000 {
24 status = "okay";
25 };
26 serial2: serial@1d0d000 {
27 status = "okay";
28 };
29 };
30};
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
new file mode 100644
index 000000000000..37dc5a3243b8
--- /dev/null
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -0,0 +1,28 @@
1/*
2 * Device Tree for DA850 EVM board
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation, version 2.
9 */
10/dts-v1/;
11/include/ "da850.dtsi"
12
13/ {
14 compatible = "ti,da850-evm", "ti,da850";
15 model = "DA850/AM1808/OMAP-L138 EVM";
16
17 soc {
18 serial0: serial@1c42000 {
19 status = "okay";
20 };
21 serial1: serial@1d0c000 {
22 status = "okay";
23 };
24 serial2: serial@1d0d000 {
25 status = "okay";
26 };
27 };
28};
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
new file mode 100644
index 000000000000..640ab75c20db
--- /dev/null
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -0,0 +1,60 @@
1/*
2 * Copyright 2012 DENX Software Engineering GmbH
3 * Heiko Schocher <hs@denx.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10/include/ "skeleton.dtsi"
11
12/ {
13 arm {
14 #address-cells = <1>;
15 #size-cells = <1>;
16 ranges;
17 intc: interrupt-controller {
18 compatible = "ti,cp-intc";
19 interrupt-controller;
20 #interrupt-cells = <1>;
21 ti,intc-size = <100>;
22 reg = <0xfffee000 0x2000>;
23 };
24 };
25 soc {
26 compatible = "simple-bus";
27 model = "da850";
28 #address-cells = <1>;
29 #size-cells = <1>;
30 ranges = <0x0 0x01c00000 0x400000>;
31
32 serial0: serial@1c42000 {
33 compatible = "ns16550a";
34 reg = <0x42000 0x100>;
35 clock-frequency = <150000000>;
36 reg-shift = <2>;
37 interrupts = <25>;
38 interrupt-parent = <&intc>;
39 status = "disabled";
40 };
41 serial1: serial@1d0c000 {
42 compatible = "ns16550a";
43 reg = <0x10c000 0x100>;
44 clock-frequency = <150000000>;
45 reg-shift = <2>;
46 interrupts = <53>;
47 interrupt-parent = <&intc>;
48 status = "disabled";
49 };
50 serial2: serial@1d0d000 {
51 compatible = "ns16550a";
52 reg = <0x10d000 0x100>;
53 clock-frequency = <150000000>;
54 reg-shift = <2>;
55 interrupts = <61>;
56 interrupt-parent = <&intc>;
57 status = "disabled";
58 };
59 };
60};
diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 4b0e0ca08f40..63f2fbcfe819 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -170,7 +170,9 @@
170 gpio-bank = <8>; 170 gpio-bank = <8>;
171 }; 171 };
172 172
173 pinctrl { 173 pinctrl@80157000 {
174 // This is actually the PRCMU base address
175 reg = <0x80157000 0x2000>;
174 compatible = "stericsson,nmk_pinctrl"; 176 compatible = "stericsson,nmk_pinctrl";
175 }; 177 };
176 178
@@ -203,129 +205,117 @@
203 reg = <0x80157450 0xC>; 205 reg = <0x80157450 0xC>;
204 }; 206 };
205 207
208 thermal@801573c0 {
209 compatible = "stericsson,db8500-thermal";
210 reg = <0x801573c0 0x40>;
211 interrupts = <21 0x4>, <22 0x4>;
212 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
213 status = "disabled";
214 };
215
206 db8500-prcmu-regulators { 216 db8500-prcmu-regulators {
207 compatible = "stericsson,db8500-prcmu-regulator"; 217 compatible = "stericsson,db8500-prcmu-regulator";
208 218
209 // DB8500_REGULATOR_VAPE 219 // DB8500_REGULATOR_VAPE
210 db8500_vape_reg: db8500_vape { 220 db8500_vape_reg: db8500_vape {
211 regulator-compatible = "db8500_vape"; 221 regulator-compatible = "db8500_vape";
212 regulator-name = "db8500-vape";
213 regulator-always-on; 222 regulator-always-on;
214 }; 223 };
215 224
216 // DB8500_REGULATOR_VARM 225 // DB8500_REGULATOR_VARM
217 db8500_varm_reg: db8500_varm { 226 db8500_varm_reg: db8500_varm {
218 regulator-compatible = "db8500_varm"; 227 regulator-compatible = "db8500_varm";
219 regulator-name = "db8500-varm";
220 }; 228 };
221 229
222 // DB8500_REGULATOR_VMODEM 230 // DB8500_REGULATOR_VMODEM
223 db8500_vmodem_reg: db8500_vmodem { 231 db8500_vmodem_reg: db8500_vmodem {
224 regulator-compatible = "db8500_vmodem"; 232 regulator-compatible = "db8500_vmodem";
225 regulator-name = "db8500-vmodem";
226 }; 233 };
227 234
228 // DB8500_REGULATOR_VPLL 235 // DB8500_REGULATOR_VPLL
229 db8500_vpll_reg: db8500_vpll { 236 db8500_vpll_reg: db8500_vpll {
230 regulator-compatible = "db8500_vpll"; 237 regulator-compatible = "db8500_vpll";
231 regulator-name = "db8500-vpll";
232 }; 238 };
233 239
234 // DB8500_REGULATOR_VSMPS1 240 // DB8500_REGULATOR_VSMPS1
235 db8500_vsmps1_reg: db8500_vsmps1 { 241 db8500_vsmps1_reg: db8500_vsmps1 {
236 regulator-compatible = "db8500_vsmps1"; 242 regulator-compatible = "db8500_vsmps1";
237 regulator-name = "db8500-vsmps1";
238 }; 243 };
239 244
240 // DB8500_REGULATOR_VSMPS2 245 // DB8500_REGULATOR_VSMPS2
241 db8500_vsmps2_reg: db8500_vsmps2 { 246 db8500_vsmps2_reg: db8500_vsmps2 {
242 regulator-compatible = "db8500_vsmps2"; 247 regulator-compatible = "db8500_vsmps2";
243 regulator-name = "db8500-vsmps2";
244 }; 248 };
245 249
246 // DB8500_REGULATOR_VSMPS3 250 // DB8500_REGULATOR_VSMPS3
247 db8500_vsmps3_reg: db8500_vsmps3 { 251 db8500_vsmps3_reg: db8500_vsmps3 {
248 regulator-compatible = "db8500_vsmps3"; 252 regulator-compatible = "db8500_vsmps3";
249 regulator-name = "db8500-vsmps3";
250 }; 253 };
251 254
252 // DB8500_REGULATOR_VRF1 255 // DB8500_REGULATOR_VRF1
253 db8500_vrf1_reg: db8500_vrf1 { 256 db8500_vrf1_reg: db8500_vrf1 {
254 regulator-compatible = "db8500_vrf1"; 257 regulator-compatible = "db8500_vrf1";
255 regulator-name = "db8500-vrf1";
256 }; 258 };
257 259
258 // DB8500_REGULATOR_SWITCH_SVAMMDSP 260 // DB8500_REGULATOR_SWITCH_SVAMMDSP
259 db8500_sva_mmdsp_reg: db8500_sva_mmdsp { 261 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
260 regulator-compatible = "db8500_sva_mmdsp"; 262 regulator-compatible = "db8500_sva_mmdsp";
261 regulator-name = "db8500-sva-mmdsp";
262 }; 263 };
263 264
264 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET 265 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET
265 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { 266 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
266 regulator-compatible = "db8500_sva_mmdsp_ret"; 267 regulator-compatible = "db8500_sva_mmdsp_ret";
267 regulator-name = "db8500-sva-mmdsp-ret";
268 }; 268 };
269 269
270 // DB8500_REGULATOR_SWITCH_SVAPIPE 270 // DB8500_REGULATOR_SWITCH_SVAPIPE
271 db8500_sva_pipe_reg: db8500_sva_pipe { 271 db8500_sva_pipe_reg: db8500_sva_pipe {
272 regulator-compatible = "db8500_sva_pipe"; 272 regulator-compatible = "db8500_sva_pipe";
273 regulator-name = "db8500_sva_pipe";
274 }; 273 };
275 274
276 // DB8500_REGULATOR_SWITCH_SIAMMDSP 275 // DB8500_REGULATOR_SWITCH_SIAMMDSP
277 db8500_sia_mmdsp_reg: db8500_sia_mmdsp { 276 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
278 regulator-compatible = "db8500_sia_mmdsp"; 277 regulator-compatible = "db8500_sia_mmdsp";
279 regulator-name = "db8500_sia_mmdsp";
280 }; 278 };
281 279
282 // DB8500_REGULATOR_SWITCH_SIAMMDSPRET 280 // DB8500_REGULATOR_SWITCH_SIAMMDSPRET
283 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { 281 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
284 regulator-name = "db8500-sia-mmdsp-ret";
285 }; 282 };
286 283
287 // DB8500_REGULATOR_SWITCH_SIAPIPE 284 // DB8500_REGULATOR_SWITCH_SIAPIPE
288 db8500_sia_pipe_reg: db8500_sia_pipe { 285 db8500_sia_pipe_reg: db8500_sia_pipe {
289 regulator-compatible = "db8500_sia_pipe"; 286 regulator-compatible = "db8500_sia_pipe";
290 regulator-name = "db8500-sia-pipe";
291 }; 287 };
292 288
293 // DB8500_REGULATOR_SWITCH_SGA 289 // DB8500_REGULATOR_SWITCH_SGA
294 db8500_sga_reg: db8500_sga { 290 db8500_sga_reg: db8500_sga {
295 regulator-compatible = "db8500_sga"; 291 regulator-compatible = "db8500_sga";
296 regulator-name = "db8500-sga";
297 vin-supply = <&db8500_vape_reg>; 292 vin-supply = <&db8500_vape_reg>;
298 }; 293 };
299 294
300 // DB8500_REGULATOR_SWITCH_B2R2_MCDE 295 // DB8500_REGULATOR_SWITCH_B2R2_MCDE
301 db8500_b2r2_mcde_reg: db8500_b2r2_mcde { 296 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
302 regulator-compatible = "db8500_b2r2_mcde"; 297 regulator-compatible = "db8500_b2r2_mcde";
303 regulator-name = "db8500-b2r2-mcde";
304 vin-supply = <&db8500_vape_reg>; 298 vin-supply = <&db8500_vape_reg>;
305 }; 299 };
306 300
307 // DB8500_REGULATOR_SWITCH_ESRAM12 301 // DB8500_REGULATOR_SWITCH_ESRAM12
308 db8500_esram12_reg: db8500_esram12 { 302 db8500_esram12_reg: db8500_esram12 {
309 regulator-compatible = "db8500_esram12"; 303 regulator-compatible = "db8500_esram12";
310 regulator-name = "db8500-esram12";
311 }; 304 };
312 305
313 // DB8500_REGULATOR_SWITCH_ESRAM12RET 306 // DB8500_REGULATOR_SWITCH_ESRAM12RET
314 db8500_esram12_ret_reg: db8500_esram12_ret { 307 db8500_esram12_ret_reg: db8500_esram12_ret {
315 regulator-compatible = "db8500_esram12_ret"; 308 regulator-compatible = "db8500_esram12_ret";
316 regulator-name = "db8500-esram12-ret";
317 }; 309 };
318 310
319 // DB8500_REGULATOR_SWITCH_ESRAM34 311 // DB8500_REGULATOR_SWITCH_ESRAM34
320 db8500_esram34_reg: db8500_esram34 { 312 db8500_esram34_reg: db8500_esram34 {
321 regulator-compatible = "db8500_esram34"; 313 regulator-compatible = "db8500_esram34";
322 regulator-name = "db8500-esram34";
323 }; 314 };
324 315
325 // DB8500_REGULATOR_SWITCH_ESRAM34RET 316 // DB8500_REGULATOR_SWITCH_ESRAM34RET
326 db8500_esram34_ret_reg: db8500_esram34_ret { 317 db8500_esram34_ret_reg: db8500_esram34_ret {
327 regulator-compatible = "db8500_esram34_ret"; 318 regulator-compatible = "db8500_esram34_ret";
328 regulator-name = "db8500-esram34-ret";
329 }; 319 };
330 }; 320 };
331 321
@@ -352,7 +342,33 @@
352 vddadc-supply = <&ab8500_ldo_tvout_reg>; 342 vddadc-supply = <&ab8500_ldo_tvout_reg>;
353 }; 343 };
354 344
355 ab8500-usb { 345 ab8500_battery: ab8500_battery {
346 stericsson,battery-type = "LIPO";
347 thermistor-on-batctrl;
348 };
349
350 ab8500_fg {
351 compatible = "stericsson,ab8500-fg";
352 battery = <&ab8500_battery>;
353 };
354
355 ab8500_btemp {
356 compatible = "stericsson,ab8500-btemp";
357 battery = <&ab8500_battery>;
358 };
359
360 ab8500_charger {
361 compatible = "stericsson,ab8500-charger";
362 battery = <&ab8500_battery>;
363 vddadc-supply = <&ab8500_ldo_tvout_reg>;
364 };
365
366 ab8500_chargalg {
367 compatible = "stericsson,ab8500-chargalg";
368 battery = <&ab8500_battery>;
369 };
370
371 ab8500_usb {
356 compatible = "stericsson,ab8500-usb"; 372 compatible = "stericsson,ab8500-usb";
357 interrupts = < 90 0x4 373 interrupts = < 90 0x4
358 96 0x4 374 96 0x4
@@ -404,7 +420,6 @@
404 // supplies to the display/camera 420 // supplies to the display/camera
405 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { 421 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
406 regulator-compatible = "ab8500_ldo_aux1"; 422 regulator-compatible = "ab8500_ldo_aux1";
407 regulator-name = "V-DISPLAY";
408 regulator-min-microvolt = <2500000>; 423 regulator-min-microvolt = <2500000>;
409 regulator-max-microvolt = <2900000>; 424 regulator-max-microvolt = <2900000>;
410 regulator-boot-on; 425 regulator-boot-on;
@@ -415,7 +430,6 @@
415 // supplies to the on-board eMMC 430 // supplies to the on-board eMMC
416 ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { 431 ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
417 regulator-compatible = "ab8500_ldo_aux2"; 432 regulator-compatible = "ab8500_ldo_aux2";
418 regulator-name = "V-eMMC1";
419 regulator-min-microvolt = <1100000>; 433 regulator-min-microvolt = <1100000>;
420 regulator-max-microvolt = <3300000>; 434 regulator-max-microvolt = <3300000>;
421 }; 435 };
@@ -423,7 +437,6 @@
423 // supply for VAUX3; SDcard slots 437 // supply for VAUX3; SDcard slots
424 ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { 438 ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
425 regulator-compatible = "ab8500_ldo_aux3"; 439 regulator-compatible = "ab8500_ldo_aux3";
426 regulator-name = "V-MMC-SD";
427 regulator-min-microvolt = <1100000>; 440 regulator-min-microvolt = <1100000>;
428 regulator-max-microvolt = <3300000>; 441 regulator-max-microvolt = <3300000>;
429 }; 442 };
@@ -431,49 +444,41 @@
431 // supply for v-intcore12; VINTCORE12 LDO 444 // supply for v-intcore12; VINTCORE12 LDO
432 ab8500_ldo_initcore_reg: ab8500_ldo_initcore { 445 ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
433 regulator-compatible = "ab8500_ldo_initcore"; 446 regulator-compatible = "ab8500_ldo_initcore";
434 regulator-name = "V-INTCORE";
435 }; 447 };
436 448
437 // supply for tvout; gpadc; TVOUT LDO 449 // supply for tvout; gpadc; TVOUT LDO
438 ab8500_ldo_tvout_reg: ab8500_ldo_tvout { 450 ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
439 regulator-compatible = "ab8500_ldo_tvout"; 451 regulator-compatible = "ab8500_ldo_tvout";
440 regulator-name = "V-TVOUT";
441 }; 452 };
442 453
443 // supply for ab8500-usb; USB LDO 454 // supply for ab8500-usb; USB LDO
444 ab8500_ldo_usb_reg: ab8500_ldo_usb { 455 ab8500_ldo_usb_reg: ab8500_ldo_usb {
445 regulator-compatible = "ab8500_ldo_usb"; 456 regulator-compatible = "ab8500_ldo_usb";
446 regulator-name = "dummy";
447 }; 457 };
448 458
449 // supply for ab8500-vaudio; VAUDIO LDO 459 // supply for ab8500-vaudio; VAUDIO LDO
450 ab8500_ldo_audio_reg: ab8500_ldo_audio { 460 ab8500_ldo_audio_reg: ab8500_ldo_audio {
451 regulator-compatible = "ab8500_ldo_audio"; 461 regulator-compatible = "ab8500_ldo_audio";
452 regulator-name = "V-AUD";
453 }; 462 };
454 463
455 // supply for v-anamic1 VAMic1-LDO 464 // supply for v-anamic1 VAMic1-LDO
456 ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { 465 ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
457 regulator-compatible = "ab8500_ldo_anamic1"; 466 regulator-compatible = "ab8500_ldo_anamic1";
458 regulator-name = "V-AMIC1";
459 }; 467 };
460 468
461 // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 469 // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
462 ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 { 470 ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
463 regulator-compatible = "ab8500_ldo_amamic2"; 471 regulator-compatible = "ab8500_ldo_amamic2";
464 regulator-name = "V-AMIC2";
465 }; 472 };
466 473
467 // supply for v-dmic; VDMIC LDO 474 // supply for v-dmic; VDMIC LDO
468 ab8500_ldo_dmic_reg: ab8500_ldo_dmic { 475 ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
469 regulator-compatible = "ab8500_ldo_dmic"; 476 regulator-compatible = "ab8500_ldo_dmic";
470 regulator-name = "V-DMIC";
471 }; 477 };
472 478
473 // supply for U8500 CSI/DSI; VANA LDO 479 // supply for U8500 CSI/DSI; VANA LDO
474 ab8500_ldo_ana_reg: ab8500_ldo_ana { 480 ab8500_ldo_ana_reg: ab8500_ldo_ana {
475 regulator-compatible = "ab8500_ldo_ana"; 481 regulator-compatible = "ab8500_ldo_ana";
476 regulator-name = "V-CSI/DSI";
477 }; 482 };
478 }; 483 };
479 }; 484 };
@@ -577,42 +582,42 @@
577 status = "disabled"; 582 status = "disabled";
578 }; 583 };
579 584
580 sdi@80126000 { 585 sdi0_per1@80126000 {
581 compatible = "arm,pl18x", "arm,primecell"; 586 compatible = "arm,pl18x", "arm,primecell";
582 reg = <0x80126000 0x1000>; 587 reg = <0x80126000 0x1000>;
583 interrupts = <0 60 0x4>; 588 interrupts = <0 60 0x4>;
584 status = "disabled"; 589 status = "disabled";
585 }; 590 };
586 591
587 sdi@80118000 { 592 sdi1_per2@80118000 {
588 compatible = "arm,pl18x", "arm,primecell"; 593 compatible = "arm,pl18x", "arm,primecell";
589 reg = <0x80118000 0x1000>; 594 reg = <0x80118000 0x1000>;
590 interrupts = <0 50 0x4>; 595 interrupts = <0 50 0x4>;
591 status = "disabled"; 596 status = "disabled";
592 }; 597 };
593 598
594 sdi@80005000 { 599 sdi2_per3@80005000 {
595 compatible = "arm,pl18x", "arm,primecell"; 600 compatible = "arm,pl18x", "arm,primecell";
596 reg = <0x80005000 0x1000>; 601 reg = <0x80005000 0x1000>;
597 interrupts = <0 41 0x4>; 602 interrupts = <0 41 0x4>;
598 status = "disabled"; 603 status = "disabled";
599 }; 604 };
600 605
601 sdi@80119000 { 606 sdi3_per2@80119000 {
602 compatible = "arm,pl18x", "arm,primecell"; 607 compatible = "arm,pl18x", "arm,primecell";
603 reg = <0x80119000 0x1000>; 608 reg = <0x80119000 0x1000>;
604 interrupts = <0 59 0x4>; 609 interrupts = <0 59 0x4>;
605 status = "disabled"; 610 status = "disabled";
606 }; 611 };
607 612
608 sdi@80114000 { 613 sdi4_per2@80114000 {
609 compatible = "arm,pl18x", "arm,primecell"; 614 compatible = "arm,pl18x", "arm,primecell";
610 reg = <0x80114000 0x1000>; 615 reg = <0x80114000 0x1000>;
611 interrupts = <0 99 0x4>; 616 interrupts = <0 99 0x4>;
612 status = "disabled"; 617 status = "disabled";
613 }; 618 };
614 619
615 sdi@80008000 { 620 sdi5_per3@80008000 {
616 compatible = "arm,pl18x", "arm,primecell"; 621 compatible = "arm,pl18x", "arm,primecell";
617 reg = <0x80008000 0x1000>; 622 reg = <0x80008000 0x1000>;
618 interrupts = <0 100 0x4>; 623 interrupts = <0 100 0x4>;
@@ -660,5 +665,24 @@
660 ranges = <0 0x50000000 0x4000000>; 665 ranges = <0 0x50000000 0x4000000>;
661 status = "disabled"; 666 status = "disabled";
662 }; 667 };
668
669 cpufreq-cooling {
670 compatible = "stericsson,db8500-cpufreq-cooling";
671 status = "disabled";
672 };
673
674 vmmci: regulator-gpio {
675 compatible = "regulator-gpio";
676
677 regulator-min-microvolt = <1800000>;
678 regulator-max-microvolt = <2600000>;
679 regulator-name = "mmci-reg";
680 regulator-type = "voltage";
681
682 states = <1800000 0x1
683 2900000 0x0>;
684
685 status = "disabled";
686 };
663 }; 687 };
664}; 688};
diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
index 0adbd5a38095..fed7d3f9f431 100644
--- a/arch/arm/boot/dts/dove-cubox.dts
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -40,3 +40,13 @@
40 reg = <0>; 40 reg = <0>;
41 }; 41 };
42}; 42};
43
44&pinctrl {
45 pinctrl-0 = <&pmx_gpio_18>;
46 pinctrl-names = "default";
47
48 pmx_gpio_18: pmx-gpio-18 {
49 marvell,pins = "mpp18";
50 marvell,function = "gpio";
51 };
52};
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 5a00022383e7..42eac1ff3cc8 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -4,6 +4,12 @@
4 compatible = "marvell,dove"; 4 compatible = "marvell,dove";
5 model = "Marvell Armada 88AP510 SoC"; 5 model = "Marvell Armada 88AP510 SoC";
6 6
7 aliases {
8 gpio0 = &gpio0;
9 gpio1 = &gpio1;
10 gpio2 = &gpio2;
11 };
12
7 soc@f1000000 { 13 soc@f1000000 {
8 compatible = "simple-bus"; 14 compatible = "simple-bus";
9 #address-cells = <1>; 15 #address-cells = <1>;
@@ -31,6 +37,19 @@
31 reg = <0x20204 0x04>, <0x20214 0x04>; 37 reg = <0x20204 0x04>, <0x20214 0x04>;
32 }; 38 };
33 39
40 core_clk: core-clocks@d0214 {
41 compatible = "marvell,dove-core-clock";
42 reg = <0xd0214 0x4>;
43 #clock-cells = <1>;
44 };
45
46 gate_clk: clock-gating-control@d0038 {
47 compatible = "marvell,dove-gating-clock";
48 reg = <0xd0038 0x4>;
49 clocks = <&core_clk 0>;
50 #clock-cells = <1>;
51 };
52
34 uart0: serial@12000 { 53 uart0: serial@12000 {
35 compatible = "ns16550a"; 54 compatible = "ns16550a";
36 reg = <0x12000 0x100>; 55 reg = <0x12000 0x100>;
@@ -72,7 +91,8 @@
72 #gpio-cells = <2>; 91 #gpio-cells = <2>;
73 gpio-controller; 92 gpio-controller;
74 reg = <0xd0400 0x20>; 93 reg = <0xd0400 0x20>;
75 ngpio = <32>; 94 ngpios = <32>;
95 interrupt-controller;
76 interrupts = <12>, <13>, <14>, <60>; 96 interrupts = <12>, <13>, <14>, <60>;
77 }; 97 };
78 98
@@ -81,7 +101,8 @@
81 #gpio-cells = <2>; 101 #gpio-cells = <2>;
82 gpio-controller; 102 gpio-controller;
83 reg = <0xd0420 0x20>; 103 reg = <0xd0420 0x20>;
84 ngpio = <32>; 104 ngpios = <32>;
105 interrupt-controller;
85 interrupts = <61>; 106 interrupts = <61>;
86 }; 107 };
87 108
@@ -90,7 +111,13 @@
90 #gpio-cells = <2>; 111 #gpio-cells = <2>;
91 gpio-controller; 112 gpio-controller;
92 reg = <0xe8400 0x0c>; 113 reg = <0xe8400 0x0c>;
93 ngpio = <8>; 114 ngpios = <8>;
115 };
116
117 pinctrl: pinctrl@d0200 {
118 compatible = "marvell,dove-pinctrl";
119 reg = <0xd0200 0x10>;
120 clocks = <&gate_clk 22>;
94 }; 121 };
95 122
96 spi0: spi@10600 { 123 spi0: spi@10600 {
@@ -100,6 +127,7 @@
100 cell-index = <0>; 127 cell-index = <0>;
101 interrupts = <6>; 128 interrupts = <6>;
102 reg = <0x10600 0x28>; 129 reg = <0x10600 0x28>;
130 clocks = <&core_clk 0>;
103 status = "disabled"; 131 status = "disabled";
104 }; 132 };
105 133
@@ -110,6 +138,7 @@
110 cell-index = <1>; 138 cell-index = <1>;
111 interrupts = <5>; 139 interrupts = <5>;
112 reg = <0x14600 0x28>; 140 reg = <0x14600 0x28>;
141 clocks = <&core_clk 0>;
113 status = "disabled"; 142 status = "disabled";
114 }; 143 };
115 144
@@ -121,6 +150,7 @@
121 interrupts = <11>; 150 interrupts = <11>;
122 clock-frequency = <400000>; 151 clock-frequency = <400000>;
123 timeout-ms = <1000>; 152 timeout-ms = <1000>;
153 clocks = <&core_clk 0>;
124 status = "disabled"; 154 status = "disabled";
125 }; 155 };
126 156
@@ -128,6 +158,7 @@
128 compatible = "marvell,dove-sdhci"; 158 compatible = "marvell,dove-sdhci";
129 reg = <0x92000 0x100>; 159 reg = <0x92000 0x100>;
130 interrupts = <35>, <37>; 160 interrupts = <35>, <37>;
161 clocks = <&gate_clk 8>;
131 status = "disabled"; 162 status = "disabled";
132 }; 163 };
133 164
@@ -135,6 +166,7 @@
135 compatible = "marvell,dove-sdhci"; 166 compatible = "marvell,dove-sdhci";
136 reg = <0x90000 0x100>; 167 reg = <0x90000 0x100>;
137 interrupts = <36>, <38>; 168 interrupts = <36>, <38>;
169 clocks = <&gate_clk 9>;
138 status = "disabled"; 170 status = "disabled";
139 }; 171 };
140 172
@@ -142,6 +174,7 @@
142 compatible = "marvell,orion-sata"; 174 compatible = "marvell,orion-sata";
143 reg = <0xa0000 0x2400>; 175 reg = <0xa0000 0x2400>;
144 interrupts = <62>; 176 interrupts = <62>;
177 clocks = <&gate_clk 3>;
145 nr-ports = <1>; 178 nr-ports = <1>;
146 status = "disabled"; 179 status = "disabled";
147 }; 180 };
@@ -152,7 +185,50 @@
152 <0xc8000000 0x800>; 185 <0xc8000000 0x800>;
153 reg-names = "regs", "sram"; 186 reg-names = "regs", "sram";
154 interrupts = <31>; 187 interrupts = <31>;
188 clocks = <&gate_clk 15>;
189 status = "okay";
190 };
191
192 xor0: dma-engine@60800 {
193 compatible = "marvell,orion-xor";
194 reg = <0x60800 0x100
195 0x60a00 0x100>;
196 clocks = <&gate_clk 23>;
197 status = "okay";
198
199 channel0 {
200 interrupts = <39>;
201 dmacap,memcpy;
202 dmacap,xor;
203 };
204
205 channel1 {
206 interrupts = <40>;
207 dmacap,memset;
208 dmacap,memcpy;
209 dmacap,xor;
210 };
211 };
212
213 xor1: dma-engine@60900 {
214 compatible = "marvell,orion-xor";
215 reg = <0x60900 0x100
216 0x60b00 0x100>;
217 clocks = <&gate_clk 24>;
155 status = "okay"; 218 status = "okay";
219
220 channel0 {
221 interrupts = <42>;
222 dmacap,memcpy;
223 dmacap,xor;
224 };
225
226 channel1 {
227 interrupts = <43>;
228 dmacap,memset;
229 dmacap,memcpy;
230 dmacap,xor;
231 };
156 }; 232 };
157 }; 233 };
158}; 234};
diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts
new file mode 100644
index 000000000000..139b40cc3a23
--- /dev/null
+++ b/arch/arm/boot/dts/ecx-2000.dts
@@ -0,0 +1,108 @@
1/*
2 * Copyright 2011-2012 Calxeda, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/dts-v1/;
18
19/* First 4KB has pen for secondary cores. */
20/memreserve/ 0x00000000 0x0001000;
21
22/ {
23 model = "Calxeda ECX-2000";
24 compatible = "calxeda,ecx-2000";
25 #address-cells = <2>;
26 #size-cells = <2>;
27 clock-ranges;
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu@0 {
34 compatible = "arm,cortex-a15";
35 device_type = "cpu";
36 reg = <0>;
37 clocks = <&a9pll>;
38 clock-names = "cpu";
39 };
40
41 cpu@1 {
42 compatible = "arm,cortex-a15";
43 device_type = "cpu";
44 reg = <1>;
45 clocks = <&a9pll>;
46 clock-names = "cpu";
47 };
48
49 cpu@2 {
50 compatible = "arm,cortex-a15";
51 device_type = "cpu";
52 reg = <2>;
53 clocks = <&a9pll>;
54 clock-names = "cpu";
55 };
56
57 cpu@3 {
58 compatible = "arm,cortex-a15";
59 device_type = "cpu";
60 reg = <3>;
61 clocks = <&a9pll>;
62 clock-names = "cpu";
63 };
64 };
65
66 memory@0 {
67 name = "memory";
68 device_type = "memory";
69 reg = <0x00000000 0x00000000 0x00000000 0xff800000>;
70 };
71
72 memory@200000000 {
73 name = "memory";
74 device_type = "memory";
75 reg = <0x00000002 0x00000000 0x00000003 0x00000000>;
76 };
77
78 soc {
79 ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>;
80
81 timer {
82 compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; interrupts = <1 13 0xf08>,
83 <1 14 0xf08>,
84 <1 11 0xf08>,
85 <1 10 0xf08>;
86 };
87
88 intc: interrupt-controller@fff11000 {
89 compatible = "arm,cortex-a15-gic";
90 #interrupt-cells = <3>;
91 #size-cells = <0>;
92 #address-cells = <1>;
93 interrupt-controller;
94 interrupts = <1 9 0xf04>;
95 reg = <0xfff11000 0x1000>,
96 <0xfff12000 0x1000>,
97 <0xfff14000 0x2000>,
98 <0xfff16000 0x2000>;
99 };
100
101 pmu {
102 compatible = "arm,cortex-a9-pmu";
103 interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
104 };
105 };
106};
107
108/include/ "ecx-common.dtsi"
diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi
new file mode 100644
index 000000000000..d61b535f682a
--- /dev/null
+++ b/arch/arm/boot/dts/ecx-common.dtsi
@@ -0,0 +1,237 @@
1/*
2 * Copyright 2011-2012 Calxeda, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/ {
18 chosen {
19 bootargs = "console=ttyAMA0";
20 };
21
22 soc {
23 #address-cells = <1>;
24 #size-cells = <1>;
25 compatible = "simple-bus";
26 interrupt-parent = <&intc>;
27
28 sata@ffe08000 {
29 compatible = "calxeda,hb-ahci";
30 reg = <0xffe08000 0x10000>;
31 interrupts = <0 83 4>;
32 dma-coherent;
33 calxeda,port-phys = <&combophy5 0 &combophy0 0
34 &combophy0 1 &combophy0 2
35 &combophy0 3>;
36 };
37
38 sdhci@ffe0e000 {
39 compatible = "calxeda,hb-sdhci";
40 reg = <0xffe0e000 0x1000>;
41 interrupts = <0 90 4>;
42 clocks = <&eclk>;
43 status = "disabled";
44 };
45
46 memory-controller@fff00000 {
47 compatible = "calxeda,hb-ddr-ctrl";
48 reg = <0xfff00000 0x1000>;
49 interrupts = <0 91 4>;
50 };
51
52 ipc@fff20000 {
53 compatible = "arm,pl320", "arm,primecell";
54 reg = <0xfff20000 0x1000>;
55 interrupts = <0 7 4>;
56 clocks = <&pclk>;
57 clock-names = "apb_pclk";
58 };
59
60 gpioe: gpio@fff30000 {
61 #gpio-cells = <2>;
62 compatible = "arm,pl061", "arm,primecell";
63 gpio-controller;
64 reg = <0xfff30000 0x1000>;
65 interrupts = <0 14 4>;
66 clocks = <&pclk>;
67 clock-names = "apb_pclk";
68 status = "disabled";
69 };
70
71 gpiof: gpio@fff31000 {
72 #gpio-cells = <2>;
73 compatible = "arm,pl061", "arm,primecell";
74 gpio-controller;
75 reg = <0xfff31000 0x1000>;
76 interrupts = <0 15 4>;
77 clocks = <&pclk>;
78 clock-names = "apb_pclk";
79 status = "disabled";
80 };
81
82 gpiog: gpio@fff32000 {
83 #gpio-cells = <2>;
84 compatible = "arm,pl061", "arm,primecell";
85 gpio-controller;
86 reg = <0xfff32000 0x1000>;
87 interrupts = <0 16 4>;
88 clocks = <&pclk>;
89 clock-names = "apb_pclk";
90 status = "disabled";
91 };
92
93 gpioh: gpio@fff33000 {
94 #gpio-cells = <2>;
95 compatible = "arm,pl061", "arm,primecell";
96 gpio-controller;
97 reg = <0xfff33000 0x1000>;
98 interrupts = <0 17 4>;
99 clocks = <&pclk>;
100 clock-names = "apb_pclk";
101 status = "disabled";
102 };
103
104 timer@fff34000 {
105 compatible = "arm,sp804", "arm,primecell";
106 reg = <0xfff34000 0x1000>;
107 interrupts = <0 18 4>;
108 clocks = <&pclk>;
109 clock-names = "apb_pclk";
110 };
111
112 rtc@fff35000 {
113 compatible = "arm,pl031", "arm,primecell";
114 reg = <0xfff35000 0x1000>;
115 interrupts = <0 19 4>;
116 clocks = <&pclk>;
117 clock-names = "apb_pclk";
118 };
119
120 serial@fff36000 {
121 compatible = "arm,pl011", "arm,primecell";
122 reg = <0xfff36000 0x1000>;
123 interrupts = <0 20 4>;
124 clocks = <&pclk>;
125 clock-names = "apb_pclk";
126 };
127
128 smic@fff3a000 {
129 compatible = "ipmi-smic";
130 device_type = "ipmi";
131 reg = <0xfff3a000 0x1000>;
132 interrupts = <0 24 4>;
133 reg-size = <4>;
134 reg-spacing = <4>;
135 };
136
137 sregs@fff3c000 {
138 compatible = "calxeda,hb-sregs";
139 reg = <0xfff3c000 0x1000>;
140
141 clocks {
142 #address-cells = <1>;
143 #size-cells = <0>;
144
145 osc: oscillator {
146 #clock-cells = <0>;
147 compatible = "fixed-clock";
148 clock-frequency = <33333000>;
149 };
150
151 ddrpll: ddrpll {
152 #clock-cells = <0>;
153 compatible = "calxeda,hb-pll-clock";
154 clocks = <&osc>;
155 reg = <0x108>;
156 };
157
158 a9pll: a9pll {
159 #clock-cells = <0>;
160 compatible = "calxeda,hb-pll-clock";
161 clocks = <&osc>;
162 reg = <0x100>;
163 };
164
165 a9periphclk: a9periphclk {
166 #clock-cells = <0>;
167 compatible = "calxeda,hb-a9periph-clock";
168 clocks = <&a9pll>;
169 reg = <0x104>;
170 };
171
172 a9bclk: a9bclk {
173 #clock-cells = <0>;
174 compatible = "calxeda,hb-a9bus-clock";
175 clocks = <&a9pll>;
176 reg = <0x104>;
177 };
178
179 emmcpll: emmcpll {
180 #clock-cells = <0>;
181 compatible = "calxeda,hb-pll-clock";
182 clocks = <&osc>;
183 reg = <0x10C>;
184 };
185
186 eclk: eclk {
187 #clock-cells = <0>;
188 compatible = "calxeda,hb-emmc-clock";
189 clocks = <&emmcpll>;
190 reg = <0x114>;
191 };
192
193 pclk: pclk {
194 #clock-cells = <0>;
195 compatible = "fixed-clock";
196 clock-frequency = <150000000>;
197 };
198 };
199 };
200
201 dma@fff3d000 {
202 compatible = "arm,pl330", "arm,primecell";
203 reg = <0xfff3d000 0x1000>;
204 interrupts = <0 92 4>;
205 clocks = <&pclk>;
206 clock-names = "apb_pclk";
207 };
208
209 ethernet@fff50000 {
210 compatible = "calxeda,hb-xgmac";
211 reg = <0xfff50000 0x1000>;
212 interrupts = <0 77 4 0 78 4 0 79 4>;
213 dma-coherent;
214 };
215
216 ethernet@fff51000 {
217 compatible = "calxeda,hb-xgmac";
218 reg = <0xfff51000 0x1000>;
219 interrupts = <0 80 4 0 81 4 0 82 4>;
220 dma-coherent;
221 };
222
223 combophy0: combo-phy@fff58000 {
224 compatible = "calxeda,hb-combophy";
225 #phy-cells = <1>;
226 reg = <0xfff58000 0x1000>;
227 phydev = <5>;
228 };
229
230 combophy5: combo-phy@fff5d000 {
231 compatible = "calxeda,hb-combophy";
232 #phy-cells = <1>;
233 reg = <0xfff5d000 0x1000>;
234 phydev = <31>;
235 };
236 };
237};
diff --git a/arch/arm/boot/dts/evk-pro3.dts b/arch/arm/boot/dts/evk-pro3.dts
index b7354e6506de..96e50f569433 100644
--- a/arch/arm/boot/dts/evk-pro3.dts
+++ b/arch/arm/boot/dts/evk-pro3.dts
@@ -22,10 +22,22 @@
22 status = "okay"; 22 status = "okay";
23 }; 23 };
24 24
25 usart0: serial@fffb0000 {
26 status = "okay";
27 };
28
29 usart2: serial@fffb8000 {
30 status = "okay";
31 };
32
25 usb1: gadget@fffa4000 { 33 usb1: gadget@fffa4000 {
26 atmel,vbus-gpio = <&pioC 5 0>; 34 atmel,vbus-gpio = <&pioC 5 0>;
27 status = "okay"; 35 status = "okay";
28 }; 36 };
37
38 watchdog@fffffd40 {
39 status = "okay";
40 };
29 }; 41 };
30 42
31 usb0: ohci@00500000 { 43 usb0: ohci@00500000 {
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index a26c3dd58269..e1347fceb5bc 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -28,6 +28,44 @@
28 spi0 = &spi_0; 28 spi0 = &spi_0;
29 spi1 = &spi_1; 29 spi1 = &spi_1;
30 spi2 = &spi_2; 30 spi2 = &spi_2;
31 i2c0 = &i2c_0;
32 i2c1 = &i2c_1;
33 i2c2 = &i2c_2;
34 i2c3 = &i2c_3;
35 i2c4 = &i2c_4;
36 i2c5 = &i2c_5;
37 i2c6 = &i2c_6;
38 i2c7 = &i2c_7;
39 };
40
41 pd_mfc: mfc-power-domain@10023C40 {
42 compatible = "samsung,exynos4210-pd";
43 reg = <0x10023C40 0x20>;
44 };
45
46 pd_g3d: g3d-power-domain@10023C60 {
47 compatible = "samsung,exynos4210-pd";
48 reg = <0x10023C60 0x20>;
49 };
50
51 pd_lcd0: lcd0-power-domain@10023C80 {
52 compatible = "samsung,exynos4210-pd";
53 reg = <0x10023C80 0x20>;
54 };
55
56 pd_tv: tv-power-domain@10023C20 {
57 compatible = "samsung,exynos4210-pd";
58 reg = <0x10023C20 0x20>;
59 };
60
61 pd_cam: cam-power-domain@10023C00 {
62 compatible = "samsung,exynos4210-pd";
63 reg = <0x10023C00 0x20>;
64 };
65
66 pd_gps: gps-power-domain@10023CE0 {
67 compatible = "samsung,exynos4210-pd";
68 reg = <0x10023CE0 0x20>;
31 }; 69 };
32 70
33 gic:interrupt-controller@10490000 { 71 gic:interrupt-controller@10490000 {
@@ -121,7 +159,7 @@
121 status = "disabled"; 159 status = "disabled";
122 }; 160 };
123 161
124 i2c@13860000 { 162 i2c_0: i2c@13860000 {
125 #address-cells = <1>; 163 #address-cells = <1>;
126 #size-cells = <0>; 164 #size-cells = <0>;
127 compatible = "samsung,s3c2440-i2c"; 165 compatible = "samsung,s3c2440-i2c";
@@ -130,7 +168,7 @@
130 status = "disabled"; 168 status = "disabled";
131 }; 169 };
132 170
133 i2c@13870000 { 171 i2c_1: i2c@13870000 {
134 #address-cells = <1>; 172 #address-cells = <1>;
135 #size-cells = <0>; 173 #size-cells = <0>;
136 compatible = "samsung,s3c2440-i2c"; 174 compatible = "samsung,s3c2440-i2c";
@@ -139,7 +177,7 @@
139 status = "disabled"; 177 status = "disabled";
140 }; 178 };
141 179
142 i2c@13880000 { 180 i2c_2: i2c@13880000 {
143 #address-cells = <1>; 181 #address-cells = <1>;
144 #size-cells = <0>; 182 #size-cells = <0>;
145 compatible = "samsung,s3c2440-i2c"; 183 compatible = "samsung,s3c2440-i2c";
@@ -148,7 +186,7 @@
148 status = "disabled"; 186 status = "disabled";
149 }; 187 };
150 188
151 i2c@13890000 { 189 i2c_3: i2c@13890000 {
152 #address-cells = <1>; 190 #address-cells = <1>;
153 #size-cells = <0>; 191 #size-cells = <0>;
154 compatible = "samsung,s3c2440-i2c"; 192 compatible = "samsung,s3c2440-i2c";
@@ -157,7 +195,7 @@
157 status = "disabled"; 195 status = "disabled";
158 }; 196 };
159 197
160 i2c@138A0000 { 198 i2c_4: i2c@138A0000 {
161 #address-cells = <1>; 199 #address-cells = <1>;
162 #size-cells = <0>; 200 #size-cells = <0>;
163 compatible = "samsung,s3c2440-i2c"; 201 compatible = "samsung,s3c2440-i2c";
@@ -166,7 +204,7 @@
166 status = "disabled"; 204 status = "disabled";
167 }; 205 };
168 206
169 i2c@138B0000 { 207 i2c_5: i2c@138B0000 {
170 #address-cells = <1>; 208 #address-cells = <1>;
171 #size-cells = <0>; 209 #size-cells = <0>;
172 compatible = "samsung,s3c2440-i2c"; 210 compatible = "samsung,s3c2440-i2c";
@@ -175,7 +213,7 @@
175 status = "disabled"; 213 status = "disabled";
176 }; 214 };
177 215
178 i2c@138C0000 { 216 i2c_6: i2c@138C0000 {
179 #address-cells = <1>; 217 #address-cells = <1>;
180 #size-cells = <0>; 218 #size-cells = <0>;
181 compatible = "samsung,s3c2440-i2c"; 219 compatible = "samsung,s3c2440-i2c";
@@ -184,7 +222,7 @@
184 status = "disabled"; 222 status = "disabled";
185 }; 223 };
186 224
187 i2c@138D0000 { 225 i2c_7: i2c@138D0000 {
188 #address-cells = <1>; 226 #address-cells = <1>;
189 #size-cells = <0>; 227 #size-cells = <0>;
190 compatible = "samsung,s3c2440-i2c"; 228 compatible = "samsung,s3c2440-i2c";
@@ -244,5 +282,11 @@
244 reg = <0x12690000 0x1000>; 282 reg = <0x12690000 0x1000>;
245 interrupts = <0 36 0>; 283 interrupts = <0 36 0>;
246 }; 284 };
285
286 mdma1: mdma@12850000 {
287 compatible = "arm,pl330", "arm,primecell";
288 reg = <0x12850000 0x1000>;
289 interrupts = <0 34 0>;
290 };
247 }; 291 };
248}; 292};
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index 3e68f52e8454..f2710018e84e 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -22,38 +22,54 @@
22 compatible = "insignal,origen", "samsung,exynos4210"; 22 compatible = "insignal,origen", "samsung,exynos4210";
23 23
24 memory { 24 memory {
25 reg = <0x40000000 0x40000000>; 25 reg = <0x40000000 0x10000000
26 0x50000000 0x10000000
27 0x60000000 0x10000000
28 0x70000000 0x10000000>;
26 }; 29 };
27 30
28 chosen { 31 chosen {
29 bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; 32 bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
30 }; 33 };
31 34
35 mmc_reg: voltage-regulator {
36 compatible = "regulator-fixed";
37 regulator-name = "VMEM_VDD_2.8V";
38 regulator-min-microvolt = <2800000>;
39 regulator-max-microvolt = <2800000>;
40 gpio = <&gpx1 1 0>;
41 enable-active-high;
42 };
43
32 sdhci@12530000 { 44 sdhci@12530000 {
33 samsung,sdhci-bus-width = <4>; 45 bus-width = <4>;
34 linux,mmc_cap_4_bit_data; 46 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
35 samsung,sdhci-cd-internal; 47 pinctrl-names = "default";
36 gpio-cd = <&gpk2 2 2 3 3>; 48 vmmc-supply = <&mmc_reg>;
37 gpios = <&gpk2 0 2 0 3>,
38 <&gpk2 1 2 0 3>,
39 <&gpk2 3 2 3 3>,
40 <&gpk2 4 2 3 3>,
41 <&gpk2 5 2 3 3>,
42 <&gpk2 6 2 3 3>;
43 status = "okay"; 49 status = "okay";
44 }; 50 };
45 51
46 sdhci@12510000 { 52 sdhci@12510000 {
47 samsung,sdhci-bus-width = <4>; 53 bus-width = <4>;
48 linux,mmc_cap_4_bit_data; 54 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_cd>;
49 samsung,sdhci-cd-internal; 55 pinctrl-names = "default";
50 gpio-cd = <&gpk0 2 2 3 3>; 56 vmmc-supply = <&mmc_reg>;
51 gpios = <&gpk0 0 2 0 3>, 57 status = "okay";
52 <&gpk0 1 2 0 3>, 58 };
53 <&gpk0 3 2 3 3>, 59
54 <&gpk0 4 2 3 3>, 60 serial@13800000 {
55 <&gpk0 5 2 3 3>, 61 status = "okay";
56 <&gpk0 6 2 3 3>; 62 };
63
64 serial@13810000 {
65 status = "okay";
66 };
67
68 serial@13820000 {
69 status = "okay";
70 };
71
72 serial@13830000 {
57 status = "okay"; 73 status = "okay";
58 }; 74 };
59 75
@@ -64,35 +80,35 @@
64 80
65 up { 81 up {
66 label = "Up"; 82 label = "Up";
67 gpios = <&gpx2 0 0 0x10000 2>; 83 gpios = <&gpx2 0 1>;
68 linux,code = <103>; 84 linux,code = <103>;
69 gpio-key,wakeup; 85 gpio-key,wakeup;
70 }; 86 };
71 87
72 down { 88 down {
73 label = "Down"; 89 label = "Down";
74 gpios = <&gpx2 1 0 0x10000 2>; 90 gpios = <&gpx2 1 1>;
75 linux,code = <108>; 91 linux,code = <108>;
76 gpio-key,wakeup; 92 gpio-key,wakeup;
77 }; 93 };
78 94
79 back { 95 back {
80 label = "Back"; 96 label = "Back";
81 gpios = <&gpx1 7 0 0x10000 2>; 97 gpios = <&gpx1 7 1>;
82 linux,code = <158>; 98 linux,code = <158>;
83 gpio-key,wakeup; 99 gpio-key,wakeup;
84 }; 100 };
85 101
86 home { 102 home {
87 label = "Home"; 103 label = "Home";
88 gpios = <&gpx1 6 0 0x10000 2>; 104 gpios = <&gpx1 6 1>;
89 linux,code = <102>; 105 linux,code = <102>;
90 gpio-key,wakeup; 106 gpio-key,wakeup;
91 }; 107 };
92 108
93 menu { 109 menu {
94 label = "Menu"; 110 label = "Menu";
95 gpios = <&gpx1 5 0 0x10000 2>; 111 gpios = <&gpx1 5 1>;
96 linux,code = <139>; 112 linux,code = <139>;
97 gpio-key,wakeup; 113 gpio-key,wakeup;
98 }; 114 };
@@ -101,7 +117,7 @@
101 leds { 117 leds {
102 compatible = "gpio-leds"; 118 compatible = "gpio-leds";
103 status { 119 status {
104 gpios = <&gpx1 3 0 0x10000 2>; 120 gpios = <&gpx1 3 1>;
105 linux,default-trigger = "heartbeat"; 121 linux,default-trigger = "heartbeat";
106 }; 122 };
107 }; 123 };
diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
index b12cf272ad0d..55a2efb763d1 100644
--- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
@@ -16,6 +16,134 @@
16 16
17/ { 17/ {
18 pinctrl@11400000 { 18 pinctrl@11400000 {
19 gpa0: gpa0 {
20 gpio-controller;
21 #gpio-cells = <2>;
22
23 interrupt-controller;
24 #interrupt-cells = <2>;
25 };
26
27 gpa1: gpa1 {
28 gpio-controller;
29 #gpio-cells = <2>;
30
31 interrupt-controller;
32 #interrupt-cells = <2>;
33 };
34
35 gpb: gpb {
36 gpio-controller;
37 #gpio-cells = <2>;
38
39 interrupt-controller;
40 #interrupt-cells = <2>;
41 };
42
43 gpc0: gpc0 {
44 gpio-controller;
45 #gpio-cells = <2>;
46
47 interrupt-controller;
48 #interrupt-cells = <2>;
49 };
50
51 gpc1: gpc1 {
52 gpio-controller;
53 #gpio-cells = <2>;
54
55 interrupt-controller;
56 #interrupt-cells = <2>;
57 };
58
59 gpd0: gpd0 {
60 gpio-controller;
61 #gpio-cells = <2>;
62
63 interrupt-controller;
64 #interrupt-cells = <2>;
65 };
66
67 gpd1: gpd1 {
68 gpio-controller;
69 #gpio-cells = <2>;
70
71 interrupt-controller;
72 #interrupt-cells = <2>;
73 };
74
75 gpe0: gpe0 {
76 gpio-controller;
77 #gpio-cells = <2>;
78
79 interrupt-controller;
80 #interrupt-cells = <2>;
81 };
82
83 gpe1: gpe1 {
84 gpio-controller;
85 #gpio-cells = <2>;
86
87 interrupt-controller;
88 #interrupt-cells = <2>;
89 };
90
91 gpe2: gpe2 {
92 gpio-controller;
93 #gpio-cells = <2>;
94
95 interrupt-controller;
96 #interrupt-cells = <2>;
97 };
98
99 gpe3: gpe3 {
100 gpio-controller;
101 #gpio-cells = <2>;
102
103 interrupt-controller;
104 #interrupt-cells = <2>;
105 };
106
107 gpe4: gpe4 {
108 gpio-controller;
109 #gpio-cells = <2>;
110
111 interrupt-controller;
112 #interrupt-cells = <2>;
113 };
114
115 gpf0: gpf0 {
116 gpio-controller;
117 #gpio-cells = <2>;
118
119 interrupt-controller;
120 #interrupt-cells = <2>;
121 };
122
123 gpf1: gpf1 {
124 gpio-controller;
125 #gpio-cells = <2>;
126
127 interrupt-controller;
128 #interrupt-cells = <2>;
129 };
130
131 gpf2: gpf2 {
132 gpio-controller;
133 #gpio-cells = <2>;
134
135 interrupt-controller;
136 #interrupt-cells = <2>;
137 };
138
139 gpf3: gpf3 {
140 gpio-controller;
141 #gpio-cells = <2>;
142
143 interrupt-controller;
144 #interrupt-cells = <2>;
145 };
146
19 uart0_data: uart0-data { 147 uart0_data: uart0-data {
20 samsung,pins = "gpa0-0", "gpa0-1"; 148 samsung,pins = "gpa0-0", "gpa0-1";
21 samsung,pin-function = <0x2>; 149 samsung,pin-function = <0x2>;
@@ -205,200 +333,345 @@
205 }; 333 };
206 334
207 pinctrl@11000000 { 335 pinctrl@11000000 {
336 gpj0: gpj0 {
337 gpio-controller;
338 #gpio-cells = <2>;
339
340 interrupt-controller;
341 #interrupt-cells = <2>;
342 };
343
344 gpj1: gpj1 {
345 gpio-controller;
346 #gpio-cells = <2>;
347
348 interrupt-controller;
349 #interrupt-cells = <2>;
350 };
351
352 gpk0: gpk0 {
353 gpio-controller;
354 #gpio-cells = <2>;
355
356 interrupt-controller;
357 #interrupt-cells = <2>;
358 };
359
360 gpk1: gpk1 {
361 gpio-controller;
362 #gpio-cells = <2>;
363
364 interrupt-controller;
365 #interrupt-cells = <2>;
366 };
367
368 gpk2: gpk2 {
369 gpio-controller;
370 #gpio-cells = <2>;
371
372 interrupt-controller;
373 #interrupt-cells = <2>;
374 };
375
376 gpk3: gpk3 {
377 gpio-controller;
378 #gpio-cells = <2>;
379
380 interrupt-controller;
381 #interrupt-cells = <2>;
382 };
383
384 gpl0: gpl0 {
385 gpio-controller;
386 #gpio-cells = <2>;
387
388 interrupt-controller;
389 #interrupt-cells = <2>;
390 };
391
392 gpl1: gpl1 {
393 gpio-controller;
394 #gpio-cells = <2>;
395
396 interrupt-controller;
397 #interrupt-cells = <2>;
398 };
399
400 gpl2: gpl2 {
401 gpio-controller;
402 #gpio-cells = <2>;
403
404 interrupt-controller;
405 #interrupt-cells = <2>;
406 };
407
408 gpy0: gpy0 {
409 gpio-controller;
410 #gpio-cells = <2>;
411 };
412
413 gpy1: gpy1 {
414 gpio-controller;
415 #gpio-cells = <2>;
416 };
417
418 gpy2: gpy2 {
419 gpio-controller;
420 #gpio-cells = <2>;
421 };
422
423 gpy3: gpy3 {
424 gpio-controller;
425 #gpio-cells = <2>;
426 };
427
428 gpy4: gpy4 {
429 gpio-controller;
430 #gpio-cells = <2>;
431 };
432
433 gpy5: gpy5 {
434 gpio-controller;
435 #gpio-cells = <2>;
436 };
437
438 gpy6: gpy6 {
439 gpio-controller;
440 #gpio-cells = <2>;
441 };
442
443 gpx0: gpx0 {
444 gpio-controller;
445 #gpio-cells = <2>;
446
447 interrupt-controller;
448 interrupt-parent = <&gic>;
449 interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
450 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
451 #interrupt-cells = <2>;
452 };
453
454 gpx1: gpx1 {
455 gpio-controller;
456 #gpio-cells = <2>;
457
458 interrupt-controller;
459 interrupt-parent = <&gic>;
460 interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
461 <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
462 #interrupt-cells = <2>;
463 };
464
465 gpx2: gpx2 {
466 gpio-controller;
467 #gpio-cells = <2>;
468
469 interrupt-controller;
470 #interrupt-cells = <2>;
471 };
472
473 gpx3: gpx3 {
474 gpio-controller;
475 #gpio-cells = <2>;
476
477 interrupt-controller;
478 #interrupt-cells = <2>;
479 };
480
208 sd0_clk: sd0-clk { 481 sd0_clk: sd0-clk {
209 samsung,pins = "gpk0-0"; 482 samsung,pins = "gpk0-0";
210 samsung,pin-function = <2>; 483 samsung,pin-function = <2>;
211 samsung,pin-pud = <0>; 484 samsung,pin-pud = <0>;
212 samsung,pin-drv = <0>; 485 samsung,pin-drv = <3>;
213 }; 486 };
214 487
215 sd0_cmd: sd0-cmd { 488 sd0_cmd: sd0-cmd {
216 samsung,pins = "gpk0-1"; 489 samsung,pins = "gpk0-1";
217 samsung,pin-function = <2>; 490 samsung,pin-function = <2>;
218 samsung,pin-pud = <0>; 491 samsung,pin-pud = <0>;
219 samsung,pin-drv = <0>; 492 samsung,pin-drv = <3>;
220 }; 493 };
221 494
222 sd0_cd: sd0-cd { 495 sd0_cd: sd0-cd {
223 samsung,pins = "gpk0-2"; 496 samsung,pins = "gpk0-2";
224 samsung,pin-function = <2>; 497 samsung,pin-function = <2>;
225 samsung,pin-pud = <3>; 498 samsung,pin-pud = <3>;
226 samsung,pin-drv = <0>; 499 samsung,pin-drv = <3>;
227 }; 500 };
228 501
229 sd0_bus1: sd0-bus-width1 { 502 sd0_bus1: sd0-bus-width1 {
230 samsung,pins = "gpk0-3"; 503 samsung,pins = "gpk0-3";
231 samsung,pin-function = <2>; 504 samsung,pin-function = <2>;
232 samsung,pin-pud = <3>; 505 samsung,pin-pud = <3>;
233 samsung,pin-drv = <0>; 506 samsung,pin-drv = <3>;
234 }; 507 };
235 508
236 sd0_bus4: sd0-bus-width4 { 509 sd0_bus4: sd0-bus-width4 {
237 samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; 510 samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
238 samsung,pin-function = <2>; 511 samsung,pin-function = <2>;
239 samsung,pin-pud = <3>; 512 samsung,pin-pud = <3>;
240 samsung,pin-drv = <0>; 513 samsung,pin-drv = <3>;
241 }; 514 };
242 515
243 sd0_bus8: sd0-bus-width8 { 516 sd0_bus8: sd0-bus-width8 {
244 samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; 517 samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
245 samsung,pin-function = <3>; 518 samsung,pin-function = <3>;
246 samsung,pin-pud = <3>; 519 samsung,pin-pud = <3>;
247 samsung,pin-drv = <0>; 520 samsung,pin-drv = <3>;
248 }; 521 };
249 522
250 sd4_clk: sd4-clk { 523 sd4_clk: sd4-clk {
251 samsung,pins = "gpk0-0"; 524 samsung,pins = "gpk0-0";
252 samsung,pin-function = <3>; 525 samsung,pin-function = <3>;
253 samsung,pin-pud = <0>; 526 samsung,pin-pud = <0>;
254 samsung,pin-drv = <0>; 527 samsung,pin-drv = <3>;
255 }; 528 };
256 529
257 sd4_cmd: sd4-cmd { 530 sd4_cmd: sd4-cmd {
258 samsung,pins = "gpk0-1"; 531 samsung,pins = "gpk0-1";
259 samsung,pin-function = <3>; 532 samsung,pin-function = <3>;
260 samsung,pin-pud = <0>; 533 samsung,pin-pud = <0>;
261 samsung,pin-drv = <0>; 534 samsung,pin-drv = <3>;
262 }; 535 };
263 536
264 sd4_cd: sd4-cd { 537 sd4_cd: sd4-cd {
265 samsung,pins = "gpk0-2"; 538 samsung,pins = "gpk0-2";
266 samsung,pin-function = <3>; 539 samsung,pin-function = <3>;
267 samsung,pin-pud = <3>; 540 samsung,pin-pud = <3>;
268 samsung,pin-drv = <0>; 541 samsung,pin-drv = <3>;
269 }; 542 };
270 543
271 sd4_bus1: sd4-bus-width1 { 544 sd4_bus1: sd4-bus-width1 {
272 samsung,pins = "gpk0-3"; 545 samsung,pins = "gpk0-3";
273 samsung,pin-function = <3>; 546 samsung,pin-function = <3>;
274 samsung,pin-pud = <3>; 547 samsung,pin-pud = <3>;
275 samsung,pin-drv = <0>; 548 samsung,pin-drv = <3>;
276 }; 549 };
277 550
278 sd4_bus4: sd4-bus-width4 { 551 sd4_bus4: sd4-bus-width4 {
279 samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; 552 samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
280 samsung,pin-function = <3>; 553 samsung,pin-function = <3>;
281 samsung,pin-pud = <3>; 554 samsung,pin-pud = <3>;
282 samsung,pin-drv = <0>; 555 samsung,pin-drv = <3>;
283 }; 556 };
284 557
285 sd4_bus8: sd4-bus-width8 { 558 sd4_bus8: sd4-bus-width8 {
286 samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; 559 samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
287 samsung,pin-function = <3>; 560 samsung,pin-function = <3>;
288 samsung,pin-pud = <4>; 561 samsung,pin-pud = <4>;
289 samsung,pin-drv = <0>; 562 samsung,pin-drv = <3>;
290 }; 563 };
291 564
292 sd1_clk: sd1-clk { 565 sd1_clk: sd1-clk {
293 samsung,pins = "gpk1-0"; 566 samsung,pins = "gpk1-0";
294 samsung,pin-function = <2>; 567 samsung,pin-function = <2>;
295 samsung,pin-pud = <0>; 568 samsung,pin-pud = <0>;
296 samsung,pin-drv = <0>; 569 samsung,pin-drv = <3>;
297 }; 570 };
298 571
299 sd1_cmd: sd1-cmd { 572 sd1_cmd: sd1-cmd {
300 samsung,pins = "gpk1-1"; 573 samsung,pins = "gpk1-1";
301 samsung,pin-function = <2>; 574 samsung,pin-function = <2>;
302 samsung,pin-pud = <0>; 575 samsung,pin-pud = <0>;
303 samsung,pin-drv = <0>; 576 samsung,pin-drv = <3>;
304 }; 577 };
305 578
306 sd1_cd: sd1-cd { 579 sd1_cd: sd1-cd {
307 samsung,pins = "gpk1-2"; 580 samsung,pins = "gpk1-2";
308 samsung,pin-function = <2>; 581 samsung,pin-function = <2>;
309 samsung,pin-pud = <3>; 582 samsung,pin-pud = <3>;
310 samsung,pin-drv = <0>; 583 samsung,pin-drv = <3>;
311 }; 584 };
312 585
313 sd1_bus1: sd1-bus-width1 { 586 sd1_bus1: sd1-bus-width1 {
314 samsung,pins = "gpk1-3"; 587 samsung,pins = "gpk1-3";
315 samsung,pin-function = <2>; 588 samsung,pin-function = <2>;
316 samsung,pin-pud = <3>; 589 samsung,pin-pud = <3>;
317 samsung,pin-drv = <0>; 590 samsung,pin-drv = <3>;
318 }; 591 };
319 592
320 sd1_bus4: sd1-bus-width4 { 593 sd1_bus4: sd1-bus-width4 {
321 samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; 594 samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
322 samsung,pin-function = <2>; 595 samsung,pin-function = <2>;
323 samsung,pin-pud = <3>; 596 samsung,pin-pud = <3>;
324 samsung,pin-drv = <0>; 597 samsung,pin-drv = <3>;
325 }; 598 };
326 599
327 sd2_clk: sd2-clk { 600 sd2_clk: sd2-clk {
328 samsung,pins = "gpk2-0"; 601 samsung,pins = "gpk2-0";
329 samsung,pin-function = <2>; 602 samsung,pin-function = <2>;
330 samsung,pin-pud = <0>; 603 samsung,pin-pud = <0>;
331 samsung,pin-drv = <0>; 604 samsung,pin-drv = <3>;
332 }; 605 };
333 606
334 sd2_cmd: sd2-cmd { 607 sd2_cmd: sd2-cmd {
335 samsung,pins = "gpk2-1"; 608 samsung,pins = "gpk2-1";
336 samsung,pin-function = <2>; 609 samsung,pin-function = <2>;
337 samsung,pin-pud = <0>; 610 samsung,pin-pud = <0>;
338 samsung,pin-drv = <0>; 611 samsung,pin-drv = <3>;
339 }; 612 };
340 613
341 sd2_cd: sd2-cd { 614 sd2_cd: sd2-cd {
342 samsung,pins = "gpk2-2"; 615 samsung,pins = "gpk2-2";
343 samsung,pin-function = <2>; 616 samsung,pin-function = <2>;
344 samsung,pin-pud = <3>; 617 samsung,pin-pud = <3>;
345 samsung,pin-drv = <0>; 618 samsung,pin-drv = <3>;
346 }; 619 };
347 620
348 sd2_bus1: sd2-bus-width1 { 621 sd2_bus1: sd2-bus-width1 {
349 samsung,pins = "gpk2-3"; 622 samsung,pins = "gpk2-3";
350 samsung,pin-function = <2>; 623 samsung,pin-function = <2>;
351 samsung,pin-pud = <3>; 624 samsung,pin-pud = <3>;
352 samsung,pin-drv = <0>; 625 samsung,pin-drv = <3>;
353 }; 626 };
354 627
355 sd2_bus4: sd2-bus-width4 { 628 sd2_bus4: sd2-bus-width4 {
356 samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; 629 samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6";
357 samsung,pin-function = <2>; 630 samsung,pin-function = <2>;
358 samsung,pin-pud = <3>; 631 samsung,pin-pud = <3>;
359 samsung,pin-drv = <0>; 632 samsung,pin-drv = <3>;
360 }; 633 };
361 634
362 sd2_bus8: sd2-bus-width8 { 635 sd2_bus8: sd2-bus-width8 {
363 samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; 636 samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
364 samsung,pin-function = <3>; 637 samsung,pin-function = <3>;
365 samsung,pin-pud = <3>; 638 samsung,pin-pud = <3>;
366 samsung,pin-drv = <0>; 639 samsung,pin-drv = <3>;
367 }; 640 };
368 641
369 sd3_clk: sd3-clk { 642 sd3_clk: sd3-clk {
370 samsung,pins = "gpk3-0"; 643 samsung,pins = "gpk3-0";
371 samsung,pin-function = <2>; 644 samsung,pin-function = <2>;
372 samsung,pin-pud = <0>; 645 samsung,pin-pud = <0>;
373 samsung,pin-drv = <0>; 646 samsung,pin-drv = <3>;
374 }; 647 };
375 648
376 sd3_cmd: sd3-cmd { 649 sd3_cmd: sd3-cmd {
377 samsung,pins = "gpk3-1"; 650 samsung,pins = "gpk3-1";
378 samsung,pin-function = <2>; 651 samsung,pin-function = <2>;
379 samsung,pin-pud = <0>; 652 samsung,pin-pud = <0>;
380 samsung,pin-drv = <0>; 653 samsung,pin-drv = <3>;
381 }; 654 };
382 655
383 sd3_cd: sd3-cd { 656 sd3_cd: sd3-cd {
384 samsung,pins = "gpk3-2"; 657 samsung,pins = "gpk3-2";
385 samsung,pin-function = <2>; 658 samsung,pin-function = <2>;
386 samsung,pin-pud = <3>; 659 samsung,pin-pud = <3>;
387 samsung,pin-drv = <0>; 660 samsung,pin-drv = <3>;
388 }; 661 };
389 662
390 sd3_bus1: sd3-bus-width1 { 663 sd3_bus1: sd3-bus-width1 {
391 samsung,pins = "gpk3-3"; 664 samsung,pins = "gpk3-3";
392 samsung,pin-function = <2>; 665 samsung,pin-function = <2>;
393 samsung,pin-pud = <3>; 666 samsung,pin-pud = <3>;
394 samsung,pin-drv = <0>; 667 samsung,pin-drv = <3>;
395 }; 668 };
396 669
397 sd3_bus4: sd3-bus-width4 { 670 sd3_bus4: sd3-bus-width4 {
398 samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; 671 samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
399 samsung,pin-function = <2>; 672 samsung,pin-function = <2>;
400 samsung,pin-pud = <3>; 673 samsung,pin-pud = <3>;
401 samsung,pin-drv = <0>; 674 samsung,pin-drv = <3>;
402 }; 675 };
403 676
404 eint0: ext-int0 { 677 eint0: ext-int0 {
@@ -438,6 +711,11 @@
438 }; 711 };
439 712
440 pinctrl@03860000 { 713 pinctrl@03860000 {
714 gpz: gpz {
715 gpio-controller;
716 #gpio-cells = <2>;
717 };
718
441 i2s0_bus: i2s0-bus { 719 i2s0_bus: i2s0-bus {
442 samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", 720 samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
443 "gpz-4", "gpz-5", "gpz-6"; 721 "gpz-4", "gpz-5", "gpz-6";
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 63610c3ba3af..f63490707f3a 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -26,7 +26,7 @@
26 }; 26 };
27 27
28 chosen { 28 chosen {
29 bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; 29 bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
30 }; 30 };
31 31
32 sdhci@12530000 { 32 sdhci@12530000 {
@@ -43,6 +43,22 @@
43 status = "okay"; 43 status = "okay";
44 }; 44 };
45 45
46 serial@13800000 {
47 status = "okay";
48 };
49
50 serial@13810000 {
51 status = "okay";
52 };
53
54 serial@13820000 {
55 status = "okay";
56 };
57
58 serial@13830000 {
59 status = "okay";
60 };
61
46 keypad@100A0000 { 62 keypad@100A0000 {
47 samsung,keypad-num-rows = <2>; 63 samsung,keypad-num-rows = <2>;
48 samsung,keypad-num-columns = <8>; 64 samsung,keypad-num-columns = <8>;
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index a21511c14071..c346b64dff55 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -35,24 +35,15 @@
35 regulator-name = "VMEM_VDD_2.8V"; 35 regulator-name = "VMEM_VDD_2.8V";
36 regulator-min-microvolt = <2800000>; 36 regulator-min-microvolt = <2800000>;
37 regulator-max-microvolt = <2800000>; 37 regulator-max-microvolt = <2800000>;
38 gpio = <&gpk0 2 1 0 0>; 38 gpio = <&gpk0 2 0>;
39 enable-active-high; 39 enable-active-high;
40 }; 40 };
41 41
42 sdhci_emmc: sdhci@12510000 { 42 sdhci_emmc: sdhci@12510000 {
43 bus-width = <8>; 43 bus-width = <8>;
44 non-removable; 44 non-removable;
45 broken-voltage; 45 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>;
46 gpios = <&gpk0 0 2 0 3>, 46 pinctrl-names = "default";
47 <&gpk0 1 2 0 3>,
48 <&gpk0 3 2 2 3>,
49 <&gpk0 4 2 2 3>,
50 <&gpk0 5 2 2 3>,
51 <&gpk0 6 2 2 3>,
52 <&gpk1 3 3 3 3>,
53 <&gpk1 4 3 3 3>,
54 <&gpk1 5 3 3 3>,
55 <&gpk1 6 3 3 3>;
56 vmmc-supply = <&vemmc_reg>; 47 vmmc-supply = <&vemmc_reg>;
57 status = "okay"; 48 status = "okay";
58 }; 49 };
@@ -73,12 +64,74 @@
73 status = "okay"; 64 status = "okay";
74 }; 65 };
75 66
67 gpio-keys {
68 compatible = "gpio-keys";
69
70 vol-down-key {
71 gpios = <&gpx2 1 1>;
72 linux,code = <114>;
73 label = "volume down";
74 debounce-interval = <10>;
75 };
76
77 vol-up-key {
78 gpios = <&gpx2 0 1>;
79 linux,code = <115>;
80 label = "volume up";
81 debounce-interval = <10>;
82 };
83
84 power-key {
85 gpios = <&gpx2 7 1>;
86 linux,code = <116>;
87 label = "power";
88 debounce-interval = <10>;
89 gpio-key,wakeup;
90 };
91
92 ok-key {
93 gpios = <&gpx3 5 1>;
94 linux,code = <352>;
95 label = "ok";
96 debounce-interval = <10>;
97 };
98 };
99
100 tsp_reg: voltage-regulator {
101 compatible = "regulator-fixed";
102 regulator-name = "TSP_FIXED_VOLTAGES";
103 regulator-min-microvolt = <2800000>;
104 regulator-max-microvolt = <2800000>;
105 gpio = <&gpl0 3 0>;
106 enable-active-high;
107 };
108
109 i2c@13890000 {
110 samsung,i2c-sda-delay = <100>;
111 samsung,i2c-slave-addr = <0x10>;
112 samsung,i2c-max-bus-freq = <400000>;
113 pinctrl-0 = <&i2c3_bus>;
114 pinctrl-names = "default";
115 status = "okay";
116
117 mms114-touchscreen@48 {
118 compatible = "melfas,mms114";
119 reg = <0x48>;
120 interrupt-parent = <&gpx0>;
121 interrupts = <4 2>;
122 x-size = <720>;
123 y-size = <1280>;
124 avdd-supply = <&tsp_reg>;
125 vdd-supply = <&tsp_reg>;
126 };
127 };
128
76 i2c@138B0000 { 129 i2c@138B0000 {
77 samsung,i2c-sda-delay = <100>; 130 samsung,i2c-sda-delay = <100>;
78 samsung,i2c-slave-addr = <0x10>; 131 samsung,i2c-slave-addr = <0x10>;
79 samsung,i2c-max-bus-freq = <100000>; 132 samsung,i2c-max-bus-freq = <100000>;
80 gpios = <&gpb 6 3 3 0>, 133 pinctrl-0 = <&i2c5_bus>;
81 <&gpb 7 3 3 0>; 134 pinctrl-names = "default";
82 status = "okay"; 135 status = "okay";
83 136
84 max8997_pmic@66 { 137 max8997_pmic@66 {
@@ -93,9 +146,9 @@
93 max8997,pmic-ignore-gpiodvs-side-effect; 146 max8997,pmic-ignore-gpiodvs-side-effect;
94 max8997,pmic-buck125-default-dvs-idx = <0>; 147 max8997,pmic-buck125-default-dvs-idx = <0>;
95 148
96 max8997,pmic-buck125-dvs-gpios = <&gpx0 5 1 0 0>, 149 max8997,pmic-buck125-dvs-gpios = <&gpx0 5 0>,
97 <&gpx0 6 1 0 0>, 150 <&gpx0 6 0>,
98 <&gpl0 0 1 0 0>; 151 <&gpl0 0 0>;
99 152
100 max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>, 153 max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>,
101 <1250000>, <1200000>, 154 <1250000>, <1200000>,
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 214c557eda7f..e31bfc4a6f09 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -31,6 +31,11 @@
31 pinctrl2 = &pinctrl_2; 31 pinctrl2 = &pinctrl_2;
32 }; 32 };
33 33
34 pd_lcd1: lcd1-power-domain@10023CA0 {
35 compatible = "samsung,exynos4210-pd";
36 reg = <0x10023CA0 0x20>;
37 };
38
34 gic:interrupt-controller@10490000 { 39 gic:interrupt-controller@10490000 {
35 cpu-offset = <0x8000>; 40 cpu-offset = <0x8000>;
36 }; 41 };
@@ -46,27 +51,17 @@
46 compatible = "samsung,pinctrl-exynos4210"; 51 compatible = "samsung,pinctrl-exynos4210";
47 reg = <0x11400000 0x1000>; 52 reg = <0x11400000 0x1000>;
48 interrupts = <0 47 0>; 53 interrupts = <0 47 0>;
49 interrupt-controller;
50 #interrupt-cells = <2>;
51 }; 54 };
52 55
53 pinctrl_1: pinctrl@11000000 { 56 pinctrl_1: pinctrl@11000000 {
54 compatible = "samsung,pinctrl-exynos4210"; 57 compatible = "samsung,pinctrl-exynos4210";
55 reg = <0x11000000 0x1000>; 58 reg = <0x11000000 0x1000>;
56 interrupts = <0 46 0>; 59 interrupts = <0 46 0>;
57 interrupt-controller;
58 #interrupt-cells = <2>;
59 60
60 wakup_eint: wakeup-interrupt-controller { 61 wakup_eint: wakeup-interrupt-controller {
61 compatible = "samsung,exynos4210-wakeup-eint"; 62 compatible = "samsung,exynos4210-wakeup-eint";
62 interrupt-parent = <&gic>; 63 interrupt-parent = <&gic>;
63 interrupt-controller; 64 interrupts = <0 32 0>;
64 #interrupt-cells = <2>;
65 interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
66 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
67 <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
68 <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>,
69 <0 32 0>;
70 }; 65 };
71 }; 66 };
72 67
@@ -75,232 +70,10 @@
75 reg = <0x03860000 0x1000>; 70 reg = <0x03860000 0x1000>;
76 }; 71 };
77 72
78 gpio-controllers { 73 tmu@100C0000 {
79 #address-cells = <1>; 74 compatible = "samsung,exynos4210-tmu";
80 #size-cells = <1>; 75 interrupt-parent = <&combiner>;
81 gpio-controller; 76 reg = <0x100C0000 0x100>;
82 ranges; 77 interrupts = <2 4>;
83
84 gpa0: gpio-controller@11400000 {
85 compatible = "samsung,exynos4-gpio";
86 reg = <0x11400000 0x20>;
87 #gpio-cells = <4>;
88 };
89
90 gpa1: gpio-controller@11400020 {
91 compatible = "samsung,exynos4-gpio";
92 reg = <0x11400020 0x20>;
93 #gpio-cells = <4>;
94 };
95
96 gpb: gpio-controller@11400040 {
97 compatible = "samsung,exynos4-gpio";
98 reg = <0x11400040 0x20>;
99 #gpio-cells = <4>;
100 };
101
102 gpc0: gpio-controller@11400060 {
103 compatible = "samsung,exynos4-gpio";
104 reg = <0x11400060 0x20>;
105 #gpio-cells = <4>;
106 };
107
108 gpc1: gpio-controller@11400080 {
109 compatible = "samsung,exynos4-gpio";
110 reg = <0x11400080 0x20>;
111 #gpio-cells = <4>;
112 };
113
114 gpd0: gpio-controller@114000A0 {
115 compatible = "samsung,exynos4-gpio";
116 reg = <0x114000A0 0x20>;
117 #gpio-cells = <4>;
118 };
119
120 gpd1: gpio-controller@114000C0 {
121 compatible = "samsung,exynos4-gpio";
122 reg = <0x114000C0 0x20>;
123 #gpio-cells = <4>;
124 };
125
126 gpe0: gpio-controller@114000E0 {
127 compatible = "samsung,exynos4-gpio";
128 reg = <0x114000E0 0x20>;
129 #gpio-cells = <4>;
130 };
131
132 gpe1: gpio-controller@11400100 {
133 compatible = "samsung,exynos4-gpio";
134 reg = <0x11400100 0x20>;
135 #gpio-cells = <4>;
136 };
137
138 gpe2: gpio-controller@11400120 {
139 compatible = "samsung,exynos4-gpio";
140 reg = <0x11400120 0x20>;
141 #gpio-cells = <4>;
142 };
143
144 gpe3: gpio-controller@11400140 {
145 compatible = "samsung,exynos4-gpio";
146 reg = <0x11400140 0x20>;
147 #gpio-cells = <4>;
148 };
149
150 gpe4: gpio-controller@11400160 {
151 compatible = "samsung,exynos4-gpio";
152 reg = <0x11400160 0x20>;
153 #gpio-cells = <4>;
154 };
155
156 gpf0: gpio-controller@11400180 {
157 compatible = "samsung,exynos4-gpio";
158 reg = <0x11400180 0x20>;
159 #gpio-cells = <4>;
160 };
161
162 gpf1: gpio-controller@114001A0 {
163 compatible = "samsung,exynos4-gpio";
164 reg = <0x114001A0 0x20>;
165 #gpio-cells = <4>;
166 };
167
168 gpf2: gpio-controller@114001C0 {
169 compatible = "samsung,exynos4-gpio";
170 reg = <0x114001C0 0x20>;
171 #gpio-cells = <4>;
172 };
173
174 gpf3: gpio-controller@114001E0 {
175 compatible = "samsung,exynos4-gpio";
176 reg = <0x114001E0 0x20>;
177 #gpio-cells = <4>;
178 };
179
180 gpj0: gpio-controller@11000000 {
181 compatible = "samsung,exynos4-gpio";
182 reg = <0x11000000 0x20>;
183 #gpio-cells = <4>;
184 };
185
186 gpj1: gpio-controller@11000020 {
187 compatible = "samsung,exynos4-gpio";
188 reg = <0x11000020 0x20>;
189 #gpio-cells = <4>;
190 };
191
192 gpk0: gpio-controller@11000040 {
193 compatible = "samsung,exynos4-gpio";
194 reg = <0x11000040 0x20>;
195 #gpio-cells = <4>;
196 };
197
198 gpk1: gpio-controller@11000060 {
199 compatible = "samsung,exynos4-gpio";
200 reg = <0x11000060 0x20>;
201 #gpio-cells = <4>;
202 };
203
204 gpk2: gpio-controller@11000080 {
205 compatible = "samsung,exynos4-gpio";
206 reg = <0x11000080 0x20>;
207 #gpio-cells = <4>;
208 };
209
210 gpk3: gpio-controller@110000A0 {
211 compatible = "samsung,exynos4-gpio";
212 reg = <0x110000A0 0x20>;
213 #gpio-cells = <4>;
214 };
215
216 gpl0: gpio-controller@110000C0 {
217 compatible = "samsung,exynos4-gpio";
218 reg = <0x110000C0 0x20>;
219 #gpio-cells = <4>;
220 };
221
222 gpl1: gpio-controller@110000E0 {
223 compatible = "samsung,exynos4-gpio";
224 reg = <0x110000E0 0x20>;
225 #gpio-cells = <4>;
226 };
227
228 gpl2: gpio-controller@11000100 {
229 compatible = "samsung,exynos4-gpio";
230 reg = <0x11000100 0x20>;
231 #gpio-cells = <4>;
232 };
233
234 gpy0: gpio-controller@11000120 {
235 compatible = "samsung,exynos4-gpio";
236 reg = <0x11000120 0x20>;
237 #gpio-cells = <4>;
238 };
239
240 gpy1: gpio-controller@11000140 {
241 compatible = "samsung,exynos4-gpio";
242 reg = <0x11000140 0x20>;
243 #gpio-cells = <4>;
244 };
245
246 gpy2: gpio-controller@11000160 {
247 compatible = "samsung,exynos4-gpio";
248 reg = <0x11000160 0x20>;
249 #gpio-cells = <4>;
250 };
251
252 gpy3: gpio-controller@11000180 {
253 compatible = "samsung,exynos4-gpio";
254 reg = <0x11000180 0x20>;
255 #gpio-cells = <4>;
256 };
257
258 gpy4: gpio-controller@110001A0 {
259 compatible = "samsung,exynos4-gpio";
260 reg = <0x110001A0 0x20>;
261 #gpio-cells = <4>;
262 };
263
264 gpy5: gpio-controller@110001C0 {
265 compatible = "samsung,exynos4-gpio";
266 reg = <0x110001C0 0x20>;
267 #gpio-cells = <4>;
268 };
269
270 gpy6: gpio-controller@110001E0 {
271 compatible = "samsung,exynos4-gpio";
272 reg = <0x110001E0 0x20>;
273 #gpio-cells = <4>;
274 };
275
276 gpx0: gpio-controller@11000C00 {
277 compatible = "samsung,exynos4-gpio";
278 reg = <0x11000C00 0x20>;
279 #gpio-cells = <4>;
280 };
281
282 gpx1: gpio-controller@11000C20 {
283 compatible = "samsung,exynos4-gpio";
284 reg = <0x11000C20 0x20>;
285 #gpio-cells = <4>;
286 };
287
288 gpx2: gpio-controller@11000C40 {
289 compatible = "samsung,exynos4-gpio";
290 reg = <0x11000C40 0x20>;
291 #gpio-cells = <4>;
292 };
293
294 gpx3: gpio-controller@11000C60 {
295 compatible = "samsung,exynos4-gpio";
296 reg = <0x11000C60 0x20>;
297 #gpio-cells = <4>;
298 };
299
300 gpz: gpio-controller@03860000 {
301 compatible = "samsung,exynos4-gpio";
302 reg = <0x03860000 0x20>;
303 #gpio-cells = <4>;
304 };
305 }; 78 };
306}; 79};
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
new file mode 100644
index 000000000000..c6ae2005961f
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -0,0 +1,28 @@
1/*
2 * Samsung's Exynos4212 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos4212 SoC device nodes are listed in this file. Exynos4212
8 * based board files can include this file and provide values for board specfic
9 * bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos4212 SoC. As device tree coverage for Exynos4212 increases, additional
13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
20/include/ "exynos4x12.dtsi"
21
22/ {
23 compatible = "samsung,exynos4212";
24
25 gic:interrupt-controller@10490000 {
26 cpu-offset = <0x8000>;
27 };
28};
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
new file mode 100644
index 000000000000..f05bf575cc45
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -0,0 +1,45 @@
1/*
2 * Samsung's Exynos4412 based SMDK board device tree source
3 *
4 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Device tree source file for Samsung's SMDK4412 board which is based on
8 * Samsung's Exynos4412 SoC.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/dts-v1/;
16/include/ "exynos4412.dtsi"
17
18/ {
19 model = "Samsung SMDK evaluation board based on Exynos4412";
20 compatible = "samsung,smdk4412", "samsung,exynos4412";
21
22 memory {
23 reg = <0x40000000 0x40000000>;
24 };
25
26 chosen {
27 bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
28 };
29
30 serial@13800000 {
31 status = "okay";
32 };
33
34 serial@13810000 {
35 status = "okay";
36 };
37
38 serial@13820000 {
39 status = "okay";
40 };
41
42 serial@13830000 {
43 status = "okay";
44 };
45};
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
new file mode 100644
index 000000000000..d7dfe312772a
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -0,0 +1,28 @@
1/*
2 * Samsung's Exynos4412 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412
8 * based board files can include this file and provide values for board specfic
9 * bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional
13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
20/include/ "exynos4x12.dtsi"
21
22/ {
23 compatible = "samsung,exynos4412";
24
25 gic:interrupt-controller@10490000 {
26 cpu-offset = <0x4000>;
27 };
28};
diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
new file mode 100644
index 000000000000..8e6115adcd97
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
@@ -0,0 +1,965 @@
1/*
2 * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos4x12 SoCs pin-mux and pin-config optiosn are listed as device
8 * tree nodes are listed in this file.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/ {
16 pinctrl@11400000 {
17 gpa0: gpa0 {
18 gpio-controller;
19 #gpio-cells = <2>;
20
21 interrupt-controller;
22 #interrupt-cells = <2>;
23 };
24
25 gpa1: gpa1 {
26 gpio-controller;
27 #gpio-cells = <2>;
28
29 interrupt-controller;
30 #interrupt-cells = <2>;
31 };
32
33 gpb: gpb {
34 gpio-controller;
35 #gpio-cells = <2>;
36
37 interrupt-controller;
38 #interrupt-cells = <2>;
39 };
40
41 gpc0: gpc0 {
42 gpio-controller;
43 #gpio-cells = <2>;
44
45 interrupt-controller;
46 #interrupt-cells = <2>;
47 };
48
49 gpc1: gpc1 {
50 gpio-controller;
51 #gpio-cells = <2>;
52
53 interrupt-controller;
54 #interrupt-cells = <2>;
55 };
56
57 gpd0: gpd0 {
58 gpio-controller;
59 #gpio-cells = <2>;
60
61 interrupt-controller;
62 #interrupt-cells = <2>;
63 };
64
65 gpd1: gpd1 {
66 gpio-controller;
67 #gpio-cells = <2>;
68
69 interrupt-controller;
70 #interrupt-cells = <2>;
71 };
72
73 gpf0: gpf0 {
74 gpio-controller;
75 #gpio-cells = <2>;
76
77 interrupt-controller;
78 #interrupt-cells = <2>;
79 };
80
81 gpf1: gpf1 {
82 gpio-controller;
83 #gpio-cells = <2>;
84
85 interrupt-controller;
86 #interrupt-cells = <2>;
87 };
88
89 gpf2: gpf2 {
90 gpio-controller;
91 #gpio-cells = <2>;
92
93 interrupt-controller;
94 #interrupt-cells = <2>;
95 };
96
97 gpf3: gpf3 {
98 gpio-controller;
99 #gpio-cells = <2>;
100
101 interrupt-controller;
102 #interrupt-cells = <2>;
103 };
104
105 gpj0: gpj0 {
106 gpio-controller;
107 #gpio-cells = <2>;
108
109 interrupt-controller;
110 #interrupt-cells = <2>;
111 };
112
113 gpj1: gpj1 {
114 gpio-controller;
115 #gpio-cells = <2>;
116
117 interrupt-controller;
118 #interrupt-cells = <2>;
119 };
120
121 uart0_data: uart0-data {
122 samsung,pins = "gpa0-0", "gpa0-1";
123 samsung,pin-function = <0x2>;
124 samsung,pin-pud = <0>;
125 samsung,pin-drv = <0>;
126 };
127
128 uart0_fctl: uart0-fctl {
129 samsung,pins = "gpa0-2", "gpa0-3";
130 samsung,pin-function = <2>;
131 samsung,pin-pud = <0>;
132 samsung,pin-drv = <0>;
133 };
134
135 uart1_data: uart1-data {
136 samsung,pins = "gpa0-4", "gpa0-5";
137 samsung,pin-function = <2>;
138 samsung,pin-pud = <0>;
139 samsung,pin-drv = <0>;
140 };
141
142 uart1_fctl: uart1-fctl {
143 samsung,pins = "gpa0-6", "gpa0-7";
144 samsung,pin-function = <2>;
145 samsung,pin-pud = <0>;
146 samsung,pin-drv = <0>;
147 };
148
149 i2c2_bus: i2c2-bus {
150 samsung,pins = "gpa0-6", "gpa0-7";
151 samsung,pin-function = <3>;
152 samsung,pin-pud = <3>;
153 samsung,pin-drv = <0>;
154 };
155
156 uart2_data: uart2-data {
157 samsung,pins = "gpa1-0", "gpa1-1";
158 samsung,pin-function = <2>;
159 samsung,pin-pud = <0>;
160 samsung,pin-drv = <0>;
161 };
162
163 uart2_fctl: uart2-fctl {
164 samsung,pins = "gpa1-2", "gpa1-3";
165 samsung,pin-function = <2>;
166 samsung,pin-pud = <0>;
167 samsung,pin-drv = <0>;
168 };
169
170 uart_audio_a: uart-audio-a {
171 samsung,pins = "gpa1-0", "gpa1-1";
172 samsung,pin-function = <4>;
173 samsung,pin-pud = <0>;
174 samsung,pin-drv = <0>;
175 };
176
177 i2c3_bus: i2c3-bus {
178 samsung,pins = "gpa1-2", "gpa1-3";
179 samsung,pin-function = <3>;
180 samsung,pin-pud = <3>;
181 samsung,pin-drv = <0>;
182 };
183
184 uart3_data: uart3-data {
185 samsung,pins = "gpa1-4", "gpa1-5";
186 samsung,pin-function = <2>;
187 samsung,pin-pud = <0>;
188 samsung,pin-drv = <0>;
189 };
190
191 uart_audio_b: uart-audio-b {
192 samsung,pins = "gpa1-4", "gpa1-5";
193 samsung,pin-function = <4>;
194 samsung,pin-pud = <0>;
195 samsung,pin-drv = <0>;
196 };
197
198 spi0_bus: spi0-bus {
199 samsung,pins = "gpb-0", "gpb-2", "gpb-3";
200 samsung,pin-function = <2>;
201 samsung,pin-pud = <3>;
202 samsung,pin-drv = <0>;
203 };
204
205 i2c4_bus: i2c4-bus {
206 samsung,pins = "gpb-0", "gpb-1";
207 samsung,pin-function = <3>;
208 samsung,pin-pud = <3>;
209 samsung,pin-drv = <0>;
210 };
211
212 spi1_bus: spi1-bus {
213 samsung,pins = "gpb-4", "gpb-6", "gpb-7";
214 samsung,pin-function = <2>;
215 samsung,pin-pud = <3>;
216 samsung,pin-drv = <0>;
217 };
218
219 i2c5_bus: i2c5-bus {
220 samsung,pins = "gpb-2", "gpb-3";
221 samsung,pin-function = <3>;
222 samsung,pin-pud = <3>;
223 samsung,pin-drv = <0>;
224 };
225
226 i2s1_bus: i2s1-bus {
227 samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
228 "gpc0-4";
229 samsung,pin-function = <2>;
230 samsung,pin-pud = <0>;
231 samsung,pin-drv = <0>;
232 };
233
234 pcm1_bus: pcm1-bus {
235 samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
236 "gpc0-4";
237 samsung,pin-function = <3>;
238 samsung,pin-pud = <0>;
239 samsung,pin-drv = <0>;
240 };
241
242 ac97_bus: ac97-bus {
243 samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
244 "gpc0-4";
245 samsung,pin-function = <4>;
246 samsung,pin-pud = <0>;
247 samsung,pin-drv = <0>;
248 };
249
250 i2s2_bus: i2s2-bus {
251 samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
252 "gpc1-4";
253 samsung,pin-function = <2>;
254 samsung,pin-pud = <0>;
255 samsung,pin-drv = <0>;
256 };
257
258 pcm2_bus: pcm2-bus {
259 samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
260 "gpc1-4";
261 samsung,pin-function = <3>;
262 samsung,pin-pud = <0>;
263 samsung,pin-drv = <0>;
264 };
265
266 spdif_bus: spdif-bus {
267 samsung,pins = "gpc1-0", "gpc1-1";
268 samsung,pin-function = <4>;
269 samsung,pin-pud = <0>;
270 samsung,pin-drv = <0>;
271 };
272
273 i2c6_bus: i2c6-bus {
274 samsung,pins = "gpc1-3", "gpc1-4";
275 samsung,pin-function = <4>;
276 samsung,pin-pud = <3>;
277 samsung,pin-drv = <0>;
278 };
279
280 spi2_bus: spi2-bus {
281 samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4";
282 samsung,pin-function = <5>;
283 samsung,pin-pud = <3>;
284 samsung,pin-drv = <0>;
285 };
286
287 pwm0_out: pwm0-out {
288 samsung,pins = "gpd0-0";
289 samsung,pin-function = <2>;
290 samsung,pin-pud = <0>;
291 samsung,pin-drv = <0>;
292 };
293
294 pwm1_out: pwm1-out {
295 samsung,pins = "gpd0-1";
296 samsung,pin-function = <2>;
297 samsung,pin-pud = <0>;
298 samsung,pin-drv = <0>;
299 };
300
301 lcd_ctrl: lcd-ctrl {
302 samsung,pins = "gpd0-0", "gpd0-1";
303 samsung,pin-function = <3>;
304 samsung,pin-pud = <0>;
305 samsung,pin-drv = <0>;
306 };
307
308 i2c7_bus: i2c7-bus {
309 samsung,pins = "gpd0-2", "gpd0-3";
310 samsung,pin-function = <3>;
311 samsung,pin-pud = <3>;
312 samsung,pin-drv = <0>;
313 };
314
315 pwm2_out: pwm2-out {
316 samsung,pins = "gpd0-2";
317 samsung,pin-function = <2>;
318 samsung,pin-pud = <0>;
319 samsung,pin-drv = <0>;
320 };
321
322 pwm3_out: pwm3-out {
323 samsung,pins = "gpd0-3";
324 samsung,pin-function = <2>;
325 samsung,pin-pud = <0>;
326 samsung,pin-drv = <0>;
327 };
328
329 i2c0_bus: i2c0-bus {
330 samsung,pins = "gpd1-0", "gpd1-1";
331 samsung,pin-function = <2>;
332 samsung,pin-pud = <3>;
333 samsung,pin-drv = <0>;
334 };
335
336 mipi0_clk: mipi0-clk {
337 samsung,pins = "gpd1-0", "gpd1-1";
338 samsung,pin-function = <3>;
339 samsung,pin-pud = <0>;
340 samsung,pin-drv = <0>;
341 };
342
343 i2c1_bus: i2c1-bus {
344 samsung,pins = "gpd1-2", "gpd1-3";
345 samsung,pin-function = <2>;
346 samsung,pin-pud = <3>;
347 samsung,pin-drv = <0>;
348 };
349
350 mipi1_clk: mipi1-clk {
351 samsung,pins = "gpd1-2", "gpd1-3";
352 samsung,pin-function = <3>;
353 samsung,pin-pud = <0>;
354 samsung,pin-drv = <0>;
355 };
356
357 lcd_clk: lcd-clk {
358 samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3";
359 samsung,pin-function = <2>;
360 samsung,pin-pud = <0>;
361 samsung,pin-drv = <0>;
362 };
363
364 lcd_data16: lcd-data-width16 {
365 samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2",
366 "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0",
367 "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7",
368 "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
369 samsung,pin-function = <2>;
370 samsung,pin-pud = <0>;
371 samsung,pin-drv = <0>;
372 };
373
374 lcd_data18: lcd-data-width18 {
375 samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1",
376 "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7",
377 "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
378 "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1",
379 "gpf3-2", "gpf3-3";
380 samsung,pin-function = <2>;
381 samsung,pin-pud = <0>;
382 samsung,pin-drv = <0>;
383 };
384
385 lcd_data24: lcd-data-width24 {
386 samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7",
387 "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3",
388 "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7",
389 "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
390 "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7",
391 "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
392 samsung,pin-function = <2>;
393 samsung,pin-pud = <0>;
394 samsung,pin-drv = <0>;
395 };
396
397 lcd_ldi: lcd-ldi {
398 samsung,pins = "gpf3-4";
399 samsung,pin-function = <2>;
400 samsung,pin-pud = <0>;
401 samsung,pin-drv = <0>;
402 };
403
404 cam_port_a: cam-port-a {
405 samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3",
406 "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7",
407 "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-3",
408 "gpj1-4";
409 samsung,pin-function = <2>;
410 samsung,pin-pud = <3>;
411 samsung,pin-drv = <0>;
412 };
413 };
414
415 pinctrl@11000000 {
416 gpk0: gpk0 {
417 gpio-controller;
418 #gpio-cells = <2>;
419
420 interrupt-controller;
421 #interrupt-cells = <2>;
422 };
423
424 gpk1: gpk1 {
425 gpio-controller;
426 #gpio-cells = <2>;
427
428 interrupt-controller;
429 #interrupt-cells = <2>;
430 };
431
432 gpk2: gpk2 {
433 gpio-controller;
434 #gpio-cells = <2>;
435
436 interrupt-controller;
437 #interrupt-cells = <2>;
438 };
439
440 gpk3: gpk3 {
441 gpio-controller;
442 #gpio-cells = <2>;
443
444 interrupt-controller;
445 #interrupt-cells = <2>;
446 };
447
448 gpl0: gpl0 {
449 gpio-controller;
450 #gpio-cells = <2>;
451
452 interrupt-controller;
453 #interrupt-cells = <2>;
454 };
455
456 gpl1: gpl1 {
457 gpio-controller;
458 #gpio-cells = <2>;
459
460 interrupt-controller;
461 #interrupt-cells = <2>;
462 };
463
464 gpl2: gpl2 {
465 gpio-controller;
466 #gpio-cells = <2>;
467
468 interrupt-controller;
469 #interrupt-cells = <2>;
470 };
471
472 gpm0: gpm0 {
473 gpio-controller;
474 #gpio-cells = <2>;
475
476 interrupt-controller;
477 #interrupt-cells = <2>;
478 };
479
480 gpm1: gpm1 {
481 gpio-controller;
482 #gpio-cells = <2>;
483
484 interrupt-controller;
485 #interrupt-cells = <2>;
486 };
487
488 gpm2: gpm2 {
489 gpio-controller;
490 #gpio-cells = <2>;
491
492 interrupt-controller;
493 #interrupt-cells = <2>;
494 };
495
496 gpm3: gpm3 {
497 gpio-controller;
498 #gpio-cells = <2>;
499
500 interrupt-controller;
501 #interrupt-cells = <2>;
502 };
503
504 gpm4: gpm4 {
505 gpio-controller;
506 #gpio-cells = <2>;
507
508 interrupt-controller;
509 #interrupt-cells = <2>;
510 };
511
512 gpy0: gpy0 {
513 gpio-controller;
514 #gpio-cells = <2>;
515 };
516
517 gpy1: gpy1 {
518 gpio-controller;
519 #gpio-cells = <2>;
520 };
521
522 gpy2: gpy2 {
523 gpio-controller;
524 #gpio-cells = <2>;
525 };
526
527 gpy3: gpy3 {
528 gpio-controller;
529 #gpio-cells = <2>;
530 };
531
532 gpy4: gpy4 {
533 gpio-controller;
534 #gpio-cells = <2>;
535 };
536
537 gpy5: gpy5 {
538 gpio-controller;
539 #gpio-cells = <2>;
540 };
541
542 gpy6: gpy6 {
543 gpio-controller;
544 #gpio-cells = <2>;
545 };
546
547 gpx0: gpx0 {
548 gpio-controller;
549 #gpio-cells = <2>;
550
551 interrupt-controller;
552 interrupt-parent = <&gic>;
553 interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
554 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
555 #interrupt-cells = <2>;
556 };
557
558 gpx1: gpx1 {
559 gpio-controller;
560 #gpio-cells = <2>;
561
562 interrupt-controller;
563 interrupt-parent = <&gic>;
564 interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
565 <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
566 #interrupt-cells = <2>;
567 };
568
569 gpx2: gpx2 {
570 gpio-controller;
571 #gpio-cells = <2>;
572
573 interrupt-controller;
574 #interrupt-cells = <2>;
575 };
576
577 gpx3: gpx3 {
578 gpio-controller;
579 #gpio-cells = <2>;
580
581 interrupt-controller;
582 #interrupt-cells = <2>;
583 };
584
585 sd0_clk: sd0-clk {
586 samsung,pins = "gpk0-0";
587 samsung,pin-function = <2>;
588 samsung,pin-pud = <0>;
589 samsung,pin-drv = <3>;
590 };
591
592 sd0_cmd: sd0-cmd {
593 samsung,pins = "gpk0-1";
594 samsung,pin-function = <2>;
595 samsung,pin-pud = <0>;
596 samsung,pin-drv = <3>;
597 };
598
599 sd0_cd: sd0-cd {
600 samsung,pins = "gpk0-2";
601 samsung,pin-function = <2>;
602 samsung,pin-pud = <3>;
603 samsung,pin-drv = <3>;
604 };
605
606 sd0_bus1: sd0-bus-width1 {
607 samsung,pins = "gpk0-3";
608 samsung,pin-function = <2>;
609 samsung,pin-pud = <3>;
610 samsung,pin-drv = <3>;
611 };
612
613 sd0_bus4: sd0-bus-width4 {
614 samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
615 samsung,pin-function = <2>;
616 samsung,pin-pud = <3>;
617 samsung,pin-drv = <3>;
618 };
619
620 sd0_bus8: sd0-bus-width8 {
621 samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
622 samsung,pin-function = <3>;
623 samsung,pin-pud = <3>;
624 samsung,pin-drv = <3>;
625 };
626
627 sd4_clk: sd4-clk {
628 samsung,pins = "gpk0-0";
629 samsung,pin-function = <3>;
630 samsung,pin-pud = <0>;
631 samsung,pin-drv = <3>;
632 };
633
634 sd4_cmd: sd4-cmd {
635 samsung,pins = "gpk0-1";
636 samsung,pin-function = <3>;
637 samsung,pin-pud = <0>;
638 samsung,pin-drv = <3>;
639 };
640
641 sd4_cd: sd4-cd {
642 samsung,pins = "gpk0-2";
643 samsung,pin-function = <3>;
644 samsung,pin-pud = <3>;
645 samsung,pin-drv = <3>;
646 };
647
648 sd4_bus1: sd4-bus-width1 {
649 samsung,pins = "gpk0-3";
650 samsung,pin-function = <3>;
651 samsung,pin-pud = <3>;
652 samsung,pin-drv = <3>;
653 };
654
655 sd4_bus4: sd4-bus-width4 {
656 samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
657 samsung,pin-function = <3>;
658 samsung,pin-pud = <3>;
659 samsung,pin-drv = <3>;
660 };
661
662 sd4_bus8: sd4-bus-width8 {
663 samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
664 samsung,pin-function = <3>;
665 samsung,pin-pud = <4>;
666 samsung,pin-drv = <3>;
667 };
668
669 sd1_clk: sd1-clk {
670 samsung,pins = "gpk1-0";
671 samsung,pin-function = <2>;
672 samsung,pin-pud = <0>;
673 samsung,pin-drv = <3>;
674 };
675
676 sd1_cmd: sd1-cmd {
677 samsung,pins = "gpk1-1";
678 samsung,pin-function = <2>;
679 samsung,pin-pud = <0>;
680 samsung,pin-drv = <3>;
681 };
682
683 sd1_cd: sd1-cd {
684 samsung,pins = "gpk1-2";
685 samsung,pin-function = <2>;
686 samsung,pin-pud = <3>;
687 samsung,pin-drv = <3>;
688 };
689
690 sd1_bus1: sd1-bus-width1 {
691 samsung,pins = "gpk1-3";
692 samsung,pin-function = <2>;
693 samsung,pin-pud = <3>;
694 samsung,pin-drv = <3>;
695 };
696
697 sd1_bus4: sd1-bus-width4 {
698 samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
699 samsung,pin-function = <2>;
700 samsung,pin-pud = <3>;
701 samsung,pin-drv = <3>;
702 };
703
704 sd2_clk: sd2-clk {
705 samsung,pins = "gpk2-0";
706 samsung,pin-function = <2>;
707 samsung,pin-pud = <0>;
708 samsung,pin-drv = <3>;
709 };
710
711 sd2_cmd: sd2-cmd {
712 samsung,pins = "gpk2-1";
713 samsung,pin-function = <2>;
714 samsung,pin-pud = <0>;
715 samsung,pin-drv = <3>;
716 };
717
718 sd2_cd: sd2-cd {
719 samsung,pins = "gpk2-2";
720 samsung,pin-function = <2>;
721 samsung,pin-pud = <3>;
722 samsung,pin-drv = <3>;
723 };
724
725 sd2_bus1: sd2-bus-width1 {
726 samsung,pins = "gpk2-3";
727 samsung,pin-function = <2>;
728 samsung,pin-pud = <3>;
729 samsung,pin-drv = <3>;
730 };
731
732 sd2_bus4: sd2-bus-width4 {
733 samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6";
734 samsung,pin-function = <2>;
735 samsung,pin-pud = <3>;
736 samsung,pin-drv = <3>;
737 };
738
739 sd2_bus8: sd2-bus-width8 {
740 samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
741 samsung,pin-function = <3>;
742 samsung,pin-pud = <3>;
743 samsung,pin-drv = <3>;
744 };
745
746 sd3_clk: sd3-clk {
747 samsung,pins = "gpk3-0";
748 samsung,pin-function = <2>;
749 samsung,pin-pud = <0>;
750 samsung,pin-drv = <3>;
751 };
752
753 sd3_cmd: sd3-cmd {
754 samsung,pins = "gpk3-1";
755 samsung,pin-function = <2>;
756 samsung,pin-pud = <0>;
757 samsung,pin-drv = <3>;
758 };
759
760 sd3_cd: sd3-cd {
761 samsung,pins = "gpk3-2";
762 samsung,pin-function = <2>;
763 samsung,pin-pud = <3>;
764 samsung,pin-drv = <3>;
765 };
766
767 sd3_bus1: sd3-bus-width1 {
768 samsung,pins = "gpk3-3";
769 samsung,pin-function = <2>;
770 samsung,pin-pud = <3>;
771 samsung,pin-drv = <3>;
772 };
773
774 sd3_bus4: sd3-bus-width4 {
775 samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
776 samsung,pin-function = <2>;
777 samsung,pin-pud = <3>;
778 samsung,pin-drv = <3>;
779 };
780
781 keypad_col0: keypad-col0 {
782 samsung,pins = "gpl2-0";
783 samsung,pin-function = <3>;
784 samsung,pin-pud = <0>;
785 samsung,pin-drv = <0>;
786 };
787
788 keypad_col1: keypad-col1 {
789 samsung,pins = "gpl2-1";
790 samsung,pin-function = <3>;
791 samsung,pin-pud = <0>;
792 samsung,pin-drv = <0>;
793 };
794
795 keypad_col2: keypad-col2 {
796 samsung,pins = "gpl2-2";
797 samsung,pin-function = <3>;
798 samsung,pin-pud = <0>;
799 samsung,pin-drv = <0>;
800 };
801
802 keypad_col3: keypad-col3 {
803 samsung,pins = "gpl2-3";
804 samsung,pin-function = <3>;
805 samsung,pin-pud = <0>;
806 samsung,pin-drv = <0>;
807 };
808
809 keypad_col4: keypad-col4 {
810 samsung,pins = "gpl2-4";
811 samsung,pin-function = <3>;
812 samsung,pin-pud = <0>;
813 samsung,pin-drv = <0>;
814 };
815
816 keypad_col5: keypad-col5 {
817 samsung,pins = "gpl2-5";
818 samsung,pin-function = <3>;
819 samsung,pin-pud = <0>;
820 samsung,pin-drv = <0>;
821 };
822
823 keypad_col6: keypad-col6 {
824 samsung,pins = "gpl2-6";
825 samsung,pin-function = <3>;
826 samsung,pin-pud = <0>;
827 samsung,pin-drv = <0>;
828 };
829
830 keypad_col7: keypad-col7 {
831 samsung,pins = "gpl2-7";
832 samsung,pin-function = <3>;
833 samsung,pin-pud = <0>;
834 samsung,pin-drv = <0>;
835 };
836
837 cam_port_b: cam-port-b {
838 samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
839 "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
840 "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1",
841 "gpm2-2";
842 samsung,pin-function = <3>;
843 samsung,pin-pud = <3>;
844 samsung,pin-drv = <0>;
845 };
846
847 eint0: ext-int0 {
848 samsung,pins = "gpx0-0";
849 samsung,pin-function = <0xf>;
850 samsung,pin-pud = <0>;
851 samsung,pin-drv = <0>;
852 };
853
854 eint8: ext-int8 {
855 samsung,pins = "gpx1-0";
856 samsung,pin-function = <0xf>;
857 samsung,pin-pud = <0>;
858 samsung,pin-drv = <0>;
859 };
860
861 eint15: ext-int15 {
862 samsung,pins = "gpx1-7";
863 samsung,pin-function = <0xf>;
864 samsung,pin-pud = <0>;
865 samsung,pin-drv = <0>;
866 };
867
868 eint16: ext-int16 {
869 samsung,pins = "gpx2-0";
870 samsung,pin-function = <0xf>;
871 samsung,pin-pud = <0>;
872 samsung,pin-drv = <0>;
873 };
874
875 eint31: ext-int31 {
876 samsung,pins = "gpx3-7";
877 samsung,pin-function = <0xf>;
878 samsung,pin-pud = <0>;
879 samsung,pin-drv = <0>;
880 };
881 };
882
883 pinctrl@03860000 {
884 gpz: gpz {
885 gpio-controller;
886 #gpio-cells = <2>;
887
888 interrupt-controller;
889 #interrupt-cells = <2>;
890 };
891
892 i2s0_bus: i2s0-bus {
893 samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
894 "gpz-4", "gpz-5", "gpz-6";
895 samsung,pin-function = <0x2>;
896 samsung,pin-pud = <0>;
897 samsung,pin-drv = <0>;
898 };
899
900 pcm0_bus: pcm0-bus {
901 samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
902 "gpz-4";
903 samsung,pin-function = <0x3>;
904 samsung,pin-pud = <0>;
905 samsung,pin-drv = <0>;
906 };
907 };
908
909 pinctrl@106E0000 {
910 gpv0: gpv0 {
911 gpio-controller;
912 #gpio-cells = <2>;
913
914 interrupt-controller;
915 #interrupt-cells = <2>;
916 };
917
918 gpv1: gpv1 {
919 gpio-controller;
920 #gpio-cells = <2>;
921
922 interrupt-controller;
923 #interrupt-cells = <2>;
924 };
925
926 gpv2: gpv2 {
927 gpio-controller;
928 #gpio-cells = <2>;
929
930 interrupt-controller;
931 #interrupt-cells = <2>;
932 };
933
934 gpv3: gpv3 {
935 gpio-controller;
936 #gpio-cells = <2>;
937
938 interrupt-controller;
939 #interrupt-cells = <2>;
940 };
941
942 gpv4: gpv4 {
943 gpio-controller;
944 #gpio-cells = <2>;
945
946 interrupt-controller;
947 #interrupt-cells = <2>;
948 };
949
950 c2c_bus: c2c-bus {
951 samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3",
952 "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7",
953 "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3",
954 "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7",
955 "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3",
956 "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7",
957 "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3",
958 "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7",
959 "gpv4-0", "gpv4-1";
960 samsung,pin-function = <0x2>;
961 samsung,pin-pud = <0>;
962 samsung,pin-drv = <0>;
963 };
964 };
965};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
new file mode 100644
index 000000000000..179a62e46c9d
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -0,0 +1,69 @@
1/*
2 * Samsung's Exynos4x12 SoCs device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
8 * based board files can include this file and provide values for board specfic
9 * bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
20/include/ "exynos4.dtsi"
21/include/ "exynos4x12-pinctrl.dtsi"
22
23/ {
24 aliases {
25 pinctrl0 = &pinctrl_0;
26 pinctrl1 = &pinctrl_1;
27 pinctrl2 = &pinctrl_2;
28 pinctrl3 = &pinctrl_3;
29 };
30
31 combiner:interrupt-controller@10440000 {
32 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
33 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
34 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
35 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
36 <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
37 };
38
39 pinctrl_0: pinctrl@11400000 {
40 compatible = "samsung,pinctrl-exynos4x12";
41 reg = <0x11400000 0x1000>;
42 interrupts = <0 47 0>;
43 };
44
45 pinctrl_1: pinctrl@11000000 {
46 compatible = "samsung,pinctrl-exynos4x12";
47 reg = <0x11000000 0x1000>;
48 interrupts = <0 46 0>;
49
50 wakup_eint: wakeup-interrupt-controller {
51 compatible = "samsung,exynos4210-wakeup-eint";
52 interrupt-parent = <&gic>;
53 interrupts = <0 32 0>;
54 };
55 };
56
57 pinctrl_2: pinctrl@03860000 {
58 compatible = "samsung,pinctrl-exynos4x12";
59 reg = <0x03860000 0x1000>;
60 interrupt-parent = <&combiner>;
61 interrupts = <10 0>;
62 };
63
64 pinctrl_3: pinctrl@106E0000 {
65 compatible = "samsung,pinctrl-exynos4x12";
66 reg = <0x106E0000 0x1000>;
67 interrupts = <0 72 0>;
68 };
69};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index a352df403b7a..942d5761ca97 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -17,10 +17,6 @@
17 compatible = "samsung,smdk5250", "samsung,exynos5250"; 17 compatible = "samsung,smdk5250", "samsung,exynos5250";
18 18
19 aliases { 19 aliases {
20 mshc0 = &dwmmc_0;
21 mshc1 = &dwmmc_1;
22 mshc2 = &dwmmc_2;
23 mshc3 = &dwmmc_3;
24 }; 20 };
25 21
26 memory { 22 memory {
@@ -55,8 +51,31 @@
55 }; 51 };
56 }; 52 };
57 53
54 i2c@121D0000 {
55 samsung,i2c-sda-delay = <100>;
56 samsung,i2c-max-bus-freq = <40000>;
57 samsung,i2c-slave-addr = <0x38>;
58
59 sata-phy {
60 compatible = "samsung,sata-phy";
61 reg = <0x38>;
62 };
63 };
64
65 sata@122F0000 {
66 samsung,sata-freq = <66>;
67 };
68
58 i2c@12C80000 { 69 i2c@12C80000 {
59 status = "disabled"; 70 samsung,i2c-sda-delay = <100>;
71 samsung,i2c-max-bus-freq = <66000>;
72 gpios = <&gpa0 6 3 3 0>,
73 <&gpa0 7 3 3 0>;
74
75 hdmiddc@50 {
76 compatible = "samsung,exynos5-hdmiddc";
77 reg = <0x50>;
78 };
60 }; 79 };
61 80
62 i2c@12C90000 { 81 i2c@12C90000 {
@@ -79,7 +98,17 @@
79 status = "disabled"; 98 status = "disabled";
80 }; 99 };
81 100
82 dwmmc_0: dwmmc0@12200000 { 101 i2c@12CE0000 {
102 samsung,i2c-sda-delay = <100>;
103 samsung,i2c-max-bus-freq = <66000>;
104
105 hdmiphy@38 {
106 compatible = "samsung,exynos5-hdmiphy";
107 reg = <0x38>;
108 };
109 };
110
111 dwmmc0@12200000 {
83 num-slots = <1>; 112 num-slots = <1>;
84 supports-highspeed; 113 supports-highspeed;
85 broken-cd; 114 broken-cd;
@@ -100,11 +129,11 @@
100 }; 129 };
101 }; 130 };
102 131
103 dwmmc_1: dwmmc1@12210000 { 132 dwmmc1@12210000 {
104 status = "disabled"; 133 status = "disabled";
105 }; 134 };
106 135
107 dwmmc_2: dwmmc2@12220000 { 136 dwmmc2@12220000 {
108 num-slots = <1>; 137 num-slots = <1>;
109 supports-highspeed; 138 supports-highspeed;
110 fifo-depth = <0x80>; 139 fifo-depth = <0x80>;
@@ -125,7 +154,7 @@
125 }; 154 };
126 }; 155 };
127 156
128 dwmmc_3: dwmmc3@12230000 { 157 dwmmc3@12230000 {
129 status = "disabled"; 158 status = "disabled";
130 }; 159 };
131 160
@@ -166,4 +195,13 @@
166 spi_2: spi@12d40000 { 195 spi_2: spi@12d40000 {
167 status = "disabled"; 196 status = "disabled";
168 }; 197 };
198
199 hdmi {
200 hpd-gpio = <&gpx3 7 0xf 1 3>;
201 };
202
203 codec@11000000 {
204 samsung,mfc-r = <0x43000000 0x800000>;
205 samsung,mfc-l = <0x51000000 0x800000>;
206 };
169}; 207};
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
new file mode 100644
index 000000000000..17dd951c1cd2
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -0,0 +1,43 @@
1/*
2 * Google Snow board device tree source
3 *
4 * Copyright (c) 2012 Google, Inc
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11/dts-v1/;
12/include/ "exynos5250.dtsi"
13/include/ "cros5250-common.dtsi"
14
15/ {
16 model = "Google Snow";
17 compatible = "google,snow", "samsung,exynos5250";
18
19 gpio-keys {
20 compatible = "gpio-keys";
21
22 lid-switch {
23 label = "Lid";
24 gpios = <&gpx3 5 0 0x10000 0>;
25 linux,input-type = <5>; /* EV_SW */
26 linux,code = <0>; /* SW_LID */
27 debounce-interval = <1>;
28 gpio-key,wakeup;
29 };
30 };
31
32 /*
33 * On Snow we've got SIP WiFi and so can keep drive strengths low to
34 * reduce EMI.
35 */
36 dwmmc3@12230000 {
37 slot@0 {
38 gpios = <&gpc4 0 2 0 0>, <&gpc4 1 2 3 0>,
39 <&gpc4 3 2 3 0>, <&gpc4 4 2 3 0>,
40 <&gpc4 5 2 3 0>, <&gpc4 6 2 3 0>;
41 };
42 };
43};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index dddfd6e444dc..3acf594ea60b 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -31,6 +31,19 @@
31 gsc1 = &gsc_1; 31 gsc1 = &gsc_1;
32 gsc2 = &gsc_2; 32 gsc2 = &gsc_2;
33 gsc3 = &gsc_3; 33 gsc3 = &gsc_3;
34 mshc0 = &dwmmc_0;
35 mshc1 = &dwmmc_1;
36 mshc2 = &dwmmc_2;
37 mshc3 = &dwmmc_3;
38 i2c0 = &i2c_0;
39 i2c1 = &i2c_1;
40 i2c2 = &i2c_2;
41 i2c3 = &i2c_3;
42 i2c4 = &i2c_4;
43 i2c5 = &i2c_5;
44 i2c6 = &i2c_6;
45 i2c7 = &i2c_7;
46 i2c8 = &i2c_8;
34 }; 47 };
35 48
36 gic:interrupt-controller@10481000 { 49 gic:interrupt-controller@10481000 {
@@ -62,12 +75,24 @@
62 interrupts = <0 42 0>; 75 interrupts = <0 42 0>;
63 }; 76 };
64 77
78 codec@11000000 {
79 compatible = "samsung,mfc-v6";
80 reg = <0x11000000 0x10000>;
81 interrupts = <0 96 0>;
82 };
83
65 rtc { 84 rtc {
66 compatible = "samsung,s3c6410-rtc"; 85 compatible = "samsung,s3c6410-rtc";
67 reg = <0x101E0000 0x100>; 86 reg = <0x101E0000 0x100>;
68 interrupts = <0 43 0>, <0 44 0>; 87 interrupts = <0 43 0>, <0 44 0>;
69 }; 88 };
70 89
90 tmu@10060000 {
91 compatible = "samsung,exynos5250-tmu";
92 reg = <0x10060000 0x100>;
93 interrupts = <0 65 0>;
94 };
95
71 serial@12C00000 { 96 serial@12C00000 {
72 compatible = "samsung,exynos4210-uart"; 97 compatible = "samsung,exynos4210-uart";
73 reg = <0x12C00000 0x100>; 98 reg = <0x12C00000 0x100>;
@@ -92,7 +117,18 @@
92 interrupts = <0 54 0>; 117 interrupts = <0 54 0>;
93 }; 118 };
94 119
95 i2c@12C60000 { 120 sata@122F0000 {
121 compatible = "samsung,exynos5-sata-ahci";
122 reg = <0x122F0000 0x1ff>;
123 interrupts = <0 115 0>;
124 };
125
126 sata-phy@12170000 {
127 compatible = "samsung,exynos5-sata-phy";
128 reg = <0x12170000 0x1ff>;
129 };
130
131 i2c_0: i2c@12C60000 {
96 compatible = "samsung,s3c2440-i2c"; 132 compatible = "samsung,s3c2440-i2c";
97 reg = <0x12C60000 0x100>; 133 reg = <0x12C60000 0x100>;
98 interrupts = <0 56 0>; 134 interrupts = <0 56 0>;
@@ -100,7 +136,7 @@
100 #size-cells = <0>; 136 #size-cells = <0>;
101 }; 137 };
102 138
103 i2c@12C70000 { 139 i2c_1: i2c@12C70000 {
104 compatible = "samsung,s3c2440-i2c"; 140 compatible = "samsung,s3c2440-i2c";
105 reg = <0x12C70000 0x100>; 141 reg = <0x12C70000 0x100>;
106 interrupts = <0 57 0>; 142 interrupts = <0 57 0>;
@@ -108,7 +144,7 @@
108 #size-cells = <0>; 144 #size-cells = <0>;
109 }; 145 };
110 146
111 i2c@12C80000 { 147 i2c_2: i2c@12C80000 {
112 compatible = "samsung,s3c2440-i2c"; 148 compatible = "samsung,s3c2440-i2c";
113 reg = <0x12C80000 0x100>; 149 reg = <0x12C80000 0x100>;
114 interrupts = <0 58 0>; 150 interrupts = <0 58 0>;
@@ -116,7 +152,7 @@
116 #size-cells = <0>; 152 #size-cells = <0>;
117 }; 153 };
118 154
119 i2c@12C90000 { 155 i2c_3: i2c@12C90000 {
120 compatible = "samsung,s3c2440-i2c"; 156 compatible = "samsung,s3c2440-i2c";
121 reg = <0x12C90000 0x100>; 157 reg = <0x12C90000 0x100>;
122 interrupts = <0 59 0>; 158 interrupts = <0 59 0>;
@@ -124,7 +160,7 @@
124 #size-cells = <0>; 160 #size-cells = <0>;
125 }; 161 };
126 162
127 i2c@12CA0000 { 163 i2c_4: i2c@12CA0000 {
128 compatible = "samsung,s3c2440-i2c"; 164 compatible = "samsung,s3c2440-i2c";
129 reg = <0x12CA0000 0x100>; 165 reg = <0x12CA0000 0x100>;
130 interrupts = <0 60 0>; 166 interrupts = <0 60 0>;
@@ -132,7 +168,7 @@
132 #size-cells = <0>; 168 #size-cells = <0>;
133 }; 169 };
134 170
135 i2c@12CB0000 { 171 i2c_5: i2c@12CB0000 {
136 compatible = "samsung,s3c2440-i2c"; 172 compatible = "samsung,s3c2440-i2c";
137 reg = <0x12CB0000 0x100>; 173 reg = <0x12CB0000 0x100>;
138 interrupts = <0 61 0>; 174 interrupts = <0 61 0>;
@@ -140,7 +176,7 @@
140 #size-cells = <0>; 176 #size-cells = <0>;
141 }; 177 };
142 178
143 i2c@12CC0000 { 179 i2c_6: i2c@12CC0000 {
144 compatible = "samsung,s3c2440-i2c"; 180 compatible = "samsung,s3c2440-i2c";
145 reg = <0x12CC0000 0x100>; 181 reg = <0x12CC0000 0x100>;
146 interrupts = <0 62 0>; 182 interrupts = <0 62 0>;
@@ -148,7 +184,7 @@
148 #size-cells = <0>; 184 #size-cells = <0>;
149 }; 185 };
150 186
151 i2c@12CD0000 { 187 i2c_7: i2c@12CD0000 {
152 compatible = "samsung,s3c2440-i2c"; 188 compatible = "samsung,s3c2440-i2c";
153 reg = <0x12CD0000 0x100>; 189 reg = <0x12CD0000 0x100>;
154 interrupts = <0 63 0>; 190 interrupts = <0 63 0>;
@@ -156,6 +192,21 @@
156 #size-cells = <0>; 192 #size-cells = <0>;
157 }; 193 };
158 194
195 i2c_8: i2c@12CE0000 {
196 compatible = "samsung,s3c2440-hdmiphy-i2c";
197 reg = <0x12CE0000 0x1000>;
198 interrupts = <0 64 0>;
199 #address-cells = <1>;
200 #size-cells = <0>;
201 };
202
203 i2c@121D0000 {
204 compatible = "samsung,exynos5-sata-phy-i2c";
205 reg = <0x121D0000 0x100>;
206 #address-cells = <1>;
207 #size-cells = <0>;
208 };
209
159 spi_0: spi@12d20000 { 210 spi_0: spi@12d20000 {
160 compatible = "samsung,exynos4210-spi"; 211 compatible = "samsung,exynos4210-spi";
161 reg = <0x12d20000 0x100>; 212 reg = <0x12d20000 0x100>;
@@ -186,7 +237,7 @@
186 #size-cells = <0>; 237 #size-cells = <0>;
187 }; 238 };
188 239
189 dwmmc0@12200000 { 240 dwmmc_0: dwmmc0@12200000 {
190 compatible = "samsung,exynos5250-dw-mshc"; 241 compatible = "samsung,exynos5250-dw-mshc";
191 reg = <0x12200000 0x1000>; 242 reg = <0x12200000 0x1000>;
192 interrupts = <0 75 0>; 243 interrupts = <0 75 0>;
@@ -194,7 +245,7 @@
194 #size-cells = <0>; 245 #size-cells = <0>;
195 }; 246 };
196 247
197 dwmmc1@12210000 { 248 dwmmc_1: dwmmc1@12210000 {
198 compatible = "samsung,exynos5250-dw-mshc"; 249 compatible = "samsung,exynos5250-dw-mshc";
199 reg = <0x12210000 0x1000>; 250 reg = <0x12210000 0x1000>;
200 interrupts = <0 76 0>; 251 interrupts = <0 76 0>;
@@ -202,7 +253,7 @@
202 #size-cells = <0>; 253 #size-cells = <0>;
203 }; 254 };
204 255
205 dwmmc2@12220000 { 256 dwmmc_2: dwmmc2@12220000 {
206 compatible = "samsung,exynos5250-dw-mshc"; 257 compatible = "samsung,exynos5250-dw-mshc";
207 reg = <0x12220000 0x1000>; 258 reg = <0x12220000 0x1000>;
208 interrupts = <0 77 0>; 259 interrupts = <0 77 0>;
@@ -210,7 +261,7 @@
210 #size-cells = <0>; 261 #size-cells = <0>;
211 }; 262 };
212 263
213 dwmmc3@12230000 { 264 dwmmc_3: dwmmc3@12230000 {
214 compatible = "samsung,exynos5250-dw-mshc"; 265 compatible = "samsung,exynos5250-dw-mshc";
215 reg = <0x12230000 0x1000>; 266 reg = <0x12230000 0x1000>;
216 interrupts = <0 78 0>; 267 interrupts = <0 78 0>;
@@ -520,4 +571,16 @@
520 reg = <0x13e30000 0x1000>; 571 reg = <0x13e30000 0x1000>;
521 interrupts = <0 88 0>; 572 interrupts = <0 88 0>;
522 }; 573 };
574
575 hdmi {
576 compatible = "samsung,exynos5-hdmi";
577 reg = <0x14530000 0x70000>;
578 interrupts = <0 95 0>;
579 };
580
581 mixer {
582 compatible = "samsung,exynos5-mixer";
583 reg = <0x14450000 0x10000>;
584 interrupts = <0 94 0>;
585 };
523}; 586};
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
new file mode 100644
index 000000000000..81e2c964a900
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -0,0 +1,46 @@
1/*
2 * SAMSUNG SSDK5440 board device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/dts-v1/;
13/include/ "exynos5440.dtsi"
14
15/ {
16 model = "SAMSUNG SSDK5440 board based on EXYNOS5440";
17 compatible = "samsung,ssdk5440", "samsung,exynos5440";
18
19 memory {
20 reg = <0x80000000 0x80000000>;
21 };
22
23 chosen {
24 bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x81000000,8M console=ttySAC0,115200 init=/linuxrc";
25 };
26
27 spi {
28 status = "disabled";
29 };
30
31 i2c@F0000 {
32 status = "disabled";
33 };
34
35 i2c@100000 {
36 status = "disabled";
37 };
38
39 watchdog {
40 status = "disabled";
41 };
42
43 rtc {
44 status = "disabled";
45 };
46};
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
new file mode 100644
index 000000000000..024269de8ee5
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -0,0 +1,159 @@
1/*
2 * SAMSUNG EXYNOS5440 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/include/ "skeleton.dtsi"
13
14/ {
15 compatible = "samsung,exynos5440";
16
17 interrupt-parent = <&gic>;
18
19 gic:interrupt-controller@2E0000 {
20 compatible = "arm,cortex-a15-gic";
21 #interrupt-cells = <3>;
22 interrupt-controller;
23 reg = <0x2E1000 0x1000>, <0x2E2000 0x1000>;
24 };
25
26 cpus {
27 cpu@0 {
28 compatible = "arm,cortex-a15";
29 timer {
30 compatible = "arm,armv7-timer";
31 interrupts = <1 13 0xf08>;
32 clock-frequency = <1000000>;
33 };
34 };
35 cpu@1 {
36 compatible = "arm,cortex-a15";
37 timer {
38 compatible = "arm,armv7-timer";
39 interrupts = <1 14 0xf08>;
40 clock-frequency = <1000000>;
41 };
42 };
43 cpu@2 {
44 compatible = "arm,cortex-a15";
45 timer {
46 compatible = "arm,armv7-timer";
47 interrupts = <1 14 0xf08>;
48 clock-frequency = <1000000>;
49 };
50 };
51 cpu@3 {
52 compatible = "arm,cortex-a15";
53 timer {
54 compatible = "arm,armv7-timer";
55 interrupts = <1 14 0xf08>;
56 clock-frequency = <1000000>;
57 };
58 };
59 };
60
61 common {
62 compatible = "samsung,exynos5440";
63
64 };
65
66 serial@B0000 {
67 compatible = "samsung,exynos4210-uart";
68 reg = <0xB0000 0x1000>;
69 interrupts = <0 2 0>;
70 };
71
72 serial@C0000 {
73 compatible = "samsung,exynos4210-uart";
74 reg = <0xC0000 0x1000>;
75 interrupts = <0 3 0>;
76 };
77
78 spi {
79 compatible = "samsung,exynos4210-spi";
80 reg = <0xD0000 0x1000>;
81 interrupts = <0 4 0>;
82 tx-dma-channel = <&pdma0 5>; /* preliminary */
83 rx-dma-channel = <&pdma0 4>; /* preliminary */
84 #address-cells = <1>;
85 #size-cells = <0>;
86 };
87
88 pinctrl {
89 compatible = "samsung,pinctrl-exynos5440";
90 reg = <0xE0000 0x1000>;
91 interrupt-controller;
92 #interrupt-cells = <2>;
93 #gpio-cells = <2>;
94
95 fan: fan {
96 samsung,exynos5440-pin-function = <1>;
97 };
98
99 hdd_led0: hdd_led0 {
100 samsung,exynos5440-pin-function = <2>;
101 };
102
103 hdd_led1: hdd_led1 {
104 samsung,exynos5440-pin-function = <3>;
105 };
106
107 uart1: uart1 {
108 samsung,exynos5440-pin-function = <4>;
109 };
110 };
111
112 i2c@F0000 {
113 compatible = "samsung,s3c2440-i2c";
114 reg = <0xF0000 0x1000>;
115 interrupts = <0 5 0>;
116 #address-cells = <1>;
117 #size-cells = <0>;
118 };
119
120 i2c@100000 {
121 compatible = "samsung,s3c2440-i2c";
122 reg = <0x100000 0x1000>;
123 interrupts = <0 6 0>;
124 #address-cells = <1>;
125 #size-cells = <0>;
126 };
127
128 watchdog {
129 compatible = "samsung,s3c2410-wdt";
130 reg = <0x110000 0x1000>;
131 interrupts = <0 1 0>;
132 };
133
134 amba {
135 #address-cells = <1>;
136 #size-cells = <1>;
137 compatible = "arm,amba-bus";
138 interrupt-parent = <&gic>;
139 ranges;
140
141 pdma0: pdma@121A0000 {
142 compatible = "arm,pl330", "arm,primecell";
143 reg = <0x120000 0x1000>;
144 interrupts = <0 34 0>;
145 };
146
147 pdma1: pdma@121B0000 {
148 compatible = "arm,pl330", "arm,primecell";
149 reg = <0x121000 0x1000>;
150 interrupts = <0 35 0>;
151 };
152 };
153
154 rtc {
155 compatible = "samsung,s3c6410-rtc";
156 reg = <0x130000 0x1000>;
157 interrupts = <0 16 0>, <0 17 0>;
158 };
159};
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index 0c6fc34821f9..5927a8df5625 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -30,33 +30,37 @@
30 #address-cells = <1>; 30 #address-cells = <1>;
31 #size-cells = <0>; 31 #size-cells = <0>;
32 32
33 cpu@0 { 33 cpu@900 {
34 compatible = "arm,cortex-a9"; 34 compatible = "arm,cortex-a9";
35 reg = <0>; 35 device_type = "cpu";
36 reg = <0x900>;
36 next-level-cache = <&L2>; 37 next-level-cache = <&L2>;
37 clocks = <&a9pll>; 38 clocks = <&a9pll>;
38 clock-names = "cpu"; 39 clock-names = "cpu";
39 }; 40 };
40 41
41 cpu@1 { 42 cpu@901 {
42 compatible = "arm,cortex-a9"; 43 compatible = "arm,cortex-a9";
43 reg = <1>; 44 device_type = "cpu";
45 reg = <0x901>;
44 next-level-cache = <&L2>; 46 next-level-cache = <&L2>;
45 clocks = <&a9pll>; 47 clocks = <&a9pll>;
46 clock-names = "cpu"; 48 clock-names = "cpu";
47 }; 49 };
48 50
49 cpu@2 { 51 cpu@902 {
50 compatible = "arm,cortex-a9"; 52 compatible = "arm,cortex-a9";
51 reg = <2>; 53 device_type = "cpu";
54 reg = <0x902>;
52 next-level-cache = <&L2>; 55 next-level-cache = <&L2>;
53 clocks = <&a9pll>; 56 clocks = <&a9pll>;
54 clock-names = "cpu"; 57 clock-names = "cpu";
55 }; 58 };
56 59
57 cpu@3 { 60 cpu@903 {
58 compatible = "arm,cortex-a9"; 61 compatible = "arm,cortex-a9";
59 reg = <3>; 62 device_type = "cpu";
63 reg = <0x903>;
60 next-level-cache = <&L2>; 64 next-level-cache = <&L2>;
61 clocks = <&a9pll>; 65 clocks = <&a9pll>;
62 clock-names = "cpu"; 66 clock-names = "cpu";
@@ -69,16 +73,8 @@
69 reg = <0x00000000 0xff900000>; 73 reg = <0x00000000 0xff900000>;
70 }; 74 };
71 75
72 chosen {
73 bootargs = "console=ttyAMA0";
74 };
75
76 soc { 76 soc {
77 #address-cells = <1>; 77 ranges = <0x00000000 0x00000000 0xffffffff>;
78 #size-cells = <1>;
79 compatible = "simple-bus";
80 interrupt-parent = <&intc>;
81 ranges;
82 78
83 timer@fff10600 { 79 timer@fff10600 {
84 compatible = "arm,cortex-a9-twd-timer"; 80 compatible = "arm,cortex-a9-twd-timer";
@@ -117,173 +113,6 @@
117 interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>; 113 interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
118 }; 114 };
119 115
120 sata@ffe08000 {
121 compatible = "calxeda,hb-ahci";
122 reg = <0xffe08000 0x10000>;
123 interrupts = <0 83 4>;
124 calxeda,port-phys = <&combophy5 0 &combophy0 0
125 &combophy0 1 &combophy0 2
126 &combophy0 3>;
127 dma-coherent;
128 };
129
130 sdhci@ffe0e000 {
131 compatible = "calxeda,hb-sdhci";
132 reg = <0xffe0e000 0x1000>;
133 interrupts = <0 90 4>;
134 clocks = <&eclk>;
135 };
136
137 memory-controller@fff00000 {
138 compatible = "calxeda,hb-ddr-ctrl";
139 reg = <0xfff00000 0x1000>;
140 interrupts = <0 91 4>;
141 };
142
143 ipc@fff20000 {
144 compatible = "arm,pl320", "arm,primecell";
145 reg = <0xfff20000 0x1000>;
146 interrupts = <0 7 4>;
147 clocks = <&pclk>;
148 clock-names = "apb_pclk";
149 };
150
151 gpioe: gpio@fff30000 {
152 #gpio-cells = <2>;
153 compatible = "arm,pl061", "arm,primecell";
154 gpio-controller;
155 reg = <0xfff30000 0x1000>;
156 interrupts = <0 14 4>;
157 clocks = <&pclk>;
158 clock-names = "apb_pclk";
159 };
160
161 gpiof: gpio@fff31000 {
162 #gpio-cells = <2>;
163 compatible = "arm,pl061", "arm,primecell";
164 gpio-controller;
165 reg = <0xfff31000 0x1000>;
166 interrupts = <0 15 4>;
167 clocks = <&pclk>;
168 clock-names = "apb_pclk";
169 };
170
171 gpiog: gpio@fff32000 {
172 #gpio-cells = <2>;
173 compatible = "arm,pl061", "arm,primecell";
174 gpio-controller;
175 reg = <0xfff32000 0x1000>;
176 interrupts = <0 16 4>;
177 clocks = <&pclk>;
178 clock-names = "apb_pclk";
179 };
180
181 gpioh: gpio@fff33000 {
182 #gpio-cells = <2>;
183 compatible = "arm,pl061", "arm,primecell";
184 gpio-controller;
185 reg = <0xfff33000 0x1000>;
186 interrupts = <0 17 4>;
187 clocks = <&pclk>;
188 clock-names = "apb_pclk";
189 };
190
191 timer {
192 compatible = "arm,sp804", "arm,primecell";
193 reg = <0xfff34000 0x1000>;
194 interrupts = <0 18 4>;
195 clocks = <&pclk>;
196 clock-names = "apb_pclk";
197 };
198
199 rtc@fff35000 {
200 compatible = "arm,pl031", "arm,primecell";
201 reg = <0xfff35000 0x1000>;
202 interrupts = <0 19 4>;
203 clocks = <&pclk>;
204 clock-names = "apb_pclk";
205 };
206
207 serial@fff36000 {
208 compatible = "arm,pl011", "arm,primecell";
209 reg = <0xfff36000 0x1000>;
210 interrupts = <0 20 4>;
211 clocks = <&pclk>;
212 clock-names = "apb_pclk";
213 };
214
215 smic@fff3a000 {
216 compatible = "ipmi-smic";
217 device_type = "ipmi";
218 reg = <0xfff3a000 0x1000>;
219 interrupts = <0 24 4>;
220 reg-size = <4>;
221 reg-spacing = <4>;
222 };
223
224 sregs@fff3c000 {
225 compatible = "calxeda,hb-sregs";
226 reg = <0xfff3c000 0x1000>;
227
228 clocks {
229 #address-cells = <1>;
230 #size-cells = <0>;
231
232 osc: oscillator {
233 #clock-cells = <0>;
234 compatible = "fixed-clock";
235 clock-frequency = <33333000>;
236 };
237
238 ddrpll: ddrpll {
239 #clock-cells = <0>;
240 compatible = "calxeda,hb-pll-clock";
241 clocks = <&osc>;
242 reg = <0x108>;
243 };
244
245 a9pll: a9pll {
246 #clock-cells = <0>;
247 compatible = "calxeda,hb-pll-clock";
248 clocks = <&osc>;
249 reg = <0x100>;
250 };
251
252 a9periphclk: a9periphclk {
253 #clock-cells = <0>;
254 compatible = "calxeda,hb-a9periph-clock";
255 clocks = <&a9pll>;
256 reg = <0x104>;
257 };
258
259 a9bclk: a9bclk {
260 #clock-cells = <0>;
261 compatible = "calxeda,hb-a9bus-clock";
262 clocks = <&a9pll>;
263 reg = <0x104>;
264 };
265
266 emmcpll: emmcpll {
267 #clock-cells = <0>;
268 compatible = "calxeda,hb-pll-clock";
269 clocks = <&osc>;
270 reg = <0x10C>;
271 };
272
273 eclk: eclk {
274 #clock-cells = <0>;
275 compatible = "calxeda,hb-emmc-clock";
276 clocks = <&emmcpll>;
277 reg = <0x114>;
278 };
279
280 pclk: pclk {
281 #clock-cells = <0>;
282 compatible = "fixed-clock";
283 clock-frequency = <150000000>;
284 };
285 };
286 };
287 116
288 sregs@fff3c200 { 117 sregs@fff3c200 {
289 compatible = "calxeda,hb-sregs-l2-ecc"; 118 compatible = "calxeda,hb-sregs-l2-ecc";
@@ -291,38 +120,7 @@
291 interrupts = <0 71 4 0 72 4>; 120 interrupts = <0 71 4 0 72 4>;
292 }; 121 };
293 122
294 dma@fff3d000 {
295 compatible = "arm,pl330", "arm,primecell";
296 reg = <0xfff3d000 0x1000>;
297 interrupts = <0 92 4>;
298 clocks = <&pclk>;
299 clock-names = "apb_pclk";
300 };
301
302 ethernet@fff50000 {
303 compatible = "calxeda,hb-xgmac";
304 reg = <0xfff50000 0x1000>;
305 interrupts = <0 77 4 0 78 4 0 79 4>;
306 };
307
308 ethernet@fff51000 {
309 compatible = "calxeda,hb-xgmac";
310 reg = <0xfff51000 0x1000>;
311 interrupts = <0 80 4 0 81 4 0 82 4>;
312 };
313
314 combophy0: combo-phy@fff58000 {
315 compatible = "calxeda,hb-combophy";
316 #phy-cells = <1>;
317 reg = <0xfff58000 0x1000>;
318 phydev = <5>;
319 };
320
321 combophy5: combo-phy@fff5d000 {
322 compatible = "calxeda,hb-combophy";
323 #phy-cells = <1>;
324 reg = <0xfff5d000 0x1000>;
325 phydev = <31>;
326 };
327 }; 123 };
328}; 124};
125
126/include/ "ecx-common.dtsi"
diff --git a/arch/arm/boot/dts/href.dtsi b/arch/arm/boot/dts/href.dtsi
new file mode 100644
index 000000000000..592fb9dc35bd
--- /dev/null
+++ b/arch/arm/boot/dts/href.dtsi
@@ -0,0 +1,273 @@
1/*
2 * Copyright 2012 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "dbx5x0.dtsi"
13
14/ {
15 memory {
16 reg = <0x00000000 0x20000000>;
17 };
18
19 gpio_keys {
20 compatible = "gpio-keys";
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 button@1 {
25 linux,code = <11>;
26 label = "SFH7741 Proximity Sensor";
27 };
28 };
29
30 soc-u9500 {
31 uart@80120000 {
32 status = "okay";
33 };
34
35 uart@80121000 {
36 status = "okay";
37 };
38
39 uart@80007000 {
40 status = "okay";
41 };
42
43 i2c@80004000 {
44 tc3589x@42 {
45 compatible = "tc3589x";
46 reg = <0x42>;
47 interrupt-parent = <&gpio6>;
48 interrupts = <25 0x1>;
49
50 interrupt-controller;
51 #interrupt-cells = <2>;
52
53 tc3589x_gpio: tc3589x_gpio {
54 compatible = "tc3589x-gpio";
55 interrupts = <0 0x1>;
56
57 interrupt-controller;
58 #interrupt-cells = <2>;
59 gpio-controller;
60 #gpio-cells = <2>;
61 };
62 };
63 };
64
65 i2c@80128000 {
66 lp5521@0x33 {
67 compatible = "lp5521";
68 reg = <0x33>;
69 };
70
71 lp5521@0x34 {
72 compatible = "lp5521";
73 reg = <0x34>;
74 };
75
76 bh1780@0x29 {
77 compatible = "rohm,bh1780gli";
78 reg = <0x33>;
79 };
80 };
81
82 // External Micro SD slot
83 sdi0_per1@80126000 {
84 arm,primecell-periphid = <0x10480180>;
85 max-frequency = <50000000>;
86 bus-width = <4>;
87 mmc-cap-sd-highspeed;
88 mmc-cap-mmc-highspeed;
89 vmmc-supply = <&ab8500_ldo_aux3_reg>;
90
91 cd-gpios = <&tc3589x_gpio 3 0x4>;
92
93 status = "okay";
94 };
95
96 // WLAN SDIO channel
97 sdi1_per2@80118000 {
98 arm,primecell-periphid = <0x10480180>;
99 max-frequency = <50000000>;
100 bus-width = <4>;
101
102 status = "okay";
103 };
104
105 // PoP:ed eMMC
106 sdi2_per3@80005000 {
107 arm,primecell-periphid = <0x10480180>;
108 max-frequency = <50000000>;
109 bus-width = <8>;
110 mmc-cap-mmc-highspeed;
111
112 status = "okay";
113 };
114
115 // On-board eMMC
116 sdi4_per2@80114000 {
117 arm,primecell-periphid = <0x10480180>;
118 max-frequency = <50000000>;
119 bus-width = <8>;
120 mmc-cap-mmc-highspeed;
121 vmmc-supply = <&ab8500_ldo_aux2_reg>;
122
123 status = "okay";
124 };
125
126 sound {
127 compatible = "stericsson,snd-soc-mop500";
128
129 stericsson,cpu-dai = <&msp1 &msp3>;
130 stericsson,audio-codec = <&codec>;
131 };
132
133 msp1: msp@80124000 {
134 status = "okay";
135 };
136
137 msp3: msp@80125000 {
138 status = "okay";
139 };
140
141 prcmu@80157000 {
142 db8500-prcmu-regulators {
143 db8500_vape_reg: db8500_vape {
144 regulator-name = "db8500-vape";
145 };
146
147 db8500_varm_reg: db8500_varm {
148 regulator-name = "db8500-varm";
149 };
150
151 db8500_vmodem_reg: db8500_vmodem {
152 regulator-name = "db8500-vmodem";
153 };
154
155 db8500_vpll_reg: db8500_vpll {
156 regulator-name = "db8500-vpll";
157 };
158
159 db8500_vsmps1_reg: db8500_vsmps1 {
160 regulator-name = "db8500-vsmps1";
161 };
162
163 db8500_vsmps2_reg: db8500_vsmps2 {
164 regulator-name = "db8500-vsmps2";
165 };
166
167 db8500_vsmps3_reg: db8500_vsmps3 {
168 regulator-name = "db8500-vsmps3";
169 };
170
171 db8500_vrf1_reg: db8500_vrf1 {
172 regulator-name = "db8500-vrf1";
173 };
174
175 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
176 regulator-name = "db8500-sva-mmdsp";
177 };
178
179 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
180 regulator-name = "db8500-sva-mmdsp-ret";
181 };
182
183 db8500_sva_pipe_reg: db8500_sva_pipe {
184 regulator-name = "db8500_sva_pipe";
185 };
186
187 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
188 regulator-name = "db8500_sia_mmdsp";
189 };
190
191 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
192 regulator-name = "db8500-sia-mmdsp-ret";
193 };
194
195 db8500_sia_pipe_reg: db8500_sia_pipe {
196 regulator-name = "db8500-sia-pipe";
197 };
198
199 db8500_sga_reg: db8500_sga {
200 regulator-name = "db8500-sga";
201 };
202
203 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
204 regulator-name = "db8500-b2r2-mcde";
205 };
206
207 db8500_esram12_reg: db8500_esram12 {
208 regulator-name = "db8500-esram12";
209 };
210
211 db8500_esram12_ret_reg: db8500_esram12_ret {
212 regulator-name = "db8500-esram12-ret";
213 };
214
215 db8500_esram34_reg: db8500_esram34 {
216 regulator-name = "db8500-esram34";
217 };
218
219 db8500_esram34_ret_reg: db8500_esram34_ret {
220 regulator-name = "db8500-esram34-ret";
221 };
222 };
223
224 ab8500@5 {
225 ab8500-regulators {
226 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
227 regulator-name = "V-DISPLAY";
228 };
229
230 ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
231 regulator-name = "V-eMMC1";
232 };
233
234 ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
235 regulator-name = "V-MMC-SD";
236 };
237
238 ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
239 regulator-name = "V-INTCORE";
240 };
241
242 ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
243 regulator-name = "V-TVOUT";
244 };
245
246 ab8500_ldo_usb_reg: ab8500_ldo_usb {
247 regulator-name = "dummy";
248 };
249
250 ab8500_ldo_audio_reg: ab8500_ldo_audio {
251 regulator-name = "V-AUD";
252 };
253
254 ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
255 regulator-name = "V-AMIC1";
256 };
257
258 ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
259 regulator-name = "V-AMIC2";
260 };
261
262 ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
263 regulator-name = "V-DMIC";
264 };
265
266 ab8500_ldo_ana_reg: ab8500_ldo_ana {
267 regulator-name = "V-CSI/DSI";
268 };
269 };
270 };
271 };
272 };
273};
diff --git a/arch/arm/boot/dts/hrefprev60.dts b/arch/arm/boot/dts/hrefprev60.dts
new file mode 100644
index 000000000000..eec29c4a86dc
--- /dev/null
+++ b/arch/arm/boot/dts/hrefprev60.dts
@@ -0,0 +1,48 @@
1/*
2 * Copyright 2012 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "dbx5x0.dtsi"
14/include/ "href.dtsi"
15/include/ "stuib.dtsi"
16
17/ {
18 model = "ST-Ericsson HREF (pre-v60) platform with Device Tree";
19 compatible = "st-ericsson,mop500", "st-ericsson,u8500";
20
21 gpio_keys {
22 button@1 {
23 gpios = <&tc3589x_gpio 7 0x4>;
24 };
25 };
26
27 soc-u9500 {
28 i2c@80004000 {
29 tps61052@33 {
30 compatible = "tps61052";
31 reg = <0x33>;
32 };
33 };
34
35 i2c@80110000 {
36 bu21013_tp@0x5c {
37 reset-gpio = <&tc3589x_gpio 13 0x4>;
38 };
39 };
40
41 vmmci: regulator-gpio {
42 gpios = <&tc3589x_gpio 18 0x4>;
43 gpio-enable = <&tc3589x_gpio 17 0x4>;
44
45 status = "okay";
46 };
47 };
48};
diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts
index 2131d77dc9c9..55f4191a626e 100644
--- a/arch/arm/boot/dts/hrefv60plus.dts
+++ b/arch/arm/boot/dts/hrefv60plus.dts
@@ -11,85 +11,200 @@
11 11
12/dts-v1/; 12/dts-v1/;
13/include/ "dbx5x0.dtsi" 13/include/ "dbx5x0.dtsi"
14/include/ "href.dtsi"
15/include/ "stuib.dtsi"
14 16
15/ { 17/ {
16 model = "ST-Ericsson HREF platform with Device Tree"; 18 model = "ST-Ericsson HREF (v60+) platform with Device Tree";
17 compatible = "st-ericsson,hrefv60+"; 19 compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500";
18 20
19 memory { 21 gpio_keys {
20 reg = <0x00000000 0x20000000>; 22 button@1 {
23 gpios = <&gpio6 25 0x4>;
24 };
21 }; 25 };
22 26
23 soc-u9500 { 27 soc-u9500 {
24 uart@80120000 { 28 i2c@80110000 {
29 bu21013_tp@0x5c {
30 reset-gpio = <&gpio4 15 0x4>;
31 };
32 };
33
34 // External Micro SD slot
35 sdi0_per1@80126000 {
36 arm,primecell-periphid = <0x10480180>;
37 max-frequency = <50000000>;
38 bus-width = <4>;
39 mmc-cap-sd-highspeed;
40 mmc-cap-mmc-highspeed;
41 vmmc-supply = <&ab8500_ldo_aux3_reg>;
42
43 cd-gpios = <&tc3589x_gpio 3 0x4>;
44
25 status = "okay"; 45 status = "okay";
26 }; 46 };
27 47
28 uart@80121000 { 48 // WLAN SDIO channel
49 sdi1_per2@80118000 {
50 arm,primecell-periphid = <0x10480180>;
51 max-frequency = <50000000>;
52 bus-width = <4>;
53
29 status = "okay"; 54 status = "okay";
30 }; 55 };
31 56
32 uart@80007000 { 57 // PoP:ed eMMC
58 sdi2_per3@80005000 {
59 arm,primecell-periphid = <0x10480180>;
60 max-frequency = <50000000>;
61 bus-width = <8>;
62 mmc-cap-mmc-highspeed;
63
33 status = "okay"; 64 status = "okay";
34 }; 65 };
35 66
36 i2c@80004000 { 67 // On-board eMMC
37 tc3589x@42 { 68 sdi4_per2@80114000 {
38 compatible = "tc3589x"; 69 arm,primecell-periphid = <0x10480180>;
39 reg = <0x42>; 70 max-frequency = <50000000>;
40 interrupt-parent = <&gpio6>; 71 bus-width = <8>;
41 interrupts = <25 0x1>; 72 mmc-cap-mmc-highspeed;
73 vmmc-supply = <&ab8500_ldo_aux2_reg>;
42 74
43 interrupt-controller; 75 status = "okay";
44 #interrupt-cells = <2>; 76 };
45 77
46 tc3589x_gpio: tc3589x_gpio { 78 prcmu@80157000 {
47 compatible = "tc3589x-gpio"; 79 db8500-prcmu-regulators {
48 interrupts = <0 0x1>; 80 db8500_vape_reg: db8500_vape {
81 regulator-name = "db8500-vape";
82 };
49 83
50 interrupt-controller; 84 db8500_varm_reg: db8500_varm {
51 #interrupt-cells = <2>; 85 regulator-name = "db8500-varm";
52 gpio-controller;
53 #gpio-cells = <2>;
54 }; 86 };
55 };
56 87
57 tps61052@33 { 88 db8500_vmodem_reg: db8500_vmodem {
58 compatible = "tps61052"; 89 regulator-name = "db8500-vmodem";
59 reg = <0x33>; 90 };
60 };
61 };
62 91
63 i2c@80128000 { 92 db8500_vpll_reg: db8500_vpll {
64 lp5521@0x33 { 93 regulator-name = "db8500-vpll";
65 compatible = "lp5521"; 94 };
66 reg = <0x33>;
67 };
68 95
69 lp5521@0x34 { 96 db8500_vsmps1_reg: db8500_vsmps1 {
70 compatible = "lp5521"; 97 regulator-name = "db8500-vsmps1";
71 reg = <0x34>; 98 };
72 }; 99
100 db8500_vsmps2_reg: db8500_vsmps2 {
101 regulator-name = "db8500-vsmps2";
102 };
103
104 db8500_vsmps3_reg: db8500_vsmps3 {
105 regulator-name = "db8500-vsmps3";
106 };
107
108 db8500_vrf1_reg: db8500_vrf1 {
109 regulator-name = "db8500-vrf1";
110 };
111
112 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
113 regulator-name = "db8500-sva-mmdsp";
114 };
115
116 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
117 regulator-name = "db8500-sva-mmdsp-ret";
118 };
119
120 db8500_sva_pipe_reg: db8500_sva_pipe {
121 regulator-name = "db8500_sva_pipe";
122 };
73 123
74 bh1780@0x29 { 124 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
75 compatible = "rohm,bh1780gli"; 125 regulator-name = "db8500_sia_mmdsp";
76 reg = <0x33>; 126 };
127
128 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
129 regulator-name = "db8500-sia-mmdsp-ret";
130 };
131
132 db8500_sia_pipe_reg: db8500_sia_pipe {
133 regulator-name = "db8500-sia-pipe";
134 };
135
136 db8500_sga_reg: db8500_sga {
137 regulator-name = "db8500-sga";
138 };
139
140 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
141 regulator-name = "db8500-b2r2-mcde";
142 };
143
144 db8500_esram12_reg: db8500_esram12 {
145 regulator-name = "db8500-esram12";
146 };
147
148 db8500_esram12_ret_reg: db8500_esram12_ret {
149 regulator-name = "db8500-esram12-ret";
150 };
151
152 db8500_esram34_reg: db8500_esram34 {
153 regulator-name = "db8500-esram34";
154 };
155
156 db8500_esram34_ret_reg: db8500_esram34_ret {
157 regulator-name = "db8500-esram34-ret";
158 };
77 }; 159 };
78 };
79 160
80 sound { 161 ab8500@5 {
81 compatible = "stericsson,snd-soc-mop500"; 162 ab8500-regulators {
163 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
164 regulator-name = "V-DISPLAY";
165 };
82 166
83 stericsson,cpu-dai = <&msp1 &msp3>; 167 ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
84 stericsson,audio-codec = <&codec>; 168 regulator-name = "V-eMMC1";
85 }; 169 };
86 170
87 msp1: msp@80124000 { 171 ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
88 status = "okay"; 172 regulator-name = "V-MMC-SD";
89 }; 173 };
90 174
91 msp3: msp@80125000 { 175 ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
92 status = "okay"; 176 regulator-name = "V-INTCORE";
177 };
178
179 ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
180 regulator-name = "V-TVOUT";
181 };
182
183 ab8500_ldo_usb_reg: ab8500_ldo_usb {
184 regulator-name = "dummy";
185 };
186
187 ab8500_ldo_audio_reg: ab8500_ldo_audio {
188 regulator-name = "V-AUD";
189 };
190
191 ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
192 regulator-name = "V-AMIC1";
193 };
194
195 ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
196 regulator-name = "V-AMIC2";
197 };
198
199 ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
200 regulator-name = "V-DMIC";
201 };
202
203 ab8500_ldo_ana_reg: ab8500_ldo_ana {
204 regulator-name = "V-CSI/DSI";
205 };
206 };
207 };
93 }; 208 };
94 }; 209 };
95}; 210};
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
index 384d8b66f337..e7484e4ea659 100644
--- a/arch/arm/boot/dts/imx23-olinuxino.dts
+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
@@ -39,13 +39,31 @@
39 hog_pins_a: hog@0 { 39 hog_pins_a: hog@0 {
40 reg = <0>; 40 reg = <0>;
41 fsl,pinmux-ids = < 41 fsl,pinmux-ids = <
42 0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */
43 0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */ 42 0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */
44 >; 43 >;
45 fsl,drive-strength = <0>; 44 fsl,drive-strength = <0>;
46 fsl,voltage = <1>; 45 fsl,voltage = <1>;
47 fsl,pull-up = <0>; 46 fsl,pull-up = <0>;
48 }; 47 };
48
49 led_pin_gpio2_1: led_gpio2_1@0 {
50 reg = <0>;
51 fsl,pinmux-ids = <
52 0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */
53 >;
54 fsl,drive-strength = <0>;
55 fsl,voltage = <1>;
56 fsl,pull-up = <0>;
57 };
58 };
59
60 ssp1: ssp@80034000 {
61 #address-cells = <1>;
62 #size-cells = <0>;
63 compatible = "fsl,imx23-spi";
64 pinctrl-names = "default";
65 pinctrl-0 = <&spi2_pins_a>;
66 status = "okay";
49 }; 67 };
50 }; 68 };
51 69
@@ -91,11 +109,12 @@
91 109
92 leds { 110 leds {
93 compatible = "gpio-leds"; 111 compatible = "gpio-leds";
112 pinctrl-names = "default";
113 pinctrl-0 = <&led_pin_gpio2_1>;
94 114
95 user { 115 user {
96 label = "green"; 116 label = "green";
97 gpios = <&gpio2 1 0>; 117 gpios = <&gpio2 1 1>;
98 linux,default-trigger = "default-on";
99 }; 118 };
100 }; 119 };
101}; 120};
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 6d31aa383460..65415c598a5e 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -279,6 +279,19 @@
279 fsl,voltage = <1>; 279 fsl,voltage = <1>;
280 fsl,pull-up = <0>; 280 fsl,pull-up = <0>;
281 }; 281 };
282
283 spi2_pins_a: spi2@0 {
284 reg = <0>;
285 fsl,pinmux-ids = <
286 0x0182 /* MX23_PAD_GPMI_WRN__SSP2_SCK */
287 0x0142 /* MX23_PAD_GPMI_RDY1__SSP2_CMD */
288 0x0002 /* MX23_PAD_GPMI_D00__SSP2_DATA0 */
289 0x0032 /* MX23_PAD_GPMI_D03__SSP2_DATA3 */
290 >;
291 fsl,drive-strength = <1>;
292 fsl,voltage = <1>;
293 fsl,pull-up = <1>;
294 };
282 }; 295 };
283 296
284 digctl@8001c000 { 297 digctl@8001c000 {
diff --git a/arch/arm/boot/dts/imx25-karo-tx25.dts b/arch/arm/boot/dts/imx25-karo-tx25.dts
new file mode 100644
index 000000000000..d81f8a0b9794
--- /dev/null
+++ b/arch/arm/boot/dts/imx25-karo-tx25.dts
@@ -0,0 +1,44 @@
1/*
2 * Copyright 2012 Sascha Hauer, Pengutronix
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx25.dtsi"
14
15/ {
16 model = "Ka-Ro TX25";
17 compatible = "karo,imx25-tx25", "fsl,imx25";
18
19 memory {
20 reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
21 };
22
23 soc {
24 aips@43f00000 {
25 uart1: serial@43f90000 {
26 status = "okay";
27 };
28 };
29
30 spba@50000000 {
31 fec: ethernet@50038000 {
32 status = "okay";
33 phy-mode = "rmii";
34 };
35 };
36
37 emi@80000000 {
38 nand@bb000000 {
39 nand-on-flash-bbt;
40 status = "okay";
41 };
42 };
43 };
44};
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
new file mode 100644
index 000000000000..e1b13ebc96d6
--- /dev/null
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -0,0 +1,515 @@
1/*
2 * Copyright 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 aliases {
16 serial0 = &uart1;
17 serial1 = &uart2;
18 serial2 = &uart3;
19 serial3 = &uart4;
20 serial4 = &uart5;
21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 usb0 = &usbotg;
26 usb1 = &usbhost1;
27 };
28
29 asic: asic-interrupt-controller@68000000 {
30 compatible = "fsl,imx25-asic", "fsl,avic";
31 interrupt-controller;
32 #interrupt-cells = <1>;
33 reg = <0x68000000 0x8000000>;
34 };
35
36 clocks {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 osc {
41 compatible = "fsl,imx-osc", "fixed-clock";
42 clock-frequency = <24000000>;
43 };
44 };
45
46 soc {
47 #address-cells = <1>;
48 #size-cells = <1>;
49 compatible = "simple-bus";
50 interrupt-parent = <&asic>;
51 ranges;
52
53 aips@43f00000 { /* AIPS1 */
54 compatible = "fsl,aips-bus", "simple-bus";
55 #address-cells = <1>;
56 #size-cells = <1>;
57 reg = <0x43f00000 0x100000>;
58 ranges;
59
60 i2c1: i2c@43f80000 {
61 #address-cells = <1>;
62 #size-cells = <0>;
63 compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
64 reg = <0x43f80000 0x4000>;
65 clocks = <&clks 48>;
66 clock-names = "";
67 interrupts = <3>;
68 status = "disabled";
69 };
70
71 i2c3: i2c@43f84000 {
72 #address-cells = <1>;
73 #size-cells = <0>;
74 compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
75 reg = <0x43f84000 0x4000>;
76 clocks = <&clks 48>;
77 clock-names = "";
78 interrupts = <10>;
79 status = "disabled";
80 };
81
82 can1: can@43f88000 {
83 compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan";
84 reg = <0x43f88000 0x4000>;
85 interrupts = <43>;
86 clocks = <&clks 75>, <&clks 75>;
87 clock-names = "ipg", "per";
88 status = "disabled";
89 };
90
91 can2: can@43f8c000 {
92 compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan";
93 reg = <0x43f8c000 0x4000>;
94 interrupts = <44>;
95 clocks = <&clks 76>, <&clks 76>;
96 clock-names = "ipg", "per";
97 status = "disabled";
98 };
99
100 uart1: serial@43f90000 {
101 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
102 reg = <0x43f90000 0x4000>;
103 interrupts = <45>;
104 clocks = <&clks 120>, <&clks 57>;
105 clock-names = "ipg", "per";
106 status = "disabled";
107 };
108
109 uart2: serial@43f94000 {
110 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
111 reg = <0x43f94000 0x4000>;
112 interrupts = <32>;
113 clocks = <&clks 121>, <&clks 57>;
114 clock-names = "ipg", "per";
115 status = "disabled";
116 };
117
118 i2c2: i2c@43f98000 {
119 #address-cells = <1>;
120 #size-cells = <0>;
121 compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
122 reg = <0x43f98000 0x4000>;
123 clocks = <&clks 48>;
124 clock-names = "";
125 interrupts = <4>;
126 status = "disabled";
127 };
128
129 owire@43f9c000 {
130 #address-cells = <1>;
131 #size-cells = <0>;
132 reg = <0x43f9c000 0x4000>;
133 clocks = <&clks 51>;
134 clock-names = "";
135 interrupts = <2>;
136 status = "disabled";
137 };
138
139 spi1: cspi@43fa4000 {
140 #address-cells = <1>;
141 #size-cells = <0>;
142 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
143 reg = <0x43fa4000 0x4000>;
144 clocks = <&clks 62>;
145 clock-names = "ipg";
146 interrupts = <14>;
147 status = "disabled";
148 };
149
150 kpp@43fa8000 {
151 #address-cells = <1>;
152 #size-cells = <0>;
153 reg = <0x43fa8000 0x4000>;
154 clocks = <&clks 102>;
155 clock-names = "";
156 interrupts = <24>;
157 status = "disabled";
158 };
159
160 iomuxc@43fac000{
161 compatible = "fsl,imx25-iomuxc";
162 reg = <0x43fac000 0x4000>;
163 };
164
165 audmux@43fb0000 {
166 compatible = "fsl,imx25-audmux", "fsl,imx31-audmux";
167 reg = <0x43fb0000 0x4000>;
168 status = "disabled";
169 };
170 };
171
172 spba@50000000 {
173 compatible = "fsl,spba-bus", "simple-bus";
174 #address-cells = <1>;
175 #size-cells = <1>;
176 reg = <0x50000000 0x40000>;
177 ranges;
178
179 spi3: cspi@50004000 {
180 #address-cells = <1>;
181 #size-cells = <0>;
182 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
183 reg = <0x50004000 0x4000>;
184 interrupts = <0>;
185 clocks = <&clks 80>;
186 clock-names = "ipg";
187 status = "disabled";
188 };
189
190 uart4: serial@50008000 {
191 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
192 reg = <0x50008000 0x4000>;
193 interrupts = <5>;
194 clocks = <&clks 123>, <&clks 57>;
195 clock-names = "ipg", "per";
196 status = "disabled";
197 };
198
199 uart3: serial@5000c000 {
200 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
201 reg = <0x5000c000 0x4000>;
202 interrupts = <18>;
203 clocks = <&clks 122>, <&clks 57>;
204 clock-names = "ipg", "per";
205 status = "disabled";
206 };
207
208 spi2: cspi@50010000 {
209 #address-cells = <1>;
210 #size-cells = <0>;
211 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
212 reg = <0x50010000 0x4000>;
213 clocks = <&clks 79>;
214 clock-names = "ipg";
215 interrupts = <13>;
216 status = "disabled";
217 };
218
219 ssi2: ssi@50014000 {
220 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
221 reg = <0x50014000 0x4000>;
222 interrupts = <11>;
223 status = "disabled";
224 };
225
226 esai@50018000 {
227 reg = <0x50018000 0x4000>;
228 interrupts = <7>;
229 };
230
231 uart5: serial@5002c000 {
232 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
233 reg = <0x5002c000 0x4000>;
234 interrupts = <40>;
235 clocks = <&clks 124>, <&clks 57>;
236 clock-names = "ipg", "per";
237 status = "disabled";
238 };
239
240 tsc: tsc@50030000 {
241 compatible = "fsl,imx25-adc", "fsl,imx21-tsc";
242 reg = <0x50030000 0x4000>;
243 interrupts = <46>;
244 clocks = <&clks 119>;
245 clock-names = "ipg";
246 status = "disabled";
247 };
248
249 ssi1: ssi@50034000 {
250 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
251 reg = <0x50034000 0x4000>;
252 interrupts = <12>;
253 status = "disabled";
254 };
255
256 fec: ethernet@50038000 {
257 compatible = "fsl,imx25-fec";
258 reg = <0x50038000 0x4000>;
259 interrupts = <57>;
260 clocks = <&clks 88>, <&clks 65>;
261 clock-names = "ipg", "ahb";
262 status = "disabled";
263 };
264 };
265
266 aips@53f00000 { /* AIPS2 */
267 compatible = "fsl,aips-bus", "simple-bus";
268 #address-cells = <1>;
269 #size-cells = <1>;
270 reg = <0x53f00000 0x100000>;
271 ranges;
272
273 clks: ccm@53f80000 {
274 compatible = "fsl,imx25-ccm";
275 reg = <0x53f80000 0x4000>;
276 interrupts = <31>;
277 #clock-cells = <1>;
278 };
279
280 gpt4: timer@53f84000 {
281 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
282 reg = <0x53f84000 0x4000>;
283 clocks = <&clks 9>, <&clks 45>;
284 clock-names = "ipg", "per";
285 interrupts = <1>;
286 };
287
288 gpt3: timer@53f88000 {
289 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
290 reg = <0x53f88000 0x4000>;
291 clocks = <&clks 9>, <&clks 47>;
292 clock-names = "ipg", "per";
293 interrupts = <29>;
294 };
295
296 gpt2: timer@53f8c000 {
297 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
298 reg = <0x53f8c000 0x4000>;
299 clocks = <&clks 9>, <&clks 47>;
300 clock-names = "ipg", "per";
301 interrupts = <53>;
302 };
303
304 gpt1: timer@53f90000 {
305 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
306 reg = <0x53f90000 0x4000>;
307 clocks = <&clks 9>, <&clks 47>;
308 clock-names = "ipg", "per";
309 interrupts = <54>;
310 };
311
312 epit1: timer@53f94000 {
313 compatible = "fsl,imx25-epit";
314 reg = <0x53f94000 0x4000>;
315 interrupts = <28>;
316 };
317
318 epit2: timer@53f98000 {
319 compatible = "fsl,imx25-epit";
320 reg = <0x53f98000 0x4000>;
321 interrupts = <27>;
322 };
323
324 gpio4: gpio@53f9c000 {
325 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
326 reg = <0x53f9c000 0x4000>;
327 interrupts = <23>;
328 gpio-controller;
329 #gpio-cells = <2>;
330 interrupt-controller;
331 #interrupt-cells = <2>;
332 };
333
334 pwm2: pwm@53fa0000 {
335 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
336 #pwm-cells = <2>;
337 reg = <0x53fa0000 0x4000>;
338 clocks = <&clks 106>, <&clks 36>;
339 clock-names = "ipg", "per";
340 interrupts = <36>;
341 };
342
343 gpio3: gpio@53fa4000 {
344 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
345 reg = <0x53fa4000 0x4000>;
346 interrupts = <16>;
347 gpio-controller;
348 #gpio-cells = <2>;
349 interrupt-controller;
350 #interrupt-cells = <2>;
351 };
352
353 pwm3: pwm@53fa8000 {
354 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
355 #pwm-cells = <2>;
356 reg = <0x53fa8000 0x4000>;
357 clocks = <&clks 107>, <&clks 36>;
358 clock-names = "ipg", "per";
359 interrupts = <41>;
360 };
361
362 esdhc1: esdhc@53fb4000 {
363 compatible = "fsl,imx25-esdhc";
364 reg = <0x53fb4000 0x4000>;
365 interrupts = <9>;
366 clocks = <&clks 86>, <&clks 63>, <&clks 45>;
367 clock-names = "ipg", "ahb", "per";
368 status = "disabled";
369 };
370
371 esdhc2: esdhc@53fb8000 {
372 compatible = "fsl,imx25-esdhc";
373 reg = <0x53fb8000 0x4000>;
374 interrupts = <8>;
375 clocks = <&clks 87>, <&clks 64>, <&clks 46>;
376 clock-names = "ipg", "ahb", "per";
377 status = "disabled";
378 };
379
380 lcdc@53fbc000 {
381 reg = <0x53fbc000 0x4000>;
382 interrupts = <39>;
383 clocks = <&clks 103>, <&clks 66>, <&clks 49>;
384 clock-names = "ipg", "ahb", "per";
385 status = "disabled";
386 };
387
388 slcdc@53fc0000 {
389 reg = <0x53fc0000 0x4000>;
390 interrupts = <38>;
391 status = "disabled";
392 };
393
394 pwm4: pwm@53fc8000 {
395 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
396 reg = <0x53fc8000 0x4000>;
397 clocks = <&clks 108>, <&clks 36>;
398 clock-names = "ipg", "per";
399 interrupts = <42>;
400 };
401
402 gpio1: gpio@53fcc000 {
403 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
404 reg = <0x53fcc000 0x4000>;
405 interrupts = <52>;
406 gpio-controller;
407 #gpio-cells = <2>;
408 interrupt-controller;
409 #interrupt-cells = <2>;
410 };
411
412 gpio2: gpio@53fd0000 {
413 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
414 reg = <0x53fd0000 0x4000>;
415 interrupts = <51>;
416 gpio-controller;
417 #gpio-cells = <2>;
418 interrupt-controller;
419 #interrupt-cells = <2>;
420 };
421
422 sdma@53fd4000 {
423 compatible = "fsl,imx25-sdma", "fsl,imx35-sdma";
424 reg = <0x53fd4000 0x4000>;
425 clocks = <&clks 112>, <&clks 68>;
426 clock-names = "ipg", "ahb";
427 interrupts = <34>;
428 };
429
430 wdog@53fdc000 {
431 compatible = "fsl,imx25-wdt", "fsl,imx21-wdt";
432 reg = <0x53fdc000 0x4000>;
433 clocks = <&clks 126>;
434 clock-names = "";
435 interrupts = <55>;
436 };
437
438 pwm1: pwm@53fe0000 {
439 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
440 #pwm-cells = <2>;
441 reg = <0x53fe0000 0x4000>;
442 clocks = <&clks 105>, <&clks 36>;
443 clock-names = "ipg", "per";
444 interrupts = <26>;
445 };
446
447 usbphy1: usbphy@1 {
448 compatible = "nop-usbphy";
449 status = "disabled";
450 };
451
452 usbphy2: usbphy@2 {
453 compatible = "nop-usbphy";
454 status = "disabled";
455 };
456
457 usbotg: usb@53ff4000 {
458 compatible = "fsl,imx25-usb", "fsl,imx27-usb";
459 reg = <0x53ff4000 0x0200>;
460 interrupts = <37>;
461 clocks = <&clks 9>, <&clks 70>, <&clks 8>;
462 clock-names = "ipg", "ahb", "per";
463 fsl,usbmisc = <&usbmisc 0>;
464 status = "disabled";
465 };
466
467 usbhost1: usb@53ff4400 {
468 compatible = "fsl,imx25-usb", "fsl,imx27-usb";
469 reg = <0x53ff4400 0x0200>;
470 interrupts = <35>;
471 clocks = <&clks 9>, <&clks 70>, <&clks 8>;
472 clock-names = "ipg", "ahb", "per";
473 fsl,usbmisc = <&usbmisc 1>;
474 status = "disabled";
475 };
476
477 usbmisc: usbmisc@53ff4600 {
478 #index-cells = <1>;
479 compatible = "fsl,imx25-usbmisc";
480 clocks = <&clks 9>, <&clks 70>, <&clks 8>;
481 clock-names = "ipg", "ahb", "per";
482 reg = <0x53ff4600 0x00f>;
483 status = "disabled";
484 };
485
486 dryice@53ffc000 {
487 compatible = "fsl,imx25-dryice", "fsl,imx25-rtc";
488 reg = <0x53ffc000 0x4000>;
489 clocks = <&clks 81>;
490 clock-names = "ipg";
491 interrupts = <25>;
492 };
493 };
494
495 emi@80000000 {
496 compatible = "fsl,emi-bus", "simple-bus";
497 #address-cells = <1>;
498 #size-cells = <1>;
499 reg = <0x80000000 0x3b002000>;
500 ranges;
501
502 nand@bb000000 {
503 #address-cells = <1>;
504 #size-cells = <1>;
505
506 compatible = "fsl,imx25-nand";
507 reg = <0xbb000000 0x2000>;
508 clocks = <&clks 50>;
509 clock-names = "";
510 interrupts = <33>;
511 status = "disabled";
512 };
513 };
514 };
515};
diff --git a/arch/arm/boot/dts/imx27-3ds.dts b/arch/arm/boot/dts/imx27-3ds.dts
index 0a8978a40ece..fa04c7b18bcb 100644
--- a/arch/arm/boot/dts/imx27-3ds.dts
+++ b/arch/arm/boot/dts/imx27-3ds.dts
@@ -21,21 +21,17 @@
21 }; 21 };
22 22
23 soc { 23 soc {
24 aipi@10000000 { /* aipi */ 24 aipi@10000000 { /* aipi1 */
25
26 wdog@10002000 {
27 status = "okay";
28 };
29
30 uart1: serial@1000a000 { 25 uart1: serial@1000a000 {
31 fsl,uart-has-rtscts; 26 fsl,uart-has-rtscts;
32 status = "okay"; 27 status = "okay";
33 }; 28 };
29 };
34 30
35 fec@1002b000 { 31 aipi@10020000 { /* aipi2 */
32 ethernet@1002b000 {
36 status = "okay"; 33 status = "okay";
37 }; 34 };
38 }; 35 };
39 }; 36 };
40
41}; 37};
diff --git a/arch/arm/boot/dts/imx27-apf27.dts b/arch/arm/boot/dts/imx27-apf27.dts
new file mode 100644
index 000000000000..c0327c054de2
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-apf27.dts
@@ -0,0 +1,89 @@
1/*
2 * Copyright 2012 Philippe Reynes <tremyfr@yahoo.fr>
3 * Copyright 2012 Armadeus Systems <support@armadeus.com>
4 *
5 * Based on code which is: Copyright 2012 Sascha Hauer, Pengutronix
6 *
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
10 *
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
13 */
14
15/dts-v1/;
16/include/ "imx27.dtsi"
17
18/ {
19 model = "Armadeus Systems APF27 module";
20 compatible = "armadeus,imx27-apf27", "fsl,imx27";
21
22 memory {
23 reg = <0xa0000000 0x04000000>;
24 };
25
26 clocks {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 osc26m {
31 compatible = "fsl,imx-osc26m", "fixed-clock";
32 clock-frequency = <0>;
33 };
34 };
35
36 soc {
37 aipi@10000000 {
38 serial@1000a000 {
39 status = "okay";
40 };
41
42 ethernet@1002b000 {
43 status = "okay";
44 };
45 };
46
47 nand@d8000000 {
48 status = "okay";
49 nand-bus-width = <16>;
50 nand-ecc-mode = "hw";
51 nand-on-flash-bbt;
52
53 partition@0 {
54 label = "u-boot";
55 reg = <0x0 0x100000>;
56 };
57
58 partition@100000 {
59 label = "env";
60 reg = <0x100000 0x80000>;
61 };
62
63 partition@180000 {
64 label = "env2";
65 reg = <0x180000 0x80000>;
66 };
67
68 partition@200000 {
69 label = "firmware";
70 reg = <0x200000 0x80000>;
71 };
72
73 partition@280000 {
74 label = "dtb";
75 reg = <0x280000 0x80000>;
76 };
77
78 partition@300000 {
79 label = "kernel";
80 reg = <0x300000 0x500000>;
81 };
82
83 partition@800000 {
84 label = "rootfs";
85 reg = <0x800000 0xf800000>;
86 };
87 };
88 };
89};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
index af50469e34b2..53b0ec0c228e 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts
@@ -21,8 +21,7 @@
21 }; 21 };
22 22
23 soc { 23 soc {
24 aipi@10000000 { /* aipi */ 24 aipi@10000000 { /* aipi1 */
25
26 serial@1000a000 { 25 serial@1000a000 {
27 fsl,uart-has-rtscts; 26 fsl,uart-has-rtscts;
28 status = "okay"; 27 status = "okay";
@@ -38,10 +37,6 @@
38 status = "okay"; 37 status = "okay";
39 }; 38 };
40 39
41 ethernet@1002b000 {
42 status = "okay";
43 };
44
45 i2c@1001d000 { 40 i2c@1001d000 {
46 clock-frequency = <400000>; 41 clock-frequency = <400000>;
47 status = "okay"; 42 status = "okay";
@@ -60,6 +55,12 @@
60 }; 55 };
61 }; 56 };
62 }; 57 };
58
59 aipi@10020000 { /* aipi2 */
60 ethernet@1002b000 {
61 status = "okay";
62 };
63 };
63 }; 64 };
64 65
65 nor_flash@c0000000 { 66 nor_flash@c0000000 {
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 3e54f1498841..5a82cb5707a8 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -55,10 +55,10 @@
55 compatible = "fsl,aipi-bus", "simple-bus"; 55 compatible = "fsl,aipi-bus", "simple-bus";
56 #address-cells = <1>; 56 #address-cells = <1>;
57 #size-cells = <1>; 57 #size-cells = <1>;
58 reg = <0x10000000 0x10000000>; 58 reg = <0x10000000 0x20000>;
59 ranges; 59 ranges;
60 60
61 wdog@10002000 { 61 wdog: wdog@10002000 {
62 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; 62 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
63 reg = <0x10002000 0x4000>; 63 reg = <0x10002000 0x4000>;
64 interrupts = <27>; 64 interrupts = <27>;
@@ -113,7 +113,7 @@
113 i2c1: i2c@10012000 { 113 i2c1: i2c@10012000 {
114 #address-cells = <1>; 114 #address-cells = <1>;
115 #size-cells = <0>; 115 #size-cells = <0>;
116 compatible = "fsl,imx27-i2c", "fsl,imx1-i2c"; 116 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
117 reg = <0x10012000 0x1000>; 117 reg = <0x10012000 0x1000>;
118 interrupts = <12>; 118 interrupts = <12>;
119 status = "disabled"; 119 status = "disabled";
@@ -205,12 +205,21 @@
205 i2c2: i2c@1001d000 { 205 i2c2: i2c@1001d000 {
206 #address-cells = <1>; 206 #address-cells = <1>;
207 #size-cells = <0>; 207 #size-cells = <0>;
208 compatible = "fsl,imx27-i2c", "fsl,imx1-i2c"; 208 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
209 reg = <0x1001d000 0x1000>; 209 reg = <0x1001d000 0x1000>;
210 interrupts = <1>; 210 interrupts = <1>;
211 status = "disabled"; 211 status = "disabled";
212 }; 212 };
213 213
214 };
215
216 aipi@10020000 { /* AIPI2 */
217 compatible = "fsl,aipi-bus", "simple-bus";
218 #address-cells = <1>;
219 #size-cells = <1>;
220 reg = <0x10020000 0x20000>;
221 ranges;
222
214 fec: ethernet@1002b000 { 223 fec: ethernet@1002b000 {
215 compatible = "fsl,imx27-fec"; 224 compatible = "fsl,imx27-fec";
216 reg = <0x1002b000 0x4000>; 225 reg = <0x1002b000 0x4000>;
@@ -218,7 +227,8 @@
218 status = "disabled"; 227 status = "disabled";
219 }; 228 };
220 }; 229 };
221 nand@d8000000 { 230
231 nfc: nand@d8000000 {
222 #address-cells = <1>; 232 #address-cells = <1>;
223 #size-cells = <1>; 233 #size-cells = <1>;
224 234
diff --git a/arch/arm/boot/dts/imx28-apf28.dts b/arch/arm/boot/dts/imx28-apf28.dts
new file mode 100644
index 000000000000..7eb075876c4c
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-apf28.dts
@@ -0,0 +1,85 @@
1/*
2 * Copyright 2012 Armadeus Systems - <support@armadeus.com>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx28.dtsi"
14
15/ {
16 model = "Armadeus Systems APF28 module";
17 compatible = "armadeus,imx28-apf28", "fsl,imx28";
18
19 memory {
20 reg = <0x40000000 0x08000000>;
21 };
22
23 apb@80000000 {
24 apbh@80000000 {
25 gpmi-nand@8000c000 {
26 pinctrl-names = "default";
27 pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
28 status = "okay";
29
30 partition@0 {
31 label = "u-boot";
32 reg = <0x0 0x300000>;
33 };
34
35 partition@300000 {
36 label = "env";
37 reg = <0x300000 0x80000>;
38 };
39
40 partition@380000 {
41 label = "env2";
42 reg = <0x380000 0x80000>;
43 };
44
45 partition@400000 {
46 label = "dtb";
47 reg = <0x400000 0x80000>;
48 };
49
50 partition@480000 {
51 label = "splash";
52 reg = <0x480000 0x80000>;
53 };
54
55 partition@500000 {
56 label = "kernel";
57 reg = <0x500000 0x800000>;
58 };
59
60 partition@d00000 {
61 label = "rootfs";
62 reg = <0xd00000 0xf300000>;
63 };
64 };
65 };
66
67 apbx@80040000 {
68 duart: serial@80074000 {
69 pinctrl-names = "default";
70 pinctrl-0 = <&duart_pins_a>;
71 status = "okay";
72 };
73 };
74 };
75
76 ahb@80080000 {
77 mac0: ethernet@800f0000 {
78 phy-mode = "rmii";
79 pinctrl-names = "default";
80 pinctrl-0 = <&mac0_pins_a>;
81 phy-reset-gpios = <&gpio4 13 0>;
82 status = "okay";
83 };
84 };
85};
diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts
new file mode 100644
index 000000000000..6d8865bfb4b7
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-apf28dev.dts
@@ -0,0 +1,154 @@
1/*
2 * Copyright 2012 Armadeus Systems - <support@armadeus.com>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/* APF28Dev is a docking board for the APF28 SOM */
13/include/ "imx28-apf28.dts"
14
15/ {
16 model = "Armadeus Systems APF28Dev docking/development board";
17 compatible = "armadeus,imx28-apf28dev", "armadeus,imx28-apf28", "fsl,imx28";
18
19 apb@80000000 {
20 apbh@80000000 {
21 ssp0: ssp@80010000 {
22 compatible = "fsl,imx28-mmc";
23 pinctrl-names = "default";
24 pinctrl-0 = <&mmc0_4bit_pins_a
25 &mmc0_cd_cfg &mmc0_sck_cfg>;
26 bus-width = <4>;
27 status = "okay";
28 };
29
30 ssp2: ssp@80014000 {
31 compatible = "fsl,imx28-spi";
32 pinctrl-names = "default";
33 pinctrl-0 = <&spi2_pins_a>;
34 status = "okay";
35 };
36
37 pinctrl@80018000 {
38 pinctrl-names = "default";
39 pinctrl-0 = <&hog_pins_apf28dev>;
40
41 hog_pins_apf28dev: hog@0 {
42 reg = <0>;
43 fsl,pinmux-ids = <
44 0x1103 /* MX28_PAD_LCD_D16__GPIO_1_16 */
45 0x1113 /* MX28_PAD_LCD_D17__GPIO_1_17 */
46 0x1123 /* MX28_PAD_LCD_D18__GPIO_1_18 */
47 0x1133 /* MX28_PAD_LCD_D19__GPIO_1_19 */
48 0x1143 /* MX28_PAD_LCD_D20__GPIO_1_20 */
49 0x1153 /* MX28_PAD_LCD_D21__GPIO_1_21 */
50 0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */
51 >;
52 fsl,drive-strength = <0>;
53 fsl,voltage = <1>;
54 fsl,pull-up = <0>;
55 };
56
57 lcdif_pins_apf28dev: lcdif-apf28dev@0 {
58 reg = <0>;
59 fsl,pinmux-ids = <
60 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
61 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
62 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
63 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
64 >;
65 fsl,drive-strength = <0>;
66 fsl,voltage = <1>;
67 fsl,pull-up = <0>;
68 };
69 };
70
71 lcdif@80030000 {
72 pinctrl-names = "default";
73 pinctrl-0 = <&lcdif_16bit_pins_a
74 &lcdif_pins_apf28dev>;
75 status = "okay";
76 };
77 };
78
79 apbx@80040000 {
80 lradc@80050000 {
81 status = "okay";
82 };
83
84 i2c0: i2c@80058000 {
85 pinctrl-names = "default";
86 pinctrl-0 = <&i2c0_pins_a>;
87 status = "okay";
88 };
89
90 pwm: pwm@80064000 {
91 pinctrl-names = "default";
92 pinctrl-0 = <&pwm3_pins_a &pwm4_pins_a>;
93 status = "okay";
94 };
95
96 usbphy0: usbphy@8007c000 {
97 status = "okay";
98 };
99
100 usbphy1: usbphy@8007e000 {
101 status = "okay";
102 };
103 };
104 };
105
106 ahb@80080000 {
107 usb0: usb@80080000 {
108 vbus-supply = <&reg_usb0_vbus>;
109 status = "okay";
110 };
111
112 usb1: usb@80090000 {
113 status = "okay";
114 };
115
116 mac1: ethernet@800f4000 {
117 phy-mode = "rmii";
118 pinctrl-names = "default";
119 pinctrl-0 = <&mac1_pins_a>;
120 phy-reset-gpios = <&gpio0 23 0>;
121 status = "okay";
122 };
123 };
124
125 regulators {
126 compatible = "simple-bus";
127
128 reg_usb0_vbus: usb0_vbus {
129 compatible = "regulator-fixed";
130 regulator-name = "usb0_vbus";
131 regulator-min-microvolt = <5000000>;
132 regulator-max-microvolt = <5000000>;
133 gpio = <&gpio1 23 1>;
134 };
135 };
136
137 leds {
138 compatible = "gpio-leds";
139
140 user {
141 label = "Heartbeat";
142 gpios = <&gpio0 21 0>;
143 linux,default-trigger = "heartbeat";
144 };
145 };
146
147 backlight {
148 compatible = "pwm-backlight";
149
150 pwms = <&pwm 3 191000>;
151 brightness-levels = <0 4 8 16 32 64 128 255>;
152 default-brightness-level = <6>;
153 };
154};
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts
index c03a577beca3..1594694532b9 100644
--- a/arch/arm/boot/dts/imx28-cfa10036.dts
+++ b/arch/arm/boot/dts/imx28-cfa10036.dts
@@ -22,6 +22,31 @@
22 22
23 apb@80000000 { 23 apb@80000000 {
24 apbh@80000000 { 24 apbh@80000000 {
25 pinctrl@80018000 {
26 pinctrl-names = "default";
27 pinctrl-0 = <&hog_pins_cfa10036>;
28
29 hog_pins_cfa10036: hog-10036@0 {
30 reg = <0>;
31 fsl,pinmux-ids = <
32 0x2073 /* MX28_PAD_SSP0_D7__GPIO_2_7 */
33 >;
34 fsl,drive-strength = <0>;
35 fsl,voltage = <1>;
36 fsl,pull-up = <0>;
37 };
38
39 led_pins_cfa10036: leds-10036@0 {
40 reg = <0>;
41 fsl,pinmux-ids = <
42 0x3043 /* MX28_PAD_AUART1_RX__GPIO_3_4 */
43 >;
44 fsl,drive-strength = <0>;
45 fsl,voltage = <1>;
46 fsl,pull-up = <0>;
47 };
48 };
49
25 ssp0: ssp@80010000 { 50 ssp0: ssp@80010000 {
26 compatible = "fsl,imx28-mmc"; 51 compatible = "fsl,imx28-mmc";
27 pinctrl-names = "default"; 52 pinctrl-names = "default";
@@ -33,16 +58,37 @@
33 }; 58 };
34 59
35 apbx@80040000 { 60 apbx@80040000 {
61 pwm: pwm@80064000 {
62 pinctrl-names = "default";
63 pinctrl-0 = <&pwm4_pins_a>;
64 status = "okay";
65 };
66
36 duart: serial@80074000 { 67 duart: serial@80074000 {
37 pinctrl-names = "default"; 68 pinctrl-names = "default";
38 pinctrl-0 = <&duart_pins_b>; 69 pinctrl-0 = <&duart_pins_b>;
39 status = "okay"; 70 status = "okay";
40 }; 71 };
72
73 i2c0: i2c@80058000 {
74 pinctrl-names = "default";
75 pinctrl-0 = <&i2c0_pins_b>;
76 status = "okay";
77
78 ssd1307: oled@3c {
79 compatible = "solomon,ssd1307fb-i2c";
80 reg = <0x3c>;
81 pwms = <&pwm 4 3000>;
82 reset-gpios = <&gpio2 7 0>;
83 };
84 };
41 }; 85 };
42 }; 86 };
43 87
44 leds { 88 leds {
45 compatible = "gpio-leds"; 89 compatible = "gpio-leds";
90 pinctrl-names = "default";
91 pinctrl-0 = <&led_pins_cfa10036>;
46 92
47 power { 93 power {
48 gpios = <&gpio3 4 1>; 94 gpios = <&gpio3 4 1>;
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
index 05c892e931e3..bdc80a4453dd 100644
--- a/arch/arm/boot/dts/imx28-cfa10049.dts
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -22,6 +22,22 @@
22 apb@80000000 { 22 apb@80000000 {
23 apbh@80000000 { 23 apbh@80000000 {
24 pinctrl@80018000 { 24 pinctrl@80018000 {
25 pinctrl-names = "default", "default";
26 pinctrl-1 = <&hog_pins_cfa10049>;
27
28 hog_pins_cfa10049: hog-10049@0 {
29 reg = <0>;
30 fsl,pinmux-ids = <
31 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */
32 0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */
33 0x1173 /* MX28_PAD_LCD_D22__GPIO_1_23 */
34 0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */
35 >;
36 fsl,drive-strength = <0>;
37 fsl,voltage = <1>;
38 fsl,pull-up = <0>;
39 };
40
25 spi3_pins_cfa10049: spi3-cfa10049@0 { 41 spi3_pins_cfa10049: spi3-cfa10049@0 {
26 reg = <0>; 42 reg = <0>;
27 fsl,pinmux-ids = < 43 fsl,pinmux-ids = <
@@ -29,6 +45,7 @@
29 0x01c1 /* MX28_PAD_GPMI_RESETN__SSP3_CMD */ 45 0x01c1 /* MX28_PAD_GPMI_RESETN__SSP3_CMD */
30 0x0111 /* MX28_PAD_GPMI_CE1N__SSP3_D3 */ 46 0x0111 /* MX28_PAD_GPMI_CE1N__SSP3_D3 */
31 0x01a2 /* MX28_PAD_GPMI_ALE__SSP3_D4 */ 47 0x01a2 /* MX28_PAD_GPMI_ALE__SSP3_D4 */
48 0x01b2 /* MX28_PAD_GPMI_CLE__SSP3_D5 */
32 >; 49 >;
33 fsl,drive-strength = <1>; 50 fsl,drive-strength = <1>;
34 fsl,voltage = <1>; 51 fsl,voltage = <1>;
@@ -60,6 +77,11 @@
60 spi-max-frequency = <100000>; 77 spi-max-frequency = <100000>;
61 }; 78 };
62 79
80 dac0: dh2228@2 {
81 compatible = "rohm,dh2228fv";
82 reg = <2>;
83 spi-max-frequency = <100000>;
84 };
63 }; 85 };
64 }; 86 };
65 87
@@ -70,6 +92,30 @@
70 status = "okay"; 92 status = "okay";
71 }; 93 };
72 94
95 i2cmux {
96 compatible = "i2c-mux-gpio";
97 #address-cells = <1>;
98 #size-cells = <0>;
99 mux-gpios = <&gpio1 22 0 &gpio1 23 0>;
100 i2c-parent = <&i2c1>;
101
102 i2c@0 {
103 reg = <0>;
104 };
105
106 i2c@1 {
107 reg = <1>;
108 };
109
110 i2c@2 {
111 reg = <2>;
112 };
113
114 i2c@3 {
115 reg = <3>;
116 };
117 };
118
73 usbphy1: usbphy@8007e000 { 119 usbphy1: usbphy@8007e000 {
74 status = "okay"; 120 status = "okay";
75 }; 121 };
@@ -96,4 +142,15 @@
96 gpio = <&gpio0 7 1>; 142 gpio = <&gpio0 7 1>;
97 }; 143 };
98 }; 144 };
145
146 ahb@80080000 {
147 mac0: ethernet@800f0000 {
148 phy-mode = "rmii";
149 pinctrl-names = "default";
150 pinctrl-0 = <&mac0_pins_a>;
151 phy-reset-gpios = <&gpio2 21 0>;
152 phy-reset-duration = <100>;
153 status = "okay";
154 };
155 };
99}; 156};
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index a0ad71ca3a44..2da316e04409 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -76,7 +76,6 @@
76 0x20c3 /* MX28_PAD_SSP1_SCK__GPIO_2_12 */ 76 0x20c3 /* MX28_PAD_SSP1_SCK__GPIO_2_12 */
77 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ 77 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */
78 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ 78 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */
79 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
80 0x3083 /* MX28_PAD_AUART2_RX__GPIO_3_8 */ 79 0x3083 /* MX28_PAD_AUART2_RX__GPIO_3_8 */
81 0x3093 /* MX28_PAD_AUART2_TX__GPIO_3_9 */ 80 0x3093 /* MX28_PAD_AUART2_TX__GPIO_3_9 */
82 >; 81 >;
@@ -85,6 +84,16 @@
85 fsl,pull-up = <0>; 84 fsl,pull-up = <0>;
86 }; 85 };
87 86
87 led_pin_gpio3_5: led_gpio3_5@0 {
88 reg = <0>;
89 fsl,pinmux-ids = <
90 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
91 >;
92 fsl,drive-strength = <0>;
93 fsl,voltage = <1>;
94 fsl,pull-up = <0>;
95 };
96
88 gpmi_pins_evk: gpmi-nand-evk@0 { 97 gpmi_pins_evk: gpmi-nand-evk@0 {
89 reg = <0>; 98 reg = <0>;
90 fsl,pinmux-ids = < 99 fsl,pinmux-ids = <
@@ -288,6 +297,8 @@
288 297
289 leds { 298 leds {
290 compatible = "gpio-leds"; 299 compatible = "gpio-leds";
300 pinctrl-names = "default";
301 pinctrl-0 = <&led_pin_gpio3_5>;
291 302
292 user { 303 user {
293 label = "Heartbeat"; 304 label = "Heartbeat";
diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/imx28-sps1.dts
new file mode 100644
index 000000000000..e6cde8aa7fff
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-sps1.dts
@@ -0,0 +1,169 @@
1/*
2 * Copyright (C) 2012 Marek Vasut <marex@denx.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx28.dtsi"
14
15/ {
16 model = "SchulerControl GmbH, SC SPS 1";
17 compatible = "schulercontrol,imx28-sps1", "fsl,imx28";
18
19 memory {
20 reg = <0x40000000 0x08000000>;
21 };
22
23 apb@80000000 {
24 apbh@80000000 {
25 pinctrl@80018000 {
26 pinctrl-names = "default";
27 pinctrl-0 = <&hog_pins_a>;
28
29 hog_pins_a: hog-gpios@0 {
30 reg = <0>;
31 fsl,pinmux-ids = <
32 0x0003 /* MX28_PAD_GPMI_D00__GPIO_0_0 */
33 0x0033 /* MX28_PAD_GPMI_D03__GPIO_0_3 */
34 0x0063 /* MX28_PAD_GPMI_D06__GPIO_0_6 */
35 >;
36 fsl,drive-strength = <0>;
37 fsl,voltage = <1>;
38 fsl,pull-up = <0>;
39 };
40
41 };
42
43 ssp0: ssp@80010000 {
44 compatible = "fsl,imx28-mmc";
45 pinctrl-names = "default";
46 pinctrl-0 = <&mmc0_4bit_pins_a>;
47 bus-width = <4>;
48 status = "okay";
49 };
50
51 ssp2: ssp@80014000 {
52 #address-cells = <1>;
53 #size-cells = <0>;
54 compatible = "fsl,imx28-spi";
55 pinctrl-names = "default";
56 pinctrl-0 = <&spi2_pins_a>;
57 status = "okay";
58
59 flash: m25p80@0 {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 compatible = "everspin,mr25h256", "mr25h256";
63 spi-max-frequency = <40000000>;
64 reg = <0>;
65 };
66 };
67 };
68
69 apbx@80040000 {
70 i2c0: i2c@80058000 {
71 pinctrl-names = "default";
72 pinctrl-0 = <&i2c0_pins_a>;
73 clock-frequency = <400000>;
74 status = "okay";
75
76 rtc: rtc@51 {
77 compatible = "nxp,pcf8563";
78 reg = <0x51>;
79 };
80
81 eeprom: eeprom@52 {
82 compatible = "atmel,24c64";
83 reg = <0x52>;
84 pagesize = <32>;
85 };
86 };
87
88 duart: serial@80074000 {
89 pinctrl-names = "default";
90 pinctrl-0 = <&duart_pins_a>;
91 status = "okay";
92 };
93
94 usbphy0: usbphy@8007c000 {
95 status = "okay";
96 };
97
98 auart0: serial@8006a000 {
99 pinctrl-names = "default";
100 pinctrl-0 = <&auart0_pins_a>;
101 status = "okay";
102 };
103 };
104 };
105
106 ahb@80080000 {
107 usb0: usb@80080000 {
108 vbus-supply = <&reg_usb0_vbus>;
109 pinctrl-names = "default";
110 pinctrl-0 = <&usbphy0_pins_b>;
111 status = "okay";
112 };
113
114 mac0: ethernet@800f0000 {
115 phy-mode = "rmii";
116 pinctrl-names = "default";
117 pinctrl-0 = <&mac0_pins_a>;
118 status = "okay";
119 };
120
121 mac1: ethernet@800f4000 {
122 phy-mode = "rmii";
123 pinctrl-names = "default";
124 pinctrl-0 = <&mac1_pins_a>;
125 status = "okay";
126 };
127 };
128
129 regulators {
130 compatible = "simple-bus";
131
132 reg_usb0_vbus: usb0_vbus {
133 compatible = "regulator-fixed";
134 regulator-name = "usb0_vbus";
135 regulator-min-microvolt = <5000000>;
136 regulator-max-microvolt = <5000000>;
137 gpio = <&gpio3 9 0>;
138 };
139 };
140
141 leds {
142 #address-cells = <1>;
143 #size-cells = <0>;
144 compatible = "gpio-leds";
145 status = "okay";
146
147 led@1 {
148 label = "sps1-1:yellow:user";
149 gpios = <&gpio0 6 0>;
150 linux,default-trigger = "heartbeat";
151 reg = <0>;
152 };
153
154 led@2 {
155 label = "sps1-2:red:user";
156 gpios = <&gpio0 3 0>;
157 linux,default-trigger = "heartbeat";
158 reg = <1>;
159 };
160
161 led@3 {
162 label = "sps1-3:red:user";
163 gpios = <&gpio0 0 0>;
164 default-trigger = "heartbeat";
165 reg = <2>;
166 };
167
168 };
169};
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 55c57ea6169e..13b7053d799e 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -492,6 +492,16 @@
492 fsl,pull-up = <0>; 492 fsl,pull-up = <0>;
493 }; 493 };
494 494
495 pwm3_pins_a: pwm3@0 {
496 reg = <0>;
497 fsl,pinmux-ids = <
498 0x31c0 /* MX28_PAD_PWM3__PWM_3 */
499 >;
500 fsl,drive-strength = <0>;
501 fsl,voltage = <1>;
502 fsl,pull-up = <0>;
503 };
504
495 pwm4_pins_a: pwm4@0 { 505 pwm4_pins_a: pwm4@0 {
496 reg = <0>; 506 reg = <0>;
497 fsl,pinmux-ids = < 507 fsl,pinmux-ids = <
@@ -535,6 +545,31 @@
535 fsl,pull-up = <0>; 545 fsl,pull-up = <0>;
536 }; 546 };
537 547
548 lcdif_16bit_pins_a: lcdif-16bit@0 {
549 reg = <0>;
550 fsl,pinmux-ids = <
551 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
552 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
553 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
554 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
555 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
556 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
557 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
558 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
559 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
560 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
561 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
562 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
563 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
564 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
565 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
566 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
567 >;
568 fsl,drive-strength = <0>;
569 fsl,voltage = <1>;
570 fsl,pull-up = <0>;
571 };
572
538 can0_pins_a: can0@0 { 573 can0_pins_a: can0@0 {
539 reg = <0>; 574 reg = <0>;
540 fsl,pinmux-ids = < 575 fsl,pinmux-ids = <
@@ -799,6 +834,7 @@
799 compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 834 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
800 reg = <0x8006a000 0x2000>; 835 reg = <0x8006a000 0x2000>;
801 interrupts = <112 70 71>; 836 interrupts = <112 70 71>;
837 fsl,auart-dma-channel = <8 9>;
802 clocks = <&clks 45>; 838 clocks = <&clks 45>;
803 status = "disabled"; 839 status = "disabled";
804 }; 840 };
diff --git a/arch/arm/boot/dts/imx31-bug.dts b/arch/arm/boot/dts/imx31-bug.dts
index 24731cb78e8e..7f67402328d3 100644
--- a/arch/arm/boot/dts/imx31-bug.dts
+++ b/arch/arm/boot/dts/imx31-bug.dts
@@ -14,7 +14,7 @@
14 14
15/ { 15/ {
16 model = "Buglabs i.MX31 Bug 1.x"; 16 model = "Buglabs i.MX31 Bug 1.x";
17 compatible = "fsl,imx31-bug", "fsl,imx31"; 17 compatible = "buglabs,imx31-bug", "fsl,imx31";
18 18
19 memory { 19 memory {
20 reg = <0x80000000 0x8000000>; /* 128M */ 20 reg = <0x80000000 0x8000000>; /* 128M */
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index cbd2b1c7487b..567e7ee72f91 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -22,6 +22,22 @@
22 }; 22 };
23 23
24 soc { 24 soc {
25 display@di0 {
26 compatible = "fsl,imx-parallel-display";
27 crtcs = <&ipu 0>;
28 interface-pix-fmt = "rgb24";
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_ipu_disp1_1>;
31 };
32
33 display@di1 {
34 compatible = "fsl,imx-parallel-display";
35 crtcs = <&ipu 1>;
36 interface-pix-fmt = "rgb565";
37 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_ipu_disp2_1>;
39 };
40
25 aips@70000000 { /* aips-1 */ 41 aips@70000000 { /* aips-1 */
26 spba@70000000 { 42 spba@70000000 {
27 esdhc@70004000 { /* ESDHC1 */ 43 esdhc@70004000 { /* ESDHC1 */
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 75d069fcf897..1f5d45eff45e 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -62,6 +62,13 @@
62 interrupt-parent = <&tzic>; 62 interrupt-parent = <&tzic>;
63 ranges; 63 ranges;
64 64
65 ipu: ipu@40000000 {
66 #crtc-cells = <1>;
67 compatible = "fsl,imx51-ipu";
68 reg = <0x40000000 0x20000000>;
69 interrupts = <11 10>;
70 };
71
65 aips@70000000 { /* AIPS1 */ 72 aips@70000000 { /* AIPS1 */
66 compatible = "fsl,aips-bus", "simple-bus"; 73 compatible = "fsl,aips-bus", "simple-bus";
67 #address-cells = <1>; 74 #address-cells = <1>;
@@ -76,17 +83,22 @@
76 reg = <0x70000000 0x40000>; 83 reg = <0x70000000 0x40000>;
77 ranges; 84 ranges;
78 85
79 esdhc@70004000 { /* ESDHC1 */ 86 esdhc1: esdhc@70004000 {
80 compatible = "fsl,imx51-esdhc"; 87 compatible = "fsl,imx51-esdhc";
81 reg = <0x70004000 0x4000>; 88 reg = <0x70004000 0x4000>;
82 interrupts = <1>; 89 interrupts = <1>;
90 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
91 clock-names = "ipg", "ahb", "per";
83 status = "disabled"; 92 status = "disabled";
84 }; 93 };
85 94
86 esdhc@70008000 { /* ESDHC2 */ 95 esdhc2: esdhc@70008000 {
87 compatible = "fsl,imx51-esdhc"; 96 compatible = "fsl,imx51-esdhc";
88 reg = <0x70008000 0x4000>; 97 reg = <0x70008000 0x4000>;
89 interrupts = <2>; 98 interrupts = <2>;
99 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
100 clock-names = "ipg", "ahb", "per";
101 bus-width = <4>;
90 status = "disabled"; 102 status = "disabled";
91 }; 103 };
92 104
@@ -94,15 +106,19 @@
94 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 106 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
95 reg = <0x7000c000 0x4000>; 107 reg = <0x7000c000 0x4000>;
96 interrupts = <33>; 108 interrupts = <33>;
109 clocks = <&clks 32>, <&clks 33>;
110 clock-names = "ipg", "per";
97 status = "disabled"; 111 status = "disabled";
98 }; 112 };
99 113
100 ecspi@70010000 { /* ECSPI1 */ 114 ecspi1: ecspi@70010000 {
101 #address-cells = <1>; 115 #address-cells = <1>;
102 #size-cells = <0>; 116 #size-cells = <0>;
103 compatible = "fsl,imx51-ecspi"; 117 compatible = "fsl,imx51-ecspi";
104 reg = <0x70010000 0x4000>; 118 reg = <0x70010000 0x4000>;
105 interrupts = <36>; 119 interrupts = <36>;
120 clocks = <&clks 51>, <&clks 52>;
121 clock-names = "ipg", "per";
106 status = "disabled"; 122 status = "disabled";
107 }; 123 };
108 124
@@ -110,48 +126,55 @@
110 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 126 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
111 reg = <0x70014000 0x4000>; 127 reg = <0x70014000 0x4000>;
112 interrupts = <30>; 128 interrupts = <30>;
129 clocks = <&clks 49>;
113 fsl,fifo-depth = <15>; 130 fsl,fifo-depth = <15>;
114 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ 131 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
115 status = "disabled"; 132 status = "disabled";
116 }; 133 };
117 134
118 esdhc@70020000 { /* ESDHC3 */ 135 esdhc3: esdhc@70020000 {
119 compatible = "fsl,imx51-esdhc"; 136 compatible = "fsl,imx51-esdhc";
120 reg = <0x70020000 0x4000>; 137 reg = <0x70020000 0x4000>;
121 interrupts = <3>; 138 interrupts = <3>;
139 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
140 clock-names = "ipg", "ahb", "per";
141 bus-width = <4>;
122 status = "disabled"; 142 status = "disabled";
123 }; 143 };
124 144
125 esdhc@70024000 { /* ESDHC4 */ 145 esdhc4: esdhc@70024000 {
126 compatible = "fsl,imx51-esdhc"; 146 compatible = "fsl,imx51-esdhc";
127 reg = <0x70024000 0x4000>; 147 reg = <0x70024000 0x4000>;
128 interrupts = <4>; 148 interrupts = <4>;
149 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
150 clock-names = "ipg", "ahb", "per";
151 bus-width = <4>;
129 status = "disabled"; 152 status = "disabled";
130 }; 153 };
131 }; 154 };
132 155
133 usb@73f80000 { 156 usbotg: usb@73f80000 {
134 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 157 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
135 reg = <0x73f80000 0x0200>; 158 reg = <0x73f80000 0x0200>;
136 interrupts = <18>; 159 interrupts = <18>;
137 status = "disabled"; 160 status = "disabled";
138 }; 161 };
139 162
140 usb@73f80200 { 163 usbh1: usb@73f80200 {
141 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 164 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
142 reg = <0x73f80200 0x0200>; 165 reg = <0x73f80200 0x0200>;
143 interrupts = <14>; 166 interrupts = <14>;
144 status = "disabled"; 167 status = "disabled";
145 }; 168 };
146 169
147 usb@73f80400 { 170 usbh2: usb@73f80400 {
148 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 171 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
149 reg = <0x73f80400 0x0200>; 172 reg = <0x73f80400 0x0200>;
150 interrupts = <16>; 173 interrupts = <16>;
151 status = "disabled"; 174 status = "disabled";
152 }; 175 };
153 176
154 usb@73f80600 { 177 usbh3: usb@73f80600 {
155 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 178 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
156 reg = <0x73f80600 0x0200>; 179 reg = <0x73f80600 0x0200>;
157 interrupts = <17>; 180 interrupts = <17>;
@@ -198,20 +221,22 @@
198 #interrupt-cells = <2>; 221 #interrupt-cells = <2>;
199 }; 222 };
200 223
201 wdog@73f98000 { /* WDOG1 */ 224 wdog1: wdog@73f98000 {
202 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 225 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
203 reg = <0x73f98000 0x4000>; 226 reg = <0x73f98000 0x4000>;
204 interrupts = <58>; 227 interrupts = <58>;
228 clocks = <&clks 0>;
205 }; 229 };
206 230
207 wdog@73f9c000 { /* WDOG2 */ 231 wdog2: wdog@73f9c000 {
208 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 232 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
209 reg = <0x73f9c000 0x4000>; 233 reg = <0x73f9c000 0x4000>;
210 interrupts = <59>; 234 interrupts = <59>;
235 clocks = <&clks 0>;
211 status = "disabled"; 236 status = "disabled";
212 }; 237 };
213 238
214 iomuxc@73fa8000 { 239 iomuxc: iomuxc@73fa8000 {
215 compatible = "fsl,imx51-iomuxc"; 240 compatible = "fsl,imx51-iomuxc";
216 reg = <0x73fa8000 0x4000>; 241 reg = <0x73fa8000 0x4000>;
217 242
@@ -295,6 +320,66 @@
295 }; 320 };
296 }; 321 };
297 322
323 ipu_disp1 {
324 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
325 fsl,pins = <
326 528 0x5 /* MX51_PAD_DISP1_DAT0__DISP1_DAT0 */
327 529 0x5 /* MX51_PAD_DISP1_DAT1__DISP1_DAT1 */
328 530 0x5 /* MX51_PAD_DISP1_DAT2__DISP1_DAT2 */
329 531 0x5 /* MX51_PAD_DISP1_DAT3__DISP1_DAT3 */
330 532 0x5 /* MX51_PAD_DISP1_DAT4__DISP1_DAT4 */
331 533 0x5 /* MX51_PAD_DISP1_DAT5__DISP1_DAT5 */
332 535 0x5 /* MX51_PAD_DISP1_DAT6__DISP1_DAT6 */
333 537 0x5 /* MX51_PAD_DISP1_DAT7__DISP1_DAT7 */
334 539 0x5 /* MX51_PAD_DISP1_DAT8__DISP1_DAT8 */
335 541 0x5 /* MX51_PAD_DISP1_DAT9__DISP1_DAT9 */
336 543 0x5 /* MX51_PAD_DISP1_DAT10__DISP1_DAT10 */
337 545 0x5 /* MX51_PAD_DISP1_DAT11__DISP1_DAT11 */
338 547 0x5 /* MX51_PAD_DISP1_DAT12__DISP1_DAT12 */
339 549 0x5 /* MX51_PAD_DISP1_DAT13__DISP1_DAT13 */
340 551 0x5 /* MX51_PAD_DISP1_DAT14__DISP1_DAT14 */
341 553 0x5 /* MX51_PAD_DISP1_DAT15__DISP1_DAT15 */
342 555 0x5 /* MX51_PAD_DISP1_DAT16__DISP1_DAT16 */
343 557 0x5 /* MX51_PAD_DISP1_DAT17__DISP1_DAT17 */
344 559 0x5 /* MX51_PAD_DISP1_DAT18__DISP1_DAT18 */
345 563 0x5 /* MX51_PAD_DISP1_DAT19__DISP1_DAT19 */
346 567 0x5 /* MX51_PAD_DISP1_DAT20__DISP1_DAT20 */
347 571 0x5 /* MX51_PAD_DISP1_DAT21__DISP1_DAT21 */
348 575 0x5 /* MX51_PAD_DISP1_DAT22__DISP1_DAT22 */
349 579 0x5 /* MX51_PAD_DISP1_DAT23__DISP1_DAT23 */
350 584 0x5 /* MX51_PAD_DI1_PIN2__DI1_PIN2 (hsync) */
351 583 0x5 /* MX51_PAD_DI1_PIN3__DI1_PIN3 (vsync) */
352 >;
353 };
354 };
355
356 ipu_disp2 {
357 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
358 fsl,pins = <
359 603 0x5 /* MX51_PAD_DISP2_DAT0__DISP2_DAT0 */
360 608 0x5 /* MX51_PAD_DISP2_DAT1__DISP2_DAT1 */
361 613 0x5 /* MX51_PAD_DISP2_DAT2__DISP2_DAT2 */
362 614 0x5 /* MX51_PAD_DISP2_DAT3__DISP2_DAT3 */
363 615 0x5 /* MX51_PAD_DISP2_DAT4__DISP2_DAT4 */
364 616 0x5 /* MX51_PAD_DISP2_DAT5__DISP2_DAT5 */
365 617 0x5 /* MX51_PAD_DISP2_DAT6__DISP2_DAT6 */
366 622 0x5 /* MX51_PAD_DISP2_DAT7__DISP2_DAT7 */
367 627 0x5 /* MX51_PAD_DISP2_DAT8__DISP2_DAT8 */
368 633 0x5 /* MX51_PAD_DISP2_DAT9__DISP2_DAT9 */
369 637 0x5 /* MX51_PAD_DISP2_DAT10__DISP2_DAT10 */
370 643 0x5 /* MX51_PAD_DISP2_DAT11__DISP2_DAT11 */
371 648 0x5 /* MX51_PAD_DISP2_DAT12__DISP2_DAT12 */
372 652 0x5 /* MX51_PAD_DISP2_DAT13__DISP2_DAT13 */
373 656 0x5 /* MX51_PAD_DISP2_DAT14__DISP2_DAT14 */
374 661 0x5 /* MX51_PAD_DISP2_DAT15__DISP2_DAT15 */
375 593 0x5 /* MX51_PAD_DI2_PIN2__DI2_PIN2 (hsync) */
376 595 0x5 /* MX51_PAD_DI2_PIN3__DI2_PIN3 (vsync) */
377 597 0x5 /* MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK */
378 599 0x5 /* MX51_PAD_DI_GP4__DI2_PIN15 */
379 >;
380 };
381 };
382
298 uart1 { 383 uart1 {
299 pinctrl_uart1_1: uart1grp-1 { 384 pinctrl_uart1_1: uart1grp-1 {
300 fsl,pins = < 385 fsl,pins = <
@@ -327,10 +412,30 @@
327 }; 412 };
328 }; 413 };
329 414
415 pwm1: pwm@73fb4000 {
416 #pwm-cells = <2>;
417 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
418 reg = <0x73fb4000 0x4000>;
419 clocks = <&clks 37>, <&clks 38>;
420 clock-names = "ipg", "per";
421 interrupts = <61>;
422 };
423
424 pwm2: pwm@73fb8000 {
425 #pwm-cells = <2>;
426 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
427 reg = <0x73fb8000 0x4000>;
428 clocks = <&clks 39>, <&clks 40>;
429 clock-names = "ipg", "per";
430 interrupts = <94>;
431 };
432
330 uart1: serial@73fbc000 { 433 uart1: serial@73fbc000 {
331 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 434 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
332 reg = <0x73fbc000 0x4000>; 435 reg = <0x73fbc000 0x4000>;
333 interrupts = <31>; 436 interrupts = <31>;
437 clocks = <&clks 28>, <&clks 29>;
438 clock-names = "ipg", "per";
334 status = "disabled"; 439 status = "disabled";
335 }; 440 };
336 441
@@ -338,8 +443,17 @@
338 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 443 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
339 reg = <0x73fc0000 0x4000>; 444 reg = <0x73fc0000 0x4000>;
340 interrupts = <32>; 445 interrupts = <32>;
446 clocks = <&clks 30>, <&clks 31>;
447 clock-names = "ipg", "per";
341 status = "disabled"; 448 status = "disabled";
342 }; 449 };
450
451 clks: ccm@73fd4000{
452 compatible = "fsl,imx51-ccm";
453 reg = <0x73fd4000 0x4000>;
454 interrupts = <0 71 0x04 0 72 0x04>;
455 #clock-cells = <1>;
456 };
343 }; 457 };
344 458
345 aips@80000000 { /* AIPS2 */ 459 aips@80000000 { /* AIPS2 */
@@ -349,46 +463,54 @@
349 reg = <0x80000000 0x10000000>; 463 reg = <0x80000000 0x10000000>;
350 ranges; 464 ranges;
351 465
352 ecspi@83fac000 { /* ECSPI2 */ 466 ecspi2: ecspi@83fac000 {
353 #address-cells = <1>; 467 #address-cells = <1>;
354 #size-cells = <0>; 468 #size-cells = <0>;
355 compatible = "fsl,imx51-ecspi"; 469 compatible = "fsl,imx51-ecspi";
356 reg = <0x83fac000 0x4000>; 470 reg = <0x83fac000 0x4000>;
357 interrupts = <37>; 471 interrupts = <37>;
472 clocks = <&clks 53>, <&clks 54>;
473 clock-names = "ipg", "per";
358 status = "disabled"; 474 status = "disabled";
359 }; 475 };
360 476
361 sdma@83fb0000 { 477 sdma: sdma@83fb0000 {
362 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; 478 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
363 reg = <0x83fb0000 0x4000>; 479 reg = <0x83fb0000 0x4000>;
364 interrupts = <6>; 480 interrupts = <6>;
481 clocks = <&clks 56>, <&clks 56>;
482 clock-names = "ipg", "ahb";
365 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; 483 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
366 }; 484 };
367 485
368 cspi@83fc0000 { 486 cspi: cspi@83fc0000 {
369 #address-cells = <1>; 487 #address-cells = <1>;
370 #size-cells = <0>; 488 #size-cells = <0>;
371 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; 489 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
372 reg = <0x83fc0000 0x4000>; 490 reg = <0x83fc0000 0x4000>;
373 interrupts = <38>; 491 interrupts = <38>;
492 clocks = <&clks 55>, <&clks 0>;
493 clock-names = "ipg", "per";
374 status = "disabled"; 494 status = "disabled";
375 }; 495 };
376 496
377 i2c@83fc4000 { /* I2C2 */ 497 i2c2: i2c@83fc4000 {
378 #address-cells = <1>; 498 #address-cells = <1>;
379 #size-cells = <0>; 499 #size-cells = <0>;
380 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c"; 500 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
381 reg = <0x83fc4000 0x4000>; 501 reg = <0x83fc4000 0x4000>;
382 interrupts = <63>; 502 interrupts = <63>;
503 clocks = <&clks 35>;
383 status = "disabled"; 504 status = "disabled";
384 }; 505 };
385 506
386 i2c@83fc8000 { /* I2C1 */ 507 i2c1: i2c@83fc8000 {
387 #address-cells = <1>; 508 #address-cells = <1>;
388 #size-cells = <0>; 509 #size-cells = <0>;
389 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c"; 510 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
390 reg = <0x83fc8000 0x4000>; 511 reg = <0x83fc8000 0x4000>;
391 interrupts = <62>; 512 interrupts = <62>;
513 clocks = <&clks 34>;
392 status = "disabled"; 514 status = "disabled";
393 }; 515 };
394 516
@@ -396,21 +518,23 @@
396 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 518 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
397 reg = <0x83fcc000 0x4000>; 519 reg = <0x83fcc000 0x4000>;
398 interrupts = <29>; 520 interrupts = <29>;
521 clocks = <&clks 48>;
399 fsl,fifo-depth = <15>; 522 fsl,fifo-depth = <15>;
400 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ 523 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
401 status = "disabled"; 524 status = "disabled";
402 }; 525 };
403 526
404 audmux@83fd0000 { 527 audmux: audmux@83fd0000 {
405 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux"; 528 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
406 reg = <0x83fd0000 0x4000>; 529 reg = <0x83fd0000 0x4000>;
407 status = "disabled"; 530 status = "disabled";
408 }; 531 };
409 532
410 nand@83fdb000 { 533 nfc: nand@83fdb000 {
411 compatible = "fsl,imx51-nand"; 534 compatible = "fsl,imx51-nand";
412 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; 535 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
413 interrupts = <8>; 536 interrupts = <8>;
537 clocks = <&clks 60>;
414 status = "disabled"; 538 status = "disabled";
415 }; 539 };
416 540
@@ -418,15 +542,18 @@
418 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 542 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
419 reg = <0x83fe8000 0x4000>; 543 reg = <0x83fe8000 0x4000>;
420 interrupts = <96>; 544 interrupts = <96>;
545 clocks = <&clks 50>;
421 fsl,fifo-depth = <15>; 546 fsl,fifo-depth = <15>;
422 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */ 547 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
423 status = "disabled"; 548 status = "disabled";
424 }; 549 };
425 550
426 ethernet@83fec000 { 551 fec: ethernet@83fec000 {
427 compatible = "fsl,imx51-fec", "fsl,imx27-fec"; 552 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
428 reg = <0x83fec000 0x4000>; 553 reg = <0x83fec000 0x4000>;
429 interrupts = <87>; 554 interrupts = <87>;
555 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
556 clock-names = "ipg", "ahb", "ptp";
430 status = "disabled"; 557 status = "disabled";
431 }; 558 };
432 }; 559 };
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index 08948af86d1a..b0075537195b 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -60,10 +60,17 @@
60 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */ 60 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
61 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */ 61 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
62 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */ 62 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
63 1149 0x80000000 /* MX53_PAD_GPIO_16__GPIO7_11 */
64 >;
65 };
66
67 led_pin_gpio7_7: led_gpio7_7@0 {
68 fsl,pins = <
63 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */ 69 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
64 >; 70 >;
65 }; 71 };
66 }; 72 };
73
67 }; 74 };
68 75
69 uart1: serial@53fbc000 { 76 uart1: serial@53fbc000 {
@@ -100,76 +107,93 @@
100 pmic: dialog@48 { 107 pmic: dialog@48 {
101 compatible = "dlg,da9053-aa", "dlg,da9052"; 108 compatible = "dlg,da9053-aa", "dlg,da9052";
102 reg = <0x48>; 109 reg = <0x48>;
110 interrupt-parent = <&gpio7>;
111 interrupts = <11 0x8>; /* low-level active IRQ at GPIO7_11 */
103 112
104 regulators { 113 regulators {
105 buck0 { 114 buck1_reg: buck1 {
106 regulator-min-microvolt = <500000>; 115 regulator-min-microvolt = <500000>;
107 regulator-max-microvolt = <2075000>; 116 regulator-max-microvolt = <2075000>;
117 regulator-always-on;
108 }; 118 };
109 119
110 buck1 { 120 buck2_reg: buck2 {
111 regulator-min-microvolt = <500000>; 121 regulator-min-microvolt = <500000>;
112 regulator-max-microvolt = <2075000>; 122 regulator-max-microvolt = <2075000>;
123 regulator-always-on;
113 }; 124 };
114 125
115 buck2 { 126 buck3_reg: buck3 {
116 regulator-min-microvolt = <925000>; 127 regulator-min-microvolt = <925000>;
117 regulator-max-microvolt = <2500000>; 128 regulator-max-microvolt = <2500000>;
129 regulator-always-on;
118 }; 130 };
119 131
120 buck3 { 132 buck4_reg: buck4 {
121 regulator-min-microvolt = <925000>; 133 regulator-min-microvolt = <925000>;
122 regulator-max-microvolt = <2500000>; 134 regulator-max-microvolt = <2500000>;
135 regulator-always-on;
123 }; 136 };
124 137
125 ldo4 { 138 ldo1_reg: ldo1 {
126 regulator-min-microvolt = <600000>; 139 regulator-min-microvolt = <600000>;
127 regulator-max-microvolt = <1800000>; 140 regulator-max-microvolt = <1800000>;
141 regulator-boot-on;
142 regulator-always-on;
128 }; 143 };
129 144
130 ldo5 { 145 ldo2_reg: ldo2 {
146 regulator-min-microvolt = <600000>;
147 regulator-max-microvolt = <1800000>;
148 regulator-always-on;
149 };
150
151 ldo3_reg: ldo3 {
131 regulator-min-microvolt = <600000>; 152 regulator-min-microvolt = <600000>;
132 regulator-max-microvolt = <1800000>; 153 regulator-max-microvolt = <1800000>;
154 regulator-always-on;
133 }; 155 };
134 156
135 ldo6 { 157 ldo4_reg: ldo4 {
136 regulator-min-microvolt = <1725000>; 158 regulator-min-microvolt = <1725000>;
137 regulator-max-microvolt = <3300000>; 159 regulator-max-microvolt = <3300000>;
160 regulator-always-on;
138 }; 161 };
139 162
140 ldo7 { 163 ldo5_reg: ldo5 {
141 regulator-min-microvolt = <1725000>; 164 regulator-min-microvolt = <1725000>;
142 regulator-max-microvolt = <3300000>; 165 regulator-max-microvolt = <3300000>;
166 regulator-always-on;
143 }; 167 };
144 168
145 ldo8 { 169 ldo6_reg: ldo6 {
146 regulator-min-microvolt = <1200000>; 170 regulator-min-microvolt = <1200000>;
147 regulator-max-microvolt = <3600000>; 171 regulator-max-microvolt = <3600000>;
172 regulator-always-on;
148 }; 173 };
149 174
150 ldo9 { 175 ldo7_reg: ldo7 {
151 regulator-min-microvolt = <1200000>; 176 regulator-min-microvolt = <1200000>;
152 regulator-max-microvolt = <3600000>; 177 regulator-max-microvolt = <3600000>;
178 regulator-always-on;
153 }; 179 };
154 180
155 ldo10 { 181 ldo8_reg: ldo8 {
156 regulator-min-microvolt = <1200000>; 182 regulator-min-microvolt = <1200000>;
157 regulator-max-microvolt = <3600000>; 183 regulator-max-microvolt = <3600000>;
184 regulator-always-on;
158 }; 185 };
159 186
160 ldo11 { 187 ldo9_reg: ldo9 {
161 regulator-min-microvolt = <1200000>; 188 regulator-min-microvolt = <1200000>;
162 regulator-max-microvolt = <3600000>; 189 regulator-max-microvolt = <3600000>;
190 regulator-always-on;
163 }; 191 };
164 192
165 ldo12 { 193 ldo10_reg: ldo10 {
166 regulator-min-microvolt = <1250000>; 194 regulator-min-microvolt = <1250000>;
167 regulator-max-microvolt = <3650000>; 195 regulator-max-microvolt = <3650000>;
168 }; 196 regulator-always-on;
169
170 ldo13 {
171 regulator-min-microvolt = <1200000>;
172 regulator-max-microvolt = <3600000>;
173 }; 197 };
174 }; 198 };
175 }; 199 };
@@ -216,6 +240,8 @@
216 240
217 leds { 241 leds {
218 compatible = "gpio-leds"; 242 compatible = "gpio-leds";
243 pinctrl-names = "default";
244 pinctrl-0 = <&led_pin_gpio7_7>;
219 245
220 user { 246 user {
221 label = "Heartbeat"; 247 label = "Heartbeat";
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 76ebb1ad2675..edc3f1eb6699 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -67,6 +67,13 @@
67 interrupt-parent = <&tzic>; 67 interrupt-parent = <&tzic>;
68 ranges; 68 ranges;
69 69
70 ipu: ipu@18000000 {
71 #crtc-cells = <1>;
72 compatible = "fsl,imx53-ipu";
73 reg = <0x18000000 0x080000000>;
74 interrupts = <11 10>;
75 };
76
70 aips@50000000 { /* AIPS1 */ 77 aips@50000000 { /* AIPS1 */
71 compatible = "fsl,aips-bus", "simple-bus"; 78 compatible = "fsl,aips-bus", "simple-bus";
72 #address-cells = <1>; 79 #address-cells = <1>;
@@ -81,17 +88,23 @@
81 reg = <0x50000000 0x40000>; 88 reg = <0x50000000 0x40000>;
82 ranges; 89 ranges;
83 90
84 esdhc@50004000 { /* ESDHC1 */ 91 esdhc1: esdhc@50004000 {
85 compatible = "fsl,imx53-esdhc"; 92 compatible = "fsl,imx53-esdhc";
86 reg = <0x50004000 0x4000>; 93 reg = <0x50004000 0x4000>;
87 interrupts = <1>; 94 interrupts = <1>;
95 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
96 clock-names = "ipg", "ahb", "per";
97 bus-width = <4>;
88 status = "disabled"; 98 status = "disabled";
89 }; 99 };
90 100
91 esdhc@50008000 { /* ESDHC2 */ 101 esdhc2: esdhc@50008000 {
92 compatible = "fsl,imx53-esdhc"; 102 compatible = "fsl,imx53-esdhc";
93 reg = <0x50008000 0x4000>; 103 reg = <0x50008000 0x4000>;
94 interrupts = <2>; 104 interrupts = <2>;
105 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
106 clock-names = "ipg", "ahb", "per";
107 bus-width = <4>;
95 status = "disabled"; 108 status = "disabled";
96 }; 109 };
97 110
@@ -99,15 +112,19 @@
99 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 112 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
100 reg = <0x5000c000 0x4000>; 113 reg = <0x5000c000 0x4000>;
101 interrupts = <33>; 114 interrupts = <33>;
115 clocks = <&clks 32>, <&clks 33>;
116 clock-names = "ipg", "per";
102 status = "disabled"; 117 status = "disabled";
103 }; 118 };
104 119
105 ecspi@50010000 { /* ECSPI1 */ 120 ecspi1: ecspi@50010000 {
106 #address-cells = <1>; 121 #address-cells = <1>;
107 #size-cells = <0>; 122 #size-cells = <0>;
108 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; 123 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
109 reg = <0x50010000 0x4000>; 124 reg = <0x50010000 0x4000>;
110 interrupts = <36>; 125 interrupts = <36>;
126 clocks = <&clks 51>, <&clks 52>;
127 clock-names = "ipg", "per";
111 status = "disabled"; 128 status = "disabled";
112 }; 129 };
113 130
@@ -115,48 +132,55 @@
115 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; 132 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
116 reg = <0x50014000 0x4000>; 133 reg = <0x50014000 0x4000>;
117 interrupts = <30>; 134 interrupts = <30>;
135 clocks = <&clks 49>;
118 fsl,fifo-depth = <15>; 136 fsl,fifo-depth = <15>;
119 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ 137 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
120 status = "disabled"; 138 status = "disabled";
121 }; 139 };
122 140
123 esdhc@50020000 { /* ESDHC3 */ 141 esdhc3: esdhc@50020000 {
124 compatible = "fsl,imx53-esdhc"; 142 compatible = "fsl,imx53-esdhc";
125 reg = <0x50020000 0x4000>; 143 reg = <0x50020000 0x4000>;
126 interrupts = <3>; 144 interrupts = <3>;
145 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
146 clock-names = "ipg", "ahb", "per";
147 bus-width = <4>;
127 status = "disabled"; 148 status = "disabled";
128 }; 149 };
129 150
130 esdhc@50024000 { /* ESDHC4 */ 151 esdhc4: esdhc@50024000 {
131 compatible = "fsl,imx53-esdhc"; 152 compatible = "fsl,imx53-esdhc";
132 reg = <0x50024000 0x4000>; 153 reg = <0x50024000 0x4000>;
133 interrupts = <4>; 154 interrupts = <4>;
155 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
156 clock-names = "ipg", "ahb", "per";
157 bus-width = <4>;
134 status = "disabled"; 158 status = "disabled";
135 }; 159 };
136 }; 160 };
137 161
138 usb@53f80000 { 162 usbotg: usb@53f80000 {
139 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 163 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
140 reg = <0x53f80000 0x0200>; 164 reg = <0x53f80000 0x0200>;
141 interrupts = <18>; 165 interrupts = <18>;
142 status = "disabled"; 166 status = "disabled";
143 }; 167 };
144 168
145 usb@53f80200 { 169 usbh1: usb@53f80200 {
146 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 170 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
147 reg = <0x53f80200 0x0200>; 171 reg = <0x53f80200 0x0200>;
148 interrupts = <14>; 172 interrupts = <14>;
149 status = "disabled"; 173 status = "disabled";
150 }; 174 };
151 175
152 usb@53f80400 { 176 usbh2: usb@53f80400 {
153 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 177 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
154 reg = <0x53f80400 0x0200>; 178 reg = <0x53f80400 0x0200>;
155 interrupts = <16>; 179 interrupts = <16>;
156 status = "disabled"; 180 status = "disabled";
157 }; 181 };
158 182
159 usb@53f80600 { 183 usbh3: usb@53f80600 {
160 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 184 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
161 reg = <0x53f80600 0x0200>; 185 reg = <0x53f80600 0x0200>;
162 interrupts = <17>; 186 interrupts = <17>;
@@ -203,20 +227,22 @@
203 #interrupt-cells = <2>; 227 #interrupt-cells = <2>;
204 }; 228 };
205 229
206 wdog@53f98000 { /* WDOG1 */ 230 wdog1: wdog@53f98000 {
207 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; 231 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
208 reg = <0x53f98000 0x4000>; 232 reg = <0x53f98000 0x4000>;
209 interrupts = <58>; 233 interrupts = <58>;
234 clocks = <&clks 0>;
210 }; 235 };
211 236
212 wdog@53f9c000 { /* WDOG2 */ 237 wdog2: wdog@53f9c000 {
213 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; 238 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
214 reg = <0x53f9c000 0x4000>; 239 reg = <0x53f9c000 0x4000>;
215 interrupts = <59>; 240 interrupts = <59>;
241 clocks = <&clks 0>;
216 status = "disabled"; 242 status = "disabled";
217 }; 243 };
218 244
219 iomuxc@53fa8000 { 245 iomuxc: iomuxc@53fa8000 {
220 compatible = "fsl,imx53-iomuxc"; 246 compatible = "fsl,imx53-iomuxc";
221 reg = <0x53fa8000 0x4000>; 247 reg = <0x53fa8000 0x4000>;
222 248
@@ -316,6 +342,24 @@
316 }; 342 };
317 }; 343 };
318 344
345 can1 {
346 pinctrl_can1_1: can1grp-1 {
347 fsl,pins = <
348 847 0x80000000 /* MX53_PAD_PATA_INTRQ__CAN1_TXCAN */
349 853 0x80000000 /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */
350 >;
351 };
352 };
353
354 can2 {
355 pinctrl_can2_1: can2grp-1 {
356 fsl,pins = <
357 67 0x80000000 /* MX53_PAD_KEY_COL4__CAN2_TXCAN */
358 74 0x80000000 /* MX53_PAD_KEY_ROW4__CAN2_RXCAN */
359 >;
360 };
361 };
362
319 i2c1 { 363 i2c1 {
320 pinctrl_i2c1_1: i2c1grp-1 { 364 pinctrl_i2c1_1: i2c1grp-1 {
321 fsl,pins = < 365 fsl,pins = <
@@ -334,6 +378,15 @@
334 }; 378 };
335 }; 379 };
336 380
381 i2c3 {
382 pinctrl_i2c3_1: i2c3grp-1 {
383 fsl,pins = <
384 1102 0xc0000000 /* MX53_PAD_GPIO_6__I2C3_SDA */
385 1130 0xc0000000 /* MX53_PAD_GPIO_5__I2C3_SCL */
386 >;
387 };
388 };
389
337 uart1 { 390 uart1 {
338 pinctrl_uart1_1: uart1grp-1 { 391 pinctrl_uart1_1: uart1grp-1 {
339 fsl,pins = < 392 fsl,pins = <
@@ -369,12 +422,51 @@
369 >; 422 >;
370 }; 423 };
371 }; 424 };
425
426 uart4 {
427 pinctrl_uart4_1: uart4grp-1 {
428 fsl,pins = <
429 11 0x1c5 /* MX53_PAD_KEY_COL0__UART4_TXD_MUX */
430 18 0x1c5 /* MX53_PAD_KEY_ROW0__UART4_RXD_MUX */
431 >;
432 };
433 };
434
435 uart5 {
436 pinctrl_uart5_1: uart5grp-1 {
437 fsl,pins = <
438 24 0x1c5 /* MX53_PAD_KEY_COL1__UART5_TXD_MUX */
439 31 0x1c5 /* MX53_PAD_KEY_ROW1__UART5_RXD_MUX */
440 >;
441 };
442 };
443
444 };
445
446 pwm1: pwm@53fb4000 {
447 #pwm-cells = <2>;
448 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
449 reg = <0x53fb4000 0x4000>;
450 clocks = <&clks 37>, <&clks 38>;
451 clock-names = "ipg", "per";
452 interrupts = <61>;
453 };
454
455 pwm2: pwm@53fb8000 {
456 #pwm-cells = <2>;
457 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
458 reg = <0x53fb8000 0x4000>;
459 clocks = <&clks 39>, <&clks 40>;
460 clock-names = "ipg", "per";
461 interrupts = <94>;
372 }; 462 };
373 463
374 uart1: serial@53fbc000 { 464 uart1: serial@53fbc000 {
375 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 465 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
376 reg = <0x53fbc000 0x4000>; 466 reg = <0x53fbc000 0x4000>;
377 interrupts = <31>; 467 interrupts = <31>;
468 clocks = <&clks 28>, <&clks 29>;
469 clock-names = "ipg", "per";
378 status = "disabled"; 470 status = "disabled";
379 }; 471 };
380 472
@@ -382,6 +474,8 @@
382 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 474 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
383 reg = <0x53fc0000 0x4000>; 475 reg = <0x53fc0000 0x4000>;
384 interrupts = <32>; 476 interrupts = <32>;
477 clocks = <&clks 30>, <&clks 31>;
478 clock-names = "ipg", "per";
385 status = "disabled"; 479 status = "disabled";
386 }; 480 };
387 481
@@ -389,6 +483,8 @@
389 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; 483 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
390 reg = <0x53fc8000 0x4000>; 484 reg = <0x53fc8000 0x4000>;
391 interrupts = <82>; 485 interrupts = <82>;
486 clocks = <&clks 158>, <&clks 157>;
487 clock-names = "ipg", "per";
392 status = "disabled"; 488 status = "disabled";
393 }; 489 };
394 490
@@ -396,9 +492,18 @@
396 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; 492 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
397 reg = <0x53fcc000 0x4000>; 493 reg = <0x53fcc000 0x4000>;
398 interrupts = <83>; 494 interrupts = <83>;
495 clocks = <&clks 87>, <&clks 86>;
496 clock-names = "ipg", "per";
399 status = "disabled"; 497 status = "disabled";
400 }; 498 };
401 499
500 clks: ccm@53fd4000{
501 compatible = "fsl,imx53-ccm";
502 reg = <0x53fd4000 0x4000>;
503 interrupts = <0 71 0x04 0 72 0x04>;
504 #clock-cells = <1>;
505 };
506
402 gpio5: gpio@53fdc000 { 507 gpio5: gpio@53fdc000 {
403 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 508 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
404 reg = <0x53fdc000 0x4000>; 509 reg = <0x53fdc000 0x4000>;
@@ -429,12 +534,13 @@
429 #interrupt-cells = <2>; 534 #interrupt-cells = <2>;
430 }; 535 };
431 536
432 i2c@53fec000 { /* I2C3 */ 537 i2c3: i2c@53fec000 {
433 #address-cells = <1>; 538 #address-cells = <1>;
434 #size-cells = <0>; 539 #size-cells = <0>;
435 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c"; 540 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
436 reg = <0x53fec000 0x4000>; 541 reg = <0x53fec000 0x4000>;
437 interrupts = <64>; 542 interrupts = <64>;
543 clocks = <&clks 88>;
438 status = "disabled"; 544 status = "disabled";
439 }; 545 };
440 546
@@ -442,6 +548,8 @@
442 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 548 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
443 reg = <0x53ff0000 0x4000>; 549 reg = <0x53ff0000 0x4000>;
444 interrupts = <13>; 550 interrupts = <13>;
551 clocks = <&clks 65>, <&clks 66>;
552 clock-names = "ipg", "per";
445 status = "disabled"; 553 status = "disabled";
446 }; 554 };
447 }; 555 };
@@ -457,49 +565,59 @@
457 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 565 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
458 reg = <0x63f90000 0x4000>; 566 reg = <0x63f90000 0x4000>;
459 interrupts = <86>; 567 interrupts = <86>;
568 clocks = <&clks 67>, <&clks 68>;
569 clock-names = "ipg", "per";
460 status = "disabled"; 570 status = "disabled";
461 }; 571 };
462 572
463 ecspi@63fac000 { /* ECSPI2 */ 573 ecspi2: ecspi@63fac000 {
464 #address-cells = <1>; 574 #address-cells = <1>;
465 #size-cells = <0>; 575 #size-cells = <0>;
466 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; 576 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
467 reg = <0x63fac000 0x4000>; 577 reg = <0x63fac000 0x4000>;
468 interrupts = <37>; 578 interrupts = <37>;
579 clocks = <&clks 53>, <&clks 54>;
580 clock-names = "ipg", "per";
469 status = "disabled"; 581 status = "disabled";
470 }; 582 };
471 583
472 sdma@63fb0000 { 584 sdma: sdma@63fb0000 {
473 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; 585 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
474 reg = <0x63fb0000 0x4000>; 586 reg = <0x63fb0000 0x4000>;
475 interrupts = <6>; 587 interrupts = <6>;
588 clocks = <&clks 56>, <&clks 56>;
589 clock-names = "ipg", "ahb";
476 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; 590 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
477 }; 591 };
478 592
479 cspi@63fc0000 { 593 cspi: cspi@63fc0000 {
480 #address-cells = <1>; 594 #address-cells = <1>;
481 #size-cells = <0>; 595 #size-cells = <0>;
482 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; 596 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
483 reg = <0x63fc0000 0x4000>; 597 reg = <0x63fc0000 0x4000>;
484 interrupts = <38>; 598 interrupts = <38>;
599 clocks = <&clks 55>, <&clks 0>;
600 clock-names = "ipg", "per";
485 status = "disabled"; 601 status = "disabled";
486 }; 602 };
487 603
488 i2c@63fc4000 { /* I2C2 */ 604 i2c2: i2c@63fc4000 {
489 #address-cells = <1>; 605 #address-cells = <1>;
490 #size-cells = <0>; 606 #size-cells = <0>;
491 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c"; 607 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
492 reg = <0x63fc4000 0x4000>; 608 reg = <0x63fc4000 0x4000>;
493 interrupts = <63>; 609 interrupts = <63>;
610 clocks = <&clks 35>;
494 status = "disabled"; 611 status = "disabled";
495 }; 612 };
496 613
497 i2c@63fc8000 { /* I2C1 */ 614 i2c1: i2c@63fc8000 {
498 #address-cells = <1>; 615 #address-cells = <1>;
499 #size-cells = <0>; 616 #size-cells = <0>;
500 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c"; 617 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
501 reg = <0x63fc8000 0x4000>; 618 reg = <0x63fc8000 0x4000>;
502 interrupts = <62>; 619 interrupts = <62>;
620 clocks = <&clks 34>;
503 status = "disabled"; 621 status = "disabled";
504 }; 622 };
505 623
@@ -507,21 +625,23 @@
507 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; 625 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
508 reg = <0x63fcc000 0x4000>; 626 reg = <0x63fcc000 0x4000>;
509 interrupts = <29>; 627 interrupts = <29>;
628 clocks = <&clks 48>;
510 fsl,fifo-depth = <15>; 629 fsl,fifo-depth = <15>;
511 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ 630 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
512 status = "disabled"; 631 status = "disabled";
513 }; 632 };
514 633
515 audmux@63fd0000 { 634 audmux: audmux@63fd0000 {
516 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; 635 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
517 reg = <0x63fd0000 0x4000>; 636 reg = <0x63fd0000 0x4000>;
518 status = "disabled"; 637 status = "disabled";
519 }; 638 };
520 639
521 nand@63fdb000 { 640 nfc: nand@63fdb000 {
522 compatible = "fsl,imx53-nand"; 641 compatible = "fsl,imx53-nand";
523 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; 642 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
524 interrupts = <8>; 643 interrupts = <8>;
644 clocks = <&clks 60>;
525 status = "disabled"; 645 status = "disabled";
526 }; 646 };
527 647
@@ -529,15 +649,18 @@
529 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; 649 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
530 reg = <0x63fe8000 0x4000>; 650 reg = <0x63fe8000 0x4000>;
531 interrupts = <96>; 651 interrupts = <96>;
652 clocks = <&clks 50>;
532 fsl,fifo-depth = <15>; 653 fsl,fifo-depth = <15>;
533 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */ 654 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
534 status = "disabled"; 655 status = "disabled";
535 }; 656 };
536 657
537 ethernet@63fec000 { 658 fec: ethernet@63fec000 {
538 compatible = "fsl,imx53-fec", "fsl,imx25-fec"; 659 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
539 reg = <0x63fec000 0x4000>; 660 reg = <0x63fec000 0x4000>;
540 interrupts = <87>; 661 interrupts = <87>;
662 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
663 clock-names = "ipg", "ahb", "ptp";
541 status = "disabled"; 664 status = "disabled";
542 }; 665 };
543 }; 666 };
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
new file mode 100644
index 000000000000..826e4ad1477e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
@@ -0,0 +1,64 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "imx6q.dtsi"
15
16/ {
17 model = "Freescale i.MX6 Quad SABRE Automotive Board";
18 compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
19
20 memory {
21 reg = <0x10000000 0x80000000>;
22 };
23
24 soc {
25 aips-bus@02000000 { /* AIPS1 */
26 iomuxc@020e0000 {
27 pinctrl-names = "default";
28 pinctrl-0 = <&pinctrl_hog>;
29
30 hog {
31 pinctrl_hog: hoggrp {
32 fsl,pins = <
33 1376 0x80000000 /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */
34 13 0x80000000 /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */
35 >;
36 };
37 };
38 };
39 };
40
41 aips-bus@02100000 { /* AIPS2 */
42 uart4: serial@021f0000 {
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_uart4_1>;
45 status = "okay";
46 };
47
48 ethernet@02188000 {
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_enet_2>;
51 phy-mode = "rgmii";
52 status = "okay";
53 };
54
55 usdhc@02198000 { /* uSDHC3 */
56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_usdhc3_1>;
58 cd-gpios = <&gpio6 15 0>;
59 wp-gpios = <&gpio1 13 0>;
60 status = "okay";
61 };
62 };
63 };
64};
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index e596c28c214d..a42402562b7b 100644
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -38,6 +38,8 @@
38 hog { 38 hog {
39 pinctrl_hog: hoggrp { 39 pinctrl_hog: hoggrp {
40 fsl,pins = < 40 fsl,pins = <
41 1004 0x80000000 /* MX6Q_PAD_GPIO_4__GPIO_1_4 */
42 1012 0x80000000 /* MX6Q_PAD_GPIO_5__GPIO_1_5 */
41 1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */ 43 1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
42 1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */ 44 1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
43 1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */ 45 1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
@@ -73,4 +75,20 @@
73 }; 75 };
74 }; 76 };
75 }; 77 };
78
79 gpio-keys {
80 compatible = "gpio-keys";
81
82 volume-up {
83 label = "Volume Up";
84 gpios = <&gpio1 4 0>;
85 linux,code = <115>; /* KEY_VOLUMEUP */
86 };
87
88 volume-down {
89 label = "Volume Down";
90 gpios = <&gpio1 5 0>;
91 linux,code = <114>; /* KEY_VOLUMEDOWN */
92 };
93 };
76}; 94};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index f3990b04fecf..d6265ca97119 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -36,6 +36,14 @@
36 compatible = "arm,cortex-a9"; 36 compatible = "arm,cortex-a9";
37 reg = <0>; 37 reg = <0>;
38 next-level-cache = <&L2>; 38 next-level-cache = <&L2>;
39 operating-points = <
40 /* kHz uV */
41 792000 1100000
42 396000 950000
43 198000 850000
44 >;
45 clock-latency = <61036>; /* two CLK32 periods */
46 cpu0-supply = <&reg_cpu>;
39 }; 47 };
40 48
41 cpu@1 { 49 cpu@1 {
@@ -100,7 +108,7 @@
100 clocks = <&clks 106>; 108 clocks = <&clks 106>;
101 }; 109 };
102 110
103 gpmi-nand@00112000 { 111 nfc: gpmi-nand@00112000 {
104 compatible = "fsl,imx6q-gpmi-nand"; 112 compatible = "fsl,imx6q-gpmi-nand";
105 #address-cells = <1>; 113 #address-cells = <1>;
106 #size-cells = <1>; 114 #size-cells = <1>;
@@ -144,12 +152,12 @@
144 reg = <0x02000000 0x40000>; 152 reg = <0x02000000 0x40000>;
145 ranges; 153 ranges;
146 154
147 spdif@02004000 { 155 spdif: spdif@02004000 {
148 reg = <0x02004000 0x4000>; 156 reg = <0x02004000 0x4000>;
149 interrupts = <0 52 0x04>; 157 interrupts = <0 52 0x04>;
150 }; 158 };
151 159
152 ecspi@02008000 { /* eCSPI1 */ 160 ecspi1: ecspi@02008000 {
153 #address-cells = <1>; 161 #address-cells = <1>;
154 #size-cells = <0>; 162 #size-cells = <0>;
155 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 163 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -160,7 +168,7 @@
160 status = "disabled"; 168 status = "disabled";
161 }; 169 };
162 170
163 ecspi@0200c000 { /* eCSPI2 */ 171 ecspi2: ecspi@0200c000 {
164 #address-cells = <1>; 172 #address-cells = <1>;
165 #size-cells = <0>; 173 #size-cells = <0>;
166 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 174 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -171,7 +179,7 @@
171 status = "disabled"; 179 status = "disabled";
172 }; 180 };
173 181
174 ecspi@02010000 { /* eCSPI3 */ 182 ecspi3: ecspi@02010000 {
175 #address-cells = <1>; 183 #address-cells = <1>;
176 #size-cells = <0>; 184 #size-cells = <0>;
177 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 185 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -182,7 +190,7 @@
182 status = "disabled"; 190 status = "disabled";
183 }; 191 };
184 192
185 ecspi@02014000 { /* eCSPI4 */ 193 ecspi4: ecspi@02014000 {
186 #address-cells = <1>; 194 #address-cells = <1>;
187 #size-cells = <0>; 195 #size-cells = <0>;
188 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 196 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -193,7 +201,7 @@
193 status = "disabled"; 201 status = "disabled";
194 }; 202 };
195 203
196 ecspi@02018000 { /* eCSPI5 */ 204 ecspi5: ecspi@02018000 {
197 #address-cells = <1>; 205 #address-cells = <1>;
198 #size-cells = <0>; 206 #size-cells = <0>;
199 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 207 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -213,7 +221,7 @@
213 status = "disabled"; 221 status = "disabled";
214 }; 222 };
215 223
216 esai@02024000 { 224 esai: esai@02024000 {
217 reg = <0x02024000 0x4000>; 225 reg = <0x02024000 0x4000>;
218 interrupts = <0 51 0x04>; 226 interrupts = <0 51 0x04>;
219 }; 227 };
@@ -248,7 +256,7 @@
248 status = "disabled"; 256 status = "disabled";
249 }; 257 };
250 258
251 asrc@02034000 { 259 asrc: asrc@02034000 {
252 reg = <0x02034000 0x4000>; 260 reg = <0x02034000 0x4000>;
253 interrupts = <0 50 0x04>; 261 interrupts = <0 50 0x04>;
254 }; 262 };
@@ -258,7 +266,7 @@
258 }; 266 };
259 }; 267 };
260 268
261 vpu@02040000 { 269 vpu: vpu@02040000 {
262 reg = <0x02040000 0x3c000>; 270 reg = <0x02040000 0x3c000>;
263 interrupts = <0 3 0x04 0 12 0x04>; 271 interrupts = <0 3 0x04 0 12 0x04>;
264 }; 272 };
@@ -267,37 +275,53 @@
267 reg = <0x0207c000 0x4000>; 275 reg = <0x0207c000 0x4000>;
268 }; 276 };
269 277
270 pwm@02080000 { /* PWM1 */ 278 pwm1: pwm@02080000 {
279 #pwm-cells = <2>;
280 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
271 reg = <0x02080000 0x4000>; 281 reg = <0x02080000 0x4000>;
272 interrupts = <0 83 0x04>; 282 interrupts = <0 83 0x04>;
283 clocks = <&clks 62>, <&clks 145>;
284 clock-names = "ipg", "per";
273 }; 285 };
274 286
275 pwm@02084000 { /* PWM2 */ 287 pwm2: pwm@02084000 {
288 #pwm-cells = <2>;
289 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
276 reg = <0x02084000 0x4000>; 290 reg = <0x02084000 0x4000>;
277 interrupts = <0 84 0x04>; 291 interrupts = <0 84 0x04>;
292 clocks = <&clks 62>, <&clks 146>;
293 clock-names = "ipg", "per";
278 }; 294 };
279 295
280 pwm@02088000 { /* PWM3 */ 296 pwm3: pwm@02088000 {
297 #pwm-cells = <2>;
298 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
281 reg = <0x02088000 0x4000>; 299 reg = <0x02088000 0x4000>;
282 interrupts = <0 85 0x04>; 300 interrupts = <0 85 0x04>;
301 clocks = <&clks 62>, <&clks 147>;
302 clock-names = "ipg", "per";
283 }; 303 };
284 304
285 pwm@0208c000 { /* PWM4 */ 305 pwm4: pwm@0208c000 {
306 #pwm-cells = <2>;
307 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
286 reg = <0x0208c000 0x4000>; 308 reg = <0x0208c000 0x4000>;
287 interrupts = <0 86 0x04>; 309 interrupts = <0 86 0x04>;
310 clocks = <&clks 62>, <&clks 148>;
311 clock-names = "ipg", "per";
288 }; 312 };
289 313
290 flexcan@02090000 { /* CAN1 */ 314 can1: flexcan@02090000 {
291 reg = <0x02090000 0x4000>; 315 reg = <0x02090000 0x4000>;
292 interrupts = <0 110 0x04>; 316 interrupts = <0 110 0x04>;
293 }; 317 };
294 318
295 flexcan@02094000 { /* CAN2 */ 319 can2: flexcan@02094000 {
296 reg = <0x02094000 0x4000>; 320 reg = <0x02094000 0x4000>;
297 interrupts = <0 111 0x04>; 321 interrupts = <0 111 0x04>;
298 }; 322 };
299 323
300 gpt@02098000 { 324 gpt: gpt@02098000 {
301 compatible = "fsl,imx6q-gpt"; 325 compatible = "fsl,imx6q-gpt";
302 reg = <0x02098000 0x4000>; 326 reg = <0x02098000 0x4000>;
303 interrupts = <0 55 0x04>; 327 interrupts = <0 55 0x04>;
@@ -373,19 +397,19 @@
373 #interrupt-cells = <2>; 397 #interrupt-cells = <2>;
374 }; 398 };
375 399
376 kpp@020b8000 { 400 kpp: kpp@020b8000 {
377 reg = <0x020b8000 0x4000>; 401 reg = <0x020b8000 0x4000>;
378 interrupts = <0 82 0x04>; 402 interrupts = <0 82 0x04>;
379 }; 403 };
380 404
381 wdog@020bc000 { /* WDOG1 */ 405 wdog1: wdog@020bc000 {
382 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 406 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
383 reg = <0x020bc000 0x4000>; 407 reg = <0x020bc000 0x4000>;
384 interrupts = <0 80 0x04>; 408 interrupts = <0 80 0x04>;
385 clocks = <&clks 0>; 409 clocks = <&clks 0>;
386 }; 410 };
387 411
388 wdog@020c0000 { /* WDOG2 */ 412 wdog2: wdog@020c0000 {
389 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 413 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
390 reg = <0x020c0000 0x4000>; 414 reg = <0x020c0000 0x4000>;
391 interrupts = <0 81 0x04>; 415 interrupts = <0 81 0x04>;
@@ -447,7 +471,7 @@
447 anatop-max-voltage = <2750000>; 471 anatop-max-voltage = <2750000>;
448 }; 472 };
449 473
450 regulator-vddcore@140 { 474 reg_cpu: regulator-vddcore@140 {
451 compatible = "fsl,anatop-regulator"; 475 compatible = "fsl,anatop-regulator";
452 regulator-name = "cpu"; 476 regulator-name = "cpu";
453 regulator-min-microvolt = <725000>; 477 regulator-min-microvolt = <725000>;
@@ -505,27 +529,35 @@
505 }; 529 };
506 530
507 snvs@020cc000 { 531 snvs@020cc000 {
508 reg = <0x020cc000 0x4000>; 532 compatible = "fsl,sec-v4.0-mon", "simple-bus";
509 interrupts = <0 19 0x04 0 20 0x04>; 533 #address-cells = <1>;
534 #size-cells = <1>;
535 ranges = <0 0x020cc000 0x4000>;
536
537 snvs-rtc-lp@34 {
538 compatible = "fsl,sec-v4.0-mon-rtc-lp";
539 reg = <0x34 0x58>;
540 interrupts = <0 19 0x04 0 20 0x04>;
541 };
510 }; 542 };
511 543
512 epit@020d0000 { /* EPIT1 */ 544 epit1: epit@020d0000 { /* EPIT1 */
513 reg = <0x020d0000 0x4000>; 545 reg = <0x020d0000 0x4000>;
514 interrupts = <0 56 0x04>; 546 interrupts = <0 56 0x04>;
515 }; 547 };
516 548
517 epit@020d4000 { /* EPIT2 */ 549 epit2: epit@020d4000 { /* EPIT2 */
518 reg = <0x020d4000 0x4000>; 550 reg = <0x020d4000 0x4000>;
519 interrupts = <0 57 0x04>; 551 interrupts = <0 57 0x04>;
520 }; 552 };
521 553
522 src@020d8000 { 554 src: src@020d8000 {
523 compatible = "fsl,imx6q-src"; 555 compatible = "fsl,imx6q-src";
524 reg = <0x020d8000 0x4000>; 556 reg = <0x020d8000 0x4000>;
525 interrupts = <0 91 0x04 0 96 0x04>; 557 interrupts = <0 91 0x04 0 96 0x04>;
526 }; 558 };
527 559
528 gpc@020dc000 { 560 gpc: gpc@020dc000 {
529 compatible = "fsl,imx6q-gpc"; 561 compatible = "fsl,imx6q-gpc";
530 reg = <0x020dc000 0x4000>; 562 reg = <0x020dc000 0x4000>;
531 interrupts = <0 89 0x04 0 90 0x04>; 563 interrupts = <0 89 0x04 0 90 0x04>;
@@ -536,7 +568,7 @@
536 reg = <0x020e0000 0x38>; 568 reg = <0x020e0000 0x38>;
537 }; 569 };
538 570
539 iomuxc@020e0000 { 571 iomuxc: iomuxc@020e0000 {
540 compatible = "fsl,imx6q-iomuxc"; 572 compatible = "fsl,imx6q-iomuxc";
541 reg = <0x020e0000 0x4000>; 573 reg = <0x020e0000 0x4000>;
542 574
@@ -580,6 +612,7 @@
580 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ 612 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
581 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ 613 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
582 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ 614 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
615 1033 0x4001b0a8 /* MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT*/
583 >; 616 >;
584 }; 617 };
585 618
@@ -748,17 +781,17 @@
748 }; 781 };
749 }; 782 };
750 783
751 dcic@020e4000 { /* DCIC1 */ 784 dcic1: dcic@020e4000 {
752 reg = <0x020e4000 0x4000>; 785 reg = <0x020e4000 0x4000>;
753 interrupts = <0 124 0x04>; 786 interrupts = <0 124 0x04>;
754 }; 787 };
755 788
756 dcic@020e8000 { /* DCIC2 */ 789 dcic2: dcic@020e8000 {
757 reg = <0x020e8000 0x4000>; 790 reg = <0x020e8000 0x4000>;
758 interrupts = <0 125 0x04>; 791 interrupts = <0 125 0x04>;
759 }; 792 };
760 793
761 sdma@020ec000 { 794 sdma: sdma@020ec000 {
762 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; 795 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
763 reg = <0x020ec000 0x4000>; 796 reg = <0x020ec000 0x4000>;
764 interrupts = <0 2 0x04>; 797 interrupts = <0 2 0x04>;
@@ -784,7 +817,7 @@
784 reg = <0x0217c000 0x4000>; 817 reg = <0x0217c000 0x4000>;
785 }; 818 };
786 819
787 usb@02184000 { /* USB OTG */ 820 usbotg: usb@02184000 {
788 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 821 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
789 reg = <0x02184000 0x200>; 822 reg = <0x02184000 0x200>;
790 interrupts = <0 43 0x04>; 823 interrupts = <0 43 0x04>;
@@ -794,7 +827,7 @@
794 status = "disabled"; 827 status = "disabled";
795 }; 828 };
796 829
797 usb@02184200 { /* USB1 */ 830 usbh1: usb@02184200 {
798 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 831 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
799 reg = <0x02184200 0x200>; 832 reg = <0x02184200 0x200>;
800 interrupts = <0 40 0x04>; 833 interrupts = <0 40 0x04>;
@@ -804,7 +837,7 @@
804 status = "disabled"; 837 status = "disabled";
805 }; 838 };
806 839
807 usb@02184400 { /* USB2 */ 840 usbh2: usb@02184400 {
808 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 841 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
809 reg = <0x02184400 0x200>; 842 reg = <0x02184400 0x200>;
810 interrupts = <0 41 0x04>; 843 interrupts = <0 41 0x04>;
@@ -813,7 +846,7 @@
813 status = "disabled"; 846 status = "disabled";
814 }; 847 };
815 848
816 usb@02184600 { /* USB3 */ 849 usbh3: usb@02184600 {
817 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 850 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
818 reg = <0x02184600 0x200>; 851 reg = <0x02184600 0x200>;
819 interrupts = <0 42 0x04>; 852 interrupts = <0 42 0x04>;
@@ -822,19 +855,19 @@
822 status = "disabled"; 855 status = "disabled";
823 }; 856 };
824 857
825 usbmisc: usbmisc@02184800 { 858 usbmisc: usbmisc: usbmisc@02184800 {
826 #index-cells = <1>; 859 #index-cells = <1>;
827 compatible = "fsl,imx6q-usbmisc"; 860 compatible = "fsl,imx6q-usbmisc";
828 reg = <0x02184800 0x200>; 861 reg = <0x02184800 0x200>;
829 clocks = <&clks 162>; 862 clocks = <&clks 162>;
830 }; 863 };
831 864
832 ethernet@02188000 { 865 fec: ethernet@02188000 {
833 compatible = "fsl,imx6q-fec"; 866 compatible = "fsl,imx6q-fec";
834 reg = <0x02188000 0x4000>; 867 reg = <0x02188000 0x4000>;
835 interrupts = <0 118 0x04 0 119 0x04>; 868 interrupts = <0 118 0x04 0 119 0x04>;
836 clocks = <&clks 117>, <&clks 117>; 869 clocks = <&clks 117>, <&clks 117>, <&clks 177>;
837 clock-names = "ipg", "ahb"; 870 clock-names = "ipg", "ahb", "ptp";
838 status = "disabled"; 871 status = "disabled";
839 }; 872 };
840 873
@@ -843,66 +876,70 @@
843 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>; 876 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
844 }; 877 };
845 878
846 usdhc@02190000 { /* uSDHC1 */ 879 usdhc1: usdhc@02190000 {
847 compatible = "fsl,imx6q-usdhc"; 880 compatible = "fsl,imx6q-usdhc";
848 reg = <0x02190000 0x4000>; 881 reg = <0x02190000 0x4000>;
849 interrupts = <0 22 0x04>; 882 interrupts = <0 22 0x04>;
850 clocks = <&clks 163>, <&clks 163>, <&clks 163>; 883 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
851 clock-names = "ipg", "ahb", "per"; 884 clock-names = "ipg", "ahb", "per";
885 bus-width = <4>;
852 status = "disabled"; 886 status = "disabled";
853 }; 887 };
854 888
855 usdhc@02194000 { /* uSDHC2 */ 889 usdhc2: usdhc@02194000 {
856 compatible = "fsl,imx6q-usdhc"; 890 compatible = "fsl,imx6q-usdhc";
857 reg = <0x02194000 0x4000>; 891 reg = <0x02194000 0x4000>;
858 interrupts = <0 23 0x04>; 892 interrupts = <0 23 0x04>;
859 clocks = <&clks 164>, <&clks 164>, <&clks 164>; 893 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
860 clock-names = "ipg", "ahb", "per"; 894 clock-names = "ipg", "ahb", "per";
895 bus-width = <4>;
861 status = "disabled"; 896 status = "disabled";
862 }; 897 };
863 898
864 usdhc@02198000 { /* uSDHC3 */ 899 usdhc3: usdhc@02198000 {
865 compatible = "fsl,imx6q-usdhc"; 900 compatible = "fsl,imx6q-usdhc";
866 reg = <0x02198000 0x4000>; 901 reg = <0x02198000 0x4000>;
867 interrupts = <0 24 0x04>; 902 interrupts = <0 24 0x04>;
868 clocks = <&clks 165>, <&clks 165>, <&clks 165>; 903 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
869 clock-names = "ipg", "ahb", "per"; 904 clock-names = "ipg", "ahb", "per";
905 bus-width = <4>;
870 status = "disabled"; 906 status = "disabled";
871 }; 907 };
872 908
873 usdhc@0219c000 { /* uSDHC4 */ 909 usdhc4: usdhc@0219c000 {
874 compatible = "fsl,imx6q-usdhc"; 910 compatible = "fsl,imx6q-usdhc";
875 reg = <0x0219c000 0x4000>; 911 reg = <0x0219c000 0x4000>;
876 interrupts = <0 25 0x04>; 912 interrupts = <0 25 0x04>;
877 clocks = <&clks 166>, <&clks 166>, <&clks 166>; 913 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
878 clock-names = "ipg", "ahb", "per"; 914 clock-names = "ipg", "ahb", "per";
915 bus-width = <4>;
879 status = "disabled"; 916 status = "disabled";
880 }; 917 };
881 918
882 i2c@021a0000 { /* I2C1 */ 919 i2c1: i2c@021a0000 {
883 #address-cells = <1>; 920 #address-cells = <1>;
884 #size-cells = <0>; 921 #size-cells = <0>;
885 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; 922 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
886 reg = <0x021a0000 0x4000>; 923 reg = <0x021a0000 0x4000>;
887 interrupts = <0 36 0x04>; 924 interrupts = <0 36 0x04>;
888 clocks = <&clks 125>; 925 clocks = <&clks 125>;
889 status = "disabled"; 926 status = "disabled";
890 }; 927 };
891 928
892 i2c@021a4000 { /* I2C2 */ 929 i2c2: i2c@021a4000 {
893 #address-cells = <1>; 930 #address-cells = <1>;
894 #size-cells = <0>; 931 #size-cells = <0>;
895 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; 932 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
896 reg = <0x021a4000 0x4000>; 933 reg = <0x021a4000 0x4000>;
897 interrupts = <0 37 0x04>; 934 interrupts = <0 37 0x04>;
898 clocks = <&clks 126>; 935 clocks = <&clks 126>;
899 status = "disabled"; 936 status = "disabled";
900 }; 937 };
901 938
902 i2c@021a8000 { /* I2C3 */ 939 i2c3: i2c@021a8000 {
903 #address-cells = <1>; 940 #address-cells = <1>;
904 #size-cells = <0>; 941 #size-cells = <0>;
905 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; 942 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
906 reg = <0x021a8000 0x4000>; 943 reg = <0x021a8000 0x4000>;
907 interrupts = <0 38 0x04>; 944 interrupts = <0 38 0x04>;
908 clocks = <&clks 127>; 945 clocks = <&clks 127>;
@@ -913,12 +950,12 @@
913 reg = <0x021ac000 0x4000>; 950 reg = <0x021ac000 0x4000>;
914 }; 951 };
915 952
916 mmdc@021b0000 { /* MMDC0 */ 953 mmdc0: mmdc@021b0000 { /* MMDC0 */
917 compatible = "fsl,imx6q-mmdc"; 954 compatible = "fsl,imx6q-mmdc";
918 reg = <0x021b0000 0x4000>; 955 reg = <0x021b0000 0x4000>;
919 }; 956 };
920 957
921 mmdc@021b4000 { /* MMDC1 */ 958 mmdc1: mmdc@021b4000 { /* MMDC1 */
922 reg = <0x021b4000 0x4000>; 959 reg = <0x021b4000 0x4000>;
923 }; 960 };
924 961
@@ -946,7 +983,7 @@
946 interrupts = <0 109 0x04>; 983 interrupts = <0 109 0x04>;
947 }; 984 };
948 985
949 audmux@021d8000 { 986 audmux: audmux@021d8000 {
950 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; 987 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
951 reg = <0x021d8000 0x4000>; 988 reg = <0x021d8000 0x4000>;
952 status = "disabled"; 989 status = "disabled";
@@ -1001,5 +1038,23 @@
1001 status = "disabled"; 1038 status = "disabled";
1002 }; 1039 };
1003 }; 1040 };
1041
1042 ipu1: ipu@02400000 {
1043 #crtc-cells = <1>;
1044 compatible = "fsl,imx6q-ipu";
1045 reg = <0x02400000 0x400000>;
1046 interrupts = <0 6 0x4 0 5 0x4>;
1047 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
1048 clock-names = "bus", "di0", "di1";
1049 };
1050
1051 ipu2: ipu@02800000 {
1052 #crtc-cells = <1>;
1053 compatible = "fsl,imx6q-ipu";
1054 reg = <0x02800000 0x400000>;
1055 interrupts = <0 8 0x4 0 7 0x4>;
1056 clocks = <&clks 133>, <&clks 134>, <&clks 137>;
1057 clock-names = "bus", "di0", "di1";
1058 };
1004 }; 1059 };
1005}; 1060};
diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts
index 61767757b50a..c9c3fa344647 100644
--- a/arch/arm/boot/dts/integratorap.dts
+++ b/arch/arm/boot/dts/integratorap.dts
@@ -18,6 +18,11 @@
18 bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk"; 18 bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
19 }; 19 };
20 20
21 syscon {
22 /* AP system controller registers */
23 reg = <0x11000000 0x100>;
24 };
25
21 timer0: timer@13000000 { 26 timer0: timer@13000000 {
22 compatible = "arm,integrator-timer"; 27 compatible = "arm,integrator-timer";
23 }; 28 };
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
index 2dd5e4e48481..8b119399025a 100644
--- a/arch/arm/boot/dts/integratorcp.dts
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -18,6 +18,11 @@
18 bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk"; 18 bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
19 }; 19 };
20 20
21 cpcon {
22 /* CP controller registers */
23 reg = <0xcb000000 0x100>;
24 };
25
21 timer0: timer@13000000 { 26 timer0: timer@13000000 {
22 compatible = "arm,sp804", "arm,primecell"; 27 compatible = "arm,sp804", "arm,primecell";
23 }; 28 };
diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi
new file mode 100644
index 000000000000..d6c9d65cbaeb
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-6281.dtsi
@@ -0,0 +1,44 @@
1/ {
2 ocp@f1000000 {
3 pinctrl: pinctrl@10000 {
4 compatible = "marvell,88f6281-pinctrl";
5 reg = <0x10000 0x20>;
6
7 pmx_nand: pmx-nand {
8 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
9 "mpp4", "mpp5", "mpp18",
10 "mpp19";
11 marvell,function = "nand";
12 };
13 pmx_sata0: pmx-sata0 {
14 marvell,pins = "mpp5", "mpp21", "mpp23";
15 marvell,function = "sata0";
16 };
17 pmx_sata1: pmx-sata1 {
18 marvell,pins = "mpp4", "mpp20", "mpp22";
19 marvell,function = "sata1";
20 };
21 pmx_spi: pmx-spi {
22 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
23 marvell,function = "spi";
24 };
25 pmx_twsi0: pmx-twsi0 {
26 marvell,pins = "mpp8", "mpp9";
27 marvell,function = "twsi0";
28 };
29 pmx_uart0: pmx-uart0 {
30 marvell,pins = "mpp10", "mpp11";
31 marvell,function = "uart0";
32 };
33 pmx_uart1: pmx-uart1 {
34 marvell,pins = "mpp13", "mpp14";
35 marvell,function = "uart1";
36 };
37 pmx_sdio: pmx-sdio {
38 marvell,pins = "mpp12", "mpp13", "mpp14",
39 "mpp15", "mpp16", "mpp17";
40 marvell,function = "sdio";
41 };
42 };
43 };
44};
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
new file mode 100644
index 000000000000..4ccea2130a6c
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -0,0 +1,46 @@
1/ {
2 ocp@f1000000 {
3
4 pinctrl: pinctrl@10000 {
5 compatible = "marvell,88f6282-pinctrl";
6 reg = <0x10000 0x20>;
7
8 pmx_sata0: pmx-sata0 {
9 marvell,pins = "mpp5", "mpp21", "mpp23";
10 marvell,function = "sata0";
11 };
12 pmx_sata1: pmx-sata1 {
13 marvell,pins = "mpp4", "mpp20", "mpp22";
14 marvell,function = "sata1";
15 };
16 pmx_spi: pmx-spi {
17 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
18 marvell,function = "spi";
19 };
20 pmx_twsi0: pmx-twsi0 {
21 marvell,pins = "mpp8", "mpp9";
22 marvell,function = "twsi0";
23 };
24 pmx_uart0: pmx-uart0 {
25 marvell,pins = "mpp10", "mpp11";
26 marvell,function = "uart0";
27 };
28
29 pmx_uart1: pmx-uart1 {
30 marvell,pins = "mpp13", "mpp14";
31 marvell,function = "uart1";
32 };
33 };
34
35 i2c@11100 {
36 compatible = "marvell,mv64xxx-i2c";
37 reg = <0x11100 0x20>;
38 #address-cells = <1>;
39 #size-cells = <0>;
40 interrupts = <32>;
41 clock-frequency = <100000>;
42 clocks = <&gate_clk 7>;
43 status = "disabled";
44 };
45 };
46};
diff --git a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi
new file mode 100644
index 000000000000..3271e4c8ea07
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi
@@ -0,0 +1,31 @@
1/ {
2 ocp@f1000000 {
3 pinctrl: pinctrl@10000 {
4 compatible = "marvell,98dx4122-pinctrl";
5 reg = <0x10000 0x20>;
6
7 pmx_nand: pmx-nand {
8 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
9 "mpp4", "mpp5", "mpp18",
10 "mpp19";
11 marvell,function = "nand";
12 };
13 pmx_spi: pmx-spi {
14 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
15 marvell,function = "spi";
16 };
17 pmx_twsi0: pmx-twsi0 {
18 marvell,pins = "mpp8", "mpp9";
19 marvell,function = "twsi0";
20 };
21 pmx_uart0: pmx-uart0 {
22 marvell,pins = "mpp10", "mpp11";
23 marvell,function = "uart0";
24 };
25 pmx_uart1: pmx-uart1 {
26 marvell,pins = "mpp13", "mpp14";
27 marvell,function = "uart1";
28 };
29 };
30 };
31};
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
index 9b32d0272825..6875ac00c174 100644
--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
@@ -1,4 +1,5 @@
1/include/ "kirkwood.dtsi" 1/include/ "kirkwood.dtsi"
2/include/ "kirkwood-6281.dtsi"
2 3
3/ { 4/ {
4 model = "D-Link DNS NASes (kirkwood-based)"; 5 model = "D-Link DNS NASes (kirkwood-based)";
@@ -35,7 +36,116 @@
35 6000 2>; 36 6000 2>;
36 }; 37 };
37 38
39 gpio_poweroff {
40 compatible = "gpio-poweroff";
41 gpios = <&gpio1 4 0>;
42 };
43
38 ocp@f1000000 { 44 ocp@f1000000 {
45 pinctrl: pinctrl@10000 {
46
47 pinctrl-0 = < &pmx_nand &pmx_uart1
48 &pmx_sata0 &pmx_sata1
49 &pmx_led_power
50 &pmx_led_red_right_hdd
51 &pmx_led_red_left_hdd
52 &pmx_led_red_usb_325
53 &pmx_button_power
54 &pmx_led_red_usb_320
55 &pmx_power_off &pmx_power_back_on
56 &pmx_power_sata0 &pmx_power_sata1
57 &pmx_present_sata0 &pmx_present_sata1
58 &pmx_led_white_usb &pmx_fan_tacho
59 &pmx_fan_high_speed &pmx_fan_low_speed
60 &pmx_button_unmount &pmx_button_reset
61 &pmx_temp_alarm >;
62 pinctrl-names = "default";
63
64 pmx_sata0: pmx-sata0 {
65 marvell,pins = "mpp20";
66 marvell,function = "sata1";
67 };
68 pmx_sata1: pmx-sata1 {
69 marvell,pins = "mpp21";
70 marvell,function = "sata0";
71 };
72 pmx_led_power: pmx-led-power {
73 marvell,pins = "mpp26";
74 marvell,function = "gpio";
75 };
76 pmx_led_red_right_hdd: pmx-led-red-right-hdd {
77 marvell,pins = "mpp27";
78 marvell,function = "gpio";
79 };
80 pmx_led_red_left_hdd: pmx-led-red-left-hdd {
81 marvell,pins = "mpp28";
82 marvell,function = "gpio";
83 };
84 pmx_led_red_usb_325: pmx-led-red-usb-325 {
85 marvell,pins = "mpp29";
86 marvell,function = "gpio";
87 };
88 pmx_button_power: pmx-button-power {
89 marvell,pins = "mpp34";
90 marvell,function = "gpio";
91 };
92 pmx_led_red_usb_320: pmx-led-red-usb-320 {
93 marvell,pins = "mpp35";
94 marvell,function = "gpio";
95 };
96 pmx_power_off: pmx-power-off {
97 marvell,pins = "mpp36";
98 marvell,function = "gpio";
99 };
100 pmx_power_back_on: pmx-power-back-on {
101 marvell,pins = "mpp37";
102 marvell,function = "gpio";
103 };
104 pmx_power_sata0: pmx-power-sata0 {
105 marvell,pins = "mpp39";
106 marvell,function = "gpio";
107 };
108 pmx_power_sata1: pmx-power-sata1 {
109 marvell,pins = "mpp40";
110 marvell,function = "gpio";
111 };
112 pmx_present_sata0: pmx-present-sata0 {
113 marvell,pins = "mpp41";
114 marvell,function = "gpio";
115 };
116 pmx_present_sata1: pmx-present-sata1 {
117 marvell,pins = "mpp42";
118 marvell,function = "gpio";
119 };
120 pmx_led_white_usb: pmx-led-white-usb {
121 marvell,pins = "mpp43";
122 marvell,function = "gpio";
123 };
124 pmx_fan_tacho: pmx-fan-tacho {
125 marvell,pins = "mpp44";
126 marvell,function = "gpio";
127 };
128 pmx_fan_high_speed: pmx-fan-high-speed {
129 marvell,pins = "mpp45";
130 marvell,function = "gpio";
131 };
132 pmx_fan_low_speed: pmx-fan-low-speed {
133 marvell,pins = "mpp46";
134 marvell,function = "gpio";
135 };
136 pmx_button_unmount: pmx-button-unmount {
137 marvell,pins = "mpp47";
138 marvell,function = "gpio";
139 };
140 pmx_button_reset: pmx-button-reset {
141 marvell,pins = "mpp48";
142 marvell,function = "gpio";
143 };
144 pmx_temp_alarm: pmx-temp-alarm {
145 marvell,pins = "mpp49";
146 marvell,function = "gpio";
147 };
148 };
39 sata@80000 { 149 sata@80000 {
40 status = "okay"; 150 status = "okay";
41 nr-ports = <2>; 151 nr-ports = <2>;
@@ -43,6 +153,7 @@
43 153
44 nand@3000000 { 154 nand@3000000 {
45 status = "okay"; 155 status = "okay";
156 chip-delay = <35>;
46 157
47 partition@0 { 158 partition@0 {
48 label = "u-boot"; 159 label = "u-boot";
@@ -76,4 +187,33 @@
76 }; 187 };
77 }; 188 };
78 }; 189 };
190
191 regulators {
192 compatible = "simple-bus";
193 #address-cells = <1>;
194 #size-cells = <0>;
195
196 sata0_power: regulator@1 {
197 compatible = "regulator-fixed";
198 reg = <1>;
199 regulator-name = "SATA0 Power";
200 regulator-min-microvolt = <5000000>;
201 regulator-max-microvolt = <5000000>;
202 enable-active-high;
203 regulator-always-on;
204 regulator-boot-on;
205 gpio = <&gpio1 7 0>;
206 };
207 sata1_power: regulator@2 {
208 compatible = "regulator-fixed";
209 reg = <2>;
210 regulator-name = "SATA1 Power";
211 regulator-min-microvolt = <5000000>;
212 regulator-max-microvolt = <5000000>;
213 enable-active-high;
214 regulator-always-on;
215 regulator-boot-on;
216 gpio = <&gpio1 8 0>;
217 };
218 };
79}; 219};
diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts
index 08a582414b88..2e3dd34e21a5 100644
--- a/arch/arm/boot/dts/kirkwood-dockstar.dts
+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts
@@ -1,6 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3/include/ "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi"
4 5
5/ { 6/ {
6 model = "Seagate FreeAgent Dockstar"; 7 model = "Seagate FreeAgent Dockstar";
@@ -16,6 +17,25 @@
16 }; 17 };
17 18
18 ocp@f1000000 { 19 ocp@f1000000 {
20 pinctrl: pinctrl@10000 {
21
22 pinctrl-0 = < &pmx_usb_power_enable
23 &pmx_led_green &pmx_led_orange >;
24 pinctrl-names = "default";
25
26 pmx_usb_power_enable: pmx-usb-power-enable {
27 marvell,pins = "mpp29";
28 marvell,function = "gpio";
29 };
30 pmx_led_green: pmx-led-green {
31 marvell,pins = "mpp46";
32 marvell,function = "gpio";
33 };
34 pmx_led_orange: pmx-led-orange {
35 marvell,pins = "mpp47";
36 marvell,function = "gpio";
37 };
38 };
19 serial@12000 { 39 serial@12000 {
20 clock-frequency = <200000000>; 40 clock-frequency = <200000000>;
21 status = "ok"; 41 status = "ok";
@@ -54,4 +74,21 @@
54 gpios = <&gpio1 15 1>; 74 gpios = <&gpio1 15 1>;
55 }; 75 };
56 }; 76 };
77 regulators {
78 compatible = "simple-bus";
79 #address-cells = <1>;
80 #size-cells = <0>;
81
82 usb_power: regulator@1 {
83 compatible = "regulator-fixed";
84 reg = <1>;
85 regulator-name = "USB Power";
86 regulator-min-microvolt = <5000000>;
87 regulator-max-microvolt = <5000000>;
88 enable-active-high;
89 regulator-always-on;
90 regulator-boot-on;
91 gpio = <&gpio0 29 0>;
92 };
93 };
57}; 94};
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index 26e281fbf6bc..f2d386c95b07 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -1,6 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3/include/ "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi"
4 5
5/ { 6/ {
6 model = "Globalscale Technologies Dreamplug"; 7 model = "Globalscale Technologies Dreamplug";
@@ -16,6 +17,26 @@
16 }; 17 };
17 18
18 ocp@f1000000 { 19 ocp@f1000000 {
20 pinctrl: pinctrl@10000 {
21
22 pinctrl-0 = < &pmx_spi
23 &pmx_led_bluetooth &pmx_led_wifi
24 &pmx_led_wifi_ap >;
25 pinctrl-names = "default";
26
27 pmx_led_bluetooth: pmx-led-bluetooth {
28 marvell,pins = "mpp47";
29 marvell,function = "gpio";
30 };
31 pmx_led_wifi: pmx-led-wifi {
32 marvell,pins = "mpp48";
33 marvell,function = "gpio";
34 };
35 pmx_led_wifi_ap: pmx-led-wifi-ap {
36 marvell,pins = "mpp49";
37 marvell,function = "gpio";
38 };
39 };
19 serial@12000 { 40 serial@12000 {
20 clock-frequency = <200000000>; 41 clock-frequency = <200000000>;
21 status = "ok"; 42 status = "ok";
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
index 7c8238fbb6f9..1b133e0c566e 100644
--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
@@ -1,6 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3/include/ "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi"
4 5
5/ { 6/ {
6 model = "Seagate GoFlex Net"; 7 model = "Seagate GoFlex Net";
@@ -16,6 +17,61 @@
16 }; 17 };
17 18
18 ocp@f1000000 { 19 ocp@f1000000 {
20 pinctrl: pinctrl@10000 {
21
22 pinctrl-0 = < &pmx_usb_power_enable &pmx_led_orange
23 &pmx_led_left_cap_0 &pmx_led_left_cap_1
24 &pmx_led_left_cap_2 &pmx_led_left_cap_3
25 &pmx_led_right_cap_0 &pmx_led_right_cap_1
26 &pmx_led_right_cap_2 &pmx_led_right_cap_3
27 >;
28 pinctrl-names = "default";
29
30 pmx_usb_power_enable: pmx-usb-power-enable {
31 marvell,pins = "mpp29";
32 marvell,function = "gpio";
33 };
34 pmx_led_right_cap_0: pmx-led_right_cap_0 {
35 marvell,pins = "mpp38";
36 marvell,function = "gpio";
37 };
38 pmx_led_right_cap_1: pmx-led_right_cap_1 {
39 marvell,pins = "mpp39";
40 marvell,function = "gpio";
41 };
42 pmx_led_right_cap_2: pmx-led_right_cap_2 {
43 marvell,pins = "mpp40";
44 marvell,function = "gpio";
45 };
46 pmx_led_right_cap_3: pmx-led_right_cap_3 {
47 marvell,pins = "mpp41";
48 marvell,function = "gpio";
49 };
50 pmx_led_left_cap_0: pmx-led_left_cap_0 {
51 marvell,pins = "mpp42";
52 marvell,function = "gpio";
53 };
54 pmx_led_left_cap_1: pmx-led_left_cap_1 {
55 marvell,pins = "mpp43";
56 marvell,function = "gpio";
57 };
58 pmx_led_left_cap_2: pmx-led_left_cap_2 {
59 marvell,pins = "mpp44";
60 marvell,function = "gpio";
61 };
62 pmx_led_left_cap_3: pmx-led_left_cap_3 {
63 marvell,pins = "mpp45";
64 marvell,function = "gpio";
65 };
66 pmx_led_green: pmx-led_green {
67 marvell,pins = "mpp46";
68 marvell,function = "gpio";
69 };
70 pmx_led_orange: pmx-led_orange {
71 marvell,pins = "mpp47";
72 marvell,function = "gpio";
73 };
74 };
19 serial@12000 { 75 serial@12000 {
20 clock-frequency = <200000000>; 76 clock-frequency = <200000000>;
21 status = "ok"; 77 status = "ok";
@@ -96,4 +152,21 @@
96 gpios = <&gpio1 9 0>; 152 gpios = <&gpio1 9 0>;
97 }; 153 };
98 }; 154 };
155 regulators {
156 compatible = "simple-bus";
157 #address-cells = <1>;
158 #size-cells = <0>;
159
160 usb_power: regulator@1 {
161 compatible = "regulator-fixed";
162 reg = <1>;
163 regulator-name = "USB Power";
164 regulator-min-microvolt = <5000000>;
165 regulator-max-microvolt = <5000000>;
166 enable-active-high;
167 regulator-always-on;
168 regulator-boot-on;
169 gpio = <&gpio0 29 0>;
170 };
171 };
99}; 172};
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts
index 66794ed75ff1..71902da33d63 100644
--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts
+++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts
@@ -1,6 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3/include/ "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi"
4 5
5/ { 6/ {
6 model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)"; 7 model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)";
@@ -16,6 +17,39 @@
16 }; 17 };
17 18
18 ocp@f1000000 { 19 ocp@f1000000 {
20 pinctrl: pinctrl@10000 {
21
22 pinctrl-0 = < &pmx_nand
23 &pmx_led_os_red &pmx_power_off
24 &pmx_led_os_green &pmx_led_usb_transfer
25 &pmx_button_reset &pmx_button_usb_copy >;
26 pinctrl-names = "default";
27
28 pmx_led_os_red: pmx-led-os-red {
29 marvell,pins = "mpp22";
30 marvell,function = "gpio";
31 };
32 pmx_power_off: pmx-power-off {
33 marvell,pins = "mpp24";
34 marvell,function = "gpio";
35 };
36 pmx_led_os_green: pmx-led-os-green {
37 marvell,pins = "mpp25";
38 marvell,function = "gpio";
39 };
40 pmx_led_usb_transfer: pmx-led-usb-transfer {
41 marvell,pins = "mpp27";
42 marvell,function = "gpio";
43 };
44 pmx_button_reset: pmx-button-reset {
45 marvell,pins = "mpp28";
46 marvell,function = "gpio";
47 };
48 pmx_button_usb_copy: pmx-button-usb-copy {
49 marvell,pins = "mpp29";
50 marvell,function = "gpio";
51 };
52 };
19 serial@12000 { 53 serial@12000 {
20 clock-frequency = <200000000>; 54 clock-frequency = <200000000>;
21 status = "okay"; 55 status = "okay";
@@ -79,4 +113,10 @@
79 gpios = <&gpio0 27 0>; 113 gpios = <&gpio0 27 0>;
80 }; 114 };
81 }; 115 };
116 gpio_poweroff {
117 compatible = "gpio-poweroff";
118 gpios = <&gpio0 24 0>;
119 };
120
121
82}; 122};
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index d97cd9d4753e..504f16be8b54 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -1,6 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3/include/ "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi"
4 5
5/ { 6/ {
6 model = "Iomega Iconnect"; 7 model = "Iomega Iconnect";
@@ -18,6 +19,56 @@
18 }; 19 };
19 20
20 ocp@f1000000 { 21 ocp@f1000000 {
22 pinctrl: pinctrl@10000 {
23
24 pinctrl-0 = < &pmx_gpio_12 &pmx_gpio_35
25 &pmx_gpio_41 &pmx_gpio_42
26 &pmx_gpio_43 &pmx_gpio_44
27 &pmx_gpio_45 &pmx_gpio_46
28 &pmx_gpio_47 &pmx_gpio_48 >;
29 pinctrl-names = "default";
30
31 pmx_gpio_12: pmx-gpio-12 {
32 marvell,pins = "mpp12";
33 marvell,function = "gpio";
34 };
35 pmx_gpio_35: pmx-gpio-35 {
36 marvell,pins = "mpp35";
37 marvell,function = "gpio";
38 };
39 pmx_gpio_41: pmx-gpio-41 {
40 marvell,pins = "mpp41";
41 marvell,function = "gpio";
42 };
43 pmx_gpio_42: pmx-gpio-42 {
44 marvell,pins = "mpp42";
45 marvell,function = "gpio";
46 };
47 pmx_gpio_43: pmx-gpio-43 {
48 marvell,pins = "mpp43";
49 marvell,function = "gpio";
50 };
51 pmx_gpio_44: pmx-gpio-44 {
52 marvell,pins = "mpp44";
53 marvell,function = "gpio";
54 };
55 pmx_gpio_45: pmx-gpio-45 {
56 marvell,pins = "mpp45";
57 marvell,function = "gpio";
58 };
59 pmx_gpio_46: pmx-gpio-46 {
60 marvell,pins = "mpp46";
61 marvell,function = "gpio";
62 };
63 pmx_gpio_47: pmx-gpio-47 {
64 marvell,pins = "mpp47";
65 marvell,function = "gpio";
66 };
67 pmx_gpio_48: pmx-gpio-48 {
68 marvell,pins = "mpp48";
69 marvell,function = "gpio";
70 };
71 };
21 i2c@11000 { 72 i2c@11000 {
22 status = "okay"; 73 status = "okay";
23 74
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
index 865aeec40a26..6cae4599c4b3 100644
--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -1,6 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3/include/ "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi"
4 5
5/ { 6/ {
6 model = "Iomega StorCenter ix2-200"; 7 model = "Iomega StorCenter ix2-200";
@@ -16,6 +17,94 @@
16 }; 17 };
17 18
18 ocp@f1000000 { 19 ocp@f1000000 {
20 pinctrl: pinctrl@10000 {
21
22 pinctrl-0 = < &pmx_button_reset &pmx_button_power
23 &pmx_led_backup &pmx_led_power
24 &pmx_button_otb &pmx_led_rebuild
25 &pmx_led_health
26 &pmx_led_sata_brt_ctrl_1
27 &pmx_led_sata_brt_ctrl_2
28 &pmx_led_backup_brt_ctrl_1
29 &pmx_led_backup_brt_ctrl_2
30 &pmx_led_power_brt_ctrl_1
31 &pmx_led_power_brt_ctrl_2
32 &pmx_led_health_brt_ctrl_1
33 &pmx_led_health_brt_ctrl_2
34 &pmx_led_rebuild_brt_ctrl_1
35 &pmx_led_rebuild_brt_ctrl_2 >;
36 pinctrl-names = "default";
37
38 pmx_button_reset: pmx-button-reset {
39 marvell,pins = "mpp12";
40 marvell,function = "gpio";
41 };
42 pmx_button_power: pmx-button-power {
43 marvell,pins = "mpp14";
44 marvell,function = "gpio";
45 };
46 pmx_led_backup: pmx-led-backup {
47 marvell,pins = "mpp15";
48 marvell,function = "gpio";
49 };
50 pmx_led_power: pmx-led-power {
51 marvell,pins = "mpp16";
52 marvell,function = "gpio";
53 };
54 pmx_button_otb: pmx-button-otb {
55 marvell,pins = "mpp35";
56 marvell,function = "gpio";
57 };
58 pmx_led_rebuild: pmx-led-rebuild {
59 marvell,pins = "mpp36";
60 marvell,function = "gpio";
61 };
62 pmx_led_health: pmx-led_health {
63 marvell,pins = "mpp37";
64 marvell,function = "gpio";
65 };
66 pmx_led_sata_brt_ctrl_1: pmx-led-sata-brt-ctrl-1 {
67 marvell,pins = "mpp38";
68 marvell,function = "gpio";
69 };
70 pmx_led_sata_brt_ctrl_2: pmx-led-sata-brt-ctrl-2 {
71 marvell,pins = "mpp39";
72 marvell,function = "gpio";
73 };
74 pmx_led_backup_brt_ctrl_1: pmx-led-backup-brt-ctrl-1 {
75 marvell,pins = "mpp40";
76 marvell,function = "gpio";
77 };
78 pmx_led_backup_brt_ctrl_2: pmx-led-backup-brt-ctrl-2 {
79 marvell,pins = "mpp41";
80 marvell,function = "gpio";
81 };
82 pmx_led_power_brt_ctrl_1: pmx-led-power-brt-ctrl-1 {
83 marvell,pins = "mpp42";
84 marvell,function = "gpio";
85 };
86 pmx_led_power_brt_ctrl_2: pmx-led-power-brt-ctrl-2 {
87 marvell,pins = "mpp43";
88 marvell,function = "gpio";
89 };
90 pmx_led_health_brt_ctrl_1: pmx-led-health-brt-ctrl-1 {
91 marvell,pins = "mpp44";
92 marvell,function = "gpio";
93 };
94 pmx_led_health_brt_ctrl_2: pmx-led-health-brt-ctrl-2 {
95 marvell,pins = "mpp45";
96 marvell,function = "gpio";
97 };
98 pmx_led_rebuild_brt_ctrl_1: pmx-led-rebuild-brt-ctrl-1 {
99 marvell,pins = "mpp44";
100 marvell,function = "gpio";
101 };
102 pmx_led_rebuild_brt_ctrl_2: pmx-led-rebuild-brt-ctrl-2 {
103 marvell,pins = "mpp45";
104 marvell,function = "gpio";
105 };
106
107 };
19 i2c@11000 { 108 i2c@11000 {
20 status = "okay"; 109 status = "okay";
21 110
diff --git a/arch/arm/boot/dts/kirkwood-is2.dts b/arch/arm/boot/dts/kirkwood-is2.dts
new file mode 100644
index 000000000000..0bdce0ad7277
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-is2.dts
@@ -0,0 +1,30 @@
1/dts-v1/;
2
3/include/ "kirkwood-ns2-common.dtsi"
4
5/ {
6 model = "LaCie Internet Space v2";
7 compatible = "lacie,inetspace_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x8000000>;
12 };
13
14 ocp@f1000000 {
15 sata@80000 {
16 status = "okay";
17 nr-ports = <1>;
18 };
19 };
20
21 ns2-leds {
22 compatible = "lacie,ns2-leds";
23
24 blue-sata {
25 label = "ns2:blue:sata";
26 slow-gpio = <&gpio0 29 0>;
27 cmd-gpio = <&gpio0 30 0>;
28 };
29 };
30};
diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
index 75bdb93fed26..8db3123ac80f 100644
--- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
+++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
@@ -1,6 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3/include/ "kirkwood.dtsi"
4/include/ "kirkwood-98dx4122.dtsi"
4 5
5/ { 6/ {
6 model = "Keymile Kirkwood Reference Design"; 7 model = "Keymile Kirkwood Reference Design";
@@ -16,6 +17,22 @@
16 }; 17 };
17 18
18 ocp@f1000000 { 19 ocp@f1000000 {
20 pinctrl: pinctrl@10000 {
21
22 pinctrl-0 = < &pmx_nand &pmx_i2c_gpio_sda
23 &pmx_i2c_gpio_scl >;
24 pinctrl-names = "default";
25
26 pmx_i2c_gpio_sda: pmx-gpio-sda {
27 marvell,pins = "mpp8";
28 marvell,function = "gpio";
29 };
30 pmx_i2c_gpio_scl: pmx-gpio-scl {
31 marvell,pins = "mpp9";
32 marvell,function = "gpio";
33 };
34 };
35
19 serial@12000 { 36 serial@12000 {
20 clock-frequency = <200000000>; 37 clock-frequency = <200000000>;
21 status = "ok"; 38 status = "ok";
diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
index 8fea375c734d..37d45c4f88fb 100644
--- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi
+++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
@@ -1,4 +1,5 @@
1/include/ "kirkwood.dtsi" 1/include/ "kirkwood.dtsi"
2/include/ "kirkwood-6281.dtsi"
2 3
3/ { 4/ {
4 chosen { 5 chosen {
@@ -6,6 +7,71 @@
6 }; 7 };
7 8
8 ocp@f1000000 { 9 ocp@f1000000 {
10 pinctrl: pinctrl@10000 {
11
12 pinctrl-0 = < &pmx_power_hdd &pmx_usb_vbus
13 &pmx_fan_low &pmx_fan_high
14 &pmx_led_function_red &pmx_led_alarm
15 &pmx_led_info &pmx_led_power
16 &pmx_fan_lock &pmx_button_function
17 &pmx_power_switch &pmx_power_auto_switch
18 &pmx_led_function_blue >;
19 pinctrl-names = "default";
20
21 pmx_power_hdd: pmx-power-hdd {
22 marvell,pins = "mpp10";
23 marvell,function = "gpo";
24 };
25 pmx_usb_vbus: pmx-usb-vbus {
26 marvell,pins = "mpp11";
27 marvell,function = "gpio";
28 };
29 pmx_fan_high: pmx-fan-high {
30 marvell,pins = "mpp18";
31 marvell,function = "gpo";
32 };
33 pmx_fan_low: pmx-fan-low {
34 marvell,pins = "mpp19";
35 marvell,function = "gpo";
36 };
37 pmx_led_function_blue: pmx-led-function-blue {
38 marvell,pins = "mpp36";
39 marvell,function = "gpio";
40 };
41 pmx_led_alarm: pmx-led-alarm {
42 marvell,pins = "mpp37";
43 marvell,function = "gpio";
44 };
45 pmx_led_info: pmx-led-info {
46 marvell,pins = "mpp38";
47 marvell,function = "gpio";
48 };
49 pmx_led_power: pmx-led-power {
50 marvell,pins = "mpp39";
51 marvell,function = "gpio";
52 };
53 pmx_fan_lock: pmx-fan-lock {
54 marvell,pins = "mpp40";
55 marvell,function = "gpio";
56 };
57 pmx_button_function: pmx-button-function {
58 marvell,pins = "mpp41";
59 marvell,function = "gpio";
60 };
61 pmx_power_switch: pmx-power-switch {
62 marvell,pins = "mpp42";
63 marvell,function = "gpio";
64 };
65 pmx_power_auto_switch: pmx-power-auto-switch {
66 marvell,pins = "mpp43";
67 marvell,function = "gpio";
68 };
69 pmx_led_function_red: pmx-led-function_red {
70 marvell,pins = "mpp48";
71 marvell,function = "gpio";
72 };
73
74 };
9 sata@80000 { 75 sata@80000 {
10 status = "okay"; 76 status = "okay";
11 nr-ports = <1>; 77 nr-ports = <1>;
@@ -94,4 +160,44 @@
94 gpios = <&gpio1 16 1>; 160 gpios = <&gpio1 16 1>;
95 }; 161 };
96 }; 162 };
163
164 gpio_fan {
165 compatible = "gpio-fan";
166 gpios = <&gpio0 19 1
167 &gpio0 18 1>;
168 gpio-fan,speed-map = <0 3
169 1500 2
170 3250 1
171 5000 0>;
172 alarm-gpios = <&gpio1 8 0>;
173 };
174
175 regulators {
176 compatible = "simple-bus";
177 #address-cells = <1>;
178 #size-cells = <0>;
179
180 usb_power: regulator@1 {
181 compatible = "regulator-fixed";
182 reg = <1>;
183 regulator-name = "USB Power";
184 regulator-min-microvolt = <5000000>;
185 regulator-max-microvolt = <5000000>;
186 enable-active-high;
187 regulator-always-on;
188 regulator-boot-on;
189 gpio = <&gpio0 11 0>;
190 };
191 hdd_power: regulator@2 {
192 compatible = "regulator-fixed";
193 reg = <2>;
194 regulator-name = "HDD Power";
195 regulator-min-microvolt = <5000000>;
196 regulator-max-microvolt = <5000000>;
197 enable-active-high;
198 regulator-always-on;
199 regulator-boot-on;
200 gpio = <&gpio0 10 0>;
201 };
202 };
97}; 203};
diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
new file mode 100644
index 000000000000..262c65403760
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
@@ -0,0 +1,178 @@
1/dts-v1/;
2
3/include/ "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi"
5
6/ {
7 model = "MPL CEC4";
8 compatible = "mpl,cec4-10", "mpl,cec4", "marvell,kirkwood-88f6281", "marvell,kirkwood";
9
10 memory {
11 device_type = "memory";
12 reg = <0x00000000 0x20000000>;
13 };
14
15 chosen {
16 bootargs = "console=ttyS0,115200n8 earlyprintk";
17 };
18
19 ocp@f1000000 {
20 pinctrl: pinctrl@10000 {
21
22 pinctrl-0 = < &pmx_nand &pmx_uart0
23 &pmx_led_health &pmx_sdio
24 &pmx_sata0 &pmx_sata1
25 &pmx_led_user1o
26 &pmx_led_user1g &pmx_led_user0o
27 &pmx_led_user0g &pmx_led_misc
28 &pmx_sdio_cd
29 >;
30 pinctrl-names = "default";
31
32 pmx_led_health: pmx-led-health {
33 marvell,pins = "mpp7";
34 marvell,function = "gpo";
35 };
36
37 pmx_sata1: pmx-sata1 {
38 marvell,pins = "mpp34";
39 marvell,function = "sata1";
40 };
41
42 pmx_sata0: pmx-sata0 {
43 marvell,pins = "mpp35";
44 marvell,function = "sata0";
45 };
46
47 pmx_led_user1o: pmx-led-user1o {
48 marvell,pins = "mpp40";
49 marvell,function = "gpio";
50 };
51
52 pmx_led_user1g: pmx-led-user1g {
53 marvell,pins = "mpp41";
54 marvell,function = "gpio";
55 };
56
57 pmx_led_user0o: pmx-led-user0o {
58 marvell,pins = "mpp44";
59 marvell,function = "gpio";
60 };
61
62 pmx_led_user0g: pmx-led-user0g {
63 marvell,pins = "mpp45";
64 marvell,function = "gpio";
65 };
66
67 pmx_led_misc: pmx-led-misc {
68 marvell,pins = "mpp46";
69 marvell,function = "gpio";
70 };
71
72 pmx_sdio_cd: pmx-sdio-cd {
73 marvell,pins = "mpp47";
74 marvell,function = "gpio";
75 };
76 };
77
78 i2c@11000 {
79 status = "okay";
80
81 rtc@51 {
82 compatible = "nxp,pcf8563";
83 reg = <0x51>;
84 };
85
86 eeprom@57 {
87 compatible = "atmel,24c02";
88 reg = <0x57>;
89 };
90
91 };
92
93 serial@12000 {
94 clock-frequency = <200000000>;
95 status = "ok";
96 };
97
98 nand@3000000 {
99 status = "okay";
100
101 partition@0 {
102 label = "uboot";
103 reg = <0x0000000 0x100000>;
104 };
105
106 partition@100000 {
107 label = "env";
108 reg = <0x100000 0x80000>;
109 };
110
111 partition@180000 {
112 label = "fdt";
113 reg = <0x180000 0x80000>;
114 };
115
116 partition@200000 {
117 label = "kernel";
118 reg = <0x200000 0x400000>;
119 };
120
121 partition@600000 {
122 label = "rootfs";
123 reg = <0x600000 0x1fa00000>;
124 };
125 };
126
127 rtc@10300 {
128 status = "disabled";
129 };
130
131 sata@80000 {
132 nr-ports = <2>;
133 status = "okay";
134
135 };
136 };
137
138 gpio-leds {
139 compatible = "gpio-leds";
140
141 health {
142 label = "status:green:health";
143 gpios = <&gpio0 7 1>;
144 };
145
146 user1o {
147 label = "user1:orange";
148 gpios = <&gpio1 8 1>;
149 default-state = "on";
150 };
151
152 user1g {
153 label = "user1:green";
154 gpios = <&gpio1 9 1>;
155 default-state = "on";
156 };
157
158 user0o {
159 label = "user0:orange";
160 gpios = <&gpio1 12 1>;
161 default-state = "on";
162 };
163
164 user0g {
165 label = "user0:green";
166 gpios = <&gpio1 13 1>;
167 default-state = "on";
168 };
169
170 misc {
171 label = "status:orange:misc";
172 gpios = <&gpio1 14 1>;
173 default-state = "on";
174 };
175
176 };
177};
178
diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
new file mode 100644
index 000000000000..9bc6785ad228
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
@@ -0,0 +1,63 @@
1/include/ "kirkwood.dtsi"
2
3/ {
4 chosen {
5 bootargs = "console=ttyS0,115200n8";
6 };
7
8 ocp@f1000000 {
9 serial@12000 {
10 clock-frequency = <166666667>;
11 status = "okay";
12 };
13
14 spi@10600 {
15 status = "okay";
16
17 flash@0 {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 compatible = "mx25l4005a";
21 reg = <0>;
22 spi-max-frequency = <20000000>;
23 mode = <0>;
24
25 partition@0 {
26 reg = <0x0 0x80000>;
27 label = "u-boot";
28 };
29 };
30 };
31
32 i2c@11000 {
33 status = "okay";
34
35 eeprom@50 {
36 compatible = "at,24c04";
37 pagesize = <16>;
38 reg = <0x50>;
39 };
40 };
41 };
42
43 gpio_keys {
44 compatible = "gpio-keys";
45 #address-cells = <1>;
46 #size-cells = <0>;
47
48 button@1 {
49 label = "Power push button";
50 linux,code = <116>;
51 gpios = <&gpio1 0 0>;
52 };
53 };
54
55 gpio-leds {
56 compatible = "gpio-leds";
57
58 red-fail {
59 label = "ns2:red:fail";
60 gpios = <&gpio0 12 0>;
61 };
62 };
63};
diff --git a/arch/arm/boot/dts/kirkwood-ns2.dts b/arch/arm/boot/dts/kirkwood-ns2.dts
new file mode 100644
index 000000000000..f2d36ecf36d8
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ns2.dts
@@ -0,0 +1,30 @@
1/dts-v1/;
2
3/include/ "kirkwood-ns2-common.dtsi"
4
5/ {
6 model = "LaCie Network Space v2";
7 compatible = "lacie,netspace_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x10000000>;
12 };
13
14 ocp@f1000000 {
15 sata@80000 {
16 status = "okay";
17 nr-ports = <1>;
18 };
19 };
20
21 ns2-leds {
22 compatible = "lacie,ns2-leds";
23
24 blue-sata {
25 label = "ns2:blue:sata";
26 slow-gpio = <&gpio0 29 0>;
27 cmd-gpio = <&gpio0 30 0>;
28 };
29 };
30};
diff --git a/arch/arm/boot/dts/kirkwood-ns2lite.dts b/arch/arm/boot/dts/kirkwood-ns2lite.dts
new file mode 100644
index 000000000000..b02eb4ea1bb4
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ns2lite.dts
@@ -0,0 +1,30 @@
1/dts-v1/;
2
3/include/ "kirkwood-ns2-common.dtsi"
4
5/ {
6 model = "LaCie Network Space Lite v2";
7 compatible = "lacie,netspace_lite_v2", "marvell,kirkwood-88f6192", "marvell,kirkwood";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x8000000>;
12 };
13
14 ocp@f1000000 {
15 sata@80000 {
16 status = "okay";
17 nr-ports = <1>;
18 };
19 };
20
21 gpio-leds {
22 compatible = "gpio-leds";
23
24 blue-sata {
25 label = "ns2:blue:sata";
26 gpios = <&gpio0 30 1>;
27 linux,default-trigger = "default-on";
28 };
29 };
30};
diff --git a/arch/arm/boot/dts/kirkwood-ns2max.dts b/arch/arm/boot/dts/kirkwood-ns2max.dts
new file mode 100644
index 000000000000..bcec4d6cada7
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ns2max.dts
@@ -0,0 +1,49 @@
1/dts-v1/;
2
3/include/ "kirkwood-ns2-common.dtsi"
4
5/ {
6 model = "LaCie Network Space Max v2";
7 compatible = "lacie,netspace_max_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x10000000>;
12 };
13
14 ocp@f1000000 {
15 sata@80000 {
16 status = "okay";
17 nr-ports = <2>;
18 };
19 };
20
21 gpio_fan {
22 compatible = "gpio-fan";
23 gpios = <&gpio0 22 1
24 &gpio0 7 1
25 &gpio1 1 1
26 &gpio0 23 1>;
27 gpio-fan,speed-map =
28 < 0 0
29 1500 15
30 1700 14
31 1800 13
32 2100 12
33 3100 11
34 3300 10
35 4300 9
36 5500 8>;
37 alarm-gpios = <&gpio0 25 1>;
38 };
39
40 ns2-leds {
41 compatible = "lacie,ns2-leds";
42
43 blue-sata {
44 label = "ns2:blue:sata";
45 slow-gpio = <&gpio0 29 0>;
46 cmd-gpio = <&gpio0 30 0>;
47 };
48 };
49};
diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/kirkwood-ns2mini.dts
new file mode 100644
index 000000000000..b79f5eb25589
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ns2mini.dts
@@ -0,0 +1,49 @@
1/dts-v1/;
2
3/include/ "kirkwood-ns2-common.dtsi"
4
5/ {
6 model = "LaCie Network Space Mini v2";
7 compatible = "lacie,netspace_mini_v2", "marvell,kirkwood-88f6192", "marvell,kirkwood";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x8000000>;
12 };
13
14 ocp@f1000000 {
15 sata@80000 {
16 status = "okay";
17 nr-ports = <1>;
18 };
19 };
20
21 gpio_fan {
22 compatible = "gpio-fan";
23 gpios = <&gpio0 22 1
24 &gpio0 7 1
25 &gpio1 1 1
26 &gpio0 23 1>;
27 gpio-fan,speed-map =
28 < 0 0
29 3000 15
30 3180 14
31 4140 13
32 4570 12
33 6760 11
34 7140 10
35 7980 9
36 9200 8>;
37 alarm-gpios = <&gpio0 25 1>;
38 };
39
40 ns2-leds {
41 compatible = "lacie,ns2-leds";
42
43 blue-sata {
44 label = "ns2:blue:sata";
45 slow-gpio = <&gpio0 29 0>;
46 cmd-gpio = <&gpio0 30 0>;
47 };
48 };
49};
diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts
new file mode 100644
index 000000000000..5509f9659546
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-nsa310.dts
@@ -0,0 +1,144 @@
1/dts-v1/;
2
3/include/ "kirkwood.dtsi"
4
5/ {
6 model = "ZyXEL NSA310";
7 compatible = "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x10000000>;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,115200";
16 };
17
18 ocp@f1000000 {
19
20 serial@12000 {
21 clock-frequency = <200000000>;
22 status = "ok";
23 };
24
25 sata@80000 {
26 status = "okay";
27 nr-ports = <2>;
28 };
29
30 i2c@11000 {
31 status = "okay";
32 };
33
34 nand@3000000 {
35 status = "okay";
36 chip-delay = <35>;
37
38 partition@0 {
39 label = "uboot";
40 reg = <0x0000000 0x0100000>;
41 read-only;
42 };
43 partition@100000 {
44 label = "uboot_env";
45 reg = <0x0100000 0x0080000>;
46 };
47 partition@180000 {
48 label = "key_store";
49 reg = <0x0180000 0x0080000>;
50 };
51 partition@200000 {
52 label = "info";
53 reg = <0x0200000 0x0080000>;
54 };
55 partition@280000 {
56 label = "etc";
57 reg = <0x0280000 0x0a00000>;
58 };
59 partition@c80000 {
60 label = "kernel_1";
61 reg = <0x0c80000 0x0a00000>;
62 };
63 partition@1680000 {
64 label = "rootfs1";
65 reg = <0x1680000 0x2fc0000>;
66 };
67 partition@4640000 {
68 label = "kernel_2";
69 reg = <0x4640000 0x0a00000>;
70 };
71 partition@5040000 {
72 label = "rootfs2";
73 reg = <0x5040000 0x2fc0000>;
74 };
75 };
76 };
77
78 gpio_keys {
79 compatible = "gpio-keys";
80 #address-cells = <1>;
81 #size-cells = <0>;
82
83 button@1 {
84 label = "Power Button";
85 linux,code = <116>;
86 gpios = <&gpio1 14 0>;
87 };
88 button@2 {
89 label = "Copy Button";
90 linux,code = <133>;
91 gpios = <&gpio1 5 1>;
92 };
93 button@3 {
94 label = "Reset Button";
95 linux,code = <0x198>;
96 gpios = <&gpio1 4 1>;
97 };
98 };
99
100 gpio-leds {
101 compatible = "gpio-leds";
102
103 green-sys {
104 label = "nsa310:green:sys";
105 gpios = <&gpio0 28 0>;
106 };
107 red-sys {
108 label = "nsa310:red:sys";
109 gpios = <&gpio0 29 0>;
110 };
111 green-hdd {
112 label = "nsa310:green:hdd";
113 gpios = <&gpio1 9 0>;
114 };
115 red-hdd {
116 label = "nsa310:red:hdd";
117 gpios = <&gpio1 10 0>;
118 };
119 green-esata {
120 label = "nsa310:green:esata";
121 gpios = <&gpio0 12 0>;
122 };
123 red-esata {
124 label = "nsa310:red:esata";
125 gpios = <&gpio0 13 0>;
126 };
127 green-usb {
128 label = "nsa310:green:usb";
129 gpios = <&gpio0 15 0>;
130 };
131 red-usb {
132 label = "nsa310:red:usb";
133 gpios = <&gpio0 16 0>;
134 };
135 green-copy {
136 label = "nsa310:green:copy";
137 gpios = <&gpio1 7 0>;
138 };
139 red-copy {
140 label = "nsa310:red:copy";
141 gpios = <&gpio1 8 0>;
142 };
143 };
144};
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
new file mode 100644
index 000000000000..49d3d74d4d38
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
@@ -0,0 +1,98 @@
1/dts-v1/;
2
3/include/ "kirkwood.dtsi"
4/include/ "kirkwood-6282.dtsi"
5
6/ {
7 model = "Plat'Home OpenBlocksA6";
8 compatible = "plathome,openblocks-a6", "marvell,kirkwood-88f6283", "marvell,kirkwood";
9
10 memory {
11 device_type = "memory";
12 reg = <0x00000000 0x20000000>;
13 };
14
15 chosen {
16 bootargs = "console=ttyS0,115200n8 earlyprintk";
17 };
18
19 ocp@f1000000 {
20 serial@12000 {
21 clock-frequency = <200000000>;
22 status = "ok";
23 };
24
25 serial@12100 {
26 clock-frequency = <200000000>;
27 status = "ok";
28 };
29
30 nand@3000000 {
31 chip-delay = <25>;
32 status = "okay";
33
34 partition@0 {
35 label = "uboot";
36 reg = <0x0 0x90000>;
37 };
38
39 partition@90000 {
40 label = "env";
41 reg = <0x90000 0x44000>;
42 };
43
44 partition@d4000 {
45 label = "test";
46 reg = <0xd4000 0x24000>;
47 };
48
49 partition@f4000 {
50 label = "conf";
51 reg = <0xf4000 0x400000>;
52 };
53
54 partition@4f4000 {
55 label = "linux";
56 reg = <0x4f4000 0x1d20000>;
57 };
58
59 partition@2214000 {
60 label = "user";
61 reg = <0x2214000 0x1dec000>;
62 };
63 };
64
65 sata@80000 {
66 nr-ports = <1>;
67 status = "okay";
68 };
69
70 i2c@11100 {
71 status = "okay";
72
73 s35390a: s35390a@30 {
74 compatible = "s35390a";
75 reg = <0x30>;
76 };
77 };
78 };
79
80 gpio-leds {
81 compatible = "gpio-leds";
82
83 led-red {
84 label = "obsa6:red:stat";
85 gpios = <&gpio1 9 1>;
86 };
87
88 led-green {
89 label = "obsa6:green:stat";
90 gpios = <&gpio1 10 1>;
91 };
92
93 led-yellow {
94 label = "obsa6:yellow:stat";
95 gpios = <&gpio1 11 1>;
96 };
97 };
98};
diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts
new file mode 100644
index 000000000000..cd15452a52a6
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-topkick.dts
@@ -0,0 +1,102 @@
1/dts-v1/;
2
3/include/ "kirkwood.dtsi"
4
5/ {
6 model = "Univeral Scientific Industrial Co. Topkick-1281P2";
7 compatible = "usi,topkick-1281P2", "usi,topkick", "marvell,kirkwood-88f6282", "marvell,kirkwood";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x10000000>;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,115200n8 earlyprintk";
16 };
17
18 ocp@f1000000 {
19 serial@12000 {
20 clock-frequency = <200000000>;
21 status = "ok";
22 };
23
24 nand@3000000 {
25 status = "okay";
26
27 partition@0 {
28 label = "u-boot";
29 reg = <0x0000000 0x180000>;
30 };
31
32 partition@180000 {
33 label = "u-boot env";
34 reg = <0x0180000 0x20000>;
35 };
36
37 partition@200000 {
38 label = "uImage";
39 reg = <0x0200000 0x600000>;
40 };
41
42 partition@800000 {
43 label = "uInitrd";
44 reg = <0x0800000 0x1000000>;
45 };
46
47 partition@1800000 {
48 label = "rootfs";
49 reg = <0x1800000 0xe800000>;
50 };
51 };
52
53 sata@80000 {
54 status = "okay";
55 nr-ports = <1>;
56 };
57 };
58
59 gpio-leds {
60 compatible = "gpio-leds";
61
62 disk {
63 label = "topkick:yellow:disk";
64 gpios = <&gpio0 21 1>;
65 linux,default-trigger = "ide-disk";
66 };
67 system2 {
68 label = "topkick:red:system";
69 gpios = <&gpio1 5 1>;
70 };
71 system {
72 label = "topkick:blue:system";
73 gpios = <&gpio1 6 1>;
74 default-state = "on";
75 };
76 wifi {
77 label = "topkick:green:wifi";
78 gpios = <&gpio1 7 1>;
79 };
80 wifi2 {
81 label = "topkick:yellow:wifi";
82 gpios = <&gpio1 16 1>;
83 };
84 };
85 regulators {
86 compatible = "simple-bus";
87 #address-cells = <1>;
88 #size-cells = <0>;
89
90 sata0_power: regulator@1 {
91 compatible = "regulator-fixed";
92 reg = <1>;
93 regulator-name = "SATA0 Power";
94 regulator-min-microvolt = <5000000>;
95 regulator-max-microvolt = <5000000>;
96 enable-active-high;
97 regulator-always-on;
98 regulator-boot-on;
99 gpio = <&gpio1 4 0>;
100 };
101 };
102};
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
index ccbf32757800..8295c833887f 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
@@ -1,8 +1,39 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood-ts219.dtsi" 3/include/ "kirkwood-ts219.dtsi"
4/include/ "kirkwood-6281.dtsi"
4 5
5/ { 6/ {
7 ocp@f1000000 {
8 pinctrl: pinctrl@10000 {
9
10 pinctrl-0 = < &pmx_uart0 &pmx_uart1 &pmx_spi
11 &pmx_twsi0 &pmx_sata0 &pmx_sata1
12 &pmx_ram_size &pmx_reset_button
13 &pmx_USB_copy_button &pmx_board_id>;
14 pinctrl-names = "default";
15
16 pmx_ram_size: pmx-ram-size {
17 /* RAM: 0: 256 MB, 1: 512 MB */
18 marvell,pins = "mpp36";
19 marvell,function = "gpio";
20 };
21 pmx_USB_copy_button: pmx-USB-copy-button {
22 marvell,pins = "mpp15";
23 marvell,function = "gpio";
24 };
25 pmx_reset_button: pmx-reset-button {
26 marvell,pins = "mpp16";
27 marvell,function = "gpio";
28 };
29 pmx_board_id: pmx-board-id {
30 /* 0: TS-11x, 1: TS-21x */
31 marvell,pins = "mpp44";
32 marvell,function = "gpio";
33 };
34 };
35 };
36
6 gpio_keys { 37 gpio_keys {
7 compatible = "gpio-keys"; 38 compatible = "gpio-keys";
8 #address-cells = <1>; 39 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
index fbe9932161a1..df3f95dfba33 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
@@ -1,8 +1,39 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood-ts219.dtsi" 3/include/ "kirkwood-ts219.dtsi"
4/include/ "kirkwood-6282.dtsi"
4 5
5/ { 6/ {
7 ocp@f1000000 {
8 pinctrl: pinctrl@10000 {
9
10 pinctrl-0 = < &pmx_uart0 &pmx_uart1 &pmx_spi
11 &pmx_twsi0 &pmx_sata0 &pmx_sata1
12 &pmx_ram_size &pmx_reset_button
13 &pmx_USB_copy_button &pmx_board_id>;
14 pinctrl-names = "default";
15
16 pmx_ram_size: pmx-ram-size {
17 /* RAM: 0: 256 MB, 1: 512 MB */
18 marvell,pins = "mpp36";
19 marvell,function = "gpio";
20 };
21 pmx_reset_button: pmx-reset-button {
22 marvell,pins = "mpp37";
23 marvell,function = "gpio";
24 };
25 pmx_USB_copy_button: pmx-USB-copy-button {
26 marvell,pins = "mpp43";
27 marvell,function = "gpio";
28 };
29 pmx_board_id: pmx-board-id {
30 /* 0: TS-11x, 1: TS-21x */
31 marvell,pins = "mpp44";
32 marvell,function = "gpio";
33 };
34 };
35 };
36
6 gpio_keys { 37 gpio_keys {
7 compatible = "gpio-keys"; 38 compatible = "gpio-keys";
8 #address-cells = <1>; 39 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 4e5b8154a5be..110d6cbb795b 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -4,6 +4,10 @@
4 compatible = "marvell,kirkwood"; 4 compatible = "marvell,kirkwood";
5 interrupt-parent = <&intc>; 5 interrupt-parent = <&intc>;
6 6
7 aliases {
8 gpio0 = &gpio0;
9 gpio1 = &gpio1;
10 };
7 intc: interrupt-controller { 11 intc: interrupt-controller {
8 compatible = "marvell,orion-intc", "marvell,intc"; 12 compatible = "marvell,orion-intc", "marvell,intc";
9 interrupt-controller; 13 interrupt-controller;
@@ -19,12 +23,19 @@
19 #address-cells = <1>; 23 #address-cells = <1>;
20 #size-cells = <1>; 24 #size-cells = <1>;
21 25
26 core_clk: core-clocks@10030 {
27 compatible = "marvell,kirkwood-core-clock";
28 reg = <0x10030 0x4>;
29 #clock-cells = <1>;
30 };
31
22 gpio0: gpio@10100 { 32 gpio0: gpio@10100 {
23 compatible = "marvell,orion-gpio"; 33 compatible = "marvell,orion-gpio";
24 #gpio-cells = <2>; 34 #gpio-cells = <2>;
25 gpio-controller; 35 gpio-controller;
26 reg = <0x10100 0x40>; 36 reg = <0x10100 0x40>;
27 ngpio = <32>; 37 ngpios = <32>;
38 interrupt-controller;
28 interrupts = <35>, <36>, <37>, <38>; 39 interrupts = <35>, <36>, <37>, <38>;
29 }; 40 };
30 41
@@ -33,7 +44,8 @@
33 #gpio-cells = <2>; 44 #gpio-cells = <2>;
34 gpio-controller; 45 gpio-controller;
35 reg = <0x10140 0x40>; 46 reg = <0x10140 0x40>;
36 ngpio = <18>; 47 ngpios = <18>;
48 interrupt-controller;
37 interrupts = <39>, <40>, <41>; 49 interrupts = <39>, <40>, <41>;
38 }; 50 };
39 51
@@ -42,6 +54,7 @@
42 reg = <0x12000 0x100>; 54 reg = <0x12000 0x100>;
43 reg-shift = <2>; 55 reg-shift = <2>;
44 interrupts = <33>; 56 interrupts = <33>;
57 clocks = <&gate_clk 7>;
45 /* set clock-frequency in board dts */ 58 /* set clock-frequency in board dts */
46 status = "disabled"; 59 status = "disabled";
47 }; 60 };
@@ -51,6 +64,7 @@
51 reg = <0x12100 0x100>; 64 reg = <0x12100 0x100>;
52 reg-shift = <2>; 65 reg-shift = <2>;
53 interrupts = <34>; 66 interrupts = <34>;
67 clocks = <&gate_clk 7>;
54 /* set clock-frequency in board dts */ 68 /* set clock-frequency in board dts */
55 status = "disabled"; 69 status = "disabled";
56 }; 70 };
@@ -68,12 +82,69 @@
68 cell-index = <0>; 82 cell-index = <0>;
69 interrupts = <23>; 83 interrupts = <23>;
70 reg = <0x10600 0x28>; 84 reg = <0x10600 0x28>;
85 clocks = <&gate_clk 7>;
71 status = "disabled"; 86 status = "disabled";
72 }; 87 };
73 88
89 gate_clk: clock-gating-control@2011c {
90 compatible = "marvell,kirkwood-gating-clock";
91 reg = <0x2011c 0x4>;
92 clocks = <&core_clk 0>;
93 #clock-cells = <1>;
94 };
95
74 wdt@20300 { 96 wdt@20300 {
75 compatible = "marvell,orion-wdt"; 97 compatible = "marvell,orion-wdt";
76 reg = <0x20300 0x28>; 98 reg = <0x20300 0x28>;
99 clocks = <&gate_clk 7>;
100 status = "okay";
101 };
102
103 xor@60800 {
104 compatible = "marvell,orion-xor";
105 reg = <0x60800 0x100
106 0x60A00 0x100>;
107 status = "okay";
108 clocks = <&gate_clk 8>;
109
110 xor00 {
111 interrupts = <5>;
112 dmacap,memcpy;
113 dmacap,xor;
114 };
115 xor01 {
116 interrupts = <6>;
117 dmacap,memcpy;
118 dmacap,xor;
119 dmacap,memset;
120 };
121 };
122
123 xor@60900 {
124 compatible = "marvell,orion-xor";
125 reg = <0x60900 0x100
126 0xd0B00 0x100>;
127 status = "okay";
128 clocks = <&gate_clk 16>;
129
130 xor00 {
131 interrupts = <7>;
132 dmacap,memcpy;
133 dmacap,xor;
134 };
135 xor01 {
136 interrupts = <8>;
137 dmacap,memcpy;
138 dmacap,xor;
139 dmacap,memset;
140 };
141 };
142
143 ehci@50000 {
144 compatible = "marvell,orion-ehci";
145 reg = <0x50000 0x1000>;
146 interrupts = <19>;
147 clocks = <&gate_clk 3>;
77 status = "okay"; 148 status = "okay";
78 }; 149 };
79 150
@@ -81,6 +152,8 @@
81 compatible = "marvell,orion-sata"; 152 compatible = "marvell,orion-sata";
82 reg = <0x80000 0x5000>; 153 reg = <0x80000 0x5000>;
83 interrupts = <21>; 154 interrupts = <21>;
155 clocks = <&gate_clk 14>, <&gate_clk 15>;
156 clock-names = "0", "1";
84 status = "disabled"; 157 status = "disabled";
85 }; 158 };
86 159
@@ -94,6 +167,7 @@
94 reg = <0x3000000 0x400>; 167 reg = <0x3000000 0x400>;
95 chip-delay = <25>; 168 chip-delay = <25>;
96 /* set partition map and/or chip-delay in board dts */ 169 /* set partition map and/or chip-delay in board dts */
170 clocks = <&gate_clk 7>;
97 status = "disabled"; 171 status = "disabled";
98 }; 172 };
99 173
@@ -104,6 +178,7 @@
104 #size-cells = <0>; 178 #size-cells = <0>;
105 interrupts = <29>; 179 interrupts = <29>;
106 clock-frequency = <100000>; 180 clock-frequency = <100000>;
181 clocks = <&gate_clk 7>;
107 status = "disabled"; 182 status = "disabled";
108 }; 183 };
109 184
@@ -113,6 +188,7 @@
113 <0xf5000000 0x800>; 188 <0xf5000000 0x800>;
114 reg-names = "regs", "sram"; 189 reg-names = "regs", "sram";
115 interrupts = <22>; 190 interrupts = <22>;
191 clocks = <&gate_clk 17>;
116 status = "okay"; 192 status = "okay";
117 }; 193 };
118 }; 194 };
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index e5ffe960dbf3..1582f484a867 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -182,6 +182,13 @@
182 pnx,timeout = <0x64>; 182 pnx,timeout = <0x64>;
183 }; 183 };
184 184
185 mpwm: mpwm@400E8000 {
186 compatible = "nxp,lpc3220-motor-pwm";
187 reg = <0x400E8000 0x78>;
188 status = "disabled";
189 #pwm-cells = <2>;
190 };
191
185 i2cusb: i2c@31020300 { 192 i2cusb: i2c@31020300 {
186 compatible = "nxp,pnx-i2c"; 193 compatible = "nxp,pnx-i2c";
187 reg = <0x31020300 0x100>; 194 reg = <0x31020300 0x100>;
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 581cb081cb0f..761c4b69b25b 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -12,6 +12,7 @@
12 12
13/ { 13/ {
14 compatible = "ti,omap2430", "ti,omap2420", "ti,omap2"; 14 compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
15 interrupt-parent = <&intc>;
15 16
16 aliases { 17 aliases {
17 serial0 = &uart1; 18 serial0 = &uart1;
@@ -65,5 +66,90 @@
65 ti,hwmods = "uart3"; 66 ti,hwmods = "uart3";
66 clock-frequency = <48000000>; 67 clock-frequency = <48000000>;
67 }; 68 };
69
70 timer2: timer@4802a000 {
71 compatible = "ti,omap2-timer";
72 reg = <0x4802a000 0x400>;
73 interrupts = <38>;
74 ti,hwmods = "timer2";
75 };
76
77 timer3: timer@48078000 {
78 compatible = "ti,omap2-timer";
79 reg = <0x48078000 0x400>;
80 interrupts = <39>;
81 ti,hwmods = "timer3";
82 };
83
84 timer4: timer@4807a000 {
85 compatible = "ti,omap2-timer";
86 reg = <0x4807a000 0x400>;
87 interrupts = <40>;
88 ti,hwmods = "timer4";
89 };
90
91 timer5: timer@4807c000 {
92 compatible = "ti,omap2-timer";
93 reg = <0x4807c000 0x400>;
94 interrupts = <41>;
95 ti,hwmods = "timer5";
96 ti,timer-dsp;
97 };
98
99 timer6: timer@4807e000 {
100 compatible = "ti,omap2-timer";
101 reg = <0x4807e000 0x400>;
102 interrupts = <42>;
103 ti,hwmods = "timer6";
104 ti,timer-dsp;
105 };
106
107 timer7: timer@48080000 {
108 compatible = "ti,omap2-timer";
109 reg = <0x48080000 0x400>;
110 interrupts = <43>;
111 ti,hwmods = "timer7";
112 ti,timer-dsp;
113 };
114
115 timer8: timer@48082000 {
116 compatible = "ti,omap2-timer";
117 reg = <0x48082000 0x400>;
118 interrupts = <44>;
119 ti,hwmods = "timer8";
120 ti,timer-dsp;
121 };
122
123 timer9: timer@48084000 {
124 compatible = "ti,omap2-timer";
125 reg = <0x48084000 0x400>;
126 interrupts = <45>;
127 ti,hwmods = "timer9";
128 ti,timer-pwm;
129 };
130
131 timer10: timer@48086000 {
132 compatible = "ti,omap2-timer";
133 reg = <0x48086000 0x400>;
134 interrupts = <46>;
135 ti,hwmods = "timer10";
136 ti,timer-pwm;
137 };
138
139 timer11: timer@48088000 {
140 compatible = "ti,omap2-timer";
141 reg = <0x48088000 0x400>;
142 interrupts = <47>;
143 ti,hwmods = "timer11";
144 ti,timer-pwm;
145 };
146
147 timer12: timer@4808a000 {
148 compatible = "ti,omap2-timer";
149 reg = <0x4808a000 0x400>;
150 interrupts = <48>;
151 ti,hwmods = "timer12";
152 ti,timer-pwm;
153 };
68 }; 154 };
69}; 155};
diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts
index 77b84e17c477..9b0d07746cba 100644
--- a/arch/arm/boot/dts/omap2420-h4.dts
+++ b/arch/arm/boot/dts/omap2420-h4.dts
@@ -15,6 +15,6 @@
15 15
16 memory { 16 memory {
17 device_type = "memory"; 17 device_type = "memory";
18 reg = <0x80000000 0x84000000>; /* 64 MB */ 18 reg = <0x80000000 0x4000000>; /* 64 MB */
19 }; 19 };
20}; 20};
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index bfd76b4a0ddc..af6560908905 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -14,6 +14,12 @@
14 compatible = "ti,omap2420", "ti,omap2"; 14 compatible = "ti,omap2420", "ti,omap2";
15 15
16 ocp { 16 ocp {
17 counter32k: counter@48004000 {
18 compatible = "ti,omap-counter32k";
19 reg = <0x48004000 0x20>;
20 ti,hwmods = "counter_32k";
21 };
22
17 omap2420_pmx: pinmux@48000030 { 23 omap2420_pmx: pinmux@48000030 {
18 compatible = "ti,omap2420-padconf", "pinctrl-single"; 24 compatible = "ti,omap2420-padconf", "pinctrl-single";
19 reg = <0x48000030 0x0113>; 25 reg = <0x48000030 0x0113>;
@@ -30,7 +36,6 @@
30 interrupts = <59>, /* TX interrupt */ 36 interrupts = <59>, /* TX interrupt */
31 <60>; /* RX interrupt */ 37 <60>; /* RX interrupt */
32 interrupt-names = "tx", "rx"; 38 interrupt-names = "tx", "rx";
33 interrupt-parent = <&intc>;
34 ti,hwmods = "mcbsp1"; 39 ti,hwmods = "mcbsp1";
35 }; 40 };
36 41
@@ -41,8 +46,15 @@
41 interrupts = <62>, /* TX interrupt */ 46 interrupts = <62>, /* TX interrupt */
42 <63>; /* RX interrupt */ 47 <63>; /* RX interrupt */
43 interrupt-names = "tx", "rx"; 48 interrupt-names = "tx", "rx";
44 interrupt-parent = <&intc>;
45 ti,hwmods = "mcbsp2"; 49 ti,hwmods = "mcbsp2";
46 }; 50 };
51
52 timer1: timer@48028000 {
53 compatible = "ti,omap2-timer";
54 reg = <0x48028000 0x400>;
55 interrupts = <37>;
56 ti,hwmods = "timer1";
57 ti,timer-alwon;
58 };
47 }; 59 };
48}; 60};
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 4565d9750f4d..c3924457c9b6 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -14,6 +14,12 @@
14 compatible = "ti,omap2430", "ti,omap2"; 14 compatible = "ti,omap2430", "ti,omap2";
15 15
16 ocp { 16 ocp {
17 counter32k: counter@49020000 {
18 compatible = "ti,omap-counter32k";
19 reg = <0x49020000 0x20>;
20 ti,hwmods = "counter_32k";
21 };
22
17 omap2430_pmx: pinmux@49002030 { 23 omap2430_pmx: pinmux@49002030 {
18 compatible = "ti,omap2430-padconf", "pinctrl-single"; 24 compatible = "ti,omap2430-padconf", "pinctrl-single";
19 reg = <0x49002030 0x0154>; 25 reg = <0x49002030 0x0154>;
@@ -32,7 +38,6 @@
32 <60>, /* RX interrupt */ 38 <60>, /* RX interrupt */
33 <61>; /* RX overflow interrupt */ 39 <61>; /* RX overflow interrupt */
34 interrupt-names = "common", "tx", "rx", "rx_overflow"; 40 interrupt-names = "common", "tx", "rx", "rx_overflow";
35 interrupt-parent = <&intc>;
36 ti,buffer-size = <128>; 41 ti,buffer-size = <128>;
37 ti,hwmods = "mcbsp1"; 42 ti,hwmods = "mcbsp1";
38 }; 43 };
@@ -45,7 +50,6 @@
45 <62>, /* TX interrupt */ 50 <62>, /* TX interrupt */
46 <63>; /* RX interrupt */ 51 <63>; /* RX interrupt */
47 interrupt-names = "common", "tx", "rx"; 52 interrupt-names = "common", "tx", "rx";
48 interrupt-parent = <&intc>;
49 ti,buffer-size = <128>; 53 ti,buffer-size = <128>;
50 ti,hwmods = "mcbsp2"; 54 ti,hwmods = "mcbsp2";
51 }; 55 };
@@ -58,7 +62,6 @@
58 <89>, /* TX interrupt */ 62 <89>, /* TX interrupt */
59 <90>; /* RX interrupt */ 63 <90>; /* RX interrupt */
60 interrupt-names = "common", "tx", "rx"; 64 interrupt-names = "common", "tx", "rx";
61 interrupt-parent = <&intc>;
62 ti,buffer-size = <128>; 65 ti,buffer-size = <128>;
63 ti,hwmods = "mcbsp3"; 66 ti,hwmods = "mcbsp3";
64 }; 67 };
@@ -71,7 +74,6 @@
71 <54>, /* TX interrupt */ 74 <54>, /* TX interrupt */
72 <55>; /* RX interrupt */ 75 <55>; /* RX interrupt */
73 interrupt-names = "common", "tx", "rx"; 76 interrupt-names = "common", "tx", "rx";
74 interrupt-parent = <&intc>;
75 ti,buffer-size = <128>; 77 ti,buffer-size = <128>;
76 ti,hwmods = "mcbsp4"; 78 ti,hwmods = "mcbsp4";
77 }; 79 };
@@ -84,9 +86,16 @@
84 <81>, /* TX interrupt */ 86 <81>, /* TX interrupt */
85 <82>; /* RX interrupt */ 87 <82>; /* RX interrupt */
86 interrupt-names = "common", "tx", "rx"; 88 interrupt-names = "common", "tx", "rx";
87 interrupt-parent = <&intc>;
88 ti,buffer-size = <128>; 89 ti,buffer-size = <128>;
89 ti,hwmods = "mcbsp5"; 90 ti,hwmods = "mcbsp5";
90 }; 91 };
92
93 timer1: timer@49018000 {
94 compatible = "ti,omap2-timer";
95 reg = <0x49018000 0x400>;
96 interrupts = <37>;
97 ti,hwmods = "timer1";
98 ti,timer-alwon;
99 };
91 }; 100 };
92}; 101};
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index c38cf76df81f..3705a81c1fc2 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -55,12 +55,6 @@
55 interrupts = <7>; /* SYS_NIRQ cascaded to intc */ 55 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
56 interrupt-parent = <&intc>; 56 interrupt-parent = <&intc>;
57 57
58 vsim: regulator-vsim {
59 compatible = "ti,twl4030-vsim";
60 regulator-min-microvolt = <1800000>;
61 regulator-max-microvolt = <3000000>;
62 };
63
64 twl_audio: audio { 58 twl_audio: audio {
65 compatible = "ti,twl4030-audio"; 59 compatible = "ti,twl4030-audio";
66 codec { 60 codec {
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
new file mode 100644
index 000000000000..f624dc85d441
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -0,0 +1,67 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "omap3.dtsi"
11
12/ {
13 model = "TI OMAP3 BeagleBoard";
14 compatible = "ti,omap3-beagle", "ti,omap3";
15
16 memory {
17 device_type = "memory";
18 reg = <0x80000000 0x10000000>; /* 256 MB */
19 };
20
21 leds {
22 compatible = "gpio-leds";
23 pmu_stat {
24 label = "beagleboard::pmu_stat";
25 gpios = <&twl_gpio 19 0>; /* LEDB */
26 };
27
28 heartbeat {
29 label = "beagleboard::usr0";
30 gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
31 linux,default-trigger = "heartbeat";
32 };
33
34 mmc {
35 label = "beagleboard::usr1";
36 gpios = <&gpio5 21 0>; /* 149 -> D7 LED */
37 linux,default-trigger = "mmc0";
38 };
39 };
40
41};
42
43&i2c1 {
44 clock-frequency = <2600000>;
45
46 twl: twl@48 {
47 reg = <0x48>;
48 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
49 interrupt-parent = <&intc>;
50 };
51};
52
53/include/ "twl4030.dtsi"
54
55&mmc1 {
56 vmmc-supply = <&vmmc1>;
57 vmmc_aux-supply = <&vsim>;
58 bus-width = <8>;
59};
60
61&mmc2 {
62 status = "disabled";
63};
64
65&mmc3 {
66 status = "disabled";
67};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 696e929d0304..1acc26148ffc 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -12,6 +12,7 @@
12 12
13/ { 13/ {
14 compatible = "ti,omap3430", "ti,omap3"; 14 compatible = "ti,omap3430", "ti,omap3";
15 interrupt-parent = <&intc>;
15 16
16 aliases { 17 aliases {
17 serial0 = &uart1; 18 serial0 = &uart1;
@@ -60,6 +61,12 @@
60 ranges; 61 ranges;
61 ti,hwmods = "l3_main"; 62 ti,hwmods = "l3_main";
62 63
64 counter32k: counter@48320000 {
65 compatible = "ti,omap-counter32k";
66 reg = <0x48320000 0x20>;
67 ti,hwmods = "counter_32k";
68 };
69
63 intc: interrupt-controller@48200000 { 70 intc: interrupt-controller@48200000 {
64 compatible = "ti,omap2-intc"; 71 compatible = "ti,omap2-intc";
65 interrupt-controller; 72 interrupt-controller;
@@ -240,7 +247,6 @@
240 <59>, /* TX interrupt */ 247 <59>, /* TX interrupt */
241 <60>; /* RX interrupt */ 248 <60>; /* RX interrupt */
242 interrupt-names = "common", "tx", "rx"; 249 interrupt-names = "common", "tx", "rx";
243 interrupt-parent = <&intc>;
244 ti,buffer-size = <128>; 250 ti,buffer-size = <128>;
245 ti,hwmods = "mcbsp1"; 251 ti,hwmods = "mcbsp1";
246 }; 252 };
@@ -255,7 +261,6 @@
255 <63>, /* RX interrupt */ 261 <63>, /* RX interrupt */
256 <4>; /* Sidetone */ 262 <4>; /* Sidetone */
257 interrupt-names = "common", "tx", "rx", "sidetone"; 263 interrupt-names = "common", "tx", "rx", "sidetone";
258 interrupt-parent = <&intc>;
259 ti,buffer-size = <1280>; 264 ti,buffer-size = <1280>;
260 ti,hwmods = "mcbsp2", "mcbsp2_sidetone"; 265 ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
261 }; 266 };
@@ -270,7 +275,6 @@
270 <90>, /* RX interrupt */ 275 <90>, /* RX interrupt */
271 <5>; /* Sidetone */ 276 <5>; /* Sidetone */
272 interrupt-names = "common", "tx", "rx", "sidetone"; 277 interrupt-names = "common", "tx", "rx", "sidetone";
273 interrupt-parent = <&intc>;
274 ti,buffer-size = <128>; 278 ti,buffer-size = <128>;
275 ti,hwmods = "mcbsp3", "mcbsp3_sidetone"; 279 ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
276 }; 280 };
@@ -283,7 +287,6 @@
283 <54>, /* TX interrupt */ 287 <54>, /* TX interrupt */
284 <55>; /* RX interrupt */ 288 <55>; /* RX interrupt */
285 interrupt-names = "common", "tx", "rx"; 289 interrupt-names = "common", "tx", "rx";
286 interrupt-parent = <&intc>;
287 ti,buffer-size = <128>; 290 ti,buffer-size = <128>;
288 ti,hwmods = "mcbsp4"; 291 ti,hwmods = "mcbsp4";
289 }; 292 };
@@ -296,9 +299,103 @@
296 <81>, /* TX interrupt */ 299 <81>, /* TX interrupt */
297 <82>; /* RX interrupt */ 300 <82>; /* RX interrupt */
298 interrupt-names = "common", "tx", "rx"; 301 interrupt-names = "common", "tx", "rx";
299 interrupt-parent = <&intc>;
300 ti,buffer-size = <128>; 302 ti,buffer-size = <128>;
301 ti,hwmods = "mcbsp5"; 303 ti,hwmods = "mcbsp5";
302 }; 304 };
305
306 timer1: timer@48318000 {
307 compatible = "ti,omap2-timer";
308 reg = <0x48318000 0x400>;
309 interrupts = <37>;
310 ti,hwmods = "timer1";
311 ti,timer-alwon;
312 };
313
314 timer2: timer@49032000 {
315 compatible = "ti,omap2-timer";
316 reg = <0x49032000 0x400>;
317 interrupts = <38>;
318 ti,hwmods = "timer2";
319 };
320
321 timer3: timer@49034000 {
322 compatible = "ti,omap2-timer";
323 reg = <0x49034000 0x400>;
324 interrupts = <39>;
325 ti,hwmods = "timer3";
326 };
327
328 timer4: timer@49036000 {
329 compatible = "ti,omap2-timer";
330 reg = <0x49036000 0x400>;
331 interrupts = <40>;
332 ti,hwmods = "timer4";
333 };
334
335 timer5: timer@49038000 {
336 compatible = "ti,omap2-timer";
337 reg = <0x49038000 0x400>;
338 interrupts = <41>;
339 ti,hwmods = "timer5";
340 ti,timer-dsp;
341 };
342
343 timer6: timer@4903a000 {
344 compatible = "ti,omap2-timer";
345 reg = <0x4903a000 0x400>;
346 interrupts = <42>;
347 ti,hwmods = "timer6";
348 ti,timer-dsp;
349 };
350
351 timer7: timer@4903c000 {
352 compatible = "ti,omap2-timer";
353 reg = <0x4903c000 0x400>;
354 interrupts = <43>;
355 ti,hwmods = "timer7";
356 ti,timer-dsp;
357 };
358
359 timer8: timer@4903e000 {
360 compatible = "ti,omap2-timer";
361 reg = <0x4903e000 0x400>;
362 interrupts = <44>;
363 ti,hwmods = "timer8";
364 ti,timer-pwm;
365 ti,timer-dsp;
366 };
367
368 timer9: timer@49040000 {
369 compatible = "ti,omap2-timer";
370 reg = <0x49040000 0x400>;
371 interrupts = <45>;
372 ti,hwmods = "timer9";
373 ti,timer-pwm;
374 };
375
376 timer10: timer@48086000 {
377 compatible = "ti,omap2-timer";
378 reg = <0x48086000 0x400>;
379 interrupts = <46>;
380 ti,hwmods = "timer10";
381 ti,timer-pwm;
382 };
383
384 timer11: timer@48088000 {
385 compatible = "ti,omap2-timer";
386 reg = <0x48088000 0x400>;
387 interrupts = <47>;
388 ti,hwmods = "timer11";
389 ti,timer-pwm;
390 };
391
392 timer12: timer@48304000 {
393 compatible = "ti,omap2-timer";
394 reg = <0x48304000 0x400>;
395 interrupts = <95>;
396 ti,hwmods = "timer12";
397 ti,timer-alwon;
398 ti,timer-secure;
399 };
303 }; 400 };
304}; 401};
diff --git a/arch/arm/boot/dts/omap4-panda-a4.dts b/arch/arm/boot/dts/omap4-panda-a4.dts
new file mode 100644
index 000000000000..75466d2abfb5
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-panda-a4.dts
@@ -0,0 +1,17 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/include/ "omap4-panda.dts"
9
10/* Pandaboard Rev A4+ have external pullups on SCL & SDA */
11&dss_hdmi_pins {
12 pinctrl-single,pins = <
13 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
14 0x5c 0x100 /* hdmi_scl.hdmi_scl INPUT | MODE 0 */
15 0x5e 0x100 /* hdmi_sda.hdmi_sda INPUT | MODE 0 */
16 >;
17};
diff --git a/arch/arm/boot/dts/omap4-pandaES.dts b/arch/arm/boot/dts/omap4-panda-es.dts
index d4ba43a48d9b..73bc1a67e444 100644
--- a/arch/arm/boot/dts/omap4-pandaES.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -22,3 +22,12 @@
22 "AFML", "Line In", 22 "AFML", "Line In",
23 "AFMR", "Line In"; 23 "AFMR", "Line In";
24}; 24};
25
26/* PandaboardES has external pullups on SCL & SDA */
27&dss_hdmi_pins {
28 pinctrl-single,pins = <
29 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
30 0x5c 0x100 /* hdmi_scl.hdmi_scl INPUT | MODE 0 */
31 0x5e 0x100 /* hdmi_sda.hdmi_sda INPUT | MODE 0 */
32 >;
33};
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index e8f927cbb376..4122efe31cfd 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -65,6 +65,8 @@
65 &twl6040_pins 65 &twl6040_pins
66 &mcpdm_pins 66 &mcpdm_pins
67 &mcbsp1_pins 67 &mcbsp1_pins
68 &dss_hdmi_pins
69 &tpd12s015_pins
68 >; 70 >;
69 71
70 twl6040_pins: pinmux_twl6040_pins { 72 twl6040_pins: pinmux_twl6040_pins {
@@ -92,6 +94,22 @@
92 0xc4 0x100 /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */ 94 0xc4 0x100 /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */
93 >; 95 >;
94 }; 96 };
97
98 dss_hdmi_pins: pinmux_dss_hdmi_pins {
99 pinctrl-single,pins = <
100 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
101 0x5c 0x118 /* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */
102 0x5e 0x118 /* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */
103 >;
104 };
105
106 tpd12s015_pins: pinmux_tpd12s015_pins {
107 pinctrl-single,pins = <
108 0x22 0x3 /* gpmc_a17.gpio_41 OUTPUT | MODE3 */
109 0x48 0x3 /* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */
110 0x58 0x10b /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */
111 >;
112 };
95}; 113};
96 114
97&i2c1 { 115&i2c1 {
@@ -184,3 +202,7 @@
184&dmic { 202&dmic {
185 status = "disabled"; 203 status = "disabled";
186}; 204};
205
206&twl_usb_comparator {
207 usb-supply = <&vusb>;
208};
diff --git a/arch/arm/boot/dts/omap4-sdp-es23plus.dts b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
new file mode 100644
index 000000000000..b4a40ffbce31
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
@@ -0,0 +1,17 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/include/ "omap4-sdp.dts"
9
10/* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */
11&dss_hdmi_pins {
12 pinctrl-single,pins = <
13 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
14 0x5c 0x100 /* hdmi_scl.hdmi_scl INPUT | MODE 0 */
15 0x5e 0x100 /* hdmi_sda.hdmi_sda INPUT | MODE 0 */
16 >;
17};
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 5b7e04fbff50..43e5258a9372 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -124,6 +124,8 @@
124 &dmic_pins 124 &dmic_pins
125 &mcbsp1_pins 125 &mcbsp1_pins
126 &mcbsp2_pins 126 &mcbsp2_pins
127 &dss_hdmi_pins
128 &tpd12s015_pins
127 >; 129 >;
128 130
129 uart2_pins: pinmux_uart2_pins { 131 uart2_pins: pinmux_uart2_pins {
@@ -194,6 +196,22 @@
194 0xbc 0x100 /* abe_mcbsp2_fsx.abe_mcbsp2_fsx INPUT | MODE0 */ 196 0xbc 0x100 /* abe_mcbsp2_fsx.abe_mcbsp2_fsx INPUT | MODE0 */
195 >; 197 >;
196 }; 198 };
199
200 dss_hdmi_pins: pinmux_dss_hdmi_pins {
201 pinctrl-single,pins = <
202 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
203 0x5c 0x118 /* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */
204 0x5e 0x118 /* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */
205 >;
206 };
207
208 tpd12s015_pins: pinmux_tpd12s015_pins {
209 pinctrl-single,pins = <
210 0x22 0x3 /* gpmc_a17.gpio_41 OUTPUT | MODE3 */
211 0x48 0x3 /* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */
212 0x58 0x10b /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */
213 >;
214 };
197}; 215};
198 216
199&i2c1 { 217&i2c1 {
@@ -406,3 +424,7 @@
406&mcbsp3 { 424&mcbsp3 {
407 status = "disabled"; 425 status = "disabled";
408}; 426};
427
428&twl_usb_comparator {
429 usb-supply = <&vusb>;
430};
diff --git a/arch/arm/boot/dts/omap4-var_som.dts b/arch/arm/boot/dts/omap4-var-som.dts
index 6601e6af6092..6601e6af6092 100644
--- a/arch/arm/boot/dts/omap4-var_som.dts
+++ b/arch/arm/boot/dts/omap4-var-som.dts
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 3883f94fdbd0..739bb79e410e 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -95,6 +95,12 @@
95 ranges; 95 ranges;
96 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; 96 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
97 97
98 counter32k: counter@4a304000 {
99 compatible = "ti,omap-counter32k";
100 reg = <0x4a304000 0x20>;
101 ti,hwmods = "counter_32k";
102 };
103
98 omap4_pmx_core: pinmux@4a100040 { 104 omap4_pmx_core: pinmux@4a100040 {
99 compatible = "ti,omap4-padconf", "pinctrl-single"; 105 compatible = "ti,omap4-padconf", "pinctrl-single";
100 reg = <0x4a100040 0x0196>; 106 reg = <0x4a100040 0x0196>;
@@ -340,7 +346,6 @@
340 <0x49032000 0x7f>; /* L3 Interconnect */ 346 <0x49032000 0x7f>; /* L3 Interconnect */
341 reg-names = "mpu", "dma"; 347 reg-names = "mpu", "dma";
342 interrupts = <0 112 0x4>; 348 interrupts = <0 112 0x4>;
343 interrupt-parent = <&gic>;
344 ti,hwmods = "mcpdm"; 349 ti,hwmods = "mcpdm";
345 }; 350 };
346 351
@@ -350,7 +355,6 @@
350 <0x4902e000 0x7f>; /* L3 Interconnect */ 355 <0x4902e000 0x7f>; /* L3 Interconnect */
351 reg-names = "mpu", "dma"; 356 reg-names = "mpu", "dma";
352 interrupts = <0 114 0x4>; 357 interrupts = <0 114 0x4>;
353 interrupt-parent = <&gic>;
354 ti,hwmods = "dmic"; 358 ti,hwmods = "dmic";
355 }; 359 };
356 360
@@ -361,7 +365,6 @@
361 reg-names = "mpu", "dma"; 365 reg-names = "mpu", "dma";
362 interrupts = <0 17 0x4>; 366 interrupts = <0 17 0x4>;
363 interrupt-names = "common"; 367 interrupt-names = "common";
364 interrupt-parent = <&gic>;
365 ti,buffer-size = <128>; 368 ti,buffer-size = <128>;
366 ti,hwmods = "mcbsp1"; 369 ti,hwmods = "mcbsp1";
367 }; 370 };
@@ -373,7 +376,6 @@
373 reg-names = "mpu", "dma"; 376 reg-names = "mpu", "dma";
374 interrupts = <0 22 0x4>; 377 interrupts = <0 22 0x4>;
375 interrupt-names = "common"; 378 interrupt-names = "common";
376 interrupt-parent = <&gic>;
377 ti,buffer-size = <128>; 379 ti,buffer-size = <128>;
378 ti,hwmods = "mcbsp2"; 380 ti,hwmods = "mcbsp2";
379 }; 381 };
@@ -385,7 +387,6 @@
385 reg-names = "mpu", "dma"; 387 reg-names = "mpu", "dma";
386 interrupts = <0 23 0x4>; 388 interrupts = <0 23 0x4>;
387 interrupt-names = "common"; 389 interrupt-names = "common";
388 interrupt-parent = <&gic>;
389 ti,buffer-size = <128>; 390 ti,buffer-size = <128>;
390 ti,hwmods = "mcbsp3"; 391 ti,hwmods = "mcbsp3";
391 }; 392 };
@@ -396,7 +397,6 @@
396 reg-names = "mpu"; 397 reg-names = "mpu";
397 interrupts = <0 16 0x4>; 398 interrupts = <0 16 0x4>;
398 interrupt-names = "common"; 399 interrupt-names = "common";
399 interrupt-parent = <&gic>;
400 ti,buffer-size = <128>; 400 ti,buffer-size = <128>;
401 ti,hwmods = "mcbsp4"; 401 ti,hwmods = "mcbsp4";
402 }; 402 };
@@ -431,12 +431,103 @@
431 hw-caps-temp-alert; 431 hw-caps-temp-alert;
432 }; 432 };
433 433
434 ocp2scp { 434 ocp2scp@4a0ad000 {
435 compatible = "ti,omap-ocp2scp"; 435 compatible = "ti,omap-ocp2scp";
436 reg = <0x4a0ad000 0x1f>;
436 #address-cells = <1>; 437 #address-cells = <1>;
437 #size-cells = <1>; 438 #size-cells = <1>;
438 ranges; 439 ranges;
439 ti,hwmods = "ocp2scp_usb_phy"; 440 ti,hwmods = "ocp2scp_usb_phy";
440 }; 441 };
442
443 timer1: timer@4a318000 {
444 compatible = "ti,omap2-timer";
445 reg = <0x4a318000 0x80>;
446 interrupts = <0 37 0x4>;
447 ti,hwmods = "timer1";
448 ti,timer-alwon;
449 };
450
451 timer2: timer@48032000 {
452 compatible = "ti,omap2-timer";
453 reg = <0x48032000 0x80>;
454 interrupts = <0 38 0x4>;
455 ti,hwmods = "timer2";
456 };
457
458 timer3: timer@48034000 {
459 compatible = "ti,omap2-timer";
460 reg = <0x48034000 0x80>;
461 interrupts = <0 39 0x4>;
462 ti,hwmods = "timer3";
463 };
464
465 timer4: timer@48036000 {
466 compatible = "ti,omap2-timer";
467 reg = <0x48036000 0x80>;
468 interrupts = <0 40 0x4>;
469 ti,hwmods = "timer4";
470 };
471
472 timer5: timer@40138000 {
473 compatible = "ti,omap2-timer";
474 reg = <0x40138000 0x80>,
475 <0x49038000 0x80>;
476 interrupts = <0 41 0x4>;
477 ti,hwmods = "timer5";
478 ti,timer-dsp;
479 };
480
481 timer6: timer@4013a000 {
482 compatible = "ti,omap2-timer";
483 reg = <0x4013a000 0x80>,
484 <0x4903a000 0x80>;
485 interrupts = <0 42 0x4>;
486 ti,hwmods = "timer6";
487 ti,timer-dsp;
488 };
489
490 timer7: timer@4013c000 {
491 compatible = "ti,omap2-timer";
492 reg = <0x4013c000 0x80>,
493 <0x4903c000 0x80>;
494 interrupts = <0 43 0x4>;
495 ti,hwmods = "timer7";
496 ti,timer-dsp;
497 };
498
499 timer8: timer@4013e000 {
500 compatible = "ti,omap2-timer";
501 reg = <0x4013e000 0x80>,
502 <0x4903e000 0x80>;
503 interrupts = <0 44 0x4>;
504 ti,hwmods = "timer8";
505 ti,timer-pwm;
506 ti,timer-dsp;
507 };
508
509 timer9: timer@4803e000 {
510 compatible = "ti,omap2-timer";
511 reg = <0x4803e000 0x80>;
512 interrupts = <0 45 0x4>;
513 ti,hwmods = "timer9";
514 ti,timer-pwm;
515 };
516
517 timer10: timer@48086000 {
518 compatible = "ti,omap2-timer";
519 reg = <0x48086000 0x80>;
520 interrupts = <0 46 0x4>;
521 ti,hwmods = "timer10";
522 ti,timer-pwm;
523 };
524
525 timer11: timer@48088000 {
526 compatible = "ti,omap2-timer";
527 reg = <0x48088000 0x80>;
528 interrupts = <0 47 0x4>;
529 ti,hwmods = "timer11";
530 ti,timer-pwm;
531 };
441 }; 532 };
442}; 533};
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index c663eba73168..8722c15bbba2 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -8,6 +8,7 @@
8/dts-v1/; 8/dts-v1/;
9 9
10/include/ "omap5.dtsi" 10/include/ "omap5.dtsi"
11/include/ "samsung_k3pe0e000b.dtsi"
11 12
12/ { 13/ {
13 model = "TI OMAP5 EVM board"; 14 model = "TI OMAP5 EVM board";
@@ -15,7 +16,7 @@
15 16
16 memory { 17 memory {
17 device_type = "memory"; 18 device_type = "memory";
18 reg = <0x80000000 0x40000000>; /* 1 GB */ 19 reg = <0x80000000 0x80000000>; /* 2 GB */
19 }; 20 };
20 21
21 vmmcsd_fixed: fixedregulator-mmcsd { 22 vmmcsd_fixed: fixedregulator-mmcsd {
@@ -140,3 +141,13 @@
140&mcbsp3 { 141&mcbsp3 {
141 status = "disabled"; 142 status = "disabled";
142}; 143};
144
145&emif1 {
146 cs1-used;
147 device-handle = <&samsung_K3PE0E000B>;
148};
149
150&emif2 {
151 cs1-used;
152 device-handle = <&samsung_K3PE0E000B>;
153};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 42c78beb4fdc..790bb2a4b343 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -77,6 +77,12 @@
77 ranges; 77 ranges;
78 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; 78 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
79 79
80 counter32k: counter@4ae04000 {
81 compatible = "ti,omap-counter32k";
82 reg = <0x4ae04000 0x40>;
83 ti,hwmods = "counter_32k";
84 };
85
80 omap5_pmx_core: pinmux@4a002840 { 86 omap5_pmx_core: pinmux@4a002840 {
81 compatible = "ti,omap4-padconf", "pinctrl-single"; 87 compatible = "ti,omap4-padconf", "pinctrl-single";
82 reg = <0x4a002840 0x01b6>; 88 reg = <0x4a002840 0x01b6>;
@@ -104,6 +110,8 @@
104 110
105 gpio1: gpio@4ae10000 { 111 gpio1: gpio@4ae10000 {
106 compatible = "ti,omap4-gpio"; 112 compatible = "ti,omap4-gpio";
113 reg = <0x4ae10000 0x200>;
114 interrupts = <0 29 0x4>;
107 ti,hwmods = "gpio1"; 115 ti,hwmods = "gpio1";
108 gpio-controller; 116 gpio-controller;
109 #gpio-cells = <2>; 117 #gpio-cells = <2>;
@@ -113,6 +121,8 @@
113 121
114 gpio2: gpio@48055000 { 122 gpio2: gpio@48055000 {
115 compatible = "ti,omap4-gpio"; 123 compatible = "ti,omap4-gpio";
124 reg = <0x48055000 0x200>;
125 interrupts = <0 30 0x4>;
116 ti,hwmods = "gpio2"; 126 ti,hwmods = "gpio2";
117 gpio-controller; 127 gpio-controller;
118 #gpio-cells = <2>; 128 #gpio-cells = <2>;
@@ -122,6 +132,8 @@
122 132
123 gpio3: gpio@48057000 { 133 gpio3: gpio@48057000 {
124 compatible = "ti,omap4-gpio"; 134 compatible = "ti,omap4-gpio";
135 reg = <0x48057000 0x200>;
136 interrupts = <0 31 0x4>;
125 ti,hwmods = "gpio3"; 137 ti,hwmods = "gpio3";
126 gpio-controller; 138 gpio-controller;
127 #gpio-cells = <2>; 139 #gpio-cells = <2>;
@@ -131,6 +143,8 @@
131 143
132 gpio4: gpio@48059000 { 144 gpio4: gpio@48059000 {
133 compatible = "ti,omap4-gpio"; 145 compatible = "ti,omap4-gpio";
146 reg = <0x48059000 0x200>;
147 interrupts = <0 32 0x4>;
134 ti,hwmods = "gpio4"; 148 ti,hwmods = "gpio4";
135 gpio-controller; 149 gpio-controller;
136 #gpio-cells = <2>; 150 #gpio-cells = <2>;
@@ -140,6 +154,8 @@
140 154
141 gpio5: gpio@4805b000 { 155 gpio5: gpio@4805b000 {
142 compatible = "ti,omap4-gpio"; 156 compatible = "ti,omap4-gpio";
157 reg = <0x4805b000 0x200>;
158 interrupts = <0 33 0x4>;
143 ti,hwmods = "gpio5"; 159 ti,hwmods = "gpio5";
144 gpio-controller; 160 gpio-controller;
145 #gpio-cells = <2>; 161 #gpio-cells = <2>;
@@ -149,6 +165,8 @@
149 165
150 gpio6: gpio@4805d000 { 166 gpio6: gpio@4805d000 {
151 compatible = "ti,omap4-gpio"; 167 compatible = "ti,omap4-gpio";
168 reg = <0x4805d000 0x200>;
169 interrupts = <0 34 0x4>;
152 ti,hwmods = "gpio6"; 170 ti,hwmods = "gpio6";
153 gpio-controller; 171 gpio-controller;
154 #gpio-cells = <2>; 172 #gpio-cells = <2>;
@@ -158,6 +176,8 @@
158 176
159 gpio7: gpio@48051000 { 177 gpio7: gpio@48051000 {
160 compatible = "ti,omap4-gpio"; 178 compatible = "ti,omap4-gpio";
179 reg = <0x48051000 0x200>;
180 interrupts = <0 35 0x4>;
161 ti,hwmods = "gpio7"; 181 ti,hwmods = "gpio7";
162 gpio-controller; 182 gpio-controller;
163 #gpio-cells = <2>; 183 #gpio-cells = <2>;
@@ -167,6 +187,8 @@
167 187
168 gpio8: gpio@48053000 { 188 gpio8: gpio@48053000 {
169 compatible = "ti,omap4-gpio"; 189 compatible = "ti,omap4-gpio";
190 reg = <0x48053000 0x200>;
191 interrupts = <0 121 0x4>;
170 ti,hwmods = "gpio8"; 192 ti,hwmods = "gpio8";
171 gpio-controller; 193 gpio-controller;
172 #gpio-cells = <2>; 194 #gpio-cells = <2>;
@@ -176,6 +198,8 @@
176 198
177 i2c1: i2c@48070000 { 199 i2c1: i2c@48070000 {
178 compatible = "ti,omap4-i2c"; 200 compatible = "ti,omap4-i2c";
201 reg = <0x48070000 0x100>;
202 interrupts = <0 56 0x4>;
179 #address-cells = <1>; 203 #address-cells = <1>;
180 #size-cells = <0>; 204 #size-cells = <0>;
181 ti,hwmods = "i2c1"; 205 ti,hwmods = "i2c1";
@@ -183,6 +207,8 @@
183 207
184 i2c2: i2c@48072000 { 208 i2c2: i2c@48072000 {
185 compatible = "ti,omap4-i2c"; 209 compatible = "ti,omap4-i2c";
210 reg = <0x48072000 0x100>;
211 interrupts = <0 57 0x4>;
186 #address-cells = <1>; 212 #address-cells = <1>;
187 #size-cells = <0>; 213 #size-cells = <0>;
188 ti,hwmods = "i2c2"; 214 ti,hwmods = "i2c2";
@@ -190,20 +216,26 @@
190 216
191 i2c3: i2c@48060000 { 217 i2c3: i2c@48060000 {
192 compatible = "ti,omap4-i2c"; 218 compatible = "ti,omap4-i2c";
219 reg = <0x48060000 0x100>;
220 interrupts = <0 61 0x4>;
193 #address-cells = <1>; 221 #address-cells = <1>;
194 #size-cells = <0>; 222 #size-cells = <0>;
195 ti,hwmods = "i2c3"; 223 ti,hwmods = "i2c3";
196 }; 224 };
197 225
198 i2c4: i2c@4807A000 { 226 i2c4: i2c@4807a000 {
199 compatible = "ti,omap4-i2c"; 227 compatible = "ti,omap4-i2c";
228 reg = <0x4807a000 0x100>;
229 interrupts = <0 62 0x4>;
200 #address-cells = <1>; 230 #address-cells = <1>;
201 #size-cells = <0>; 231 #size-cells = <0>;
202 ti,hwmods = "i2c4"; 232 ti,hwmods = "i2c4";
203 }; 233 };
204 234
205 i2c5: i2c@4807C000 { 235 i2c5: i2c@4807c000 {
206 compatible = "ti,omap4-i2c"; 236 compatible = "ti,omap4-i2c";
237 reg = <0x4807c000 0x100>;
238 interrupts = <0 60 0x4>;
207 #address-cells = <1>; 239 #address-cells = <1>;
208 #size-cells = <0>; 240 #size-cells = <0>;
209 ti,hwmods = "i2c5"; 241 ti,hwmods = "i2c5";
@@ -211,42 +243,56 @@
211 243
212 uart1: serial@4806a000 { 244 uart1: serial@4806a000 {
213 compatible = "ti,omap4-uart"; 245 compatible = "ti,omap4-uart";
246 reg = <0x4806a000 0x100>;
247 interrupts = <0 72 0x4>;
214 ti,hwmods = "uart1"; 248 ti,hwmods = "uart1";
215 clock-frequency = <48000000>; 249 clock-frequency = <48000000>;
216 }; 250 };
217 251
218 uart2: serial@4806c000 { 252 uart2: serial@4806c000 {
219 compatible = "ti,omap4-uart"; 253 compatible = "ti,omap4-uart";
254 reg = <0x4806c000 0x100>;
255 interrupts = <0 73 0x4>;
220 ti,hwmods = "uart2"; 256 ti,hwmods = "uart2";
221 clock-frequency = <48000000>; 257 clock-frequency = <48000000>;
222 }; 258 };
223 259
224 uart3: serial@48020000 { 260 uart3: serial@48020000 {
225 compatible = "ti,omap4-uart"; 261 compatible = "ti,omap4-uart";
262 reg = <0x48020000 0x100>;
263 interrupts = <0 74 0x4>;
226 ti,hwmods = "uart3"; 264 ti,hwmods = "uart3";
227 clock-frequency = <48000000>; 265 clock-frequency = <48000000>;
228 }; 266 };
229 267
230 uart4: serial@4806e000 { 268 uart4: serial@4806e000 {
231 compatible = "ti,omap4-uart"; 269 compatible = "ti,omap4-uart";
270 reg = <0x4806e000 0x100>;
271 interrupts = <0 70 0x4>;
232 ti,hwmods = "uart4"; 272 ti,hwmods = "uart4";
233 clock-frequency = <48000000>; 273 clock-frequency = <48000000>;
234 }; 274 };
235 275
236 uart5: serial@48066000 { 276 uart5: serial@48066000 {
237 compatible = "ti,omap5-uart"; 277 compatible = "ti,omap4-uart";
278 reg = <0x48066000 0x100>;
279 interrupts = <0 105 0x4>;
238 ti,hwmods = "uart5"; 280 ti,hwmods = "uart5";
239 clock-frequency = <48000000>; 281 clock-frequency = <48000000>;
240 }; 282 };
241 283
242 uart6: serial@48068000 { 284 uart6: serial@48068000 {
243 compatible = "ti,omap6-uart"; 285 compatible = "ti,omap4-uart";
286 reg = <0x48068000 0x100>;
287 interrupts = <0 106 0x4>;
244 ti,hwmods = "uart6"; 288 ti,hwmods = "uart6";
245 clock-frequency = <48000000>; 289 clock-frequency = <48000000>;
246 }; 290 };
247 291
248 mmc1: mmc@4809c000 { 292 mmc1: mmc@4809c000 {
249 compatible = "ti,omap4-hsmmc"; 293 compatible = "ti,omap4-hsmmc";
294 reg = <0x4809c000 0x400>;
295 interrupts = <0 83 0x4>;
250 ti,hwmods = "mmc1"; 296 ti,hwmods = "mmc1";
251 ti,dual-volt; 297 ti,dual-volt;
252 ti,needs-special-reset; 298 ti,needs-special-reset;
@@ -254,24 +300,32 @@
254 300
255 mmc2: mmc@480b4000 { 301 mmc2: mmc@480b4000 {
256 compatible = "ti,omap4-hsmmc"; 302 compatible = "ti,omap4-hsmmc";
303 reg = <0x480b4000 0x400>;
304 interrupts = <0 86 0x4>;
257 ti,hwmods = "mmc2"; 305 ti,hwmods = "mmc2";
258 ti,needs-special-reset; 306 ti,needs-special-reset;
259 }; 307 };
260 308
261 mmc3: mmc@480ad000 { 309 mmc3: mmc@480ad000 {
262 compatible = "ti,omap4-hsmmc"; 310 compatible = "ti,omap4-hsmmc";
311 reg = <0x480ad000 0x400>;
312 interrupts = <0 94 0x4>;
263 ti,hwmods = "mmc3"; 313 ti,hwmods = "mmc3";
264 ti,needs-special-reset; 314 ti,needs-special-reset;
265 }; 315 };
266 316
267 mmc4: mmc@480d1000 { 317 mmc4: mmc@480d1000 {
268 compatible = "ti,omap4-hsmmc"; 318 compatible = "ti,omap4-hsmmc";
319 reg = <0x480d1000 0x400>;
320 interrupts = <0 96 0x4>;
269 ti,hwmods = "mmc4"; 321 ti,hwmods = "mmc4";
270 ti,needs-special-reset; 322 ti,needs-special-reset;
271 }; 323 };
272 324
273 mmc5: mmc@480d5000 { 325 mmc5: mmc@480d5000 {
274 compatible = "ti,omap4-hsmmc"; 326 compatible = "ti,omap4-hsmmc";
327 reg = <0x480d5000 0x400>;
328 interrupts = <0 59 0x4>;
275 ti,hwmods = "mmc5"; 329 ti,hwmods = "mmc5";
276 ti,needs-special-reset; 330 ti,needs-special-reset;
277 }; 331 };
@@ -287,7 +341,6 @@
287 <0x49032000 0x7f>; /* L3 Interconnect */ 341 <0x49032000 0x7f>; /* L3 Interconnect */
288 reg-names = "mpu", "dma"; 342 reg-names = "mpu", "dma";
289 interrupts = <0 112 0x4>; 343 interrupts = <0 112 0x4>;
290 interrupt-parent = <&gic>;
291 ti,hwmods = "mcpdm"; 344 ti,hwmods = "mcpdm";
292 }; 345 };
293 346
@@ -297,7 +350,6 @@
297 <0x4902e000 0x7f>; /* L3 Interconnect */ 350 <0x4902e000 0x7f>; /* L3 Interconnect */
298 reg-names = "mpu", "dma"; 351 reg-names = "mpu", "dma";
299 interrupts = <0 114 0x4>; 352 interrupts = <0 114 0x4>;
300 interrupt-parent = <&gic>;
301 ti,hwmods = "dmic"; 353 ti,hwmods = "dmic";
302 }; 354 };
303 355
@@ -308,7 +360,6 @@
308 reg-names = "mpu", "dma"; 360 reg-names = "mpu", "dma";
309 interrupts = <0 17 0x4>; 361 interrupts = <0 17 0x4>;
310 interrupt-names = "common"; 362 interrupt-names = "common";
311 interrupt-parent = <&gic>;
312 ti,buffer-size = <128>; 363 ti,buffer-size = <128>;
313 ti,hwmods = "mcbsp1"; 364 ti,hwmods = "mcbsp1";
314 }; 365 };
@@ -320,7 +371,6 @@
320 reg-names = "mpu", "dma"; 371 reg-names = "mpu", "dma";
321 interrupts = <0 22 0x4>; 372 interrupts = <0 22 0x4>;
322 interrupt-names = "common"; 373 interrupt-names = "common";
323 interrupt-parent = <&gic>;
324 ti,buffer-size = <128>; 374 ti,buffer-size = <128>;
325 ti,hwmods = "mcbsp2"; 375 ti,hwmods = "mcbsp2";
326 }; 376 };
@@ -332,9 +382,119 @@
332 reg-names = "mpu", "dma"; 382 reg-names = "mpu", "dma";
333 interrupts = <0 23 0x4>; 383 interrupts = <0 23 0x4>;
334 interrupt-names = "common"; 384 interrupt-names = "common";
335 interrupt-parent = <&gic>;
336 ti,buffer-size = <128>; 385 ti,buffer-size = <128>;
337 ti,hwmods = "mcbsp3"; 386 ti,hwmods = "mcbsp3";
338 }; 387 };
388
389 timer1: timer@4ae18000 {
390 compatible = "ti,omap2-timer";
391 reg = <0x4ae18000 0x80>;
392 interrupts = <0 37 0x4>;
393 ti,hwmods = "timer1";
394 ti,timer-alwon;
395 };
396
397 timer2: timer@48032000 {
398 compatible = "ti,omap2-timer";
399 reg = <0x48032000 0x80>;
400 interrupts = <0 38 0x4>;
401 ti,hwmods = "timer2";
402 };
403
404 timer3: timer@48034000 {
405 compatible = "ti,omap2-timer";
406 reg = <0x48034000 0x80>;
407 interrupts = <0 39 0x4>;
408 ti,hwmods = "timer3";
409 };
410
411 timer4: timer@48036000 {
412 compatible = "ti,omap2-timer";
413 reg = <0x48036000 0x80>;
414 interrupts = <0 40 0x4>;
415 ti,hwmods = "timer4";
416 };
417
418 timer5: timer@40138000 {
419 compatible = "ti,omap2-timer";
420 reg = <0x40138000 0x80>,
421 <0x49038000 0x80>;
422 interrupts = <0 41 0x4>;
423 ti,hwmods = "timer5";
424 ti,timer-dsp;
425 };
426
427 timer6: timer@4013a000 {
428 compatible = "ti,omap2-timer";
429 reg = <0x4013a000 0x80>,
430 <0x4903a000 0x80>;
431 interrupts = <0 42 0x4>;
432 ti,hwmods = "timer6";
433 ti,timer-dsp;
434 ti,timer-pwm;
435 };
436
437 timer7: timer@4013c000 {
438 compatible = "ti,omap2-timer";
439 reg = <0x4013c000 0x80>,
440 <0x4903c000 0x80>;
441 interrupts = <0 43 0x4>;
442 ti,hwmods = "timer7";
443 ti,timer-dsp;
444 };
445
446 timer8: timer@4013e000 {
447 compatible = "ti,omap2-timer";
448 reg = <0x4013e000 0x80>,
449 <0x4903e000 0x80>;
450 interrupts = <0 44 0x4>;
451 ti,hwmods = "timer8";
452 ti,timer-dsp;
453 ti,timer-pwm;
454 };
455
456 timer9: timer@4803e000 {
457 compatible = "ti,omap2-timer";
458 reg = <0x4803e000 0x80>;
459 interrupts = <0 45 0x4>;
460 ti,hwmods = "timer9";
461 };
462
463 timer10: timer@48086000 {
464 compatible = "ti,omap2-timer";
465 reg = <0x48086000 0x80>;
466 interrupts = <0 46 0x4>;
467 ti,hwmods = "timer10";
468 };
469
470 timer11: timer@48088000 {
471 compatible = "ti,omap2-timer";
472 reg = <0x48088000 0x80>;
473 interrupts = <0 47 0x4>;
474 ti,hwmods = "timer11";
475 ti,timer-pwm;
476 };
477
478 emif1: emif@0x4c000000 {
479 compatible = "ti,emif-4d5";
480 ti,hwmods = "emif1";
481 phy-type = <2>; /* DDR PHY type: Intelli PHY */
482 reg = <0x4c000000 0x400>;
483 interrupts = <0 110 0x4>;
484 hw-caps-read-idle-ctrl;
485 hw-caps-ll-interface;
486 hw-caps-temp-alert;
487 };
488
489 emif2: emif@0x4d000000 {
490 compatible = "ti,emif-4d5";
491 ti,hwmods = "emif2";
492 phy-type = <2>; /* DDR PHY type: Intelli PHY */
493 reg = <0x4d000000 0x400>;
494 interrupts = <0 111 0x4>;
495 hw-caps-read-idle-ctrl;
496 hw-caps-ll-interface;
497 hw-caps-temp-alert;
498 };
339 }; 499 };
340}; 500};
diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
new file mode 100644
index 000000000000..5a3a58b7e18f
--- /dev/null
+++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
@@ -0,0 +1,55 @@
1/*
2 * Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9/dts-v1/;
10/include/ "orion5x.dtsi"
11
12/ {
13 model = "LaCie Ethernet Disk mini V2";
14 compatible = "lacie,ethernet-disk-mini-v2", "marvell-orion5x-88f5182", "marvell,orion5x";
15
16 memory {
17 reg = <0x00000000 0x4000000>; /* 64 MB */
18 };
19
20 chosen {
21 bootargs = "console=ttyS0,115200n8 earlyprintk";
22 };
23
24 ocp@f1000000 {
25 serial@12000 {
26 clock-frequency = <166666667>;
27 status = "okay";
28 };
29
30 sata@80000 {
31 status = "okay";
32 nr-ports = <2>;
33 };
34 };
35
36 gpio_keys {
37 compatible = "gpio-keys";
38 #address-cells = <1>;
39 #size-cells = <0>;
40 button@1 {
41 label = "Power-on Switch";
42 linux,code = <116>; /* KEY_POWER */
43 gpios = <&gpio0 18 0>;
44 };
45 };
46
47 gpio_leds {
48 compatible = "gpio-leds";
49
50 led@1 {
51 label = "power:blue";
52 gpios = <&gpio0 16 1>;
53 };
54 };
55};
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
new file mode 100644
index 000000000000..8aad00f81ed9
--- /dev/null
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -0,0 +1,98 @@
1/*
2 * Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
12 model = "Marvell Orion5x SoC";
13 compatible = "marvell,orion5x";
14 interrupt-parent = <&intc>;
15
16 intc: interrupt-controller {
17 compatible = "marvell,orion-intc", "marvell,intc";
18 interrupt-controller;
19 #interrupt-cells = <1>;
20 reg = <0xf1020204 0x04>;
21 };
22
23 ocp@f1000000 {
24 compatible = "simple-bus";
25 ranges = <0x00000000 0xf1000000 0x4000000
26 0xf2200000 0xf2200000 0x0000800>;
27 #address-cells = <1>;
28 #size-cells = <1>;
29
30 gpio0: gpio@10100 {
31 compatible = "marvell,orion-gpio";
32 #gpio-cells = <2>;
33 gpio-controller;
34 reg = <0x10100 0x40>;
35 ngpio = <32>;
36 interrupts = <6>, <7>, <8>, <9>;
37 };
38
39 serial@12000 {
40 compatible = "ns16550a";
41 reg = <0x12000 0x100>;
42 reg-shift = <2>;
43 interrupts = <3>;
44 /* set clock-frequency in board dts */
45 status = "disabled";
46 };
47
48 serial@12100 {
49 compatible = "ns16550a";
50 reg = <0x12100 0x100>;
51 reg-shift = <2>;
52 interrupts = <4>;
53 /* set clock-frequency in board dts */
54 status = "disabled";
55 };
56
57 spi@10600 {
58 compatible = "marvell,orion-spi";
59 #address-cells = <1>;
60 #size-cells = <0>;
61 cell-index = <0>;
62 reg = <0x10600 0x28>;
63 status = "disabled";
64 };
65
66 wdt@20300 {
67 compatible = "marvell,orion-wdt";
68 reg = <0x20300 0x28>;
69 status = "okay";
70 };
71
72 sata@80000 {
73 compatible = "marvell,orion-sata";
74 reg = <0x80000 0x5000>;
75 interrupts = <29>;
76 status = "disabled";
77 };
78
79 i2c@11000 {
80 compatible = "marvell,mv64xxx-i2c";
81 reg = <0x11000 0x20>;
82 #address-cells = <1>;
83 #size-cells = <0>;
84 interrupts = <5>;
85 clock-frequency = <100000>;
86 status = "disabled";
87 };
88
89 crypto@90000 {
90 compatible = "marvell,orion-crypto";
91 reg = <0x90000 0x10000>,
92 <0xf2200000 0x800>;
93 reg-names = "regs", "sram";
94 interrupts = <22>;
95 status = "okay";
96 };
97 };
98};
diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/pm9g45.dts
new file mode 100644
index 000000000000..387fedb58988
--- /dev/null
+++ b/arch/arm/boot/dts/pm9g45.dts
@@ -0,0 +1,165 @@
1/*
2 * pm9g45.dts - Device Tree file for Ronetix pm9g45 board
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8/dts-v1/;
9/include/ "at91sam9g45.dtsi"
10
11/ {
12 model = "Ronetix pm9g45";
13 compatible = "ronetix,pm9g45", "atmel,at91sam9g45", "atmel,at91sam9";
14
15 chosen {
16 bootargs = "console=ttyS0,115200";
17 };
18
19 memory {
20 reg = <0x70000000 0x8000000>;
21 };
22
23 clocks {
24 #address-cells = <1>;
25 #size-cells = <1>;
26 ranges;
27
28 main_clock: clock@0 {
29 compatible = "atmel,osc", "fixed-clock";
30 clock-frequency = <12000000>;
31 };
32 };
33
34 ahb {
35 apb {
36 dbgu: serial@ffffee00 {
37 status = "okay";
38 };
39
40 pinctrl@fffff200 {
41
42 board {
43 pinctrl_board_nand: nand0-board {
44 atmel,pins =
45 <3 3 0x0 0x1 /* PD3 gpio RDY pin pull_up*/
46 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
47 };
48 };
49
50 mmc {
51 pinctrl_board_mmc: mmc0-board {
52 atmel,pins =
53 <3 6 0x0 0x5>; /* PD6 gpio CD pin pull_up and deglitch */
54 };
55 };
56 };
57
58 mmc0: mmc@fff80000 {
59 pinctrl-0 = <
60 &pinctrl_board_mmc
61 &pinctrl_mmc0_slot0_clk_cmd_dat0
62 &pinctrl_mmc0_slot0_dat1_3>;
63 status = "okay";
64 slot@0 {
65 reg = <0>;
66 bus-width = <4>;
67 cd-gpios = <&pioD 6 0>;
68 };
69 };
70
71 macb0: ethernet@fffbc000 {
72 phy-mode = "rmii";
73 status = "okay";
74 };
75
76 };
77
78 nand0: nand@40000000 {
79 nand-bus-width = <8>;
80 nand-ecc-mode = "soft";
81 nand-on-flash-bbt;
82 pinctrl-0 = <&pinctrl_board_nand>;
83
84 gpios = <&pioD 3 0
85 &pioC 14 0
86 0
87 >;
88
89 status = "okay";
90
91 at91bootstrap@0 {
92 label = "at91bootstrap";
93 reg = <0x0 0x20000>;
94 };
95
96 barebox@20000 {
97 label = "barebox";
98 reg = <0x20000 0x40000>;
99 };
100
101 bareboxenv@60000 {
102 label = "bareboxenv";
103 reg = <0x60000 0x1A0000>;
104 };
105
106 kernel@200000 {
107 label = "bareboxenv2";
108 reg = <0x200000 0x300000>;
109 };
110
111 kernel@500000 {
112 label = "root";
113 reg = <0x500000 0x400000>;
114 };
115
116 data@900000 {
117 label = "data";
118 reg = <0x900000 0x8340000>;
119 };
120 };
121
122 usb0: ohci@00700000 {
123 status = "okay";
124 num-ports = <2>;
125 };
126
127 usb1: ehci@00800000 {
128 status = "okay";
129 };
130 };
131
132 leds {
133 compatible = "gpio-leds";
134
135 led0 {
136 label = "led0";
137 gpios = <&pioD 0 1>;
138 linux,default-trigger = "nand-disk";
139 };
140
141 led1 {
142 label = "led1";
143 gpios = <&pioD 31 0>;
144 linux,default-trigger = "heartbeat";
145 };
146 };
147
148 gpio_keys {
149 compatible = "gpio-keys";
150 #address-cells = <1>;
151 #size-cells = <0>;
152
153 right {
154 label = "SW4";
155 gpios = <&pioE 7 1>;
156 linux,code = <106>;
157 };
158
159 up {
160 label = "SW3";
161 gpios = <&pioE 8 1>;
162 linux,code = <103>;
163 };
164 };
165};
diff --git a/arch/arm/boot/dts/samsung_k3pe0e000b.dtsi b/arch/arm/boot/dts/samsung_k3pe0e000b.dtsi
new file mode 100644
index 000000000000..9657a5cbc3ad
--- /dev/null
+++ b/arch/arm/boot/dts/samsung_k3pe0e000b.dtsi
@@ -0,0 +1,67 @@
1/*
2 * Timings and Geometry for Samsung K3PE0E000B memory part
3 */
4
5/ {
6 samsung_K3PE0E000B: lpddr2 {
7 compatible = "Samsung,K3PE0E000B","jedec,lpddr2-s4";
8 density = <4096>;
9 io-width = <32>;
10
11 tRPab-min-tck = <3>;
12 tRCD-min-tck = <3>;
13 tWR-min-tck = <3>;
14 tRASmin-min-tck = <3>;
15 tRRD-min-tck = <2>;
16 tWTR-min-tck = <2>;
17 tXP-min-tck = <2>;
18 tRTP-min-tck = <2>;
19 tCKE-min-tck = <3>;
20 tCKESR-min-tck = <3>;
21 tFAW-min-tck = <8>;
22
23 timings_samsung_K3PE0E000B_533MHz: lpddr2-timings@0 {
24 compatible = "jedec,lpddr2-timings";
25 min-freq = <10000000>;
26 max-freq = <533333333>;
27 tRPab = <21000>;
28 tRCD = <18000>;
29 tWR = <15000>;
30 tRAS-min = <42000>;
31 tRRD = <10000>;
32 tWTR = <7500>;
33 tXP = <7500>;
34 tRTP = <7500>;
35 tCKESR = <15000>;
36 tDQSCK-max = <5500>;
37 tFAW = <50000>;
38 tZQCS = <90000>;
39 tZQCL = <360000>;
40 tZQinit = <1000000>;
41 tRAS-max-ns = <70000>;
42 tDQSCK-max-derated = <6000>;
43 };
44
45 timings_samsung_K3PE0E000B_266MHz: lpddr2-timings@1 {
46 compatible = "jedec,lpddr2-timings";
47 min-freq = <10000000>;
48 max-freq = <266666666>;
49 tRPab = <21000>;
50 tRCD = <18000>;
51 tWR = <15000>;
52 tRAS-min = <42000>;
53 tRRD = <10000>;
54 tWTR = <7500>;
55 tXP = <7500>;
56 tRTP = <7500>;
57 tCKESR = <15000>;
58 tDQSCK-max = <5500>;
59 tFAW = <50000>;
60 tZQCS = <90000>;
61 tZQCL = <360000>;
62 tZQinit = <1000000>;
63 tRAS-max-ns = <70000>;
64 tDQSCK-max-derated = <6000>;
65 };
66 };
67};
diff --git a/arch/arm/boot/dts/sh7377.dtsi b/arch/arm/boot/dts/sh7372-mackerel.dts
index 767ee0796daa..286f0caef013 100644
--- a/arch/arm/boot/dts/sh7377.dtsi
+++ b/arch/arm/boot/dts/sh7372-mackerel.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Device Tree Source for the sh7377 SoC 2 * Device Tree Source for the mackerel board
3 * 3 *
4 * Copyright (C) 2012 Renesas Solutions Corp. 4 * Copyright (C) 2012 Renesas Solutions Corp.
5 * 5 *
@@ -8,14 +8,15 @@
8 * kind, whether express or implied. 8 * kind, whether express or implied.
9 */ 9 */
10 10
11/dts-v1/;
11/include/ "skeleton.dtsi" 12/include/ "skeleton.dtsi"
12 13
13/ { 14/ {
14 compatible = "renesas,sh7377"; 15 model = "Mackerel (AP4 EVM 2nd)";
16 compatible = "renesas,mackerel";
15 17
16 cpus { 18 memory {
17 cpu@0 { 19 device_type = "memory";
18 compatible = "arm,cortex-a8"; 20 reg = <0x40000000 0x10000000>;
19 };
20 }; 21 };
21}; 22};
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index 702c0baa6004..27f31a5fa494 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -14,7 +14,7 @@
14 14
15/ { 15/ {
16 model = "Calao Systems Snowball platform with device tree"; 16 model = "Calao Systems Snowball platform with device tree";
17 compatible = "calaosystems,snowball-a9500"; 17 compatible = "calaosystems,snowball-a9500", "st-ericsson,u9500";
18 18
19 memory { 19 memory {
20 reg = <0x00000000 0x20000000>; 20 reg = <0x00000000 0x20000000>;
@@ -99,6 +99,33 @@
99 status = "okay"; 99 status = "okay";
100 }; 100 };
101 101
102 prcmu@80157000 {
103 thermal@801573c0 {
104 num-trips = <4>;
105
106 trip0-temp = <70000>;
107 trip0-type = "active";
108 trip0-cdev-num = <1>;
109 trip0-cdev-name0 = "thermal-cpufreq-0";
110
111 trip1-temp = <75000>;
112 trip1-type = "active";
113 trip1-cdev-num = <1>;
114 trip1-cdev-name0 = "thermal-cpufreq-0";
115
116 trip2-temp = <80000>;
117 trip2-type = "active";
118 trip2-cdev-num = <1>;
119 trip2-cdev-name0 = "thermal-cpufreq-0";
120
121 trip3-temp = <85000>;
122 trip3-type = "critical";
123 trip3-cdev-num = <0>;
124
125 status = "okay";
126 };
127 };
128
102 external-bus@50000000 { 129 external-bus@50000000 {
103 status = "okay"; 130 status = "okay";
104 131
@@ -120,10 +147,10 @@
120 }; 147 };
121 148
122 // External Micro SD slot 149 // External Micro SD slot
123 sdi@80126000 { 150 sdi0_per1@80126000 {
124 arm,primecell-periphid = <0x10480180>; 151 arm,primecell-periphid = <0x10480180>;
125 max-frequency = <50000000>; 152 max-frequency = <50000000>;
126 bus-width = <8>; 153 bus-width = <4>;
127 mmc-cap-mmc-highspeed; 154 mmc-cap-mmc-highspeed;
128 vmmc-supply = <&ab8500_ldo_aux3_reg>; 155 vmmc-supply = <&ab8500_ldo_aux3_reg>;
129 156
@@ -134,7 +161,7 @@
134 }; 161 };
135 162
136 // On-board eMMC 163 // On-board eMMC
137 sdi@80114000 { 164 sdi4_per2@80114000 {
138 arm,primecell-periphid = <0x10480180>; 165 arm,primecell-periphid = <0x10480180>;
139 max-frequency = <50000000>; 166 max-frequency = <50000000>;
140 bus-width = <8>; 167 bus-width = <8>;
@@ -183,5 +210,141 @@
183 reg = <0x33>; 210 reg = <0x33>;
184 }; 211 };
185 }; 212 };
213
214 cpufreq-cooling {
215 status = "okay";
216 };
217
218 prcmu@80157000 {
219 db8500-prcmu-regulators {
220 db8500_vape_reg: db8500_vape {
221 regulator-name = "db8500-vape";
222 };
223
224 db8500_varm_reg: db8500_varm {
225 regulator-name = "db8500-varm";
226 };
227
228 db8500_vmodem_reg: db8500_vmodem {
229 regulator-name = "db8500-vmodem";
230 };
231
232 db8500_vpll_reg: db8500_vpll {
233 regulator-name = "db8500-vpll";
234 };
235
236 db8500_vsmps1_reg: db8500_vsmps1 {
237 regulator-name = "db8500-vsmps1";
238 };
239
240 db8500_vsmps2_reg: db8500_vsmps2 {
241 regulator-name = "db8500-vsmps2";
242 };
243
244 db8500_vsmps3_reg: db8500_vsmps3 {
245 regulator-name = "db8500-vsmps3";
246 };
247
248 db8500_vrf1_reg: db8500_vrf1 {
249 regulator-name = "db8500-vrf1";
250 };
251
252 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
253 regulator-name = "db8500-sva-mmdsp";
254 };
255
256 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
257 regulator-name = "db8500-sva-mmdsp-ret";
258 };
259
260 db8500_sva_pipe_reg: db8500_sva_pipe {
261 regulator-name = "db8500_sva_pipe";
262 };
263
264 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
265 regulator-name = "db8500_sia_mmdsp";
266 };
267
268 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
269 regulator-name = "db8500-sia-mmdsp-ret";
270 };
271
272 db8500_sia_pipe_reg: db8500_sia_pipe {
273 regulator-name = "db8500-sia-pipe";
274 };
275
276 db8500_sga_reg: db8500_sga {
277 regulator-name = "db8500-sga";
278 };
279
280 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
281 regulator-name = "db8500-b2r2-mcde";
282 };
283
284 db8500_esram12_reg: db8500_esram12 {
285 regulator-name = "db8500-esram12";
286 };
287
288 db8500_esram12_ret_reg: db8500_esram12_ret {
289 regulator-name = "db8500-esram12-ret";
290 };
291
292 db8500_esram34_reg: db8500_esram34 {
293 regulator-name = "db8500-esram34";
294 };
295
296 db8500_esram34_ret_reg: db8500_esram34_ret {
297 regulator-name = "db8500-esram34-ret";
298 };
299 };
300
301 ab8500@5 {
302 ab8500-regulators {
303 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
304 regulator-name = "V-DISPLAY";
305 };
306
307 ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
308 regulator-name = "V-eMMC1";
309 };
310
311 ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
312 regulator-name = "V-MMC-SD";
313 };
314
315 ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
316 regulator-name = "V-INTCORE";
317 };
318
319 ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
320 regulator-name = "V-TVOUT";
321 };
322
323 ab8500_ldo_usb_reg: ab8500_ldo_usb {
324 regulator-name = "dummy";
325 };
326
327 ab8500_ldo_audio_reg: ab8500_ldo_audio {
328 regulator-name = "V-AUD";
329 };
330
331 ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
332 regulator-name = "V-AMIC1";
333 };
334
335 ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
336 regulator-name = "V-AMIC2";
337 };
338
339 ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
340 regulator-name = "V-DMIC";
341 };
342
343 ab8500_ldo_ana_reg: ab8500_ldo_ana {
344 regulator-name = "V-CSI/DSI";
345 };
346 };
347 };
348 };
186 }; 349 };
187}; 350};
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 0772f5739f59..19aec421bb26 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -143,5 +143,15 @@
143 reg-shift = <2>; 143 reg-shift = <2>;
144 reg-io-width = <4>; 144 reg-io-width = <4>;
145 }; 145 };
146
147 rstmgr@ffd05000 {
148 compatible = "altr,rst-mgr";
149 reg = <0xffd05000 0x1000>;
150 };
151
152 sysmgr@ffd08000 {
153 compatible = "altr,sys-mgr";
154 reg = <0xffd08000 0x4000>;
155 };
146 }; 156 };
147}; 157};
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
index dd4358bc26e2..b56a801e42a2 100644
--- a/arch/arm/boot/dts/spear1310-evb.dts
+++ b/arch/arm/boot/dts/spear1310-evb.dts
@@ -30,10 +30,14 @@
30 pinctrl-0 = <&state_default>; 30 pinctrl-0 = <&state_default>;
31 31
32 state_default: pinmux { 32 state_default: pinmux {
33 i2c0-pmx { 33 i2c0 {
34 st,pins = "i2c0_grp"; 34 st,pins = "i2c0_grp";
35 st,function = "i2c0"; 35 st,function = "i2c0";
36 }; 36 };
37 i2s0 {
38 st,pins = "i2s0_grp";
39 st,function = "i2s0";
40 };
37 i2s1 { 41 i2s1 {
38 st,pins = "i2s1_grp"; 42 st,pins = "i2s1_grp";
39 st,function = "i2s1"; 43 st,function = "i2s1";
@@ -42,6 +46,10 @@
42 st,pins = "arm_gpio_grp"; 46 st,pins = "arm_gpio_grp";
43 st,function = "arm_gpio"; 47 st,function = "arm_gpio";
44 }; 48 };
49 clcd {
50 st,pins = "clcd_grp" , "clcd_high_res";
51 st,function = "clcd";
52 };
45 eth { 53 eth {
46 st,pins = "gmii_grp"; 54 st,pins = "gmii_grp";
47 st,function = "gmii"; 55 st,function = "gmii";
@@ -74,11 +82,6 @@
74 st,pins = "i2c_1_2_grp"; 82 st,pins = "i2c_1_2_grp";
75 st,function = "i2c_1_2"; 83 st,function = "i2c_1_2";
76 }; 84 };
77 pci {
78 st,pins = "pcie0_grp","pcie1_grp",
79 "pcie2_grp";
80 st,function = "pci";
81 };
82 smii { 85 smii {
83 st,pins = "smii_0_1_2_grp"; 86 st,pins = "smii_0_1_2_grp";
84 st,function = "smii_0_1_2"; 87 st,function = "smii_0_1_2";
@@ -88,6 +91,14 @@
88 "nand_16bit_grp"; 91 "nand_16bit_grp";
89 st,function = "nand"; 92 st,function = "nand";
90 }; 93 };
94 sata {
95 st,pins = "sata0_grp";
96 st,function = "sata";
97 };
98 pcie {
99 st,pins = "pcie1_grp", "pcie2_grp";
100 st,function = "pci_express";
101 };
91 }; 102 };
92 }; 103 };
93 104
@@ -109,9 +120,49 @@
109 120
110 fsmc: flash@b0000000 { 121 fsmc: flash@b0000000 {
111 status = "okay"; 122 status = "okay";
123
124 partition@0 {
125 label = "xloader";
126 reg = <0x0 0x80000>;
127 };
128 partition@80000 {
129 label = "u-boot";
130 reg = <0x80000 0x140000>;
131 };
132 partition@1C0000 {
133 label = "environment";
134 reg = <0x1C0000 0x40000>;
135 };
136 partition@200000 {
137 label = "dtb";
138 reg = <0x200000 0x40000>;
139 };
140 partition@240000 {
141 label = "linux";
142 reg = <0x240000 0xC00000>;
143 };
144 partition@E40000 {
145 label = "rootfs";
146 reg = <0xE40000 0x0>;
147 };
148 };
149
150 gpio_keys {
151 compatible = "gpio-keys";
152 #address-cells = <1>;
153 #size-cells = <0>;
154
155 button@1 {
156 label = "wakeup";
157 linux,code = <0x100>;
158 gpios = <&gpio0 7 0x4>;
159 debounce-interval = <20>;
160 gpio-key,wakeup = <1>;
161 };
112 }; 162 };
113 163
114 gmac0: eth@e2000000 { 164 gmac0: eth@e2000000 {
165 phy-mode = "gmii";
115 status = "okay"; 166 status = "okay";
116 }; 167 };
117 168
@@ -135,23 +186,27 @@
135 }; 186 };
136 partition@10000 { 187 partition@10000 {
137 label = "u-boot"; 188 label = "u-boot";
138 reg = <0x10000 0x40000>; 189 reg = <0x10000 0x50000>;
190 };
191 partition@60000 {
192 label = "environment";
193 reg = <0x60000 0x10000>;
139 }; 194 };
140 partition@50000 { 195 partition@70000 {
196 label = "dtb";
197 reg = <0x70000 0x10000>;
198 };
199 partition@80000 {
141 label = "linux"; 200 label = "linux";
142 reg = <0x50000 0x2c0000>; 201 reg = <0x80000 0x310000>;
143 }; 202 };
144 partition@310000 { 203 partition@390000 {
145 label = "rootfs"; 204 label = "rootfs";
146 reg = <0x310000 0x4f0000>; 205 reg = <0x390000 0x0>;
147 }; 206 };
148 }; 207 };
149 }; 208 };
150 209
151 spi0: spi@e0100000 {
152 status = "okay";
153 };
154
155 ehci@e4800000 { 210 ehci@e4800000 {
156 status = "okay"; 211 status = "okay";
157 }; 212 };
@@ -181,11 +236,11 @@
181 status = "okay"; 236 status = "okay";
182 }; 237 };
183 238
184 i2c0: i2c@e0280000 { 239 gpio@d8400000 {
185 status = "okay"; 240 status = "okay";
186 }; 241 };
187 242
188 i2c1: i2c@5cd00000 { 243 i2c0: i2c@e0280000 {
189 status = "okay"; 244 status = "okay";
190 }; 245 };
191 246
@@ -273,6 +328,7 @@
273 0x08080052 >; 328 0x08080052 >;
274 autorepeat; 329 autorepeat;
275 st,mode = <0>; 330 st,mode = <0>;
331 suspended_rate = <2000000>;
276 status = "okay"; 332 status = "okay";
277 }; 333 };
278 334
@@ -282,6 +338,81 @@
282 338
283 serial@e0000000 { 339 serial@e0000000 {
284 status = "okay"; 340 status = "okay";
341 pinctrl-names = "default";
342 pinctrl-0 = <>;
343 };
344
345 spi0: spi@e0100000 {
346 status = "okay";
347 num-cs = <3>;
348 cs-gpios = <&gpio1 7 0>, <&spics 0>, <&spics 1>;
349
350 stmpe610@0 {
351 compatible = "st,stmpe610";
352 reg = <0>;
353 #address-cells = <1>;
354 #size-cells = <0>;
355 spi-max-frequency = <1000000>;
356 spi-cpha;
357 pl022,hierarchy = <0>;
358 pl022,interface = <0>;
359 pl022,slave-tx-disable;
360 pl022,com-mode = <0>;
361 pl022,rx-level-trig = <0>;
362 pl022,tx-level-trig = <0>;
363 pl022,ctrl-len = <0x7>;
364 pl022,wait-state = <0>;
365 pl022,duplex = <0>;
366 interrupts = <6 0x4>;
367 interrupt-parent = <&gpio1>;
368 irq-trigger = <0x2>;
369
370 stmpe_touchscreen {
371 compatible = "st,stmpe-ts";
372 ts,sample-time = <4>;
373 ts,mod-12b = <1>;
374 ts,ref-sel = <0>;
375 ts,adc-freq = <1>;
376 ts,ave-ctrl = <1>;
377 ts,touch-det-delay = <2>;
378 ts,settling = <2>;
379 ts,fraction-z = <7>;
380 ts,i-drive = <1>;
381 };
382 };
383
384 m25p80@1 {
385 compatible = "st,m25p80";
386 reg = <1>;
387 spi-max-frequency = <12000000>;
388 spi-cpol;
389 spi-cpha;
390 pl022,hierarchy = <0>;
391 pl022,interface = <0>;
392 pl022,slave-tx-disable;
393 pl022,com-mode = <0x2>;
394 pl022,rx-level-trig = <0>;
395 pl022,tx-level-trig = <0>;
396 pl022,ctrl-len = <0x11>;
397 pl022,wait-state = <0>;
398 pl022,duplex = <0>;
399 };
400
401 spidev@2 {
402 compatible = "spidev";
403 reg = <2>;
404 spi-max-frequency = <25000000>;
405 spi-cpha;
406 pl022,hierarchy = <0>;
407 pl022,interface = <0>;
408 pl022,slave-tx-disable;
409 pl022,com-mode = <0x2>;
410 pl022,rx-level-trig = <0>;
411 pl022,tx-level-trig = <0>;
412 pl022,ctrl-len = <0x11>;
413 pl022,wait-state = <0>;
414 pl022,duplex = <0>;
415 };
285 }; 416 };
286 417
287 wdt@ec800620 { 418 wdt@ec800620 {
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index 419ea7413d23..1513c1927cc8 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -17,6 +17,18 @@
17 compatible = "st,spear1310"; 17 compatible = "st,spear1310";
18 18
19 ahb { 19 ahb {
20 spics: spics@e0700000{
21 compatible = "st,spear-spics-gpio";
22 reg = <0xe0700000 0x1000>;
23 st-spics,peripcfg-reg = <0x3b0>;
24 st-spics,sw-enable-bit = <12>;
25 st-spics,cs-value-bit = <11>;
26 st-spics,cs-enable-mask = <3>;
27 st-spics,cs-enable-shift = <8>;
28 gpio-controller;
29 #gpio-cells = <2>;
30 };
31
20 ahci@b1000000 { 32 ahci@b1000000 {
21 compatible = "snps,spear-ahci"; 33 compatible = "snps,spear-ahci";
22 reg = <0xb1000000 0x10000>; 34 reg = <0xb1000000 0x10000>;
@@ -43,6 +55,7 @@
43 reg = <0x5c400000 0x8000>; 55 reg = <0x5c400000 0x8000>;
44 interrupts = <0 95 0x4>; 56 interrupts = <0 95 0x4>;
45 interrupt-names = "macirq"; 57 interrupt-names = "macirq";
58 phy-mode = "mii";
46 status = "disabled"; 59 status = "disabled";
47 }; 60 };
48 61
@@ -51,6 +64,7 @@
51 reg = <0x5c500000 0x8000>; 64 reg = <0x5c500000 0x8000>;
52 interrupts = <0 96 0x4>; 65 interrupts = <0 96 0x4>;
53 interrupt-names = "macirq"; 66 interrupt-names = "macirq";
67 phy-mode = "mii";
54 status = "disabled"; 68 status = "disabled";
55 }; 69 };
56 70
@@ -59,6 +73,7 @@
59 reg = <0x5c600000 0x8000>; 73 reg = <0x5c600000 0x8000>;
60 interrupts = <0 97 0x4>; 74 interrupts = <0 97 0x4>;
61 interrupt-names = "macirq"; 75 interrupt-names = "macirq";
76 phy-mode = "rmii";
62 status = "disabled"; 77 status = "disabled";
63 }; 78 };
64 79
@@ -67,14 +82,14 @@
67 reg = <0x5c700000 0x8000>; 82 reg = <0x5c700000 0x8000>;
68 interrupts = <0 98 0x4>; 83 interrupts = <0 98 0x4>;
69 interrupt-names = "macirq"; 84 interrupt-names = "macirq";
85 phy-mode = "rgmii";
70 status = "disabled"; 86 status = "disabled";
71 }; 87 };
72 88
73 spi1: spi@5d400000 { 89 pinmux: pinmux@e0700000 {
74 compatible = "arm,pl022", "arm,primecell"; 90 compatible = "st,spear1310-pinmux";
75 reg = <0x5d400000 0x1000>; 91 reg = <0xe0700000 0x1000>;
76 interrupts = <0 99 0x4>; 92 #gpio-range-cells = <2>;
77 status = "disabled";
78 }; 93 };
79 94
80 apb { 95 apb {
@@ -141,6 +156,15 @@
141 status = "disabled"; 156 status = "disabled";
142 }; 157 };
143 158
159 spi1: spi@5d400000 {
160 compatible = "arm,pl022", "arm,primecell";
161 reg = <0x5d400000 0x1000>;
162 interrupts = <0 99 0x4>;
163 #address-cells = <1>;
164 #size-cells = <0>;
165 status = "disabled";
166 };
167
144 serial@5c800000 { 168 serial@5c800000 {
145 compatible = "arm,pl011", "arm,primecell"; 169 compatible = "arm,pl011", "arm,primecell";
146 reg = <0x5c800000 0x1000>; 170 reg = <0x5c800000 0x1000>;
@@ -179,6 +203,27 @@
179 thermal@e07008c4 { 203 thermal@e07008c4 {
180 st,thermal-flags = <0x7000>; 204 st,thermal-flags = <0x7000>;
181 }; 205 };
206
207 gpiopinctrl: gpio@d8400000 {
208 compatible = "st,spear-plgpio";
209 reg = <0xd8400000 0x1000>;
210 interrupts = <0 100 0x4>;
211 #interrupt-cells = <1>;
212 interrupt-controller;
213 gpio-controller;
214 #gpio-cells = <2>;
215 gpio-ranges = <&pinmux 0 246>;
216 status = "disabled";
217
218 st-plgpio,ngpio = <246>;
219 st-plgpio,enb-reg = <0xd0>;
220 st-plgpio,wdata-reg = <0x90>;
221 st-plgpio,dir-reg = <0xb0>;
222 st-plgpio,ie-reg = <0x30>;
223 st-plgpio,rdata-reg = <0x70>;
224 st-plgpio,mis-reg = <0x10>;
225 st-plgpio,eit-reg = <0x50>;
226 };
182 }; 227 };
183 }; 228 };
184}; 229};
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
index c9a54e06fb68..d6c30ae0a8d7 100644
--- a/arch/arm/boot/dts/spear1340-evb.dts
+++ b/arch/arm/boot/dts/spear1340-evb.dts
@@ -38,20 +38,15 @@
38 st,pins = "fsmc_8bit_grp"; 38 st,pins = "fsmc_8bit_grp";
39 st,function = "fsmc"; 39 st,function = "fsmc";
40 }; 40 };
41 kbd {
42 st,pins = "keyboard_row_col_grp",
43 "keyboard_col5_grp";
44 st,function = "keyboard";
45 };
46 uart0 { 41 uart0 {
47 st,pins = "uart0_grp", "uart0_enh_grp"; 42 st,pins = "uart0_grp";
48 st,function = "uart0"; 43 st,function = "uart0";
49 }; 44 };
50 i2c0-pmx { 45 i2c0 {
51 st,pins = "i2c0_grp"; 46 st,pins = "i2c0_grp";
52 st,function = "i2c0"; 47 st,function = "i2c0";
53 }; 48 };
54 i2c1-pmx { 49 i2c1 {
55 st,pins = "i2c1_grp"; 50 st,pins = "i2c1_grp";
56 st,function = "i2c1"; 51 st,function = "i2c1";
57 }; 52 };
@@ -64,14 +59,9 @@
64 st,function = "spdif_out"; 59 st,function = "spdif_out";
65 }; 60 };
66 ssp0 { 61 ssp0 {
67 st,pins = "ssp0_grp", "ssp0_cs1_grp", 62 st,pins = "ssp0_grp", "ssp0_cs1_grp", "ssp0_cs2_grp", "ssp0_cs3_grp";
68 "ssp0_cs3_grp";
69 st,function = "ssp0"; 63 st,function = "ssp0";
70 }; 64 };
71 pwm {
72 st,pins = "pwm2_grp", "pwm3_grp";
73 st,function = "pwm";
74 };
75 smi-pmx { 65 smi-pmx {
76 st,pins = "smi_grp"; 66 st,pins = "smi_grp";
77 st,function = "smi"; 67 st,function = "smi";
@@ -84,6 +74,18 @@
84 st,pins = "gmii_grp", "rgmii_grp"; 74 st,pins = "gmii_grp", "rgmii_grp";
85 st,function = "gmac"; 75 st,function = "gmac";
86 }; 76 };
77 cam0 {
78 st,pins = "cam0_grp";
79 st,function = "cam0";
80 };
81 cam1 {
82 st,pins = "cam1_grp";
83 st,function = "cam1";
84 };
85 cam2 {
86 st,pins = "cam2_grp";
87 st,function = "cam2";
88 };
87 cam3 { 89 cam3 {
88 st,pins = "cam3_grp"; 90 st,pins = "cam3_grp";
89 st,function = "cam3"; 91 st,function = "cam3";
@@ -108,9 +110,18 @@
108 st,pins = "sata_grp"; 110 st,pins = "sata_grp";
109 st,function = "sata"; 111 st,function = "sata";
110 }; 112 };
113 pcie {
114 st,pins = "pcie_grp";
115 st,function = "pcie";
116 };
117
111 }; 118 };
112 }; 119 };
113 120
121 ahci@b1000000 {
122 status = "okay";
123 };
124
114 dma@ea800000 { 125 dma@ea800000 {
115 status = "okay"; 126 status = "okay";
116 }; 127 };
@@ -121,9 +132,35 @@
121 132
122 fsmc: flash@b0000000 { 133 fsmc: flash@b0000000 {
123 status = "okay"; 134 status = "okay";
135
136 partition@0 {
137 label = "xloader";
138 reg = <0x0 0x200000>;
139 };
140 partition@200000 {
141 label = "u-boot";
142 reg = <0x200000 0x200000>;
143 };
144 partition@400000 {
145 label = "environment";
146 reg = <0x400000 0x100000>;
147 };
148 partition@500000 {
149 label = "dtb";
150 reg = <0x500000 0x100000>;
151 };
152 partition@600000 {
153 label = "linux";
154 reg = <0x600000 0xC00000>;
155 };
156 partition@1200000 {
157 label = "rootfs";
158 reg = <0x1200000 0x0>;
159 };
124 }; 160 };
125 161
126 gmac0: eth@e2000000 { 162 gmac0: eth@e2000000 {
163 phy-mode = "rgmii";
127 status = "okay"; 164 status = "okay";
128 }; 165 };
129 166
@@ -147,31 +184,62 @@
147 }; 184 };
148 partition@10000 { 185 partition@10000 {
149 label = "u-boot"; 186 label = "u-boot";
150 reg = <0x10000 0x40000>; 187 reg = <0x10000 0x50000>;
188 };
189 partition@60000 {
190 label = "environment";
191 reg = <0x60000 0x10000>;
192 };
193 partition@70000 {
194 label = "dtb";
195 reg = <0x70000 0x10000>;
151 }; 196 };
152 partition@50000 { 197 partition@80000 {
153 label = "linux"; 198 label = "linux";
154 reg = <0x50000 0x2c0000>; 199 reg = <0x80000 0x310000>;
155 }; 200 };
156 partition@310000 { 201 partition@390000 {
157 label = "rootfs"; 202 label = "rootfs";
158 reg = <0x310000 0x4f0000>; 203 reg = <0x390000 0x0>;
159 }; 204 };
160 }; 205 };
161 }; 206 };
162 207
163 spi0: spi@e0100000 { 208 ehci@e4800000 {
164 status = "okay"; 209 status = "okay";
165 }; 210 };
166 211
167 ehci@e4800000 { 212 gpio_keys {
168 status = "okay"; 213 compatible = "gpio-keys";
214 #address-cells = <1>;
215 #size-cells = <0>;
216
217 button@1 {
218 label = "wakeup";
219 linux,code = <0x100>;
220 gpios = <&gpio1 1 0x4>;
221 debounce-interval = <20>;
222 gpio-key,wakeup = <1>;
223 };
169 }; 224 };
170 225
171 ehci@e5800000 { 226 ehci@e5800000 {
172 status = "okay"; 227 status = "okay";
173 }; 228 };
174 229
230 i2s0: i2s-play@b2400000 {
231 status = "okay";
232 };
233
234 i2s1: i2s-rec@b2000000 {
235 status = "okay";
236 };
237
238 incodec: dir-hifi {
239 compatible = "dummy,dir-hifi";
240 status = "okay";
241 };
242
175 ohci@e4000000 { 243 ohci@e4000000 {
176 status = "okay"; 244 status = "okay";
177 }; 245 };
@@ -180,11 +248,43 @@
180 status = "okay"; 248 status = "okay";
181 }; 249 };
182 250
251 outcodec: dit-hifi {
252 compatible = "dummy,dit-hifi";
253 status = "okay";
254 };
255
256 sound {
257 compatible = "spear,spear-evb";
258 audio-controllers = <&spdif0 &spdif1 &i2s0 &i2s1>;
259 audio-codecs = <&incodec &outcodec &sta529 &sta529>;
260 codec_dai_name = "dir-hifi", "dit-hifi", "sta529-audio", "sta529-audio";
261 stream_name = "spdif-cap", "spdif-play", "i2s-play", "i2s-cap";
262 dai_name = "spdifin-pcm", "spdifout-pcm", "i2s0-pcm", "i2s1-pcm";
263 nr_controllers = <4>;
264 status = "okay";
265 };
266
267 spdif0: spdif-in@d0100000 {
268 status = "okay";
269 };
270
271 spdif1: spdif-out@d0000000 {
272 status = "okay";
273 };
274
183 apb { 275 apb {
184 adc@e0080000 { 276 adc@e0080000 {
185 status = "okay"; 277 status = "okay";
186 }; 278 };
187 279
280 i2s-play@b2400000 {
281 status = "okay";
282 };
283
284 i2s-rec@b2000000 {
285 status = "okay";
286 };
287
188 gpio0: gpio@e0600000 { 288 gpio0: gpio@e0600000 {
189 status = "okay"; 289 status = "okay";
190 }; 290 };
@@ -193,12 +293,42 @@
193 status = "okay"; 293 status = "okay";
194 }; 294 };
195 295
296 gpio@e2800000 {
297 status = "okay";
298 };
299
196 i2c0: i2c@e0280000 { 300 i2c0: i2c@e0280000 {
197 status = "okay"; 301 status = "okay";
302
303 sta529: sta529@1a {
304 compatible = "st,sta529";
305 reg = <0x1a>;
306 };
198 }; 307 };
199 308
200 i2c1: i2c@b4000000 { 309 i2c1: i2c@b4000000 {
201 status = "okay"; 310 status = "okay";
311
312 eeprom0@56 {
313 compatible = "st,eeprom";
314 reg = <0x56>;
315 };
316
317 stmpe801@41 {
318 compatible = "st,stmpe801";
319 #address-cells = <1>;
320 #size-cells = <0>;
321 reg = <0x41>;
322 interrupts = <4 0x4>;
323 interrupt-parent = <&gpio0>;
324 irq-trigger = <0x2>;
325
326 stmpegpio: stmpe_gpio {
327 compatible = "st,stmpe-gpio";
328 gpio-controller;
329 #gpio-cells = <2>;
330 };
331 };
202 }; 332 };
203 333
204 kbd@e0300000 { 334 kbd@e0300000 {
@@ -285,6 +415,7 @@
285 0x08080052 >; 415 0x08080052 >;
286 autorepeat; 416 autorepeat;
287 st,mode = <0>; 417 st,mode = <0>;
418 suspended_rate = <2000000>;
288 status = "okay"; 419 status = "okay";
289 }; 420 };
290 421
@@ -294,10 +425,92 @@
294 425
295 serial@e0000000 { 426 serial@e0000000 {
296 status = "okay"; 427 status = "okay";
428 pinctrl-names = "default";
429 pinctrl-0 = <>;
297 }; 430 };
298 431
299 serial@b4100000 { 432 serial@b4100000 {
300 status = "okay"; 433 status = "okay";
434 pinctrl-names = "default";
435 pinctrl-0 = <>;
436 };
437
438 spi0: spi@e0100000 {
439 status = "okay";
440 num-cs = <3>;
441 cs-gpios = <&gpiopinctrl 80 0>, <&gpiopinctrl 24 0>,
442 <&gpiopinctrl 85 0>;
443
444 m25p80@0 {
445 compatible = "m25p80";
446 reg = <0>;
447 spi-max-frequency = <12000000>;
448 spi-cpol;
449 spi-cpha;
450 pl022,hierarchy = <0>;
451 pl022,interface = <0>;
452 pl022,slave-tx-disable;
453 pl022,com-mode = <0x2>;
454 pl022,rx-level-trig = <0>;
455 pl022,tx-level-trig = <0>;
456 pl022,ctrl-len = <0x11>;
457 pl022,wait-state = <0>;
458 pl022,duplex = <0>;
459 };
460
461 stmpe610@1 {
462 compatible = "st,stmpe610";
463 spi-max-frequency = <1000000>;
464 spi-cpha;
465 reg = <1>;
466 pl022,hierarchy = <0>;
467 pl022,interface = <0>;
468 pl022,slave-tx-disable;
469 pl022,com-mode = <0>;
470 pl022,rx-level-trig = <0>;
471 pl022,tx-level-trig = <0>;
472 pl022,ctrl-len = <0x7>;
473 pl022,wait-state = <0>;
474 pl022,duplex = <0>;
475 interrupts = <100 0>;
476 interrupt-parent = <&gpiopinctrl>;
477 irq-trigger = <0x2>;
478 #address-cells = <1>;
479 #size-cells = <0>;
480
481 stmpe_touchscreen {
482 compatible = "st,stmpe-ts";
483 ts,sample-time = <4>;
484 ts,mod-12b = <1>;
485 ts,ref-sel = <0>;
486 ts,adc-freq = <1>;
487 ts,ave-ctrl = <1>;
488 ts,touch-det-delay = <2>;
489 ts,settling = <2>;
490 ts,fraction-z = <7>;
491 ts,i-drive = <1>;
492 };
493 };
494
495 spidev@2 {
496 compatible = "spidev";
497 reg = <2>;
498 spi-max-frequency = <25000000>;
499 spi-cpha;
500 pl022,hierarchy = <0>;
501 pl022,interface = <0>;
502 pl022,slave-tx-disable;
503 pl022,com-mode = <0x2>;
504 pl022,rx-level-trig = <0>;
505 pl022,tx-level-trig = <0>;
506 pl022,ctrl-len = <0x11>;
507 pl022,wait-state = <0>;
508 pl022,duplex = <0>;
509 };
510 };
511
512 timer@ec800600 {
513 status = "okay";
301 }; 514 };
302 515
303 wdt@ec800620 { 516 wdt@ec800620 {
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index d71fe2a68f09..34da11aa6795 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -17,6 +17,20 @@
17 compatible = "st,spear1340"; 17 compatible = "st,spear1340";
18 18
19 ahb { 19 ahb {
20
21 spics: spics@e0700000{
22 compatible = "st,spear-spics-gpio";
23 reg = <0xe0700000 0x1000>;
24 st-spics,peripcfg-reg = <0x42c>;
25 st-spics,sw-enable-bit = <21>;
26 st-spics,cs-value-bit = <20>;
27 st-spics,cs-enable-mask = <3>;
28 st-spics,cs-enable-shift = <18>;
29 gpio-controller;
30 #gpio-cells = <2>;
31 status = "disabled";
32 };
33
20 ahci@b1000000 { 34 ahci@b1000000 {
21 compatible = "snps,spear-ahci"; 35 compatible = "snps,spear-ahci";
22 reg = <0xb1000000 0x10000>; 36 reg = <0xb1000000 0x10000>;
@@ -24,9 +38,61 @@
24 status = "disabled"; 38 status = "disabled";
25 }; 39 };
26 40
41 i2s-play@b2400000 {
42 compatible = "snps,designware-i2s";
43 reg = <0xb2400000 0x10000>;
44 interrupt-names = "play_irq";
45 interrupts = <0 98 0x4
46 0 99 0x4>;
47 play;
48 channel = <8>;
49 status = "disabled";
50 };
51
52 i2s-rec@b2000000 {
53 compatible = "snps,designware-i2s";
54 reg = <0xb2000000 0x10000>;
55 interrupt-names = "record_irq";
56 interrupts = <0 100 0x4
57 0 101 0x4>;
58 record;
59 channel = <8>;
60 status = "disabled";
61 };
62
63 pinmux: pinmux@e0700000 {
64 compatible = "st,spear1340-pinmux";
65 reg = <0xe0700000 0x1000>;
66 #gpio-range-cells = <2>;
67 };
68
69 pwm: pwm@e0180000 {
70 compatible ="st,spear13xx-pwm";
71 reg = <0xe0180000 0x1000>;
72 #pwm-cells = <2>;
73 status = "disabled";
74 };
75
76 spdif-in@d0100000 {
77 compatible = "st,spdif-in";
78 reg = < 0xd0100000 0x20000
79 0xd0110000 0x10000 >;
80 interrupts = <0 84 0x4>;
81 status = "disabled";
82 };
83
84 spdif-out@d0000000 {
85 compatible = "st,spdif-out";
86 reg = <0xd0000000 0x20000>;
87 interrupts = <0 85 0x4>;
88 status = "disabled";
89 };
90
27 spi1: spi@5d400000 { 91 spi1: spi@5d400000 {
28 compatible = "arm,pl022", "arm,primecell"; 92 compatible = "arm,pl022", "arm,primecell";
29 reg = <0x5d400000 0x1000>; 93 reg = <0x5d400000 0x1000>;
94 #address-cells = <1>;
95 #size-cells = <0>;
30 interrupts = <0 99 0x4>; 96 interrupts = <0 99 0x4>;
31 status = "disabled"; 97 status = "disabled";
32 }; 98 };
@@ -38,6 +104,7 @@
38 compatible = "snps,designware-i2c"; 104 compatible = "snps,designware-i2c";
39 reg = <0xb4000000 0x1000>; 105 reg = <0xb4000000 0x1000>;
40 interrupts = <0 104 0x4>; 106 interrupts = <0 104 0x4>;
107 write-16bit;
41 status = "disabled"; 108 status = "disabled";
42 }; 109 };
43 110
@@ -51,6 +118,26 @@
51 thermal@e07008c4 { 118 thermal@e07008c4 {
52 st,thermal-flags = <0x2a00>; 119 st,thermal-flags = <0x2a00>;
53 }; 120 };
121
122 gpiopinctrl: gpio@e2800000 {
123 compatible = "st,spear-plgpio";
124 reg = <0xe2800000 0x1000>;
125 interrupts = <0 107 0x4>;
126 #interrupt-cells = <1>;
127 interrupt-controller;
128 gpio-controller;
129 #gpio-cells = <2>;
130 gpio-ranges = <&pinmux 0 252>;
131 status = "disabled";
132
133 st-plgpio,ngpio = <250>;
134 st-plgpio,wdata-reg = <0x40>;
135 st-plgpio,dir-reg = <0x00>;
136 st-plgpio,ie-reg = <0x80>;
137 st-plgpio,rdata-reg = <0x20>;
138 st-plgpio,mis-reg = <0xa0>;
139 st-plgpio,eit-reg = <0x60>;
140 };
54 }; 141 };
55 }; 142 };
56}; 143};
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index f7b84aced654..b4ca60f4eb42 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -64,12 +64,26 @@
64 bootargs = "console=ttyAMA0,115200"; 64 bootargs = "console=ttyAMA0,115200";
65 }; 65 };
66 66
67 cpufreq {
68 compatible = "st,cpufreq-spear";
69 cpufreq_tbl = < 166000
70 200000
71 250000
72 300000
73 400000
74 500000
75 600000 >;
76 status = "disabled";
77 };
78
67 ahb { 79 ahb {
68 #address-cells = <1>; 80 #address-cells = <1>;
69 #size-cells = <1>; 81 #size-cells = <1>;
70 compatible = "simple-bus"; 82 compatible = "simple-bus";
71 ranges = <0x50000000 0x50000000 0x10000000 83 ranges = <0x50000000 0x50000000 0x10000000
72 0xb0000000 0xb0000000 0x10000000 84 0xb0000000 0xb0000000 0x10000000
85 0xd0000000 0xd0000000 0x02000000
86 0xd8000000 0xd8000000 0x01000000
73 0xe0000000 0xe0000000 0x10000000>; 87 0xe0000000 0xe0000000 0x10000000>;
74 88
75 sdhci@b3000000 { 89 sdhci@b3000000 {
@@ -81,7 +95,7 @@
81 95
82 cf@b2800000 { 96 cf@b2800000 {
83 compatible = "arasan,cf-spear1340"; 97 compatible = "arasan,cf-spear1340";
84 reg = <0xb2800000 0x100>; 98 reg = <0xb2800000 0x1000>;
85 interrupts = <0 29 0x4>; 99 interrupts = <0 29 0x4>;
86 status = "disabled"; 100 status = "disabled";
87 }; 101 };
@@ -104,15 +118,16 @@
104 compatible = "st,spear600-fsmc-nand"; 118 compatible = "st,spear600-fsmc-nand";
105 #address-cells = <1>; 119 #address-cells = <1>;
106 #size-cells = <1>; 120 #size-cells = <1>;
107 reg = <0xb0000000 0x1000 /* FSMC Register */ 121 reg = <0xb0000000 0x1000 /* FSMC Register*/
108 0xb0800000 0x0010>; /* NAND Base */ 122 0xb0800000 0x0010 /* NAND Base DATA */
109 reg-names = "fsmc_regs", "nand_data"; 123 0xb0820000 0x0010 /* NAND Base ADDR */
124 0xb0810000 0x0010>; /* NAND Base CMD */
125 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
110 interrupts = <0 20 0x4 126 interrupts = <0 20 0x4
111 0 21 0x4 127 0 21 0x4
112 0 22 0x4 128 0 22 0x4
113 0 23 0x4>; 129 0 23 0x4>;
114 st,ale-off = <0x20000>; 130 st,mode = <2>;
115 st,cle-off = <0x10000>;
116 status = "disabled"; 131 status = "disabled";
117 }; 132 };
118 133
@@ -125,6 +140,13 @@
125 status = "disabled"; 140 status = "disabled";
126 }; 141 };
127 142
143 pcm {
144 compatible = "st,pcm-audio";
145 #address-cells = <0>;
146 #size-cells = <0>;
147 status = "disabled";
148 };
149
128 smi: flash@ea000000 { 150 smi: flash@ea000000 {
129 compatible = "st,spear600-smi"; 151 compatible = "st,spear600-smi";
130 #address-cells = <1>; 152 #address-cells = <1>;
@@ -134,17 +156,11 @@
134 status = "disabled"; 156 status = "disabled";
135 }; 157 };
136 158
137 spi0: spi@e0100000 {
138 compatible = "arm,pl022", "arm,primecell";
139 reg = <0xe0100000 0x1000>;
140 interrupts = <0 31 0x4>;
141 status = "disabled";
142 };
143
144 ehci@e4800000 { 159 ehci@e4800000 {
145 compatible = "st,spear600-ehci", "usb-ehci"; 160 compatible = "st,spear600-ehci", "usb-ehci";
146 reg = <0xe4800000 0x1000>; 161 reg = <0xe4800000 0x1000>;
147 interrupts = <0 64 0x4>; 162 interrupts = <0 64 0x4>;
163 usbh0_id = <0>;
148 status = "disabled"; 164 status = "disabled";
149 }; 165 };
150 166
@@ -152,6 +168,7 @@
152 compatible = "st,spear600-ehci", "usb-ehci"; 168 compatible = "st,spear600-ehci", "usb-ehci";
153 reg = <0xe5800000 0x1000>; 169 reg = <0xe5800000 0x1000>;
154 interrupts = <0 66 0x4>; 170 interrupts = <0 66 0x4>;
171 usbh1_id = <1>;
155 status = "disabled"; 172 status = "disabled";
156 }; 173 };
157 174
@@ -159,6 +176,7 @@
159 compatible = "st,spear600-ohci", "usb-ohci"; 176 compatible = "st,spear600-ohci", "usb-ohci";
160 reg = <0xe4000000 0x1000>; 177 reg = <0xe4000000 0x1000>;
161 interrupts = <0 65 0x4>; 178 interrupts = <0 65 0x4>;
179 usbh0_id = <0>;
162 status = "disabled"; 180 status = "disabled";
163 }; 181 };
164 182
@@ -166,6 +184,7 @@
166 compatible = "st,spear600-ohci", "usb-ohci"; 184 compatible = "st,spear600-ohci", "usb-ohci";
167 reg = <0xe5000000 0x1000>; 185 reg = <0xe5000000 0x1000>;
168 interrupts = <0 67 0x4>; 186 interrupts = <0 67 0x4>;
187 usbh1_id = <1>;
169 status = "disabled"; 188 status = "disabled";
170 }; 189 };
171 190
@@ -175,6 +194,8 @@
175 compatible = "simple-bus"; 194 compatible = "simple-bus";
176 ranges = <0x50000000 0x50000000 0x10000000 195 ranges = <0x50000000 0x50000000 0x10000000
177 0xb0000000 0xb0000000 0x10000000 196 0xb0000000 0xb0000000 0x10000000
197 0xd0000000 0xd0000000 0x02000000
198 0xd8000000 0xd8000000 0x01000000
178 0xe0000000 0xe0000000 0x10000000>; 199 0xe0000000 0xe0000000 0x10000000>;
179 200
180 gpio0: gpio@e0600000 { 201 gpio0: gpio@e0600000 {
@@ -215,8 +236,35 @@
215 status = "disabled"; 236 status = "disabled";
216 }; 237 };
217 238
239 i2s@e0180000 {
240 compatible = "st,designware-i2s";
241 reg = <0xe0180000 0x1000>;
242 interrupt-names = "play_irq", "record_irq";
243 interrupts = <0 10 0x4
244 0 11 0x4 >;
245 status = "disabled";
246 };
247
248 i2s@e0200000 {
249 compatible = "st,designware-i2s";
250 reg = <0xe0200000 0x1000>;
251 interrupt-names = "play_irq", "record_irq";
252 interrupts = <0 26 0x4
253 0 53 0x4>;
254 status = "disabled";
255 };
256
257 spi0: spi@e0100000 {
258 compatible = "arm,pl022", "arm,primecell";
259 reg = <0xe0100000 0x1000>;
260 #address-cells = <1>;
261 #size-cells = <0>;
262 interrupts = <0 31 0x4>;
263 status = "disabled";
264 };
265
218 rtc@e0580000 { 266 rtc@e0580000 {
219 compatible = "st,spear-rtc"; 267 compatible = "st,spear600-rtc";
220 reg = <0xe0580000 0x1000>; 268 reg = <0xe0580000 0x1000>;
221 interrupts = <0 36 0x4>; 269 interrupts = <0 36 0x4>;
222 status = "disabled"; 270 status = "disabled";
@@ -232,7 +280,7 @@
232 adc@e0080000 { 280 adc@e0080000 {
233 compatible = "st,spear600-adc"; 281 compatible = "st,spear600-adc";
234 reg = <0xe0080000 0x1000>; 282 reg = <0xe0080000 0x1000>;
235 interrupts = <0 44 0x4>; 283 interrupts = <0 12 0x4>;
236 status = "disabled"; 284 status = "disabled";
237 }; 285 };
238 286
@@ -245,7 +293,8 @@
245 timer@ec800600 { 293 timer@ec800600 {
246 compatible = "arm,cortex-a9-twd-timer"; 294 compatible = "arm,cortex-a9-twd-timer";
247 reg = <0xec800600 0x20>; 295 reg = <0xec800600 0x20>;
248 interrupts = <1 13 0x301>; 296 interrupts = <1 13 0x4>;
297 status = "disabled";
249 }; 298 };
250 299
251 wdt@ec800620 { 300 wdt@ec800620 {
@@ -257,6 +306,7 @@
257 thermal@e07008c4 { 306 thermal@e07008c4 {
258 compatible = "st,thermal-spear1340"; 307 compatible = "st,thermal-spear1340";
259 reg = <0xe07008c4 0x4>; 308 reg = <0xe07008c4 0x4>;
309 thermal_flags = <0x7000>;
260 }; 310 };
261 }; 311 };
262 }; 312 };
diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts
index 1e7c7a8e2123..5de1431653e4 100644
--- a/arch/arm/boot/dts/spear300-evb.dts
+++ b/arch/arm/boot/dts/spear300-evb.dts
@@ -100,15 +100,23 @@
100 }; 100 };
101 partition@10000 { 101 partition@10000 {
102 label = "u-boot"; 102 label = "u-boot";
103 reg = <0x10000 0x40000>; 103 reg = <0x10000 0x50000>;
104 }; 104 };
105 partition@50000 { 105 partition@60000 {
106 label = "environment";
107 reg = <0x60000 0x10000>;
108 };
109 partition@70000 {
110 label = "dtb";
111 reg = <0x70000 0x10000>;
112 };
113 partition@80000 {
106 label = "linux"; 114 label = "linux";
107 reg = <0x50000 0x2c0000>; 115 reg = <0x80000 0x310000>;
108 }; 116 };
109 partition@310000 { 117 partition@390000 {
110 label = "rootfs"; 118 label = "rootfs";
111 reg = <0x310000 0x4f0000>; 119 reg = <0x390000 0x0>;
112 }; 120 };
113 }; 121 };
114 }; 122 };
@@ -235,6 +243,8 @@
235 243
236 serial@d0000000 { 244 serial@d0000000 {
237 status = "okay"; 245 status = "okay";
246 pinctrl-names = "default";
247 pinctrl-0 = <>;
238 }; 248 };
239 249
240 wdt@fc880000 { 250 wdt@fc880000 {
diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/spear300.dtsi
index ed3627c116cc..f79b3dfaabe6 100644
--- a/arch/arm/boot/dts/spear300.dtsi
+++ b/arch/arm/boot/dts/spear300.dtsi
@@ -27,7 +27,7 @@
27 }; 27 };
28 28
29 clcd@60000000 { 29 clcd@60000000 {
30 compatible = "arm,clcd-pl110", "arm,primecell"; 30 compatible = "arm,pl110", "arm,primecell";
31 reg = <0x60000000 0x1000>; 31 reg = <0x60000000 0x1000>;
32 interrupts = <30>; 32 interrupts = <30>;
33 status = "disabled"; 33 status = "disabled";
@@ -38,10 +38,10 @@
38 #address-cells = <1>; 38 #address-cells = <1>;
39 #size-cells = <1>; 39 #size-cells = <1>;
40 reg = <0x94000000 0x1000 /* FSMC Register */ 40 reg = <0x94000000 0x1000 /* FSMC Register */
41 0x80000000 0x0010>; /* NAND Base */ 41 0x80000000 0x0010 /* NAND Base DATA */
42 reg-names = "fsmc_regs", "nand_data"; 42 0x80020000 0x0010 /* NAND Base ADDR */
43 st,ale-off = <0x20000>; 43 0x80010000 0x0010>; /* NAND Base CMD */
44 st,cle-off = <0x10000>; 44 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
45 status = "disabled"; 45 status = "disabled";
46 }; 46 };
47 47
@@ -52,6 +52,14 @@
52 status = "disabled"; 52 status = "disabled";
53 }; 53 };
54 54
55 shirq: interrupt-controller@0x50000000 {
56 compatible = "st,spear300-shirq";
57 reg = <0x50000000 0x1000>;
58 interrupts = <28>;
59 #interrupt-cells = <1>;
60 interrupt-controller;
61 };
62
55 apb { 63 apb {
56 #address-cells = <1>; 64 #address-cells = <1>;
57 #size-cells = <1>; 65 #size-cells = <1>;
@@ -64,12 +72,16 @@
64 compatible = "arm,pl061", "arm,primecell"; 72 compatible = "arm,pl061", "arm,primecell";
65 gpio-controller; 73 gpio-controller;
66 reg = <0xa9000000 0x1000>; 74 reg = <0xa9000000 0x1000>;
75 interrupts = <8>;
76 interrupt-parent = <&shirq>;
67 status = "disabled"; 77 status = "disabled";
68 }; 78 };
69 79
70 kbd@a0000000 { 80 kbd@a0000000 {
71 compatible = "st,spear300-kbd"; 81 compatible = "st,spear300-kbd";
72 reg = <0xa0000000 0x1000>; 82 reg = <0xa0000000 0x1000>;
83 interrupts = <7>;
84 interrupt-parent = <&shirq>;
73 status = "disabled"; 85 status = "disabled";
74 }; 86 };
75 }; 87 };
diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts
index b00544e0cd5d..b09632963d15 100644
--- a/arch/arm/boot/dts/spear310-evb.dts
+++ b/arch/arm/boot/dts/spear310-evb.dts
@@ -114,15 +114,23 @@
114 }; 114 };
115 partition@10000 { 115 partition@10000 {
116 label = "u-boot"; 116 label = "u-boot";
117 reg = <0x10000 0x40000>; 117 reg = <0x10000 0x50000>;
118 }; 118 };
119 partition@50000 { 119 partition@60000 {
120 label = "environment";
121 reg = <0x60000 0x10000>;
122 };
123 partition@70000 {
124 label = "dtb";
125 reg = <0x70000 0x10000>;
126 };
127 partition@80000 {
120 label = "linux"; 128 label = "linux";
121 reg = <0x50000 0x2c0000>; 129 reg = <0x80000 0x310000>;
122 }; 130 };
123 partition@310000 { 131 partition@390000 {
124 label = "rootfs"; 132 label = "rootfs";
125 reg = <0x310000 0x4f0000>; 133 reg = <0x390000 0x0>;
126 }; 134 };
127 }; 135 };
128 }; 136 };
@@ -158,26 +166,38 @@
158 166
159 serial@d0000000 { 167 serial@d0000000 {
160 status = "okay"; 168 status = "okay";
169 pinctrl-names = "default";
170 pinctrl-0 = <>;
161 }; 171 };
162 172
163 serial@b2000000 { 173 serial@b2000000 {
164 status = "okay"; 174 status = "okay";
175 pinctrl-names = "default";
176 pinctrl-0 = <>;
165 }; 177 };
166 178
167 serial@b2080000 { 179 serial@b2080000 {
168 status = "okay"; 180 status = "okay";
181 pinctrl-names = "default";
182 pinctrl-0 = <>;
169 }; 183 };
170 184
171 serial@b2100000 { 185 serial@b2100000 {
172 status = "okay"; 186 status = "okay";
187 pinctrl-names = "default";
188 pinctrl-0 = <>;
173 }; 189 };
174 190
175 serial@b2180000 { 191 serial@b2180000 {
176 status = "okay"; 192 status = "okay";
193 pinctrl-names = "default";
194 pinctrl-0 = <>;
177 }; 195 };
178 196
179 serial@b2200000 { 197 serial@b2200000 {
180 status = "okay"; 198 status = "okay";
199 pinctrl-names = "default";
200 pinctrl-0 = <>;
181 }; 201 };
182 202
183 wdt@fc880000 { 203 wdt@fc880000 {
diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi
index 62fc4fb3e5f9..ab45b8c81982 100644
--- a/arch/arm/boot/dts/spear310.dtsi
+++ b/arch/arm/boot/dts/spear310.dtsi
@@ -22,9 +22,10 @@
22 0xb0000000 0xb0000000 0x10000000 22 0xb0000000 0xb0000000 0x10000000
23 0xd0000000 0xd0000000 0x30000000>; 23 0xd0000000 0xd0000000 0x30000000>;
24 24
25 pinmux@b4000000 { 25 pinmux: pinmux@b4000000 {
26 compatible = "st,spear310-pinmux"; 26 compatible = "st,spear310-pinmux";
27 reg = <0xb4000000 0x1000>; 27 reg = <0xb4000000 0x1000>;
28 #gpio-range-cells = <2>;
28 }; 29 };
29 30
30 fsmc: flash@44000000 { 31 fsmc: flash@44000000 {
@@ -32,13 +33,21 @@
32 #address-cells = <1>; 33 #address-cells = <1>;
33 #size-cells = <1>; 34 #size-cells = <1>;
34 reg = <0x44000000 0x1000 /* FSMC Register */ 35 reg = <0x44000000 0x1000 /* FSMC Register */
35 0x40000000 0x0010>; /* NAND Base */ 36 0x40000000 0x0010 /* NAND Base DATA */
36 reg-names = "fsmc_regs", "nand_data"; 37 0x40020000 0x0010 /* NAND Base ADDR */
37 st,ale-off = <0x10000>; 38 0x40010000 0x0010>; /* NAND Base CMD */
38 st,cle-off = <0x20000>; 39 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
39 status = "disabled"; 40 status = "disabled";
40 }; 41 };
41 42
43 shirq: interrupt-controller@0xb4000000 {
44 compatible = "st,spear310-shirq";
45 reg = <0xb4000000 0x1000>;
46 interrupts = <28 29 30 1>;
47 #interrupt-cells = <1>;
48 interrupt-controller;
49 };
50
42 apb { 51 apb {
43 #address-cells = <1>; 52 #address-cells = <1>;
44 #size-cells = <1>; 53 #size-cells = <1>;
@@ -49,32 +58,61 @@
49 serial@b2000000 { 58 serial@b2000000 {
50 compatible = "arm,pl011", "arm,primecell"; 59 compatible = "arm,pl011", "arm,primecell";
51 reg = <0xb2000000 0x1000>; 60 reg = <0xb2000000 0x1000>;
61 interrupts = <8>;
62 interrupt-parent = <&shirq>;
52 status = "disabled"; 63 status = "disabled";
53 }; 64 };
54 65
55 serial@b2080000 { 66 serial@b2080000 {
56 compatible = "arm,pl011", "arm,primecell"; 67 compatible = "arm,pl011", "arm,primecell";
57 reg = <0xb2080000 0x1000>; 68 reg = <0xb2080000 0x1000>;
69 interrupts = <9>;
70 interrupt-parent = <&shirq>;
58 status = "disabled"; 71 status = "disabled";
59 }; 72 };
60 73
61 serial@b2100000 { 74 serial@b2100000 {
62 compatible = "arm,pl011", "arm,primecell"; 75 compatible = "arm,pl011", "arm,primecell";
63 reg = <0xb2100000 0x1000>; 76 reg = <0xb2100000 0x1000>;
77 interrupts = <10>;
78 interrupt-parent = <&shirq>;
64 status = "disabled"; 79 status = "disabled";
65 }; 80 };
66 81
67 serial@b2180000 { 82 serial@b2180000 {
68 compatible = "arm,pl011", "arm,primecell"; 83 compatible = "arm,pl011", "arm,primecell";
69 reg = <0xb2180000 0x1000>; 84 reg = <0xb2180000 0x1000>;
85 interrupts = <11>;
86 interrupt-parent = <&shirq>;
70 status = "disabled"; 87 status = "disabled";
71 }; 88 };
72 89
73 serial@b2200000 { 90 serial@b2200000 {
74 compatible = "arm,pl011", "arm,primecell"; 91 compatible = "arm,pl011", "arm,primecell";
75 reg = <0xb2200000 0x1000>; 92 reg = <0xb2200000 0x1000>;
93 interrupts = <12>;
94 interrupt-parent = <&shirq>;
76 status = "disabled"; 95 status = "disabled";
77 }; 96 };
97
98 gpiopinctrl: gpio@b4000000 {
99 compatible = "st,spear-plgpio";
100 reg = <0xb4000000 0x1000>;
101 #interrupt-cells = <1>;
102 interrupt-controller;
103 gpio-controller;
104 #gpio-cells = <2>;
105 gpio-ranges = <&pinmux 0 102>;
106 status = "disabled";
107
108 st-plgpio,ngpio = <102>;
109 st-plgpio,enb-reg = <0x10>;
110 st-plgpio,wdata-reg = <0x20>;
111 st-plgpio,dir-reg = <0x30>;
112 st-plgpio,ie-reg = <0x50>;
113 st-plgpio,rdata-reg = <0x40>;
114 st-plgpio,mis-reg = <0x60>;
115 };
78 }; 116 };
79 }; 117 };
80}; 118};
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
index 082328bd64ab..fdedbb514102 100644
--- a/arch/arm/boot/dts/spear320-evb.dts
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -76,20 +76,12 @@
76 st,function = "mii2"; 76 st,function = "mii2";
77 }; 77 };
78 pwm0_1 { 78 pwm0_1 {
79 st,pins = "pwm0_1_pin_14_15_grp"; 79 st,pins = "pwm0_1_pin_37_38_grp";
80 st,function = "pwm0_1"; 80 st,function = "pwm0_1";
81 }; 81 };
82 pwm2 {
83 st,pins = "pwm2_pin_13_grp";
84 st,function = "pwm2";
85 };
86 }; 82 };
87 }; 83 };
88 84
89 clcd@90000000 {
90 status = "okay";
91 };
92
93 dma@fc400000 { 85 dma@fc400000 {
94 status = "okay"; 86 status = "okay";
95 }; 87 };
@@ -103,6 +95,7 @@
103 }; 95 };
104 96
105 sdhci@70000000 { 97 sdhci@70000000 {
98 power-gpio = <&gpiopinctrl 61 1>;
106 status = "okay"; 99 status = "okay";
107 }; 100 };
108 101
@@ -122,15 +115,23 @@
122 }; 115 };
123 partition@10000 { 116 partition@10000 {
124 label = "u-boot"; 117 label = "u-boot";
125 reg = <0x10000 0x40000>; 118 reg = <0x10000 0x50000>;
119 };
120 partition@60000 {
121 label = "environment";
122 reg = <0x60000 0x10000>;
126 }; 123 };
127 partition@50000 { 124 partition@70000 {
125 label = "dtb";
126 reg = <0x70000 0x10000>;
127 };
128 partition@80000 {
128 label = "linux"; 129 label = "linux";
129 reg = <0x50000 0x2c0000>; 130 reg = <0x80000 0x310000>;
130 }; 131 };
131 partition@310000 { 132 partition@390000 {
132 label = "rootfs"; 133 label = "rootfs";
133 reg = <0x310000 0x4f0000>; 134 reg = <0x390000 0x0>;
134 }; 135 };
135 }; 136 };
136 }; 137 };
@@ -164,6 +165,10 @@
164 status = "okay"; 165 status = "okay";
165 }; 166 };
166 167
168 gpio@b3000000 {
169 status = "okay";
170 };
171
167 i2c0: i2c@d0180000 { 172 i2c0: i2c@d0180000 {
168 status = "okay"; 173 status = "okay";
169 }; 174 };
@@ -178,14 +183,20 @@
178 183
179 serial@d0000000 { 184 serial@d0000000 {
180 status = "okay"; 185 status = "okay";
186 pinctrl-names = "default";
187 pinctrl-0 = <>;
181 }; 188 };
182 189
183 serial@a3000000 { 190 serial@a3000000 {
184 status = "okay"; 191 status = "okay";
192 pinctrl-names = "default";
193 pinctrl-0 = <>;
185 }; 194 };
186 195
187 serial@a4000000 { 196 serial@a4000000 {
188 status = "okay"; 197 status = "okay";
198 pinctrl-names = "default";
199 pinctrl-0 = <>;
189 }; 200 };
190 201
191 wdt@fc880000 { 202 wdt@fc880000 {
diff --git a/arch/arm/boot/dts/spear320-hmi.dts b/arch/arm/boot/dts/spear320-hmi.dts
new file mode 100644
index 000000000000..3075d2d3a8be
--- /dev/null
+++ b/arch/arm/boot/dts/spear320-hmi.dts
@@ -0,0 +1,305 @@
1/*
2 * DTS file for SPEAr320 Evaluation Baord
3 *
4 * Copyright 2012 Shiraz Hashim <shiraz.hashim@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "spear320.dtsi"
16
17/ {
18 model = "ST SPEAr320 HMI Board";
19 compatible = "st,spear320-hmi", "st,spear320";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 reg = <0 0x40000000>;
25 };
26
27 ahb {
28 pinmux@b3000000 {
29 st,pinmux-mode = <4>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&state_default>;
32
33 state_default: pinmux {
34 i2c0 {
35 st,pins = "i2c0_grp";
36 st,function = "i2c0";
37 };
38 ssp0 {
39 st,pins = "ssp0_grp";
40 st,function = "ssp0";
41 };
42 uart0 {
43 st,pins = "uart0_grp";
44 st,function = "uart0";
45 };
46 clcd {
47 st,pins = "clcd_grp";
48 st,function = "clcd";
49 };
50 fsmc {
51 st,pins = "fsmc_8bit_grp";
52 st,function = "fsmc";
53 };
54 sdhci {
55 st,pins = "sdhci_cd_12_grp";
56 st,function = "sdhci";
57 };
58 i2s {
59 st,pins = "i2s_grp";
60 st,function = "i2s";
61 };
62 uart1 {
63 st,pins = "uart1_grp";
64 st,function = "uart1";
65 };
66 uart2 {
67 st,pins = "uart2_grp";
68 st,function = "uart2";
69 };
70 can0 {
71 st,pins = "can0_grp";
72 st,function = "can0";
73 };
74 can1 {
75 st,pins = "can1_grp";
76 st,function = "can1";
77 };
78 mii0_1 {
79 st,pins = "rmii0_1_grp";
80 st,function = "mii0_1";
81 };
82 pwm0_1 {
83 st,pins = "pwm0_1_pin_37_38_grp";
84 st,function = "pwm0_1";
85 };
86 pwm2 {
87 st,pins = "pwm2_pin_34_grp";
88 st,function = "pwm2";
89 };
90 };
91 };
92
93 clcd@90000000 {
94 status = "okay";
95 };
96
97 dma@fc400000 {
98 status = "okay";
99 };
100
101 ehci@e1800000 {
102 status = "okay";
103 };
104
105 fsmc: flash@4c000000 {
106 status = "okay";
107
108 partition@0 {
109 label = "xloader";
110 reg = <0x0 0x80000>;
111 };
112 partition@80000 {
113 label = "u-boot";
114 reg = <0x80000 0x140000>;
115 };
116 partition@1C0000 {
117 label = "environment";
118 reg = <0x1C0000 0x40000>;
119 };
120 partition@200000 {
121 label = "dtb";
122 reg = <0x200000 0x40000>;
123 };
124 partition@240000 {
125 label = "linux";
126 reg = <0x240000 0xC00000>;
127 };
128 partition@E40000 {
129 label = "rootfs";
130 reg = <0xE40000 0x0>;
131 };
132 };
133
134 gpio_keys {
135 compatible = "gpio-keys";
136 #address-cells = <1>;
137 #size-cells = <0>;
138
139 button@1 {
140 label = "user button 1";
141 linux,code = <0x100>;
142 gpios = <&stmpegpio 3 0x4>;
143 debounce-interval = <20>;
144 gpio-key,wakeup = <1>;
145 };
146
147 button@2 {
148 label = "user button 2";
149 linux,code = <0x200>;
150 gpios = <&stmpegpio 2 0x4>;
151 debounce-interval = <20>;
152 gpio-key,wakeup = <1>;
153 };
154 };
155
156 ohci@e1900000 {
157 status = "okay";
158 };
159
160 ohci@e2100000 {
161 status = "okay";
162 };
163
164 pwm: pwm@a8000000 {
165 status = "okay";
166 };
167
168 sdhci@70000000 {
169 power-gpio = <&gpiopinctrl 50 1>;
170 power_always_enb;
171 status = "okay";
172 };
173
174 smi: flash@fc000000 {
175 status = "okay";
176 clock-rate=<50000000>;
177
178 flash@f8000000 {
179 #address-cells = <1>;
180 #size-cells = <1>;
181 reg = <0xf8000000 0x800000>;
182 st,smi-fast-mode;
183
184 partition@0 {
185 label = "xloader";
186 reg = <0x0 0x10000>;
187 };
188 partition@10000 {
189 label = "u-boot";
190 reg = <0x10000 0x50000>;
191 };
192 partition@60000 {
193 label = "environment";
194 reg = <0x60000 0x10000>;
195 };
196 partition@70000 {
197 label = "dtb";
198 reg = <0x70000 0x10000>;
199 };
200 partition@80000 {
201 label = "linux";
202 reg = <0x80000 0x310000>;
203 };
204 partition@390000 {
205 label = "rootfs";
206 reg = <0x390000 0x0>;
207 };
208 };
209 };
210
211 spi0: spi@d0100000 {
212 status = "okay";
213 };
214
215 spi1: spi@a5000000 {
216 status = "okay";
217 };
218
219 spi2: spi@a6000000 {
220 status = "okay";
221 };
222
223 usbd@e1100000 {
224 status = "okay";
225 };
226
227 apb {
228 gpio0: gpio@fc980000 {
229 status = "okay";
230 };
231
232 gpio@b3000000 {
233 status = "okay";
234 };
235
236 i2c0: i2c@d0180000 {
237 status = "okay";
238
239 stmpe811@41 {
240 compatible = "st,stmpe811";
241 #address-cells = <1>;
242 #size-cells = <0>;
243 reg = <0x41>;
244 irq-over-gpio;
245 irq-gpios = <&gpiopinctrl 29 0x4>;
246 id = <0>;
247 blocks = <0x5>;
248 irq-trigger = <0x1>;
249
250 stmpegpio: stmpe-gpio {
251 compatible = "stmpe,gpio";
252 reg = <0>;
253 gpio-controller;
254 #gpio-cells = <2>;
255 gpio,norequest-mask = <0xF3>;
256 };
257
258 stmpe610-ts {
259 compatible = "stmpe,ts";
260 reg = <0>;
261 ts,sample-time = <4>;
262 ts,mod-12b = <1>;
263 ts,ref-sel = <0>;
264 ts,adc-freq = <1>;
265 ts,ave-ctrl = <1>;
266 ts,touch-det-delay = <3>;
267 ts,settling = <4>;
268 ts,fraction-z = <7>;
269 ts,i-drive = <1>;
270 };
271 };
272 };
273
274 i2c1: i2c@a7000000 {
275 status = "okay";
276 };
277
278 rtc@fc900000 {
279 status = "okay";
280 };
281
282 serial@d0000000 {
283 status = "okay";
284 pinctrl-names = "default";
285 pinctrl-0 = <>;
286 };
287
288 serial@a3000000 {
289 status = "okay";
290 pinctrl-names = "default";
291 pinctrl-0 = <>;
292 };
293
294 serial@a4000000 {
295 status = "okay";
296 pinctrl-names = "default";
297 pinctrl-0 = <>;
298 };
299
300 wdt@fc880000 {
301 status = "okay";
302 };
303 };
304 };
305};
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
index 1f49d69595a0..caa5520b1fd4 100644
--- a/arch/arm/boot/dts/spear320.dtsi
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -21,15 +21,17 @@
21 ranges = <0x40000000 0x40000000 0x80000000 21 ranges = <0x40000000 0x40000000 0x80000000
22 0xd0000000 0xd0000000 0x30000000>; 22 0xd0000000 0xd0000000 0x30000000>;
23 23
24 pinmux@b3000000 { 24 pinmux: pinmux@b3000000 {
25 compatible = "st,spear320-pinmux"; 25 compatible = "st,spear320-pinmux";
26 reg = <0xb3000000 0x1000>; 26 reg = <0xb3000000 0x1000>;
27 #gpio-range-cells = <2>;
27 }; 28 };
28 29
29 clcd@90000000 { 30 clcd@90000000 {
30 compatible = "arm,clcd-pl110", "arm,primecell"; 31 compatible = "arm,pl110", "arm,primecell";
31 reg = <0x90000000 0x1000>; 32 reg = <0x90000000 0x1000>;
32 interrupts = <33>; 33 interrupts = <8>;
34 interrupt-parent = <&shirq>;
33 status = "disabled"; 35 status = "disabled";
34 }; 36 };
35 37
@@ -38,37 +40,61 @@
38 #address-cells = <1>; 40 #address-cells = <1>;
39 #size-cells = <1>; 41 #size-cells = <1>;
40 reg = <0x4c000000 0x1000 /* FSMC Register */ 42 reg = <0x4c000000 0x1000 /* FSMC Register */
41 0x50000000 0x0010>; /* NAND Base */ 43 0x50000000 0x0010 /* NAND Base DATA */
42 reg-names = "fsmc_regs", "nand_data"; 44 0x50020000 0x0010 /* NAND Base ADDR */
43 st,ale-off = <0x20000>; 45 0x50010000 0x0010>; /* NAND Base CMD */
44 st,cle-off = <0x10000>; 46 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
45 status = "disabled"; 47 status = "disabled";
46 }; 48 };
47 49
48 sdhci@70000000 { 50 sdhci@70000000 {
49 compatible = "st,sdhci-spear"; 51 compatible = "st,sdhci-spear";
50 reg = <0x70000000 0x100>; 52 reg = <0x70000000 0x100>;
51 interrupts = <29>; 53 interrupts = <10>;
54 interrupt-parent = <&shirq>;
52 status = "disabled"; 55 status = "disabled";
53 }; 56 };
54 57
58 shirq: interrupt-controller@0xb3000000 {
59 compatible = "st,spear320-shirq";
60 reg = <0xb3000000 0x1000>;
61 interrupts = <30 28 29 1>;
62 #interrupt-cells = <1>;
63 interrupt-controller;
64 };
65
55 spi1: spi@a5000000 { 66 spi1: spi@a5000000 {
56 compatible = "arm,pl022", "arm,primecell"; 67 compatible = "arm,pl022", "arm,primecell";
57 reg = <0xa5000000 0x1000>; 68 reg = <0xa5000000 0x1000>;
69 interrupts = <15>;
70 interrupt-parent = <&shirq>;
71 #address-cells = <1>;
72 #size-cells = <0>;
58 status = "disabled"; 73 status = "disabled";
59 }; 74 };
60 75
61 spi2: spi@a6000000 { 76 spi2: spi@a6000000 {
62 compatible = "arm,pl022", "arm,primecell"; 77 compatible = "arm,pl022", "arm,primecell";
63 reg = <0xa6000000 0x1000>; 78 reg = <0xa6000000 0x1000>;
79 interrupts = <16>;
80 interrupt-parent = <&shirq>;
81 #address-cells = <1>;
82 #size-cells = <0>;
64 status = "disabled"; 83 status = "disabled";
65 }; 84 };
66 85
86 pwm: pwm@a8000000 {
87 compatible ="st,spear-pwm";
88 reg = <0xa8000000 0x1000>;
89 #pwm-cells = <2>;
90 status = "disabled";
91 };
92
67 apb { 93 apb {
68 #address-cells = <1>; 94 #address-cells = <1>;
69 #size-cells = <1>; 95 #size-cells = <1>;
70 compatible = "simple-bus"; 96 compatible = "simple-bus";
71 ranges = <0xa0000000 0xa0000000 0x10000000 97 ranges = <0xa0000000 0xa0000000 0x20000000
72 0xd0000000 0xd0000000 0x30000000>; 98 0xd0000000 0xd0000000 0x30000000>;
73 99
74 i2c1: i2c@a7000000 { 100 i2c1: i2c@a7000000 {
@@ -76,20 +102,46 @@
76 #size-cells = <0>; 102 #size-cells = <0>;
77 compatible = "snps,designware-i2c"; 103 compatible = "snps,designware-i2c";
78 reg = <0xa7000000 0x1000>; 104 reg = <0xa7000000 0x1000>;
105 interrupts = <21>;
106 interrupt-parent = <&shirq>;
79 status = "disabled"; 107 status = "disabled";
80 }; 108 };
81 109
82 serial@a3000000 { 110 serial@a3000000 {
83 compatible = "arm,pl011", "arm,primecell"; 111 compatible = "arm,pl011", "arm,primecell";
84 reg = <0xa3000000 0x1000>; 112 reg = <0xa3000000 0x1000>;
113 interrupts = <13>;
114 interrupt-parent = <&shirq>;
85 status = "disabled"; 115 status = "disabled";
86 }; 116 };
87 117
88 serial@a4000000 { 118 serial@a4000000 {
89 compatible = "arm,pl011", "arm,primecell"; 119 compatible = "arm,pl011", "arm,primecell";
90 reg = <0xa4000000 0x1000>; 120 reg = <0xa4000000 0x1000>;
121 interrupts = <14>;
122 interrupt-parent = <&shirq>;
91 status = "disabled"; 123 status = "disabled";
92 }; 124 };
125
126 gpiopinctrl: gpio@b3000000 {
127 compatible = "st,spear-plgpio";
128 reg = <0xb3000000 0x1000>;
129 #interrupt-cells = <1>;
130 interrupt-controller;
131 gpio-controller;
132 #gpio-cells = <2>;
133 gpio-ranges = <&pinmux 0 102>;
134 status = "disabled";
135
136 st-plgpio,ngpio = <102>;
137 st-plgpio,enb-reg = <0x24>;
138 st-plgpio,wdata-reg = <0x34>;
139 st-plgpio,dir-reg = <0x44>;
140 st-plgpio,ie-reg = <0x64>;
141 st-plgpio,rdata-reg = <0x54>;
142 st-plgpio,mis-reg = <0x84>;
143 st-plgpio,eit-reg = <0x94>;
144 };
93 }; 145 };
94 }; 146 };
95}; 147};
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
index 3a8bb5736928..c2a852d43c48 100644
--- a/arch/arm/boot/dts/spear3xx.dtsi
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -53,6 +53,7 @@
53 reg = <0xe0800000 0x8000>; 53 reg = <0xe0800000 0x8000>;
54 interrupts = <23 22>; 54 interrupts = <23 22>;
55 interrupt-names = "macirq", "eth_wake_irq"; 55 interrupt-names = "macirq", "eth_wake_irq";
56 phy-mode = "mii";
56 status = "disabled"; 57 status = "disabled";
57 }; 58 };
58 59
@@ -69,6 +70,8 @@
69 compatible = "arm,pl022", "arm,primecell"; 70 compatible = "arm,pl022", "arm,primecell";
70 reg = <0xd0100000 0x1000>; 71 reg = <0xd0100000 0x1000>;
71 interrupts = <20>; 72 interrupts = <20>;
73 #address-cells = <1>;
74 #size-cells = <0>;
72 status = "disabled"; 75 status = "disabled";
73 }; 76 };
74 77
@@ -120,7 +123,7 @@
120 }; 123 };
121 124
122 rtc@fc900000 { 125 rtc@fc900000 {
123 compatible = "st,spear-rtc"; 126 compatible = "st,spear600-rtc";
124 reg = <0xfc900000 0x1000>; 127 reg = <0xfc900000 0x1000>;
125 interrupts = <10>; 128 interrupts = <10>;
126 status = "disabled"; 129 status = "disabled";
diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
index 1119c22c9a82..d865a891776d 100644
--- a/arch/arm/boot/dts/spear600-evb.dts
+++ b/arch/arm/boot/dts/spear600-evb.dts
@@ -24,15 +24,35 @@
24 }; 24 };
25 25
26 ahb { 26 ahb {
27 clcd@fc200000 {
28 status = "okay";
29 };
30
27 dma@fc400000 { 31 dma@fc400000 {
28 status = "okay"; 32 status = "okay";
29 }; 33 };
30 34
35 ehci@e1800000 {
36 status = "okay";
37 };
38
39 ehci@e2000000 {
40 status = "okay";
41 };
42
31 gmac: ethernet@e0800000 { 43 gmac: ethernet@e0800000 {
32 phy-mode = "gmii"; 44 phy-mode = "gmii";
33 status = "okay"; 45 status = "okay";
34 }; 46 };
35 47
48 ohci@e1900000 {
49 status = "okay";
50 };
51
52 ohci@e2100000 {
53 status = "okay";
54 };
55
36 smi: flash@fc000000 { 56 smi: flash@fc000000 {
37 status = "okay"; 57 status = "okay";
38 clock-rate=<50000000>; 58 clock-rate=<50000000>;
@@ -49,15 +69,23 @@
49 }; 69 };
50 partition@10000 { 70 partition@10000 {
51 label = "u-boot"; 71 label = "u-boot";
52 reg = <0x10000 0x40000>; 72 reg = <0x10000 0x50000>;
53 }; 73 };
54 partition@50000 { 74 partition@60000 {
75 label = "environment";
76 reg = <0x60000 0x10000>;
77 };
78 partition@70000 {
79 label = "dtb";
80 reg = <0x70000 0x10000>;
81 };
82 partition@80000 {
55 label = "linux"; 83 label = "linux";
56 reg = <0x50000 0x2c0000>; 84 reg = <0x80000 0x310000>;
57 }; 85 };
58 partition@310000 { 86 partition@390000 {
59 label = "rootfs"; 87 label = "rootfs";
60 reg = <0x310000 0x4f0000>; 88 reg = <0x390000 0x0>;
61 }; 89 };
62 }; 90 };
63 }; 91 };
@@ -65,10 +93,18 @@
65 apb { 93 apb {
66 serial@d0000000 { 94 serial@d0000000 {
67 status = "okay"; 95 status = "okay";
96 pinctrl-names = "default";
97 pinctrl-0 = <>;
68 }; 98 };
69 99
70 serial@d0080000 { 100 serial@d0080000 {
71 status = "okay"; 101 status = "okay";
102 pinctrl-names = "default";
103 pinctrl-0 = <>;
104 };
105
106 rtc@fc900000 {
107 status = "okay";
72 }; 108 };
73 109
74 i2c@d0200000 { 110 i2c@d0200000 {
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index a3c36e47d7ef..19f99dc4115e 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -45,6 +45,14 @@
45 #interrupt-cells = <1>; 45 #interrupt-cells = <1>;
46 }; 46 };
47 47
48 clcd@fc200000 {
49 compatible = "arm,pl110", "arm,primecell";
50 reg = <0xfc200000 0x1000>;
51 interrupt-parent = <&vic1>;
52 interrupts = <12>;
53 status = "disabled";
54 };
55
48 dma@fc400000 { 56 dma@fc400000 {
49 compatible = "arm,pl080", "arm,primecell"; 57 compatible = "arm,pl080", "arm,primecell";
50 reg = <0xfc400000 0x1000>; 58 reg = <0xfc400000 0x1000>;
@@ -59,6 +67,7 @@
59 interrupt-parent = <&vic1>; 67 interrupt-parent = <&vic1>;
60 interrupts = <24 23>; 68 interrupts = <24 23>;
61 interrupt-names = "macirq", "eth_wake_irq"; 69 interrupt-names = "macirq", "eth_wake_irq";
70 phy-mode = "gmii";
62 status = "disabled"; 71 status = "disabled";
63 }; 72 };
64 73
@@ -67,10 +76,10 @@
67 #address-cells = <1>; 76 #address-cells = <1>;
68 #size-cells = <1>; 77 #size-cells = <1>;
69 reg = <0xd1800000 0x1000 /* FSMC Register */ 78 reg = <0xd1800000 0x1000 /* FSMC Register */
70 0xd2000000 0x4000>; /* NAND Base */ 79 0xd2000000 0x0010 /* NAND Base DATA */
71 reg-names = "fsmc_regs", "nand_data"; 80 0xd2020000 0x0010 /* NAND Base ADDR */
72 st,ale-off = <0x20000>; 81 0xd2010000 0x0010>; /* NAND Base CMD */
73 st,cle-off = <0x10000>; 82 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
74 status = "disabled"; 83 status = "disabled";
75 }; 84 };
76 85
@@ -178,6 +187,13 @@
178 status = "disabled"; 187 status = "disabled";
179 }; 188 };
180 189
190 rtc@fc900000 {
191 compatible = "st,spear600-rtc";
192 reg = <0xfc900000 0x1000>;
193 interrupts = <10>;
194 status = "disabled";
195 };
196
181 timer@f0000000 { 197 timer@f0000000 {
182 compatible = "st,spear-timer"; 198 compatible = "st,spear-timer";
183 reg = <0xf0000000 0x400>; 199 reg = <0xf0000000 0x400>;
diff --git a/arch/arm/boot/dts/stuib.dtsi b/arch/arm/boot/dts/stuib.dtsi
new file mode 100644
index 000000000000..39446a247e79
--- /dev/null
+++ b/arch/arm/boot/dts/stuib.dtsi
@@ -0,0 +1,78 @@
1/*
2 * Copyright 2012 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/ {
13 soc-u9500 {
14 i2c@80004000 {
15 stmpe1601: stmpe1601@40 {
16 compatible = "st,stmpe1601";
17 reg = <0x40>;
18 interrupts = <26 0x1>;
19 interrupt-parent = <&gpio6>;
20 interrupt-controller;
21
22 wakeup-source;
23 st,autosleep-timeout = <1024>;
24
25 stmpe_keypad {
26 compatible = "st,stmpe-keypad";
27
28 debounce-interval = <64>;
29 st,scan-count = <8>;
30 st,no-autorepeat;
31
32 linux,keymap = <0x205006b
33 0x4010074
34 0x3050072
35 0x1030004
36 0x502006a
37 0x500000a
38 0x5008b
39 0x706001c
40 0x405000b
41 0x6070003
42 0x3040067
43 0x303006c
44 0x60400e7
45 0x602009e
46 0x4020073
47 0x5050002
48 0x4030069
49 0x3020008>;
50 };
51 };
52 };
53
54 i2c@80110000 {
55 bu21013_tp@0x5c {
56 compatible = "rhom,bu21013_tp";
57 reg = <0x5c>;
58 touch-gpio = <&gpio2 20 0x4>;
59 avdd-supply = <&ab8500_ldo_aux1_reg>;
60
61 rhom,touch-max-x = <384>;
62 rhom,touch-max-y = <704>;
63 rhom,flip-y;
64 };
65
66 bu21013_tp@0x5d {
67 compatible = "rhom,bu21013_tp";
68 reg = <0x5d>;
69 touch-gpio = <&gpio2 20 0x4>;
70 avdd-supply = <&ab8500_ldo_aux1_reg>;
71
72 rhom,touch-max-x = <384>;
73 rhom,touch-max-y = <704>;
74 rhom,flip-y;
75 };
76 };
77 };
78};
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
new file mode 100644
index 000000000000..5cab82540437
--- /dev/null
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -0,0 +1,38 @@
1/*
2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "sun4i-a10.dtsi"
15
16/ {
17 model = "Cubietech Cubieboard";
18 compatible = "cubietech,a10-cubieboard", "allwinner,sun4i-a10";
19
20 aliases {
21 serial0 = &uart0;
22 serial1 = &uart1;
23 };
24
25 chosen {
26 bootargs = "earlyprintk console=ttyS0,115200";
27 };
28
29 soc {
30 uart0: uart@01c28000 {
31 status = "okay";
32 };
33
34 uart1: uart@01c28400 {
35 status = "okay";
36 };
37 };
38};
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
new file mode 100644
index 000000000000..e61fdd47bd01
--- /dev/null
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -0,0 +1,19 @@
1/*
2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "sunxi.dtsi"
14
15/ {
16 memory {
17 reg = <0x40000000 0x80000000>;
18 };
19};
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
new file mode 100644
index 000000000000..498a091a4ea2
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -0,0 +1,30 @@
1/*
2 * Copyright 2012 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "sun5i-a13.dtsi"
16
17/ {
18 model = "Olimex A13-Olinuxino";
19 compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13";
20
21 chosen {
22 bootargs = "earlyprintk console=ttyS0,115200";
23 };
24
25 soc {
26 uart1: uart@01c28400 {
27 status = "okay";
28 };
29 };
30};
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
new file mode 100644
index 000000000000..59a2d265a98e
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -0,0 +1,20 @@
1/*
2 * Copyright 2012 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "sunxi.dtsi"
15
16/ {
17 memory {
18 reg = <0x40000000 0x20000000>;
19 };
20};
diff --git a/arch/arm/boot/dts/sunxi.dtsi b/arch/arm/boot/dts/sunxi.dtsi
new file mode 100644
index 000000000000..8bbc2bfef221
--- /dev/null
+++ b/arch/arm/boot/dts/sunxi.dtsi
@@ -0,0 +1,80 @@
1/*
2 * Copyright 2012 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 interrupt-parent = <&intc>;
18
19 cpus {
20 cpu@0 {
21 compatible = "arm,cortex-a8";
22 };
23 };
24
25 clocks {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 osc: oscillator {
30 #clock-cells = <0>;
31 compatible = "fixed-clock";
32 clock-frequency = <24000000>;
33 };
34 };
35
36 soc {
37 compatible = "simple-bus";
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x01c20000 0x300000>;
41 ranges;
42
43 timer@01c20c00 {
44 compatible = "allwinner,sunxi-timer";
45 reg = <0x01c20c00 0x90>;
46 interrupts = <22>;
47 clocks = <&osc>;
48 };
49
50 wdt: watchdog@01c20c90 {
51 compatible = "allwinner,sunxi-wdt";
52 reg = <0x01c20c90 0x10>;
53 };
54
55 intc: interrupt-controller@01c20400 {
56 compatible = "allwinner,sunxi-ic";
57 reg = <0x01c20400 0x400>;
58 interrupt-controller;
59 #interrupt-cells = <1>;
60 };
61
62 uart0: uart@01c28000 {
63 compatible = "ns8250";
64 reg = <0x01c28000 0x400>;
65 interrupts = <1>;
66 reg-shift = <2>;
67 clock-frequency = <24000000>;
68 status = "disabled";
69 };
70
71 uart1: uart@01c28400 {
72 compatible = "ns8250";
73 reg = <0x01c28400 0x400>;
74 interrupts = <2>;
75 reg-shift = <2>;
76 clock-frequency = <24000000>;
77 status = "disabled";
78 };
79 };
80};
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index c3ef1ad26b6a..43eb72af8948 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -10,6 +10,18 @@
10 reg = <0x00000000 0x40000000>; 10 reg = <0x00000000 0x40000000>;
11 }; 11 };
12 12
13 host1x {
14 hdmi {
15 status = "okay";
16
17 vdd-supply = <&hdmi_vdd_reg>;
18 pll-supply = <&hdmi_pll_reg>;
19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
22 };
23 };
24
13 pinmux { 25 pinmux {
14 pinctrl-names = "default"; 26 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>; 27 pinctrl-0 = <&state_default>;
@@ -262,9 +274,9 @@
262 }; 274 };
263 }; 275 };
264 276
265 i2c@7000c400 { 277 hdmi_ddc: i2c@7000c400 {
266 status = "okay"; 278 status = "okay";
267 clock-frequency = <400000>; 279 clock-frequency = <100000>;
268 }; 280 };
269 281
270 i2c@7000c500 { 282 i2c@7000c500 {
@@ -297,131 +309,98 @@
297 vinldo9-supply = <&sm2_reg>; 309 vinldo9-supply = <&sm2_reg>;
298 310
299 regulators { 311 regulators {
300 #address-cells = <1>; 312 sys_reg: sys {
301 #size-cells = <0>;
302
303 sys_reg: regulator@0 {
304 reg = <0>;
305 regulator-compatible = "sys";
306 regulator-name = "vdd_sys"; 313 regulator-name = "vdd_sys";
307 regulator-always-on; 314 regulator-always-on;
308 }; 315 };
309 316
310 regulator@1 { 317 sm0 {
311 reg = <1>;
312 regulator-compatible = "sm0";
313 regulator-name = "vdd_sm0,vdd_core"; 318 regulator-name = "vdd_sm0,vdd_core";
314 regulator-min-microvolt = <1200000>; 319 regulator-min-microvolt = <1200000>;
315 regulator-max-microvolt = <1200000>; 320 regulator-max-microvolt = <1200000>;
316 regulator-always-on; 321 regulator-always-on;
317 }; 322 };
318 323
319 regulator@2 { 324 sm1 {
320 reg = <2>;
321 regulator-compatible = "sm1";
322 regulator-name = "vdd_sm1,vdd_cpu"; 325 regulator-name = "vdd_sm1,vdd_cpu";
323 regulator-min-microvolt = <1000000>; 326 regulator-min-microvolt = <1000000>;
324 regulator-max-microvolt = <1000000>; 327 regulator-max-microvolt = <1000000>;
325 regulator-always-on; 328 regulator-always-on;
326 }; 329 };
327 330
328 sm2_reg: regulator@3 { 331 sm2_reg: sm2 {
329 reg = <3>;
330 regulator-compatible = "sm2";
331 regulator-name = "vdd_sm2,vin_ldo*"; 332 regulator-name = "vdd_sm2,vin_ldo*";
332 regulator-min-microvolt = <3700000>; 333 regulator-min-microvolt = <3700000>;
333 regulator-max-microvolt = <3700000>; 334 regulator-max-microvolt = <3700000>;
334 regulator-always-on; 335 regulator-always-on;
335 }; 336 };
336 337
337 regulator@4 { 338 ldo0 {
338 reg = <4>;
339 regulator-compatible = "ldo0";
340 regulator-name = "vdd_ldo0,vddio_pex_clk"; 339 regulator-name = "vdd_ldo0,vddio_pex_clk";
341 regulator-min-microvolt = <3300000>; 340 regulator-min-microvolt = <3300000>;
342 regulator-max-microvolt = <3300000>; 341 regulator-max-microvolt = <3300000>;
343 }; 342 };
344 343
345 regulator@5 { 344 ldo1 {
346 reg = <5>;
347 regulator-compatible = "ldo1";
348 regulator-name = "vdd_ldo1,avdd_pll*"; 345 regulator-name = "vdd_ldo1,avdd_pll*";
349 regulator-min-microvolt = <1100000>; 346 regulator-min-microvolt = <1100000>;
350 regulator-max-microvolt = <1100000>; 347 regulator-max-microvolt = <1100000>;
351 regulator-always-on; 348 regulator-always-on;
352 }; 349 };
353 350
354 regulator@6 { 351 ldo2 {
355 reg = <6>;
356 regulator-compatible = "ldo2";
357 regulator-name = "vdd_ldo2,vdd_rtc"; 352 regulator-name = "vdd_ldo2,vdd_rtc";
358 regulator-min-microvolt = <1200000>; 353 regulator-min-microvolt = <1200000>;
359 regulator-max-microvolt = <1200000>; 354 regulator-max-microvolt = <1200000>;
360 }; 355 };
361 356
362 regulator@7 { 357 ldo3 {
363 reg = <7>;
364 regulator-compatible = "ldo3";
365 regulator-name = "vdd_ldo3,avdd_usb*"; 358 regulator-name = "vdd_ldo3,avdd_usb*";
366 regulator-min-microvolt = <3300000>; 359 regulator-min-microvolt = <3300000>;
367 regulator-max-microvolt = <3300000>; 360 regulator-max-microvolt = <3300000>;
368 regulator-always-on; 361 regulator-always-on;
369 }; 362 };
370 363
371 regulator@8 { 364 ldo4 {
372 reg = <8>;
373 regulator-compatible = "ldo4";
374 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; 365 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
375 regulator-min-microvolt = <1800000>; 366 regulator-min-microvolt = <1800000>;
376 regulator-max-microvolt = <1800000>; 367 regulator-max-microvolt = <1800000>;
377 regulator-always-on; 368 regulator-always-on;
378 }; 369 };
379 370
380 regulator@9 { 371 ldo5 {
381 reg = <9>;
382 regulator-compatible = "ldo5";
383 regulator-name = "vdd_ldo5,vcore_mmc"; 372 regulator-name = "vdd_ldo5,vcore_mmc";
384 regulator-min-microvolt = <2850000>; 373 regulator-min-microvolt = <2850000>;
385 regulator-max-microvolt = <2850000>; 374 regulator-max-microvolt = <2850000>;
386 regulator-always-on; 375 regulator-always-on;
387 }; 376 };
388 377
389 regulator@10 { 378 ldo6 {
390 reg = <10>;
391 regulator-compatible = "ldo6";
392 regulator-name = "vdd_ldo6,avdd_vdac"; 379 regulator-name = "vdd_ldo6,avdd_vdac";
393 regulator-min-microvolt = <1800000>; 380 regulator-min-microvolt = <1800000>;
394 regulator-max-microvolt = <1800000>; 381 regulator-max-microvolt = <1800000>;
395 }; 382 };
396 383
397 regulator@11 { 384 hdmi_vdd_reg: ldo7 {
398 reg = <11>;
399 regulator-compatible = "ldo7";
400 regulator-name = "vdd_ldo7,avdd_hdmi"; 385 regulator-name = "vdd_ldo7,avdd_hdmi";
401 regulator-min-microvolt = <3300000>; 386 regulator-min-microvolt = <3300000>;
402 regulator-max-microvolt = <3300000>; 387 regulator-max-microvolt = <3300000>;
403 }; 388 };
404 389
405 regulator@12 { 390 hdmi_pll_reg: ldo8 {
406 reg = <12>;
407 regulator-compatible = "ldo8";
408 regulator-name = "vdd_ldo8,avdd_hdmi_pll"; 391 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
409 regulator-min-microvolt = <1800000>; 392 regulator-min-microvolt = <1800000>;
410 regulator-max-microvolt = <1800000>; 393 regulator-max-microvolt = <1800000>;
411 }; 394 };
412 395
413 regulator@13 { 396 ldo9 {
414 reg = <13>;
415 regulator-compatible = "ldo9";
416 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; 397 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
417 regulator-min-microvolt = <2850000>; 398 regulator-min-microvolt = <2850000>;
418 regulator-max-microvolt = <2850000>; 399 regulator-max-microvolt = <2850000>;
419 regulator-always-on; 400 regulator-always-on;
420 }; 401 };
421 402
422 regulator@14 { 403 ldo_rtc {
423 reg = <14>;
424 regulator-compatible = "ldo_rtc";
425 regulator-name = "vdd_rtc_out,vdd_cell"; 404 regulator-name = "vdd_rtc_out,vdd_cell";
426 regulator-min-microvolt = <3300000>; 405 regulator-min-microvolt = <3300000>;
427 regulator-max-microvolt = <3300000>; 406 regulator-max-microvolt = <3300000>;
@@ -429,6 +408,11 @@
429 }; 408 };
430 }; 409 };
431 }; 410 };
411
412 temperature-sensor@4c {
413 compatible = "adi,adt7461";
414 reg = <0x4c>;
415 };
432 }; 416 };
433 417
434 pmc { 418 pmc {
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index ddf287f52d49..6a93d1404c76 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -291,37 +291,26 @@
291 vinldo9-supply = <&sm2_reg>; 291 vinldo9-supply = <&sm2_reg>;
292 292
293 regulators { 293 regulators {
294 #address-cells = <1>; 294 sys_reg: sys {
295 #size-cells = <0>;
296
297 sys_reg: regulator@0 {
298 reg = <0>;
299 regulator-compatible = "sys";
300 regulator-name = "vdd_sys"; 295 regulator-name = "vdd_sys";
301 regulator-always-on; 296 regulator-always-on;
302 }; 297 };
303 298
304 regulator@1 { 299 sm0 {
305 reg = <1>;
306 regulator-compatible = "sm0";
307 regulator-name = "+1.2vs_sm0,vdd_core"; 300 regulator-name = "+1.2vs_sm0,vdd_core";
308 regulator-min-microvolt = <1200000>; 301 regulator-min-microvolt = <1200000>;
309 regulator-max-microvolt = <1200000>; 302 regulator-max-microvolt = <1200000>;
310 regulator-always-on; 303 regulator-always-on;
311 }; 304 };
312 305
313 regulator@2 { 306 sm1 {
314 reg = <2>;
315 regulator-compatible = "sm1";
316 regulator-name = "+1.0vs_sm1,vdd_cpu"; 307 regulator-name = "+1.0vs_sm1,vdd_cpu";
317 regulator-min-microvolt = <1000000>; 308 regulator-min-microvolt = <1000000>;
318 regulator-max-microvolt = <1000000>; 309 regulator-max-microvolt = <1000000>;
319 regulator-always-on; 310 regulator-always-on;
320 }; 311 };
321 312
322 sm2_reg: regulator@3 { 313 sm2_reg: sm2 {
323 reg = <3>;
324 regulator-compatible = "sm2";
325 regulator-name = "+3.7vs_sm2,vin_ldo*"; 314 regulator-name = "+3.7vs_sm2,vin_ldo*";
326 regulator-min-microvolt = <3700000>; 315 regulator-min-microvolt = <3700000>;
327 regulator-max-microvolt = <3700000>; 316 regulator-max-microvolt = <3700000>;
@@ -330,53 +319,41 @@
330 319
331 /* LDO0 is not connected to anything */ 320 /* LDO0 is not connected to anything */
332 321
333 regulator@5 { 322 ldo1 {
334 reg = <5>;
335 regulator-compatible = "ldo1";
336 regulator-name = "+1.1vs_ldo1,avdd_pll*"; 323 regulator-name = "+1.1vs_ldo1,avdd_pll*";
337 regulator-min-microvolt = <1100000>; 324 regulator-min-microvolt = <1100000>;
338 regulator-max-microvolt = <1100000>; 325 regulator-max-microvolt = <1100000>;
339 regulator-always-on; 326 regulator-always-on;
340 }; 327 };
341 328
342 regulator@6 { 329 ldo2 {
343 reg = <6>;
344 regulator-compatible = "ldo2";
345 regulator-name = "+1.2vs_ldo2,vdd_rtc"; 330 regulator-name = "+1.2vs_ldo2,vdd_rtc";
346 regulator-min-microvolt = <1200000>; 331 regulator-min-microvolt = <1200000>;
347 regulator-max-microvolt = <1200000>; 332 regulator-max-microvolt = <1200000>;
348 }; 333 };
349 334
350 regulator@7 { 335 ldo3 {
351 reg = <7>;
352 regulator-compatible = "ldo3";
353 regulator-name = "+3.3vs_ldo3,avdd_usb*"; 336 regulator-name = "+3.3vs_ldo3,avdd_usb*";
354 regulator-min-microvolt = <3300000>; 337 regulator-min-microvolt = <3300000>;
355 regulator-max-microvolt = <3300000>; 338 regulator-max-microvolt = <3300000>;
356 regulator-always-on; 339 regulator-always-on;
357 }; 340 };
358 341
359 regulator@8 { 342 ldo4 {
360 reg = <8>;
361 regulator-compatible = "ldo4";
362 regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys"; 343 regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
363 regulator-min-microvolt = <1800000>; 344 regulator-min-microvolt = <1800000>;
364 regulator-max-microvolt = <1800000>; 345 regulator-max-microvolt = <1800000>;
365 regulator-always-on; 346 regulator-always-on;
366 }; 347 };
367 348
368 regulator@9 { 349 ldo5 {
369 reg = <9>;
370 regulator-compatible = "ldo5";
371 regulator-name = "+2.85vs_ldo5,vcore_mmc"; 350 regulator-name = "+2.85vs_ldo5,vcore_mmc";
372 regulator-min-microvolt = <2850000>; 351 regulator-min-microvolt = <2850000>;
373 regulator-max-microvolt = <2850000>; 352 regulator-max-microvolt = <2850000>;
374 regulator-always-on; 353 regulator-always-on;
375 }; 354 };
376 355
377 regulator@10 { 356 ldo6 {
378 reg = <10>;
379 regulator-compatible = "ldo6";
380 /* 357 /*
381 * Research indicates this should be 358 * Research indicates this should be
382 * 1.8v; other boards that use this 359 * 1.8v; other boards that use this
@@ -390,34 +367,26 @@
390 regulator-max-microvolt = <1800000>; 367 regulator-max-microvolt = <1800000>;
391 }; 368 };
392 369
393 regulator@11 { 370 ldo7 {
394 reg = <11>;
395 regulator-compatible = "ldo7";
396 regulator-name = "+3.3vs_ldo7,avdd_hdmi"; 371 regulator-name = "+3.3vs_ldo7,avdd_hdmi";
397 regulator-min-microvolt = <3300000>; 372 regulator-min-microvolt = <3300000>;
398 regulator-max-microvolt = <3300000>; 373 regulator-max-microvolt = <3300000>;
399 }; 374 };
400 375
401 regulator@12 { 376 ldo8 {
402 reg = <12>;
403 regulator-compatible = "ldo8";
404 regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll"; 377 regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
405 regulator-min-microvolt = <1800000>; 378 regulator-min-microvolt = <1800000>;
406 regulator-max-microvolt = <1800000>; 379 regulator-max-microvolt = <1800000>;
407 }; 380 };
408 381
409 regulator@13 { 382 ldo9 {
410 reg = <13>;
411 regulator-compatible = "ldo9";
412 regulator-name = "+2.85vs_ldo9,vdd_ddr_rx"; 383 regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
413 regulator-min-microvolt = <2850000>; 384 regulator-min-microvolt = <2850000>;
414 regulator-max-microvolt = <2850000>; 385 regulator-max-microvolt = <2850000>;
415 regulator-always-on; 386 regulator-always-on;
416 }; 387 };
417 388
418 regulator@14 { 389 ldo_rtc {
419 reg = <14>;
420 regulator-compatible = "ldo_rtc";
421 regulator-name = "+3.3vs_rtc"; 390 regulator-name = "+3.3vs_rtc";
422 regulator-min-microvolt = <3300000>; 391 regulator-min-microvolt = <3300000>;
423 regulator-max-microvolt = <3300000>; 392 regulator-max-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
index 331a3ef24d59..289480026fbf 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -6,6 +6,12 @@
6 model = "Avionic Design Plutux board"; 6 model = "Avionic Design Plutux board";
7 compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20"; 7 compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20";
8 8
9 host1x {
10 hdmi {
11 status = "okay";
12 };
13 };
14
9 i2c@7000c000 { 15 i2c@7000c000 {
10 wm8903: wm8903@1a { 16 wm8903: wm8903@1a {
11 compatible = "wlf,wm8903"; 17 compatible = "wlf,wm8903";
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index f0ba901676ac..420459825b46 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -395,37 +395,26 @@
395 vinldo9-supply = <&sm2_reg>; 395 vinldo9-supply = <&sm2_reg>;
396 396
397 regulators { 397 regulators {
398 #address-cells = <1>; 398 sys_reg: sys {
399 #size-cells = <0>;
400
401 sys_reg: regulator@0 {
402 reg = <0>;
403 regulator-compatible = "sys";
404 regulator-name = "vdd_sys"; 399 regulator-name = "vdd_sys";
405 regulator-always-on; 400 regulator-always-on;
406 }; 401 };
407 402
408 regulator@1 { 403 sm0 {
409 reg = <1>;
410 regulator-compatible = "sm0";
411 regulator-name = "vdd_sm0,vdd_core"; 404 regulator-name = "vdd_sm0,vdd_core";
412 regulator-min-microvolt = <1300000>; 405 regulator-min-microvolt = <1300000>;
413 regulator-max-microvolt = <1300000>; 406 regulator-max-microvolt = <1300000>;
414 regulator-always-on; 407 regulator-always-on;
415 }; 408 };
416 409
417 regulator@2 { 410 sm1 {
418 reg = <2>;
419 regulator-compatible = "sm1";
420 regulator-name = "vdd_sm1,vdd_cpu"; 411 regulator-name = "vdd_sm1,vdd_cpu";
421 regulator-min-microvolt = <1125000>; 412 regulator-min-microvolt = <1125000>;
422 regulator-max-microvolt = <1125000>; 413 regulator-max-microvolt = <1125000>;
423 regulator-always-on; 414 regulator-always-on;
424 }; 415 };
425 416
426 sm2_reg: regulator@3 { 417 sm2_reg: sm2 {
427 reg = <3>;
428 regulator-compatible = "sm2";
429 regulator-name = "vdd_sm2,vin_ldo*"; 418 regulator-name = "vdd_sm2,vin_ldo*";
430 regulator-min-microvolt = <3700000>; 419 regulator-min-microvolt = <3700000>;
431 regulator-max-microvolt = <3700000>; 420 regulator-max-microvolt = <3700000>;
@@ -434,86 +423,66 @@
434 423
435 /* LDO0 is not connected to anything */ 424 /* LDO0 is not connected to anything */
436 425
437 regulator@5 { 426 ldo1 {
438 reg = <5>;
439 regulator-compatible = "ldo1";
440 regulator-name = "vdd_ldo1,avdd_pll*"; 427 regulator-name = "vdd_ldo1,avdd_pll*";
441 regulator-min-microvolt = <1100000>; 428 regulator-min-microvolt = <1100000>;
442 regulator-max-microvolt = <1100000>; 429 regulator-max-microvolt = <1100000>;
443 regulator-always-on; 430 regulator-always-on;
444 }; 431 };
445 432
446 regulator@6 { 433 ldo2 {
447 reg = <6>;
448 regulator-compatible = "ldo2";
449 regulator-name = "vdd_ldo2,vdd_rtc"; 434 regulator-name = "vdd_ldo2,vdd_rtc";
450 regulator-min-microvolt = <1200000>; 435 regulator-min-microvolt = <1200000>;
451 regulator-max-microvolt = <1200000>; 436 regulator-max-microvolt = <1200000>;
452 }; 437 };
453 438
454 regulator@7 { 439 ldo3 {
455 reg = <7>;
456 regulator-compatible = "ldo3";
457 regulator-name = "vdd_ldo3,avdd_usb*"; 440 regulator-name = "vdd_ldo3,avdd_usb*";
458 regulator-min-microvolt = <3300000>; 441 regulator-min-microvolt = <3300000>;
459 regulator-max-microvolt = <3300000>; 442 regulator-max-microvolt = <3300000>;
460 regulator-always-on; 443 regulator-always-on;
461 }; 444 };
462 445
463 regulator@8 { 446 ldo4 {
464 reg = <8>;
465 regulator-compatible = "ldo4";
466 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; 447 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
467 regulator-min-microvolt = <1800000>; 448 regulator-min-microvolt = <1800000>;
468 regulator-max-microvolt = <1800000>; 449 regulator-max-microvolt = <1800000>;
469 regulator-always-on; 450 regulator-always-on;
470 }; 451 };
471 452
472 regulator@9 { 453 ldo5 {
473 reg = <9>;
474 regulator-compatible = "ldo5";
475 regulator-name = "vdd_ldo5,vcore_mmc"; 454 regulator-name = "vdd_ldo5,vcore_mmc";
476 regulator-min-microvolt = <2850000>; 455 regulator-min-microvolt = <2850000>;
477 regulator-max-microvolt = <2850000>; 456 regulator-max-microvolt = <2850000>;
478 regulator-always-on; 457 regulator-always-on;
479 }; 458 };
480 459
481 regulator@10 { 460 ldo6 {
482 reg = <10>;
483 regulator-compatible = "ldo6";
484 regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; 461 regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
485 regulator-min-microvolt = <1800000>; 462 regulator-min-microvolt = <1800000>;
486 regulator-max-microvolt = <1800000>; 463 regulator-max-microvolt = <1800000>;
487 }; 464 };
488 465
489 regulator@11 { 466 ldo7 {
490 reg = <11>;
491 regulator-compatible = "ldo7";
492 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; 467 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
493 regulator-min-microvolt = <3300000>; 468 regulator-min-microvolt = <3300000>;
494 regulator-max-microvolt = <3300000>; 469 regulator-max-microvolt = <3300000>;
495 }; 470 };
496 471
497 regulator@12 { 472 ldo8 {
498 reg = <12>;
499 regulator-compatible = "ldo8";
500 regulator-name = "vdd_ldo8,avdd_hdmi_pll"; 473 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
501 regulator-min-microvolt = <1800000>; 474 regulator-min-microvolt = <1800000>;
502 regulator-max-microvolt = <1800000>; 475 regulator-max-microvolt = <1800000>;
503 }; 476 };
504 477
505 regulator@13 { 478 ldo9 {
506 reg = <13>;
507 regulator-compatible = "ldo9";
508 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; 479 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
509 regulator-min-microvolt = <2850000>; 480 regulator-min-microvolt = <2850000>;
510 regulator-max-microvolt = <2850000>; 481 regulator-max-microvolt = <2850000>;
511 regulator-always-on; 482 regulator-always-on;
512 }; 483 };
513 484
514 regulator@14 { 485 ldo_rtc {
515 reg = <14>;
516 regulator-compatible = "ldo_rtc";
517 regulator-name = "vdd_rtc_out,vdd_cell"; 486 regulator-name = "vdd_rtc_out,vdd_cell";
518 regulator-min-microvolt = <3300000>; 487 regulator-min-microvolt = <3300000>;
519 regulator-max-microvolt = <3300000>; 488 regulator-max-microvolt = <3300000>;
@@ -523,12 +492,12 @@
523 }; 492 };
524 493
525 temperature-sensor@4c { 494 temperature-sensor@4c {
526 compatible = "nct1008"; 495 compatible = "onnn,nct1008";
527 reg = <0x4c>; 496 reg = <0x4c>;
528 }; 497 };
529 498
530 magnetometer@c { 499 magnetometer@c {
531 compatible = "ak8975"; 500 compatible = "ak,ak8975";
532 reg = <0xc>; 501 reg = <0xc>;
533 interrupt-parent = <&gpio>; 502 interrupt-parent = <&gpio>;
534 interrupts = <109 0x04>; /* gpio PN5 */ 503 interrupts = <109 0x04>; /* gpio PN5 */
@@ -592,6 +561,12 @@
592 status = "okay"; 561 status = "okay";
593 }; 562 };
594 563
564 sdhci@c8000000 {
565 status = "okay";
566 power-gpios = <&gpio 86 0>; /* gpio PK6 */
567 bus-width = <4>;
568 };
569
595 sdhci@c8000400 { 570 sdhci@c8000400 {
596 status = "okay"; 571 status = "okay";
597 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 572 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index f18cec9f6a77..a239ccdfaa52 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -8,6 +8,16 @@
8 reg = <0x00000000 0x20000000>; 8 reg = <0x00000000 0x20000000>;
9 }; 9 };
10 10
11 host1x {
12 hdmi {
13 vdd-supply = <&hdmi_vdd_reg>;
14 pll-supply = <&hdmi_pll_reg>;
15
16 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
17 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
18 };
19 };
20
11 pinmux { 21 pinmux {
12 pinctrl-names = "default"; 22 pinctrl-names = "default";
13 pinctrl-0 = <&state_default>; 23 pinctrl-0 = <&state_default>;
@@ -62,10 +72,6 @@
62 nvidia,pins = "dap4"; 72 nvidia,pins = "dap4";
63 nvidia,function = "dap4"; 73 nvidia,function = "dap4";
64 }; 74 };
65 ddc {
66 nvidia,pins = "ddc";
67 nvidia,function = "i2c2";
68 };
69 dta { 75 dta {
70 nvidia,pins = "dta", "dtd"; 76 nvidia,pins = "dta", "dtd";
71 nvidia,function = "sdio2"; 77 nvidia,function = "sdio2";
@@ -91,7 +97,7 @@
91 nvidia,function = "pcie"; 97 nvidia,function = "pcie";
92 }; 98 };
93 hdint { 99 hdint {
94 nvidia,pins = "hdint", "pta"; 100 nvidia,pins = "hdint";
95 nvidia,function = "hdmi"; 101 nvidia,function = "hdmi";
96 }; 102 };
97 i2cp { 103 i2cp {
@@ -230,6 +236,39 @@
230 nvidia,pull = <1>; 236 nvidia,pull = <1>;
231 }; 237 };
232 }; 238 };
239
240 state_i2cmux_ddc: pinmux_i2cmux_ddc {
241 ddc {
242 nvidia,pins = "ddc";
243 nvidia,function = "i2c2";
244 };
245 pta {
246 nvidia,pins = "pta";
247 nvidia,function = "rsvd4";
248 };
249 };
250
251 state_i2cmux_pta: pinmux_i2cmux_pta {
252 ddc {
253 nvidia,pins = "ddc";
254 nvidia,function = "rsvd4";
255 };
256 pta {
257 nvidia,pins = "pta";
258 nvidia,function = "i2c2";
259 };
260 };
261
262 state_i2cmux_idle: pinmux_i2cmux_idle {
263 ddc {
264 nvidia,pins = "ddc";
265 nvidia,function = "rsvd4";
266 };
267 pta {
268 nvidia,pins = "pta";
269 nvidia,function = "rsvd4";
270 };
271 };
233 }; 272 };
234 273
235 i2s@70002800 { 274 i2s@70002800 {
@@ -246,6 +285,36 @@
246 status = "okay"; 285 status = "okay";
247 }; 286 };
248 287
288 i2c@7000c400 {
289 clock-frequency = <100000>;
290 status = "okay";
291 };
292
293 i2cmux {
294 compatible = "i2c-mux-pinctrl";
295 #address-cells = <1>;
296 #size-cells = <0>;
297
298 i2c-parent = <&{/i2c@7000c400}>;
299
300 pinctrl-names = "ddc", "pta", "idle";
301 pinctrl-0 = <&state_i2cmux_ddc>;
302 pinctrl-1 = <&state_i2cmux_pta>;
303 pinctrl-2 = <&state_i2cmux_idle>;
304
305 hdmi_ddc: i2c@0 {
306 reg = <0>;
307 #address-cells = <1>;
308 #size-cells = <0>;
309 };
310
311 i2c@1 {
312 reg = <1>;
313 #address-cells = <1>;
314 #size-cells = <0>;
315 };
316 };
317
249 i2c@7000d000 { 318 i2c@7000d000 {
250 clock-frequency = <400000>; 319 clock-frequency = <400000>;
251 status = "okay"; 320 status = "okay";
@@ -271,97 +340,72 @@
271 vinldo9-supply = <&sm2_reg>; 340 vinldo9-supply = <&sm2_reg>;
272 341
273 regulators { 342 regulators {
274 #address-cells = <1>; 343 sys_reg: sys {
275 #size-cells = <0>;
276
277 sys_reg: regulator@0 {
278 reg = <0>;
279 regulator-compatible = "sys";
280 regulator-name = "vdd_sys"; 344 regulator-name = "vdd_sys";
281 regulator-always-on; 345 regulator-always-on;
282 }; 346 };
283 347
284 regulator@1 { 348 sm0 {
285 reg = <1>;
286 regulator-compatible = "sm0";
287 regulator-name = "vdd_sys_sm0,vdd_core"; 349 regulator-name = "vdd_sys_sm0,vdd_core";
288 regulator-min-microvolt = <1200000>; 350 regulator-min-microvolt = <1200000>;
289 regulator-max-microvolt = <1200000>; 351 regulator-max-microvolt = <1200000>;
290 regulator-always-on; 352 regulator-always-on;
291 }; 353 };
292 354
293 regulator@2 { 355 sm1 {
294 reg = <2>;
295 regulator-compatible = "sm1";
296 regulator-name = "vdd_sys_sm1,vdd_cpu"; 356 regulator-name = "vdd_sys_sm1,vdd_cpu";
297 regulator-min-microvolt = <1000000>; 357 regulator-min-microvolt = <1000000>;
298 regulator-max-microvolt = <1000000>; 358 regulator-max-microvolt = <1000000>;
299 regulator-always-on; 359 regulator-always-on;
300 }; 360 };
301 361
302 sm2_reg: regulator@3 { 362 sm2_reg: sm2 {
303 reg = <3>;
304 regulator-compatible = "sm2";
305 regulator-name = "vdd_sys_sm2,vin_ldo*"; 363 regulator-name = "vdd_sys_sm2,vin_ldo*";
306 regulator-min-microvolt = <3700000>; 364 regulator-min-microvolt = <3700000>;
307 regulator-max-microvolt = <3700000>; 365 regulator-max-microvolt = <3700000>;
308 regulator-always-on; 366 regulator-always-on;
309 }; 367 };
310 368
311 regulator@4 { 369 ldo0 {
312 reg = <4>;
313 regulator-compatible = "ldo0";
314 regulator-name = "vdd_ldo0,vddio_pex_clk"; 370 regulator-name = "vdd_ldo0,vddio_pex_clk";
315 regulator-min-microvolt = <3300000>; 371 regulator-min-microvolt = <3300000>;
316 regulator-max-microvolt = <3300000>; 372 regulator-max-microvolt = <3300000>;
317 }; 373 };
318 374
319 regulator@5 { 375 ldo1 {
320 reg = <5>;
321 regulator-compatible = "ldo1";
322 regulator-name = "vdd_ldo1,avdd_pll*"; 376 regulator-name = "vdd_ldo1,avdd_pll*";
323 regulator-min-microvolt = <1100000>; 377 regulator-min-microvolt = <1100000>;
324 regulator-max-microvolt = <1100000>; 378 regulator-max-microvolt = <1100000>;
325 regulator-always-on; 379 regulator-always-on;
326 }; 380 };
327 381
328 regulator@6 { 382 ldo2 {
329 reg = <6>;
330 regulator-compatible = "ldo2";
331 regulator-name = "vdd_ldo2,vdd_rtc"; 383 regulator-name = "vdd_ldo2,vdd_rtc";
332 regulator-min-microvolt = <1200000>; 384 regulator-min-microvolt = <1200000>;
333 regulator-max-microvolt = <1200000>; 385 regulator-max-microvolt = <1200000>;
334 }; 386 };
335 387
336 regulator@7 { 388 ldo3 {
337 reg = <7>;
338 regulator-compatible = "ldo3";
339 regulator-name = "vdd_ldo3,avdd_usb*"; 389 regulator-name = "vdd_ldo3,avdd_usb*";
340 regulator-min-microvolt = <3300000>; 390 regulator-min-microvolt = <3300000>;
341 regulator-max-microvolt = <3300000>; 391 regulator-max-microvolt = <3300000>;
342 regulator-always-on; 392 regulator-always-on;
343 }; 393 };
344 394
345 regulator@8 { 395 ldo4 {
346 reg = <8>;
347 regulator-compatible = "ldo4";
348 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; 396 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
349 regulator-min-microvolt = <1800000>; 397 regulator-min-microvolt = <1800000>;
350 regulator-max-microvolt = <1800000>; 398 regulator-max-microvolt = <1800000>;
351 regulator-always-on; 399 regulator-always-on;
352 }; 400 };
353 401
354 regulator@9 { 402 ldo5 {
355 reg = <9>;
356 regulator-compatible = "ldo5";
357 regulator-name = "vdd_ldo5,vcore_mmc"; 403 regulator-name = "vdd_ldo5,vcore_mmc";
358 regulator-min-microvolt = <2850000>; 404 regulator-min-microvolt = <2850000>;
359 regulator-max-microvolt = <2850000>; 405 regulator-max-microvolt = <2850000>;
360 }; 406 };
361 407
362 regulator@10 { 408 ldo6 {
363 reg = <10>;
364 regulator-compatible = "ldo6";
365 regulator-name = "vdd_ldo6,avdd_vdac"; 409 regulator-name = "vdd_ldo6,avdd_vdac";
366 /* 410 /*
367 * According to the Tegra 2 Automotive 411 * According to the Tegra 2 Automotive
@@ -373,25 +417,19 @@
373 regulator-max-microvolt = <2850000>; 417 regulator-max-microvolt = <2850000>;
374 }; 418 };
375 419
376 regulator@11 { 420 hdmi_vdd_reg: ldo7 {
377 reg = <11>;
378 regulator-compatible = "ldo7";
379 regulator-name = "vdd_ldo7,avdd_hdmi"; 421 regulator-name = "vdd_ldo7,avdd_hdmi";
380 regulator-min-microvolt = <3300000>; 422 regulator-min-microvolt = <3300000>;
381 regulator-max-microvolt = <3300000>; 423 regulator-max-microvolt = <3300000>;
382 }; 424 };
383 425
384 regulator@12 { 426 hdmi_pll_reg: ldo8 {
385 reg = <12>;
386 regulator-compatible = "ldo8";
387 regulator-name = "vdd_ldo8,avdd_hdmi_pll"; 427 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
388 regulator-min-microvolt = <1800000>; 428 regulator-min-microvolt = <1800000>;
389 regulator-max-microvolt = <1800000>; 429 regulator-max-microvolt = <1800000>;
390 }; 430 };
391 431
392 regulator@13 { 432 ldo9 {
393 reg = <13>;
394 regulator-compatible = "ldo9";
395 regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam"; 433 regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
396 /* 434 /*
397 * According to the Tegra 2 Automotive 435 * According to the Tegra 2 Automotive
@@ -404,9 +442,7 @@
404 regulator-always-on; 442 regulator-always-on;
405 }; 443 };
406 444
407 regulator@14 { 445 ldo_rtc {
408 reg = <14>;
409 regulator-compatible = "ldo_rtc";
410 regulator-name = "vdd_rtc_out"; 446 regulator-name = "vdd_rtc_out";
411 regulator-min-microvolt = <3300000>; 447 regulator-min-microvolt = <3300000>;
412 regulator-max-microvolt = <3300000>; 448 regulator-max-microvolt = <3300000>;
@@ -414,6 +450,11 @@
414 }; 450 };
415 }; 451 };
416 }; 452 };
453
454 temperature-sensor@4c {
455 compatible = "onnn,nct1008";
456 reg = <0x4c>;
457 };
417 }; 458 };
418 459
419 pmc { 460 pmc {
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
index 9aff31b0fe4a..402b21004bef 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -6,10 +6,13 @@
6 model = "Avionic Design Tamonten Evaluation Carrier"; 6 model = "Avionic Design Tamonten Evaluation Carrier";
7 compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20"; 7 compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
8 8
9 i2c@7000c000 { 9 host1x {
10 clock-frequency = <400000>; 10 hdmi {
11 status = "okay"; 11 status = "okay";
12 };
13 };
12 14
15 i2c@7000c000 {
13 wm8903: wm8903@1a { 16 wm8903: wm8903@1a {
14 compatible = "wlf,wm8903"; 17 compatible = "wlf,wm8903";
15 reg = <0x1a>; 18 reg = <0x1a>;
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 27fb8a67ea42..b70b4cb754c8 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -10,6 +10,18 @@
10 reg = <0x00000000 0x40000000>; 10 reg = <0x00000000 0x40000000>;
11 }; 11 };
12 12
13 host1x {
14 hdmi {
15 status = "okay";
16
17 vdd-supply = <&hdmi_vdd_reg>;
18 pll-supply = <&hdmi_pll_reg>;
19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
22 };
23 };
24
13 pinmux { 25 pinmux {
14 pinctrl-names = "default"; 26 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>; 27 pinctrl-0 = <&state_default>;
@@ -249,14 +261,24 @@
249 clock-frequency = <216000000>; 261 clock-frequency = <216000000>;
250 }; 262 };
251 263
252 i2c@7000c000 { 264 dvi_ddc: i2c@7000c000 {
253 status = "okay"; 265 status = "okay";
254 clock-frequency = <400000>; 266 clock-frequency = <100000>;
255 }; 267 };
256 268
257 i2c@7000c400 { 269 spi@7000c380 {
258 status = "okay"; 270 status = "okay";
259 clock-frequency = <400000>; 271 spi-max-frequency = <48000000>;
272 spi-flash@0 {
273 compatible = "winbond,w25q80bl";
274 reg = <0>;
275 spi-max-frequency = <48000000>;
276 };
277 };
278
279 hdmi_ddc: i2c@7000c400 {
280 status = "okay";
281 clock-frequency = <100000>;
260 }; 282 };
261 283
262 i2c@7000c500 { 284 i2c@7000c500 {
@@ -300,6 +322,30 @@
300 bus-width = <4>; 322 bus-width = <4>;
301 }; 323 };
302 324
325 regulators {
326 compatible = "simple-bus";
327 #address-cells = <1>;
328 #size-cells = <0>;
329
330 hdmi_vdd_reg: regulator@0 {
331 compatible = "regulator-fixed";
332 reg = <0>;
333 regulator-name = "avdd_hdmi";
334 regulator-min-microvolt = <3300000>;
335 regulator-max-microvolt = <3300000>;
336 regulator-always-on;
337 };
338
339 hdmi_pll_reg: regulator@1 {
340 compatible = "regulator-fixed";
341 reg = <1>;
342 regulator-name = "avdd_hdmi_pll";
343 regulator-min-microvolt = <1800000>;
344 regulator-max-microvolt = <1800000>;
345 regulator-always-on;
346 };
347 };
348
303 sound { 349 sound {
304 compatible = "nvidia,tegra-audio-trimslice"; 350 compatible = "nvidia,tegra-audio-trimslice";
305 nvidia,i2s-controller = <&tegra_i2s1>; 351 nvidia,i2s-controller = <&tegra_i2s1>;
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 3e5952fcfbc5..adc47547eaae 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -64,11 +64,6 @@
64 nvidia,pins = "dap4"; 64 nvidia,pins = "dap4";
65 nvidia,function = "dap4"; 65 nvidia,function = "dap4";
66 }; 66 };
67 ddc {
68 nvidia,pins = "ddc", "owc", "spdi", "spdo",
69 "uac";
70 nvidia,function = "rsvd2";
71 };
72 dta { 67 dta {
73 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; 68 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
74 nvidia,function = "vi"; 69 nvidia,function = "vi";
@@ -98,7 +93,7 @@
98 nvidia,function = "pcie"; 93 nvidia,function = "pcie";
99 }; 94 };
100 hdint { 95 hdint {
101 nvidia,pins = "hdint", "pta"; 96 nvidia,pins = "hdint";
102 nvidia,function = "hdmi"; 97 nvidia,function = "hdmi";
103 }; 98 };
104 i2cp { 99 i2cp {
@@ -129,6 +124,10 @@
129 "lspi", "lvp1", "lvs"; 124 "lspi", "lvp1", "lvs";
130 nvidia,function = "displaya"; 125 nvidia,function = "displaya";
131 }; 126 };
127 owc {
128 nvidia,pins = "owc", "spdi", "spdo", "uac";
129 nvidia,function = "rsvd2";
130 };
132 pmc { 131 pmc {
133 nvidia,pins = "pmc"; 132 nvidia,pins = "pmc";
134 nvidia,function = "pwr_on"; 133 nvidia,function = "pwr_on";
@@ -237,6 +236,49 @@
237 "ld23_22"; 236 "ld23_22";
238 nvidia,pull = <1>; 237 nvidia,pull = <1>;
239 }; 238 };
239 drive_sdio1 {
240 nvidia,pins = "drive_sdio1";
241 nvidia,high-speed-mode = <0>;
242 nvidia,schmitt = <1>;
243 nvidia,low-power-mode = <3>;
244 nvidia,pull-down-strength = <31>;
245 nvidia,pull-up-strength = <31>;
246 nvidia,slew-rate-rising = <3>;
247 nvidia,slew-rate-falling = <3>;
248 };
249 };
250
251 state_i2cmux_ddc: pinmux_i2cmux_ddc {
252 ddc {
253 nvidia,pins = "ddc";
254 nvidia,function = "i2c2";
255 };
256 pta {
257 nvidia,pins = "pta";
258 nvidia,function = "rsvd4";
259 };
260 };
261
262 state_i2cmux_pta: pinmux_i2cmux_pta {
263 ddc {
264 nvidia,pins = "ddc";
265 nvidia,function = "rsvd4";
266 };
267 pta {
268 nvidia,pins = "pta";
269 nvidia,function = "i2c2";
270 };
271 };
272
273 state_i2cmux_idle: pinmux_i2cmux_idle {
274 ddc {
275 nvidia,pins = "ddc";
276 nvidia,function = "rsvd4";
277 };
278 pta {
279 nvidia,pins = "pta";
280 nvidia,function = "rsvd4";
281 };
240 }; 282 };
241 }; 283 };
242 284
@@ -281,6 +323,31 @@
281 clock-frequency = <400000>; 323 clock-frequency = <400000>;
282 }; 324 };
283 325
326 i2cmux {
327 compatible = "i2c-mux-pinctrl";
328 #address-cells = <1>;
329 #size-cells = <0>;
330
331 i2c-parent = <&{/i2c@7000c400}>;
332
333 pinctrl-names = "ddc", "pta", "idle";
334 pinctrl-0 = <&state_i2cmux_ddc>;
335 pinctrl-1 = <&state_i2cmux_pta>;
336 pinctrl-2 = <&state_i2cmux_idle>;
337
338 i2c@0 {
339 reg = <0>;
340 #address-cells = <1>;
341 #size-cells = <0>;
342 };
343
344 i2c@1 {
345 reg = <1>;
346 #address-cells = <1>;
347 #size-cells = <0>;
348 };
349 };
350
284 i2c@7000c500 { 351 i2c@7000c500 {
285 status = "okay"; 352 status = "okay";
286 clock-frequency = <400000>; 353 clock-frequency = <400000>;
@@ -311,37 +378,26 @@
311 vinldo9-supply = <&sm2_reg>; 378 vinldo9-supply = <&sm2_reg>;
312 379
313 regulators { 380 regulators {
314 #address-cells = <1>; 381 sys_reg: sys {
315 #size-cells = <0>;
316
317 sys_reg: regulator@0 {
318 reg = <0>;
319 regulator-compatible = "sys";
320 regulator-name = "vdd_sys"; 382 regulator-name = "vdd_sys";
321 regulator-always-on; 383 regulator-always-on;
322 }; 384 };
323 385
324 regulator@1 { 386 sm0 {
325 reg = <1>;
326 regulator-compatible = "sm0";
327 regulator-name = "vdd_sm0,vdd_core"; 387 regulator-name = "vdd_sm0,vdd_core";
328 regulator-min-microvolt = <1200000>; 388 regulator-min-microvolt = <1200000>;
329 regulator-max-microvolt = <1200000>; 389 regulator-max-microvolt = <1200000>;
330 regulator-always-on; 390 regulator-always-on;
331 }; 391 };
332 392
333 regulator@2 { 393 sm1 {
334 reg = <2>;
335 regulator-compatible = "sm1";
336 regulator-name = "vdd_sm1,vdd_cpu"; 394 regulator-name = "vdd_sm1,vdd_cpu";
337 regulator-min-microvolt = <1000000>; 395 regulator-min-microvolt = <1000000>;
338 regulator-max-microvolt = <1000000>; 396 regulator-max-microvolt = <1000000>;
339 regulator-always-on; 397 regulator-always-on;
340 }; 398 };
341 399
342 sm2_reg: regulator@3 { 400 sm2_reg: sm2 {
343 reg = <3>;
344 regulator-compatible = "sm2";
345 regulator-name = "vdd_sm2,vin_ldo*"; 401 regulator-name = "vdd_sm2,vin_ldo*";
346 regulator-min-microvolt = <3700000>; 402 regulator-min-microvolt = <3700000>;
347 regulator-max-microvolt = <3700000>; 403 regulator-max-microvolt = <3700000>;
@@ -350,86 +406,66 @@
350 406
351 /* LDO0 is not connected to anything */ 407 /* LDO0 is not connected to anything */
352 408
353 regulator@5 { 409 ldo1 {
354 reg = <5>;
355 regulator-compatible = "ldo1";
356 regulator-name = "vdd_ldo1,avdd_pll*"; 410 regulator-name = "vdd_ldo1,avdd_pll*";
357 regulator-min-microvolt = <1100000>; 411 regulator-min-microvolt = <1100000>;
358 regulator-max-microvolt = <1100000>; 412 regulator-max-microvolt = <1100000>;
359 regulator-always-on; 413 regulator-always-on;
360 }; 414 };
361 415
362 regulator@6 { 416 ldo2 {
363 reg = <6>;
364 regulator-compatible = "ldo2";
365 regulator-name = "vdd_ldo2,vdd_rtc"; 417 regulator-name = "vdd_ldo2,vdd_rtc";
366 regulator-min-microvolt = <1200000>; 418 regulator-min-microvolt = <1200000>;
367 regulator-max-microvolt = <1200000>; 419 regulator-max-microvolt = <1200000>;
368 }; 420 };
369 421
370 regulator@7 { 422 ldo3 {
371 reg = <7>;
372 regulator-compatible = "ldo3";
373 regulator-name = "vdd_ldo3,avdd_usb*"; 423 regulator-name = "vdd_ldo3,avdd_usb*";
374 regulator-min-microvolt = <3300000>; 424 regulator-min-microvolt = <3300000>;
375 regulator-max-microvolt = <3300000>; 425 regulator-max-microvolt = <3300000>;
376 regulator-always-on; 426 regulator-always-on;
377 }; 427 };
378 428
379 regulator@8 { 429 ldo4 {
380 reg = <8>;
381 regulator-compatible = "ldo4";
382 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; 430 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
383 regulator-min-microvolt = <1800000>; 431 regulator-min-microvolt = <1800000>;
384 regulator-max-microvolt = <1800000>; 432 regulator-max-microvolt = <1800000>;
385 regulator-always-on; 433 regulator-always-on;
386 }; 434 };
387 435
388 regulator@9 { 436 ldo5 {
389 reg = <9>;
390 regulator-compatible = "ldo5";
391 regulator-name = "vdd_ldo5,vcore_mmc"; 437 regulator-name = "vdd_ldo5,vcore_mmc";
392 regulator-min-microvolt = <2850000>; 438 regulator-min-microvolt = <2850000>;
393 regulator-max-microvolt = <2850000>; 439 regulator-max-microvolt = <2850000>;
394 regulator-always-on; 440 regulator-always-on;
395 }; 441 };
396 442
397 regulator@10 { 443 ldo6 {
398 reg = <10>;
399 regulator-compatible = "ldo6";
400 regulator-name = "vdd_ldo6,avdd_vdac"; 444 regulator-name = "vdd_ldo6,avdd_vdac";
401 regulator-min-microvolt = <1800000>; 445 regulator-min-microvolt = <1800000>;
402 regulator-max-microvolt = <1800000>; 446 regulator-max-microvolt = <1800000>;
403 }; 447 };
404 448
405 regulator@11 { 449 ldo7 {
406 reg = <11>;
407 regulator-compatible = "ldo7";
408 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; 450 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
409 regulator-min-microvolt = <3300000>; 451 regulator-min-microvolt = <3300000>;
410 regulator-max-microvolt = <3300000>; 452 regulator-max-microvolt = <3300000>;
411 }; 453 };
412 454
413 regulator@12 { 455 ldo8 {
414 reg = <12>;
415 regulator-compatible = "ldo8";
416 regulator-name = "vdd_ldo8,avdd_hdmi_pll"; 456 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
417 regulator-min-microvolt = <1800000>; 457 regulator-min-microvolt = <1800000>;
418 regulator-max-microvolt = <1800000>; 458 regulator-max-microvolt = <1800000>;
419 }; 459 };
420 460
421 regulator@13 { 461 ldo9 {
422 reg = <13>;
423 regulator-compatible = "ldo9";
424 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; 462 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
425 regulator-min-microvolt = <2850000>; 463 regulator-min-microvolt = <2850000>;
426 regulator-max-microvolt = <2850000>; 464 regulator-max-microvolt = <2850000>;
427 regulator-always-on; 465 regulator-always-on;
428 }; 466 };
429 467
430 regulator@14 { 468 ldo_rtc {
431 reg = <14>;
432 regulator-compatible = "ldo_rtc";
433 regulator-name = "vdd_rtc_out,vdd_cell"; 469 regulator-name = "vdd_rtc_out,vdd_cell";
434 regulator-min-microvolt = <3300000>; 470 regulator-min-microvolt = <3300000>;
435 regulator-max-microvolt = <3300000>; 471 regulator-max-microvolt = <3300000>;
@@ -437,6 +473,11 @@
437 }; 473 };
438 }; 474 };
439 }; 475 };
476
477 temperature-sensor@4c {
478 compatible = "onnn,nct1008";
479 reg = <0x4c>;
480 };
440 }; 481 };
441 482
442 pmc { 483 pmc {
@@ -456,6 +497,12 @@
456 status = "okay"; 497 status = "okay";
457 }; 498 };
458 499
500 sdhci@c8000000 {
501 status = "okay";
502 power-gpios = <&gpio 86 0>; /* gpio PK6 */
503 bus-width = <4>;
504 };
505
459 sdhci@c8000400 { 506 sdhci@c8000400 {
460 status = "okay"; 507 status = "okay";
461 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 508 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index c636d002d6d8..20d576ecd555 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -10,6 +10,18 @@
10 reg = <0x00000000 0x20000000>; 10 reg = <0x00000000 0x20000000>;
11 }; 11 };
12 12
13 host1x {
14 hdmi {
15 status = "okay";
16
17 vdd-supply = <&hdmi_vdd_reg>;
18 pll-supply = <&hdmi_pll_reg>;
19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
22 };
23 };
24
13 pinmux { 25 pinmux {
14 pinctrl-names = "default"; 26 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>; 27 pinctrl-0 = <&state_default>;
@@ -246,6 +258,11 @@
246 clock-frequency = <216000000>; 258 clock-frequency = <216000000>;
247 }; 259 };
248 260
261 hdmi_ddc: i2c@7000c400 {
262 status = "okay";
263 clock-frequency = <100000>;
264 };
265
249 i2c@7000d000 { 266 i2c@7000d000 {
250 status = "okay"; 267 status = "okay";
251 clock-frequency = <100000>; 268 clock-frequency = <100000>;
@@ -295,243 +312,182 @@
295 in20-supply = <&mbatt_reg>; 312 in20-supply = <&mbatt_reg>;
296 313
297 regulators { 314 regulators {
298 #address-cells = <1>; 315 mbatt_reg: mbatt {
299 #size-cells = <0>;
300
301 mbatt_reg: regulator@0 {
302 reg = <0>;
303 regulator-compatible = "mbatt";
304 regulator-name = "vbat_pmu"; 316 regulator-name = "vbat_pmu";
305 regulator-always-on; 317 regulator-always-on;
306 }; 318 };
307 319
308 regulator@1 { 320 sd1 {
309 reg = <1>;
310 regulator-compatible = "sd1";
311 regulator-name = "nvvdd_sv1,vdd_cpu_pmu"; 321 regulator-name = "nvvdd_sv1,vdd_cpu_pmu";
312 regulator-min-microvolt = <1000000>; 322 regulator-min-microvolt = <1000000>;
313 regulator-max-microvolt = <1000000>; 323 regulator-max-microvolt = <1000000>;
314 regulator-always-on; 324 regulator-always-on;
315 }; 325 };
316 326
317 regulator@2 { 327 sd2 {
318 reg = <2>;
319 regulator-compatible = "sd2";
320 regulator-name = "nvvdd_sv2,vdd_core"; 328 regulator-name = "nvvdd_sv2,vdd_core";
321 regulator-min-microvolt = <1200000>; 329 regulator-min-microvolt = <1200000>;
322 regulator-max-microvolt = <1200000>; 330 regulator-max-microvolt = <1200000>;
323 regulator-always-on; 331 regulator-always-on;
324 }; 332 };
325 333
326 nvvdd_sv3_reg: regulator@3 { 334 nvvdd_sv3_reg: sd3 {
327 reg = <3>;
328 regulator-compatible = "sd3";
329 regulator-name = "nvvdd_sv3"; 335 regulator-name = "nvvdd_sv3";
330 regulator-min-microvolt = <1800000>; 336 regulator-min-microvolt = <1800000>;
331 regulator-max-microvolt = <1800000>; 337 regulator-max-microvolt = <1800000>;
332 regulator-always-on; 338 regulator-always-on;
333 }; 339 };
334 340
335 regulator@4 { 341 ldo1 {
336 reg = <4>;
337 regulator-compatible = "ldo1";
338 regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc"; 342 regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc";
339 regulator-min-microvolt = <3300000>; 343 regulator-min-microvolt = <3300000>;
340 regulator-max-microvolt = <3300000>; 344 regulator-max-microvolt = <3300000>;
341 regulator-always-on; 345 regulator-always-on;
342 }; 346 };
343 347
344 regulator@5 { 348 ldo2 {
345 reg = <5>;
346 regulator-compatible = "ldo2";
347 regulator-name = "nvvdd_ldo2,avdd_pll*"; 349 regulator-name = "nvvdd_ldo2,avdd_pll*";
348 regulator-min-microvolt = <1100000>; 350 regulator-min-microvolt = <1100000>;
349 regulator-max-microvolt = <1100000>; 351 regulator-max-microvolt = <1100000>;
350 regulator-always-on; 352 regulator-always-on;
351 }; 353 };
352 354
353 regulator@6 { 355 ldo3 {
354 reg = <6>;
355 regulator-compatible = "ldo3";
356 regulator-name = "nvvdd_ldo3,vcom_1v8b"; 356 regulator-name = "nvvdd_ldo3,vcom_1v8b";
357 regulator-min-microvolt = <1800000>; 357 regulator-min-microvolt = <1800000>;
358 regulator-max-microvolt = <1800000>; 358 regulator-max-microvolt = <1800000>;
359 regulator-always-on; 359 regulator-always-on;
360 }; 360 };
361 361
362 regulator@7 { 362 ldo4 {
363 reg = <7>;
364 regulator-compatible = "ldo4";
365 regulator-name = "nvvdd_ldo4,avdd_usb*"; 363 regulator-name = "nvvdd_ldo4,avdd_usb*";
366 regulator-min-microvolt = <3300000>; 364 regulator-min-microvolt = <3300000>;
367 regulator-max-microvolt = <3300000>; 365 regulator-max-microvolt = <3300000>;
368 regulator-always-on; 366 regulator-always-on;
369 }; 367 };
370 368
371 regulator@8 { 369 ldo5 {
372 reg = <8>;
373 regulator-compatible = "ldo5";
374 regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire"; 370 regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire";
375 regulator-min-microvolt = <2800000>; 371 regulator-min-microvolt = <2800000>;
376 regulator-max-microvolt = <2800000>; 372 regulator-max-microvolt = <2800000>;
377 regulator-always-on; 373 regulator-always-on;
378 }; 374 };
379 375
380 regulator@9 { 376 hdmi_pll_reg: ldo6 {
381 reg = <9>;
382 regulator-compatible = "ldo6";
383 regulator-name = "nvvdd_ldo6,avdd_hdmi_pll"; 377 regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
384 regulator-min-microvolt = <1800000>; 378 regulator-min-microvolt = <1800000>;
385 regulator-max-microvolt = <1800000>; 379 regulator-max-microvolt = <1800000>;
386 }; 380 };
387 381
388 regulator@10 { 382 ldo7 {
389 reg = <10>;
390 regulator-compatible = "ldo7";
391 regulator-name = "nvvdd_ldo7,avddio_audio"; 383 regulator-name = "nvvdd_ldo7,avddio_audio";
392 regulator-min-microvolt = <2800000>; 384 regulator-min-microvolt = <2800000>;
393 regulator-max-microvolt = <2800000>; 385 regulator-max-microvolt = <2800000>;
394 regulator-always-on; 386 regulator-always-on;
395 }; 387 };
396 388
397 regulator@11 { 389 ldo8 {
398 reg = <11>;
399 regulator-compatible = "ldo8";
400 regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps"; 390 regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps";
401 regulator-min-microvolt = <3000000>; 391 regulator-min-microvolt = <3000000>;
402 regulator-max-microvolt = <3000000>; 392 regulator-max-microvolt = <3000000>;
403 }; 393 };
404 394
405 regulator@12 { 395 ldo9 {
406 reg = <12>;
407 regulator-compatible = "ldo9";
408 regulator-name = "nvvdd_ldo9,avdd_cam*"; 396 regulator-name = "nvvdd_ldo9,avdd_cam*";
409 regulator-min-microvolt = <2800000>; 397 regulator-min-microvolt = <2800000>;
410 regulator-max-microvolt = <2800000>; 398 regulator-max-microvolt = <2800000>;
411 }; 399 };
412 400
413 regulator@13 { 401 ldo10 {
414 reg = <13>;
415 regulator-compatible = "ldo10";
416 regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0"; 402 regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0";
417 regulator-min-microvolt = <3000000>; 403 regulator-min-microvolt = <3000000>;
418 regulator-max-microvolt = <3000000>; 404 regulator-max-microvolt = <3000000>;
419 regulator-always-on; 405 regulator-always-on;
420 }; 406 };
421 407
422 regulator@14 { 408 hdmi_vdd_reg: ldo11 {
423 reg = <14>;
424 regulator-compatible = "ldo11";
425 regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi"; 409 regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
426 regulator-min-microvolt = <3300000>; 410 regulator-min-microvolt = <3300000>;
427 regulator-max-microvolt = <3300000>; 411 regulator-max-microvolt = <3300000>;
428 }; 412 };
429 413
430 regulator@15 { 414 ldo12 {
431 reg = <15>;
432 regulator-compatible = "ldo12";
433 regulator-name = "nvvdd_ldo12,vddio_sdio"; 415 regulator-name = "nvvdd_ldo12,vddio_sdio";
434 regulator-min-microvolt = <2800000>; 416 regulator-min-microvolt = <2800000>;
435 regulator-max-microvolt = <2800000>; 417 regulator-max-microvolt = <2800000>;
436 regulator-always-on; 418 regulator-always-on;
437 }; 419 };
438 420
439 regulator@16 { 421 ldo13 {
440 reg = <16>;
441 regulator-compatible = "ldo13";
442 regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af"; 422 regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af";
443 regulator-min-microvolt = <2800000>; 423 regulator-min-microvolt = <2800000>;
444 regulator-max-microvolt = <2800000>; 424 regulator-max-microvolt = <2800000>;
445 }; 425 };
446 426
447 regulator@17 { 427 ldo14 {
448 reg = <17>;
449 regulator-compatible = "ldo14";
450 regulator-name = "nvvdd_ldo14,avdd_vdac"; 428 regulator-name = "nvvdd_ldo14,avdd_vdac";
451 regulator-min-microvolt = <2800000>; 429 regulator-min-microvolt = <2800000>;
452 regulator-max-microvolt = <2800000>; 430 regulator-max-microvolt = <2800000>;
453 }; 431 };
454 432
455 regulator@18 { 433 ldo15 {
456 reg = <18>;
457 regulator-compatible = "ldo15";
458 regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp"; 434 regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp";
459 regulator-min-microvolt = <3300000>; 435 regulator-min-microvolt = <3300000>;
460 regulator-max-microvolt = <3300000>; 436 regulator-max-microvolt = <3300000>;
461 }; 437 };
462 438
463 regulator@19 { 439 ldo16 {
464 reg = <19>;
465 regulator-compatible = "ldo16";
466 regulator-name = "nvvdd_ldo16,vdd_dbrtr"; 440 regulator-name = "nvvdd_ldo16,vdd_dbrtr";
467 regulator-min-microvolt = <1300000>; 441 regulator-min-microvolt = <1300000>;
468 regulator-max-microvolt = <1300000>; 442 regulator-max-microvolt = <1300000>;
469 }; 443 };
470 444
471 regulator@20 { 445 ldo17 {
472 reg = <20>;
473 regulator-compatible = "ldo17";
474 regulator-name = "nvvdd_ldo17,vddio_mipi"; 446 regulator-name = "nvvdd_ldo17,vddio_mipi";
475 regulator-min-microvolt = <1200000>; 447 regulator-min-microvolt = <1200000>;
476 regulator-max-microvolt = <1200000>; 448 regulator-max-microvolt = <1200000>;
477 }; 449 };
478 450
479 regulator@21 { 451 ldo18 {
480 reg = <21>;
481 regulator-compatible = "ldo18";
482 regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*"; 452 regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*";
483 regulator-min-microvolt = <1800000>; 453 regulator-min-microvolt = <1800000>;
484 regulator-max-microvolt = <1800000>; 454 regulator-max-microvolt = <1800000>;
485 }; 455 };
486 456
487 regulator@22 { 457 ldo19 {
488 reg = <22>;
489 regulator-compatible = "ldo19";
490 regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx"; 458 regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx";
491 regulator-min-microvolt = <2800000>; 459 regulator-min-microvolt = <2800000>;
492 regulator-max-microvolt = <2800000>; 460 regulator-max-microvolt = <2800000>;
493 }; 461 };
494 462
495 regulator@23 { 463 ldo20 {
496 reg = <23>;
497 regulator-compatible = "ldo20";
498 regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2"; 464 regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2";
499 regulator-min-microvolt = <1200000>; 465 regulator-min-microvolt = <1200000>;
500 regulator-max-microvolt = <1200000>; 466 regulator-max-microvolt = <1200000>;
501 regulator-always-on; 467 regulator-always-on;
502 }; 468 };
503 469
504 regulator@24 { 470 out5v {
505 reg = <24>;
506 regulator-compatible = "out5v";
507 regulator-name = "usb0_vbus_reg"; 471 regulator-name = "usb0_vbus_reg";
508 }; 472 };
509 473
510 regulator@25 { 474 out33v {
511 reg = <25>;
512 regulator-compatible = "out33v";
513 regulator-name = "pmu_out3v3"; 475 regulator-name = "pmu_out3v3";
514 }; 476 };
515 477
516 regulator@26 { 478 bbat {
517 reg = <26>;
518 regulator-compatible = "bbat";
519 regulator-name = "pmu_bbat"; 479 regulator-name = "pmu_bbat";
520 regulator-min-microvolt = <2400000>; 480 regulator-min-microvolt = <2400000>;
521 regulator-max-microvolt = <2400000>; 481 regulator-max-microvolt = <2400000>;
522 regulator-always-on; 482 regulator-always-on;
523 }; 483 };
524 484
525 regulator@27 { 485 sdby {
526 reg = <27>;
527 regulator-compatible = "sdby";
528 regulator-name = "vdd_aon"; 486 regulator-name = "vdd_aon";
529 regulator-always-on; 487 regulator-always-on;
530 }; 488 };
531 489
532 regulator@28 { 490 vrtc {
533 reg = <28>;
534 regulator-compatible = "vrtc";
535 regulator-name = "vrtc,pmu_vccadc"; 491 regulator-name = "vrtc,pmu_vccadc";
536 regulator-always-on; 492 regulator-always-on;
537 }; 493 };
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index f3a09d0d45bc..b8effa1cbda7 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -4,6 +4,108 @@
4 compatible = "nvidia,tegra20"; 4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>; 5 interrupt-parent = <&intc>;
6 6
7 host1x {
8 compatible = "nvidia,tegra20-host1x", "simple-bus";
9 reg = <0x50000000 0x00024000>;
10 interrupts = <0 65 0x04 /* mpcore syncpt */
11 0 67 0x04>; /* mpcore general */
12
13 #address-cells = <1>;
14 #size-cells = <1>;
15
16 ranges = <0x54000000 0x54000000 0x04000000>;
17
18 mpe {
19 compatible = "nvidia,tegra20-mpe";
20 reg = <0x54040000 0x00040000>;
21 interrupts = <0 68 0x04>;
22 };
23
24 vi {
25 compatible = "nvidia,tegra20-vi";
26 reg = <0x54080000 0x00040000>;
27 interrupts = <0 69 0x04>;
28 };
29
30 epp {
31 compatible = "nvidia,tegra20-epp";
32 reg = <0x540c0000 0x00040000>;
33 interrupts = <0 70 0x04>;
34 };
35
36 isp {
37 compatible = "nvidia,tegra20-isp";
38 reg = <0x54100000 0x00040000>;
39 interrupts = <0 71 0x04>;
40 };
41
42 gr2d {
43 compatible = "nvidia,tegra20-gr2d";
44 reg = <0x54140000 0x00040000>;
45 interrupts = <0 72 0x04>;
46 };
47
48 gr3d {
49 compatible = "nvidia,tegra20-gr3d";
50 reg = <0x54180000 0x00040000>;
51 };
52
53 dc@54200000 {
54 compatible = "nvidia,tegra20-dc";
55 reg = <0x54200000 0x00040000>;
56 interrupts = <0 73 0x04>;
57
58 rgb {
59 status = "disabled";
60 };
61 };
62
63 dc@54240000 {
64 compatible = "nvidia,tegra20-dc";
65 reg = <0x54240000 0x00040000>;
66 interrupts = <0 74 0x04>;
67
68 rgb {
69 status = "disabled";
70 };
71 };
72
73 hdmi {
74 compatible = "nvidia,tegra20-hdmi";
75 reg = <0x54280000 0x00040000>;
76 interrupts = <0 75 0x04>;
77 status = "disabled";
78 };
79
80 tvo {
81 compatible = "nvidia,tegra20-tvo";
82 reg = <0x542c0000 0x00040000>;
83 interrupts = <0 76 0x04>;
84 status = "disabled";
85 };
86
87 dsi {
88 compatible = "nvidia,tegra20-dsi";
89 reg = <0x54300000 0x00040000>;
90 status = "disabled";
91 };
92 };
93
94 timer@50004600 {
95 compatible = "arm,cortex-a9-twd-timer";
96 reg = <0x50040600 0x20>;
97 interrupts = <1 13 0x304>;
98 };
99
100 cache-controller@50043000 {
101 compatible = "arm,pl310-cache";
102 reg = <0x50043000 0x1000>;
103 arm,data-latency = <5 5 2>;
104 arm,tag-latency = <4 4 2>;
105 cache-unified;
106 cache-level = <2>;
107 };
108
7 intc: interrupt-controller { 109 intc: interrupt-controller {
8 compatible = "arm,cortex-a9-gic"; 110 compatible = "arm,cortex-a9-gic";
9 reg = <0x50041000 0x1000 111 reg = <0x50041000 0x1000
@@ -12,6 +114,15 @@
12 #interrupt-cells = <3>; 114 #interrupt-cells = <3>;
13 }; 115 };
14 116
117 timer@60005000 {
118 compatible = "nvidia,tegra20-timer";
119 reg = <0x60005000 0x60>;
120 interrupts = <0 0 0x04
121 0 1 0x04
122 0 41 0x04
123 0 42 0x04>;
124 };
125
15 apbdma: dma { 126 apbdma: dma {
16 compatible = "nvidia,tegra20-apbdma"; 127 compatible = "nvidia,tegra20-apbdma";
17 reg = <0x6000a000 0x1200>; 128 reg = <0x6000a000 0x1200>;
@@ -129,6 +240,12 @@
129 #pwm-cells = <2>; 240 #pwm-cells = <2>;
130 }; 241 };
131 242
243 rtc {
244 compatible = "nvidia,tegra20-rtc";
245 reg = <0x7000e000 0x100>;
246 interrupts = <0 2 0x04>;
247 };
248
132 i2c@7000c000 { 249 i2c@7000c000 {
133 compatible = "nvidia,tegra20-i2c"; 250 compatible = "nvidia,tegra20-i2c";
134 reg = <0x7000c000 0x100>; 251 reg = <0x7000c000 0x100>;
@@ -138,6 +255,16 @@
138 status = "disabled"; 255 status = "disabled";
139 }; 256 };
140 257
258 spi@7000c380 {
259 compatible = "nvidia,tegra20-sflash";
260 reg = <0x7000c380 0x80>;
261 interrupts = <0 39 0x04>;
262 nvidia,dma-request-selector = <&apbdma 11>;
263 #address-cells = <1>;
264 #size-cells = <0>;
265 status = "disabled";
266 };
267
141 i2c@7000c400 { 268 i2c@7000c400 {
142 compatible = "nvidia,tegra20-i2c"; 269 compatible = "nvidia,tegra20-i2c";
143 reg = <0x7000c400 0x100>; 270 reg = <0x7000c400 0x100>;
@@ -165,6 +292,46 @@
165 status = "disabled"; 292 status = "disabled";
166 }; 293 };
167 294
295 spi@7000d400 {
296 compatible = "nvidia,tegra20-slink";
297 reg = <0x7000d400 0x200>;
298 interrupts = <0 59 0x04>;
299 nvidia,dma-request-selector = <&apbdma 15>;
300 #address-cells = <1>;
301 #size-cells = <0>;
302 status = "disabled";
303 };
304
305 spi@7000d600 {
306 compatible = "nvidia,tegra20-slink";
307 reg = <0x7000d600 0x200>;
308 interrupts = <0 82 0x04>;
309 nvidia,dma-request-selector = <&apbdma 16>;
310 #address-cells = <1>;
311 #size-cells = <0>;
312 status = "disabled";
313 };
314
315 spi@7000d800 {
316 compatible = "nvidia,tegra20-slink";
317 reg = <0x7000d480 0x200>;
318 interrupts = <0 83 0x04>;
319 nvidia,dma-request-selector = <&apbdma 17>;
320 #address-cells = <1>;
321 #size-cells = <0>;
322 status = "disabled";
323 };
324
325 spi@7000da00 {
326 compatible = "nvidia,tegra20-slink";
327 reg = <0x7000da00 0x200>;
328 interrupts = <0 93 0x04>;
329 nvidia,dma-request-selector = <&apbdma 18>;
330 #address-cells = <1>;
331 #size-cells = <0>;
332 status = "disabled";
333 };
334
168 pmc { 335 pmc {
169 compatible = "nvidia,tegra20-pmc"; 336 compatible = "nvidia,tegra20-pmc";
170 reg = <0x7000e400 0x400>; 337 reg = <0x7000e400 0x400>;
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
index dd4222f00eca..adc88aa50eb6 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
@@ -83,5 +83,11 @@
83 gpio = <&gpio 83 0>; /* GPIO PK3 */ 83 gpio = <&gpio 83 0>; /* GPIO PK3 */
84 }; 84 };
85 }; 85 };
86
87 sdhci@78000400 {
88 status = "okay";
89 power-gpios = <&gpio 28 0>; /* gpio PD4 */
90 bus-width = <4>;
91 };
86}; 92};
87 93
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
index 0828f097ca86..08163e145d57 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
@@ -95,4 +95,10 @@
95 gpio = <&gpio 232 0>; /* GPIO PDD0 */ 95 gpio = <&gpio 232 0>; /* GPIO PDD0 */
96 }; 96 };
97 }; 97 };
98
99 sdhci@78000400 {
100 status = "okay";
101 power-gpios = <&gpio 27 0>; /* gpio PD3 */
102 bus-width = <4>;
103 };
98}; 104};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index d10c9c5a3606..bdb2a660f376 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -52,6 +52,22 @@
52 nvidia,pull = <2>; 52 nvidia,pull = <2>;
53 nvidia,tristate = <0>; 53 nvidia,tristate = <0>;
54 }; 54 };
55 sdmmc3_clk_pa6 {
56 nvidia,pins = "sdmmc3_clk_pa6";
57 nvidia,function = "sdmmc3";
58 nvidia,pull = <0>;
59 nvidia,tristate = <0>;
60 };
61 sdmmc3_cmd_pa7 {
62 nvidia,pins = "sdmmc3_cmd_pa7",
63 "sdmmc3_dat0_pb7",
64 "sdmmc3_dat1_pb6",
65 "sdmmc3_dat2_pb5",
66 "sdmmc3_dat3_pb4";
67 nvidia,function = "sdmmc3";
68 nvidia,pull = <2>;
69 nvidia,tristate = <0>;
70 };
55 sdmmc4_clk_pcc4 { 71 sdmmc4_clk_pcc4 {
56 nvidia,pins = "sdmmc4_clk_pcc4", 72 nvidia,pins = "sdmmc4_clk_pcc4",
57 "sdmmc4_rst_n_pcc3"; 73 "sdmmc4_rst_n_pcc3";
@@ -81,6 +97,15 @@
81 nvidia,pull = <0>; 97 nvidia,pull = <0>;
82 nvidia,tristate = <0>; 98 nvidia,tristate = <0>;
83 }; 99 };
100 sdio3 {
101 nvidia,pins = "drive_sdio3";
102 nvidia,high-speed-mode = <0>;
103 nvidia,schmitt = <0>;
104 nvidia,pull-down-strength = <46>;
105 nvidia,pull-up-strength = <42>;
106 nvidia,slew-rate-rising = <1>;
107 nvidia,slew-rate-falling = <1>;
108 };
84 }; 109 };
85 }; 110 };
86 111
@@ -171,56 +196,41 @@
171 vccio-supply = <&vdd_ac_bat_reg>; 196 vccio-supply = <&vdd_ac_bat_reg>;
172 197
173 regulators { 198 regulators {
174 #address-cells = <1>; 199 vdd1_reg: vdd1 {
175 #size-cells = <0>;
176
177 vdd1_reg: regulator@0 {
178 reg = <0>;
179 regulator-compatible = "vdd1";
180 regulator-name = "vddio_ddr_1v2"; 200 regulator-name = "vddio_ddr_1v2";
181 regulator-min-microvolt = <1200000>; 201 regulator-min-microvolt = <1200000>;
182 regulator-max-microvolt = <1200000>; 202 regulator-max-microvolt = <1200000>;
183 regulator-always-on; 203 regulator-always-on;
184 }; 204 };
185 205
186 vdd2_reg: regulator@1 { 206 vdd2_reg: vdd2 {
187 reg = <1>;
188 regulator-compatible = "vdd2";
189 regulator-name = "vdd_1v5_gen"; 207 regulator-name = "vdd_1v5_gen";
190 regulator-min-microvolt = <1500000>; 208 regulator-min-microvolt = <1500000>;
191 regulator-max-microvolt = <1500000>; 209 regulator-max-microvolt = <1500000>;
192 regulator-always-on; 210 regulator-always-on;
193 }; 211 };
194 212
195 vddctrl_reg: regulator@2 { 213 vddctrl_reg: vddctrl {
196 reg = <2>;
197 regulator-compatible = "vddctrl";
198 regulator-name = "vdd_cpu,vdd_sys"; 214 regulator-name = "vdd_cpu,vdd_sys";
199 regulator-min-microvolt = <1000000>; 215 regulator-min-microvolt = <1000000>;
200 regulator-max-microvolt = <1000000>; 216 regulator-max-microvolt = <1000000>;
201 regulator-always-on; 217 regulator-always-on;
202 }; 218 };
203 219
204 vio_reg: regulator@3 { 220 vio_reg: vio {
205 reg = <3>;
206 regulator-compatible = "vio";
207 regulator-name = "vdd_1v8_gen"; 221 regulator-name = "vdd_1v8_gen";
208 regulator-min-microvolt = <1800000>; 222 regulator-min-microvolt = <1800000>;
209 regulator-max-microvolt = <1800000>; 223 regulator-max-microvolt = <1800000>;
210 regulator-always-on; 224 regulator-always-on;
211 }; 225 };
212 226
213 ldo1_reg: regulator@4 { 227 ldo1_reg: ldo1 {
214 reg = <4>;
215 regulator-compatible = "ldo1";
216 regulator-name = "vdd_pexa,vdd_pexb"; 228 regulator-name = "vdd_pexa,vdd_pexb";
217 regulator-min-microvolt = <1050000>; 229 regulator-min-microvolt = <1050000>;
218 regulator-max-microvolt = <1050000>; 230 regulator-max-microvolt = <1050000>;
219 }; 231 };
220 232
221 ldo2_reg: regulator@5 { 233 ldo2_reg: ldo2 {
222 reg = <5>;
223 regulator-compatible = "ldo2";
224 regulator-name = "vdd_sata,avdd_plle"; 234 regulator-name = "vdd_sata,avdd_plle";
225 regulator-min-microvolt = <1050000>; 235 regulator-min-microvolt = <1050000>;
226 regulator-max-microvolt = <1050000>; 236 regulator-max-microvolt = <1050000>;
@@ -228,44 +238,34 @@
228 238
229 /* LDO3 is not connected to anything */ 239 /* LDO3 is not connected to anything */
230 240
231 ldo4_reg: regulator@7 { 241 ldo4_reg: ldo4 {
232 reg = <7>;
233 regulator-compatible = "ldo4";
234 regulator-name = "vdd_rtc"; 242 regulator-name = "vdd_rtc";
235 regulator-min-microvolt = <1200000>; 243 regulator-min-microvolt = <1200000>;
236 regulator-max-microvolt = <1200000>; 244 regulator-max-microvolt = <1200000>;
237 regulator-always-on; 245 regulator-always-on;
238 }; 246 };
239 247
240 ldo5_reg: regulator@8 { 248 ldo5_reg: ldo5 {
241 reg = <8>;
242 regulator-compatible = "ldo5";
243 regulator-name = "vddio_sdmmc,avdd_vdac"; 249 regulator-name = "vddio_sdmmc,avdd_vdac";
244 regulator-min-microvolt = <3300000>; 250 regulator-min-microvolt = <3300000>;
245 regulator-max-microvolt = <3300000>; 251 regulator-max-microvolt = <3300000>;
246 regulator-always-on; 252 regulator-always-on;
247 }; 253 };
248 254
249 ldo6_reg: regulator@9 { 255 ldo6_reg: ldo6 {
250 reg = <9>;
251 regulator-compatible = "ldo6";
252 regulator-name = "avdd_dsi_csi,pwrdet_mipi"; 256 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
253 regulator-min-microvolt = <1200000>; 257 regulator-min-microvolt = <1200000>;
254 regulator-max-microvolt = <1200000>; 258 regulator-max-microvolt = <1200000>;
255 }; 259 };
256 260
257 ldo7_reg: regulator@10 { 261 ldo7_reg: ldo7 {
258 reg = <10>;
259 regulator-compatible = "ldo7";
260 regulator-name = "vdd_pllm,x,u,a_p_c_s"; 262 regulator-name = "vdd_pllm,x,u,a_p_c_s";
261 regulator-min-microvolt = <1200000>; 263 regulator-min-microvolt = <1200000>;
262 regulator-max-microvolt = <1200000>; 264 regulator-max-microvolt = <1200000>;
263 regulator-always-on; 265 regulator-always-on;
264 }; 266 };
265 267
266 ldo8_reg: regulator@11 { 268 ldo8_reg: ldo8 {
267 reg = <11>;
268 regulator-compatible = "ldo8";
269 regulator-name = "vdd_ddr_hs"; 269 regulator-name = "vdd_ddr_hs";
270 regulator-min-microvolt = <1000000>; 270 regulator-min-microvolt = <1000000>;
271 regulator-max-microvolt = <1000000>; 271 regulator-max-microvolt = <1000000>;
@@ -275,6 +275,16 @@
275 }; 275 };
276 }; 276 };
277 277
278 spi@7000da00 {
279 status = "okay";
280 spi-max-frequency = <25000000>;
281 spi-flash@1 {
282 compatible = "winbond,w25q32";
283 reg = <1>;
284 spi-max-frequency = <20000000>;
285 };
286 };
287
278 ahub { 288 ahub {
279 i2s@70080400 { 289 i2s@70080400 {
280 status = "okay"; 290 status = "okay";
@@ -409,6 +419,8 @@
409 regulator-name = "vdd_com"; 419 regulator-name = "vdd_com";
410 regulator-min-microvolt = <3300000>; 420 regulator-min-microvolt = <3300000>;
411 regulator-max-microvolt = <3300000>; 421 regulator-max-microvolt = <3300000>;
422 regulator-always-on;
423 regulator-boot-on;
412 enable-active-high; 424 enable-active-high;
413 gpio = <&gpio 24 0>; /* gpio PD0 */ 425 gpio = <&gpio 24 0>; /* gpio PD0 */
414 vin-supply = <&sys_3v3_reg>; 426 vin-supply = <&sys_3v3_reg>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index b1497c7d7d68..529fdb82dfdb 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -4,6 +4,108 @@
4 compatible = "nvidia,tegra30"; 4 compatible = "nvidia,tegra30";
5 interrupt-parent = <&intc>; 5 interrupt-parent = <&intc>;
6 6
7 host1x {
8 compatible = "nvidia,tegra30-host1x", "simple-bus";
9 reg = <0x50000000 0x00024000>;
10 interrupts = <0 65 0x04 /* mpcore syncpt */
11 0 67 0x04>; /* mpcore general */
12
13 #address-cells = <1>;
14 #size-cells = <1>;
15
16 ranges = <0x54000000 0x54000000 0x04000000>;
17
18 mpe {
19 compatible = "nvidia,tegra30-mpe";
20 reg = <0x54040000 0x00040000>;
21 interrupts = <0 68 0x04>;
22 };
23
24 vi {
25 compatible = "nvidia,tegra30-vi";
26 reg = <0x54080000 0x00040000>;
27 interrupts = <0 69 0x04>;
28 };
29
30 epp {
31 compatible = "nvidia,tegra30-epp";
32 reg = <0x540c0000 0x00040000>;
33 interrupts = <0 70 0x04>;
34 };
35
36 isp {
37 compatible = "nvidia,tegra30-isp";
38 reg = <0x54100000 0x00040000>;
39 interrupts = <0 71 0x04>;
40 };
41
42 gr2d {
43 compatible = "nvidia,tegra30-gr2d";
44 reg = <0x54140000 0x00040000>;
45 interrupts = <0 72 0x04>;
46 };
47
48 gr3d {
49 compatible = "nvidia,tegra30-gr3d";
50 reg = <0x54180000 0x00040000>;
51 };
52
53 dc@54200000 {
54 compatible = "nvidia,tegra30-dc";
55 reg = <0x54200000 0x00040000>;
56 interrupts = <0 73 0x04>;
57
58 rgb {
59 status = "disabled";
60 };
61 };
62
63 dc@54240000 {
64 compatible = "nvidia,tegra30-dc";
65 reg = <0x54240000 0x00040000>;
66 interrupts = <0 74 0x04>;
67
68 rgb {
69 status = "disabled";
70 };
71 };
72
73 hdmi {
74 compatible = "nvidia,tegra30-hdmi";
75 reg = <0x54280000 0x00040000>;
76 interrupts = <0 75 0x04>;
77 status = "disabled";
78 };
79
80 tvo {
81 compatible = "nvidia,tegra30-tvo";
82 reg = <0x542c0000 0x00040000>;
83 interrupts = <0 76 0x04>;
84 status = "disabled";
85 };
86
87 dsi {
88 compatible = "nvidia,tegra30-dsi";
89 reg = <0x54300000 0x00040000>;
90 status = "disabled";
91 };
92 };
93
94 timer@50004600 {
95 compatible = "arm,cortex-a9-twd-timer";
96 reg = <0x50040600 0x20>;
97 interrupts = <1 13 0xf04>;
98 };
99
100 cache-controller@50043000 {
101 compatible = "arm,pl310-cache";
102 reg = <0x50043000 0x1000>;
103 arm,data-latency = <6 6 2>;
104 arm,tag-latency = <5 5 2>;
105 cache-unified;
106 cache-level = <2>;
107 };
108
7 intc: interrupt-controller { 109 intc: interrupt-controller {
8 compatible = "arm,cortex-a9-gic"; 110 compatible = "arm,cortex-a9-gic";
9 reg = <0x50041000 0x1000 111 reg = <0x50041000 0x1000
@@ -12,6 +114,17 @@
12 #interrupt-cells = <3>; 114 #interrupt-cells = <3>;
13 }; 115 };
14 116
117 timer@60005000 {
118 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
119 reg = <0x60005000 0x400>;
120 interrupts = <0 0 0x04
121 0 1 0x04
122 0 41 0x04
123 0 42 0x04
124 0 121 0x04
125 0 122 0x04>;
126 };
127
15 apbdma: dma { 128 apbdma: dma {
16 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; 129 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
17 reg = <0x6000a000 0x1400>; 130 reg = <0x6000a000 0x1400>;
@@ -73,8 +186,8 @@
73 186
74 pinmux: pinmux { 187 pinmux: pinmux {
75 compatible = "nvidia,tegra30-pinmux"; 188 compatible = "nvidia,tegra30-pinmux";
76 reg = <0x70000868 0xd0 /* Pad control registers */ 189 reg = <0x70000868 0xd4 /* Pad control registers */
77 0x70003000 0x3e0>; /* Mux registers */ 190 0x70003000 0x3e4>; /* Mux registers */
78 }; 191 };
79 192
80 serial@70006000 { 193 serial@70006000 {
@@ -123,6 +236,12 @@
123 #pwm-cells = <2>; 236 #pwm-cells = <2>;
124 }; 237 };
125 238
239 rtc {
240 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
241 reg = <0x7000e000 0x100>;
242 interrupts = <0 2 0x04>;
243 };
244
126 i2c@7000c000 { 245 i2c@7000c000 {
127 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 246 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
128 reg = <0x7000c000 0x100>; 247 reg = <0x7000c000 0x100>;
@@ -168,6 +287,66 @@
168 status = "disabled"; 287 status = "disabled";
169 }; 288 };
170 289
290 spi@7000d400 {
291 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
292 reg = <0x7000d400 0x200>;
293 interrupts = <0 59 0x04>;
294 nvidia,dma-request-selector = <&apbdma 15>;
295 #address-cells = <1>;
296 #size-cells = <0>;
297 status = "disabled";
298 };
299
300 spi@7000d600 {
301 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
302 reg = <0x7000d600 0x200>;
303 interrupts = <0 82 0x04>;
304 nvidia,dma-request-selector = <&apbdma 16>;
305 #address-cells = <1>;
306 #size-cells = <0>;
307 status = "disabled";
308 };
309
310 spi@7000d800 {
311 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
312 reg = <0x7000d480 0x200>;
313 interrupts = <0 83 0x04>;
314 nvidia,dma-request-selector = <&apbdma 17>;
315 #address-cells = <1>;
316 #size-cells = <0>;
317 status = "disabled";
318 };
319
320 spi@7000da00 {
321 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
322 reg = <0x7000da00 0x200>;
323 interrupts = <0 93 0x04>;
324 nvidia,dma-request-selector = <&apbdma 18>;
325 #address-cells = <1>;
326 #size-cells = <0>;
327 status = "disabled";
328 };
329
330 spi@7000dc00 {
331 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
332 reg = <0x7000dc00 0x200>;
333 interrupts = <0 94 0x04>;
334 nvidia,dma-request-selector = <&apbdma 27>;
335 #address-cells = <1>;
336 #size-cells = <0>;
337 status = "disabled";
338 };
339
340 spi@7000de00 {
341 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
342 reg = <0x7000de00 0x200>;
343 interrupts = <0 79 0x04>;
344 nvidia,dma-request-selector = <&apbdma 28>;
345 #address-cells = <1>;
346 #size-cells = <0>;
347 status = "disabled";
348 };
349
171 pmc { 350 pmc {
172 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc"; 351 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
173 reg = <0x7000e400 0x400>; 352 reg = <0x7000e400 0x400>;
diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
index ff000172c93c..ed0bc9546837 100644
--- a/arch/arm/boot/dts/twl4030.dtsi
+++ b/arch/arm/boot/dts/twl4030.dtsi
@@ -19,6 +19,10 @@
19 interrupts = <11>; 19 interrupts = <11>;
20 }; 20 };
21 21
22 watchdog {
23 compatible = "ti,twl4030-wdt";
24 };
25
22 vdac: regulator-vdac { 26 vdac: regulator-vdac {
23 compatible = "ti,twl4030-vdac"; 27 compatible = "ti,twl4030-vdac";
24 regulator-min-microvolt = <1800000>; 28 regulator-min-microvolt = <1800000>;
@@ -37,6 +41,24 @@
37 regulator-max-microvolt = <3150000>; 41 regulator-max-microvolt = <3150000>;
38 }; 42 };
39 43
44 vusb1v5: regulator-vusb1v5 {
45 compatible = "ti,twl4030-vusb1v5";
46 };
47
48 vusb1v8: regulator-vusb1v8 {
49 compatible = "ti,twl4030-vusb1v8";
50 };
51
52 vusb3v1: regulator-vusb3v1 {
53 compatible = "ti,twl4030-vusb3v1";
54 };
55
56 vsim: regulator-vsim {
57 compatible = "ti,twl4030-vsim";
58 regulator-min-microvolt = <1800000>;
59 regulator-max-microvolt = <3000000>;
60 };
61
40 twl_gpio: gpio { 62 twl_gpio: gpio {
41 compatible = "ti,twl4030-gpio"; 63 compatible = "ti,twl4030-gpio";
42 gpio-controller; 64 gpio-controller;
@@ -44,4 +66,13 @@
44 interrupt-controller; 66 interrupt-controller;
45 #interrupt-cells = <1>; 67 #interrupt-cells = <1>;
46 }; 68 };
69
70 twl4030-usb {
71 compatible = "ti,twl4030-usb";
72 interrupts = <10>, <4>;
73 usb1v5-supply = <&vusb1v5>;
74 usb1v8-supply = <&vusb1v8>;
75 usb3v1-supply = <&vusb3v1>;
76 usb_mode = <1>;
77 };
47}; 78};
diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi
index 123e2c40218a..9996cfc5ee80 100644
--- a/arch/arm/boot/dts/twl6030.dtsi
+++ b/arch/arm/boot/dts/twl6030.dtsi
@@ -86,4 +86,9 @@
86 clk32kg: regulator-clk32kg { 86 clk32kg: regulator-clk32kg {
87 compatible = "ti,twl6030-clk32kg"; 87 compatible = "ti,twl6030-clk32kg";
88 }; 88 };
89
90 twl_usb_comparator: usb-comparator {
91 compatible = "ti,twl6030-usb";
92 interrupts = <4>, <10>;
93 };
89}; 94};
diff --git a/arch/arm/boot/dts/u9540.dts b/arch/arm/boot/dts/u9540.dts
new file mode 100644
index 000000000000..95892ec6c342
--- /dev/null
+++ b/arch/arm/boot/dts/u9540.dts
@@ -0,0 +1,72 @@
1/*
2 * Copyright 2012 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "dbx5x0.dtsi"
14
15/ {
16 model = "ST-Ericsson U9540 platform with Device Tree";
17 compatible = "st-ericsson,u9540";
18
19 memory {
20 reg = <0x00000000 0x20000000>;
21 };
22
23 soc-u9500 {
24 uart@80120000 {
25 status = "okay";
26 };
27
28 uart@80121000 {
29 status = "okay";
30 };
31
32 uart@80007000 {
33 status = "okay";
34 };
35
36 // External Micro SD slot
37 sdi0_per1@80126000 {
38 arm,primecell-periphid = <0x10480180>;
39 max-frequency = <100000000>;
40 bus-width = <4>;
41 mmc-cap-sd-highspeed;
42 mmc-cap-mmc-highspeed;
43 vmmc-supply = <&ab8500_ldo_aux3_reg>;
44
45 cd-gpios = <&gpio7 6 0x4>; // 230
46 cd-inverted;
47
48 status = "okay";
49 };
50
51
52 // WLAN SDIO channel
53 sdi1_per2@80118000 {
54 arm,primecell-periphid = <0x10480180>;
55 max-frequency = <50000000>;
56 bus-width = <4>;
57
58 status = "okay";
59 };
60
61 // On-board eMMC
62 sdi4_per2@80114000 {
63 arm,primecell-periphid = <0x10480180>;
64 max-frequency = <100000000>;
65 bus-width = <8>;
66 mmc-cap-mmc-highspeed;
67 vmmc-supply = <&ab8500_ldo_aux2_reg>;
68
69 status = "okay";
70 };
71 };
72};
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
index d8a827bd2bf3..ac870fb3fa0d 100644
--- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -17,17 +17,16 @@
17 * CHANGES TO vexpress-v2m.dtsi! 17 * CHANGES TO vexpress-v2m.dtsi!
18 */ 18 */
19 19
20/ {
21 aliases {
22 arm,v2m_timer = &v2m_timer01;
23 };
24
25 motherboard { 20 motherboard {
26 compatible = "simple-bus"; 21 model = "V2M-P1";
22 arm,hbi = <0x190>;
23 arm,vexpress,site = <0>;
27 arm,v2m-memory-map = "rs1"; 24 arm,v2m-memory-map = "rs1";
25 compatible = "arm,vexpress,v2m-p1", "simple-bus";
28 #address-cells = <2>; /* SMB chipselect number and offset */ 26 #address-cells = <2>; /* SMB chipselect number and offset */
29 #size-cells = <1>; 27 #size-cells = <1>;
30 #interrupt-cells = <1>; 28 #interrupt-cells = <1>;
29 ranges;
31 30
32 flash@0,00000000 { 31 flash@0,00000000 {
33 compatible = "arm,vexpress-flash", "cfi-flash"; 32 compatible = "arm,vexpress-flash", "cfi-flash";
@@ -72,14 +71,20 @@
72 #size-cells = <1>; 71 #size-cells = <1>;
73 ranges = <0 3 0 0x200000>; 72 ranges = <0 3 0 0x200000>;
74 73
75 sysreg@010000 { 74 v2m_sysreg: sysreg@010000 {
76 compatible = "arm,vexpress-sysreg"; 75 compatible = "arm,vexpress-sysreg";
77 reg = <0x010000 0x1000>; 76 reg = <0x010000 0x1000>;
77 gpio-controller;
78 #gpio-cells = <2>;
78 }; 79 };
79 80
80 sysctl@020000 { 81 v2m_sysctl: sysctl@020000 {
81 compatible = "arm,sp810", "arm,primecell"; 82 compatible = "arm,sp810", "arm,primecell";
82 reg = <0x020000 0x1000>; 83 reg = <0x020000 0x1000>;
84 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
85 clock-names = "refclk", "timclk", "apb_pclk";
86 #clock-cells = <1>;
87 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
83 }; 88 };
84 89
85 /* PCI-E I2C bus */ 90 /* PCI-E I2C bus */
@@ -100,66 +105,92 @@
100 compatible = "arm,pl041", "arm,primecell"; 105 compatible = "arm,pl041", "arm,primecell";
101 reg = <0x040000 0x1000>; 106 reg = <0x040000 0x1000>;
102 interrupts = <11>; 107 interrupts = <11>;
108 clocks = <&smbclk>;
109 clock-names = "apb_pclk";
103 }; 110 };
104 111
105 mmci@050000 { 112 mmci@050000 {
106 compatible = "arm,pl180", "arm,primecell"; 113 compatible = "arm,pl180", "arm,primecell";
107 reg = <0x050000 0x1000>; 114 reg = <0x050000 0x1000>;
108 interrupts = <9 10>; 115 interrupts = <9 10>;
116 cd-gpios = <&v2m_sysreg 0 0>;
117 wp-gpios = <&v2m_sysreg 1 0>;
118 max-frequency = <12000000>;
119 vmmc-supply = <&v2m_fixed_3v3>;
120 clocks = <&v2m_clk24mhz>, <&smbclk>;
121 clock-names = "mclk", "apb_pclk";
109 }; 122 };
110 123
111 kmi@060000 { 124 kmi@060000 {
112 compatible = "arm,pl050", "arm,primecell"; 125 compatible = "arm,pl050", "arm,primecell";
113 reg = <0x060000 0x1000>; 126 reg = <0x060000 0x1000>;
114 interrupts = <12>; 127 interrupts = <12>;
128 clocks = <&v2m_clk24mhz>, <&smbclk>;
129 clock-names = "KMIREFCLK", "apb_pclk";
115 }; 130 };
116 131
117 kmi@070000 { 132 kmi@070000 {
118 compatible = "arm,pl050", "arm,primecell"; 133 compatible = "arm,pl050", "arm,primecell";
119 reg = <0x070000 0x1000>; 134 reg = <0x070000 0x1000>;
120 interrupts = <13>; 135 interrupts = <13>;
136 clocks = <&v2m_clk24mhz>, <&smbclk>;
137 clock-names = "KMIREFCLK", "apb_pclk";
121 }; 138 };
122 139
123 v2m_serial0: uart@090000 { 140 v2m_serial0: uart@090000 {
124 compatible = "arm,pl011", "arm,primecell"; 141 compatible = "arm,pl011", "arm,primecell";
125 reg = <0x090000 0x1000>; 142 reg = <0x090000 0x1000>;
126 interrupts = <5>; 143 interrupts = <5>;
144 clocks = <&v2m_oscclk2>, <&smbclk>;
145 clock-names = "uartclk", "apb_pclk";
127 }; 146 };
128 147
129 v2m_serial1: uart@0a0000 { 148 v2m_serial1: uart@0a0000 {
130 compatible = "arm,pl011", "arm,primecell"; 149 compatible = "arm,pl011", "arm,primecell";
131 reg = <0x0a0000 0x1000>; 150 reg = <0x0a0000 0x1000>;
132 interrupts = <6>; 151 interrupts = <6>;
152 clocks = <&v2m_oscclk2>, <&smbclk>;
153 clock-names = "uartclk", "apb_pclk";
133 }; 154 };
134 155
135 v2m_serial2: uart@0b0000 { 156 v2m_serial2: uart@0b0000 {
136 compatible = "arm,pl011", "arm,primecell"; 157 compatible = "arm,pl011", "arm,primecell";
137 reg = <0x0b0000 0x1000>; 158 reg = <0x0b0000 0x1000>;
138 interrupts = <7>; 159 interrupts = <7>;
160 clocks = <&v2m_oscclk2>, <&smbclk>;
161 clock-names = "uartclk", "apb_pclk";
139 }; 162 };
140 163
141 v2m_serial3: uart@0c0000 { 164 v2m_serial3: uart@0c0000 {
142 compatible = "arm,pl011", "arm,primecell"; 165 compatible = "arm,pl011", "arm,primecell";
143 reg = <0x0c0000 0x1000>; 166 reg = <0x0c0000 0x1000>;
144 interrupts = <8>; 167 interrupts = <8>;
168 clocks = <&v2m_oscclk2>, <&smbclk>;
169 clock-names = "uartclk", "apb_pclk";
145 }; 170 };
146 171
147 wdt@0f0000 { 172 wdt@0f0000 {
148 compatible = "arm,sp805", "arm,primecell"; 173 compatible = "arm,sp805", "arm,primecell";
149 reg = <0x0f0000 0x1000>; 174 reg = <0x0f0000 0x1000>;
150 interrupts = <0>; 175 interrupts = <0>;
176 clocks = <&v2m_refclk32khz>, <&smbclk>;
177 clock-names = "wdogclk", "apb_pclk";
151 }; 178 };
152 179
153 v2m_timer01: timer@110000 { 180 v2m_timer01: timer@110000 {
154 compatible = "arm,sp804", "arm,primecell"; 181 compatible = "arm,sp804", "arm,primecell";
155 reg = <0x110000 0x1000>; 182 reg = <0x110000 0x1000>;
156 interrupts = <2>; 183 interrupts = <2>;
184 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
185 clock-names = "timclken1", "timclken2", "apb_pclk";
157 }; 186 };
158 187
159 v2m_timer23: timer@120000 { 188 v2m_timer23: timer@120000 {
160 compatible = "arm,sp804", "arm,primecell"; 189 compatible = "arm,sp804", "arm,primecell";
161 reg = <0x120000 0x1000>; 190 reg = <0x120000 0x1000>;
162 interrupts = <3>; 191 interrupts = <3>;
192 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
193 clock-names = "timclken1", "timclken2", "apb_pclk";
163 }; 194 };
164 195
165 /* DVI I2C bus */ 196 /* DVI I2C bus */
@@ -185,6 +216,8 @@
185 compatible = "arm,pl031", "arm,primecell"; 216 compatible = "arm,pl031", "arm,primecell";
186 reg = <0x170000 0x1000>; 217 reg = <0x170000 0x1000>;
187 interrupts = <4>; 218 interrupts = <4>;
219 clocks = <&smbclk>;
220 clock-names = "apb_pclk";
188 }; 221 };
189 222
190 compact-flash@1a0000 { 223 compact-flash@1a0000 {
@@ -198,6 +231,8 @@
198 compatible = "arm,pl111", "arm,primecell"; 231 compatible = "arm,pl111", "arm,primecell";
199 reg = <0x1f0000 0x1000>; 232 reg = <0x1f0000 0x1000>;
200 interrupts = <14>; 233 interrupts = <14>;
234 clocks = <&v2m_oscclk1>, <&smbclk>;
235 clock-names = "clcdclk", "apb_pclk";
201 }; 236 };
202 }; 237 };
203 238
@@ -208,5 +243,98 @@
208 regulator-max-microvolt = <3300000>; 243 regulator-max-microvolt = <3300000>;
209 regulator-always-on; 244 regulator-always-on;
210 }; 245 };
246
247 v2m_clk24mhz: clk24mhz {
248 compatible = "fixed-clock";
249 #clock-cells = <0>;
250 clock-frequency = <24000000>;
251 clock-output-names = "v2m:clk24mhz";
252 };
253
254 v2m_refclk1mhz: refclk1mhz {
255 compatible = "fixed-clock";
256 #clock-cells = <0>;
257 clock-frequency = <1000000>;
258 clock-output-names = "v2m:refclk1mhz";
259 };
260
261 v2m_refclk32khz: refclk32khz {
262 compatible = "fixed-clock";
263 #clock-cells = <0>;
264 clock-frequency = <32768>;
265 clock-output-names = "v2m:refclk32khz";
266 };
267
268 mcc {
269 compatible = "arm,vexpress,config-bus";
270 arm,vexpress,config-bridge = <&v2m_sysreg>;
271
272 osc@0 {
273 /* MCC static memory clock */
274 compatible = "arm,vexpress-osc";
275 arm,vexpress-sysreg,func = <1 0>;
276 freq-range = <25000000 60000000>;
277 #clock-cells = <0>;
278 clock-output-names = "v2m:oscclk0";
279 };
280
281 v2m_oscclk1: osc@1 {
282 /* CLCD clock */
283 compatible = "arm,vexpress-osc";
284 arm,vexpress-sysreg,func = <1 1>;
285 freq-range = <23750000 63500000>;
286 #clock-cells = <0>;
287 clock-output-names = "v2m:oscclk1";
288 };
289
290 v2m_oscclk2: osc@2 {
291 /* IO FPGA peripheral clock */
292 compatible = "arm,vexpress-osc";
293 arm,vexpress-sysreg,func = <1 2>;
294 freq-range = <24000000 24000000>;
295 #clock-cells = <0>;
296 clock-output-names = "v2m:oscclk2";
297 };
298
299 volt@0 {
300 /* Logic level voltage */
301 compatible = "arm,vexpress-volt";
302 arm,vexpress-sysreg,func = <2 0>;
303 regulator-name = "VIO";
304 regulator-always-on;
305 label = "VIO";
306 };
307
308 temp@0 {
309 /* MCC internal operating temperature */
310 compatible = "arm,vexpress-temp";
311 arm,vexpress-sysreg,func = <4 0>;
312 label = "MCC";
313 };
314
315 reset@0 {
316 compatible = "arm,vexpress-reset";
317 arm,vexpress-sysreg,func = <5 0>;
318 };
319
320 muxfpga@0 {
321 compatible = "arm,vexpress-muxfpga";
322 arm,vexpress-sysreg,func = <7 0>;
323 };
324
325 shutdown@0 {
326 compatible = "arm,vexpress-shutdown";
327 arm,vexpress-sysreg,func = <8 0>;
328 };
329
330 reboot@0 {
331 compatible = "arm,vexpress-reboot";
332 arm,vexpress-sysreg,func = <9 0>;
333 };
334
335 dvimode@0 {
336 compatible = "arm,vexpress-dvimode";
337 arm,vexpress-sysreg,func = <11 0>;
338 };
339 };
211 }; 340 };
212};
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
index dba53fd026bb..f1420368355b 100644
--- a/arch/arm/boot/dts/vexpress-v2m.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -17,16 +17,15 @@
17 * CHANGES TO vexpress-v2m-rs1.dtsi! 17 * CHANGES TO vexpress-v2m-rs1.dtsi!
18 */ 18 */
19 19
20/ {
21 aliases {
22 arm,v2m_timer = &v2m_timer01;
23 };
24
25 motherboard { 20 motherboard {
26 compatible = "simple-bus"; 21 model = "V2M-P1";
22 arm,hbi = <0x190>;
23 arm,vexpress,site = <0>;
24 compatible = "arm,vexpress,v2m-p1", "simple-bus";
27 #address-cells = <2>; /* SMB chipselect number and offset */ 25 #address-cells = <2>; /* SMB chipselect number and offset */
28 #size-cells = <1>; 26 #size-cells = <1>;
29 #interrupt-cells = <1>; 27 #interrupt-cells = <1>;
28 ranges;
30 29
31 flash@0,00000000 { 30 flash@0,00000000 {
32 compatible = "arm,vexpress-flash", "cfi-flash"; 31 compatible = "arm,vexpress-flash", "cfi-flash";
@@ -71,14 +70,20 @@
71 #size-cells = <1>; 70 #size-cells = <1>;
72 ranges = <0 7 0 0x20000>; 71 ranges = <0 7 0 0x20000>;
73 72
74 sysreg@00000 { 73 v2m_sysreg: sysreg@00000 {
75 compatible = "arm,vexpress-sysreg"; 74 compatible = "arm,vexpress-sysreg";
76 reg = <0x00000 0x1000>; 75 reg = <0x00000 0x1000>;
76 gpio-controller;
77 #gpio-cells = <2>;
77 }; 78 };
78 79
79 sysctl@01000 { 80 v2m_sysctl: sysctl@01000 {
80 compatible = "arm,sp810", "arm,primecell"; 81 compatible = "arm,sp810", "arm,primecell";
81 reg = <0x01000 0x1000>; 82 reg = <0x01000 0x1000>;
83 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
84 clock-names = "refclk", "timclk", "apb_pclk";
85 #clock-cells = <1>;
86 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
82 }; 87 };
83 88
84 /* PCI-E I2C bus */ 89 /* PCI-E I2C bus */
@@ -99,66 +104,92 @@
99 compatible = "arm,pl041", "arm,primecell"; 104 compatible = "arm,pl041", "arm,primecell";
100 reg = <0x04000 0x1000>; 105 reg = <0x04000 0x1000>;
101 interrupts = <11>; 106 interrupts = <11>;
107 clocks = <&smbclk>;
108 clock-names = "apb_pclk";
102 }; 109 };
103 110
104 mmci@05000 { 111 mmci@05000 {
105 compatible = "arm,pl180", "arm,primecell"; 112 compatible = "arm,pl180", "arm,primecell";
106 reg = <0x05000 0x1000>; 113 reg = <0x05000 0x1000>;
107 interrupts = <9 10>; 114 interrupts = <9 10>;
115 cd-gpios = <&v2m_sysreg 0 0>;
116 wp-gpios = <&v2m_sysreg 1 0>;
117 max-frequency = <12000000>;
118 vmmc-supply = <&v2m_fixed_3v3>;
119 clocks = <&v2m_clk24mhz>, <&smbclk>;
120 clock-names = "mclk", "apb_pclk";
108 }; 121 };
109 122
110 kmi@06000 { 123 kmi@06000 {
111 compatible = "arm,pl050", "arm,primecell"; 124 compatible = "arm,pl050", "arm,primecell";
112 reg = <0x06000 0x1000>; 125 reg = <0x06000 0x1000>;
113 interrupts = <12>; 126 interrupts = <12>;
127 clocks = <&v2m_clk24mhz>, <&smbclk>;
128 clock-names = "KMIREFCLK", "apb_pclk";
114 }; 129 };
115 130
116 kmi@07000 { 131 kmi@07000 {
117 compatible = "arm,pl050", "arm,primecell"; 132 compatible = "arm,pl050", "arm,primecell";
118 reg = <0x07000 0x1000>; 133 reg = <0x07000 0x1000>;
119 interrupts = <13>; 134 interrupts = <13>;
135 clocks = <&v2m_clk24mhz>, <&smbclk>;
136 clock-names = "KMIREFCLK", "apb_pclk";
120 }; 137 };
121 138
122 v2m_serial0: uart@09000 { 139 v2m_serial0: uart@09000 {
123 compatible = "arm,pl011", "arm,primecell"; 140 compatible = "arm,pl011", "arm,primecell";
124 reg = <0x09000 0x1000>; 141 reg = <0x09000 0x1000>;
125 interrupts = <5>; 142 interrupts = <5>;
143 clocks = <&v2m_oscclk2>, <&smbclk>;
144 clock-names = "uartclk", "apb_pclk";
126 }; 145 };
127 146
128 v2m_serial1: uart@0a000 { 147 v2m_serial1: uart@0a000 {
129 compatible = "arm,pl011", "arm,primecell"; 148 compatible = "arm,pl011", "arm,primecell";
130 reg = <0x0a000 0x1000>; 149 reg = <0x0a000 0x1000>;
131 interrupts = <6>; 150 interrupts = <6>;
151 clocks = <&v2m_oscclk2>, <&smbclk>;
152 clock-names = "uartclk", "apb_pclk";
132 }; 153 };
133 154
134 v2m_serial2: uart@0b000 { 155 v2m_serial2: uart@0b000 {
135 compatible = "arm,pl011", "arm,primecell"; 156 compatible = "arm,pl011", "arm,primecell";
136 reg = <0x0b000 0x1000>; 157 reg = <0x0b000 0x1000>;
137 interrupts = <7>; 158 interrupts = <7>;
159 clocks = <&v2m_oscclk2>, <&smbclk>;
160 clock-names = "uartclk", "apb_pclk";
138 }; 161 };
139 162
140 v2m_serial3: uart@0c000 { 163 v2m_serial3: uart@0c000 {
141 compatible = "arm,pl011", "arm,primecell"; 164 compatible = "arm,pl011", "arm,primecell";
142 reg = <0x0c000 0x1000>; 165 reg = <0x0c000 0x1000>;
143 interrupts = <8>; 166 interrupts = <8>;
167 clocks = <&v2m_oscclk2>, <&smbclk>;
168 clock-names = "uartclk", "apb_pclk";
144 }; 169 };
145 170
146 wdt@0f000 { 171 wdt@0f000 {
147 compatible = "arm,sp805", "arm,primecell"; 172 compatible = "arm,sp805", "arm,primecell";
148 reg = <0x0f000 0x1000>; 173 reg = <0x0f000 0x1000>;
149 interrupts = <0>; 174 interrupts = <0>;
175 clocks = <&v2m_refclk32khz>, <&smbclk>;
176 clock-names = "wdogclk", "apb_pclk";
150 }; 177 };
151 178
152 v2m_timer01: timer@11000 { 179 v2m_timer01: timer@11000 {
153 compatible = "arm,sp804", "arm,primecell"; 180 compatible = "arm,sp804", "arm,primecell";
154 reg = <0x11000 0x1000>; 181 reg = <0x11000 0x1000>;
155 interrupts = <2>; 182 interrupts = <2>;
183 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
184 clock-names = "timclken1", "timclken2", "apb_pclk";
156 }; 185 };
157 186
158 v2m_timer23: timer@12000 { 187 v2m_timer23: timer@12000 {
159 compatible = "arm,sp804", "arm,primecell"; 188 compatible = "arm,sp804", "arm,primecell";
160 reg = <0x12000 0x1000>; 189 reg = <0x12000 0x1000>;
161 interrupts = <3>; 190 interrupts = <3>;
191 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
192 clock-names = "timclken1", "timclken2", "apb_pclk";
162 }; 193 };
163 194
164 /* DVI I2C bus */ 195 /* DVI I2C bus */
@@ -184,6 +215,8 @@
184 compatible = "arm,pl031", "arm,primecell"; 215 compatible = "arm,pl031", "arm,primecell";
185 reg = <0x17000 0x1000>; 216 reg = <0x17000 0x1000>;
186 interrupts = <4>; 217 interrupts = <4>;
218 clocks = <&smbclk>;
219 clock-names = "apb_pclk";
187 }; 220 };
188 221
189 compact-flash@1a000 { 222 compact-flash@1a000 {
@@ -197,6 +230,8 @@
197 compatible = "arm,pl111", "arm,primecell"; 230 compatible = "arm,pl111", "arm,primecell";
198 reg = <0x1f000 0x1000>; 231 reg = <0x1f000 0x1000>;
199 interrupts = <14>; 232 interrupts = <14>;
233 clocks = <&v2m_oscclk1>, <&smbclk>;
234 clock-names = "clcdclk", "apb_pclk";
200 }; 235 };
201 }; 236 };
202 237
@@ -207,5 +242,98 @@
207 regulator-max-microvolt = <3300000>; 242 regulator-max-microvolt = <3300000>;
208 regulator-always-on; 243 regulator-always-on;
209 }; 244 };
245
246 v2m_clk24mhz: clk24mhz {
247 compatible = "fixed-clock";
248 #clock-cells = <0>;
249 clock-frequency = <24000000>;
250 clock-output-names = "v2m:clk24mhz";
251 };
252
253 v2m_refclk1mhz: refclk1mhz {
254 compatible = "fixed-clock";
255 #clock-cells = <0>;
256 clock-frequency = <1000000>;
257 clock-output-names = "v2m:refclk1mhz";
258 };
259
260 v2m_refclk32khz: refclk32khz {
261 compatible = "fixed-clock";
262 #clock-cells = <0>;
263 clock-frequency = <32768>;
264 clock-output-names = "v2m:refclk32khz";
265 };
266
267 mcc {
268 compatible = "arm,vexpress,config-bus";
269 arm,vexpress,config-bridge = <&v2m_sysreg>;
270
271 osc@0 {
272 /* MCC static memory clock */
273 compatible = "arm,vexpress-osc";
274 arm,vexpress-sysreg,func = <1 0>;
275 freq-range = <25000000 60000000>;
276 #clock-cells = <0>;
277 clock-output-names = "v2m:oscclk0";
278 };
279
280 v2m_oscclk1: osc@1 {
281 /* CLCD clock */
282 compatible = "arm,vexpress-osc";
283 arm,vexpress-sysreg,func = <1 1>;
284 freq-range = <23750000 63500000>;
285 #clock-cells = <0>;
286 clock-output-names = "v2m:oscclk1";
287 };
288
289 v2m_oscclk2: osc@2 {
290 /* IO FPGA peripheral clock */
291 compatible = "arm,vexpress-osc";
292 arm,vexpress-sysreg,func = <1 2>;
293 freq-range = <24000000 24000000>;
294 #clock-cells = <0>;
295 clock-output-names = "v2m:oscclk2";
296 };
297
298 volt@0 {
299 /* Logic level voltage */
300 compatible = "arm,vexpress-volt";
301 arm,vexpress-sysreg,func = <2 0>;
302 regulator-name = "VIO";
303 regulator-always-on;
304 label = "VIO";
305 };
306
307 temp@0 {
308 /* MCC internal operating temperature */
309 compatible = "arm,vexpress-temp";
310 arm,vexpress-sysreg,func = <4 0>;
311 label = "MCC";
312 };
313
314 reset@0 {
315 compatible = "arm,vexpress-reset";
316 arm,vexpress-sysreg,func = <5 0>;
317 };
318
319 muxfpga@0 {
320 compatible = "arm,vexpress-muxfpga";
321 arm,vexpress-sysreg,func = <7 0>;
322 };
323
324 shutdown@0 {
325 compatible = "arm,vexpress-shutdown";
326 arm,vexpress-sysreg,func = <8 0>;
327 };
328
329 reboot@0 {
330 compatible = "arm,vexpress-reboot";
331 arm,vexpress-sysreg,func = <9 0>;
332 };
333
334 dvimode@0 {
335 compatible = "arm,vexpress-dvimode";
336 arm,vexpress-sysreg,func = <11 0>;
337 };
338 };
210 }; 339 };
211};
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
index d12b34ca0568..a3d37ec2655d 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -12,6 +12,7 @@
12/ { 12/ {
13 model = "V2P-CA15"; 13 model = "V2P-CA15";
14 arm,hbi = <0x237>; 14 arm,hbi = <0x237>;
15 arm,vexpress,site = <0xf>;
15 compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress"; 16 compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
16 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
17 #address-cells = <2>; 18 #address-cells = <2>;
@@ -54,17 +55,24 @@
54 compatible = "arm,hdlcd"; 55 compatible = "arm,hdlcd";
55 reg = <0 0x2b000000 0 0x1000>; 56 reg = <0 0x2b000000 0 0x1000>;
56 interrupts = <0 85 4>; 57 interrupts = <0 85 4>;
58 clocks = <&oscclk5>;
59 clock-names = "pxlclk";
57 }; 60 };
58 61
59 memory-controller@2b0a0000 { 62 memory-controller@2b0a0000 {
60 compatible = "arm,pl341", "arm,primecell"; 63 compatible = "arm,pl341", "arm,primecell";
61 reg = <0 0x2b0a0000 0 0x1000>; 64 reg = <0 0x2b0a0000 0 0x1000>;
65 clocks = <&oscclk7>;
66 clock-names = "apb_pclk";
62 }; 67 };
63 68
64 wdt@2b060000 { 69 wdt@2b060000 {
65 compatible = "arm,sp805", "arm,primecell"; 70 compatible = "arm,sp805", "arm,primecell";
71 status = "disabled";
66 reg = <0 0x2b060000 0 0x1000>; 72 reg = <0 0x2b060000 0 0x1000>;
67 interrupts = <98>; 73 interrupts = <98>;
74 clocks = <&oscclk7>;
75 clock-names = "apb_pclk";
68 }; 76 };
69 77
70 gic: interrupt-controller@2c001000 { 78 gic: interrupt-controller@2c001000 {
@@ -84,6 +92,8 @@
84 reg = <0 0x7ffd0000 0 0x1000>; 92 reg = <0 0x7ffd0000 0 0x1000>;
85 interrupts = <0 86 4>, 93 interrupts = <0 86 4>,
86 <0 87 4>; 94 <0 87 4>;
95 clocks = <&oscclk7>;
96 clock-names = "apb_pclk";
87 }; 97 };
88 98
89 dma@7ffb0000 { 99 dma@7ffb0000 {
@@ -94,6 +104,8 @@
94 <0 89 4>, 104 <0 89 4>,
95 <0 90 4>, 105 <0 90 4>,
96 <0 91 4>; 106 <0 91 4>;
107 clocks = <&oscclk7>;
108 clock-names = "apb_pclk";
97 }; 109 };
98 110
99 timer { 111 timer {
@@ -110,7 +122,109 @@
110 <0 69 4>; 122 <0 69 4>;
111 }; 123 };
112 124
113 motherboard { 125 dcc {
126 compatible = "arm,vexpress,config-bus";
127 arm,vexpress,config-bridge = <&v2m_sysreg>;
128
129 osc@0 {
130 /* CPU PLL reference clock */
131 compatible = "arm,vexpress-osc";
132 arm,vexpress-sysreg,func = <1 0>;
133 freq-range = <50000000 60000000>;
134 #clock-cells = <0>;
135 clock-output-names = "oscclk0";
136 };
137
138 osc@4 {
139 /* Multiplexed AXI master clock */
140 compatible = "arm,vexpress-osc";
141 arm,vexpress-sysreg,func = <1 4>;
142 freq-range = <20000000 40000000>;
143 #clock-cells = <0>;
144 clock-output-names = "oscclk4";
145 };
146
147 oscclk5: osc@5 {
148 /* HDLCD PLL reference clock */
149 compatible = "arm,vexpress-osc";
150 arm,vexpress-sysreg,func = <1 5>;
151 freq-range = <23750000 165000000>;
152 #clock-cells = <0>;
153 clock-output-names = "oscclk5";
154 };
155
156 smbclk: osc@6 {
157 /* SMB clock */
158 compatible = "arm,vexpress-osc";
159 arm,vexpress-sysreg,func = <1 6>;
160 freq-range = <20000000 50000000>;
161 #clock-cells = <0>;
162 clock-output-names = "oscclk6";
163 };
164
165 oscclk7: osc@7 {
166 /* SYS PLL reference clock */
167 compatible = "arm,vexpress-osc";
168 arm,vexpress-sysreg,func = <1 7>;
169 freq-range = <20000000 60000000>;
170 #clock-cells = <0>;
171 clock-output-names = "oscclk7";
172 };
173
174 osc@8 {
175 /* DDR2 PLL reference clock */
176 compatible = "arm,vexpress-osc";
177 arm,vexpress-sysreg,func = <1 8>;
178 freq-range = <40000000 40000000>;
179 #clock-cells = <0>;
180 clock-output-names = "oscclk8";
181 };
182
183 volt@0 {
184 /* CPU core voltage */
185 compatible = "arm,vexpress-volt";
186 arm,vexpress-sysreg,func = <2 0>;
187 regulator-name = "Cores";
188 regulator-min-microvolt = <800000>;
189 regulator-max-microvolt = <1050000>;
190 regulator-always-on;
191 label = "Cores";
192 };
193
194 amp@0 {
195 /* Total current for the two cores */
196 compatible = "arm,vexpress-amp";
197 arm,vexpress-sysreg,func = <3 0>;
198 label = "Cores";
199 };
200
201 temp@0 {
202 /* DCC internal temperature */
203 compatible = "arm,vexpress-temp";
204 arm,vexpress-sysreg,func = <4 0>;
205 label = "DCC";
206 };
207
208 power@0 {
209 /* Total power */
210 compatible = "arm,vexpress-power";
211 arm,vexpress-sysreg,func = <12 0>;
212 label = "Cores";
213 };
214
215 energy@0 {
216 /* Total energy */
217 compatible = "arm,vexpress-energy";
218 arm,vexpress-sysreg,func = <13 0>;
219 label = "Cores";
220 };
221 };
222
223 smb {
224 compatible = "simple-bus";
225
226 #address-cells = <2>;
227 #size-cells = <1>;
114 ranges = <0 0 0 0x08000000 0x04000000>, 228 ranges = <0 0 0 0x08000000 0x04000000>,
115 <1 0 0 0x14000000 0x04000000>, 229 <1 0 0 0x14000000 0x04000000>,
116 <2 0 0 0x18000000 0x04000000>, 230 <2 0 0 0x18000000 0x04000000>,
@@ -118,6 +232,7 @@
118 <4 0 0 0x0c000000 0x04000000>, 232 <4 0 0 0x0c000000 0x04000000>,
119 <5 0 0 0x10000000 0x04000000>; 233 <5 0 0 0x10000000 0x04000000>;
120 234
235 #interrupt-cells = <1>;
121 interrupt-map-mask = <0 0 63>; 236 interrupt-map-mask = <0 0 63>;
122 interrupt-map = <0 0 0 &gic 0 0 4>, 237 interrupt-map = <0 0 0 &gic 0 0 4>,
123 <0 0 1 &gic 0 1 4>, 238 <0 0 1 &gic 0 1 4>,
@@ -162,7 +277,7 @@
162 <0 0 40 &gic 0 40 4>, 277 <0 0 40 &gic 0 40 4>,
163 <0 0 41 &gic 0 41 4>, 278 <0 0 41 &gic 0 41 4>,
164 <0 0 42 &gic 0 42 4>; 279 <0 0 42 &gic 0 42 4>;
280
281 /include/ "vexpress-v2m-rs1.dtsi"
165 }; 282 };
166}; 283};
167
168/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index 4890a81c5467..1fc405a9ecfb 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -12,6 +12,7 @@
12/ { 12/ {
13 model = "V2P-CA15_CA7"; 13 model = "V2P-CA15_CA7";
14 arm,hbi = <0x249>; 14 arm,hbi = <0x249>;
15 arm,vexpress,site = <0xf>;
15 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress"; 16 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
16 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
17 #address-cells = <2>; 18 #address-cells = <2>;
@@ -74,17 +75,23 @@
74 compatible = "arm,sp805", "arm,primecell"; 75 compatible = "arm,sp805", "arm,primecell";
75 reg = <0 0x2a490000 0 0x1000>; 76 reg = <0 0x2a490000 0 0x1000>;
76 interrupts = <98>; 77 interrupts = <98>;
78 clocks = <&oscclk6a>, <&oscclk6a>;
79 clock-names = "wdogclk", "apb_pclk";
77 }; 80 };
78 81
79 hdlcd@2b000000 { 82 hdlcd@2b000000 {
80 compatible = "arm,hdlcd"; 83 compatible = "arm,hdlcd";
81 reg = <0 0x2b000000 0 0x1000>; 84 reg = <0 0x2b000000 0 0x1000>;
82 interrupts = <0 85 4>; 85 interrupts = <0 85 4>;
86 clocks = <&oscclk5>;
87 clock-names = "pxlclk";
83 }; 88 };
84 89
85 memory-controller@2b0a0000 { 90 memory-controller@2b0a0000 {
86 compatible = "arm,pl341", "arm,primecell"; 91 compatible = "arm,pl341", "arm,primecell";
87 reg = <0 0x2b0a0000 0 0x1000>; 92 reg = <0 0x2b0a0000 0 0x1000>;
93 clocks = <&oscclk6a>;
94 clock-names = "apb_pclk";
88 }; 95 };
89 96
90 gic: interrupt-controller@2c001000 { 97 gic: interrupt-controller@2c001000 {
@@ -104,6 +111,8 @@
104 reg = <0 0x7ffd0000 0 0x1000>; 111 reg = <0 0x7ffd0000 0 0x1000>;
105 interrupts = <0 86 4>, 112 interrupts = <0 86 4>,
106 <0 87 4>; 113 <0 87 4>;
114 clocks = <&oscclk6a>;
115 clock-names = "apb_pclk";
107 }; 116 };
108 117
109 dma@7ff00000 { 118 dma@7ff00000 {
@@ -114,6 +123,8 @@
114 <0 89 4>, 123 <0 89 4>,
115 <0 90 4>, 124 <0 90 4>,
116 <0 91 4>; 125 <0 91 4>;
126 clocks = <&oscclk6a>;
127 clock-names = "apb_pclk";
117 }; 128 };
118 129
119 timer { 130 timer {
@@ -130,7 +141,175 @@
130 <0 69 4>; 141 <0 69 4>;
131 }; 142 };
132 143
133 motherboard { 144 oscclk6a: oscclk6a {
145 /* Reference 24MHz clock */
146 compatible = "fixed-clock";
147 #clock-cells = <0>;
148 clock-frequency = <24000000>;
149 clock-output-names = "oscclk6a";
150 };
151
152 dcc {
153 compatible = "arm,vexpress,config-bus";
154 arm,vexpress,config-bridge = <&v2m_sysreg>;
155
156 osc@0 {
157 /* A15 PLL 0 reference clock */
158 compatible = "arm,vexpress-osc";
159 arm,vexpress-sysreg,func = <1 0>;
160 freq-range = <17000000 50000000>;
161 #clock-cells = <0>;
162 clock-output-names = "oscclk0";
163 };
164
165 osc@1 {
166 /* A15 PLL 1 reference clock */
167 compatible = "arm,vexpress-osc";
168 arm,vexpress-sysreg,func = <1 1>;
169 freq-range = <17000000 50000000>;
170 #clock-cells = <0>;
171 clock-output-names = "oscclk1";
172 };
173
174 osc@2 {
175 /* A7 PLL 0 reference clock */
176 compatible = "arm,vexpress-osc";
177 arm,vexpress-sysreg,func = <1 2>;
178 freq-range = <17000000 50000000>;
179 #clock-cells = <0>;
180 clock-output-names = "oscclk2";
181 };
182
183 osc@3 {
184 /* A7 PLL 1 reference clock */
185 compatible = "arm,vexpress-osc";
186 arm,vexpress-sysreg,func = <1 3>;
187 freq-range = <17000000 50000000>;
188 #clock-cells = <0>;
189 clock-output-names = "oscclk3";
190 };
191
192 osc@4 {
193 /* External AXI master clock */
194 compatible = "arm,vexpress-osc";
195 arm,vexpress-sysreg,func = <1 4>;
196 freq-range = <20000000 40000000>;
197 #clock-cells = <0>;
198 clock-output-names = "oscclk4";
199 };
200
201 oscclk5: osc@5 {
202 /* HDLCD PLL reference clock */
203 compatible = "arm,vexpress-osc";
204 arm,vexpress-sysreg,func = <1 5>;
205 freq-range = <23750000 165000000>;
206 #clock-cells = <0>;
207 clock-output-names = "oscclk5";
208 };
209
210 smbclk: osc@6 {
211 /* Static memory controller clock */
212 compatible = "arm,vexpress-osc";
213 arm,vexpress-sysreg,func = <1 6>;
214 freq-range = <20000000 40000000>;
215 #clock-cells = <0>;
216 clock-output-names = "oscclk6";
217 };
218
219 osc@7 {
220 /* SYS PLL reference clock */
221 compatible = "arm,vexpress-osc";
222 arm,vexpress-sysreg,func = <1 7>;
223 freq-range = <17000000 50000000>;
224 #clock-cells = <0>;
225 clock-output-names = "oscclk7";
226 };
227
228 osc@8 {
229 /* DDR2 PLL reference clock */
230 compatible = "arm,vexpress-osc";
231 arm,vexpress-sysreg,func = <1 8>;
232 freq-range = <20000000 50000000>;
233 #clock-cells = <0>;
234 clock-output-names = "oscclk8";
235 };
236
237 volt@0 {
238 /* A15 CPU core voltage */
239 compatible = "arm,vexpress-volt";
240 arm,vexpress-sysreg,func = <2 0>;
241 regulator-name = "A15 Vcore";
242 regulator-min-microvolt = <800000>;
243 regulator-max-microvolt = <1050000>;
244 regulator-always-on;
245 label = "A15 Vcore";
246 };
247
248 volt@1 {
249 /* A7 CPU core voltage */
250 compatible = "arm,vexpress-volt";
251 arm,vexpress-sysreg,func = <2 1>;
252 regulator-name = "A7 Vcore";
253 regulator-min-microvolt = <800000>;
254 regulator-max-microvolt = <1050000>;
255 regulator-always-on;
256 label = "A7 Vcore";
257 };
258
259 amp@0 {
260 /* Total current for the two A15 cores */
261 compatible = "arm,vexpress-amp";
262 arm,vexpress-sysreg,func = <3 0>;
263 label = "A15 Icore";
264 };
265
266 amp@1 {
267 /* Total current for the three A7 cores */
268 compatible = "arm,vexpress-amp";
269 arm,vexpress-sysreg,func = <3 1>;
270 label = "A7 Icore";
271 };
272
273 temp@0 {
274 /* DCC internal temperature */
275 compatible = "arm,vexpress-temp";
276 arm,vexpress-sysreg,func = <4 0>;
277 label = "DCC";
278 };
279
280 power@0 {
281 /* Total power for the two A15 cores */
282 compatible = "arm,vexpress-power";
283 arm,vexpress-sysreg,func = <12 0>;
284 label = "A15 Pcore";
285 };
286 power@1 {
287 /* Total power for the three A7 cores */
288 compatible = "arm,vexpress-power";
289 arm,vexpress-sysreg,func = <12 1>;
290 label = "A7 Pcore";
291 };
292
293 energy@0 {
294 /* Total energy for the two A15 cores */
295 compatible = "arm,vexpress-energy";
296 arm,vexpress-sysreg,func = <13 0>;
297 label = "A15 Jcore";
298 };
299
300 energy@2 {
301 /* Total energy for the three A7 cores */
302 compatible = "arm,vexpress-energy";
303 arm,vexpress-sysreg,func = <13 2>;
304 label = "A7 Jcore";
305 };
306 };
307
308 smb {
309 compatible = "simple-bus";
310
311 #address-cells = <2>;
312 #size-cells = <1>;
134 ranges = <0 0 0 0x08000000 0x04000000>, 313 ranges = <0 0 0 0x08000000 0x04000000>,
135 <1 0 0 0x14000000 0x04000000>, 314 <1 0 0 0x14000000 0x04000000>,
136 <2 0 0 0x18000000 0x04000000>, 315 <2 0 0 0x18000000 0x04000000>,
@@ -138,6 +317,7 @@
138 <4 0 0 0x0c000000 0x04000000>, 317 <4 0 0 0x0c000000 0x04000000>,
139 <5 0 0 0x10000000 0x04000000>; 318 <5 0 0 0x10000000 0x04000000>;
140 319
320 #interrupt-cells = <1>;
141 interrupt-map-mask = <0 0 63>; 321 interrupt-map-mask = <0 0 63>;
142 interrupt-map = <0 0 0 &gic 0 0 4>, 322 interrupt-map = <0 0 0 &gic 0 0 4>,
143 <0 0 1 &gic 0 1 4>, 323 <0 0 1 &gic 0 1 4>,
@@ -182,7 +362,7 @@
182 <0 0 40 &gic 0 40 4>, 362 <0 0 40 &gic 0 40 4>,
183 <0 0 41 &gic 0 41 4>, 363 <0 0 41 &gic 0 41 4>,
184 <0 0 42 &gic 0 42 4>; 364 <0 0 42 &gic 0 42 4>;
365
366 /include/ "vexpress-v2m-rs1.dtsi"
185 }; 367 };
186}; 368};
187
188/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
index 18917a0f8604..6328cbc71d30 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -12,6 +12,7 @@
12/ { 12/ {
13 model = "V2P-CA5s"; 13 model = "V2P-CA5s";
14 arm,hbi = <0x225>; 14 arm,hbi = <0x225>;
15 arm,vexpress,site = <0xf>;
15 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; 16 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
16 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
17 #address-cells = <1>; 18 #address-cells = <1>;
@@ -56,11 +57,15 @@
56 compatible = "arm,hdlcd"; 57 compatible = "arm,hdlcd";
57 reg = <0x2a110000 0x1000>; 58 reg = <0x2a110000 0x1000>;
58 interrupts = <0 85 4>; 59 interrupts = <0 85 4>;
60 clocks = <&oscclk3>;
61 clock-names = "pxlclk";
59 }; 62 };
60 63
61 memory-controller@2a150000 { 64 memory-controller@2a150000 {
62 compatible = "arm,pl341", "arm,primecell"; 65 compatible = "arm,pl341", "arm,primecell";
63 reg = <0x2a150000 0x1000>; 66 reg = <0x2a150000 0x1000>;
67 clocks = <&oscclk1>;
68 clock-names = "apb_pclk";
64 }; 69 };
65 70
66 memory-controller@2a190000 { 71 memory-controller@2a190000 {
@@ -68,6 +73,8 @@
68 reg = <0x2a190000 0x1000>; 73 reg = <0x2a190000 0x1000>;
69 interrupts = <0 86 4>, 74 interrupts = <0 86 4>,
70 <0 87 4>; 75 <0 87 4>;
76 clocks = <&oscclk1>;
77 clock-names = "apb_pclk";
71 }; 78 };
72 79
73 scu@2c000000 { 80 scu@2c000000 {
@@ -109,7 +116,77 @@
109 <0 69 4>; 116 <0 69 4>;
110 }; 117 };
111 118
112 motherboard { 119 dcc {
120 compatible = "arm,vexpress,config-bus";
121 arm,vexpress,config-bridge = <&v2m_sysreg>;
122
123 osc@0 {
124 /* CPU and internal AXI reference clock */
125 compatible = "arm,vexpress-osc";
126 arm,vexpress-sysreg,func = <1 0>;
127 freq-range = <50000000 100000000>;
128 #clock-cells = <0>;
129 clock-output-names = "oscclk0";
130 };
131
132 oscclk1: osc@1 {
133 /* Multiplexed AXI master clock */
134 compatible = "arm,vexpress-osc";
135 arm,vexpress-sysreg,func = <1 1>;
136 freq-range = <5000000 50000000>;
137 #clock-cells = <0>;
138 clock-output-names = "oscclk1";
139 };
140
141 osc@2 {
142 /* DDR2 */
143 compatible = "arm,vexpress-osc";
144 arm,vexpress-sysreg,func = <1 2>;
145 freq-range = <80000000 120000000>;
146 #clock-cells = <0>;
147 clock-output-names = "oscclk2";
148 };
149
150 oscclk3: osc@3 {
151 /* HDLCD */
152 compatible = "arm,vexpress-osc";
153 arm,vexpress-sysreg,func = <1 3>;
154 freq-range = <23750000 165000000>;
155 #clock-cells = <0>;
156 clock-output-names = "oscclk3";
157 };
158
159 osc@4 {
160 /* Test chip gate configuration */
161 compatible = "arm,vexpress-osc";
162 arm,vexpress-sysreg,func = <1 4>;
163 freq-range = <80000000 80000000>;
164 #clock-cells = <0>;
165 clock-output-names = "oscclk4";
166 };
167
168 smbclk: osc@5 {
169 /* SMB clock */
170 compatible = "arm,vexpress-osc";
171 arm,vexpress-sysreg,func = <1 5>;
172 freq-range = <25000000 60000000>;
173 #clock-cells = <0>;
174 clock-output-names = "oscclk5";
175 };
176
177 temp@0 {
178 /* DCC internal operating temperature */
179 compatible = "arm,vexpress-temp";
180 arm,vexpress-sysreg,func = <4 0>;
181 label = "DCC";
182 };
183 };
184
185 smb {
186 compatible = "simple-bus";
187
188 #address-cells = <2>;
189 #size-cells = <1>;
113 ranges = <0 0 0x08000000 0x04000000>, 190 ranges = <0 0 0x08000000 0x04000000>,
114 <1 0 0x14000000 0x04000000>, 191 <1 0 0x14000000 0x04000000>,
115 <2 0 0x18000000 0x04000000>, 192 <2 0 0x18000000 0x04000000>,
@@ -117,6 +194,7 @@
117 <4 0 0x0c000000 0x04000000>, 194 <4 0 0x0c000000 0x04000000>,
118 <5 0 0x10000000 0x04000000>; 195 <5 0 0x10000000 0x04000000>;
119 196
197 #interrupt-cells = <1>;
120 interrupt-map-mask = <0 0 63>; 198 interrupt-map-mask = <0 0 63>;
121 interrupt-map = <0 0 0 &gic 0 0 4>, 199 interrupt-map = <0 0 0 &gic 0 0 4>,
122 <0 0 1 &gic 0 1 4>, 200 <0 0 1 &gic 0 1 4>,
@@ -161,7 +239,7 @@
161 <0 0 40 &gic 0 40 4>, 239 <0 0 40 &gic 0 40 4>,
162 <0 0 41 &gic 0 41 4>, 240 <0 0 41 &gic 0 41 4>,
163 <0 0 42 &gic 0 42 4>; 241 <0 0 42 &gic 0 42 4>;
242
243 /include/ "vexpress-v2m-rs1.dtsi"
164 }; 244 };
165}; 245};
166
167/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
index 3f0c736d31d6..1420bb14d95c 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -12,6 +12,7 @@
12/ { 12/ {
13 model = "V2P-CA9"; 13 model = "V2P-CA9";
14 arm,hbi = <0x191>; 14 arm,hbi = <0x191>;
15 arm,vexpress,site = <0xf>;
15 compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; 16 compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
16 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
17 #address-cells = <1>; 18 #address-cells = <1>;
@@ -70,11 +71,15 @@
70 compatible = "arm,pl111", "arm,primecell"; 71 compatible = "arm,pl111", "arm,primecell";
71 reg = <0x10020000 0x1000>; 72 reg = <0x10020000 0x1000>;
72 interrupts = <0 44 4>; 73 interrupts = <0 44 4>;
74 clocks = <&oscclk1>, <&oscclk2>;
75 clock-names = "clcdclk", "apb_pclk";
73 }; 76 };
74 77
75 memory-controller@100e0000 { 78 memory-controller@100e0000 {
76 compatible = "arm,pl341", "arm,primecell"; 79 compatible = "arm,pl341", "arm,primecell";
77 reg = <0x100e0000 0x1000>; 80 reg = <0x100e0000 0x1000>;
81 clocks = <&oscclk2>;
82 clock-names = "apb_pclk";
78 }; 83 };
79 84
80 memory-controller@100e1000 { 85 memory-controller@100e1000 {
@@ -82,6 +87,8 @@
82 reg = <0x100e1000 0x1000>; 87 reg = <0x100e1000 0x1000>;
83 interrupts = <0 45 4>, 88 interrupts = <0 45 4>,
84 <0 46 4>; 89 <0 46 4>;
90 clocks = <&oscclk2>;
91 clock-names = "apb_pclk";
85 }; 92 };
86 93
87 timer@100e4000 { 94 timer@100e4000 {
@@ -89,12 +96,16 @@
89 reg = <0x100e4000 0x1000>; 96 reg = <0x100e4000 0x1000>;
90 interrupts = <0 48 4>, 97 interrupts = <0 48 4>,
91 <0 49 4>; 98 <0 49 4>;
99 clocks = <&oscclk2>, <&oscclk2>;
100 clock-names = "timclk", "apb_pclk";
92 }; 101 };
93 102
94 watchdog@100e5000 { 103 watchdog@100e5000 {
95 compatible = "arm,sp805", "arm,primecell"; 104 compatible = "arm,sp805", "arm,primecell";
96 reg = <0x100e5000 0x1000>; 105 reg = <0x100e5000 0x1000>;
97 interrupts = <0 51 4>; 106 interrupts = <0 51 4>;
107 clocks = <&oscclk2>, <&oscclk2>;
108 clock-names = "wdogclk", "apb_pclk";
98 }; 109 };
99 110
100 scu@1e000000 { 111 scu@1e000000 {
@@ -140,13 +151,132 @@
140 <0 63 4>; 151 <0 63 4>;
141 }; 152 };
142 153
143 motherboard { 154 dcc {
155 compatible = "arm,vexpress,config-bus";
156 arm,vexpress,config-bridge = <&v2m_sysreg>;
157
158 osc@0 {
159 /* ACLK clock to the AXI master port on the test chip */
160 compatible = "arm,vexpress-osc";
161 arm,vexpress-sysreg,func = <1 0>;
162 freq-range = <30000000 50000000>;
163 #clock-cells = <0>;
164 clock-output-names = "extsaxiclk";
165 };
166
167 oscclk1: osc@1 {
168 /* Reference clock for the CLCD */
169 compatible = "arm,vexpress-osc";
170 arm,vexpress-sysreg,func = <1 1>;
171 freq-range = <10000000 80000000>;
172 #clock-cells = <0>;
173 clock-output-names = "clcdclk";
174 };
175
176 smbclk: oscclk2: osc@2 {
177 /* Reference clock for the test chip internal PLLs */
178 compatible = "arm,vexpress-osc";
179 arm,vexpress-sysreg,func = <1 2>;
180 freq-range = <33000000 100000000>;
181 #clock-cells = <0>;
182 clock-output-names = "tcrefclk";
183 };
184
185 volt@0 {
186 /* Test Chip internal logic voltage */
187 compatible = "arm,vexpress-volt";
188 arm,vexpress-sysreg,func = <2 0>;
189 regulator-name = "VD10";
190 regulator-always-on;
191 label = "VD10";
192 };
193
194 volt@1 {
195 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
196 compatible = "arm,vexpress-volt";
197 arm,vexpress-sysreg,func = <2 1>;
198 regulator-name = "VD10_S2";
199 regulator-always-on;
200 label = "VD10_S2";
201 };
202
203 volt@2 {
204 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
205 compatible = "arm,vexpress-volt";
206 arm,vexpress-sysreg,func = <2 2>;
207 regulator-name = "VD10_S3";
208 regulator-always-on;
209 label = "VD10_S3";
210 };
211
212 volt@3 {
213 /* DDR2 SDRAM and Test Chip DDR2 I/O supply */
214 compatible = "arm,vexpress-volt";
215 arm,vexpress-sysreg,func = <2 3>;
216 regulator-name = "VCC1V8";
217 regulator-always-on;
218 label = "VCC1V8";
219 };
220
221 volt@4 {
222 /* DDR2 SDRAM VTT termination voltage */
223 compatible = "arm,vexpress-volt";
224 arm,vexpress-sysreg,func = <2 4>;
225 regulator-name = "DDR2VTT";
226 regulator-always-on;
227 label = "DDR2VTT";
228 };
229
230 volt@5 {
231 /* Local board supply for miscellaneous logic external to the Test Chip */
232 arm,vexpress-sysreg,func = <2 5>;
233 compatible = "arm,vexpress-volt";
234 regulator-name = "VCC3V3";
235 regulator-always-on;
236 label = "VCC3V3";
237 };
238
239 amp@0 {
240 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
241 compatible = "arm,vexpress-amp";
242 arm,vexpress-sysreg,func = <3 0>;
243 label = "VD10_S2";
244 };
245
246 amp@1 {
247 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
248 compatible = "arm,vexpress-amp";
249 arm,vexpress-sysreg,func = <3 1>;
250 label = "VD10_S3";
251 };
252
253 power@0 {
254 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
255 compatible = "arm,vexpress-power";
256 arm,vexpress-sysreg,func = <12 0>;
257 label = "PVD10_S2";
258 };
259
260 power@1 {
261 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
262 compatible = "arm,vexpress-power";
263 arm,vexpress-sysreg,func = <12 1>;
264 label = "PVD10_S3";
265 };
266 };
267
268 smb {
269 compatible = "simple-bus";
270
271 #address-cells = <2>;
272 #size-cells = <1>;
144 ranges = <0 0 0x40000000 0x04000000>, 273 ranges = <0 0 0x40000000 0x04000000>,
145 <1 0 0x44000000 0x04000000>, 274 <1 0 0x44000000 0x04000000>,
146 <2 0 0x48000000 0x04000000>, 275 <2 0 0x48000000 0x04000000>,
147 <3 0 0x4c000000 0x04000000>, 276 <3 0 0x4c000000 0x04000000>,
148 <7 0 0x10000000 0x00020000>; 277 <7 0 0x10000000 0x00020000>;
149 278
279 #interrupt-cells = <1>;
150 interrupt-map-mask = <0 0 63>; 280 interrupt-map-mask = <0 0 63>;
151 interrupt-map = <0 0 0 &gic 0 0 4>, 281 interrupt-map = <0 0 0 &gic 0 0 4>,
152 <0 0 1 &gic 0 1 4>, 282 <0 0 1 &gic 0 1 4>,
@@ -191,7 +321,7 @@
191 <0 0 40 &gic 0 40 4>, 321 <0 0 40 &gic 0 40 4>,
192 <0 0 41 &gic 0 41 4>, 322 <0 0 41 &gic 0 41 4>,
193 <0 0 42 &gic 0 42 4>; 323 <0 0 42 &gic 0 42 4>;
324
325 /include/ "vexpress-v2m.dtsi"
194 }; 326 };
195}; 327};
196
197/include/ "vexpress-v2m.dtsi"
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
new file mode 100644
index 000000000000..401c1262d4ed
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -0,0 +1,166 @@
1/*
2 * Copyright (C) 2011 Xilinx
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13/include/ "skeleton.dtsi"
14
15/ {
16 compatible = "xlnx,zynq-7000";
17
18 amba {
19 compatible = "simple-bus";
20 #address-cells = <1>;
21 #size-cells = <1>;
22 interrupt-parent = <&intc>;
23 ranges;
24
25 intc: interrupt-controller@f8f01000 {
26 compatible = "arm,cortex-a9-gic";
27 #interrupt-cells = <3>;
28 #address-cells = <1>;
29 interrupt-controller;
30 reg = <0xF8F01000 0x1000>,
31 <0xF8F00100 0x100>;
32 };
33
34 L2: cache-controller {
35 compatible = "arm,pl310-cache";
36 reg = <0xF8F02000 0x1000>;
37 arm,data-latency = <2 3 2>;
38 arm,tag-latency = <2 3 2>;
39 cache-unified;
40 cache-level = <2>;
41 };
42
43 uart0: uart@e0000000 {
44 compatible = "xlnx,xuartps";
45 reg = <0xE0000000 0x1000>;
46 interrupts = <0 27 4>;
47 clock = <50000000>;
48 };
49
50 uart1: uart@e0001000 {
51 compatible = "xlnx,xuartps";
52 reg = <0xE0001000 0x1000>;
53 interrupts = <0 50 4>;
54 clock = <50000000>;
55 };
56
57 slcr: slcr@f8000000 {
58 compatible = "xlnx,zynq-slcr";
59 reg = <0xF8000000 0x1000>;
60
61 clocks {
62 #address-cells = <1>;
63 #size-cells = <0>;
64
65 ps_clk: ps_clk {
66 #clock-cells = <0>;
67 compatible = "fixed-clock";
68 /* clock-frequency set in board-specific file */
69 clock-output-names = "ps_clk";
70 };
71 armpll: armpll {
72 #clock-cells = <0>;
73 compatible = "xlnx,zynq-pll";
74 clocks = <&ps_clk>;
75 reg = <0x100 0x110>;
76 clock-output-names = "armpll";
77 };
78 ddrpll: ddrpll {
79 #clock-cells = <0>;
80 compatible = "xlnx,zynq-pll";
81 clocks = <&ps_clk>;
82 reg = <0x104 0x114>;
83 clock-output-names = "ddrpll";
84 };
85 iopll: iopll {
86 #clock-cells = <0>;
87 compatible = "xlnx,zynq-pll";
88 clocks = <&ps_clk>;
89 reg = <0x108 0x118>;
90 clock-output-names = "iopll";
91 };
92 uart_clk: uart_clk {
93 #clock-cells = <1>;
94 compatible = "xlnx,zynq-periph-clock";
95 clocks = <&iopll &armpll &ddrpll>;
96 reg = <0x154>;
97 clock-output-names = "uart0_ref_clk",
98 "uart1_ref_clk";
99 };
100 cpu_clk: cpu_clk {
101 #clock-cells = <1>;
102 compatible = "xlnx,zynq-cpu-clock";
103 clocks = <&iopll &armpll &ddrpll>;
104 reg = <0x120 0x1C4>;
105 clock-output-names = "cpu_6x4x",
106 "cpu_3x2x",
107 "cpu_2x",
108 "cpu_1x";
109 };
110 };
111 };
112
113 ttc0: ttc0@f8001000 {
114 #address-cells = <1>;
115 #size-cells = <0>;
116 compatible = "xlnx,ttc";
117 reg = <0xF8001000 0x1000>;
118 clocks = <&cpu_clk 3>;
119 clock-names = "cpu_1x";
120 clock-ranges;
121
122 ttc0_0: ttc0.0 {
123 status = "disabled";
124 reg = <0>;
125 interrupts = <0 10 4>;
126 };
127 ttc0_1: ttc0.1 {
128 status = "disabled";
129 reg = <1>;
130 interrupts = <0 11 4>;
131 };
132 ttc0_2: ttc0.2 {
133 status = "disabled";
134 reg = <2>;
135 interrupts = <0 12 4>;
136 };
137 };
138
139 ttc1: ttc1@f8002000 {
140 #interrupt-parent = <&intc>;
141 #address-cells = <1>;
142 #size-cells = <0>;
143 compatible = "xlnx,ttc";
144 reg = <0xF8002000 0x1000>;
145 clocks = <&cpu_clk 3>;
146 clock-names = "cpu_1x";
147 clock-ranges;
148
149 ttc1_0: ttc1.0 {
150 status = "disabled";
151 reg = <0>;
152 interrupts = <0 37 4>;
153 };
154 ttc1_1: ttc1.1 {
155 status = "disabled";
156 reg = <1>;
157 interrupts = <0 38 4>;
158 };
159 ttc1_2: ttc1.2 {
160 status = "disabled";
161 reg = <2>;
162 interrupts = <0 39 4>;
163 };
164 };
165 };
166};
diff --git a/arch/arm/boot/dts/zynq-ep107.dts b/arch/arm/boot/dts/zynq-ep107.dts
deleted file mode 100644
index 37ca192fb193..000000000000
--- a/arch/arm/boot/dts/zynq-ep107.dts
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * Copyright (C) 2011 Xilinx
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14/dts-v1/;
15/ {
16 model = "Xilinx Zynq EP107";
17 compatible = "xlnx,zynq-ep107";
18 #address-cells = <1>;
19 #size-cells = <1>;
20 interrupt-parent = <&intc>;
21
22 memory {
23 device_type = "memory";
24 reg = <0x0 0x10000000>;
25 };
26
27 chosen {
28 bootargs = "console=ttyPS0,9600 root=/dev/ram rw initrd=0x800000,8M earlyprintk";
29 linux,stdout-path = &uart0;
30 };
31
32 amba {
33 compatible = "simple-bus";
34 #address-cells = <1>;
35 #size-cells = <1>;
36 ranges;
37
38 intc: interrupt-controller@f8f01000 {
39 interrupt-controller;
40 compatible = "arm,gic";
41 reg = <0xF8F01000 0x1000>;
42 #interrupt-cells = <2>;
43 };
44
45 uart0: uart@e0000000 {
46 compatible = "xlnx,xuartps";
47 reg = <0xE0000000 0x1000>;
48 interrupts = <59 0>;
49 clock = <50000000>;
50 };
51 };
52};
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
new file mode 100644
index 000000000000..c772942a399a
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -0,0 +1,44 @@
1/*
2 * Copyright (C) 2011 Xilinx
3 * Copyright (C) 2012 National Instruments Corp.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14/dts-v1/;
15/include/ "zynq-7000.dtsi"
16
17/ {
18 model = "Zynq ZC702 Development Board";
19 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
20
21 memory {
22 device_type = "memory";
23 reg = <0x0 0x40000000>;
24 };
25
26 chosen {
27 bootargs = "console=ttyPS1,115200 earlyprintk";
28 };
29
30};
31
32&ps_clk {
33 clock-frequency = <33333330>;
34};
35
36&ttc0_0 {
37 status = "ok";
38 compatible = "xlnx,ttc-counter-clocksource";
39};
40
41&ttc0_1 {
42 status = "ok";
43 compatible = "xlnx,ttc-counter-clockevent";
44};
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-08 18:49:50 -0500