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-rw-r--r--arch/arm/boot/dts/imx51.dtsi171
1 files changed, 149 insertions, 22 deletions
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 75d069fcf897..1f5d45eff45e 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -62,6 +62,13 @@
62 interrupt-parent = <&tzic>; 62 interrupt-parent = <&tzic>;
63 ranges; 63 ranges;
64 64
65 ipu: ipu@40000000 {
66 #crtc-cells = <1>;
67 compatible = "fsl,imx51-ipu";
68 reg = <0x40000000 0x20000000>;
69 interrupts = <11 10>;
70 };
71
65 aips@70000000 { /* AIPS1 */ 72 aips@70000000 { /* AIPS1 */
66 compatible = "fsl,aips-bus", "simple-bus"; 73 compatible = "fsl,aips-bus", "simple-bus";
67 #address-cells = <1>; 74 #address-cells = <1>;
@@ -76,17 +83,22 @@
76 reg = <0x70000000 0x40000>; 83 reg = <0x70000000 0x40000>;
77 ranges; 84 ranges;
78 85
79 esdhc@70004000 { /* ESDHC1 */ 86 esdhc1: esdhc@70004000 {
80 compatible = "fsl,imx51-esdhc"; 87 compatible = "fsl,imx51-esdhc";
81 reg = <0x70004000 0x4000>; 88 reg = <0x70004000 0x4000>;
82 interrupts = <1>; 89 interrupts = <1>;
90 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
91 clock-names = "ipg", "ahb", "per";
83 status = "disabled"; 92 status = "disabled";
84 }; 93 };
85 94
86 esdhc@70008000 { /* ESDHC2 */ 95 esdhc2: esdhc@70008000 {
87 compatible = "fsl,imx51-esdhc"; 96 compatible = "fsl,imx51-esdhc";
88 reg = <0x70008000 0x4000>; 97 reg = <0x70008000 0x4000>;
89 interrupts = <2>; 98 interrupts = <2>;
99 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
100 clock-names = "ipg", "ahb", "per";
101 bus-width = <4>;
90 status = "disabled"; 102 status = "disabled";
91 }; 103 };
92 104
@@ -94,15 +106,19 @@
94 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 106 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
95 reg = <0x7000c000 0x4000>; 107 reg = <0x7000c000 0x4000>;
96 interrupts = <33>; 108 interrupts = <33>;
109 clocks = <&clks 32>, <&clks 33>;
110 clock-names = "ipg", "per";
97 status = "disabled"; 111 status = "disabled";
98 }; 112 };
99 113
100 ecspi@70010000 { /* ECSPI1 */ 114 ecspi1: ecspi@70010000 {
101 #address-cells = <1>; 115 #address-cells = <1>;
102 #size-cells = <0>; 116 #size-cells = <0>;
103 compatible = "fsl,imx51-ecspi"; 117 compatible = "fsl,imx51-ecspi";
104 reg = <0x70010000 0x4000>; 118 reg = <0x70010000 0x4000>;
105 interrupts = <36>; 119 interrupts = <36>;
120 clocks = <&clks 51>, <&clks 52>;
121 clock-names = "ipg", "per";
106 status = "disabled"; 122 status = "disabled";
107 }; 123 };
108 124
@@ -110,48 +126,55 @@
110 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 126 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
111 reg = <0x70014000 0x4000>; 127 reg = <0x70014000 0x4000>;
112 interrupts = <30>; 128 interrupts = <30>;
129 clocks = <&clks 49>;
113 fsl,fifo-depth = <15>; 130 fsl,fifo-depth = <15>;
114 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ 131 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
115 status = "disabled"; 132 status = "disabled";
116 }; 133 };
117 134
118 esdhc@70020000 { /* ESDHC3 */ 135 esdhc3: esdhc@70020000 {
119 compatible = "fsl,imx51-esdhc"; 136 compatible = "fsl,imx51-esdhc";
120 reg = <0x70020000 0x4000>; 137 reg = <0x70020000 0x4000>;
121 interrupts = <3>; 138 interrupts = <3>;
139 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
140 clock-names = "ipg", "ahb", "per";
141 bus-width = <4>;
122 status = "disabled"; 142 status = "disabled";
123 }; 143 };
124 144
125 esdhc@70024000 { /* ESDHC4 */ 145 esdhc4: esdhc@70024000 {
126 compatible = "fsl,imx51-esdhc"; 146 compatible = "fsl,imx51-esdhc";
127 reg = <0x70024000 0x4000>; 147 reg = <0x70024000 0x4000>;
128 interrupts = <4>; 148 interrupts = <4>;
149 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
150 clock-names = "ipg", "ahb", "per";
151 bus-width = <4>;
129 status = "disabled"; 152 status = "disabled";
130 }; 153 };
131 }; 154 };
132 155
133 usb@73f80000 { 156 usbotg: usb@73f80000 {
134 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 157 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
135 reg = <0x73f80000 0x0200>; 158 reg = <0x73f80000 0x0200>;
136 interrupts = <18>; 159 interrupts = <18>;
137 status = "disabled"; 160 status = "disabled";
138 }; 161 };
139 162
140 usb@73f80200 { 163 usbh1: usb@73f80200 {
141 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 164 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
142 reg = <0x73f80200 0x0200>; 165 reg = <0x73f80200 0x0200>;
143 interrupts = <14>; 166 interrupts = <14>;
144 status = "disabled"; 167 status = "disabled";
145 }; 168 };
146 169
147 usb@73f80400 { 170 usbh2: usb@73f80400 {
148 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 171 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
149 reg = <0x73f80400 0x0200>; 172 reg = <0x73f80400 0x0200>;
150 interrupts = <16>; 173 interrupts = <16>;
151 status = "disabled"; 174 status = "disabled";
152 }; 175 };
153 176
154 usb@73f80600 { 177 usbh3: usb@73f80600 {
155 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 178 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
156 reg = <0x73f80600 0x0200>; 179 reg = <0x73f80600 0x0200>;
157 interrupts = <17>; 180 interrupts = <17>;
@@ -198,20 +221,22 @@
198 #interrupt-cells = <2>; 221 #interrupt-cells = <2>;
199 }; 222 };
200 223
201 wdog@73f98000 { /* WDOG1 */ 224 wdog1: wdog@73f98000 {
202 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 225 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
203 reg = <0x73f98000 0x4000>; 226 reg = <0x73f98000 0x4000>;
204 interrupts = <58>; 227 interrupts = <58>;
228 clocks = <&clks 0>;
205 }; 229 };
206 230
207 wdog@73f9c000 { /* WDOG2 */ 231 wdog2: wdog@73f9c000 {
208 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 232 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
209 reg = <0x73f9c000 0x4000>; 233 reg = <0x73f9c000 0x4000>;
210 interrupts = <59>; 234 interrupts = <59>;
235 clocks = <&clks 0>;
211 status = "disabled"; 236 status = "disabled";
212 }; 237 };
213 238
214 iomuxc@73fa8000 { 239 iomuxc: iomuxc@73fa8000 {
215 compatible = "fsl,imx51-iomuxc"; 240 compatible = "fsl,imx51-iomuxc";
216 reg = <0x73fa8000 0x4000>; 241 reg = <0x73fa8000 0x4000>;
217 242
@@ -295,6 +320,66 @@
295 }; 320 };
296 }; 321 };
297 322
323 ipu_disp1 {
324 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
325 fsl,pins = <
326 528 0x5 /* MX51_PAD_DISP1_DAT0__DISP1_DAT0 */
327 529 0x5 /* MX51_PAD_DISP1_DAT1__DISP1_DAT1 */
328 530 0x5 /* MX51_PAD_DISP1_DAT2__DISP1_DAT2 */
329 531 0x5 /* MX51_PAD_DISP1_DAT3__DISP1_DAT3 */
330 532 0x5 /* MX51_PAD_DISP1_DAT4__DISP1_DAT4 */
331 533 0x5 /* MX51_PAD_DISP1_DAT5__DISP1_DAT5 */
332 535 0x5 /* MX51_PAD_DISP1_DAT6__DISP1_DAT6 */
333 537 0x5 /* MX51_PAD_DISP1_DAT7__DISP1_DAT7 */
334 539 0x5 /* MX51_PAD_DISP1_DAT8__DISP1_DAT8 */
335 541 0x5 /* MX51_PAD_DISP1_DAT9__DISP1_DAT9 */
336 543 0x5 /* MX51_PAD_DISP1_DAT10__DISP1_DAT10 */
337 545 0x5 /* MX51_PAD_DISP1_DAT11__DISP1_DAT11 */
338 547 0x5 /* MX51_PAD_DISP1_DAT12__DISP1_DAT12 */
339 549 0x5 /* MX51_PAD_DISP1_DAT13__DISP1_DAT13 */
340 551 0x5 /* MX51_PAD_DISP1_DAT14__DISP1_DAT14 */
341 553 0x5 /* MX51_PAD_DISP1_DAT15__DISP1_DAT15 */
342 555 0x5 /* MX51_PAD_DISP1_DAT16__DISP1_DAT16 */
343 557 0x5 /* MX51_PAD_DISP1_DAT17__DISP1_DAT17 */
344 559 0x5 /* MX51_PAD_DISP1_DAT18__DISP1_DAT18 */
345 563 0x5 /* MX51_PAD_DISP1_DAT19__DISP1_DAT19 */
346 567 0x5 /* MX51_PAD_DISP1_DAT20__DISP1_DAT20 */
347 571 0x5 /* MX51_PAD_DISP1_DAT21__DISP1_DAT21 */
348 575 0x5 /* MX51_PAD_DISP1_DAT22__DISP1_DAT22 */
349 579 0x5 /* MX51_PAD_DISP1_DAT23__DISP1_DAT23 */
350 584 0x5 /* MX51_PAD_DI1_PIN2__DI1_PIN2 (hsync) */
351 583 0x5 /* MX51_PAD_DI1_PIN3__DI1_PIN3 (vsync) */
352 >;
353 };
354 };
355
356 ipu_disp2 {
357 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
358 fsl,pins = <
359 603 0x5 /* MX51_PAD_DISP2_DAT0__DISP2_DAT0 */
360 608 0x5 /* MX51_PAD_DISP2_DAT1__DISP2_DAT1 */
361 613 0x5 /* MX51_PAD_DISP2_DAT2__DISP2_DAT2 */
362 614 0x5 /* MX51_PAD_DISP2_DAT3__DISP2_DAT3 */
363 615 0x5 /* MX51_PAD_DISP2_DAT4__DISP2_DAT4 */
364 616 0x5 /* MX51_PAD_DISP2_DAT5__DISP2_DAT5 */
365 617 0x5 /* MX51_PAD_DISP2_DAT6__DISP2_DAT6 */
366 622 0x5 /* MX51_PAD_DISP2_DAT7__DISP2_DAT7 */
367 627 0x5 /* MX51_PAD_DISP2_DAT8__DISP2_DAT8 */
368 633 0x5 /* MX51_PAD_DISP2_DAT9__DISP2_DAT9 */
369 637 0x5 /* MX51_PAD_DISP2_DAT10__DISP2_DAT10 */
370 643 0x5 /* MX51_PAD_DISP2_DAT11__DISP2_DAT11 */
371 648 0x5 /* MX51_PAD_DISP2_DAT12__DISP2_DAT12 */
372 652 0x5 /* MX51_PAD_DISP2_DAT13__DISP2_DAT13 */
373 656 0x5 /* MX51_PAD_DISP2_DAT14__DISP2_DAT14 */
374 661 0x5 /* MX51_PAD_DISP2_DAT15__DISP2_DAT15 */
375 593 0x5 /* MX51_PAD_DI2_PIN2__DI2_PIN2 (hsync) */
376 595 0x5 /* MX51_PAD_DI2_PIN3__DI2_PIN3 (vsync) */
377 597 0x5 /* MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK */
378 599 0x5 /* MX51_PAD_DI_GP4__DI2_PIN15 */
379 >;
380 };
381 };
382
298 uart1 { 383 uart1 {
299 pinctrl_uart1_1: uart1grp-1 { 384 pinctrl_uart1_1: uart1grp-1 {
300 fsl,pins = < 385 fsl,pins = <
@@ -327,10 +412,30 @@
327 }; 412 };
328 }; 413 };
329 414
415 pwm1: pwm@73fb4000 {
416 #pwm-cells = <2>;
417 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
418 reg = <0x73fb4000 0x4000>;
419 clocks = <&clks 37>, <&clks 38>;
420 clock-names = "ipg", "per";
421 interrupts = <61>;
422 };
423
424 pwm2: pwm@73fb8000 {
425 #pwm-cells = <2>;
426 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
427 reg = <0x73fb8000 0x4000>;
428 clocks = <&clks 39>, <&clks 40>;
429 clock-names = "ipg", "per";
430 interrupts = <94>;
431 };
432
330 uart1: serial@73fbc000 { 433 uart1: serial@73fbc000 {
331 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 434 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
332 reg = <0x73fbc000 0x4000>; 435 reg = <0x73fbc000 0x4000>;
333 interrupts = <31>; 436 interrupts = <31>;
437 clocks = <&clks 28>, <&clks 29>;
438 clock-names = "ipg", "per";
334 status = "disabled"; 439 status = "disabled";
335 }; 440 };
336 441
@@ -338,8 +443,17 @@
338 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 443 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
339 reg = <0x73fc0000 0x4000>; 444 reg = <0x73fc0000 0x4000>;
340 interrupts = <32>; 445 interrupts = <32>;
446 clocks = <&clks 30>, <&clks 31>;
447 clock-names = "ipg", "per";
341 status = "disabled"; 448 status = "disabled";
342 }; 449 };
450
451 clks: ccm@73fd4000{
452 compatible = "fsl,imx51-ccm";
453 reg = <0x73fd4000 0x4000>;
454 interrupts = <0 71 0x04 0 72 0x04>;
455 #clock-cells = <1>;
456 };
343 }; 457 };
344 458
345 aips@80000000 { /* AIPS2 */ 459 aips@80000000 { /* AIPS2 */
@@ -349,46 +463,54 @@
349 reg = <0x80000000 0x10000000>; 463 reg = <0x80000000 0x10000000>;
350 ranges; 464 ranges;
351 465
352 ecspi@83fac000 { /* ECSPI2 */ 466 ecspi2: ecspi@83fac000 {
353 #address-cells = <1>; 467 #address-cells = <1>;
354 #size-cells = <0>; 468 #size-cells = <0>;
355 compatible = "fsl,imx51-ecspi"; 469 compatible = "fsl,imx51-ecspi";
356 reg = <0x83fac000 0x4000>; 470 reg = <0x83fac000 0x4000>;
357 interrupts = <37>; 471 interrupts = <37>;
472 clocks = <&clks 53>, <&clks 54>;
473 clock-names = "ipg", "per";
358 status = "disabled"; 474 status = "disabled";
359 }; 475 };
360 476
361 sdma@83fb0000 { 477 sdma: sdma@83fb0000 {
362 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; 478 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
363 reg = <0x83fb0000 0x4000>; 479 reg = <0x83fb0000 0x4000>;
364 interrupts = <6>; 480 interrupts = <6>;
481 clocks = <&clks 56>, <&clks 56>;
482 clock-names = "ipg", "ahb";
365 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; 483 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
366 }; 484 };
367 485
368 cspi@83fc0000 { 486 cspi: cspi@83fc0000 {
369 #address-cells = <1>; 487 #address-cells = <1>;
370 #size-cells = <0>; 488 #size-cells = <0>;
371 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; 489 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
372 reg = <0x83fc0000 0x4000>; 490 reg = <0x83fc0000 0x4000>;
373 interrupts = <38>; 491 interrupts = <38>;
492 clocks = <&clks 55>, <&clks 0>;
493 clock-names = "ipg", "per";
374 status = "disabled"; 494 status = "disabled";
375 }; 495 };
376 496
377 i2c@83fc4000 { /* I2C2 */ 497 i2c2: i2c@83fc4000 {
378 #address-cells = <1>; 498 #address-cells = <1>;
379 #size-cells = <0>; 499 #size-cells = <0>;
380 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c"; 500 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
381 reg = <0x83fc4000 0x4000>; 501 reg = <0x83fc4000 0x4000>;
382 interrupts = <63>; 502 interrupts = <63>;
503 clocks = <&clks 35>;
383 status = "disabled"; 504 status = "disabled";
384 }; 505 };
385 506
386 i2c@83fc8000 { /* I2C1 */ 507 i2c1: i2c@83fc8000 {
387 #address-cells = <1>; 508 #address-cells = <1>;
388 #size-cells = <0>; 509 #size-cells = <0>;
389 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c"; 510 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
390 reg = <0x83fc8000 0x4000>; 511 reg = <0x83fc8000 0x4000>;
391 interrupts = <62>; 512 interrupts = <62>;
513 clocks = <&clks 34>;
392 status = "disabled"; 514 status = "disabled";
393 }; 515 };
394 516
@@ -396,21 +518,23 @@
396 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 518 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
397 reg = <0x83fcc000 0x4000>; 519 reg = <0x83fcc000 0x4000>;
398 interrupts = <29>; 520 interrupts = <29>;
521 clocks = <&clks 48>;
399 fsl,fifo-depth = <15>; 522 fsl,fifo-depth = <15>;
400 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ 523 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
401 status = "disabled"; 524 status = "disabled";
402 }; 525 };
403 526
404 audmux@83fd0000 { 527 audmux: audmux@83fd0000 {
405 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux"; 528 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
406 reg = <0x83fd0000 0x4000>; 529 reg = <0x83fd0000 0x4000>;
407 status = "disabled"; 530 status = "disabled";
408 }; 531 };
409 532
410 nand@83fdb000 { 533 nfc: nand@83fdb000 {
411 compatible = "fsl,imx51-nand"; 534 compatible = "fsl,imx51-nand";
412 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; 535 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
413 interrupts = <8>; 536 interrupts = <8>;
537 clocks = <&clks 60>;
414 status = "disabled"; 538 status = "disabled";
415 }; 539 };
416 540
@@ -418,15 +542,18 @@
418 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 542 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
419 reg = <0x83fe8000 0x4000>; 543 reg = <0x83fe8000 0x4000>;
420 interrupts = <96>; 544 interrupts = <96>;
545 clocks = <&clks 50>;
421 fsl,fifo-depth = <15>; 546 fsl,fifo-depth = <15>;
422 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */ 547 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
423 status = "disabled"; 548 status = "disabled";
424 }; 549 };
425 550
426 ethernet@83fec000 { 551 fec: ethernet@83fec000 {
427 compatible = "fsl,imx51-fec", "fsl,imx27-fec"; 552 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
428 reg = <0x83fec000 0x4000>; 553 reg = <0x83fec000 0x4000>;
429 interrupts = <87>; 554 interrupts = <87>;
555 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
556 clock-names = "ipg", "ahb", "ptp";
430 status = "disabled"; 557 status = "disabled";
431 }; 558 };
432 }; 559 };
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-09 12:24:33 -0500