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authorChristian König <christian.koenig@amd.com>2017-12-18 11:08:25 -0500
committerAlex Deucher <alexander.deucher@amd.com>2017-12-27 11:34:02 -0500
commitc4f46f22c448ff571eb8fdbe4ab71a25805228d1 (patch)
tree50d8eafedcb7b1bbc3fa00561101d395d9ec003b /drivers/gpu/drm/amd/amdgpu
parent620f774f4687d86c420152309eefb0ef0fcc7e51 (diff)
drm/amdgpu: rename vm_id to vmid
sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.c sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.h Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_job.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h28
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c14
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik_ih.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik_sdma.c14
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cz_ih.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c14
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c18
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c18
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c18
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c14
-rw-r--r--drivers/gpu/drm/amd/amdgpu/iceland_ih.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c16
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c16
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c18
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si_dma.c16
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si_ih.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/tonga_ih.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c26
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c36
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v3_0.c10
-rwxr-xr-xdrivers/gpu/drm/amd/amdgpu/vce_v4_0.c18
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c36
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vega10_ih.c4
33 files changed, 188 insertions, 194 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index bbe06e04dcb6..642bea2c9b3a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -351,7 +351,7 @@ struct amdgpu_gart_funcs {
351 /* get the pde for a given mc addr */ 351 /* get the pde for a given mc addr */
352 void (*get_vm_pde)(struct amdgpu_device *adev, int level, 352 void (*get_vm_pde)(struct amdgpu_device *adev, int level,
353 u64 *dst, u64 *flags); 353 u64 *dst, u64 *flags);
354 uint32_t (*get_invalidate_req)(unsigned int vm_id); 354 uint32_t (*get_invalidate_req)(unsigned int vmid);
355}; 355};
356 356
357/* provided by the ih block */ 357/* provided by the ih block */
@@ -1124,7 +1124,7 @@ struct amdgpu_job {
1124 void *owner; 1124 void *owner;
1125 uint64_t fence_ctx; /* the fence_context this job uses */ 1125 uint64_t fence_ctx; /* the fence_context this job uses */
1126 bool vm_needs_flush; 1126 bool vm_needs_flush;
1127 unsigned vm_id; 1127 unsigned vmid;
1128 uint64_t vm_pd_addr; 1128 uint64_t vm_pd_addr;
1129 uint32_t gds_base, gds_size; 1129 uint32_t gds_base, gds_size;
1130 uint32_t gws_base, gws_size; 1130 uint32_t gws_base, gws_size;
@@ -1849,7 +1849,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
1849#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 1849#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
1850#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 1850#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
1851#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 1851#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
1852#define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c)) 1852#define amdgpu_ring_emit_ib(r, ib, vmid, c) (r)->funcs->emit_ib((r), (ib), (vmid), (c))
1853#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 1853#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
1854#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 1854#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
1855#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 1855#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 03a69942cce5..a162d87ca0c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -149,7 +149,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
149 return -EINVAL; 149 return -EINVAL;
150 } 150 }
151 151
152 if (vm && !job->vm_id) { 152 if (vm && !job->vmid) {
153 dev_err(adev->dev, "VM IB without ID\n"); 153 dev_err(adev->dev, "VM IB without ID\n");
154 return -EINVAL; 154 return -EINVAL;
155 } 155 }
@@ -211,7 +211,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
211 !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */ 211 !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */
212 continue; 212 continue;
213 213
214 amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0, 214 amdgpu_ring_emit_ib(ring, ib, job ? job->vmid : 0,
215 need_ctx_switch); 215 need_ctx_switch);
216 need_ctx_switch = false; 216 need_ctx_switch = false;
217 } 217 }
@@ -229,8 +229,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
229 r = amdgpu_fence_emit(ring, f); 229 r = amdgpu_fence_emit(ring, f);
230 if (r) { 230 if (r) {
231 dev_err(adev->dev, "failed to emit fence (%d)\n", r); 231 dev_err(adev->dev, "failed to emit fence (%d)\n", r);
232 if (job && job->vm_id) 232 if (job && job->vmid)
233 amdgpu_vmid_reset(adev, ring->funcs->vmhub, job->vm_id); 233 amdgpu_vmid_reset(adev, ring->funcs->vmhub, job->vmid);
234 amdgpu_ring_undo(ring); 234 amdgpu_ring_undo(ring);
235 return r; 235 return r;
236 } 236 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
index 71f8a76d4c10..d24884b419cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
@@ -150,7 +150,7 @@ static int amdgpu_vmid_grab_reserved_locked(struct amdgpu_vm *vm,
150 dma_fence_put(id->last_flush); 150 dma_fence_put(id->last_flush);
151 id->last_flush = NULL; 151 id->last_flush = NULL;
152 } 152 }
153 job->vm_id = id - id_mgr->ids; 153 job->vmid = id - id_mgr->ids;
154 trace_amdgpu_vm_grab_id(vm, ring, job); 154 trace_amdgpu_vm_grab_id(vm, ring, job);
155out: 155out:
156 return r; 156 return r;
@@ -301,7 +301,7 @@ needs_flush:
301no_flush_needed: 301no_flush_needed:
302 list_move_tail(&id->list, &id_mgr->ids_lru); 302 list_move_tail(&id->list, &id_mgr->ids_lru);
303 303
304 job->vm_id = id - id_mgr->ids; 304 job->vmid = id - id_mgr->ids;
305 trace_amdgpu_vm_grab_id(vm, ring, job); 305 trace_amdgpu_vm_grab_id(vm, ring, job);
306 306
307error: 307error:
@@ -360,7 +360,7 @@ void amdgpu_vmid_free_reserved(struct amdgpu_device *adev,
360 * amdgpu_vmid_reset - reset VMID to zero 360 * amdgpu_vmid_reset - reset VMID to zero
361 * 361 *
362 * @adev: amdgpu device structure 362 * @adev: amdgpu device structure
363 * @vm_id: vmid number to use 363 * @vmid: vmid number to use
364 * 364 *
365 * Reset saved GDW, GWS and OA to force switch on next flush. 365 * Reset saved GDW, GWS and OA to force switch on next flush.
366 */ 366 */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index ada89358e220..29cf10927a92 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -105,8 +105,8 @@ struct amdgpu_iv_entry {
105 unsigned client_id; 105 unsigned client_id;
106 unsigned src_id; 106 unsigned src_id;
107 unsigned ring_id; 107 unsigned ring_id;
108 unsigned vm_id; 108 unsigned vmid;
109 unsigned vm_id_src; 109 unsigned vmid_src;
110 uint64_t timestamp; 110 uint64_t timestamp;
111 unsigned timestamp_src; 111 unsigned timestamp_src;
112 unsigned pas_id; 112 unsigned pas_id;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index cdc9e0f5336a..2bd56760c744 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -158,7 +158,7 @@ static struct dma_fence *amdgpu_job_dependency(struct drm_sched_job *sched_job,
158 } 158 }
159 } 159 }
160 160
161 while (fence == NULL && vm && !job->vm_id) { 161 while (fence == NULL && vm && !job->vmid) {
162 struct amdgpu_ring *ring = job->ring; 162 struct amdgpu_ring *ring = job->ring;
163 163
164 r = amdgpu_vmid_grab(vm, ring, &job->sync, 164 r = amdgpu_vmid_grab(vm, ring, &job->sync,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 010f69084af5..102dad3edf6a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -121,11 +121,11 @@ struct amdgpu_ring_funcs {
121 /* command emit functions */ 121 /* command emit functions */
122 void (*emit_ib)(struct amdgpu_ring *ring, 122 void (*emit_ib)(struct amdgpu_ring *ring,
123 struct amdgpu_ib *ib, 123 struct amdgpu_ib *ib,
124 unsigned vm_id, bool ctx_switch); 124 unsigned vmid, bool ctx_switch);
125 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 125 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
126 uint64_t seq, unsigned flags); 126 uint64_t seq, unsigned flags);
127 void (*emit_pipeline_sync)(struct amdgpu_ring *ring); 127 void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
128 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, 128 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid,
129 uint64_t pd_addr); 129 uint64_t pd_addr);
130 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 130 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
131 void (*emit_hdp_invalidate)(struct amdgpu_ring *ring); 131 void (*emit_hdp_invalidate)(struct amdgpu_ring *ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index 06525f2c36c3..cace7a93fc94 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -82,8 +82,8 @@ TRACE_EVENT(amdgpu_iv,
82 __field(unsigned, client_id) 82 __field(unsigned, client_id)
83 __field(unsigned, src_id) 83 __field(unsigned, src_id)
84 __field(unsigned, ring_id) 84 __field(unsigned, ring_id)
85 __field(unsigned, vm_id) 85 __field(unsigned, vmid)
86 __field(unsigned, vm_id_src) 86 __field(unsigned, vmid_src)
87 __field(uint64_t, timestamp) 87 __field(uint64_t, timestamp)
88 __field(unsigned, timestamp_src) 88 __field(unsigned, timestamp_src)
89 __field(unsigned, pas_id) 89 __field(unsigned, pas_id)
@@ -93,8 +93,8 @@ TRACE_EVENT(amdgpu_iv,
93 __entry->client_id = iv->client_id; 93 __entry->client_id = iv->client_id;
94 __entry->src_id = iv->src_id; 94 __entry->src_id = iv->src_id;
95 __entry->ring_id = iv->ring_id; 95 __entry->ring_id = iv->ring_id;
96 __entry->vm_id = iv->vm_id; 96 __entry->vmid = iv->vmid;
97 __entry->vm_id_src = iv->vm_id_src; 97 __entry->vmid_src = iv->vmid_src;
98 __entry->timestamp = iv->timestamp; 98 __entry->timestamp = iv->timestamp;
99 __entry->timestamp_src = iv->timestamp_src; 99 __entry->timestamp_src = iv->timestamp_src;
100 __entry->pas_id = iv->pas_id; 100 __entry->pas_id = iv->pas_id;
@@ -103,9 +103,9 @@ TRACE_EVENT(amdgpu_iv,
103 __entry->src_data[2] = iv->src_data[2]; 103 __entry->src_data[2] = iv->src_data[2];
104 __entry->src_data[3] = iv->src_data[3]; 104 __entry->src_data[3] = iv->src_data[3];
105 ), 105 ),
106 TP_printk("client_id:%u src_id:%u ring:%u vm_id:%u timestamp: %llu pas_id:%u src_data: %08x %08x %08x %08x\n", 106 TP_printk("client_id:%u src_id:%u ring:%u vmid:%u timestamp: %llu pas_id:%u src_data: %08x %08x %08x %08x\n",
107 __entry->client_id, __entry->src_id, 107 __entry->client_id, __entry->src_id,
108 __entry->ring_id, __entry->vm_id, 108 __entry->ring_id, __entry->vmid,
109 __entry->timestamp, __entry->pas_id, 109 __entry->timestamp, __entry->pas_id,
110 __entry->src_data[0], __entry->src_data[1], 110 __entry->src_data[0], __entry->src_data[1],
111 __entry->src_data[2], __entry->src_data[3]) 111 __entry->src_data[2], __entry->src_data[3])
@@ -219,7 +219,7 @@ TRACE_EVENT(amdgpu_vm_grab_id,
219 TP_STRUCT__entry( 219 TP_STRUCT__entry(
220 __field(struct amdgpu_vm *, vm) 220 __field(struct amdgpu_vm *, vm)
221 __field(u32, ring) 221 __field(u32, ring)
222 __field(u32, vm_id) 222 __field(u32, vmid)
223 __field(u32, vm_hub) 223 __field(u32, vm_hub)
224 __field(u64, pd_addr) 224 __field(u64, pd_addr)
225 __field(u32, needs_flush) 225 __field(u32, needs_flush)
@@ -228,13 +228,13 @@ TRACE_EVENT(amdgpu_vm_grab_id,
228 TP_fast_assign( 228 TP_fast_assign(
229 __entry->vm = vm; 229 __entry->vm = vm;
230 __entry->ring = ring->idx; 230 __entry->ring = ring->idx;
231 __entry->vm_id = job->vm_id; 231 __entry->vmid = job->vmid;
232 __entry->vm_hub = ring->funcs->vmhub, 232 __entry->vm_hub = ring->funcs->vmhub,
233 __entry->pd_addr = job->vm_pd_addr; 233 __entry->pd_addr = job->vm_pd_addr;
234 __entry->needs_flush = job->vm_needs_flush; 234 __entry->needs_flush = job->vm_needs_flush;
235 ), 235 ),
236 TP_printk("vm=%p, ring=%u, id=%u, hub=%u, pd_addr=%010Lx needs_flush=%u", 236 TP_printk("vm=%p, ring=%u, id=%u, hub=%u, pd_addr=%010Lx needs_flush=%u",
237 __entry->vm, __entry->ring, __entry->vm_id, 237 __entry->vm, __entry->ring, __entry->vmid,
238 __entry->vm_hub, __entry->pd_addr, __entry->needs_flush) 238 __entry->vm_hub, __entry->pd_addr, __entry->needs_flush)
239); 239);
240 240
@@ -357,24 +357,24 @@ TRACE_EVENT(amdgpu_vm_copy_ptes,
357); 357);
358 358
359TRACE_EVENT(amdgpu_vm_flush, 359TRACE_EVENT(amdgpu_vm_flush,
360 TP_PROTO(struct amdgpu_ring *ring, unsigned vm_id, 360 TP_PROTO(struct amdgpu_ring *ring, unsigned vmid,
361 uint64_t pd_addr), 361 uint64_t pd_addr),
362 TP_ARGS(ring, vm_id, pd_addr), 362 TP_ARGS(ring, vmid, pd_addr),
363 TP_STRUCT__entry( 363 TP_STRUCT__entry(
364 __field(u32, ring) 364 __field(u32, ring)
365 __field(u32, vm_id) 365 __field(u32, vmid)
366 __field(u32, vm_hub) 366 __field(u32, vm_hub)
367 __field(u64, pd_addr) 367 __field(u64, pd_addr)
368 ), 368 ),
369 369
370 TP_fast_assign( 370 TP_fast_assign(
371 __entry->ring = ring->idx; 371 __entry->ring = ring->idx;
372 __entry->vm_id = vm_id; 372 __entry->vmid = vmid;
373 __entry->vm_hub = ring->funcs->vmhub; 373 __entry->vm_hub = ring->funcs->vmhub;
374 __entry->pd_addr = pd_addr; 374 __entry->pd_addr = pd_addr;
375 ), 375 ),
376 TP_printk("ring=%u, id=%u, hub=%u, pd_addr=%010Lx", 376 TP_printk("ring=%u, id=%u, hub=%u, pd_addr=%010Lx",
377 __entry->ring, __entry->vm_id, 377 __entry->ring, __entry->vmid,
378 __entry->vm_hub,__entry->pd_addr) 378 __entry->vm_hub,__entry->pd_addr)
379); 379);
380 380
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 9857d482c942..55a726a322e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -991,7 +991,7 @@ out:
991 * 991 *
992 */ 992 */
993void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib, 993void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib,
994 unsigned vm_id, bool ctx_switch) 994 unsigned vmid, bool ctx_switch)
995{ 995{
996 amdgpu_ring_write(ring, VCE_CMD_IB); 996 amdgpu_ring_write(ring, VCE_CMD_IB);
997 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 997 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
index 162cae94e3b1..0fd378ae92c3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
@@ -63,7 +63,7 @@ void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp);
63int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx); 63int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx);
64int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, uint32_t ib_idx); 64int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, uint32_t ib_idx);
65void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib, 65void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib,
66 unsigned vm_id, bool ctx_switch); 66 unsigned vmid, bool ctx_switch);
67void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 67void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
68 unsigned flags); 68 unsigned flags);
69int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring); 69int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 01ee8e2258c8..946bc21c6d7d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -446,9 +446,9 @@ bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
446 bool gds_switch_needed; 446 bool gds_switch_needed;
447 bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug; 447 bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
448 448
449 if (job->vm_id == 0) 449 if (job->vmid == 0)
450 return false; 450 return false;
451 id = &id_mgr->ids[job->vm_id]; 451 id = &id_mgr->ids[job->vmid];
452 gds_switch_needed = ring->funcs->emit_gds_switch && ( 452 gds_switch_needed = ring->funcs->emit_gds_switch && (
453 id->gds_base != job->gds_base || 453 id->gds_base != job->gds_base ||
454 id->gds_size != job->gds_size || 454 id->gds_size != job->gds_size ||
@@ -472,7 +472,7 @@ static bool amdgpu_vm_is_large_bar(struct amdgpu_device *adev)
472 * amdgpu_vm_flush - hardware flush the vm 472 * amdgpu_vm_flush - hardware flush the vm
473 * 473 *
474 * @ring: ring to use for flush 474 * @ring: ring to use for flush
475 * @vm_id: vmid number to use 475 * @vmid: vmid number to use
476 * @pd_addr: address of the page directory 476 * @pd_addr: address of the page directory
477 * 477 *
478 * Emit a VM flush when it is necessary. 478 * Emit a VM flush when it is necessary.
@@ -482,7 +482,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_
482 struct amdgpu_device *adev = ring->adev; 482 struct amdgpu_device *adev = ring->adev;
483 unsigned vmhub = ring->funcs->vmhub; 483 unsigned vmhub = ring->funcs->vmhub;
484 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; 484 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
485 struct amdgpu_vmid *id = &id_mgr->ids[job->vm_id]; 485 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
486 bool gds_switch_needed = ring->funcs->emit_gds_switch && ( 486 bool gds_switch_needed = ring->funcs->emit_gds_switch && (
487 id->gds_base != job->gds_base || 487 id->gds_base != job->gds_base ||
488 id->gds_size != job->gds_size || 488 id->gds_size != job->gds_size ||
@@ -511,8 +511,8 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_
511 if (ring->funcs->emit_vm_flush && vm_flush_needed) { 511 if (ring->funcs->emit_vm_flush && vm_flush_needed) {
512 struct dma_fence *fence; 512 struct dma_fence *fence;
513 513
514 trace_amdgpu_vm_flush(ring, job->vm_id, job->vm_pd_addr); 514 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
515 amdgpu_ring_emit_vm_flush(ring, job->vm_id, job->vm_pd_addr); 515 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
516 516
517 r = amdgpu_fence_emit(ring, &fence); 517 r = amdgpu_fence_emit(ring, &fence);
518 if (r) 518 if (r)
@@ -532,7 +532,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_
532 id->gws_size = job->gws_size; 532 id->gws_size = job->gws_size;
533 id->oa_base = job->oa_base; 533 id->oa_base = job->oa_base;
534 id->oa_size = job->oa_size; 534 id->oa_size = job->oa_size;
535 amdgpu_ring_emit_gds_switch(ring, job->vm_id, job->gds_base, 535 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
536 job->gds_size, job->gws_base, 536 job->gds_size, job->gws_base,
537 job->gws_size, job->oa_base, 537 job->gws_size, job->oa_base,
538 job->oa_size); 538 job->oa_size);
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
index a870b354e3f7..d5a05c19708f 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
@@ -280,7 +280,7 @@ static void cik_ih_decode_iv(struct amdgpu_device *adev,
280 entry->src_id = dw[0] & 0xff; 280 entry->src_id = dw[0] & 0xff;
281 entry->src_data[0] = dw[1] & 0xfffffff; 281 entry->src_data[0] = dw[1] & 0xfffffff;
282 entry->ring_id = dw[2] & 0xff; 282 entry->ring_id = dw[2] & 0xff;
283 entry->vm_id = (dw[2] >> 8) & 0xff; 283 entry->vmid = (dw[2] >> 8) & 0xff;
284 entry->pas_id = (dw[2] >> 16) & 0xffff; 284 entry->pas_id = (dw[2] >> 16) & 0xffff;
285 285
286 /* wptr/rptr are in bytes! */ 286 /* wptr/rptr are in bytes! */
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index e406c93d01d6..6e8278e689b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -221,9 +221,9 @@ static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
221 */ 221 */
222static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring, 222static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
223 struct amdgpu_ib *ib, 223 struct amdgpu_ib *ib,
224 unsigned vm_id, bool ctx_switch) 224 unsigned vmid, bool ctx_switch)
225{ 225{
226 u32 extra_bits = vm_id & 0xf; 226 u32 extra_bits = vmid & 0xf;
227 227
228 /* IB packet must end on a 8 DW boundary */ 228 /* IB packet must end on a 8 DW boundary */
229 cik_sdma_ring_insert_nop(ring, (12 - (lower_32_bits(ring->wptr) & 7)) % 8); 229 cik_sdma_ring_insert_nop(ring, (12 - (lower_32_bits(ring->wptr) & 7)) % 8);
@@ -880,23 +880,23 @@ static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
880 * using sDMA (CIK). 880 * using sDMA (CIK).
881 */ 881 */
882static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring, 882static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
883 unsigned vm_id, uint64_t pd_addr) 883 unsigned vmid, uint64_t pd_addr)
884{ 884{
885 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) | 885 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
886 SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */ 886 SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
887 887
888 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 888 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
889 if (vm_id < 8) { 889 if (vmid < 8) {
890 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); 890 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
891 } else { 891 } else {
892 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); 892 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8));
893 } 893 }
894 amdgpu_ring_write(ring, pd_addr >> 12); 894 amdgpu_ring_write(ring, pd_addr >> 12);
895 895
896 /* flush TLB */ 896 /* flush TLB */
897 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 897 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
898 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 898 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
899 amdgpu_ring_write(ring, 1 << vm_id); 899 amdgpu_ring_write(ring, 1 << vmid);
900 900
901 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); 901 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
902 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 902 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
index fa61d649bb44..f576e9cbbc61 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
@@ -259,7 +259,7 @@ static void cz_ih_decode_iv(struct amdgpu_device *adev,
259 entry->src_id = dw[0] & 0xff; 259 entry->src_id = dw[0] & 0xff;
260 entry->src_data[0] = dw[1] & 0xfffffff; 260 entry->src_data[0] = dw[1] & 0xfffffff;
261 entry->ring_id = dw[2] & 0xff; 261 entry->ring_id = dw[2] & 0xff;
262 entry->vm_id = (dw[2] >> 8) & 0xff; 262 entry->vmid = (dw[2] >> 8) & 0xff;
263 entry->pas_id = (dw[2] >> 16) & 0xffff; 263 entry->pas_id = (dw[2] >> 16) & 0xffff;
264 264
265 /* wptr/rptr are in bytes! */ 265 /* wptr/rptr are in bytes! */
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index edef17d93527..9870d83b68c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -1874,7 +1874,7 @@ static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1874 1874
1875static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 1875static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1876 struct amdgpu_ib *ib, 1876 struct amdgpu_ib *ib,
1877 unsigned vm_id, bool ctx_switch) 1877 unsigned vmid, bool ctx_switch)
1878{ 1878{
1879 u32 header, control = 0; 1879 u32 header, control = 0;
1880 1880
@@ -1889,7 +1889,7 @@ static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1889 else 1889 else
1890 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 1890 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1891 1891
1892 control |= ib->length_dw | (vm_id << 24); 1892 control |= ib->length_dw | (vmid << 24);
1893 1893
1894 amdgpu_ring_write(ring, header); 1894 amdgpu_ring_write(ring, header);
1895 amdgpu_ring_write(ring, 1895 amdgpu_ring_write(ring,
@@ -2354,7 +2354,7 @@ static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2354} 2354}
2355 2355
2356static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 2356static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2357 unsigned vm_id, uint64_t pd_addr) 2357 unsigned vmid, uint64_t pd_addr)
2358{ 2358{
2359 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2359 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2360 2360
@@ -2362,10 +2362,10 @@ static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2362 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2362 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2363 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 2363 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
2364 WRITE_DATA_DST_SEL(0))); 2364 WRITE_DATA_DST_SEL(0)));
2365 if (vm_id < 8) { 2365 if (vmid < 8) {
2366 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id )); 2366 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid ));
2367 } else { 2367 } else {
2368 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8))); 2368 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8)));
2369 } 2369 }
2370 amdgpu_ring_write(ring, 0); 2370 amdgpu_ring_write(ring, 0);
2371 amdgpu_ring_write(ring, pd_addr >> 12); 2371 amdgpu_ring_write(ring, pd_addr >> 12);
@@ -2376,7 +2376,7 @@ static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2376 WRITE_DATA_DST_SEL(0))); 2376 WRITE_DATA_DST_SEL(0)));
2377 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 2377 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
2378 amdgpu_ring_write(ring, 0); 2378 amdgpu_ring_write(ring, 0);
2379 amdgpu_ring_write(ring, 1 << vm_id); 2379 amdgpu_ring_write(ring, 1 << vmid);
2380 2380
2381 /* wait for the invalidate to complete */ 2381 /* wait for the invalidate to complete */
2382 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2382 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 83d94c23aa78..4b5109bfd5f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2252,7 +2252,7 @@ static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
2252 */ 2252 */
2253static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 2253static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
2254 struct amdgpu_ib *ib, 2254 struct amdgpu_ib *ib,
2255 unsigned vm_id, bool ctx_switch) 2255 unsigned vmid, bool ctx_switch)
2256{ 2256{
2257 u32 header, control = 0; 2257 u32 header, control = 0;
2258 2258
@@ -2267,7 +2267,7 @@ static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
2267 else 2267 else
2268 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 2268 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2269 2269
2270 control |= ib->length_dw | (vm_id << 24); 2270 control |= ib->length_dw | (vmid << 24);
2271 2271
2272 amdgpu_ring_write(ring, header); 2272 amdgpu_ring_write(ring, header);
2273 amdgpu_ring_write(ring, 2273 amdgpu_ring_write(ring,
@@ -2281,9 +2281,9 @@ static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
2281 2281
2282static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 2282static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
2283 struct amdgpu_ib *ib, 2283 struct amdgpu_ib *ib,
2284 unsigned vm_id, bool ctx_switch) 2284 unsigned vmid, bool ctx_switch)
2285{ 2285{
2286 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24); 2286 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
2287 2287
2288 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2288 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2289 amdgpu_ring_write(ring, 2289 amdgpu_ring_write(ring,
@@ -3237,19 +3237,19 @@ static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3237 * using the CP (CIK). 3237 * using the CP (CIK).
3238 */ 3238 */
3239static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 3239static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3240 unsigned vm_id, uint64_t pd_addr) 3240 unsigned vmid, uint64_t pd_addr)
3241{ 3241{
3242 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3242 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3243 3243
3244 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3244 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3245 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | 3245 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3246 WRITE_DATA_DST_SEL(0))); 3246 WRITE_DATA_DST_SEL(0)));
3247 if (vm_id < 8) { 3247 if (vmid < 8) {
3248 amdgpu_ring_write(ring, 3248 amdgpu_ring_write(ring,
3249 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); 3249 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
3250 } else { 3250 } else {
3251 amdgpu_ring_write(ring, 3251 amdgpu_ring_write(ring,
3252 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); 3252 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8));
3253 } 3253 }
3254 amdgpu_ring_write(ring, 0); 3254 amdgpu_ring_write(ring, 0);
3255 amdgpu_ring_write(ring, pd_addr >> 12); 3255 amdgpu_ring_write(ring, pd_addr >> 12);
@@ -3260,7 +3260,7 @@ static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3260 WRITE_DATA_DST_SEL(0))); 3260 WRITE_DATA_DST_SEL(0)));
3261 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 3261 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3262 amdgpu_ring_write(ring, 0); 3262 amdgpu_ring_write(ring, 0);
3263 amdgpu_ring_write(ring, 1 << vm_id); 3263 amdgpu_ring_write(ring, 1 << vmid);
3264 3264
3265 /* wait for the invalidate to complete */ 3265 /* wait for the invalidate to complete */
3266 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3266 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 46550b588982..ff9f1a82630f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6245,7 +6245,7 @@ static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
6245 6245
6246static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 6246static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
6247 struct amdgpu_ib *ib, 6247 struct amdgpu_ib *ib,
6248 unsigned vm_id, bool ctx_switch) 6248 unsigned vmid, bool ctx_switch)
6249{ 6249{
6250 u32 header, control = 0; 6250 u32 header, control = 0;
6251 6251
@@ -6254,7 +6254,7 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
6254 else 6254 else
6255 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 6255 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
6256 6256
6257 control |= ib->length_dw | (vm_id << 24); 6257 control |= ib->length_dw | (vmid << 24);
6258 6258
6259 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 6259 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
6260 control |= INDIRECT_BUFFER_PRE_ENB(1); 6260 control |= INDIRECT_BUFFER_PRE_ENB(1);
@@ -6275,9 +6275,9 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
6275 6275
6276static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 6276static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
6277 struct amdgpu_ib *ib, 6277 struct amdgpu_ib *ib,
6278 unsigned vm_id, bool ctx_switch) 6278 unsigned vmid, bool ctx_switch)
6279{ 6279{
6280 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24); 6280 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
6281 6281
6282 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 6282 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
6283 amdgpu_ring_write(ring, 6283 amdgpu_ring_write(ring,
@@ -6328,7 +6328,7 @@ static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
6328} 6328}
6329 6329
6330static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 6330static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
6331 unsigned vm_id, uint64_t pd_addr) 6331 unsigned vmid, uint64_t pd_addr)
6332{ 6332{
6333 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 6333 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
6334 6334
@@ -6336,12 +6336,12 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
6336 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | 6336 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
6337 WRITE_DATA_DST_SEL(0)) | 6337 WRITE_DATA_DST_SEL(0)) |
6338 WR_CONFIRM); 6338 WR_CONFIRM);
6339 if (vm_id < 8) { 6339 if (vmid < 8) {
6340 amdgpu_ring_write(ring, 6340 amdgpu_ring_write(ring,
6341 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); 6341 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
6342 } else { 6342 } else {
6343 amdgpu_ring_write(ring, 6343 amdgpu_ring_write(ring,
6344 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); 6344 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8));
6345 } 6345 }
6346 amdgpu_ring_write(ring, 0); 6346 amdgpu_ring_write(ring, 0);
6347 amdgpu_ring_write(ring, pd_addr >> 12); 6347 amdgpu_ring_write(ring, pd_addr >> 12);
@@ -6353,7 +6353,7 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
6353 WRITE_DATA_DST_SEL(0))); 6353 WRITE_DATA_DST_SEL(0)));
6354 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 6354 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
6355 amdgpu_ring_write(ring, 0); 6355 amdgpu_ring_write(ring, 0);
6356 amdgpu_ring_write(ring, 1 << vm_id); 6356 amdgpu_ring_write(ring, 1 << vmid);
6357 6357
6358 /* wait for the invalidate to complete */ 6358 /* wait for the invalidate to complete */
6359 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 6359 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 9f7be230734c..55670dbacace 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3594,7 +3594,7 @@ static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
3594 3594
3595static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 3595static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3596 struct amdgpu_ib *ib, 3596 struct amdgpu_ib *ib,
3597 unsigned vm_id, bool ctx_switch) 3597 unsigned vmid, bool ctx_switch)
3598{ 3598{
3599 u32 header, control = 0; 3599 u32 header, control = 0;
3600 3600
@@ -3603,7 +3603,7 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3603 else 3603 else
3604 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 3604 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3605 3605
3606 control |= ib->length_dw | (vm_id << 24); 3606 control |= ib->length_dw | (vmid << 24);
3607 3607
3608 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 3608 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
3609 control |= INDIRECT_BUFFER_PRE_ENB(1); 3609 control |= INDIRECT_BUFFER_PRE_ENB(1);
@@ -3625,9 +3625,9 @@ BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3625 3625
3626static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 3626static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3627 struct amdgpu_ib *ib, 3627 struct amdgpu_ib *ib,
3628 unsigned vm_id, bool ctx_switch) 3628 unsigned vmid, bool ctx_switch)
3629{ 3629{
3630 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24); 3630 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
3631 3631
3632 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3632 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3633 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 3633 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
@@ -3683,11 +3683,11 @@ static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3683} 3683}
3684 3684
3685static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 3685static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3686 unsigned vm_id, uint64_t pd_addr) 3686 unsigned vmid, uint64_t pd_addr)
3687{ 3687{
3688 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 3688 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
3689 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3689 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3690 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); 3690 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
3691 uint64_t flags = AMDGPU_PTE_VALID; 3691 uint64_t flags = AMDGPU_PTE_VALID;
3692 unsigned eng = ring->vm_inv_eng; 3692 unsigned eng = ring->vm_inv_eng;
3693 3693
@@ -3695,11 +3695,11 @@ static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3695 pd_addr |= flags; 3695 pd_addr |= flags;
3696 3696
3697 gfx_v9_0_write_data_to_reg(ring, usepfp, true, 3697 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3698 hub->ctx0_ptb_addr_lo32 + (2 * vm_id), 3698 hub->ctx0_ptb_addr_lo32 + (2 * vmid),
3699 lower_32_bits(pd_addr)); 3699 lower_32_bits(pd_addr));
3700 3700
3701 gfx_v9_0_write_data_to_reg(ring, usepfp, true, 3701 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3702 hub->ctx0_ptb_addr_hi32 + (2 * vm_id), 3702 hub->ctx0_ptb_addr_hi32 + (2 * vmid),
3703 upper_32_bits(pd_addr)); 3703 upper_32_bits(pd_addr));
3704 3704
3705 gfx_v9_0_write_data_to_reg(ring, usepfp, true, 3705 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
@@ -3707,7 +3707,7 @@ static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3707 3707
3708 /* wait for the invalidate to complete */ 3708 /* wait for the invalidate to complete */
3709 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack + 3709 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
3710 eng, 0, 1 << vm_id, 1 << vm_id, 0x20); 3710 eng, 0, 1 << vmid, 1 << vmid, 0x20);
3711 3711
3712 /* compute doesn't have PFP */ 3712 /* compute doesn't have PFP */
3713 if (usepfp) { 3713 if (usepfp) {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 909274e3ebe7..eb8b1bb66389 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -248,7 +248,7 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
248 struct amdgpu_irq_src *source, 248 struct amdgpu_irq_src *source,
249 struct amdgpu_iv_entry *entry) 249 struct amdgpu_iv_entry *entry)
250{ 250{
251 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vm_id_src]; 251 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
252 uint32_t status = 0; 252 uint32_t status = 0;
253 u64 addr; 253 u64 addr;
254 254
@@ -262,9 +262,9 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
262 262
263 if (printk_ratelimit()) { 263 if (printk_ratelimit()) {
264 dev_err(adev->dev, 264 dev_err(adev->dev,
265 "[%s] VMC page fault (src_id:%u ring:%u vm_id:%u pas_id:%u)\n", 265 "[%s] VMC page fault (src_id:%u ring:%u vmid:%u pas_id:%u)\n",
266 entry->vm_id_src ? "mmhub" : "gfxhub", 266 entry->vmid_src ? "mmhub" : "gfxhub",
267 entry->src_id, entry->ring_id, entry->vm_id, 267 entry->src_id, entry->ring_id, entry->vmid,
268 entry->pas_id); 268 entry->pas_id);
269 dev_err(adev->dev, " at page 0x%016llx from %d\n", 269 dev_err(adev->dev, " at page 0x%016llx from %d\n",
270 addr, entry->client_id); 270 addr, entry->client_id);
@@ -288,13 +288,13 @@ static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
288 adev->mc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 288 adev->mc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
289} 289}
290 290
291static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vm_id) 291static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid)
292{ 292{
293 u32 req = 0; 293 u32 req = 0;
294 294
295 /* invalidate using legacy mode on vm_id*/ 295 /* invalidate using legacy mode on vmid*/
296 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 296 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
297 PER_VMID_INVALIDATE_REQ, 1 << vm_id); 297 PER_VMID_INVALIDATE_REQ, 1 << vmid);
298 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0); 298 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
299 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 299 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
300 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 300 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
index bd592cb39f37..c4e4be3dd31d 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
@@ -259,7 +259,7 @@ static void iceland_ih_decode_iv(struct amdgpu_device *adev,
259 entry->src_id = dw[0] & 0xff; 259 entry->src_id = dw[0] & 0xff;
260 entry->src_data[0] = dw[1] & 0xfffffff; 260 entry->src_data[0] = dw[1] & 0xfffffff;
261 entry->ring_id = dw[2] & 0xff; 261 entry->ring_id = dw[2] & 0xff;
262 entry->vm_id = (dw[2] >> 8) & 0xff; 262 entry->vmid = (dw[2] >> 8) & 0xff;
263 entry->pas_id = (dw[2] >> 16) & 0xffff; 263 entry->pas_id = (dw[2] >> 16) & 0xffff;
264 264
265 /* wptr/rptr are in bytes! */ 265 /* wptr/rptr are in bytes! */
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 401552bae7f5..d4787ad4d346 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -246,15 +246,13 @@ static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
246 */ 246 */
247static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring, 247static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
248 struct amdgpu_ib *ib, 248 struct amdgpu_ib *ib,
249 unsigned vm_id, bool ctx_switch) 249 unsigned vmid, bool ctx_switch)
250{ 250{
251 u32 vmid = vm_id & 0xf;
252
253 /* IB packet must end on a 8 DW boundary */ 251 /* IB packet must end on a 8 DW boundary */
254 sdma_v2_4_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 252 sdma_v2_4_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
255 253
256 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 254 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
257 SDMA_PKT_INDIRECT_HEADER_VMID(vmid)); 255 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
258 /* base must be 32 byte aligned */ 256 /* base must be 32 byte aligned */
259 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 257 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
260 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 258 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
@@ -861,14 +859,14 @@ static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
861 * using sDMA (VI). 859 * using sDMA (VI).
862 */ 860 */
863static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring, 861static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
864 unsigned vm_id, uint64_t pd_addr) 862 unsigned vmid, uint64_t pd_addr)
865{ 863{
866 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 864 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
867 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 865 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
868 if (vm_id < 8) { 866 if (vmid < 8) {
869 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); 867 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
870 } else { 868 } else {
871 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); 869 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8));
872 } 870 }
873 amdgpu_ring_write(ring, pd_addr >> 12); 871 amdgpu_ring_write(ring, pd_addr >> 12);
874 872
@@ -876,7 +874,7 @@ static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
876 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 874 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
877 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 875 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
878 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 876 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
879 amdgpu_ring_write(ring, 1 << vm_id); 877 amdgpu_ring_write(ring, 1 << vmid);
880 878
881 /* wait for flush */ 879 /* wait for flush */
882 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 880 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 0735d4d0e56a..521978c40537 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -417,15 +417,13 @@ static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
417 */ 417 */
418static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, 418static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
419 struct amdgpu_ib *ib, 419 struct amdgpu_ib *ib,
420 unsigned vm_id, bool ctx_switch) 420 unsigned vmid, bool ctx_switch)
421{ 421{
422 u32 vmid = vm_id & 0xf;
423
424 /* IB packet must end on a 8 DW boundary */ 422 /* IB packet must end on a 8 DW boundary */
425 sdma_v3_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 423 sdma_v3_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
426 424
427 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 425 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
428 SDMA_PKT_INDIRECT_HEADER_VMID(vmid)); 426 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
429 /* base must be 32 byte aligned */ 427 /* base must be 32 byte aligned */
430 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 428 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
431 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 429 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
@@ -1127,14 +1125,14 @@ static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1127 * using sDMA (VI). 1125 * using sDMA (VI).
1128 */ 1126 */
1129static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1127static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1130 unsigned vm_id, uint64_t pd_addr) 1128 unsigned vmid, uint64_t pd_addr)
1131{ 1129{
1132 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1130 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1133 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1131 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1134 if (vm_id < 8) { 1132 if (vmid < 8) {
1135 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); 1133 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
1136 } else { 1134 } else {
1137 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); 1135 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8));
1138 } 1136 }
1139 amdgpu_ring_write(ring, pd_addr >> 12); 1137 amdgpu_ring_write(ring, pd_addr >> 12);
1140 1138
@@ -1142,7 +1140,7 @@ static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1142 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1140 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1143 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1141 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1144 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 1142 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
1145 amdgpu_ring_write(ring, 1 << vm_id); 1143 amdgpu_ring_write(ring, 1 << vmid);
1146 1144
1147 /* wait for flush */ 1145 /* wait for flush */
1148 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1146 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 73477c5ed9b4..e92fb372bc99 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -330,15 +330,13 @@ static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
330 */ 330 */
331static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 331static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
332 struct amdgpu_ib *ib, 332 struct amdgpu_ib *ib,
333 unsigned vm_id, bool ctx_switch) 333 unsigned vmid, bool ctx_switch)
334{ 334{
335 u32 vmid = vm_id & 0xf;
336
337 /* IB packet must end on a 8 DW boundary */ 335 /* IB packet must end on a 8 DW boundary */
338 sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 336 sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
339 337
340 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 338 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
341 SDMA_PKT_INDIRECT_HEADER_VMID(vmid)); 339 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
342 /* base must be 32 byte aligned */ 340 /* base must be 32 byte aligned */
343 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 341 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
344 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 342 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
@@ -1135,10 +1133,10 @@ static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1135 * using sDMA (VEGA10). 1133 * using sDMA (VEGA10).
1136 */ 1134 */
1137static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1135static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1138 unsigned vm_id, uint64_t pd_addr) 1136 unsigned vmid, uint64_t pd_addr)
1139{ 1137{
1140 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1138 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1141 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); 1139 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
1142 uint64_t flags = AMDGPU_PTE_VALID; 1140 uint64_t flags = AMDGPU_PTE_VALID;
1143 unsigned eng = ring->vm_inv_eng; 1141 unsigned eng = ring->vm_inv_eng;
1144 1142
@@ -1147,12 +1145,12 @@ static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1147 1145
1148 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1146 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1149 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1147 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1150 amdgpu_ring_write(ring, hub->ctx0_ptb_addr_lo32 + vm_id * 2); 1148 amdgpu_ring_write(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2);
1151 amdgpu_ring_write(ring, lower_32_bits(pd_addr)); 1149 amdgpu_ring_write(ring, lower_32_bits(pd_addr));
1152 1150
1153 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1151 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1154 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1152 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1155 amdgpu_ring_write(ring, hub->ctx0_ptb_addr_hi32 + vm_id * 2); 1153 amdgpu_ring_write(ring, hub->ctx0_ptb_addr_hi32 + vmid * 2);
1156 amdgpu_ring_write(ring, upper_32_bits(pd_addr)); 1154 amdgpu_ring_write(ring, upper_32_bits(pd_addr));
1157 1155
1158 /* flush TLB */ 1156 /* flush TLB */
@@ -1167,8 +1165,8 @@ static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1167 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1165 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1168 amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2); 1166 amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
1169 amdgpu_ring_write(ring, 0); 1167 amdgpu_ring_write(ring, 0);
1170 amdgpu_ring_write(ring, 1 << vm_id); /* reference */ 1168 amdgpu_ring_write(ring, 1 << vmid); /* reference */
1171 amdgpu_ring_write(ring, 1 << vm_id); /* mask */ 1169 amdgpu_ring_write(ring, 1 << vmid); /* mask */
1172 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1170 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1173 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1171 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1174} 1172}
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 9adca5d8b045..9a29c1399091 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -61,14 +61,14 @@ static void si_dma_ring_set_wptr(struct amdgpu_ring *ring)
61 61
62static void si_dma_ring_emit_ib(struct amdgpu_ring *ring, 62static void si_dma_ring_emit_ib(struct amdgpu_ring *ring,
63 struct amdgpu_ib *ib, 63 struct amdgpu_ib *ib,
64 unsigned vm_id, bool ctx_switch) 64 unsigned vmid, bool ctx_switch)
65{ 65{
66 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring. 66 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
67 * Pad as necessary with NOPs. 67 * Pad as necessary with NOPs.
68 */ 68 */
69 while ((lower_32_bits(ring->wptr) & 7) != 5) 69 while ((lower_32_bits(ring->wptr) & 7) != 5)
70 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); 70 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
71 amdgpu_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vm_id, 0)); 71 amdgpu_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vmid, 0));
72 amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); 72 amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
73 amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); 73 amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
74 74
@@ -473,25 +473,25 @@ static void si_dma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
473 * using sDMA (VI). 473 * using sDMA (VI).
474 */ 474 */
475static void si_dma_ring_emit_vm_flush(struct amdgpu_ring *ring, 475static void si_dma_ring_emit_vm_flush(struct amdgpu_ring *ring,
476 unsigned vm_id, uint64_t pd_addr) 476 unsigned vmid, uint64_t pd_addr)
477{ 477{
478 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); 478 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
479 if (vm_id < 8) 479 if (vmid < 8)
480 amdgpu_ring_write(ring, (0xf << 16) | (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); 480 amdgpu_ring_write(ring, (0xf << 16) | (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
481 else 481 else
482 amdgpu_ring_write(ring, (0xf << 16) | (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8))); 482 amdgpu_ring_write(ring, (0xf << 16) | (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8)));
483 amdgpu_ring_write(ring, pd_addr >> 12); 483 amdgpu_ring_write(ring, pd_addr >> 12);
484 484
485 /* bits 0-7 are the VM contexts0-7 */ 485 /* bits 0-7 are the VM contexts0-7 */
486 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); 486 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
487 amdgpu_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST)); 487 amdgpu_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST));
488 amdgpu_ring_write(ring, 1 << vm_id); 488 amdgpu_ring_write(ring, 1 << vmid);
489 489
490 /* wait for invalidate to complete */ 490 /* wait for invalidate to complete */
491 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_POLL_REG_MEM, 0, 0, 0, 0)); 491 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_POLL_REG_MEM, 0, 0, 0, 0));
492 amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST); 492 amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST);
493 amdgpu_ring_write(ring, 0xff << 16); /* retry */ 493 amdgpu_ring_write(ring, 0xff << 16); /* retry */
494 amdgpu_ring_write(ring, 1 << vm_id); /* mask */ 494 amdgpu_ring_write(ring, 1 << vmid); /* mask */
495 amdgpu_ring_write(ring, 0); /* value */ 495 amdgpu_ring_write(ring, 0); /* value */
496 amdgpu_ring_write(ring, (0 << 28) | 0x20); /* func(always) | poll interval */ 496 amdgpu_ring_write(ring, (0 << 28) | 0x20); /* func(always) | poll interval */
497} 497}
diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
index d2c6b80309c8..60dad63098a2 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
@@ -146,7 +146,7 @@ static void si_ih_decode_iv(struct amdgpu_device *adev,
146 entry->src_id = dw[0] & 0xff; 146 entry->src_id = dw[0] & 0xff;
147 entry->src_data[0] = dw[1] & 0xfffffff; 147 entry->src_data[0] = dw[1] & 0xfffffff;
148 entry->ring_id = dw[2] & 0xff; 148 entry->ring_id = dw[2] & 0xff;
149 entry->vm_id = (dw[2] >> 8) & 0xff; 149 entry->vmid = (dw[2] >> 8) & 0xff;
150 150
151 adev->irq.ih.rptr += 16; 151 adev->irq.ih.rptr += 16;
152} 152}
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index aa4e320e31f8..5995ffc183de 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -270,7 +270,7 @@ static void tonga_ih_decode_iv(struct amdgpu_device *adev,
270 entry->src_id = dw[0] & 0xff; 270 entry->src_id = dw[0] & 0xff;
271 entry->src_data[0] = dw[1] & 0xfffffff; 271 entry->src_data[0] = dw[1] & 0xfffffff;
272 entry->ring_id = dw[2] & 0xff; 272 entry->ring_id = dw[2] & 0xff;
273 entry->vm_id = (dw[2] >> 8) & 0xff; 273 entry->vmid = (dw[2] >> 8) & 0xff;
274 entry->pas_id = (dw[2] >> 16) & 0xffff; 274 entry->pas_id = (dw[2] >> 16) & 0xffff;
275 275
276 /* wptr/rptr are in bytes! */ 276 /* wptr/rptr are in bytes! */
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index b13ae34be1c2..8ab10c220910 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -541,7 +541,7 @@ static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring)
541 */ 541 */
542static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring, 542static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring,
543 struct amdgpu_ib *ib, 543 struct amdgpu_ib *ib,
544 unsigned vm_id, bool ctx_switch) 544 unsigned vmid, bool ctx_switch)
545{ 545{
546 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0)); 546 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0));
547 amdgpu_ring_write(ring, ib->gpu_addr); 547 amdgpu_ring_write(ring, ib->gpu_addr);
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index a4b0f1d842b7..c1fe30cdba32 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -556,7 +556,7 @@ static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring)
556 */ 556 */
557static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 557static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
558 struct amdgpu_ib *ib, 558 struct amdgpu_ib *ib,
559 unsigned vm_id, bool ctx_switch) 559 unsigned vmid, bool ctx_switch)
560{ 560{
561 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); 561 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
562 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 562 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 86123448a8ff..59271055a30e 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -1028,10 +1028,10 @@ static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring)
1028 */ 1028 */
1029static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 1029static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1030 struct amdgpu_ib *ib, 1030 struct amdgpu_ib *ib,
1031 unsigned vm_id, bool ctx_switch) 1031 unsigned vmid, bool ctx_switch)
1032{ 1032{
1033 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0)); 1033 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0));
1034 amdgpu_ring_write(ring, vm_id); 1034 amdgpu_ring_write(ring, vmid);
1035 1035
1036 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); 1036 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
1037 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1037 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
@@ -1050,24 +1050,24 @@ static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1050 * Write enc ring commands to execute the indirect buffer 1050 * Write enc ring commands to execute the indirect buffer
1051 */ 1051 */
1052static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1052static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1053 struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch) 1053 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
1054{ 1054{
1055 amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM); 1055 amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
1056 amdgpu_ring_write(ring, vm_id); 1056 amdgpu_ring_write(ring, vmid);
1057 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1057 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1058 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1058 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1059 amdgpu_ring_write(ring, ib->length_dw); 1059 amdgpu_ring_write(ring, ib->length_dw);
1060} 1060}
1061 1061
1062static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1062static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1063 unsigned vm_id, uint64_t pd_addr) 1063 unsigned vmid, uint64_t pd_addr)
1064{ 1064{
1065 uint32_t reg; 1065 uint32_t reg;
1066 1066
1067 if (vm_id < 8) 1067 if (vmid < 8)
1068 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id; 1068 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
1069 else 1069 else
1070 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8; 1070 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
1071 1071
1072 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 1072 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1073 amdgpu_ring_write(ring, reg << 2); 1073 amdgpu_ring_write(ring, reg << 2);
@@ -1079,7 +1079,7 @@ static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1079 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 1079 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1080 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 1080 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1081 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 1081 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1082 amdgpu_ring_write(ring, 1 << vm_id); 1082 amdgpu_ring_write(ring, 1 << vmid);
1083 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 1083 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1084 amdgpu_ring_write(ring, 0x8); 1084 amdgpu_ring_write(ring, 0x8);
1085 1085
@@ -1088,7 +1088,7 @@ static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1088 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 1088 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1089 amdgpu_ring_write(ring, 0); 1089 amdgpu_ring_write(ring, 0);
1090 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0)); 1090 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
1091 amdgpu_ring_write(ring, 1 << vm_id); /* mask */ 1091 amdgpu_ring_write(ring, 1 << vmid); /* mask */
1092 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 1092 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1093 amdgpu_ring_write(ring, 0xC); 1093 amdgpu_ring_write(ring, 0xC);
1094} 1094}
@@ -1127,14 +1127,14 @@ static void uvd_v6_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1127} 1127}
1128 1128
1129static void uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1129static void uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1130 unsigned int vm_id, uint64_t pd_addr) 1130 unsigned int vmid, uint64_t pd_addr)
1131{ 1131{
1132 amdgpu_ring_write(ring, HEVC_ENC_CMD_UPDATE_PTB); 1132 amdgpu_ring_write(ring, HEVC_ENC_CMD_UPDATE_PTB);
1133 amdgpu_ring_write(ring, vm_id); 1133 amdgpu_ring_write(ring, vmid);
1134 amdgpu_ring_write(ring, pd_addr >> 12); 1134 amdgpu_ring_write(ring, pd_addr >> 12);
1135 1135
1136 amdgpu_ring_write(ring, HEVC_ENC_CMD_FLUSH_TLB); 1136 amdgpu_ring_write(ring, HEVC_ENC_CMD_FLUSH_TLB);
1137 amdgpu_ring_write(ring, vm_id); 1137 amdgpu_ring_write(ring, vmid);
1138} 1138}
1139 1139
1140static bool uvd_v6_0_is_idle(void *handle) 1140static bool uvd_v6_0_is_idle(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 4ec4447d33c0..6b95f4f344b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -1218,13 +1218,13 @@ static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring)
1218 */ 1218 */
1219static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring, 1219static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
1220 struct amdgpu_ib *ib, 1220 struct amdgpu_ib *ib,
1221 unsigned vm_id, bool ctx_switch) 1221 unsigned vmid, bool ctx_switch)
1222{ 1222{
1223 struct amdgpu_device *adev = ring->adev; 1223 struct amdgpu_device *adev = ring->adev;
1224 1224
1225 amdgpu_ring_write(ring, 1225 amdgpu_ring_write(ring,
1226 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0)); 1226 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
1227 amdgpu_ring_write(ring, vm_id); 1227 amdgpu_ring_write(ring, vmid);
1228 1228
1229 amdgpu_ring_write(ring, 1229 amdgpu_ring_write(ring,
1230 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); 1230 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
@@ -1246,10 +1246,10 @@ static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
1246 * Write enc ring commands to execute the indirect buffer 1246 * Write enc ring commands to execute the indirect buffer
1247 */ 1247 */
1248static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1248static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1249 struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch) 1249 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
1250{ 1250{
1251 amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM); 1251 amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
1252 amdgpu_ring_write(ring, vm_id); 1252 amdgpu_ring_write(ring, vmid);
1253 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1253 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1254 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1254 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1255 amdgpu_ring_write(ring, ib->length_dw); 1255 amdgpu_ring_write(ring, ib->length_dw);
@@ -1291,10 +1291,10 @@ static void uvd_v7_0_vm_reg_wait(struct amdgpu_ring *ring,
1291} 1291}
1292 1292
1293static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1293static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1294 unsigned vm_id, uint64_t pd_addr) 1294 unsigned vmid, uint64_t pd_addr)
1295{ 1295{
1296 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1296 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1297 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); 1297 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
1298 uint64_t flags = AMDGPU_PTE_VALID; 1298 uint64_t flags = AMDGPU_PTE_VALID;
1299 unsigned eng = ring->vm_inv_eng; 1299 unsigned eng = ring->vm_inv_eng;
1300 uint32_t data0, data1, mask; 1300 uint32_t data0, data1, mask;
@@ -1302,15 +1302,15 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1302 amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags); 1302 amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
1303 pd_addr |= flags; 1303 pd_addr |= flags;
1304 1304
1305 data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2; 1305 data0 = (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2;
1306 data1 = upper_32_bits(pd_addr); 1306 data1 = upper_32_bits(pd_addr);
1307 uvd_v7_0_vm_reg_write(ring, data0, data1); 1307 uvd_v7_0_vm_reg_write(ring, data0, data1);
1308 1308
1309 data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2; 1309 data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
1310 data1 = lower_32_bits(pd_addr); 1310 data1 = lower_32_bits(pd_addr);
1311 uvd_v7_0_vm_reg_write(ring, data0, data1); 1311 uvd_v7_0_vm_reg_write(ring, data0, data1);
1312 1312
1313 data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2; 1313 data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
1314 data1 = lower_32_bits(pd_addr); 1314 data1 = lower_32_bits(pd_addr);
1315 mask = 0xffffffff; 1315 mask = 0xffffffff;
1316 uvd_v7_0_vm_reg_wait(ring, data0, data1, mask); 1316 uvd_v7_0_vm_reg_wait(ring, data0, data1, mask);
@@ -1322,8 +1322,8 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1322 1322
1323 /* wait for flush */ 1323 /* wait for flush */
1324 data0 = (hub->vm_inv_eng0_ack + eng) << 2; 1324 data0 = (hub->vm_inv_eng0_ack + eng) << 2;
1325 data1 = 1 << vm_id; 1325 data1 = 1 << vmid;
1326 mask = 1 << vm_id; 1326 mask = 1 << vmid;
1327 uvd_v7_0_vm_reg_wait(ring, data0, data1, mask); 1327 uvd_v7_0_vm_reg_wait(ring, data0, data1, mask);
1328} 1328}
1329 1329
@@ -1343,10 +1343,10 @@ static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1343} 1343}
1344 1344
1345static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1345static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1346 unsigned int vm_id, uint64_t pd_addr) 1346 unsigned int vmid, uint64_t pd_addr)
1347{ 1347{
1348 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1348 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1349 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); 1349 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
1350 uint64_t flags = AMDGPU_PTE_VALID; 1350 uint64_t flags = AMDGPU_PTE_VALID;
1351 unsigned eng = ring->vm_inv_eng; 1351 unsigned eng = ring->vm_inv_eng;
1352 1352
@@ -1354,15 +1354,15 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1354 pd_addr |= flags; 1354 pd_addr |= flags;
1355 1355
1356 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE); 1356 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
1357 amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2); 1357 amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2);
1358 amdgpu_ring_write(ring, upper_32_bits(pd_addr)); 1358 amdgpu_ring_write(ring, upper_32_bits(pd_addr));
1359 1359
1360 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE); 1360 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
1361 amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2); 1361 amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
1362 amdgpu_ring_write(ring, lower_32_bits(pd_addr)); 1362 amdgpu_ring_write(ring, lower_32_bits(pd_addr));
1363 1363
1364 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT); 1364 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
1365 amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2); 1365 amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
1366 amdgpu_ring_write(ring, 0xffffffff); 1366 amdgpu_ring_write(ring, 0xffffffff);
1367 amdgpu_ring_write(ring, lower_32_bits(pd_addr)); 1367 amdgpu_ring_write(ring, lower_32_bits(pd_addr));
1368 1368
@@ -1374,8 +1374,8 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1374 /* wait for flush */ 1374 /* wait for flush */
1375 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT); 1375 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
1376 amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2); 1376 amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
1377 amdgpu_ring_write(ring, 1 << vm_id); 1377 amdgpu_ring_write(ring, 1 << vmid);
1378 amdgpu_ring_write(ring, 1 << vm_id); 1378 amdgpu_ring_write(ring, 1 << vmid);
1379} 1379}
1380 1380
1381#if 0 1381#if 0
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index cf81065e3c5a..a5355eb689f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -834,24 +834,24 @@ out:
834} 834}
835 835
836static void vce_v3_0_ring_emit_ib(struct amdgpu_ring *ring, 836static void vce_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
837 struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch) 837 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
838{ 838{
839 amdgpu_ring_write(ring, VCE_CMD_IB_VM); 839 amdgpu_ring_write(ring, VCE_CMD_IB_VM);
840 amdgpu_ring_write(ring, vm_id); 840 amdgpu_ring_write(ring, vmid);
841 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 841 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
842 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 842 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
843 amdgpu_ring_write(ring, ib->length_dw); 843 amdgpu_ring_write(ring, ib->length_dw);
844} 844}
845 845
846static void vce_v3_0_emit_vm_flush(struct amdgpu_ring *ring, 846static void vce_v3_0_emit_vm_flush(struct amdgpu_ring *ring,
847 unsigned int vm_id, uint64_t pd_addr) 847 unsigned int vmid, uint64_t pd_addr)
848{ 848{
849 amdgpu_ring_write(ring, VCE_CMD_UPDATE_PTB); 849 amdgpu_ring_write(ring, VCE_CMD_UPDATE_PTB);
850 amdgpu_ring_write(ring, vm_id); 850 amdgpu_ring_write(ring, vmid);
851 amdgpu_ring_write(ring, pd_addr >> 12); 851 amdgpu_ring_write(ring, pd_addr >> 12);
852 852
853 amdgpu_ring_write(ring, VCE_CMD_FLUSH_TLB); 853 amdgpu_ring_write(ring, VCE_CMD_FLUSH_TLB);
854 amdgpu_ring_write(ring, vm_id); 854 amdgpu_ring_write(ring, vmid);
855 amdgpu_ring_write(ring, VCE_CMD_END); 855 amdgpu_ring_write(ring, VCE_CMD_END);
856} 856}
857 857
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 308949d6edde..7cf2eef68cf2 100755
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -938,10 +938,10 @@ static int vce_v4_0_set_powergating_state(void *handle,
938#endif 938#endif
939 939
940static void vce_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 940static void vce_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
941 struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch) 941 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
942{ 942{
943 amdgpu_ring_write(ring, VCE_CMD_IB_VM); 943 amdgpu_ring_write(ring, VCE_CMD_IB_VM);
944 amdgpu_ring_write(ring, vm_id); 944 amdgpu_ring_write(ring, vmid);
945 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 945 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
946 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 946 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
947 amdgpu_ring_write(ring, ib->length_dw); 947 amdgpu_ring_write(ring, ib->length_dw);
@@ -965,10 +965,10 @@ static void vce_v4_0_ring_insert_end(struct amdgpu_ring *ring)
965} 965}
966 966
967static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring, 967static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring,
968 unsigned int vm_id, uint64_t pd_addr) 968 unsigned int vmid, uint64_t pd_addr)
969{ 969{
970 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 970 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
971 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); 971 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
972 uint64_t flags = AMDGPU_PTE_VALID; 972 uint64_t flags = AMDGPU_PTE_VALID;
973 unsigned eng = ring->vm_inv_eng; 973 unsigned eng = ring->vm_inv_eng;
974 974
@@ -976,15 +976,15 @@ static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring,
976 pd_addr |= flags; 976 pd_addr |= flags;
977 977
978 amdgpu_ring_write(ring, VCE_CMD_REG_WRITE); 978 amdgpu_ring_write(ring, VCE_CMD_REG_WRITE);
979 amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2); 979 amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2);
980 amdgpu_ring_write(ring, upper_32_bits(pd_addr)); 980 amdgpu_ring_write(ring, upper_32_bits(pd_addr));
981 981
982 amdgpu_ring_write(ring, VCE_CMD_REG_WRITE); 982 amdgpu_ring_write(ring, VCE_CMD_REG_WRITE);
983 amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2); 983 amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
984 amdgpu_ring_write(ring, lower_32_bits(pd_addr)); 984 amdgpu_ring_write(ring, lower_32_bits(pd_addr));
985 985
986 amdgpu_ring_write(ring, VCE_CMD_REG_WAIT); 986 amdgpu_ring_write(ring, VCE_CMD_REG_WAIT);
987 amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2); 987 amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
988 amdgpu_ring_write(ring, 0xffffffff); 988 amdgpu_ring_write(ring, 0xffffffff);
989 amdgpu_ring_write(ring, lower_32_bits(pd_addr)); 989 amdgpu_ring_write(ring, lower_32_bits(pd_addr));
990 990
@@ -996,8 +996,8 @@ static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring,
996 /* wait for flush */ 996 /* wait for flush */
997 amdgpu_ring_write(ring, VCE_CMD_REG_WAIT); 997 amdgpu_ring_write(ring, VCE_CMD_REG_WAIT);
998 amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2); 998 amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
999 amdgpu_ring_write(ring, 1 << vm_id); 999 amdgpu_ring_write(ring, 1 << vmid);
1000 amdgpu_ring_write(ring, 1 << vm_id); 1000 amdgpu_ring_write(ring, 1 << vmid);
1001} 1001}
1002 1002
1003static int vce_v4_0_set_interrupt_state(struct amdgpu_device *adev, 1003static int vce_v4_0_set_interrupt_state(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index deb3fba790a5..b99e15c43e45 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -833,13 +833,13 @@ static void vcn_v1_0_dec_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
833 */ 833 */
834static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 834static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
835 struct amdgpu_ib *ib, 835 struct amdgpu_ib *ib,
836 unsigned vm_id, bool ctx_switch) 836 unsigned vmid, bool ctx_switch)
837{ 837{
838 struct amdgpu_device *adev = ring->adev; 838 struct amdgpu_device *adev = ring->adev;
839 839
840 amdgpu_ring_write(ring, 840 amdgpu_ring_write(ring,
841 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0)); 841 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
842 amdgpu_ring_write(ring, vm_id); 842 amdgpu_ring_write(ring, vmid);
843 843
844 amdgpu_ring_write(ring, 844 amdgpu_ring_write(ring,
845 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); 845 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
@@ -888,10 +888,10 @@ static void vcn_v1_0_dec_vm_reg_wait(struct amdgpu_ring *ring,
888} 888}
889 889
890static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 890static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
891 unsigned vm_id, uint64_t pd_addr) 891 unsigned vmid, uint64_t pd_addr)
892{ 892{
893 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 893 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
894 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); 894 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
895 uint64_t flags = AMDGPU_PTE_VALID; 895 uint64_t flags = AMDGPU_PTE_VALID;
896 unsigned eng = ring->vm_inv_eng; 896 unsigned eng = ring->vm_inv_eng;
897 uint32_t data0, data1, mask; 897 uint32_t data0, data1, mask;
@@ -899,15 +899,15 @@ static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
899 amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags); 899 amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
900 pd_addr |= flags; 900 pd_addr |= flags;
901 901
902 data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2; 902 data0 = (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2;
903 data1 = upper_32_bits(pd_addr); 903 data1 = upper_32_bits(pd_addr);
904 vcn_v1_0_dec_vm_reg_write(ring, data0, data1); 904 vcn_v1_0_dec_vm_reg_write(ring, data0, data1);
905 905
906 data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2; 906 data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
907 data1 = lower_32_bits(pd_addr); 907 data1 = lower_32_bits(pd_addr);
908 vcn_v1_0_dec_vm_reg_write(ring, data0, data1); 908 vcn_v1_0_dec_vm_reg_write(ring, data0, data1);
909 909
910 data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2; 910 data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
911 data1 = lower_32_bits(pd_addr); 911 data1 = lower_32_bits(pd_addr);
912 mask = 0xffffffff; 912 mask = 0xffffffff;
913 vcn_v1_0_dec_vm_reg_wait(ring, data0, data1, mask); 913 vcn_v1_0_dec_vm_reg_wait(ring, data0, data1, mask);
@@ -919,8 +919,8 @@ static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
919 919
920 /* wait for flush */ 920 /* wait for flush */
921 data0 = (hub->vm_inv_eng0_ack + eng) << 2; 921 data0 = (hub->vm_inv_eng0_ack + eng) << 2;
922 data1 = 1 << vm_id; 922 data1 = 1 << vmid;
923 mask = 1 << vm_id; 923 mask = 1 << vmid;
924 vcn_v1_0_dec_vm_reg_wait(ring, data0, data1, mask); 924 vcn_v1_0_dec_vm_reg_wait(ring, data0, data1, mask);
925} 925}
926 926
@@ -1011,20 +1011,20 @@ static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1011 * Write enc ring commands to execute the indirect buffer 1011 * Write enc ring commands to execute the indirect buffer
1012 */ 1012 */
1013static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1013static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1014 struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch) 1014 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
1015{ 1015{
1016 amdgpu_ring_write(ring, VCN_ENC_CMD_IB); 1016 amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1017 amdgpu_ring_write(ring, vm_id); 1017 amdgpu_ring_write(ring, vmid);
1018 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1018 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1019 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1019 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1020 amdgpu_ring_write(ring, ib->length_dw); 1020 amdgpu_ring_write(ring, ib->length_dw);
1021} 1021}
1022 1022
1023static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1023static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1024 unsigned int vm_id, uint64_t pd_addr) 1024 unsigned int vmid, uint64_t pd_addr)
1025{ 1025{
1026 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1026 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1027 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); 1027 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
1028 uint64_t flags = AMDGPU_PTE_VALID; 1028 uint64_t flags = AMDGPU_PTE_VALID;
1029 unsigned eng = ring->vm_inv_eng; 1029 unsigned eng = ring->vm_inv_eng;
1030 1030
@@ -1033,17 +1033,17 @@ static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1033 1033
1034 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1034 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1035 amdgpu_ring_write(ring, 1035 amdgpu_ring_write(ring,
1036 (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2); 1036 (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2);
1037 amdgpu_ring_write(ring, upper_32_bits(pd_addr)); 1037 amdgpu_ring_write(ring, upper_32_bits(pd_addr));
1038 1038
1039 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1039 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1040 amdgpu_ring_write(ring, 1040 amdgpu_ring_write(ring,
1041 (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2); 1041 (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
1042 amdgpu_ring_write(ring, lower_32_bits(pd_addr)); 1042 amdgpu_ring_write(ring, lower_32_bits(pd_addr));
1043 1043
1044 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1044 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1045 amdgpu_ring_write(ring, 1045 amdgpu_ring_write(ring,
1046 (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2); 1046 (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
1047 amdgpu_ring_write(ring, 0xffffffff); 1047 amdgpu_ring_write(ring, 0xffffffff);
1048 amdgpu_ring_write(ring, lower_32_bits(pd_addr)); 1048 amdgpu_ring_write(ring, lower_32_bits(pd_addr));
1049 1049
@@ -1055,8 +1055,8 @@ static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1055 /* wait for flush */ 1055 /* wait for flush */
1056 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1056 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1057 amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2); 1057 amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
1058 amdgpu_ring_write(ring, 1 << vm_id); 1058 amdgpu_ring_write(ring, 1 << vmid);
1059 amdgpu_ring_write(ring, 1 << vm_id); 1059 amdgpu_ring_write(ring, 1 << vmid);
1060} 1060}
1061 1061
1062static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev, 1062static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index e1d7dae0989b..b69ceafb7888 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -327,8 +327,8 @@ static void vega10_ih_decode_iv(struct amdgpu_device *adev,
327 entry->client_id = dw[0] & 0xff; 327 entry->client_id = dw[0] & 0xff;
328 entry->src_id = (dw[0] >> 8) & 0xff; 328 entry->src_id = (dw[0] >> 8) & 0xff;
329 entry->ring_id = (dw[0] >> 16) & 0xff; 329 entry->ring_id = (dw[0] >> 16) & 0xff;
330 entry->vm_id = (dw[0] >> 24) & 0xf; 330 entry->vmid = (dw[0] >> 24) & 0xf;
331 entry->vm_id_src = (dw[0] >> 31); 331 entry->vmid_src = (dw[0] >> 31);
332 entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 332 entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32);
333 entry->timestamp_src = dw[2] >> 31; 333 entry->timestamp_src = dw[2] >> 31;
334 entry->pas_id = dw[3] & 0xffff; 334 entry->pas_id = dw[3] & 0xffff;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-27 22:47:22 -0400