diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 46550b588982..ff9f1a82630f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | |||
@@ -6245,7 +6245,7 @@ static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) | |||
6245 | 6245 | ||
6246 | static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, | 6246 | static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, |
6247 | struct amdgpu_ib *ib, | 6247 | struct amdgpu_ib *ib, |
6248 | unsigned vm_id, bool ctx_switch) | 6248 | unsigned vmid, bool ctx_switch) |
6249 | { | 6249 | { |
6250 | u32 header, control = 0; | 6250 | u32 header, control = 0; |
6251 | 6251 | ||
@@ -6254,7 +6254,7 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, | |||
6254 | else | 6254 | else |
6255 | header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); | 6255 | header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); |
6256 | 6256 | ||
6257 | control |= ib->length_dw | (vm_id << 24); | 6257 | control |= ib->length_dw | (vmid << 24); |
6258 | 6258 | ||
6259 | if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { | 6259 | if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { |
6260 | control |= INDIRECT_BUFFER_PRE_ENB(1); | 6260 | control |= INDIRECT_BUFFER_PRE_ENB(1); |
@@ -6275,9 +6275,9 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, | |||
6275 | 6275 | ||
6276 | static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring, | 6276 | static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring, |
6277 | struct amdgpu_ib *ib, | 6277 | struct amdgpu_ib *ib, |
6278 | unsigned vm_id, bool ctx_switch) | 6278 | unsigned vmid, bool ctx_switch) |
6279 | { | 6279 | { |
6280 | u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24); | 6280 | u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); |
6281 | 6281 | ||
6282 | amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); | 6282 | amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
6283 | amdgpu_ring_write(ring, | 6283 | amdgpu_ring_write(ring, |
@@ -6328,7 +6328,7 @@ static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) | |||
6328 | } | 6328 | } |
6329 | 6329 | ||
6330 | static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring, | 6330 | static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring, |
6331 | unsigned vm_id, uint64_t pd_addr) | 6331 | unsigned vmid, uint64_t pd_addr) |
6332 | { | 6332 | { |
6333 | int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); | 6333 | int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); |
6334 | 6334 | ||
@@ -6336,12 +6336,12 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring, | |||
6336 | amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | | 6336 | amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | |
6337 | WRITE_DATA_DST_SEL(0)) | | 6337 | WRITE_DATA_DST_SEL(0)) | |
6338 | WR_CONFIRM); | 6338 | WR_CONFIRM); |
6339 | if (vm_id < 8) { | 6339 | if (vmid < 8) { |
6340 | amdgpu_ring_write(ring, | 6340 | amdgpu_ring_write(ring, |
6341 | (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); | 6341 | (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid)); |
6342 | } else { | 6342 | } else { |
6343 | amdgpu_ring_write(ring, | 6343 | amdgpu_ring_write(ring, |
6344 | (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); | 6344 | (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8)); |
6345 | } | 6345 | } |
6346 | amdgpu_ring_write(ring, 0); | 6346 | amdgpu_ring_write(ring, 0); |
6347 | amdgpu_ring_write(ring, pd_addr >> 12); | 6347 | amdgpu_ring_write(ring, pd_addr >> 12); |
@@ -6353,7 +6353,7 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring, | |||
6353 | WRITE_DATA_DST_SEL(0))); | 6353 | WRITE_DATA_DST_SEL(0))); |
6354 | amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); | 6354 | amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); |
6355 | amdgpu_ring_write(ring, 0); | 6355 | amdgpu_ring_write(ring, 0); |
6356 | amdgpu_ring_write(ring, 1 << vm_id); | 6356 | amdgpu_ring_write(ring, 1 << vmid); |
6357 | 6357 | ||
6358 | /* wait for the invalidate to complete */ | 6358 | /* wait for the invalidate to complete */ |
6359 | amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); | 6359 | amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); |