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path: root/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/cik_sdma.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik_sdma.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index e406c93d01d6..6e8278e689b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -221,9 +221,9 @@ static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
221 */ 221 */
222static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring, 222static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
223 struct amdgpu_ib *ib, 223 struct amdgpu_ib *ib,
224 unsigned vm_id, bool ctx_switch) 224 unsigned vmid, bool ctx_switch)
225{ 225{
226 u32 extra_bits = vm_id & 0xf; 226 u32 extra_bits = vmid & 0xf;
227 227
228 /* IB packet must end on a 8 DW boundary */ 228 /* IB packet must end on a 8 DW boundary */
229 cik_sdma_ring_insert_nop(ring, (12 - (lower_32_bits(ring->wptr) & 7)) % 8); 229 cik_sdma_ring_insert_nop(ring, (12 - (lower_32_bits(ring->wptr) & 7)) % 8);
@@ -880,23 +880,23 @@ static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
880 * using sDMA (CIK). 880 * using sDMA (CIK).
881 */ 881 */
882static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring, 882static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
883 unsigned vm_id, uint64_t pd_addr) 883 unsigned vmid, uint64_t pd_addr)
884{ 884{
885 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) | 885 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
886 SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */ 886 SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
887 887
888 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 888 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
889 if (vm_id < 8) { 889 if (vmid < 8) {
890 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); 890 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
891 } else { 891 } else {
892 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); 892 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8));
893 } 893 }
894 amdgpu_ring_write(ring, pd_addr >> 12); 894 amdgpu_ring_write(ring, pd_addr >> 12);
895 895
896 /* flush TLB */ 896 /* flush TLB */
897 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 897 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
898 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 898 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
899 amdgpu_ring_write(ring, 1 << vm_id); 899 amdgpu_ring_write(ring, 1 << vmid);
900 900
901 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); 901 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
902 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 902 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);