aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index edef17d93527..9870d83b68c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -1874,7 +1874,7 @@ static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1874 1874
1875static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 1875static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1876 struct amdgpu_ib *ib, 1876 struct amdgpu_ib *ib,
1877 unsigned vm_id, bool ctx_switch) 1877 unsigned vmid, bool ctx_switch)
1878{ 1878{
1879 u32 header, control = 0; 1879 u32 header, control = 0;
1880 1880
@@ -1889,7 +1889,7 @@ static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1889 else 1889 else
1890 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 1890 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1891 1891
1892 control |= ib->length_dw | (vm_id << 24); 1892 control |= ib->length_dw | (vmid << 24);
1893 1893
1894 amdgpu_ring_write(ring, header); 1894 amdgpu_ring_write(ring, header);
1895 amdgpu_ring_write(ring, 1895 amdgpu_ring_write(ring,
@@ -2354,7 +2354,7 @@ static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2354} 2354}
2355 2355
2356static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 2356static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2357 unsigned vm_id, uint64_t pd_addr) 2357 unsigned vmid, uint64_t pd_addr)
2358{ 2358{
2359 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2359 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2360 2360
@@ -2362,10 +2362,10 @@ static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2362 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2362 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2363 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 2363 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
2364 WRITE_DATA_DST_SEL(0))); 2364 WRITE_DATA_DST_SEL(0)));
2365 if (vm_id < 8) { 2365 if (vmid < 8) {
2366 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id )); 2366 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid ));
2367 } else { 2367 } else {
2368 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8))); 2368 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8)));
2369 } 2369 }
2370 amdgpu_ring_write(ring, 0); 2370 amdgpu_ring_write(ring, 0);
2371 amdgpu_ring_write(ring, pd_addr >> 12); 2371 amdgpu_ring_write(ring, pd_addr >> 12);
@@ -2376,7 +2376,7 @@ static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2376 WRITE_DATA_DST_SEL(0))); 2376 WRITE_DATA_DST_SEL(0)));
2377 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 2377 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
2378 amdgpu_ring_write(ring, 0); 2378 amdgpu_ring_write(ring, 0);
2379 amdgpu_ring_write(ring, 1 << vm_id); 2379 amdgpu_ring_write(ring, 1 << vmid);
2380 2380
2381 /* wait for the invalidate to complete */ 2381 /* wait for the invalidate to complete */
2382 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2382 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));