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authorChristian König <christian.koenig@amd.com>2017-11-03 10:59:25 -0400
committerAlex Deucher <alexander.deucher@amd.com>2017-12-06 12:47:21 -0500
commitc47b41a79ab5e8faec9aea6c4a06c4d1e4d1132f (patch)
tree97820364b390c2b55ace5d1d27faf14c1f8193fb
parent6f16b4fb60011cbc7d4530e112739ea4416c6ea6 (diff)
drm/amdgpu: remove nonsense const u32 cast on ARRAY_SIZE result
Not sure what that should originally been good for, but it doesn't seem to make any sense any more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik.c40
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v10_0.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v11_0.c10
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c38
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c18
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c12
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c20
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si.c34
-rw-r--r--drivers/gpu/drm/amd/amdgpu/soc15.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.c10
15 files changed, 113 insertions, 113 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index a296f7bbe57c..8ba056a2a5da 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -757,72 +757,72 @@ static void cik_init_golden_registers(struct amdgpu_device *adev)
757 case CHIP_BONAIRE: 757 case CHIP_BONAIRE:
758 amdgpu_program_register_sequence(adev, 758 amdgpu_program_register_sequence(adev,
759 bonaire_mgcg_cgcg_init, 759 bonaire_mgcg_cgcg_init,
760 (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init)); 760 ARRAY_SIZE(bonaire_mgcg_cgcg_init));
761 amdgpu_program_register_sequence(adev, 761 amdgpu_program_register_sequence(adev,
762 bonaire_golden_registers, 762 bonaire_golden_registers,
763 (const u32)ARRAY_SIZE(bonaire_golden_registers)); 763 ARRAY_SIZE(bonaire_golden_registers));
764 amdgpu_program_register_sequence(adev, 764 amdgpu_program_register_sequence(adev,
765 bonaire_golden_common_registers, 765 bonaire_golden_common_registers,
766 (const u32)ARRAY_SIZE(bonaire_golden_common_registers)); 766 ARRAY_SIZE(bonaire_golden_common_registers));
767 amdgpu_program_register_sequence(adev, 767 amdgpu_program_register_sequence(adev,
768 bonaire_golden_spm_registers, 768 bonaire_golden_spm_registers,
769 (const u32)ARRAY_SIZE(bonaire_golden_spm_registers)); 769 ARRAY_SIZE(bonaire_golden_spm_registers));
770 break; 770 break;
771 case CHIP_KABINI: 771 case CHIP_KABINI:
772 amdgpu_program_register_sequence(adev, 772 amdgpu_program_register_sequence(adev,
773 kalindi_mgcg_cgcg_init, 773 kalindi_mgcg_cgcg_init,
774 (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init)); 774 ARRAY_SIZE(kalindi_mgcg_cgcg_init));
775 amdgpu_program_register_sequence(adev, 775 amdgpu_program_register_sequence(adev,
776 kalindi_golden_registers, 776 kalindi_golden_registers,
777 (const u32)ARRAY_SIZE(kalindi_golden_registers)); 777 ARRAY_SIZE(kalindi_golden_registers));
778 amdgpu_program_register_sequence(adev, 778 amdgpu_program_register_sequence(adev,
779 kalindi_golden_common_registers, 779 kalindi_golden_common_registers,
780 (const u32)ARRAY_SIZE(kalindi_golden_common_registers)); 780 ARRAY_SIZE(kalindi_golden_common_registers));
781 amdgpu_program_register_sequence(adev, 781 amdgpu_program_register_sequence(adev,
782 kalindi_golden_spm_registers, 782 kalindi_golden_spm_registers,
783 (const u32)ARRAY_SIZE(kalindi_golden_spm_registers)); 783 ARRAY_SIZE(kalindi_golden_spm_registers));
784 break; 784 break;
785 case CHIP_MULLINS: 785 case CHIP_MULLINS:
786 amdgpu_program_register_sequence(adev, 786 amdgpu_program_register_sequence(adev,
787 kalindi_mgcg_cgcg_init, 787 kalindi_mgcg_cgcg_init,
788 (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init)); 788 ARRAY_SIZE(kalindi_mgcg_cgcg_init));
789 amdgpu_program_register_sequence(adev, 789 amdgpu_program_register_sequence(adev,
790 godavari_golden_registers, 790 godavari_golden_registers,
791 (const u32)ARRAY_SIZE(godavari_golden_registers)); 791 ARRAY_SIZE(godavari_golden_registers));
792 amdgpu_program_register_sequence(adev, 792 amdgpu_program_register_sequence(adev,
793 kalindi_golden_common_registers, 793 kalindi_golden_common_registers,
794 (const u32)ARRAY_SIZE(kalindi_golden_common_registers)); 794 ARRAY_SIZE(kalindi_golden_common_registers));
795 amdgpu_program_register_sequence(adev, 795 amdgpu_program_register_sequence(adev,
796 kalindi_golden_spm_registers, 796 kalindi_golden_spm_registers,
797 (const u32)ARRAY_SIZE(kalindi_golden_spm_registers)); 797 ARRAY_SIZE(kalindi_golden_spm_registers));
798 break; 798 break;
799 case CHIP_KAVERI: 799 case CHIP_KAVERI:
800 amdgpu_program_register_sequence(adev, 800 amdgpu_program_register_sequence(adev,
801 spectre_mgcg_cgcg_init, 801 spectre_mgcg_cgcg_init,
802 (const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init)); 802 ARRAY_SIZE(spectre_mgcg_cgcg_init));
803 amdgpu_program_register_sequence(adev, 803 amdgpu_program_register_sequence(adev,
804 spectre_golden_registers, 804 spectre_golden_registers,
805 (const u32)ARRAY_SIZE(spectre_golden_registers)); 805 ARRAY_SIZE(spectre_golden_registers));
806 amdgpu_program_register_sequence(adev, 806 amdgpu_program_register_sequence(adev,
807 spectre_golden_common_registers, 807 spectre_golden_common_registers,
808 (const u32)ARRAY_SIZE(spectre_golden_common_registers)); 808 ARRAY_SIZE(spectre_golden_common_registers));
809 amdgpu_program_register_sequence(adev, 809 amdgpu_program_register_sequence(adev,
810 spectre_golden_spm_registers, 810 spectre_golden_spm_registers,
811 (const u32)ARRAY_SIZE(spectre_golden_spm_registers)); 811 ARRAY_SIZE(spectre_golden_spm_registers));
812 break; 812 break;
813 case CHIP_HAWAII: 813 case CHIP_HAWAII:
814 amdgpu_program_register_sequence(adev, 814 amdgpu_program_register_sequence(adev,
815 hawaii_mgcg_cgcg_init, 815 hawaii_mgcg_cgcg_init,
816 (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init)); 816 ARRAY_SIZE(hawaii_mgcg_cgcg_init));
817 amdgpu_program_register_sequence(adev, 817 amdgpu_program_register_sequence(adev,
818 hawaii_golden_registers, 818 hawaii_golden_registers,
819 (const u32)ARRAY_SIZE(hawaii_golden_registers)); 819 ARRAY_SIZE(hawaii_golden_registers));
820 amdgpu_program_register_sequence(adev, 820 amdgpu_program_register_sequence(adev,
821 hawaii_golden_common_registers, 821 hawaii_golden_common_registers,
822 (const u32)ARRAY_SIZE(hawaii_golden_common_registers)); 822 ARRAY_SIZE(hawaii_golden_common_registers));
823 amdgpu_program_register_sequence(adev, 823 amdgpu_program_register_sequence(adev,
824 hawaii_golden_spm_registers, 824 hawaii_golden_spm_registers,
825 (const u32)ARRAY_SIZE(hawaii_golden_spm_registers)); 825 ARRAY_SIZE(hawaii_golden_spm_registers));
826 break; 826 break;
827 default: 827 default:
828 break; 828 break;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index f3dd6b7bfd4d..a397111c2ced 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -147,18 +147,18 @@ static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
147 case CHIP_FIJI: 147 case CHIP_FIJI:
148 amdgpu_program_register_sequence(adev, 148 amdgpu_program_register_sequence(adev,
149 fiji_mgcg_cgcg_init, 149 fiji_mgcg_cgcg_init,
150 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); 150 ARRAY_SIZE(fiji_mgcg_cgcg_init));
151 amdgpu_program_register_sequence(adev, 151 amdgpu_program_register_sequence(adev,
152 golden_settings_fiji_a10, 152 golden_settings_fiji_a10,
153 (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); 153 ARRAY_SIZE(golden_settings_fiji_a10));
154 break; 154 break;
155 case CHIP_TONGA: 155 case CHIP_TONGA:
156 amdgpu_program_register_sequence(adev, 156 amdgpu_program_register_sequence(adev,
157 tonga_mgcg_cgcg_init, 157 tonga_mgcg_cgcg_init,
158 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); 158 ARRAY_SIZE(tonga_mgcg_cgcg_init));
159 amdgpu_program_register_sequence(adev, 159 amdgpu_program_register_sequence(adev,
160 golden_settings_tonga_a11, 160 golden_settings_tonga_a11,
161 (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); 161 ARRAY_SIZE(golden_settings_tonga_a11));
162 break; 162 break;
163 default: 163 default:
164 break; 164 break;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index be25706e5f07..67e670989e81 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -156,26 +156,26 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
156 case CHIP_CARRIZO: 156 case CHIP_CARRIZO:
157 amdgpu_program_register_sequence(adev, 157 amdgpu_program_register_sequence(adev,
158 cz_mgcg_cgcg_init, 158 cz_mgcg_cgcg_init,
159 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 159 ARRAY_SIZE(cz_mgcg_cgcg_init));
160 amdgpu_program_register_sequence(adev, 160 amdgpu_program_register_sequence(adev,
161 cz_golden_settings_a11, 161 cz_golden_settings_a11,
162 (const u32)ARRAY_SIZE(cz_golden_settings_a11)); 162 ARRAY_SIZE(cz_golden_settings_a11));
163 break; 163 break;
164 case CHIP_STONEY: 164 case CHIP_STONEY:
165 amdgpu_program_register_sequence(adev, 165 amdgpu_program_register_sequence(adev,
166 stoney_golden_settings_a11, 166 stoney_golden_settings_a11,
167 (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); 167 ARRAY_SIZE(stoney_golden_settings_a11));
168 break; 168 break;
169 case CHIP_POLARIS11: 169 case CHIP_POLARIS11:
170 case CHIP_POLARIS12: 170 case CHIP_POLARIS12:
171 amdgpu_program_register_sequence(adev, 171 amdgpu_program_register_sequence(adev,
172 polaris11_golden_settings_a11, 172 polaris11_golden_settings_a11,
173 (const u32)ARRAY_SIZE(polaris11_golden_settings_a11)); 173 ARRAY_SIZE(polaris11_golden_settings_a11));
174 break; 174 break;
175 case CHIP_POLARIS10: 175 case CHIP_POLARIS10:
176 amdgpu_program_register_sequence(adev, 176 amdgpu_program_register_sequence(adev,
177 polaris10_golden_settings_a11, 177 polaris10_golden_settings_a11,
178 (const u32)ARRAY_SIZE(polaris10_golden_settings_a11)); 178 ARRAY_SIZE(polaris10_golden_settings_a11));
179 break; 179 break;
180 default: 180 default:
181 break; 181 break;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 96a3345e872e..426e51866a15 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -681,53 +681,53 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
681 case CHIP_TOPAZ: 681 case CHIP_TOPAZ:
682 amdgpu_program_register_sequence(adev, 682 amdgpu_program_register_sequence(adev,
683 iceland_mgcg_cgcg_init, 683 iceland_mgcg_cgcg_init,
684 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); 684 ARRAY_SIZE(iceland_mgcg_cgcg_init));
685 amdgpu_program_register_sequence(adev, 685 amdgpu_program_register_sequence(adev,
686 golden_settings_iceland_a11, 686 golden_settings_iceland_a11,
687 (const u32)ARRAY_SIZE(golden_settings_iceland_a11)); 687 ARRAY_SIZE(golden_settings_iceland_a11));
688 amdgpu_program_register_sequence(adev, 688 amdgpu_program_register_sequence(adev,
689 iceland_golden_common_all, 689 iceland_golden_common_all,
690 (const u32)ARRAY_SIZE(iceland_golden_common_all)); 690 ARRAY_SIZE(iceland_golden_common_all));
691 break; 691 break;
692 case CHIP_FIJI: 692 case CHIP_FIJI:
693 amdgpu_program_register_sequence(adev, 693 amdgpu_program_register_sequence(adev,
694 fiji_mgcg_cgcg_init, 694 fiji_mgcg_cgcg_init,
695 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); 695 ARRAY_SIZE(fiji_mgcg_cgcg_init));
696 amdgpu_program_register_sequence(adev, 696 amdgpu_program_register_sequence(adev,
697 golden_settings_fiji_a10, 697 golden_settings_fiji_a10,
698 (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); 698 ARRAY_SIZE(golden_settings_fiji_a10));
699 amdgpu_program_register_sequence(adev, 699 amdgpu_program_register_sequence(adev,
700 fiji_golden_common_all, 700 fiji_golden_common_all,
701 (const u32)ARRAY_SIZE(fiji_golden_common_all)); 701 ARRAY_SIZE(fiji_golden_common_all));
702 break; 702 break;
703 703
704 case CHIP_TONGA: 704 case CHIP_TONGA:
705 amdgpu_program_register_sequence(adev, 705 amdgpu_program_register_sequence(adev,
706 tonga_mgcg_cgcg_init, 706 tonga_mgcg_cgcg_init,
707 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); 707 ARRAY_SIZE(tonga_mgcg_cgcg_init));
708 amdgpu_program_register_sequence(adev, 708 amdgpu_program_register_sequence(adev,
709 golden_settings_tonga_a11, 709 golden_settings_tonga_a11,
710 (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); 710 ARRAY_SIZE(golden_settings_tonga_a11));
711 amdgpu_program_register_sequence(adev, 711 amdgpu_program_register_sequence(adev,
712 tonga_golden_common_all, 712 tonga_golden_common_all,
713 (const u32)ARRAY_SIZE(tonga_golden_common_all)); 713 ARRAY_SIZE(tonga_golden_common_all));
714 break; 714 break;
715 case CHIP_POLARIS11: 715 case CHIP_POLARIS11:
716 case CHIP_POLARIS12: 716 case CHIP_POLARIS12:
717 amdgpu_program_register_sequence(adev, 717 amdgpu_program_register_sequence(adev,
718 golden_settings_polaris11_a11, 718 golden_settings_polaris11_a11,
719 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); 719 ARRAY_SIZE(golden_settings_polaris11_a11));
720 amdgpu_program_register_sequence(adev, 720 amdgpu_program_register_sequence(adev,
721 polaris11_golden_common_all, 721 polaris11_golden_common_all,
722 (const u32)ARRAY_SIZE(polaris11_golden_common_all)); 722 ARRAY_SIZE(polaris11_golden_common_all));
723 break; 723 break;
724 case CHIP_POLARIS10: 724 case CHIP_POLARIS10:
725 amdgpu_program_register_sequence(adev, 725 amdgpu_program_register_sequence(adev,
726 golden_settings_polaris10_a11, 726 golden_settings_polaris10_a11,
727 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); 727 ARRAY_SIZE(golden_settings_polaris10_a11));
728 amdgpu_program_register_sequence(adev, 728 amdgpu_program_register_sequence(adev,
729 polaris10_golden_common_all, 729 polaris10_golden_common_all,
730 (const u32)ARRAY_SIZE(polaris10_golden_common_all)); 730 ARRAY_SIZE(polaris10_golden_common_all));
731 WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C); 731 WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C);
732 if (adev->pdev->revision == 0xc7 && 732 if (adev->pdev->revision == 0xc7 &&
733 ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) || 733 ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) ||
@@ -740,24 +740,24 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
740 case CHIP_CARRIZO: 740 case CHIP_CARRIZO:
741 amdgpu_program_register_sequence(adev, 741 amdgpu_program_register_sequence(adev,
742 cz_mgcg_cgcg_init, 742 cz_mgcg_cgcg_init,
743 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 743 ARRAY_SIZE(cz_mgcg_cgcg_init));
744 amdgpu_program_register_sequence(adev, 744 amdgpu_program_register_sequence(adev,
745 cz_golden_settings_a11, 745 cz_golden_settings_a11,
746 (const u32)ARRAY_SIZE(cz_golden_settings_a11)); 746 ARRAY_SIZE(cz_golden_settings_a11));
747 amdgpu_program_register_sequence(adev, 747 amdgpu_program_register_sequence(adev,
748 cz_golden_common_all, 748 cz_golden_common_all,
749 (const u32)ARRAY_SIZE(cz_golden_common_all)); 749 ARRAY_SIZE(cz_golden_common_all));
750 break; 750 break;
751 case CHIP_STONEY: 751 case CHIP_STONEY:
752 amdgpu_program_register_sequence(adev, 752 amdgpu_program_register_sequence(adev,
753 stoney_mgcg_cgcg_init, 753 stoney_mgcg_cgcg_init,
754 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); 754 ARRAY_SIZE(stoney_mgcg_cgcg_init));
755 amdgpu_program_register_sequence(adev, 755 amdgpu_program_register_sequence(adev,
756 stoney_golden_settings_a11, 756 stoney_golden_settings_a11,
757 (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); 757 ARRAY_SIZE(stoney_golden_settings_a11));
758 amdgpu_program_register_sequence(adev, 758 amdgpu_program_register_sequence(adev,
759 stoney_golden_common_all, 759 stoney_golden_common_all,
760 (const u32)ARRAY_SIZE(stoney_golden_common_all)); 760 ARRAY_SIZE(stoney_golden_common_all));
761 break; 761 break;
762 default: 762 default:
763 break; 763 break;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 19a619f759f6..5ba24792f801 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -232,18 +232,18 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
232 case CHIP_VEGA10: 232 case CHIP_VEGA10:
233 amdgpu_program_register_sequence(adev, 233 amdgpu_program_register_sequence(adev,
234 golden_settings_gc_9_0, 234 golden_settings_gc_9_0,
235 (const u32)ARRAY_SIZE(golden_settings_gc_9_0)); 235 ARRAY_SIZE(golden_settings_gc_9_0));
236 amdgpu_program_register_sequence(adev, 236 amdgpu_program_register_sequence(adev,
237 golden_settings_gc_9_0_vg10, 237 golden_settings_gc_9_0_vg10,
238 (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10)); 238 ARRAY_SIZE(golden_settings_gc_9_0_vg10));
239 break; 239 break;
240 case CHIP_RAVEN: 240 case CHIP_RAVEN:
241 amdgpu_program_register_sequence(adev, 241 amdgpu_program_register_sequence(adev,
242 golden_settings_gc_9_1, 242 golden_settings_gc_9_1,
243 (const u32)ARRAY_SIZE(golden_settings_gc_9_1)); 243 ARRAY_SIZE(golden_settings_gc_9_1));
244 amdgpu_program_register_sequence(adev, 244 amdgpu_program_register_sequence(adev,
245 golden_settings_gc_9_1_rv1, 245 golden_settings_gc_9_1_rv1,
246 (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1)); 246 ARRAY_SIZE(golden_settings_gc_9_1_rv1));
247 break; 247 break;
248 default: 248 default:
249 break; 249 break;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 583d87792820..6c6a7e14359c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -69,10 +69,10 @@ static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
69 case CHIP_TOPAZ: 69 case CHIP_TOPAZ:
70 amdgpu_program_register_sequence(adev, 70 amdgpu_program_register_sequence(adev,
71 iceland_mgcg_cgcg_init, 71 iceland_mgcg_cgcg_init,
72 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); 72 ARRAY_SIZE(iceland_mgcg_cgcg_init));
73 amdgpu_program_register_sequence(adev, 73 amdgpu_program_register_sequence(adev,
74 golden_settings_iceland_a11, 74 golden_settings_iceland_a11,
75 (const u32)ARRAY_SIZE(golden_settings_iceland_a11)); 75 ARRAY_SIZE(golden_settings_iceland_a11));
76 break; 76 break;
77 default: 77 default:
78 break; 78 break;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 9ca5fea93ebc..edbe0df24d90 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -122,42 +122,42 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
122 case CHIP_FIJI: 122 case CHIP_FIJI:
123 amdgpu_program_register_sequence(adev, 123 amdgpu_program_register_sequence(adev,
124 fiji_mgcg_cgcg_init, 124 fiji_mgcg_cgcg_init,
125 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); 125 ARRAY_SIZE(fiji_mgcg_cgcg_init));
126 amdgpu_program_register_sequence(adev, 126 amdgpu_program_register_sequence(adev,
127 golden_settings_fiji_a10, 127 golden_settings_fiji_a10,
128 (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); 128 ARRAY_SIZE(golden_settings_fiji_a10));
129 break; 129 break;
130 case CHIP_TONGA: 130 case CHIP_TONGA:
131 amdgpu_program_register_sequence(adev, 131 amdgpu_program_register_sequence(adev,
132 tonga_mgcg_cgcg_init, 132 tonga_mgcg_cgcg_init,
133 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); 133 ARRAY_SIZE(tonga_mgcg_cgcg_init));
134 amdgpu_program_register_sequence(adev, 134 amdgpu_program_register_sequence(adev,
135 golden_settings_tonga_a11, 135 golden_settings_tonga_a11,
136 (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); 136 ARRAY_SIZE(golden_settings_tonga_a11));
137 break; 137 break;
138 case CHIP_POLARIS11: 138 case CHIP_POLARIS11:
139 case CHIP_POLARIS12: 139 case CHIP_POLARIS12:
140 amdgpu_program_register_sequence(adev, 140 amdgpu_program_register_sequence(adev,
141 golden_settings_polaris11_a11, 141 golden_settings_polaris11_a11,
142 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); 142 ARRAY_SIZE(golden_settings_polaris11_a11));
143 break; 143 break;
144 case CHIP_POLARIS10: 144 case CHIP_POLARIS10:
145 amdgpu_program_register_sequence(adev, 145 amdgpu_program_register_sequence(adev,
146 golden_settings_polaris10_a11, 146 golden_settings_polaris10_a11,
147 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); 147 ARRAY_SIZE(golden_settings_polaris10_a11));
148 break; 148 break;
149 case CHIP_CARRIZO: 149 case CHIP_CARRIZO:
150 amdgpu_program_register_sequence(adev, 150 amdgpu_program_register_sequence(adev,
151 cz_mgcg_cgcg_init, 151 cz_mgcg_cgcg_init,
152 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 152 ARRAY_SIZE(cz_mgcg_cgcg_init));
153 break; 153 break;
154 case CHIP_STONEY: 154 case CHIP_STONEY:
155 amdgpu_program_register_sequence(adev, 155 amdgpu_program_register_sequence(adev,
156 stoney_mgcg_cgcg_init, 156 stoney_mgcg_cgcg_init,
157 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); 157 ARRAY_SIZE(stoney_mgcg_cgcg_init));
158 amdgpu_program_register_sequence(adev, 158 amdgpu_program_register_sequence(adev,
159 golden_settings_stoney_common, 159 golden_settings_stoney_common,
160 (const u32)ARRAY_SIZE(golden_settings_stoney_common)); 160 ARRAY_SIZE(golden_settings_stoney_common));
161 break; 161 break;
162 default: 162 default:
163 break; 163 break;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index f11dfd47b517..69c9af7af6f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -696,15 +696,15 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
696 case CHIP_VEGA10: 696 case CHIP_VEGA10:
697 amdgpu_program_register_sequence(adev, 697 amdgpu_program_register_sequence(adev,
698 golden_settings_mmhub_1_0_0, 698 golden_settings_mmhub_1_0_0,
699 (const u32)ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 699 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
700 amdgpu_program_register_sequence(adev, 700 amdgpu_program_register_sequence(adev,
701 golden_settings_athub_1_0_0, 701 golden_settings_athub_1_0_0,
702 (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0)); 702 ARRAY_SIZE(golden_settings_athub_1_0_0));
703 break; 703 break;
704 case CHIP_RAVEN: 704 case CHIP_RAVEN:
705 amdgpu_program_register_sequence(adev, 705 amdgpu_program_register_sequence(adev,
706 golden_settings_athub_1_0_0, 706 golden_settings_athub_1_0_0,
707 (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0)); 707 ARRAY_SIZE(golden_settings_athub_1_0_0));
708 break; 708 break;
709 default: 709 default:
710 break; 710 break;
@@ -724,7 +724,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
724 724
725 amdgpu_program_register_sequence(adev, 725 amdgpu_program_register_sequence(adev,
726 golden_settings_vega10_hdp, 726 golden_settings_vega10_hdp,
727 (const u32)ARRAY_SIZE(golden_settings_vega10_hdp)); 727 ARRAY_SIZE(golden_settings_vega10_hdp));
728 728
729 if (adev->gart.robj == NULL) { 729 if (adev->gart.robj == NULL) {
730 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 730 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
index 2b435c02ef44..df52824c0cd4 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
@@ -281,29 +281,29 @@ void xgpu_vi_init_golden_registers(struct amdgpu_device *adev)
281 case CHIP_FIJI: 281 case CHIP_FIJI:
282 amdgpu_program_register_sequence(adev, 282 amdgpu_program_register_sequence(adev,
283 xgpu_fiji_mgcg_cgcg_init, 283 xgpu_fiji_mgcg_cgcg_init,
284 (const u32)ARRAY_SIZE( 284 ARRAY_SIZE(
285 xgpu_fiji_mgcg_cgcg_init)); 285 xgpu_fiji_mgcg_cgcg_init));
286 amdgpu_program_register_sequence(adev, 286 amdgpu_program_register_sequence(adev,
287 xgpu_fiji_golden_settings_a10, 287 xgpu_fiji_golden_settings_a10,
288 (const u32)ARRAY_SIZE( 288 ARRAY_SIZE(
289 xgpu_fiji_golden_settings_a10)); 289 xgpu_fiji_golden_settings_a10));
290 amdgpu_program_register_sequence(adev, 290 amdgpu_program_register_sequence(adev,
291 xgpu_fiji_golden_common_all, 291 xgpu_fiji_golden_common_all,
292 (const u32)ARRAY_SIZE( 292 ARRAY_SIZE(
293 xgpu_fiji_golden_common_all)); 293 xgpu_fiji_golden_common_all));
294 break; 294 break;
295 case CHIP_TONGA: 295 case CHIP_TONGA:
296 amdgpu_program_register_sequence(adev, 296 amdgpu_program_register_sequence(adev,
297 xgpu_tonga_mgcg_cgcg_init, 297 xgpu_tonga_mgcg_cgcg_init,
298 (const u32)ARRAY_SIZE( 298 ARRAY_SIZE(
299 xgpu_tonga_mgcg_cgcg_init)); 299 xgpu_tonga_mgcg_cgcg_init));
300 amdgpu_program_register_sequence(adev, 300 amdgpu_program_register_sequence(adev,
301 xgpu_tonga_golden_settings_a11, 301 xgpu_tonga_golden_settings_a11,
302 (const u32)ARRAY_SIZE( 302 ARRAY_SIZE(
303 xgpu_tonga_golden_settings_a11)); 303 xgpu_tonga_golden_settings_a11));
304 amdgpu_program_register_sequence(adev, 304 amdgpu_program_register_sequence(adev,
305 xgpu_tonga_golden_common_all, 305 xgpu_tonga_golden_common_all,
306 (const u32)ARRAY_SIZE( 306 ARRAY_SIZE(
307 xgpu_tonga_golden_common_all)); 307 xgpu_tonga_golden_common_all));
308 break; 308 break;
309 default: 309 default:
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 92f8c44a73b6..121e628e7cdb 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -95,10 +95,10 @@ static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
95 case CHIP_TOPAZ: 95 case CHIP_TOPAZ:
96 amdgpu_program_register_sequence(adev, 96 amdgpu_program_register_sequence(adev,
97 iceland_mgcg_cgcg_init, 97 iceland_mgcg_cgcg_init,
98 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); 98 ARRAY_SIZE(iceland_mgcg_cgcg_init));
99 amdgpu_program_register_sequence(adev, 99 amdgpu_program_register_sequence(adev,
100 golden_settings_iceland_a11, 100 golden_settings_iceland_a11,
101 (const u32)ARRAY_SIZE(golden_settings_iceland_a11)); 101 ARRAY_SIZE(golden_settings_iceland_a11));
102 break; 102 break;
103 default: 103 default:
104 break; 104 break;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 52e6bf2e9e59..c8c93f9dac21 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -194,45 +194,45 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
194 case CHIP_FIJI: 194 case CHIP_FIJI:
195 amdgpu_program_register_sequence(adev, 195 amdgpu_program_register_sequence(adev,
196 fiji_mgcg_cgcg_init, 196 fiji_mgcg_cgcg_init,
197 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); 197 ARRAY_SIZE(fiji_mgcg_cgcg_init));
198 amdgpu_program_register_sequence(adev, 198 amdgpu_program_register_sequence(adev,
199 golden_settings_fiji_a10, 199 golden_settings_fiji_a10,
200 (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); 200 ARRAY_SIZE(golden_settings_fiji_a10));
201 break; 201 break;
202 case CHIP_TONGA: 202 case CHIP_TONGA:
203 amdgpu_program_register_sequence(adev, 203 amdgpu_program_register_sequence(adev,
204 tonga_mgcg_cgcg_init, 204 tonga_mgcg_cgcg_init,
205 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); 205 ARRAY_SIZE(tonga_mgcg_cgcg_init));
206 amdgpu_program_register_sequence(adev, 206 amdgpu_program_register_sequence(adev,
207 golden_settings_tonga_a11, 207 golden_settings_tonga_a11,
208 (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); 208 ARRAY_SIZE(golden_settings_tonga_a11));
209 break; 209 break;
210 case CHIP_POLARIS11: 210 case CHIP_POLARIS11:
211 case CHIP_POLARIS12: 211 case CHIP_POLARIS12:
212 amdgpu_program_register_sequence(adev, 212 amdgpu_program_register_sequence(adev,
213 golden_settings_polaris11_a11, 213 golden_settings_polaris11_a11,
214 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); 214 ARRAY_SIZE(golden_settings_polaris11_a11));
215 break; 215 break;
216 case CHIP_POLARIS10: 216 case CHIP_POLARIS10:
217 amdgpu_program_register_sequence(adev, 217 amdgpu_program_register_sequence(adev,
218 golden_settings_polaris10_a11, 218 golden_settings_polaris10_a11,
219 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); 219 ARRAY_SIZE(golden_settings_polaris10_a11));
220 break; 220 break;
221 case CHIP_CARRIZO: 221 case CHIP_CARRIZO:
222 amdgpu_program_register_sequence(adev, 222 amdgpu_program_register_sequence(adev,
223 cz_mgcg_cgcg_init, 223 cz_mgcg_cgcg_init,
224 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 224 ARRAY_SIZE(cz_mgcg_cgcg_init));
225 amdgpu_program_register_sequence(adev, 225 amdgpu_program_register_sequence(adev,
226 cz_golden_settings_a11, 226 cz_golden_settings_a11,
227 (const u32)ARRAY_SIZE(cz_golden_settings_a11)); 227 ARRAY_SIZE(cz_golden_settings_a11));
228 break; 228 break;
229 case CHIP_STONEY: 229 case CHIP_STONEY:
230 amdgpu_program_register_sequence(adev, 230 amdgpu_program_register_sequence(adev,
231 stoney_mgcg_cgcg_init, 231 stoney_mgcg_cgcg_init,
232 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); 232 ARRAY_SIZE(stoney_mgcg_cgcg_init));
233 amdgpu_program_register_sequence(adev, 233 amdgpu_program_register_sequence(adev,
234 stoney_golden_settings_a11, 234 stoney_golden_settings_a11,
235 (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); 235 ARRAY_SIZE(stoney_golden_settings_a11));
236 break; 236 break;
237 default: 237 default:
238 break; 238 break;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index fe78c00b9ffa..a0a5a8da4c4f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -132,18 +132,18 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
132 case CHIP_VEGA10: 132 case CHIP_VEGA10:
133 amdgpu_program_register_sequence(adev, 133 amdgpu_program_register_sequence(adev,
134 golden_settings_sdma_4, 134 golden_settings_sdma_4,
135 (const u32)ARRAY_SIZE(golden_settings_sdma_4)); 135 ARRAY_SIZE(golden_settings_sdma_4));
136 amdgpu_program_register_sequence(adev, 136 amdgpu_program_register_sequence(adev,
137 golden_settings_sdma_vg10, 137 golden_settings_sdma_vg10,
138 (const u32)ARRAY_SIZE(golden_settings_sdma_vg10)); 138 ARRAY_SIZE(golden_settings_sdma_vg10));
139 break; 139 break;
140 case CHIP_RAVEN: 140 case CHIP_RAVEN:
141 amdgpu_program_register_sequence(adev, 141 amdgpu_program_register_sequence(adev,
142 golden_settings_sdma_4_1, 142 golden_settings_sdma_4_1,
143 (const u32)ARRAY_SIZE(golden_settings_sdma_4_1)); 143 ARRAY_SIZE(golden_settings_sdma_4_1));
144 amdgpu_program_register_sequence(adev, 144 amdgpu_program_register_sequence(adev,
145 golden_settings_sdma_rv1, 145 golden_settings_sdma_rv1,
146 (const u32)ARRAY_SIZE(golden_settings_sdma_rv1)); 146 ARRAY_SIZE(golden_settings_sdma_rv1));
147 break; 147 break;
148 default: 148 default:
149 break; 149 break;
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 8284d5dbfc30..49eef3090f08 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1392,63 +1392,63 @@ static void si_init_golden_registers(struct amdgpu_device *adev)
1392 case CHIP_TAHITI: 1392 case CHIP_TAHITI:
1393 amdgpu_program_register_sequence(adev, 1393 amdgpu_program_register_sequence(adev,
1394 tahiti_golden_registers, 1394 tahiti_golden_registers,
1395 (const u32)ARRAY_SIZE(tahiti_golden_registers)); 1395 ARRAY_SIZE(tahiti_golden_registers));
1396 amdgpu_program_register_sequence(adev, 1396 amdgpu_program_register_sequence(adev,
1397 tahiti_golden_rlc_registers, 1397 tahiti_golden_rlc_registers,
1398 (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers)); 1398 ARRAY_SIZE(tahiti_golden_rlc_registers));
1399 amdgpu_program_register_sequence(adev, 1399 amdgpu_program_register_sequence(adev,
1400 tahiti_mgcg_cgcg_init, 1400 tahiti_mgcg_cgcg_init,
1401 (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init)); 1401 ARRAY_SIZE(tahiti_mgcg_cgcg_init));
1402 amdgpu_program_register_sequence(adev, 1402 amdgpu_program_register_sequence(adev,
1403 tahiti_golden_registers2, 1403 tahiti_golden_registers2,
1404 (const u32)ARRAY_SIZE(tahiti_golden_registers2)); 1404 ARRAY_SIZE(tahiti_golden_registers2));
1405 break; 1405 break;
1406 case CHIP_PITCAIRN: 1406 case CHIP_PITCAIRN:
1407 amdgpu_program_register_sequence(adev, 1407 amdgpu_program_register_sequence(adev,
1408 pitcairn_golden_registers, 1408 pitcairn_golden_registers,
1409 (const u32)ARRAY_SIZE(pitcairn_golden_registers)); 1409 ARRAY_SIZE(pitcairn_golden_registers));
1410 amdgpu_program_register_sequence(adev, 1410 amdgpu_program_register_sequence(adev,
1411 pitcairn_golden_rlc_registers, 1411 pitcairn_golden_rlc_registers,
1412 (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers)); 1412 ARRAY_SIZE(pitcairn_golden_rlc_registers));
1413 amdgpu_program_register_sequence(adev, 1413 amdgpu_program_register_sequence(adev,
1414 pitcairn_mgcg_cgcg_init, 1414 pitcairn_mgcg_cgcg_init,
1415 (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init)); 1415 ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
1416 break; 1416 break;
1417 case CHIP_VERDE: 1417 case CHIP_VERDE:
1418 amdgpu_program_register_sequence(adev, 1418 amdgpu_program_register_sequence(adev,
1419 verde_golden_registers, 1419 verde_golden_registers,
1420 (const u32)ARRAY_SIZE(verde_golden_registers)); 1420 ARRAY_SIZE(verde_golden_registers));
1421 amdgpu_program_register_sequence(adev, 1421 amdgpu_program_register_sequence(adev,
1422 verde_golden_rlc_registers, 1422 verde_golden_rlc_registers,
1423 (const u32)ARRAY_SIZE(verde_golden_rlc_registers)); 1423 ARRAY_SIZE(verde_golden_rlc_registers));
1424 amdgpu_program_register_sequence(adev, 1424 amdgpu_program_register_sequence(adev,
1425 verde_mgcg_cgcg_init, 1425 verde_mgcg_cgcg_init,
1426 (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init)); 1426 ARRAY_SIZE(verde_mgcg_cgcg_init));
1427 amdgpu_program_register_sequence(adev, 1427 amdgpu_program_register_sequence(adev,
1428 verde_pg_init, 1428 verde_pg_init,
1429 (const u32)ARRAY_SIZE(verde_pg_init)); 1429 ARRAY_SIZE(verde_pg_init));
1430 break; 1430 break;
1431 case CHIP_OLAND: 1431 case CHIP_OLAND:
1432 amdgpu_program_register_sequence(adev, 1432 amdgpu_program_register_sequence(adev,
1433 oland_golden_registers, 1433 oland_golden_registers,
1434 (const u32)ARRAY_SIZE(oland_golden_registers)); 1434 ARRAY_SIZE(oland_golden_registers));
1435 amdgpu_program_register_sequence(adev, 1435 amdgpu_program_register_sequence(adev,
1436 oland_golden_rlc_registers, 1436 oland_golden_rlc_registers,
1437 (const u32)ARRAY_SIZE(oland_golden_rlc_registers)); 1437 ARRAY_SIZE(oland_golden_rlc_registers));
1438 amdgpu_program_register_sequence(adev, 1438 amdgpu_program_register_sequence(adev,
1439 oland_mgcg_cgcg_init, 1439 oland_mgcg_cgcg_init,
1440 (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init)); 1440 ARRAY_SIZE(oland_mgcg_cgcg_init));
1441 break; 1441 break;
1442 case CHIP_HAINAN: 1442 case CHIP_HAINAN:
1443 amdgpu_program_register_sequence(adev, 1443 amdgpu_program_register_sequence(adev,
1444 hainan_golden_registers, 1444 hainan_golden_registers,
1445 (const u32)ARRAY_SIZE(hainan_golden_registers)); 1445 ARRAY_SIZE(hainan_golden_registers));
1446 amdgpu_program_register_sequence(adev, 1446 amdgpu_program_register_sequence(adev,
1447 hainan_golden_registers2, 1447 hainan_golden_registers2,
1448 (const u32)ARRAY_SIZE(hainan_golden_registers2)); 1448 ARRAY_SIZE(hainan_golden_registers2));
1449 amdgpu_program_register_sequence(adev, 1449 amdgpu_program_register_sequence(adev,
1450 hainan_mgcg_cgcg_init, 1450 hainan_mgcg_cgcg_init,
1451 (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init)); 1451 ARRAY_SIZE(hainan_mgcg_cgcg_init));
1452 break; 1452 break;
1453 1453
1454 1454
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 4e67fe1e7955..fa27e0354f35 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -265,12 +265,12 @@ static void soc15_init_golden_registers(struct amdgpu_device *adev)
265 case CHIP_VEGA10: 265 case CHIP_VEGA10:
266 amdgpu_program_register_sequence(adev, 266 amdgpu_program_register_sequence(adev,
267 vega10_golden_init, 267 vega10_golden_init,
268 (const u32)ARRAY_SIZE(vega10_golden_init)); 268 ARRAY_SIZE(vega10_golden_init));
269 break; 269 break;
270 case CHIP_RAVEN: 270 case CHIP_RAVEN:
271 amdgpu_program_register_sequence(adev, 271 amdgpu_program_register_sequence(adev,
272 raven_golden_init, 272 raven_golden_init,
273 (const u32)ARRAY_SIZE(raven_golden_init)); 273 ARRAY_SIZE(raven_golden_init));
274 break; 274 break;
275 default: 275 default:
276 break; 276 break;
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 3a4c2fa7e36d..bb8ca9489546 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -284,27 +284,27 @@ static void vi_init_golden_registers(struct amdgpu_device *adev)
284 case CHIP_TOPAZ: 284 case CHIP_TOPAZ:
285 amdgpu_program_register_sequence(adev, 285 amdgpu_program_register_sequence(adev,
286 iceland_mgcg_cgcg_init, 286 iceland_mgcg_cgcg_init,
287 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); 287 ARRAY_SIZE(iceland_mgcg_cgcg_init));
288 break; 288 break;
289 case CHIP_FIJI: 289 case CHIP_FIJI:
290 amdgpu_program_register_sequence(adev, 290 amdgpu_program_register_sequence(adev,
291 fiji_mgcg_cgcg_init, 291 fiji_mgcg_cgcg_init,
292 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); 292 ARRAY_SIZE(fiji_mgcg_cgcg_init));
293 break; 293 break;
294 case CHIP_TONGA: 294 case CHIP_TONGA:
295 amdgpu_program_register_sequence(adev, 295 amdgpu_program_register_sequence(adev,
296 tonga_mgcg_cgcg_init, 296 tonga_mgcg_cgcg_init,
297 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); 297 ARRAY_SIZE(tonga_mgcg_cgcg_init));
298 break; 298 break;
299 case CHIP_CARRIZO: 299 case CHIP_CARRIZO:
300 amdgpu_program_register_sequence(adev, 300 amdgpu_program_register_sequence(adev,
301 cz_mgcg_cgcg_init, 301 cz_mgcg_cgcg_init,
302 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 302 ARRAY_SIZE(cz_mgcg_cgcg_init));
303 break; 303 break;
304 case CHIP_STONEY: 304 case CHIP_STONEY:
305 amdgpu_program_register_sequence(adev, 305 amdgpu_program_register_sequence(adev,
306 stoney_mgcg_cgcg_init, 306 stoney_mgcg_cgcg_init,
307 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); 307 ARRAY_SIZE(stoney_mgcg_cgcg_init));
308 break; 308 break;
309 case CHIP_POLARIS11: 309 case CHIP_POLARIS11:
310 case CHIP_POLARIS10: 310 case CHIP_POLARIS10:
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-31 12:39:05 -0400