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path: root/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 19a619f759f6..5ba24792f801 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -232,18 +232,18 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
232 case CHIP_VEGA10: 232 case CHIP_VEGA10:
233 amdgpu_program_register_sequence(adev, 233 amdgpu_program_register_sequence(adev,
234 golden_settings_gc_9_0, 234 golden_settings_gc_9_0,
235 (const u32)ARRAY_SIZE(golden_settings_gc_9_0)); 235 ARRAY_SIZE(golden_settings_gc_9_0));
236 amdgpu_program_register_sequence(adev, 236 amdgpu_program_register_sequence(adev,
237 golden_settings_gc_9_0_vg10, 237 golden_settings_gc_9_0_vg10,
238 (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10)); 238 ARRAY_SIZE(golden_settings_gc_9_0_vg10));
239 break; 239 break;
240 case CHIP_RAVEN: 240 case CHIP_RAVEN:
241 amdgpu_program_register_sequence(adev, 241 amdgpu_program_register_sequence(adev,
242 golden_settings_gc_9_1, 242 golden_settings_gc_9_1,
243 (const u32)ARRAY_SIZE(golden_settings_gc_9_1)); 243 ARRAY_SIZE(golden_settings_gc_9_1));
244 amdgpu_program_register_sequence(adev, 244 amdgpu_program_register_sequence(adev,
245 golden_settings_gc_9_1_rv1, 245 golden_settings_gc_9_1_rv1,
246 (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1)); 246 ARRAY_SIZE(golden_settings_gc_9_1_rv1));
247 break; 247 break;
248 default: 248 default:
249 break; 249 break;