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path: root/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 52e6bf2e9e59..c8c93f9dac21 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -194,45 +194,45 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
194 case CHIP_FIJI: 194 case CHIP_FIJI:
195 amdgpu_program_register_sequence(adev, 195 amdgpu_program_register_sequence(adev,
196 fiji_mgcg_cgcg_init, 196 fiji_mgcg_cgcg_init,
197 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); 197 ARRAY_SIZE(fiji_mgcg_cgcg_init));
198 amdgpu_program_register_sequence(adev, 198 amdgpu_program_register_sequence(adev,
199 golden_settings_fiji_a10, 199 golden_settings_fiji_a10,
200 (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); 200 ARRAY_SIZE(golden_settings_fiji_a10));
201 break; 201 break;
202 case CHIP_TONGA: 202 case CHIP_TONGA:
203 amdgpu_program_register_sequence(adev, 203 amdgpu_program_register_sequence(adev,
204 tonga_mgcg_cgcg_init, 204 tonga_mgcg_cgcg_init,
205 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); 205 ARRAY_SIZE(tonga_mgcg_cgcg_init));
206 amdgpu_program_register_sequence(adev, 206 amdgpu_program_register_sequence(adev,
207 golden_settings_tonga_a11, 207 golden_settings_tonga_a11,
208 (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); 208 ARRAY_SIZE(golden_settings_tonga_a11));
209 break; 209 break;
210 case CHIP_POLARIS11: 210 case CHIP_POLARIS11:
211 case CHIP_POLARIS12: 211 case CHIP_POLARIS12:
212 amdgpu_program_register_sequence(adev, 212 amdgpu_program_register_sequence(adev,
213 golden_settings_polaris11_a11, 213 golden_settings_polaris11_a11,
214 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); 214 ARRAY_SIZE(golden_settings_polaris11_a11));
215 break; 215 break;
216 case CHIP_POLARIS10: 216 case CHIP_POLARIS10:
217 amdgpu_program_register_sequence(adev, 217 amdgpu_program_register_sequence(adev,
218 golden_settings_polaris10_a11, 218 golden_settings_polaris10_a11,
219 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); 219 ARRAY_SIZE(golden_settings_polaris10_a11));
220 break; 220 break;
221 case CHIP_CARRIZO: 221 case CHIP_CARRIZO:
222 amdgpu_program_register_sequence(adev, 222 amdgpu_program_register_sequence(adev,
223 cz_mgcg_cgcg_init, 223 cz_mgcg_cgcg_init,
224 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 224 ARRAY_SIZE(cz_mgcg_cgcg_init));
225 amdgpu_program_register_sequence(adev, 225 amdgpu_program_register_sequence(adev,
226 cz_golden_settings_a11, 226 cz_golden_settings_a11,
227 (const u32)ARRAY_SIZE(cz_golden_settings_a11)); 227 ARRAY_SIZE(cz_golden_settings_a11));
228 break; 228 break;
229 case CHIP_STONEY: 229 case CHIP_STONEY:
230 amdgpu_program_register_sequence(adev, 230 amdgpu_program_register_sequence(adev,
231 stoney_mgcg_cgcg_init, 231 stoney_mgcg_cgcg_init,
232 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); 232 ARRAY_SIZE(stoney_mgcg_cgcg_init));
233 amdgpu_program_register_sequence(adev, 233 amdgpu_program_register_sequence(adev,
234 stoney_golden_settings_a11, 234 stoney_golden_settings_a11,
235 (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); 235 ARRAY_SIZE(stoney_golden_settings_a11));
236 break; 236 break;
237 default: 237 default:
238 break; 238 break;