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* drm/i915: Leave DPLL ref clocks onVille Syrjälä2014-08-08
| | | | | | | | | We enable the DPLL refclock already when bringing up the cmnlane power well, so also leave it on when otherwise disabling the DPLL. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Disable cdclk changes for chv until Punit is readyVille Syrjälä2014-08-08
| | | | | | | | | Punit seems a bit WIP still. Disable cdclk changes until we have hardware where it works. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Add cdclk change support for chvVille Syrjälä2014-08-08
| | | | | | | | | | | Looks like the Punit is supposed to support the 400MHz cdclk directly on chv, so we don't need the vlv tricks. FIXME: Punit doesn't seem ready for this yet on current hw Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* d rm/i915: freeze display before the interrupts and GTPaulo Zanoni2014-08-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we started using intel_runtime_pm_disable_interrupts() at normal (non-runtime) suspend/resume, we had to remove a WARN from ironlake_disable_display_irq to avoid a case where we were doing the correct thing and the WARN was not really needed. The problem is that the WARN was useful in other cases, and its removal can hide some bugs that we would catch automatically. To be able to add back the WARN, we have to call intel_crtc_control() before interrupts are disabled, which is what this patch currently does. Also notice that Ville's patch from the Watermarks series "drm/i915: Leave interrupts enabled while disabling crtcs during suspend" also did a change that's equivalent to the one we're doing on this patch, with the exception that its original patch, when applied to the current tree, procduces a WARN. Related commits: commit daa390e5ee45cc051d6bf37b296901f2f92b002d Author: Jesse Barnes <jbarnes@virtuousgeek.org> drm/i915: don't warn if IRQs are disabled when shutting down display IRQs commit e11aa362308f5de467ce355a2a2471321b15a35c Author: Jesse Barnes <jbarnes@virtuousgeek.org> drm/i915: use runtime irq suspend/resume in freeze/thaw Note that the function part of this patch has already been done in commit 0e32b39ceed665bfa4a77a4bc307b6652b991632 Author: Dave Airlie <airlied@redhat.com> Date: Fri May 2 14:02:48 2014 +1000 drm/i915: add DP 1.2 MST support (v0.7) with the fixup commit 09b64267c1f72f2670fcde9f11e5453ce365ca23 Author: Dave Airlie <airlied@redhat.com> Date: Wed Jul 23 14:25:24 2014 +1000 drm/i915: don't suspend gt until after we disable irqs and display (v2) so all that's left from Paulo's patch is reinstating the WARNING. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> [danvet: Explain conflict resolution with Dave's DP MST patches with a note in the commit message.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Make ddi_clock_gate() HSW/BDW specificDaniel Vetter2014-08-08
| | | | | | | | Turns out we were again way too naive and optimistic, of course things will change. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Split the CDCLK retrieval per-platformDamien Lespiau2014-08-08
| | | | | | | | | This is only going to get worse, so split it now to avoid adding more cases to the if/else ladder. Suggested-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Make intel_ddi_calculate_wrpll() HSW/BDW specificDamien Lespiau2014-08-08
| | | | | Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Split the BDW/HSW specific shared pll selectionDamien Lespiau2014-08-08
| | | | | | | We'll need a different algorithm to select the shared DPLL. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Fix stale comment for intel_ddi_pll_select()Damien Lespiau2014-08-08
| | | | | | | | Since the run-time PM on DPMS series, this function has an outdated comment. Refresh it a bit. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Restrict hsw_dp_set_ddi_pll_sel() to HSW/BDWDamien Lespiau2014-08-08
| | | | | | | Future platform will use config->ddi_pll_sel in a different way. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Extract the HSW/BDW shared dpll init codeDamien Lespiau2014-08-08
| | | | | | | So we can easily provide an alternate implementation in the future. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Extract the HSW DDI selection code into its own functionDamien Lespiau2014-08-08
| | | | | | | Future platform will slightly change that. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Add a space to the shared DPLL debug messageDamien Lespiau2014-08-08
| | | | | Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Specify when the PLL hw state fields are validDamien Lespiau2014-08-08
| | | | | | | | | | | | Not all those fields are valid on a given platform. Make it explicit. Unions could also be used, but were cluttering some code paths with if/else ladders. v2: Don't use anonymous unions (Daniel) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Add DP training pattern 3 for CHVVille Syrjälä2014-08-08
| | | | | | | | CHV supports DP training pattern 3. Add the required stuff. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Split a few long debug printsVille Syrjälä2014-08-08
| | | | | | | | | | Split some WM debug prints to multiple lines. This shouldn't hurt grappability since the important part is at the start and the rest is just repeated stuff for each pipe. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Fix read back of plane stride registerRafael Barbalho2014-08-08
| | | | | | | | | | According to the specifications bit 6 is actually valid in the stride register. Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Add chv port D TX wellsVille Syrjälä2014-08-08
| | | | | | | | | | Add the TX wells for port D. The Punit subsystem numbers are a total guess at this time. Also I'm not sure these even exist. Certainly the Punit in current hardware doesn't deal with these. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Add chv port B and C TX wellsVille Syrjälä2014-08-08
| | | | | | | | | | | Add the TX wells for ports B and C just like on VLV. Again Punit doesn't seem ready (or the wells don't even exist anymore) so leave it iffed out. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Add per-pipe power wells for chvVille Syrjälä2014-08-08
| | | | | | | | | | | CHV has a power well for each pipe. Add the code to deal with them. The Punit in current hardware doesn't seem ready for this yet, so leave it iffed out. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Add disp2d power well for chvVille Syrjälä2014-08-08
| | | | | | | | | | | Not sure if it's still there since chv has per-pipe power wells. At least with current Punit this doesn't work. Also the display irq handling would need to be adjusted for pipe C. So leave the code iffed out for now. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Kill intel_reset_dpio()Ville Syrjälä2014-08-08
| | | | | | | | | Both VLV and CHV handle the cmnreset stuff in the power well code now, so intel_reset_dpio() is no longer needed. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Add chv cmnlane power wellsVille Syrjälä2014-08-08
| | | | | | | | | | | | | | CHV has two display PHYs so there are also two cmnlane power wells. Add the approriate code to power the wells up/down. Like on VLV we do the cmnreset assert/deassert and the DPLL refclock enabling at approriate times. This code actually works on my bsw. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Add chv_power_wells[]Ville Syrjälä2014-08-08
| | | | | | | | | Add chv_power_wells[] so we can start to build up the power well support for chv. Just the "always on" well there initialy. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Rafael Barbalho <rafael.barbalho@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Kill intel_crtc->vbl_waitVille Syrjälä2014-08-08
| | | | | | | | | | | Share the waitqueue that drm_irq uses when performing the vblank evade trick for atomic pipe updates. v2: Keep intel_pipe_handle_vblank() (Chris) Suggested-by: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm: Add drm_crtc_vblank_waitqueue()Ville Syrjälä2014-08-08
| | | | | | | | | | | | | | | Add a small static inline helper to grab the vblank wait queue based on the drm_crtc. This is useful for drivers to do internal vblank waits using wait_event() & co. v2: Pimp commit message (Daniel) Add kernel doc (Daniel) Suggested-by: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: State readout and cross-checking for dp_m2_n2Vandana Kannan2014-08-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding relevant read out comparison code, in check_crtc_state, for the new member of crtc_config, dp_m2_n2, which was introduced to store link_m_n values for a DP downclock mode (if available). Suggested by Daniel. v2: Changed patch title. Daniel's review comments incorporated. Added relevant state readout code for M2_N2. dp_m2_n2 comparison to be done only when high RR is not in use (This is because alternate m_n register programming will be done only when low RR is being used). v3: Modified call to get_m2_n2 which had dp_m_n as param by mistake. Compare dp_m_n and dp_m2_n2 for gen 7 and below. compare the structures based on DRRS state for gen 8 and above. Save and restore M2 N2 registers for gen 7 and below v4: For Gen>=8, check M_N registers against dp_m_n and dp_m2_n2 as there is only one set of M_N registers v5: Removed the chunk which saves and restores M2_N2 registers. Modified get_m_n() to get M2_N2 registers as well. Modified the macro which compares hw.dp_m_n against sw.dp_m2_n2/sw.dp_m_n for gen > 8. v6: Added check to compare dp_m2_n2 only when DRRS is enabled v7: Modified drrs check to use has_drrs v8: Add has_drrs check before reading M2_N2 registers Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Set M2_N2 registers during mode setVandana Kannan2014-08-08
| | | | | | | | | | | | | | | | | | | | | | For Gen < 8, set M2_N2 registers on every mode set. This is required to make sure M2_N2 registers are set during boot, resume from sleep for cross- checking the state. The register is set only if DRRS is supported. v2: Patch rebased v3: Daniel's review comments - Removed HAS_DRRS(dev) and added bool has_drrs to pipe_config to track drrs support v4: Jesse's review comments - Made changes to set m2_n2 in intel_dp_set_m_n() Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* Revert "drm/i915: Enable semaphores on BDW"Rodrigo Vivi2014-08-08
| | | | | | | | | | | | | | | | | | This reverts commit 521e62e49a42661a4ee0102644517dbe2f100a23. Although POST_SYNC brought a bit of stability to Semaphores on BDW it didn't solved all issues and some hungs can still occour when semaphores are enabled on BDW. Also some sloweness can be found on some igt tests, althoguth it apparently doesn't affect real workloads. Besides that, no real performance gain was found on our tests with different and even multiple workloads. Let's disable it again for now. At least until we are sure it is safe to re-enable it. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: read HEAD register back in init_ring_common() to enforce orderingJiri Kosina2014-08-08
| | | | | | | | | | | | | | | | | | | | | | Withtout this, ring initialization fails reliabily during resume with [drm:init_ring_common] *ERROR* render ring initialization failed ctl 0001f001 head ffffff8804 tail 00000000 start 000e4000 This is not a complete fix, but it is verified to make the ring initialization failures during resume much less likely. We were not able to root-cause this bug (likely HW-specific to Gen4 chips) yet. This is therefore used as a ducttape before problem is fully understood and proper fix created, so that people don't suffer from completely unusable systems in the meantime. The discussion and debugging is happening at https://bugs.freedesktop.org/show_bug.cgi?id=76554 Signed-off-by: Jiri Kosina <jkosina@suse.cz> Cc: stable@vger.kernel.org Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Fix crash when failing to parse MIPI VBTRafael Barbalho2014-08-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This particular nasty presented itself while trying to register the intelfb device (intel_fbdev.c). During the process of registering the device the driver will disable the crtc via i9xx_crtc_disable. These will also disable the panel using the generic mipi panel functions in dsi_mod_vbt_generic.c. The stale MIPI generic data sequence pointers would cause a crash within those functions. However, all of this is happening while console_lock is held from do_register_framebuffer inside fbcon.c. Which means that you got kernel log and just the device appearing to reboot/hang for no apparent reason. The fault started from the FB_EVENT_FB_REGISTERED event using the fb_notifier_call_chain call in fbcon.c. This regression has been introduced in commit d3b542fcfc72d7724585e3fd2c5e75351bc3df47 Author: Shobhit Kumar <shobhit.kumar@intel.com> Date: Mon Apr 14 11:00:34 2014 +0530 drm/i915: Add parsing support for new MIPI blocks in VBT Cc: Shobhit Kumar <shobhit.kumar@intel.com> Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com> Reviewed-by: Shobhit Kumar <shobhit.kumar@intel.com> [danvet: Add regression citation.] Cc: stable@vger.kernel.org Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Bring GPU Freq to min while suspending.Deepak S2014-08-07
| | | | | | | | | We might be leaving the PGU Frequency (and thus vnn) high during the suspend. Flusing the delayed work queue should take care of this. Signed-off-by: Deepak S <deepak.s@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Fix DEIER and GTIER collecting for BDW.Rodrigo Vivi2014-08-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | BDW has many other Display Engine interrupts and GT interrupts registers. Collecting it properly on gpu_error_state. On debugfs all was properly listed already but besides we were also listing old DEIER and GTIER that doesn't exist on BDW anymore. This was causing unclaimed register messages v2: Fix small issues of first version and don't read DEIER regs when pipe's power well is disabled v3: bikeshed accepted: use enum pipe pipe instead of int i for pipe interection v4: Ben notice previous version was checking for display_power_enabled without using propper locks. Using _unlocked version isn't reliable and we cannot get this registers when power well is off. So let's avoid getting all DE_IER per pipe for now. If someone think this is an useful information it can be added later. v5: Ben: put back debugfs stuff that might be coverred by pm_get and use gen >= 8 trying to predict future. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81701 Cc: Ben Widawsky <ben@bwidawsk.net> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: (v3) Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Don't accumulate hangcheck score on forward progressMika Kuoppala2014-08-07
| | | | | | | | | | | | | | | | | If the actual head has progressed forward inside a batch (request), don't accumulate hangcheck score. As the hangcheck score in increased only by acthd jumping backwards, the result is that we only declare an active batch as stuck if it is trapped inside a loop. Or that the looping will dominate the batch progression so that it overcomes the bonus that forward progress gives. v2: Improved commit message (Chris Wilson) Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> [danvet: s/active_loop/active (loop)/ as requested by Chris.] Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Add the WaCsStallBeforeStateCacheInvalidate:bdw workaround.Kenneth Graunke2014-08-07
| | | | | | | | | | | | | | On Broadwell, any PIPE_CONTROL with the "State Cache Invalidate" bit set must be preceded by a PIPE_CONTROL with the "CS Stall" bit set. Documented on the BSpec 3D workarounds page. Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> [vsyrjala: add chv w/a note too] Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Refactor Broadwell PIPE_CONTROL emission into a helper.Kenneth Graunke2014-08-07
| | | | | | | | | We'll want to reuse this for a workaround. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> [danvet: Rmove now unused int.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Fix threshold for choosing 32 vs. 64 precisions for VLV DDL valuesVille Syrjälä2014-08-07
| | | | | | | | | | | | | | The DDL registers can hold 7bit numbers. Make the most of those seven bits by adjusting the threshold where we switch between the 64 vs. 32 precision multipliers. Also we compute 'entries' to make the decision about precision, and then we recompute the same value to calculate the actual drain latency. Just use the already calculate 'entries' there. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Fix drain latency precision multipler for VLVZhenyu Wang2014-08-07
| | | | | | Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Collect gtier properly on HSW.Rodrigo Vivi2014-08-07
| | | | | | | | | | | | | | | | | | GTIER and DEIER doesn't have same interface on HSW so this "or" operation makes the information provided useless. v2: since we have gtier variable already let's split for everybody and avoid the strange | op. Also avoid overriding the value that was set for vlv. In this case I believe that we should reorganize the whole function, but I'll respect the comment that ask to not touch the order and let this organization work to be done later. v3: moving VLV check to the right place. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Tune down MCH_SSKPD values warningDaniel Vetter2014-08-07
| | | | | | | | | | | | | Users often can't do anything about this since their vendors stopped providing BIOS updates. Also we seem to be able to hack around it with increased latency values, and thus far the only reports have been for screens with really high resolutions. So tune it down to a level where only developers can see it. Also drop some of the end-user fluff. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Tune done rc6 enabling outputDaniel Vetter2014-08-07
| | | | | | | | | | Power users spot this and then get adventurous and try to adjust module driver options. Nothing good ever came out of that, so hide it better. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Don't require dev->struct_mutex in psr_match_conditionsDaniel Vetter2014-08-07
| | | | | | | | | | | | | Since I've reworked psr support to no longer require x-tiling we don't check any state protected by the Giant GEM Lock. So drop that check. Also boo for lockdep_assert_held for not yelling when lockdep is disabled. Cc: Paulo Zanoni <przanoni@gmail.com> Reported-by: Paulo Zanoni <przanoni@gmail.com> Acked-by: Paulo Zanoni <przanoni@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Fix error state collectingRodrigo Vivi2014-08-07
| | | | | | | | Fix signal_offset when recording semaphore state on BDW. Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: fix VDD state tracking after system resumeImre Deak2014-08-07
| | | | | | | | | | | | | | | | | Just like during booting the BIOS can leave the VDD bit enabled after system resume. So apply the same state sanitization there too. This fixes a problem where after resume the port power domain refcount gets unbalanced. v2: - unchanged v3: - call edp sanitizing from the encoder reset handler (Daniel) Reported-and-tested-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Add correct hw/sw config check for DSI encoderShobhit Kumar2014-08-07
| | | | | | | | | | | | | | | | | | | | | | | | | | Check in vlv_crtc_clock_get if DPLL is enabled before calling dpio read. It will not be enabled for DSI and avoid dpio read WARN dumps. Absence of ->get_config was causing other WARN dumps as well. Update dpll_hw_state as well correctly v2: Address review comments by Daniel - Check if DPLL is enabled rather than checking pipe output type - set adjusted_mode->flags to 0 in compute_config rather than using pipe_config->quirks - Add helper function in intel_dsi_pll.c and use that in intel_dsi.c - updated dpll_hw_state correctly - Updated commit message and title v3: Address review comments by Imre - Proper masking of P1, M1 fields while computing divisors - assert in case of bpp mismatch - guard for divide by 0 while computing pclk - Use ARRAY_SIZE instead of direct calculation Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: factor out intel_edp_panel_vdd_sanitizeImre Deak2014-08-07
| | | | | | | | | | | | | | This will be needed by an upcoming patch too that needs to sanitize the VDD state during resume. The additional async disabling is only needed for the resume path, here it doesn't make a difference since we enable VDD right after the sanitize call. v2: - don't set intel_dp ptr for non-eDP encoders (Ville) Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: wait for all DSI FIFOs to be emptyShobhit Kumar2014-08-07
| | | | | | | | | Ensure that the DSI packets for a particular sequence are completely sent before going ahead in the enabling or disabling of the panel Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: work around warning in i915_gem_gttPavel Machek2014-08-07
| | | | | | | | | | | | Gcc warns that addr might be used uninitialized. It may not, but I see why gcc gets confused. Additionally, hiding code with side-effects inside WARN_ON() argument seems uncool, so I moved it outside. Signed-off-by: Pavel Machek <pavel@ucw.cz> [danvet: Add obligatory /* shuts up gcc */ comment.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Update DRIVER_DATE to 20140725Daniel Vetter2014-08-05
| | | | Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/ttm: Pass GFP flags in order to avoid deadlock.Tetsuo Handa2014-08-04
| | | | | | | | | | | | | | Commit 7dc19d5a "drivers: convert shrinkers to new count/scan API" added deadlock warnings that ttm_page_pool_free() and ttm_dma_page_pool_free() are currently doing GFP_KERNEL allocation. But these functions did not get updated to receive gfp_t argument. This patch explicitly passes sc->gfp_mask or GFP_KERNEL to these functions, and removes the deadlock warning. Signed-off-by: Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp> Cc: stable <stable@kernel.org> [2.6.35+] Signed-off-by: Dave Airlie <airlied@redhat.com>
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