diff options
author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2014-06-27 19:04:13 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-08-08 11:43:31 -0400 |
commit | 2ce147f36dc5a1f3b49abd8ce3164ad0f04ec863 (patch) | |
tree | 018ed5bf2709d0c125785cd0c9b98d7248d5a2fd | |
parent | 8258356537871cf579868002552a0ed1762b0487 (diff) |
drm/i915: Add chv port D TX wells
Add the TX wells for port D. The Punit subsystem numbers are a total
guess at this time. Also I'm not sure these even exist. Certainly the
Punit in current hardware doesn't deal with these.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 23 |
2 files changed, 27 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9d54aee6f8c8..e01a1a0b9613 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -527,6 +527,10 @@ enum punit_power_well { | |||
527 | PUNIT_POWER_WELL_DPIO_RX0 = 10, | 527 | PUNIT_POWER_WELL_DPIO_RX0 = 10, |
528 | PUNIT_POWER_WELL_DPIO_RX1 = 11, | 528 | PUNIT_POWER_WELL_DPIO_RX1 = 11, |
529 | PUNIT_POWER_WELL_DPIO_CMN_D = 12, | 529 | PUNIT_POWER_WELL_DPIO_CMN_D = 12, |
530 | /* FIXME: guesswork below */ | ||
531 | PUNIT_POWER_WELL_DPIO_TX_D_LANES_01 = 13, | ||
532 | PUNIT_POWER_WELL_DPIO_TX_D_LANES_23 = 14, | ||
533 | PUNIT_POWER_WELL_DPIO_RX2 = 15, | ||
530 | 534 | ||
531 | PUNIT_POWER_WELL_NUM, | 535 | PUNIT_POWER_WELL_NUM, |
532 | }; | 536 | }; |
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 59157635d418..f4a1837c231c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c | |||
@@ -6616,6 +6616,15 @@ EXPORT_SYMBOL_GPL(i915_get_cdclk_freq); | |||
6616 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | 6616 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ |
6617 | BIT(POWER_DOMAIN_INIT)) | 6617 | BIT(POWER_DOMAIN_INIT)) |
6618 | 6618 | ||
6619 | #define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \ | ||
6620 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ | ||
6621 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | ||
6622 | BIT(POWER_DOMAIN_INIT)) | ||
6623 | |||
6624 | #define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \ | ||
6625 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | ||
6626 | BIT(POWER_DOMAIN_INIT)) | ||
6627 | |||
6619 | static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { | 6628 | static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { |
6620 | .sync_hw = i9xx_always_on_power_well_noop, | 6629 | .sync_hw = i9xx_always_on_power_well_noop, |
6621 | .enable = i9xx_always_on_power_well_noop, | 6630 | .enable = i9xx_always_on_power_well_noop, |
@@ -6833,6 +6842,20 @@ static struct i915_power_well chv_power_wells[] = { | |||
6833 | .ops = &vlv_dpio_power_well_ops, | 6842 | .ops = &vlv_dpio_power_well_ops, |
6834 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, | 6843 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, |
6835 | }, | 6844 | }, |
6845 | { | ||
6846 | .name = "dpio-tx-d-01", | ||
6847 | .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | | ||
6848 | CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, | ||
6849 | .ops = &vlv_dpio_power_well_ops, | ||
6850 | .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01, | ||
6851 | }, | ||
6852 | { | ||
6853 | .name = "dpio-tx-d-23", | ||
6854 | .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | | ||
6855 | CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, | ||
6856 | .ops = &vlv_dpio_power_well_ops, | ||
6857 | .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23, | ||
6858 | }, | ||
6836 | #endif | 6859 | #endif |
6837 | }; | 6860 | }; |
6838 | 6861 | ||