drm/i915: Add correct hw/sw config check for DSI encoder

Check in vlv_crtc_clock_get if DPLL is enabled before calling dpio read.
It will not be enabled for DSI and avoid dpio read WARN dumps.

Absence of ->get_config was causing other WARN dumps as well. Update
dpll_hw_state as well correctly

v2: Address review comments by Daniel
    - Check if DPLL is enabled rather than checking pipe output type
    - set adjusted_mode->flags to 0 in compute_config rather than using
      pipe_config->quirks
    - Add helper function in intel_dsi_pll.c and use that in intel_dsi.c
    - updated dpll_hw_state correctly
    - Updated commit message and title

v3: Address review comments by Imre
    - Proper masking of P1, M1 fields while computing divisors
    - assert in case of bpp mismatch
    - guard for divide by 0 while computing pclk
    - Use ARRAY_SIZE instead of direct calculation

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

4 files changed, 106 insertions, 1 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 99eb7cad62a8..018fb7222f60 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6161,6 +6161,10 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc,
         u32 mdiv;
         int refclk = 100000;
 
+        /* In case of MIPI DPLL will not even be used */
+        if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
+                return;
+
         mutex_lock(&dev_priv->dpio_lock);
         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
         mutex_unlock(&dev_priv->dpio_lock);
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 09e1cafe3e87..670c29a7b5dd 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -92,6 +92,9 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
         if (fixed_mode)
                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
 
+        /* DSI uses short packets for sync events, so clear mode flags for DSI */
+        adjusted_mode->flags = 0;
+
         if (intel_dsi->dev.dev_ops->mode_fixup)
                 return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev,
                                                           mode, adjusted_mode);
@@ -179,6 +182,10 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
         tmp |= DPLL_REFA_CLK_ENABLE_VLV;
         I915_WRITE(DPLL(pipe), tmp);
 
+        /* update the hw state for DPLL */
+        intel_crtc->config.dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV |
+                                                DPLL_REFA_CLK_ENABLE_VLV;
+
         tmp = I915_READ(DSPCLK_GATE_D);
         tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
         I915_WRITE(DSPCLK_GATE_D, tmp);
@@ -359,9 +366,21 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 static void intel_dsi_get_config(struct intel_encoder *encoder,
                                  struct intel_crtc_config *pipe_config)
 {
+        u32 pclk;
         DRM_DEBUG_KMS("\n");
 
-        /* XXX: read flags, set to adjusted_mode */
+        /*
+         * DPLL_MD is not used in case of DSI, reading will get some default value
+         * set dpll_md = 0
+         */
+        pipe_config->dpll_hw_state.dpll_md = 0;
+
+        pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
+        if (!pclk)
+                return;
+
+        pipe_config->adjusted_mode.crtc_clock = pclk;
+        pipe_config->port_clock = pclk;
 }
 
 static enum drm_mode_status
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 31db33d3e5cc..fd51867fd0d3 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -132,6 +132,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
 
 extern void vlv_enable_dsi_pll(struct intel_encoder *encoder);
 extern void vlv_disable_dsi_pll(struct intel_encoder *encoder);
+extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
 
 extern struct intel_dsi_dev_ops vbt_generic_dsi_display_ops;
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index ba79ec19da3b..d8bb1ea2f0da 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -298,3 +298,84 @@ void vlv_disable_dsi_pll(struct intel_encoder *encoder)
 
         mutex_unlock(&dev_priv->dpio_lock);
 }
+
+static void assert_bpp_mismatch(int pixel_format, int pipe_bpp)
+{
+        int bpp;
+
+        switch (pixel_format) {
+        default:
+        case VID_MODE_FORMAT_RGB888:
+        case VID_MODE_FORMAT_RGB666_LOOSE:
+                bpp = 24;
+                break;
+        case VID_MODE_FORMAT_RGB666:
+                bpp = 18;
+                break;
+        case VID_MODE_FORMAT_RGB565:
+                bpp = 16;
+                break;
+        }
+
+        WARN(bpp != pipe_bpp,
+                "bpp match assertion failure (expected %d, current %d)\n",
+                bpp, pipe_bpp);
+}
+
+u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
+{
+        struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+        struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+        u32 dsi_clock, pclk;
+        u32 pll_ctl, pll_div;
+        u32 m = 0, p = 0;
+        int refclk = 25000;
+        int i;
+
+        DRM_DEBUG_KMS("\n");
+
+        mutex_lock(&dev_priv->dpio_lock);
+        pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
+        pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);
+        mutex_unlock(&dev_priv->dpio_lock);
+
+        /* mask out other bits and extract the P1 divisor */
+        pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;
+        pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2);
+
+        /* mask out the other bits and extract the M1 divisor */
+        pll_div &= DSI_PLL_M1_DIV_MASK;
+        pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT;
+
+        while (pll_ctl) {
+                pll_ctl = pll_ctl >> 1;
+                p++;
+        }
+        p--;
+
+        if (!p) {
+                DRM_ERROR("wrong P1 divisor\n");
+                return 0;
+        }
+
+        for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) {
+                if (lfsr_converts[i] == pll_div)
+                        break;
+        }
+
+        if (i == ARRAY_SIZE(lfsr_converts)) {
+                DRM_ERROR("wrong m_seed programmed\n");
+                return 0;
+        }
+
+        m = i + 62;
+
+        dsi_clock = (m * refclk) / p;
+
+        /* pixel_format and pipe_bpp should agree */
+        assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);
+
+        pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp);
+
+        return pclk;
+}