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* Merge tag 'renesas-dt2-for-v3.14' of ↵Olof Johansson2013-12-29
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt From Simon Horman: Second Round of Renesas ARM Based SoC DT Updates for v3.13 * r8a7791 (R-Car M2) based Koelsch board - Add GPIO keys * sh73a0 (SH-Mobile AG5) based kzm9g board - Add FSI support * tag 'renesas-dt2-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: koelsch: dts: Add gpio-keys device ARM: shmobile: kzm9g: add FSI support for DTS ARM: shmobile: sh73a0: add FSI support via DTSI Signed-off-by: Olof Johansson <olof@lixom.net>
| * ARM: shmobile: koelsch: dts: Add gpio-keys deviceLaurent Pinchart2013-12-12
| | | | | | | | | | | | | | | | The board has 7 buttons connected to GPIOs, add a corresponding gpio-keys device. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: kzm9g: add FSI support for DTSKuninori Morimoto2013-12-12
| | | | | | | | | | | | | | This patch support FSI-AK4648 with simple audio card Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: sh73a0: add FSI support via DTSIKuninori Morimoto2013-12-12
| | | | | | | | | | Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | Merge tag 'tegra-for-3.14-dt-2' of ↵Olof Johansson2013-12-27
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt From Stephen Warren: ARM: tegra: second set of device tree changes This branch contains changes to Tegra's device tree that came in after I sent the previous pull-request/tag tegra-for-3.14-dt. Changes are: * Set up aliases for RTCs, so that the correct RTC is chosen to initialize the system date/time. * Venice2 pinctrl and regulator configuration. * Built-in panel enablement for Harmony, Cardhu, Dalmore. * HDMI enablement for Dalmore. * USB2 port enablement for Beaver. * Keyboard and power key enablement for Venice2. * tag 'tegra-for-3.14-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: Enable power key on Venice2 ARM: tegra: Enable Venice2 keyboard ARM: tegra: enable USB2 on Tegra30 Beaver ARM: tegra: modify Tegra30 USB2 default phy_type to UTMI ARM: tegra: Enable HDMI support on Dalmore ARM: tegra: Enable DSI support on Dalmore ARM: tegra: Add Tegra114 gr3d support ARM: tegra: Add Tegra114 gr2d support ARM: tegra: Add Tegra114 DSI support ARM: tegra: Add host1x, DC and HDMI to Tegra114 device tree ARM: tegra: Add MIPI calibration DT entries for Tegra114 ARM: tegra: Enable LVDS on Cardhu ARM: tegra: Enable LVDS on Harmony ARM: tegra: set up /aliases for RTCs on Venice2 ARM: tegra: add ams AS3722 device to Venice2 DT ARM: tegra: fix missing pincontrol configuration for Venice2 ARM: tegra: set up /aliases entries for RTCs Signed-off-by: Olof Johansson <olof@lixom.net>
| * | ARM: tegra: Enable power key on Venice2Thierry Reding2013-12-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | Contrary to the rest of the keyboard, which is connected to the ChromeOS embedded controller, the power key is hooked up to a GPIO. Add a device tree node to handle it. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: Enable Venice2 keyboardThierry Reding2013-12-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The keyboard on Venice2 is attached to the ChromeOS embedded controller. Add the corresponding device tree nodes and use the MATRIX_KEY define to encode keycodes. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: enable USB2 on Tegra30 BeaverEric Brower2013-12-20
| | | | | | | | | | | | | | | | | | | | | Enable USB2 on Beaver, exposed via the mini-PCIe connector. Signed-off-by: Eric Brower <ebrower@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: modify Tegra30 USB2 default phy_type to UTMIEric Brower2013-12-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modify Tegra30 default USB2 phy_type to UTMI; this matches power-on-reset defaults and is expected to be the common case. The current implementation is likely an incorrect carry-over from Tegra20, where USB2 does default to ULPI. Signed-off-by: Eric Brower <ebrower@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: Enable HDMI support on DalmoreMikko Perttunen2013-12-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add HDMI node to the Dalmore device tree and hook up the VDD and PLL regulators as well as the I2C adapter used for DDC and the GPIO used for hotplug detection. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: Enable DSI support on DalmoreThierry Reding2013-12-19
| | | | | | | | | | | | | | | | | | | | | | | | Dalmore has a 10.1" WUXGA panel connected to one of the DSI outputs of the Tegra114. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: Add Tegra114 gr3d supportThierry Reding2013-12-19
| | | | | | | | | | | | | | | | | | | | | | | | Add the gr3d device tree node. The gr3d block on Tegra114 is backwards- compatible with the one on Tegra20. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: Add Tegra114 gr2d supportThierry Reding2013-12-19
| | | | | | | | | | | | | | | | | | | | | Add the device tree for the gr2d hardware found on Tegra114 SoCs. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: Add Tegra114 DSI supportThierry Reding2013-12-19
| | | | | | | | | | | | | | | | | | | | | Add device tree nodes for the DSI controllers found on Tegra114 SoCs. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: Add host1x, DC and HDMI to Tegra114 device treeMikko Perttunen2013-12-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add host1x, DC (display controller) and HDMI devices to Tegra114 device tree. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: Add MIPI calibration DT entries for Tegra114Thierry Reding2013-12-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a device node for the MIPI calibration block on Tegra114. There is no need to disable it by default because it only enables the clock while performing calibration and therefore shouldn't be consuming any power when unused. Signed-off-by: Thierry Reding <treding@nvidia.com> [swarren, add unit address to new DT node name] Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: Enable LVDS on CardhuThierry Reding2013-12-19
| | | | | | | | | | | | | | | | | | | | | Add backlight and panel nodes for the Cardhu 10.1" WXGA TFT LCD panel. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: Enable LVDS on HarmonyThierry Reding2013-12-19
| | | | | | | | | | | | | | | | | | | | | Add backlight and panel nodes for the Harmony TFT LCD panel. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: set up /aliases for RTCs on Venice2Stephen Warren2013-12-19
| | | | | | | | | | | | | | | | | | | | | This ensures that the PMIC RTC provides the system time, rather than the on-SoC RTC, which is not battery-backed. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: add ams AS3722 device to Venice2 DTLaxman Dewangan2013-12-19
| | | | | | | | | | | | | | | | | | | | | | | | Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: fix missing pincontrol configuration for Venice2Laxman Dewangan2013-12-19
| | | | | | | | | | | | | | | | | | | | | | | | Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: set up /aliases entries for RTCsStephen Warren2013-12-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This ensures that the PMIC RTC provides the system time, rather than the on-SoC RTC, which is not battery-backed. tegra124-venice2.dts isn't touched yet since we haven't added any off- SoC RTC device to its device tree. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | Merge tag 'tegra-for-3.14-dt' of ↵Olof Johansson2013-12-26
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt From Stephen Warren: ARM: tegra: device tree changes This branch contains all the changes to Tegra's device tree. The highlights are: * Many patches for Tegra124 SoC support, and the Venice2 board which uses that SoC. * Conversion to use more headers providing named constants for pinctrl and key codes, which improves readability. * A few cleanups. This branch is based on tag tegra-for-3.14-dmas-resets-rework in order to avoid conflicts with the DT changes required to use the common bindings for DMAs and resets. * tag 'tegra-for-3.14-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (24 commits) ARM: tegra: Add SPI controller nodes for Tegra124 ARM: tegra: Fix misconfiguration of pin PH2 on Venice2 ARM: tegra: fix pinctrl misconfiguration on Venice2 ARM: tegra: add default pinctrl nodes for Venice2 ARM: tegra: correct Colibri T20 regulator settings ARM: tegra: convert dts files of Tegra30 platforms to use pinctrl defines ARM: tegra: convert dts files of Tegra20 platforms to use pinctrl defines ARM: tegra: convert dts files of Tegra114 platforms to use pinctrl defines ARM: tegra: Add header file for pinctrl constants ARM: tegra: convert device tree files to use key defines ARM: tegra: Enable PWM on Venice2 ARM: tegra: Add Tegra124 PWM support ARM: tegra: add sound card to Venice2 DT ARM: tegra: add audio-related device to Tegra124 DT ARM: tegra: enable I2C controllers on Venice2 ARM: tegra: add I2C controllers to Tegra124 DT ARM: tegra: add MMC controllers to Tegra124 DT ARM: tegra: add Tegra124 pinmux node to DT ARM: tegra: add APB DMA controller to Tegra124 DT ARM: tegra: add reset properties to Tegra124 DTs ... Signed-off-by: Olof Johansson <olof@lixom.net>
| * | ARM: tegra: Add SPI controller nodes for Tegra124Thierry Reding2013-12-16
| | | | | | | | | | | | | | | | | | | | | | | | The SPI controllers on Tegra124 are compatible with those found on the Tegra114 SoC. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: Fix misconfiguration of pin PH2 on Venice2Thierry Reding2013-12-16
| | | | | | | | | | | | | | | | | | | | | | | | This pin needs to be configured in pull-down, non-tristate mode in order for the backlight to work correctly. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: fix pinctrl misconfiguration on Venice2Stephen Warren2013-12-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Other boards use PULL_NONE for their debug UART pins, and without this change, the board doesn't accept any serial input. Don't set the I2S port pins to tristate mode, or no audio signal will be sent out. Fixes: 605ae5804385 ("ARM: tegra: add default pinctrl nodes for Venice2") Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: add default pinctrl nodes for Venice2Laxman Dewangan2013-12-16
| | | | | | | | | | | | | | | | | | | | | | | | Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: correct Colibri T20 regulator settingsStefan Agner2013-12-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set the parent of the regulators LDO2 to LDO9 according to the schematic. Set the base voltage to 3.3V, there is only 3.3V on the module itself. Set the Core and CPU voltage to the specified voltages of 1.2V and 1.0V respectivly. LDO6 should deliver 2.85V. The attached peripherals were not in use so far. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: convert dts files of Tegra30 platforms to use pinctrl definesLaxman Dewangan2013-12-16
| | | | | | | | | | | | | | | | | | | | | | | | Use Tegra pinconrol dt-binding macro to set the values of different pinmux properties of Tegra30 platforms. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: convert dts files of Tegra20 platforms to use pinctrl definesLaxman Dewangan2013-12-16
| | | | | | | | | | | | | | | | | | | | | | | | Use Tegra pinconrol dt-binding macro to set the values of different pinmux properties of Tegra20 platforms. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: convert dts files of Tegra114 platforms to use pinctrl definesLaxman Dewangan2013-12-16
| | | | | | | | | | | | | | | | | | | | | | | | Use Tegra pinconrol dt-binding macro to set the values of different pinmux properties of Tegra114 platforms. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: Add header file for pinctrl constantsLaxman Dewangan2013-12-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | This new header file defines pincontrol constants for Tegra to use from Tegra's DTS file for pincontrol properties option. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: convert device tree files to use key definesLaxman Dewangan2013-12-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use key code macros for all key code refernced for keys. For tegra20-seaboard.dts and tegra20-harmony.dts: The key comment for key (16th row and 1st column) is KEY_KPSLASH but code is 0x004e which is the key code for KEY_KPPLUS. As there other key exist with KY_KPPLUS, I am assuming key code is wrong and comment is fine. With this assumption, I am keeping the key code as KEY_KPSLASH. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: Enable PWM on Venice2Thierry Reding2013-12-16
| | | | | | | | | | | | | | | | | | | | | | | | Subsequent patches will need to reference a PWM channel for backlight support, so enable the PWM device and assign a label to it. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: Add Tegra124 PWM supportThierry Reding2013-12-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | The PWM controller on Tegra124 is the same as the one on earlier SoC generations. Signed-off-by: Thierry Reding <treding@nvidia.com> [swarren, added reset properties] Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: add sound card to Venice2 DTStephen Warren2013-12-16
| | | | | | | | | | | | | | | | | | | | | | | | Venice2 uses the MAX98090 audio CODEC, and supports built-in speakers, and a combo headphones/microphone jack. Add a top-level sound card node to represent this. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: add audio-related device to Tegra124 DTStephen Warren2013-12-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra124 contains a similar set of audio devices to previous Tegra chips. Specifically, there is an AHUB device which contains DMA FIFOs and audio routing, and which hosts various audio-related components such as I2S controllers. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: enable I2C controllers on Venice2Stephen Warren2013-12-16
| | | | | | | | | | | | | | | | | | | | | | | | Enable all the I2C controllers that are wired up on Venice2. I don't know the correct I2C bus clock rates, so set them all to a conservative 100KHz for now. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: add I2C controllers to Tegra124 DTStephen Warren2013-12-16
| | | | | | | | | | | | | | | | | | | | | Tegra124 has 6 I2C controllers. The first 5 have identical configuration to Tegra114, but the sixth obviously has different interrupt/... IDs. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: add MMC controllers to Tegra124 DTStephen Warren2013-12-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra124 has 4 MMC controllers just like previous versions of the SoC. Note that there are some non-backwards-compatible HW differences, and hence a new DT compatible value must be used to describe the HW. Also enable the relevant controllers in the Venice2 board DT. power-gpios property suggested by Thierry Reding. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com>
| * | ARM: tegra: add Tegra124 pinmux node to DTStephen Warren2013-12-16
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked by: Laxman Dewangan <ldewangan@nvidia.com>
| * | ARM: tegra: add APB DMA controller to Tegra124 DTStephen Warren2013-12-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | Instantiate the APB DMA controller in the Tegra124 DT, and add all DMA-related properties to other DT nodes that rely on (reference) the DMA controller's node. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
| * | ARM: tegra: add reset properties to Tegra124 DTsStephen Warren2013-12-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | The DT bindings now require module resets to be specified. The earlier patches which added these nodes were originally written before that requirement. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
| * | ARM: tegra: add clock properties for devices of Tegra124Joseph Lo2013-12-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds clock properties for devices in the DT for basic support of Tegra124 SoC. Signed-off-by: Joseph Lo <josephl@nvidia.com> [swarren, added missing unit address to "clock" node] Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: fix node sort orderStephen Warren2013-12-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For Tegra DT files, I've been attempting to keep the nodes sorted in the order: 1) Nodes with reg, in order of reg. 2) Nodes without reg, alphabetically. This patch fixes a few escapees that I missed:-( The diffs look larger than they really are, because sometimes when one node was moved up or down, diff chose to represent this as many other nodes being moved the other way! Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: add missing unit addresses to DTStephen Warren2013-12-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DT node names should include a unit address iff the node has a reg property. For Tegra DTs at least, we were previously applying a different rule, namely that node names only needed to include a unit address if it was required to make the node name unique. Consequently, many unit addresses are missing. Add them. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: add port FF to GPIO IDsAshwini Ghuge2013-12-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NVIDIA Tegra124 supports has the new GPIO port as GPIO_FF. Add the macro for this port name. Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | Merge branch 'tegra/dma-reset-rework' into next/dtOlof Johansson2013-12-26
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bringing in the tegra dma/reset framework cleanup as a base for the DT changes. * tegra/dma-reset-rework: (320 commits) spi: tegra: checking for ERR_PTR instead of NULL ASoC: tegra: update module reset list for Tegra124 clk: tegra: remove bogus PCIE_XCLK clk: tegra: remove legacy reset APIs ARM: tegra: remove legacy DMA entries from DT ARM: tegra: remove legacy clock entries from DT USB: EHCI: tegra: use reset framework Input: tegra-kbc - use reset framework serial: tegra: convert to standard DMA DT bindings serial: tegra: use reset framework spi: tegra: convert to standard DMA DT bindings spi: tegra: use reset framework staging: nvec: use reset framework i2c: tegra: use reset framework ASoC: tegra: convert to standard DMA DT bindings ASoC: tegra: allocate AHUB FIFO during probe() not startup() ASoC: tegra: call pm_runtime APIs around register accesses ASoC: tegra: use reset framework dma: tegra: register as an OF DMA controller dma: tegra: use reset framework ... Signed-off-by: Olof Johansson <olof@lixom.net>
| * | spi: tegra: checking for ERR_PTR instead of NULLDan Carpenter2013-12-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dma_request_slave_channel() returns NULL on error and not ERR_PTRs. I've fixed this by using dma_request_slave_channel_reason() which does return ERR_PTRs. Fixes: a915d150f68d ('spi: tegra: convert to standard DMA DT bindings') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ASoC: tegra: update module reset list for Tegra124Stephen Warren2013-12-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra124 adds a number of extra modules into the configlink bus, which must be taken out of reset before the bus is used. Update the AHUB driver to know about these extra modules (the AHUB HW module hosts the configlink bus). Based-on-work-by: Arun Shamanna Lakshmi <aruns@nvidia.com> Based-on-work-by: Songhee Baek <sbaek@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Mark Brown <broonie@linaro.org> --- This patch depends on "ASoC: tegra: use reset framework" to compile, which is ack'd and slated to go through a (large) topic branch in the Tegra tree. So, we can either: a) Merge that Tegra topic branch into the ASoC tree, then apply this. Note that I haven't created the topic branch yet, since I'm still waiting for DMA dependencies to be applied. b) Apply this change to the Tegra tree too. This change isn't directly related to the changes in the Tegra tree; it just makes use of the new reset controller feature that's introduced there.
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