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authorLaxman Dewangan <ldewangan@nvidia.com>2013-12-05 05:44:09 -0500
committerStephen Warren <swarren@nvidia.com>2013-12-16 16:09:20 -0500
commita47c662aad72cbabdb0e8df6c25c47c68b400e40 (patch)
tree08f552fd4229686cf54db0a06eb1d911c7aec563
parentba4104e79470ae848a9f38029fe1371790dc0df9 (diff)
ARM: tegra: convert dts files of Tegra30 platforms to use pinctrl defines
Use Tegra pinconrol dt-binding macro to set the values of different pinmux properties of Tegra30 platforms. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat
-rw-r--r--arch/arm/boot/dts/tegra30-beaver.dts34
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dtsi40
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi1
3 files changed, 38 insertions, 37 deletions
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 3ad193c37436..7e8562a8507d 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -52,8 +52,8 @@
52 sdmmc1_clk_pz0 { 52 sdmmc1_clk_pz0 {
53 nvidia,pins = "sdmmc1_clk_pz0"; 53 nvidia,pins = "sdmmc1_clk_pz0";
54 nvidia,function = "sdmmc1"; 54 nvidia,function = "sdmmc1";
55 nvidia,pull = <0>; 55 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
56 nvidia,tristate = <0>; 56 nvidia,tristate = <TEGRA_PIN_DISABLE>;
57 }; 57 };
58 sdmmc1_cmd_pz1 { 58 sdmmc1_cmd_pz1 {
59 nvidia,pins = "sdmmc1_cmd_pz1", 59 nvidia,pins = "sdmmc1_cmd_pz1",
@@ -62,14 +62,14 @@
62 "sdmmc1_dat2_py5", 62 "sdmmc1_dat2_py5",
63 "sdmmc1_dat3_py4"; 63 "sdmmc1_dat3_py4";
64 nvidia,function = "sdmmc1"; 64 nvidia,function = "sdmmc1";
65 nvidia,pull = <2>; 65 nvidia,pull = <TEGRA_PIN_PULL_UP>;
66 nvidia,tristate = <0>; 66 nvidia,tristate = <TEGRA_PIN_DISABLE>;
67 }; 67 };
68 sdmmc3_clk_pa6 { 68 sdmmc3_clk_pa6 {
69 nvidia,pins = "sdmmc3_clk_pa6"; 69 nvidia,pins = "sdmmc3_clk_pa6";
70 nvidia,function = "sdmmc3"; 70 nvidia,function = "sdmmc3";
71 nvidia,pull = <0>; 71 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
72 nvidia,tristate = <0>; 72 nvidia,tristate = <TEGRA_PIN_DISABLE>;
73 }; 73 };
74 sdmmc3_cmd_pa7 { 74 sdmmc3_cmd_pa7 {
75 nvidia,pins = "sdmmc3_cmd_pa7", 75 nvidia,pins = "sdmmc3_cmd_pa7",
@@ -78,15 +78,15 @@
78 "sdmmc3_dat2_pb5", 78 "sdmmc3_dat2_pb5",
79 "sdmmc3_dat3_pb4"; 79 "sdmmc3_dat3_pb4";
80 nvidia,function = "sdmmc3"; 80 nvidia,function = "sdmmc3";
81 nvidia,pull = <2>; 81 nvidia,pull = <TEGRA_PIN_PULL_UP>;
82 nvidia,tristate = <0>; 82 nvidia,tristate = <TEGRA_PIN_DISABLE>;
83 }; 83 };
84 sdmmc4_clk_pcc4 { 84 sdmmc4_clk_pcc4 {
85 nvidia,pins = "sdmmc4_clk_pcc4", 85 nvidia,pins = "sdmmc4_clk_pcc4",
86 "sdmmc4_rst_n_pcc3"; 86 "sdmmc4_rst_n_pcc3";
87 nvidia,function = "sdmmc4"; 87 nvidia,function = "sdmmc4";
88 nvidia,pull = <0>; 88 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
89 nvidia,tristate = <0>; 89 nvidia,tristate = <TEGRA_PIN_DISABLE>;
90 }; 90 };
91 sdmmc4_dat0_paa0 { 91 sdmmc4_dat0_paa0 {
92 nvidia,pins = "sdmmc4_dat0_paa0", 92 nvidia,pins = "sdmmc4_dat0_paa0",
@@ -98,8 +98,8 @@
98 "sdmmc4_dat6_paa6", 98 "sdmmc4_dat6_paa6",
99 "sdmmc4_dat7_paa7"; 99 "sdmmc4_dat7_paa7";
100 nvidia,function = "sdmmc4"; 100 nvidia,function = "sdmmc4";
101 nvidia,pull = <2>; 101 nvidia,pull = <TEGRA_PIN_PULL_UP>;
102 nvidia,tristate = <0>; 102 nvidia,tristate = <TEGRA_PIN_DISABLE>;
103 }; 103 };
104 dap2_fs_pa2 { 104 dap2_fs_pa2 {
105 nvidia,pins = "dap2_fs_pa2", 105 nvidia,pins = "dap2_fs_pa2",
@@ -107,18 +107,18 @@
107 "dap2_din_pa4", 107 "dap2_din_pa4",
108 "dap2_dout_pa5"; 108 "dap2_dout_pa5";
109 nvidia,function = "i2s1"; 109 nvidia,function = "i2s1";
110 nvidia,pull = <0>; 110 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
111 nvidia,tristate = <0>; 111 nvidia,tristate = <TEGRA_PIN_DISABLE>;
112 }; 112 };
113 pex_l1_prsnt_n_pdd4 { 113 pex_l1_prsnt_n_pdd4 {
114 nvidia,pins = "pex_l1_prsnt_n_pdd4", 114 nvidia,pins = "pex_l1_prsnt_n_pdd4",
115 "pex_l1_clkreq_n_pdd6"; 115 "pex_l1_clkreq_n_pdd6";
116 nvidia,pull = <2>; 116 nvidia,pull = <TEGRA_PIN_PULL_UP>;
117 }; 117 };
118 sdio3 { 118 sdio3 {
119 nvidia,pins = "drive_sdio3"; 119 nvidia,pins = "drive_sdio3";
120 nvidia,high-speed-mode = <0>; 120 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
121 nvidia,schmitt = <0>; 121 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
122 nvidia,pull-down-strength = <46>; 122 nvidia,pull-down-strength = <46>;
123 nvidia,pull-up-strength = <42>; 123 nvidia,pull-up-strength = <42>;
124 nvidia,slew-rate-rising = <1>; 124 nvidia,slew-rate-rising = <1>;
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 748b4ba945ee..f3aab9eb6453 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -59,8 +59,8 @@
59 sdmmc1_clk_pz0 { 59 sdmmc1_clk_pz0 {
60 nvidia,pins = "sdmmc1_clk_pz0"; 60 nvidia,pins = "sdmmc1_clk_pz0";
61 nvidia,function = "sdmmc1"; 61 nvidia,function = "sdmmc1";
62 nvidia,pull = <0>; 62 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
63 nvidia,tristate = <0>; 63 nvidia,tristate = <TEGRA_PIN_DISABLE>;
64 }; 64 };
65 sdmmc1_cmd_pz1 { 65 sdmmc1_cmd_pz1 {
66 nvidia,pins = "sdmmc1_cmd_pz1", 66 nvidia,pins = "sdmmc1_cmd_pz1",
@@ -69,14 +69,14 @@
69 "sdmmc1_dat2_py5", 69 "sdmmc1_dat2_py5",
70 "sdmmc1_dat3_py4"; 70 "sdmmc1_dat3_py4";
71 nvidia,function = "sdmmc1"; 71 nvidia,function = "sdmmc1";
72 nvidia,pull = <2>; 72 nvidia,pull = <TEGRA_PIN_PULL_UP>;
73 nvidia,tristate = <0>; 73 nvidia,tristate = <TEGRA_PIN_DISABLE>;
74 }; 74 };
75 sdmmc3_clk_pa6 { 75 sdmmc3_clk_pa6 {
76 nvidia,pins = "sdmmc3_clk_pa6"; 76 nvidia,pins = "sdmmc3_clk_pa6";
77 nvidia,function = "sdmmc3"; 77 nvidia,function = "sdmmc3";
78 nvidia,pull = <0>; 78 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
79 nvidia,tristate = <0>; 79 nvidia,tristate = <TEGRA_PIN_DISABLE>;
80 }; 80 };
81 sdmmc3_cmd_pa7 { 81 sdmmc3_cmd_pa7 {
82 nvidia,pins = "sdmmc3_cmd_pa7", 82 nvidia,pins = "sdmmc3_cmd_pa7",
@@ -85,15 +85,15 @@
85 "sdmmc3_dat2_pb5", 85 "sdmmc3_dat2_pb5",
86 "sdmmc3_dat3_pb4"; 86 "sdmmc3_dat3_pb4";
87 nvidia,function = "sdmmc3"; 87 nvidia,function = "sdmmc3";
88 nvidia,pull = <2>; 88 nvidia,pull = <TEGRA_PIN_PULL_UP>;
89 nvidia,tristate = <0>; 89 nvidia,tristate = <TEGRA_PIN_DISABLE>;
90 }; 90 };
91 sdmmc4_clk_pcc4 { 91 sdmmc4_clk_pcc4 {
92 nvidia,pins = "sdmmc4_clk_pcc4", 92 nvidia,pins = "sdmmc4_clk_pcc4",
93 "sdmmc4_rst_n_pcc3"; 93 "sdmmc4_rst_n_pcc3";
94 nvidia,function = "sdmmc4"; 94 nvidia,function = "sdmmc4";
95 nvidia,pull = <0>; 95 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
96 nvidia,tristate = <0>; 96 nvidia,tristate = <TEGRA_PIN_DISABLE>;
97 }; 97 };
98 sdmmc4_dat0_paa0 { 98 sdmmc4_dat0_paa0 {
99 nvidia,pins = "sdmmc4_dat0_paa0", 99 nvidia,pins = "sdmmc4_dat0_paa0",
@@ -105,8 +105,8 @@
105 "sdmmc4_dat6_paa6", 105 "sdmmc4_dat6_paa6",
106 "sdmmc4_dat7_paa7"; 106 "sdmmc4_dat7_paa7";
107 nvidia,function = "sdmmc4"; 107 nvidia,function = "sdmmc4";
108 nvidia,pull = <2>; 108 nvidia,pull = <TEGRA_PIN_PULL_UP>;
109 nvidia,tristate = <0>; 109 nvidia,tristate = <TEGRA_PIN_DISABLE>;
110 }; 110 };
111 dap2_fs_pa2 { 111 dap2_fs_pa2 {
112 nvidia,pins = "dap2_fs_pa2", 112 nvidia,pins = "dap2_fs_pa2",
@@ -114,17 +114,17 @@
114 "dap2_din_pa4", 114 "dap2_din_pa4",
115 "dap2_dout_pa5"; 115 "dap2_dout_pa5";
116 nvidia,function = "i2s1"; 116 nvidia,function = "i2s1";
117 nvidia,pull = <0>; 117 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
118 nvidia,tristate = <0>; 118 nvidia,tristate = <TEGRA_PIN_DISABLE>;
119 }; 119 };
120 sdio3 { 120 sdio3 {
121 nvidia,pins = "drive_sdio3"; 121 nvidia,pins = "drive_sdio3";
122 nvidia,high-speed-mode = <0>; 122 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
123 nvidia,schmitt = <0>; 123 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
124 nvidia,pull-down-strength = <46>; 124 nvidia,pull-down-strength = <46>;
125 nvidia,pull-up-strength = <42>; 125 nvidia,pull-up-strength = <42>;
126 nvidia,slew-rate-rising = <1>; 126 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
127 nvidia,slew-rate-falling = <1>; 127 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
128 }; 128 };
129 uart3_txd_pw6 { 129 uart3_txd_pw6 {
130 nvidia,pins = "uart3_txd_pw6", 130 nvidia,pins = "uart3_txd_pw6",
@@ -132,8 +132,8 @@
132 "uart3_rts_n_pc0", 132 "uart3_rts_n_pc0",
133 "uart3_rxd_pw7"; 133 "uart3_rxd_pw7";
134 nvidia,function = "uartc"; 134 nvidia,function = "uartc";
135 nvidia,pull = <0>; 135 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
136 nvidia,tristate = <0>; 136 nvidia,tristate = <TEGRA_PIN_DISABLE>;
137 }; 137 };
138 }; 138 };
139 }; 139 };
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 829eb4b5091d..ee5e9d8bf194 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -1,5 +1,6 @@
1#include <dt-bindings/clock/tegra30-car.h> 1#include <dt-bindings/clock/tegra30-car.h>
2#include <dt-bindings/gpio/tegra-gpio.h> 2#include <dt-bindings/gpio/tegra-gpio.h>
3#include <dt-bindings/pinctrl/pinctrl-tegra.h>
3#include <dt-bindings/interrupt-controller/arm-gic.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h>
4 5
5#include "skeleton.dtsi" 6#include "skeleton.dtsi"
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-17 05:14:29 -0400