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authorStephen Warren <swarren@nvidia.com>2013-11-07 14:20:57 -0500
committerStephen Warren <swarren@nvidia.com>2013-12-16 16:09:17 -0500
commitf71e4f034a57b0203d91aa7c805a12c75f476dab (patch)
tree485c079855597c0895606103a7fc249b1a4629a9
parent3b86baf296eb2791eeeacd2ed07f7d2789784d24 (diff)
ARM: tegra: add reset properties to Tegra124 DTs
The DT bindings now require module resets to be specified. The earlier patches which added these nodes were originally written before that requirement. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
-rw-r--r--arch/arm/boot/dts/tegra124.dtsi11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 936579b806d4..4ed6a3a8e2de 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -36,6 +36,7 @@
36 compatible = "nvidia,tegra124-car"; 36 compatible = "nvidia,tegra124-car";
37 reg = <0x60006000 0x1000>; 37 reg = <0x60006000 0x1000>;
38 #clock-cells = <1>; 38 #clock-cells = <1>;
39 #reset-cells = <1>;
39 }; 40 };
40 41
41 gpio: gpio@6000d000 { 42 gpio: gpio@6000d000 {
@@ -69,6 +70,8 @@
69 reg-shift = <2>; 70 reg-shift = <2>;
70 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 71 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
71 clocks = <&tegra_car TEGRA124_CLK_UARTA>; 72 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
73 resets = <&tegra_car 6>;
74 reset-names = "serial";
72 status = "disabled"; 75 status = "disabled";
73 }; 76 };
74 77
@@ -78,6 +81,8 @@
78 reg-shift = <2>; 81 reg-shift = <2>;
79 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 82 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
80 clocks = <&tegra_car TEGRA124_CLK_UARTB>; 83 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
84 resets = <&tegra_car 7>;
85 reset-names = "serial";
81 status = "disabled"; 86 status = "disabled";
82 }; 87 };
83 88
@@ -87,6 +92,8 @@
87 reg-shift = <2>; 92 reg-shift = <2>;
88 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 93 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
89 clocks = <&tegra_car TEGRA124_CLK_UARTC>; 94 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
95 resets = <&tegra_car 55>;
96 reset-names = "serial";
90 status = "disabled"; 97 status = "disabled";
91 }; 98 };
92 99
@@ -96,6 +103,8 @@
96 reg-shift = <2>; 103 reg-shift = <2>;
97 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 104 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
98 clocks = <&tegra_car TEGRA124_CLK_UARTD>; 105 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
106 resets = <&tegra_car 65>;
107 reset-names = "serial";
99 status = "disabled"; 108 status = "disabled";
100 }; 109 };
101 110
@@ -105,6 +114,8 @@
105 reg-shift = <2>; 114 reg-shift = <2>;
106 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 115 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
107 clocks = <&tegra_car TEGRA124_CLK_UARTE>; 116 clocks = <&tegra_car TEGRA124_CLK_UARTE>;
117 resets = <&tegra_car 66>;
118 reset-names = "serial";
108 status = "disabled"; 119 status = "disabled";
109 }; 120 };
110 121