107 files changed, 5335 insertions, 4248 deletions

diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 64b3f52bd9b2..6da796ef82bd 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -7,24 +7,35 @@ config ARCH_OMAP_OTG
 
 choice
         prompt "OMAP System Type"
-        default ARCH_OMAP1
+        default ARCH_OMAP2PLUS
 
 config ARCH_OMAP1
         bool "TI OMAP1"
         select COMMON_CLKDEV
+        help
+          "Systems based on omap7xx, omap15xx or omap16xx"
+
+config ARCH_OMAP2PLUS
+        bool "TI OMAP2/3/4"
+        select COMMON_CLKDEV
+        help
+          "Systems based on omap24xx, omap34xx or omap44xx"
 
 config ARCH_OMAP2
         bool "TI OMAP2"
+        depends on ARCH_OMAP2PLUS
         select CPU_V6
-        select COMMON_CLKDEV
 
 config ARCH_OMAP3
         bool "TI OMAP3"
+        depends on ARCH_OMAP2PLUS
         select CPU_V7
-        select COMMON_CLKDEV
+        select USB_ARCH_HAS_EHCI
+        select ARM_L1_CACHE_SHIFT_6
 
 config ARCH_OMAP4
         bool "TI OMAP4"
+        depends on ARCH_OMAP2PLUS
         select CPU_V7
         select ARM_GIC
 
@@ -42,28 +53,6 @@ config OMAP_DEBUG_LEDS
         depends on OMAP_DEBUG_DEVICES
         default y if LEDS || LEDS_OMAP_DEBUG
 
-config OMAP_DEBUG_POWERDOMAIN
-        bool "Emit debug messages from powerdomain layer"
-        depends on ARCH_OMAP2 || ARCH_OMAP3
-        help
-          Say Y here if you want to compile in powerdomain layer
-          debugging messages for OMAP2/3.   These messages can
-          provide more detail as to why some powerdomain calls
-          may be failing, and will also emit a descriptive message
-          for every powerdomain register write.  However, the
-          extra detail costs some memory.
-
-config OMAP_DEBUG_CLOCKDOMAIN
-        bool "Emit debug messages from clockdomain layer"
-        depends on ARCH_OMAP2 || ARCH_OMAP3
-        help
-          Say Y here if you want to compile in clockdomain layer
-          debugging messages for OMAP2/3.   These messages can
-          provide more detail as to why some clockdomain calls
-          may be failing, and will also emit a descriptive message
-          for every clockdomain register write.  However, the
-          extra detail costs some memory.
-
 config OMAP_RESET_CLOCKS
         bool "Reset unused clocks during boot"
         depends on ARCH_OMAP
@@ -78,28 +67,28 @@ config OMAP_RESET_CLOCKS
 
 config OMAP_MUX
         bool "OMAP multiplexing support"
-        depends on ARCH_OMAP
+        depends on ARCH_OMAP
         default y
-        help
-          Pin multiplexing support for OMAP boards. If your bootloader
-          sets the multiplexing correctly, say N. Otherwise, or if unsure,
-          say Y.
+        help
+          Pin multiplexing support for OMAP boards. If your bootloader
+          sets the multiplexing correctly, say N. Otherwise, or if unsure,
+          say Y.
 
 config OMAP_MUX_DEBUG
         bool "Multiplexing debug output"
-        depends on OMAP_MUX
-        help
-          Makes the multiplexing functions print out a lot of debug info.
-          This is useful if you want to find out the correct values of the
-          multiplexing registers.
+        depends on OMAP_MUX
+        help
+          Makes the multiplexing functions print out a lot of debug info.
+          This is useful if you want to find out the correct values of the
+          multiplexing registers.
 
 config OMAP_MUX_WARNINGS
         bool "Warn about pins the bootloader didn't set up"
-        depends on OMAP_MUX
-        default y
-        help
+        depends on OMAP_MUX
+        default y
+        help
           Choose Y here to warn whenever driver initialization logic needs
-          to change the pin multiplexing setup.  When there are no warnings
+          to change the pin multiplexing setup.  When there are no warnings
           printed, it's safe to deselect OMAP_MUX for your product.
 
 config OMAP_MCBSP
@@ -125,7 +114,7 @@ config OMAP_IOMMU_DEBUG
         tristate
 
 choice
-        prompt "System timer"
+        prompt "System timer"
         default OMAP_MPU_TIMER
 
 config OMAP_MPU_TIMER
@@ -137,7 +126,7 @@ config OMAP_MPU_TIMER
 
 config OMAP_32K_TIMER
         bool "Use 32KHz timer"
-        depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX || ARCH_OMAP4
+        depends on ARCH_OMAP16XX || ARCH_OMAP2PLUS
         help
           Select this option if you want to enable the OMAP 32KHz timer.
           This timer saves power compared to the OMAP_MPU_TIMER, and has
@@ -147,37 +136,38 @@ config OMAP_32K_TIMER
 
 endchoice
 
+config OMAP3_L2_AUX_SECURE_SAVE_RESTORE
+        bool "OMAP3 HS/EMU save and restore for L2 AUX control register"
+        depends on ARCH_OMAP3 && PM
+        default n
+        help
+          Without this option, L2 Auxiliary control register contents are
+          lost during off-mode entry on HS/EMU devices. This feature
+          requires support from PPA / boot-loader in HS/EMU devices, which
+          currently does not exist by default.
+
+config OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
+        int "Service ID for the support routine to set L2 AUX control"
+        depends on OMAP3_L2_AUX_SECURE_SAVE_RESTORE
+        default 43
+        help
+          PPA routine service ID for setting L2 auxiliary control register.
+
 config OMAP_32K_TIMER_HZ
-       int "Kernel internal timer frequency for 32KHz timer"
-       range 32 1024
-       depends on OMAP_32K_TIMER
-       default "128"
-       help
+        int "Kernel internal timer frequency for 32KHz timer"
+        range 32 1024
+        depends on OMAP_32K_TIMER
+        default "128"
+        help
           Kernel internal timer frequency should be a divisor of 32768,
           such as 64 or 128.
 
 config OMAP_DM_TIMER
         bool "Use dual-mode timer"
-        depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX || ARCH_OMAP4
+        depends on ARCH_OMAP16XX || ARCH_OMAP2PLUS
         help
          Select this option if you want to use OMAP Dual-Mode timers.
 
-choice
-        prompt "Low-level debug console UART"
-        depends on ARCH_OMAP
-        default OMAP_LL_DEBUG_UART1
-
-config OMAP_LL_DEBUG_UART1
-        bool "UART1"
-
-config OMAP_LL_DEBUG_UART2
-        bool "UART2"
-
-config OMAP_LL_DEBUG_UART3
-        bool "UART3"
-
-endchoice
-
 config OMAP_SERIAL_WAKE
         bool "Enable wake-up events for serial ports"
         depends on ARCH_OMAP1 && OMAP_MUX
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index bf880e966d3b..5261a0923691 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -24,7 +24,7 @@
 #include <linux/debugfs.h>
 #include <linux/io.h>
 
-#include <mach/clock.h>
+#include <plat/clock.h>
 
 static LIST_HEAD(clocks);
 static DEFINE_MUTEX(clocks_mutex);
@@ -36,40 +36,10 @@ static struct clk_functions *arch_clock;
  * Standard clock functions defined in include/linux/clk.h
  *-------------------------------------------------------------------------*/
 
-/* This functions is moved to arch/arm/common/clkdev.c. For OMAP4 since
- * clock framework is not up , it is defined here to avoid rework in
- * every driver. Also dummy prcm reset function is added */
-
-/* Dummy hooks only for OMAP4.For rest OMAPs, common clkdev is used */
-#if defined(CONFIG_ARCH_OMAP4)
-struct clk *clk_get(struct device *dev, const char *id)
-{
-        return NULL;
-}
-EXPORT_SYMBOL(clk_get);
-
-void clk_put(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_put);
-
-void omap2_clk_prepare_for_reboot(void)
-{
-}
-EXPORT_SYMBOL(omap2_clk_prepare_for_reboot);
-
-void omap_prcm_arch_reset(char mode)
-{
-}
-EXPORT_SYMBOL(omap_prcm_arch_reset);
-#endif
 int clk_enable(struct clk *clk)
 {
         unsigned long flags;
         int ret = 0;
-        if (cpu_is_omap44xx())
-                /* OMAP4 clk framework not supported yet */
-                return 0;
 
         if (clk == NULL || IS_ERR(clk))
                 return -EINVAL;
@@ -203,7 +173,7 @@ EXPORT_SYMBOL(clk_get_parent);
  * OMAP specific clock functions shared between omap1 and omap2
  *-------------------------------------------------------------------------*/
 
-unsigned int __initdata mpurate;
+int __initdata mpurate;
 
 /*
  * By default we use the rate set by the bootloader.
@@ -229,6 +199,17 @@ unsigned long followparent_recalc(struct clk *clk)
         return clk->parent->rate;
 }
 
+/*
+ * Used for clocks that have the same value as the parent clock,
+ * divided by some factor
+ */
+unsigned long omap_fixed_divisor_recalc(struct clk *clk)
+{
+        WARN_ON(!clk->fixed_div);
+
+        return clk->parent->rate / clk->fixed_div;
+}
+
 void clk_reparent(struct clk *child, struct clk *parent)
 {
         list_del_init(&child->sibling);
@@ -331,7 +312,33 @@ void clk_enable_init_clocks(void)
                         clk_enable(clkp);
         }
 }
-EXPORT_SYMBOL(clk_enable_init_clocks);
+
+/**
+ * omap_clk_get_by_name - locate OMAP struct clk by its name
+ * @name: name of the struct clk to locate
+ *
+ * Locate an OMAP struct clk by its name.  Assumes that struct clk
+ * names are unique.  Returns NULL if not found or a pointer to the
+ * struct clk if found.
+ */
+struct clk *omap_clk_get_by_name(const char *name)
+{
+        struct clk *c;
+        struct clk *ret = NULL;
+
+        mutex_lock(&clocks_mutex);
+
+        list_for_each_entry(c, &clocks, node) {
+                if (!strcmp(c->name, name)) {
+                        ret = c;
+                        break;
+                }
+        }
+
+        mutex_unlock(&clocks_mutex);
+
+        return ret;
+}
 
 /*
  * Low level helpers
@@ -350,6 +357,16 @@ const struct clkops clkops_null = {
         .disable        = clkll_disable_null,
 };
 
+/*
+ * Dummy clock
+ *
+ * Used for clock aliases that are needed on some OMAPs, but not others
+ */
+struct clk dummy_ck = {
+        .name   = "dummy",
+        .ops    = &clkops_null,
+};
+
 #ifdef CONFIG_CPU_FREQ
 void clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
 {
@@ -360,7 +377,16 @@ void clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
                 arch_clock->clk_init_cpufreq_table(table);
         spin_unlock_irqrestore(&clockfw_lock, flags);
 }
-EXPORT_SYMBOL(clk_init_cpufreq_table);
+
+void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+        if (arch_clock->clk_exit_cpufreq_table)
+                arch_clock->clk_exit_cpufreq_table(table);
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+}
 #endif
 
 /*-------------------------------------------------------------------------*/
@@ -413,14 +439,12 @@ static struct dentry *clk_debugfs_root;
 static int clk_debugfs_register_one(struct clk *c)
 {
         int err;
-        struct dentry *d, *child;
+        struct dentry *d, *child, *child_tmp;
         struct clk *pa = c->parent;
         char s[255];
         char *p = s;
 
         p += sprintf(p, "%s", c->name);
-        if (c->id != 0)
-                sprintf(p, ":%d", c->id);
         d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
         if (!d)
                 return -ENOMEM;
@@ -445,7 +469,7 @@ static int clk_debugfs_register_one(struct clk *c)
 
 err_out:
         d = c->dent;
-        list_for_each_entry(child, &d->d_subdirs, d_u.d_child)
+        list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child)
                 debugfs_remove(child);
         debugfs_remove(c->dent);
         return err;
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 3a4768d55895..f12f0e39ddf2 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -29,13 +29,14 @@
 #include <asm/mach/map.h>
 #include <asm/setup.h>
 
-#include <mach/common.h>
-#include <mach/board.h>
-#include <mach/control.h>
-#include <mach/mux.h>
-#include <mach/fpga.h>
+#include <plat/common.h>
+#include <plat/board.h>
+#include <plat/control.h>
+#include <plat/mux.h>
+#include <plat/fpga.h>
+#include <plat/serial.h>
 
-#include <mach/clock.h>
+#include <plat/clock.h>
 
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
 # include "../mach-omap2/sdrc.h"
@@ -43,12 +44,12 @@
 
 #define NO_LENGTH_CHECK 0xffffffff
 
-unsigned char omap_bootloader_tag[512];
-int omap_bootloader_tag_len;
-
 struct omap_board_config_kernel *omap_board_config;
 int omap_board_config_size;
 
+/* used by omap-smp.c and board-4430sdp.c */
+void __iomem *gic_cpu_base_addr;
+
 static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out)
 {
         struct omap_board_config_kernel *kinfo = NULL;
@@ -96,10 +97,17 @@ EXPORT_SYMBOL(omap_get_var_config);
 
 #include <linux/clocksource.h>
 
+/*
+ * offset_32k holds the init time counter value. It is then subtracted
+ * from every counter read to achieve a counter that counts time from the
+ * kernel boot (needed for sched_clock()).
+ */
+static u32 offset_32k __read_mostly;
+
 #ifdef CONFIG_ARCH_OMAP16XX
 static cycle_t omap16xx_32k_read(struct clocksource *cs)
 {
-        return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED);
+        return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED) - offset_32k;
 }
 #else
 #define omap16xx_32k_read       NULL
@@ -108,7 +116,7 @@ static cycle_t omap16xx_32k_read(struct clocksource *cs)
 #ifdef CONFIG_ARCH_OMAP2420
 static cycle_t omap2420_32k_read(struct clocksource *cs)
 {
-        return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10);
+        return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k;
 }
 #else
 #define omap2420_32k_read       NULL
@@ -117,16 +125,16 @@ static cycle_t omap2420_32k_read(struct clocksource *cs)
 #ifdef CONFIG_ARCH_OMAP2430
 static cycle_t omap2430_32k_read(struct clocksource *cs)
 {
-        return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10);
+        return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k;
 }
 #else
 #define omap2430_32k_read       NULL
 #endif
 
-#ifdef CONFIG_ARCH_OMAP34XX
+#ifdef CONFIG_ARCH_OMAP3
 static cycle_t omap34xx_32k_read(struct clocksource *cs)
 {
-        return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10);
+        return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10) - offset_32k;
 }
 #else
 #define omap34xx_32k_read       NULL
@@ -135,7 +143,7 @@ static cycle_t omap34xx_32k_read(struct clocksource *cs)
 #ifdef CONFIG_ARCH_OMAP4
 static cycle_t omap44xx_32k_read(struct clocksource *cs)
 {
-        return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10);
+        return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10) - offset_32k;
 }
 #else
 #define omap44xx_32k_read       NULL
@@ -169,6 +177,32 @@ unsigned long long sched_clock(void)
                                   clocksource_32k.mult, clocksource_32k.shift);
 }
 
+/**
+ * read_persistent_clock -  Return time from a persistent clock.
+ *
+ * Reads the time from a source which isn't disabled during PM, the
+ * 32k sync timer.  Convert the cycles elapsed since last read into
+ * nsecs and adds to a monotonically increasing timespec.
+ */
+static struct timespec persistent_ts;
+static cycles_t cycles, last_cycles;
+void read_persistent_clock(struct timespec *ts)
+{
+        unsigned long long nsecs;
+        cycles_t delta;
+        struct timespec *tsp = &persistent_ts;
+
+        last_cycles = cycles;
+        cycles = clocksource_32k.read(&clocksource_32k);
+        delta = cycles - last_cycles;
+
+        nsecs = clocksource_cyc2ns(delta,
+                                   clocksource_32k.mult, clocksource_32k.shift);
+
+        timespec_add_ns(tsp, nsecs);
+        *ts = *tsp;
+}
+
 static int __init omap_init_clocksource_32k(void)
 {
         static char err[] __initdata = KERN_ERR
@@ -197,6 +231,8 @@ static int __init omap_init_clocksource_32k(void)
                 clocksource_32k.mult = clocksource_hz2mult(32768,
                                             clocksource_32k.shift);
 
+                offset_32k = clocksource_32k.read(&clocksource_32k);
+
                 if (clocksource_register(&clocksource_32k))
                         printk(err, clocksource_32k.name);
         }
@@ -216,6 +252,7 @@ static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
         omap2_set_globals_sdrc(omap2_globals);
         omap2_set_globals_control(omap2_globals);
         omap2_set_globals_prcm(omap2_globals);
+        omap2_set_globals_uart(omap2_globals);
 }
 
 #endif
@@ -224,12 +261,15 @@ static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
 
 static struct omap_globals omap242x_globals = {
         .class  = OMAP242X_CLASS,
-        .tap    = OMAP2_IO_ADDRESS(0x48014000),
-        .sdrc   = OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE),
-        .sms    = OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE),
-        .ctrl   = OMAP2_IO_ADDRESS(OMAP2420_CTRL_BASE),
-        .prm    = OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE),
-        .cm     = OMAP2_IO_ADDRESS(OMAP2420_CM_BASE),
+        .tap    = OMAP2_L4_IO_ADDRESS(0x48014000),
+        .sdrc   = OMAP2420_SDRC_BASE,
+        .sms    = OMAP2420_SMS_BASE,
+        .ctrl   = OMAP2420_CTRL_BASE,
+        .prm    = OMAP2420_PRM_BASE,
+        .cm     = OMAP2420_CM_BASE,
+        .uart1_phys     = OMAP2_UART1_BASE,
+        .uart2_phys     = OMAP2_UART2_BASE,
+        .uart3_phys     = OMAP2_UART3_BASE,
 };
 
 void __init omap2_set_globals_242x(void)
@@ -242,12 +282,15 @@ void __init omap2_set_globals_242x(void)
 
 static struct omap_globals omap243x_globals = {
         .class  = OMAP243X_CLASS,
-        .tap    = OMAP2_IO_ADDRESS(0x4900a000),
-        .sdrc   = OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE),
-        .sms    = OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE),
-        .ctrl   = OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE),
-        .prm    = OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE),
-        .cm     = OMAP2_IO_ADDRESS(OMAP2430_CM_BASE),
+        .tap    = OMAP2_L4_IO_ADDRESS(0x4900a000),
+        .sdrc   = OMAP243X_SDRC_BASE,
+        .sms    = OMAP243X_SMS_BASE,
+        .ctrl   = OMAP243X_CTRL_BASE,
+        .prm    = OMAP2430_PRM_BASE,
+        .cm     = OMAP2430_CM_BASE,
+        .uart1_phys     = OMAP2_UART1_BASE,
+        .uart2_phys     = OMAP2_UART2_BASE,
+        .uart3_phys     = OMAP2_UART3_BASE,
 };
 
 void __init omap2_set_globals_243x(void)
@@ -256,37 +299,54 @@ void __init omap2_set_globals_243x(void)
 }
 #endif
 
-#if defined(CONFIG_ARCH_OMAP3430)
+#if defined(CONFIG_ARCH_OMAP3)
 
-static struct omap_globals omap343x_globals = {
+static struct omap_globals omap3_globals = {
         .class  = OMAP343X_CLASS,
-        .tap    = OMAP2_IO_ADDRESS(0x4830A000),
-        .sdrc   = OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE),
-        .sms    = OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE),
-        .ctrl   = OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE),
-        .prm    = OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE),
-        .cm     = OMAP2_IO_ADDRESS(OMAP3430_CM_BASE),
+        .tap    = OMAP2_L4_IO_ADDRESS(0x4830A000),
+        .sdrc   = OMAP343X_SDRC_BASE,
+        .sms    = OMAP343X_SMS_BASE,
+        .ctrl   = OMAP343X_CTRL_BASE,
+        .prm    = OMAP3430_PRM_BASE,
+        .cm     = OMAP3430_CM_BASE,
+        .uart1_phys     = OMAP3_UART1_BASE,
+        .uart2_phys     = OMAP3_UART2_BASE,
+        .uart3_phys     = OMAP3_UART3_BASE,
 };
 
 void __init omap2_set_globals_343x(void)
 {
-        __omap2_set_globals(&omap343x_globals);
+        __omap2_set_globals(&omap3_globals);
+}
+
+void __init omap2_set_globals_36xx(void)
+{
+        omap3_globals.uart4_phys = OMAP3_UART4_BASE;
+
+        __omap2_set_globals(&omap3_globals);
 }
 #endif
 
 #if defined(CONFIG_ARCH_OMAP4)
 static struct omap_globals omap4_globals = {
         .class  = OMAP443X_CLASS,
-        .tap    = OMAP2_IO_ADDRESS(0x4830a000),
-        .ctrl   = OMAP2_IO_ADDRESS(OMAP443X_CTRL_BASE),
-        .prm    = OMAP2_IO_ADDRESS(OMAP4430_PRM_BASE),
-        .cm     = OMAP2_IO_ADDRESS(OMAP4430_CM_BASE),
+        .tap    = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
+        .ctrl   = OMAP443X_CTRL_BASE,
+        .prm    = OMAP4430_PRM_BASE,
+        .cm     = OMAP4430_CM_BASE,
+        .cm2    = OMAP4430_CM2_BASE,
+        .uart1_phys     = OMAP4_UART1_BASE,
+        .uart2_phys     = OMAP4_UART2_BASE,
+        .uart3_phys     = OMAP4_UART3_BASE,
+        .uart4_phys     = OMAP4_UART4_BASE,
 };
 
 void __init omap2_set_globals_443x(void)
 {
         omap2_set_globals_tap(&omap4_globals);
         omap2_set_globals_control(&omap4_globals);
+        omap2_set_globals_prcm(&omap4_globals);
+        omap2_set_globals_uart(&omap4_globals);
 }
 #endif
 
diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c
index 341235c278ac..6d3d33360056 100644
--- a/arch/arm/plat-omap/cpu-omap.c
+++ b/arch/arm/plat-omap/cpu-omap.c
@@ -23,7 +23,7 @@
 #include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <mach/clock.h>
+#include <plat/clock.h>
 #include <asm/system.h>
 
 #define VERY_HI_RATE    900000000
@@ -134,6 +134,7 @@ static int __init omap_cpu_init(struct cpufreq_policy *policy)
 
 static int omap_cpu_exit(struct cpufreq_policy *policy)
 {
+        clk_exit_cpufreq_table(&freq_table);
         clk_put(mpu_clk);
         return 0;
 }
diff --git a/arch/arm/plat-omap/debug-devices.c b/arch/arm/plat-omap/debug-devices.c
index f6684832ca8f..923c9621096b 100644
--- a/arch/arm/plat-omap/debug-devices.c
+++ b/arch/arm/plat-omap/debug-devices.c
@@ -13,10 +13,11 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/smc91x.h>
 
 #include <mach/hardware.h>
 
-#include <mach/board.h>
+#include <plat/board.h>
 #include <mach/gpio.h>
 
 
@@ -24,6 +25,12 @@
  * platforms include H2, H3, H4, and Perseus2.
  */
 
+static struct smc91x_platdata smc91x_info = {
+        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
+        .leda   = RPC_LED_100_10,
+        .ledb   = RPC_LED_TX_RX,
+};
+
 static struct resource smc91x_resources[] = {
         [0] = {
                 .flags  = IORESOURCE_MEM,
@@ -36,6 +43,9 @@ static struct resource smc91x_resources[] = {
 static struct platform_device smc91x_device = {
         .name           = "smc91x",
         .id             = -1,
+        .dev            = {
+                .platform_data = &smc91x_info,
+        },
         .num_resources  = ARRAY_SIZE(smc91x_resources),
         .resource       = smc91x_resources,
 };
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index 9395898dd49a..53fcef7c5201 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -18,7 +18,7 @@
 #include <asm/system.h>
 #include <asm/mach-types.h>
 
-#include <mach/fpga.h>
+#include <plat/fpga.h>
 #include <mach/gpio.h>
 
 
@@ -293,7 +293,7 @@ static int fpga_resume_noirq(struct device *dev)
         return 0;
 }
 
-static struct dev_pm_ops fpga_dev_pm_ops = {
+static const struct dev_pm_ops fpga_dev_pm_ops = {
         .suspend_noirq = fpga_suspend_noirq,
         .resume_noirq = fpga_resume_noirq,
 };
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index a64b692a1bfe..95677d17cd1c 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -14,20 +14,22 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/slab.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
 
-#include <mach/tc.h>
-#include <mach/control.h>
-#include <mach/board.h>
-#include <mach/mmc.h>
-#include <mach/mux.h>
+#include <plat/tc.h>
+#include <plat/control.h>
+#include <plat/board.h>
+#include <plat/mmc.h>
+#include <plat/mux.h>
 #include <mach/gpio.h>
-#include <mach/menelaus.h>
-#include <mach/mcbsp.h>
-#include <mach/dsp_common.h>
+#include <plat/menelaus.h>
+#include <plat/mcbsp.h>
+#include <plat/dsp_common.h>
+#include <plat/omap44xx.h>
 
 #if     defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
 
@@ -113,17 +115,17 @@ static void omap_init_kp(void)
                 omap_cfg_reg(E19_1610_KBR4);
                 omap_cfg_reg(N19_1610_KBR5);
         } else if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
-                omap_cfg_reg(E2_730_KBR0);
-                omap_cfg_reg(J7_730_KBR1);
-                omap_cfg_reg(E1_730_KBR2);
-                omap_cfg_reg(F3_730_KBR3);
-                omap_cfg_reg(D2_730_KBR4);
-
-                omap_cfg_reg(C2_730_KBC0);
-                omap_cfg_reg(D3_730_KBC1);
-                omap_cfg_reg(E4_730_KBC2);
-                omap_cfg_reg(F4_730_KBC3);
-                omap_cfg_reg(E3_730_KBC4);
+                omap_cfg_reg(E2_7XX_KBR0);
+                omap_cfg_reg(J7_7XX_KBR1);
+                omap_cfg_reg(E1_7XX_KBR2);
+                omap_cfg_reg(F3_7XX_KBR3);
+                omap_cfg_reg(D2_7XX_KBR4);
+
+                omap_cfg_reg(C2_7XX_KBC0);
+                omap_cfg_reg(D3_7XX_KBC1);
+                omap_cfg_reg(E4_7XX_KBC2);
+                omap_cfg_reg(F4_7XX_KBC3);
+                omap_cfg_reg(E3_7XX_KBC4);
         } else if (machine_is_omap_h4()) {
                 omap_cfg_reg(T19_24XX_KBR0);
                 omap_cfg_reg(R19_24XX_KBR1);
@@ -192,6 +194,41 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
 
 /*-------------------------------------------------------------------------*/
 
+#if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \
+                defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE)
+
+static struct resource mcpdm_resources[] = {
+        {
+                .name           = "mcpdm_mem",
+                .start          = OMAP44XX_MCPDM_BASE,
+                .end            = OMAP44XX_MCPDM_BASE + SZ_4K,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .name           = "mcpdm_irq",
+                .start          = OMAP44XX_IRQ_MCPDM,
+                .end            = OMAP44XX_IRQ_MCPDM,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device omap_mcpdm_device = {
+        .name           = "omap-mcpdm",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(mcpdm_resources),
+        .resource       = mcpdm_resources,
+};
+
+static void omap_init_mcpdm(void)
+{
+        (void) platform_device_register(&omap_mcpdm_device);
+}
+#else
+static inline void omap_init_mcpdm(void) {}
+#endif
+
+/*-------------------------------------------------------------------------*/
+
 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
         defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
 
@@ -242,6 +279,39 @@ fail:
 
 /*-------------------------------------------------------------------------*/
 
+#if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE)
+
+#ifdef CONFIG_ARCH_OMAP2
+#define OMAP_RNG_BASE           0x480A0000
+#else
+#define OMAP_RNG_BASE           0xfffe5000
+#endif
+
+static struct resource rng_resources[] = {
+        {
+                .start          = OMAP_RNG_BASE,
+                .end            = OMAP_RNG_BASE + 0x4f,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device omap_rng_device = {
+        .name           = "omap_rng",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(rng_resources),
+        .resource       = rng_resources,
+};
+
+static void omap_init_rng(void)
+{
+        (void) platform_device_register(&omap_rng_device);
+}
+#else
+static inline void omap_init_rng(void) {}
+#endif
+
+/*-------------------------------------------------------------------------*/
+
 /* Numbering for the SPI-capable controllers when used for SPI:
  * spi          = 1
  * uwire        = 2
@@ -324,39 +394,6 @@ static void omap_init_wdt(void)
 static inline void omap_init_wdt(void) {}
 #endif
 
-/*-------------------------------------------------------------------------*/
-
-#if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE)
-
-#ifdef CONFIG_ARCH_OMAP24XX
-#define OMAP_RNG_BASE           0x480A0000
-#else
-#define OMAP_RNG_BASE           0xfffe5000
-#endif
-
-static struct resource rng_resources[] = {
-        {
-                .start          = OMAP_RNG_BASE,
-                .end            = OMAP_RNG_BASE + 0x4f,
-                .flags          = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device omap_rng_device = {
-        .name      = "omap_rng",
-        .id          = -1,
-        .num_resources  = ARRAY_SIZE(rng_resources),
-        .resource       = rng_resources,
-};
-
-static void omap_init_rng(void)
-{
-        (void) platform_device_register(&omap_rng_device);
-}
-#else
-static inline void omap_init_rng(void) {}
-#endif
-
 /*
  * This gets called after board-specific INIT_MACHINE, and initializes most
  * on-chip peripherals accessible on this board (except for few like USB):
@@ -384,9 +421,10 @@ static int __init omap_init_devices(void)
          */
         omap_init_dsp();
         omap_init_kp();
+        omap_init_rng();
+        omap_init_mcpdm();
         omap_init_uwire();
         omap_init_wdt();
-        omap_init_rng();
         return 0;
 }
 arch_initcall(omap_init_devices);
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 68eaae324b6a..1d959965ff52 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -29,12 +29,13 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/io.h>
+#include <linux/slab.h>
 
 #include <asm/system.h>
 #include <mach/hardware.h>
-#include <mach/dma.h>
+#include <plat/dma.h>
 
-#include <mach/tc.h>
+#include <plat/tc.h>
 
 #undef DEBUG
 
@@ -47,13 +48,18 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
 #endif
 
 #define OMAP_DMA_ACTIVE                 0x01
-#define OMAP_DMA_CCR_EN                 (1 << 7)
 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffe
 
 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
 
 static int enable_1510_mode;
 
+static struct omap_dma_global_context_registers {
+        u32 dma_irqenable_l0;
+        u32 dma_ocp_sysconfig;
+        u32 dma_gcr;
+} omap_dma_global_context;
+
 struct omap_dma_lch {
         int next_lch;
         int dev_id;
@@ -931,6 +937,15 @@ void omap_start_dma(int lch)
 {
         u32 l;
 
+        /*
+         * The CPC/CDAC register needs to be initialized to zero
+         * before starting dma transfer.
+         */
+        if (cpu_is_omap15xx())
+                dma_write(0, CPC(lch));
+        else
+                dma_write(0, CDAC(lch));
+
         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
                 int next_lch, cur_lch;
                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
@@ -1114,17 +1129,8 @@ int omap_dma_running(void)
 {
         int lch;
 
-        /*
-         * On OMAP1510, internal LCD controller will start the transfer
-         * when it gets enabled, so assume DMA running if LCD enabled.
-         */
-        if (cpu_is_omap1510())
-                if (omap_readw(0xfffec000 + 0x00) & (1 << 0))
-                        return 1;
-
-        /* Check if LCD DMA is running */
-        if (cpu_is_omap16xx())
-                if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
+        if (cpu_class_is_omap1())
+                if (omap_lcd_dma_running())
                         return 1;
 
         for (lch = 0; lch < dma_chan_count; lch++)
@@ -1187,7 +1193,7 @@ void omap_dma_unlink_lch(int lch_head, int lch_queue)
         }
 
         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
-            (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
+            (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
                        "before unlinking\n");
                 dump_stack();
@@ -1246,7 +1252,7 @@ static void create_dma_lch_chain(int lch_head, int lch_queue)
  *                                            OMAP_DMA_DYNAMIC_CHAIN
  * @params - Channel parameters
  *
- * @return - Succes : 0
+ * @return - Success : 0
  *           Failure: -EINVAL/-ENOMEM
  */
 int omap_request_dma_chain(int dev_id, const char *dev_name,
@@ -1874,8 +1880,7 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
 #define omap1_dma_irq_handler   NULL
 #endif
 
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
-                        defined(CONFIG_ARCH_OMAP4)
+#ifdef CONFIG_ARCH_OMAP2PLUS
 
 static int omap2_dma_handle_ch(int ch)
 {
@@ -1984,415 +1989,83 @@ static struct irqaction omap24xx_dma_irq;
 
 /*----------------------------------------------------------------------------*/
 
-static struct lcd_dma_info {
-        spinlock_t lock;
-        int reserved;
-        void (*callback)(u16 status, void *data);
-        void *cb_data;
-
-        int active;
-        unsigned long addr, size;
-        int rotate, data_type, xres, yres;
-        int vxres;
-        int mirror;
-        int xscale, yscale;
-        int ext_ctrl;
-        int src_port;
-        int single_transfer;
-} lcd_dma;
-
-void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
-                         int data_type)
-{
-        lcd_dma.addr = addr;
-        lcd_dma.data_type = data_type;
-        lcd_dma.xres = fb_xres;
-        lcd_dma.yres = fb_yres;
-}
-EXPORT_SYMBOL(omap_set_lcd_dma_b1);
-
-void omap_set_lcd_dma_src_port(int port)
-{
-        lcd_dma.src_port = port;
-}
-
-void omap_set_lcd_dma_ext_controller(int external)
+void omap_dma_global_context_save(void)
 {
-        lcd_dma.ext_ctrl = external;
+        omap_dma_global_context.dma_irqenable_l0 =
+                dma_read(IRQENABLE_L0);
+        omap_dma_global_context.dma_ocp_sysconfig =
+                dma_read(OCP_SYSCONFIG);
+        omap_dma_global_context.dma_gcr = dma_read(GCR);
 }
-EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
 
-void omap_set_lcd_dma_single_transfer(int single)
+void omap_dma_global_context_restore(void)
 {
-        lcd_dma.single_transfer = single;
-}
-EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
+        int ch;
 
-void omap_set_lcd_dma_b1_rotation(int rotate)
-{
-        if (omap_dma_in_1510_mode()) {
-                printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
-                BUG();
-                return;
-        }
-        lcd_dma.rotate = rotate;
-}
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
-
-void omap_set_lcd_dma_b1_mirror(int mirror)
-{
-        if (omap_dma_in_1510_mode()) {
-                printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
-                BUG();
-        }
-        lcd_dma.mirror = mirror;
-}
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
-
-void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
-{
-        if (omap_dma_in_1510_mode()) {
-                printk(KERN_ERR "DMA virtual resulotion is not supported "
-                                "in 1510 mode\n");
-                BUG();
-        }
-        lcd_dma.vxres = vxres;
-}
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
-
-void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
-{
-        if (omap_dma_in_1510_mode()) {
-                printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
-                BUG();
-        }
-        lcd_dma.xscale = xscale;
-        lcd_dma.yscale = yscale;
-}
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
-
-static void set_b1_regs(void)
-{
-        unsigned long top, bottom;
-        int es;
-        u16 w;
-        unsigned long en, fn;
-        long ei, fi;
-        unsigned long vxres;
-        unsigned int xscale, yscale;
-
-        switch (lcd_dma.data_type) {
-        case OMAP_DMA_DATA_TYPE_S8:
-                es = 1;
-                break;
-        case OMAP_DMA_DATA_TYPE_S16:
-                es = 2;
-                break;
-        case OMAP_DMA_DATA_TYPE_S32:
-                es = 4;
-                break;
-        default:
-                BUG();
-                return;
-        }
-
-        vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
-        xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
-        yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
-        BUG_ON(vxres < lcd_dma.xres);
-
-#define PIXADDR(x, y) (lcd_dma.addr +                                   \
-                ((y) * vxres * yscale + (x) * xscale) * es)
-#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
-
-        switch (lcd_dma.rotate) {
-        case 0:
-                if (!lcd_dma.mirror) {
-                        top = PIXADDR(0, 0);
-                        bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
-                        /* 1510 DMA requires the bottom address to be 2 more
-                         * than the actual last memory access location. */
-                        if (omap_dma_in_1510_mode() &&
-                                lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
-                                        bottom += 2;
-                        ei = PIXSTEP(0, 0, 1, 0);
-                        fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
-                } else {
-                        top = PIXADDR(lcd_dma.xres - 1, 0);
-                        bottom = PIXADDR(0, lcd_dma.yres - 1);
-                        ei = PIXSTEP(1, 0, 0, 0);
-                        fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
-                }
-                en = lcd_dma.xres;
-                fn = lcd_dma.yres;
-                break;
-        case 90:
-                if (!lcd_dma.mirror) {
-                        top = PIXADDR(0, lcd_dma.yres - 1);
-                        bottom = PIXADDR(lcd_dma.xres - 1, 0);
-                        ei = PIXSTEP(0, 1, 0, 0);
-                        fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
-                } else {
-                        top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
-                        bottom = PIXADDR(0, 0);
-                        ei = PIXSTEP(0, 1, 0, 0);
-                        fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
-                }
-                en = lcd_dma.yres;
-                fn = lcd_dma.xres;
-                break;
-        case 180:
-                if (!lcd_dma.mirror) {
-                        top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
-                        bottom = PIXADDR(0, 0);
-                        ei = PIXSTEP(1, 0, 0, 0);
-                        fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
-                } else {
-                        top = PIXADDR(0, lcd_dma.yres - 1);
-                        bottom = PIXADDR(lcd_dma.xres - 1, 0);
-                        ei = PIXSTEP(0, 0, 1, 0);
-                        fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
-                }
-                en = lcd_dma.xres;
-                fn = lcd_dma.yres;
-                break;
-        case 270:
-                if (!lcd_dma.mirror) {
-                        top = PIXADDR(lcd_dma.xres - 1, 0);
-                        bottom = PIXADDR(0, lcd_dma.yres - 1);
-                        ei = PIXSTEP(0, 0, 0, 1);
-                        fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
-                } else {
-                        top = PIXADDR(0, 0);
-                        bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
-                        ei = PIXSTEP(0, 0, 0, 1);
-                        fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
-                }
-                en = lcd_dma.yres;
-                fn = lcd_dma.xres;
-                break;
-        default:
-                BUG();
-                return; /* Suppress warning about uninitialized vars */
-        }
-
-        if (omap_dma_in_1510_mode()) {
-                omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
-                omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
-                omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
-                omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
-
-                return;
-        }
-
-        /* 1610 regs */
-        omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
-        omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
-        omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
-        omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
-
-        omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
-        omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
-
-        w = omap_readw(OMAP1610_DMA_LCD_CSDP);
-        w &= ~0x03;
-        w |= lcd_dma.data_type;
-        omap_writew(w, OMAP1610_DMA_LCD_CSDP);
-
-        w = omap_readw(OMAP1610_DMA_LCD_CTRL);
-        /* Always set the source port as SDRAM for now*/
-        w &= ~(0x03 << 6);
-        if (lcd_dma.callback != NULL)
-                w |= 1 << 1;            /* Block interrupt enable */
-        else
-                w &= ~(1 << 1);
-        omap_writew(w, OMAP1610_DMA_LCD_CTRL);
-
-        if (!(lcd_dma.rotate || lcd_dma.mirror ||
-              lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
-                return;
-
-        w = omap_readw(OMAP1610_DMA_LCD_CCR);
-        /* Set the double-indexed addressing mode */
-        w |= (0x03 << 12);
-        omap_writew(w, OMAP1610_DMA_LCD_CCR);
-
-        omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
-        omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
-        omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
-}
-
-static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
-{
-        u16 w;
-
-        w = omap_readw(OMAP1610_DMA_LCD_CTRL);
-        if (unlikely(!(w & (1 << 3)))) {
-                printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
-                return IRQ_NONE;
-        }
-        /* Ack the IRQ */
-        w |= (1 << 3);
-        omap_writew(w, OMAP1610_DMA_LCD_CTRL);
-        lcd_dma.active = 0;
-        if (lcd_dma.callback != NULL)
-                lcd_dma.callback(w, lcd_dma.cb_data);
-
-        return IRQ_HANDLED;
-}
-
-int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
-                         void *data)
-{
-        spin_lock_irq(&lcd_dma.lock);
-        if (lcd_dma.reserved) {
-                spin_unlock_irq(&lcd_dma.lock);
-                printk(KERN_ERR "LCD DMA channel already reserved\n");
-                BUG();
-                return -EBUSY;
-        }
-        lcd_dma.reserved = 1;
-        spin_unlock_irq(&lcd_dma.lock);
-        lcd_dma.callback = callback;
-        lcd_dma.cb_data = data;
-        lcd_dma.active = 0;
-        lcd_dma.single_transfer = 0;
-        lcd_dma.rotate = 0;
-        lcd_dma.vxres = 0;
-        lcd_dma.mirror = 0;
-        lcd_dma.xscale = 0;
-        lcd_dma.yscale = 0;
-        lcd_dma.ext_ctrl = 0;
-        lcd_dma.src_port = 0;
-
-        return 0;
-}
-EXPORT_SYMBOL(omap_request_lcd_dma);
-
-void omap_free_lcd_dma(void)
-{
-        spin_lock(&lcd_dma.lock);
-        if (!lcd_dma.reserved) {
-                spin_unlock(&lcd_dma.lock);
-                printk(KERN_ERR "LCD DMA is not reserved\n");
-                BUG();
-                return;
-        }
-        if (!enable_1510_mode)
-                omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
-                            OMAP1610_DMA_LCD_CCR);
-        lcd_dma.reserved = 0;
-        spin_unlock(&lcd_dma.lock);
-}
-EXPORT_SYMBOL(omap_free_lcd_dma);
-
-void omap_enable_lcd_dma(void)
-{
-        u16 w;
+        dma_write(omap_dma_global_context.dma_gcr, GCR);
+        dma_write(omap_dma_global_context.dma_ocp_sysconfig,
+                OCP_SYSCONFIG);
+        dma_write(omap_dma_global_context.dma_irqenable_l0,
+                IRQENABLE_L0);
 
         /*
-         * Set the Enable bit only if an external controller is
-         * connected. Otherwise the OMAP internal controller will
-         * start the transfer when it gets enabled.
+         * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
+         * after secure sram context save and restore. Hence we need to
+         * manually clear those IRQs to avoid spurious interrupts. This
+         * affects only secure devices.
          */
-        if (enable_1510_mode || !lcd_dma.ext_ctrl)
-                return;
-
-        w = omap_readw(OMAP1610_DMA_LCD_CTRL);
-        w |= 1 << 8;
-        omap_writew(w, OMAP1610_DMA_LCD_CTRL);
-
-        lcd_dma.active = 1;
+        if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
+                dma_write(0x3 , IRQSTATUS_L0);
 
-        w = omap_readw(OMAP1610_DMA_LCD_CCR);
-        w |= 1 << 7;
-        omap_writew(w, OMAP1610_DMA_LCD_CCR);
+        for (ch = 0; ch < dma_chan_count; ch++)
+                if (dma_chan[ch].dev_id != -1)
+                        omap_clear_dma(ch);
 }
-EXPORT_SYMBOL(omap_enable_lcd_dma);
-
-void omap_setup_lcd_dma(void)
-{
-        BUG_ON(lcd_dma.active);
-        if (!enable_1510_mode) {
-                /* Set some reasonable defaults */
-                omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
-                omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
-                omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
-        }
-        set_b1_regs();
-        if (!enable_1510_mode) {
-                u16 w;
-
-                w = omap_readw(OMAP1610_DMA_LCD_CCR);
-                /*
-                 * If DMA was already active set the end_prog bit to have
-                 * the programmed register set loaded into the active
-                 * register set.
-                 */
-                w |= 1 << 11;           /* End_prog */
-                if (!lcd_dma.single_transfer)
-                        w |= (3 << 8);  /* Auto_init, repeat */
-                omap_writew(w, OMAP1610_DMA_LCD_CCR);
-        }
-}
-EXPORT_SYMBOL(omap_setup_lcd_dma);
-
-void omap_stop_lcd_dma(void)
-{
-        u16 w;
-
-        lcd_dma.active = 0;
-        if (enable_1510_mode || !lcd_dma.ext_ctrl)
-                return;
-
-        w = omap_readw(OMAP1610_DMA_LCD_CCR);
-        w &= ~(1 << 7);
-        omap_writew(w, OMAP1610_DMA_LCD_CCR);
-
-        w = omap_readw(OMAP1610_DMA_LCD_CTRL);
-        w &= ~(1 << 8);
-        omap_writew(w, OMAP1610_DMA_LCD_CTRL);
-}
-EXPORT_SYMBOL(omap_stop_lcd_dma);
 
 /*----------------------------------------------------------------------------*/
 
 static int __init omap_init_dma(void)
 {
+        unsigned long base;
         int ch, r;
 
         if (cpu_class_is_omap1()) {
-                omap_dma_base = OMAP1_IO_ADDRESS(OMAP1_DMA_BASE);
+                base = OMAP1_DMA_BASE;
                 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
         } else if (cpu_is_omap24xx()) {
-                omap_dma_base = OMAP2_IO_ADDRESS(OMAP24XX_DMA4_BASE);
+                base = OMAP24XX_DMA4_BASE;
                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
         } else if (cpu_is_omap34xx()) {
-                omap_dma_base = OMAP2_IO_ADDRESS(OMAP34XX_DMA4_BASE);
+                base = OMAP34XX_DMA4_BASE;
                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
         } else if (cpu_is_omap44xx()) {
-                omap_dma_base = OMAP2_IO_ADDRESS(OMAP44XX_DMA4_BASE);
+                base = OMAP44XX_DMA4_BASE;
                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
         } else {
                 pr_err("DMA init failed for unsupported omap\n");
                 return -ENODEV;
         }
 
+        omap_dma_base = ioremap(base, SZ_4K);
+        BUG_ON(!omap_dma_base);
+
         if (cpu_class_is_omap2() && omap_dma_reserve_channels
                         && (omap_dma_reserve_channels <= dma_lch_count))
                 dma_lch_count = omap_dma_reserve_channels;
 
         dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
                                 GFP_KERNEL);
-        if (!dma_chan)
-                return -ENOMEM;
+        if (!dma_chan) {
+                r = -ENOMEM;
+                goto out_unmap;
+        }
 
         if (cpu_class_is_omap2()) {
                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
                                                 dma_lch_count, GFP_KERNEL);
                 if (!dma_linked_lch) {
-                        kfree(dma_chan);
-                        return -ENOMEM;
+                        r = -ENOMEM;
+                        goto out_free;
                 }
         }
 
@@ -2420,14 +2093,6 @@ static int __init omap_init_dma(void)
                         dma_chan_count = 16;
                 } else
                         dma_chan_count = 9;
-                if (cpu_is_omap16xx()) {
-                        u16 w;
-
-                        /* this would prevent OMAP sleep */
-                        w = omap_readw(OMAP1610_DMA_LCD_CTRL);
-                        w &= ~(1 << 8);
-                        omap_writew(w, OMAP1610_DMA_LCD_CTRL);
-                }
         } else if (cpu_class_is_omap2()) {
                 u8 revision = dma_read(REVISION) & 0xff;
                 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
@@ -2438,7 +2103,6 @@ static int __init omap_init_dma(void)
                 return 0;
         }
 
-        spin_lock_init(&lcd_dma.lock);
         spin_lock_init(&dma_chan_lock);
 
         for (ch = 0; ch < dma_chan_count; ch++) {
@@ -2466,7 +2130,7 @@ static int __init omap_init_dma(void)
                                 for (i = 0; i < ch; i++)
                                         free_irq(omap1_dma_irq[i],
                                                  (void *) (i + 1));
-                                return r;
+                                goto out_free;
                         }
                 }
         }
@@ -2478,14 +2142,14 @@ static int __init omap_init_dma(void)
         if (cpu_class_is_omap2()) {
                 int irq;
                 if (cpu_is_omap44xx())
-                        irq = INT_44XX_SDMA_IRQ0;
+                        irq = OMAP44XX_IRQ_SDMA_0;
                 else
                         irq = INT_24XX_SDMA_IRQ0;
                 setup_irq(irq, &omap24xx_dma_irq);
         }
 
-        /* Enable smartidle idlemodes and autoidle */
-        if (cpu_is_omap34xx()) {
+        if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+                /* Enable smartidle idlemodes and autoidle */
                 u32 v = dma_read(OCP_SYSCONFIG);
                 v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
                                 DMA_SYSCONFIG_SIDLEMODE_MASK |
@@ -2494,25 +2158,25 @@ static int __init omap_init_dma(void)
                         DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
                         DMA_SYSCONFIG_AUTOIDLE);
                 dma_write(v , OCP_SYSCONFIG);
-        }
-
-
-        /* FIXME: Update LCD DMA to work on 24xx */
-        if (cpu_class_is_omap1()) {
-                r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
-                                "LCD DMA", NULL);
-                if (r != 0) {
-                        int i;
-
-                        printk(KERN_ERR "unable to request IRQ for LCD DMA "
-                               "(error %d)\n", r);
-                        for (i = 0; i < dma_chan_count; i++)
-                                free_irq(omap1_dma_irq[i], (void *) (i + 1));
-                        return r;
+                /* reserve dma channels 0 and 1 in high security devices */
+                if (cpu_is_omap34xx() &&
+                        (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
+                        printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
+                                        "HS ROM code\n");
+                        dma_chan[0].dev_id = 0;
+                        dma_chan[1].dev_id = 1;
                 }
         }
 
         return 0;
+
+out_free:
+        kfree(dma_chan);
+
+out_unmap:
+        iounmap(omap_dma_base);
+
+        return r;
 }
 
 arch_initcall(omap_init_dma);
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index d325b54daeb5..4d99dfbc8bef 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -38,7 +38,7 @@
 #include <linux/io.h>
 #include <linux/module.h>
 #include <mach/hardware.h>
-#include <mach/dmtimer.h>
+#include <plat/dmtimer.h>
 #include <mach/irqs.h>
 
 /* register offsets */
@@ -153,8 +153,7 @@
 struct omap_dm_timer {
         unsigned long phys_base;
         int irq;
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
-                        defined(CONFIG_ARCH_OMAP4)
+#ifdef CONFIG_ARCH_OMAP2PLUS
         struct clk *iclk, *fclk;
 #endif
         void __iomem *io_base;
@@ -163,20 +162,9 @@ struct omap_dm_timer {
         unsigned posted:1;
 };
 
-#ifdef CONFIG_ARCH_OMAP1
-
-#define omap_dm_clk_enable(x)
-#define omap_dm_clk_disable(x)
-#define omap2_dm_timers                 NULL
-#define omap2_dm_source_names           NULL
-#define omap2_dm_source_clocks          NULL
-#define omap3_dm_timers                 NULL
-#define omap3_dm_source_names           NULL
-#define omap3_dm_source_clocks          NULL
-#define omap4_dm_timers                 NULL
-#define omap4_dm_source_names           NULL
-#define omap4_dm_source_clocks          NULL
+static int dm_timer_count;
 
+#ifdef CONFIG_ARCH_OMAP1
 static struct omap_dm_timer omap1_dm_timers[] = {
         { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
         { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
@@ -188,20 +176,14 @@ static struct omap_dm_timer omap1_dm_timers[] = {
         { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 },
 };
 
-static const int dm_timer_count = ARRAY_SIZE(omap1_dm_timers);
+static const int omap1_dm_timer_count = ARRAY_SIZE(omap1_dm_timers);
 
-#elif defined(CONFIG_ARCH_OMAP2)
-
-#define omap_dm_clk_enable(x)           clk_enable(x)
-#define omap_dm_clk_disable(x)          clk_disable(x)
+#else
 #define omap1_dm_timers                 NULL
-#define omap3_dm_timers                 NULL
-#define omap3_dm_source_names           NULL
-#define omap3_dm_source_clocks          NULL
-#define omap4_dm_timers                 NULL
-#define omap4_dm_source_names           NULL
-#define omap4_dm_source_clocks          NULL
+#define omap1_dm_timer_count            0
+#endif  /* CONFIG_ARCH_OMAP1 */
 
+#ifdef CONFIG_ARCH_OMAP2
 static struct omap_dm_timer omap2_dm_timers[] = {
         { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
         { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
@@ -225,20 +207,16 @@ static const char *omap2_dm_source_names[] __initdata = {
 };
 
 static struct clk *omap2_dm_source_clocks[3];
-static const int dm_timer_count = ARRAY_SIZE(omap2_dm_timers);
-
-#elif defined(CONFIG_ARCH_OMAP3)
+static const int omap2_dm_timer_count = ARRAY_SIZE(omap2_dm_timers);
 
-#define omap_dm_clk_enable(x)           clk_enable(x)
-#define omap_dm_clk_disable(x)          clk_disable(x)
-#define omap1_dm_timers                 NULL
+#else
 #define omap2_dm_timers                 NULL
+#define omap2_dm_timer_count            0
 #define omap2_dm_source_names           NULL
 #define omap2_dm_source_clocks          NULL
-#define omap4_dm_timers                 NULL
-#define omap4_dm_source_names           NULL
-#define omap4_dm_source_clocks          NULL
+#endif  /* CONFIG_ARCH_OMAP2 */
 
+#ifdef CONFIG_ARCH_OMAP3
 static struct omap_dm_timer omap3_dm_timers[] = {
         { .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 },
         { .phys_base = 0x49032000, .irq = INT_24XX_GPTIMER2 },
@@ -261,33 +239,29 @@ static const char *omap3_dm_source_names[] __initdata = {
 };
 
 static struct clk *omap3_dm_source_clocks[2];
-static const int dm_timer_count = ARRAY_SIZE(omap3_dm_timers);
-
-#elif defined(CONFIG_ARCH_OMAP4)
+static const int omap3_dm_timer_count = ARRAY_SIZE(omap3_dm_timers);
 
-#define omap_dm_clk_enable(x)           clk_enable(x)
-#define omap_dm_clk_disable(x)          clk_disable(x)
-#define omap1_dm_timers                 NULL
-#define omap2_dm_timers                 NULL
-#define omap2_dm_source_names           NULL
-#define omap2_dm_source_clocks          NULL
+#else
 #define omap3_dm_timers                 NULL
+#define omap3_dm_timer_count            0
 #define omap3_dm_source_names           NULL
 #define omap3_dm_source_clocks          NULL
+#endif  /* CONFIG_ARCH_OMAP3 */
 
+#ifdef CONFIG_ARCH_OMAP4
 static struct omap_dm_timer omap4_dm_timers[] = {
-        { .phys_base = 0x4a318000, .irq = INT_44XX_GPTIMER1 },
-        { .phys_base = 0x48032000, .irq = INT_44XX_GPTIMER2 },
-        { .phys_base = 0x48034000, .irq = INT_44XX_GPTIMER3 },
-        { .phys_base = 0x48036000, .irq = INT_44XX_GPTIMER4 },
-        { .phys_base = 0x40138000, .irq = INT_44XX_GPTIMER5 },
-        { .phys_base = 0x4013a000, .irq = INT_44XX_GPTIMER6 },
-        { .phys_base = 0x4013a000, .irq = INT_44XX_GPTIMER7 },
-        { .phys_base = 0x4013e000, .irq = INT_44XX_GPTIMER8 },
-        { .phys_base = 0x4803e000, .irq = INT_44XX_GPTIMER9 },
-        { .phys_base = 0x48086000, .irq = INT_44XX_GPTIMER10 },
-        { .phys_base = 0x48088000, .irq = INT_44XX_GPTIMER11 },
-        { .phys_base = 0x4a320000, .irq = INT_44XX_GPTIMER12 },
+        { .phys_base = 0x4a318000, .irq = OMAP44XX_IRQ_GPT1 },
+        { .phys_base = 0x48032000, .irq = OMAP44XX_IRQ_GPT2 },
+        { .phys_base = 0x48034000, .irq = OMAP44XX_IRQ_GPT3 },
+        { .phys_base = 0x48036000, .irq = OMAP44XX_IRQ_GPT4 },
+        { .phys_base = 0x40138000, .irq = OMAP44XX_IRQ_GPT5 },
+        { .phys_base = 0x4013a000, .irq = OMAP44XX_IRQ_GPT6 },
+        { .phys_base = 0x4013a000, .irq = OMAP44XX_IRQ_GPT7 },
+        { .phys_base = 0x4013e000, .irq = OMAP44XX_IRQ_GPT8 },
+        { .phys_base = 0x4803e000, .irq = OMAP44XX_IRQ_GPT9 },
+        { .phys_base = 0x48086000, .irq = OMAP44XX_IRQ_GPT10 },
+        { .phys_base = 0x48088000, .irq = OMAP44XX_IRQ_GPT11 },
+        { .phys_base = 0x4a320000, .irq = OMAP44XX_IRQ_GPT12 },
 };
 static const char *omap4_dm_source_names[] __initdata = {
         "sys_ck",
@@ -295,13 +269,14 @@ static const char *omap4_dm_source_names[] __initdata = {
         NULL
 };
 static struct clk *omap4_dm_source_clocks[2];
-static const int dm_timer_count = ARRAY_SIZE(omap4_dm_timers);
+static const int omap4_dm_timer_count = ARRAY_SIZE(omap4_dm_timers);
 
 #else
-
-#error OMAP architecture not supported!
-
-#endif
+#define omap4_dm_timers                 NULL
+#define omap4_dm_timer_count            0
+#define omap4_dm_source_names           NULL
+#define omap4_dm_source_clocks          NULL
+#endif  /* CONFIG_ARCH_OMAP4 */
 
 static struct omap_dm_timer *dm_timers;
 static const char **dm_source_names;
@@ -450,8 +425,12 @@ void omap_dm_timer_enable(struct omap_dm_timer *timer)
         if (timer->enabled)
                 return;
 
-        omap_dm_clk_enable(timer->fclk);
-        omap_dm_clk_enable(timer->iclk);
+#ifdef CONFIG_ARCH_OMAP2PLUS
+        if (cpu_class_is_omap2()) {
+                clk_enable(timer->fclk);
+                clk_enable(timer->iclk);
+        }
+#endif
 
         timer->enabled = 1;
 }
@@ -462,8 +441,12 @@ void omap_dm_timer_disable(struct omap_dm_timer *timer)
         if (!timer->enabled)
                 return;
 
-        omap_dm_clk_disable(timer->iclk);
-        omap_dm_clk_disable(timer->fclk);
+#ifdef CONFIG_ARCH_OMAP2PLUS
+        if (cpu_class_is_omap2()) {
+                clk_disable(timer->iclk);
+                clk_disable(timer->fclk);
+        }
+#endif
 
         timer->enabled = 0;
 }
@@ -506,8 +489,7 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
 
-#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
-                                defined(CONFIG_ARCH_OMAP4)
+#else
 
 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
 {
@@ -551,6 +533,18 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer)
         if (l & OMAP_TIMER_CTRL_ST) {
                 l &= ~0x1;
                 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
+#ifdef CONFIG_ARCH_OMAP2PLUS
+                /* Readback to make sure write has completed */
+                omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
+                 /*
+                  * Wait for functional clock period x 3.5 to make sure that
+                  * timer is stopped
+                  */
+                udelay(3500000 / clk_get_rate(timer->fclk) + 1);
+                /* Ack possibly pending interrupt */
+                omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG,
+                                OMAP_TIMER_INT_OVERFLOW);
+#endif
         }
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
@@ -742,25 +736,30 @@ EXPORT_SYMBOL_GPL(omap_dm_timers_active);
 int __init omap_dm_timer_init(void)
 {
         struct omap_dm_timer *timer;
-        int i;
+        int i, map_size = SZ_8K;        /* Module 4KB + L4 4KB except on omap1 */
 
         if (!(cpu_is_omap16xx() || cpu_class_is_omap2()))
                 return -ENODEV;
 
         spin_lock_init(&dm_timer_lock);
 
-        if (cpu_class_is_omap1())
+        if (cpu_class_is_omap1()) {
                 dm_timers = omap1_dm_timers;
-        else if (cpu_is_omap24xx()) {
+                dm_timer_count = omap1_dm_timer_count;
+                map_size = SZ_2K;
+        } else if (cpu_is_omap24xx()) {
                 dm_timers = omap2_dm_timers;
+                dm_timer_count = omap2_dm_timer_count;
                 dm_source_names = omap2_dm_source_names;
                 dm_source_clocks = omap2_dm_source_clocks;
         } else if (cpu_is_omap34xx()) {
                 dm_timers = omap3_dm_timers;
+                dm_timer_count = omap3_dm_timer_count;
                 dm_source_names = omap3_dm_source_names;
                 dm_source_clocks = omap3_dm_source_clocks;
         } else if (cpu_is_omap44xx()) {
                 dm_timers = omap4_dm_timers;
+                dm_timer_count = omap4_dm_timer_count;
                 dm_source_names = omap4_dm_source_names;
                 dm_source_clocks = omap4_dm_source_clocks;
         }
@@ -774,12 +773,12 @@ int __init omap_dm_timer_init(void)
 
         for (i = 0; i < dm_timer_count; i++) {
                 timer = &dm_timers[i];
-                if (cpu_class_is_omap1())
-                        timer->io_base = OMAP1_IO_ADDRESS(timer->phys_base);
-                else
-                        timer->io_base = OMAP2_IO_ADDRESS(timer->phys_base);
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
-                                        defined(CONFIG_ARCH_OMAP4)
+
+                /* Static mapping, never released */
+                timer->io_base = ioremap(timer->phys_base, map_size);
+                BUG_ON(!timer->io_base);
+
+#ifdef CONFIG_ARCH_OMAP2PLUS
                 if (cpu_class_is_omap2()) {
                         char clk_name[16];
                         sprintf(clk_name, "gpt%d_ick", i + 1);
diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
index 3746222bed10..d3eea4f47533 100644
--- a/arch/arm/plat-omap/fb.c
+++ b/arch/arm/plat-omap/fb.c
@@ -28,13 +28,13 @@
 #include <linux/platform_device.h>
 #include <linux/bootmem.h>
 #include <linux/io.h>
+#include <linux/omapfb.h>
 
 #include <mach/hardware.h>
 #include <asm/mach/map.h>
 
-#include <mach/board.h>
-#include <mach/sram.h>
-#include <mach/omapfb.h>
+#include <plat/board.h>
+#include <plat/sram.h>
 
 #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
 
@@ -55,6 +55,10 @@ static struct platform_device omap_fb_device = {
         .num_resources = 0,
 };
 
+void omapfb_set_platform_data(struct omapfb_platform_data *data)
+{
+}
+
 static inline int ranges_overlap(unsigned long start1, unsigned long size1,
                                  unsigned long start2, unsigned long size2)
 {
@@ -327,7 +331,33 @@ static inline int omap_init_fb(void)
 
 arch_initcall(omap_init_fb);
 
-#else
+#elif defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
+
+static u64 omap_fb_dma_mask = ~(u32)0;
+static struct omapfb_platform_data omapfb_config;
+
+static struct platform_device omap_fb_device = {
+        .name           = "omapfb",
+        .id             = -1,
+        .dev = {
+                .dma_mask               = &omap_fb_dma_mask,
+                .coherent_dma_mask      = ~(u32)0,
+                .platform_data          = &omapfb_config,
+        },
+        .num_resources = 0,
+};
+
+void omapfb_set_platform_data(struct omapfb_platform_data *data)
+{
+        omapfb_config = *data;
+}
+
+static inline int omap_init_fb(void)
+{
+        return platform_device_register(&omap_fb_device);
+}
+
+arch_initcall(omap_init_fb);
 
 void omapfb_reserve_sdram(void) {}
 unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
@@ -339,5 +369,20 @@ unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
         return 0;
 }
 
+#else
+
+void omapfb_set_platform_data(struct omapfb_platform_data *data)
+{
+}
+
+void omapfb_reserve_sdram(void) {}
+unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
+                                  unsigned long sram_vstart,
+                                  unsigned long sram_size,
+                                  unsigned long start_avail,
+                                  unsigned long size_avail)
+{
+        return 0;
+}
 
 #endif
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 7c345b757df1..45a225d09125 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -31,7 +31,7 @@
 /*
  * OMAP1510 GPIO registers
  */
-#define OMAP1510_GPIO_BASE              OMAP1_IO_ADDRESS(0xfffce000)
+#define OMAP1510_GPIO_BASE              0xfffce000
 #define OMAP1510_GPIO_DATA_INPUT        0x00
 #define OMAP1510_GPIO_DATA_OUTPUT       0x04
 #define OMAP1510_GPIO_DIR_CONTROL       0x08
@@ -45,10 +45,10 @@
 /*
  * OMAP1610 specific GPIO registers
  */
-#define OMAP1610_GPIO1_BASE             OMAP1_IO_ADDRESS(0xfffbe400)
-#define OMAP1610_GPIO2_BASE             OMAP1_IO_ADDRESS(0xfffbec00)
-#define OMAP1610_GPIO3_BASE             OMAP1_IO_ADDRESS(0xfffbb400)
-#define OMAP1610_GPIO4_BASE             OMAP1_IO_ADDRESS(0xfffbbc00)
+#define OMAP1610_GPIO1_BASE             0xfffbe400
+#define OMAP1610_GPIO2_BASE             0xfffbec00
+#define OMAP1610_GPIO3_BASE             0xfffbb400
+#define OMAP1610_GPIO4_BASE             0xfffbbc00
 #define OMAP1610_GPIO_REVISION          0x0000
 #define OMAP1610_GPIO_SYSCONFIG         0x0010
 #define OMAP1610_GPIO_SYSSTATUS         0x0014
@@ -68,52 +68,36 @@
 #define OMAP1610_GPIO_SET_DATAOUT       0x00f0
 
 /*
- * OMAP730 specific GPIO registers
+ * OMAP7XX specific GPIO registers
  */
-#define OMAP730_GPIO1_BASE              OMAP1_IO_ADDRESS(0xfffbc000)
-#define OMAP730_GPIO2_BASE              OMAP1_IO_ADDRESS(0xfffbc800)
-#define OMAP730_GPIO3_BASE              OMAP1_IO_ADDRESS(0xfffbd000)
-#define OMAP730_GPIO4_BASE              OMAP1_IO_ADDRESS(0xfffbd800)
-#define OMAP730_GPIO5_BASE              OMAP1_IO_ADDRESS(0xfffbe000)
-#define OMAP730_GPIO6_BASE              OMAP1_IO_ADDRESS(0xfffbe800)
-#define OMAP730_GPIO_DATA_INPUT         0x00
-#define OMAP730_GPIO_DATA_OUTPUT        0x04
-#define OMAP730_GPIO_DIR_CONTROL        0x08
-#define OMAP730_GPIO_INT_CONTROL        0x0c
-#define OMAP730_GPIO_INT_MASK           0x10
-#define OMAP730_GPIO_INT_STATUS         0x14
-
-/*
- * OMAP850 specific GPIO registers
- */
-#define OMAP850_GPIO1_BASE              OMAP1_IO_ADDRESS(0xfffbc000)
-#define OMAP850_GPIO2_BASE              OMAP1_IO_ADDRESS(0xfffbc800)
-#define OMAP850_GPIO3_BASE              OMAP1_IO_ADDRESS(0xfffbd000)
-#define OMAP850_GPIO4_BASE              OMAP1_IO_ADDRESS(0xfffbd800)
-#define OMAP850_GPIO5_BASE              OMAP1_IO_ADDRESS(0xfffbe000)
-#define OMAP850_GPIO6_BASE              OMAP1_IO_ADDRESS(0xfffbe800)
-#define OMAP850_GPIO_DATA_INPUT         0x00
-#define OMAP850_GPIO_DATA_OUTPUT        0x04
-#define OMAP850_GPIO_DIR_CONTROL        0x08
-#define OMAP850_GPIO_INT_CONTROL        0x0c
-#define OMAP850_GPIO_INT_MASK           0x10
-#define OMAP850_GPIO_INT_STATUS         0x14
-
-#define OMAP1_MPUIO_VBASE               OMAP1_IO_ADDRESS(OMAP1_MPUIO_BASE)
+#define OMAP7XX_GPIO1_BASE              0xfffbc000
+#define OMAP7XX_GPIO2_BASE              0xfffbc800
+#define OMAP7XX_GPIO3_BASE              0xfffbd000
+#define OMAP7XX_GPIO4_BASE              0xfffbd800
+#define OMAP7XX_GPIO5_BASE              0xfffbe000
+#define OMAP7XX_GPIO6_BASE              0xfffbe800
+#define OMAP7XX_GPIO_DATA_INPUT         0x00
+#define OMAP7XX_GPIO_DATA_OUTPUT        0x04
+#define OMAP7XX_GPIO_DIR_CONTROL        0x08
+#define OMAP7XX_GPIO_INT_CONTROL        0x0c
+#define OMAP7XX_GPIO_INT_MASK           0x10
+#define OMAP7XX_GPIO_INT_STATUS         0x14
+
+#define OMAP1_MPUIO_VBASE               OMAP1_MPUIO_BASE
 
 /*
  * omap24xx specific GPIO registers
  */
-#define OMAP242X_GPIO1_BASE             OMAP2_IO_ADDRESS(0x48018000)
-#define OMAP242X_GPIO2_BASE             OMAP2_IO_ADDRESS(0x4801a000)
-#define OMAP242X_GPIO3_BASE             OMAP2_IO_ADDRESS(0x4801c000)
-#define OMAP242X_GPIO4_BASE             OMAP2_IO_ADDRESS(0x4801e000)
+#define OMAP242X_GPIO1_BASE             0x48018000
+#define OMAP242X_GPIO2_BASE             0x4801a000
+#define OMAP242X_GPIO3_BASE             0x4801c000
+#define OMAP242X_GPIO4_BASE             0x4801e000
 
-#define OMAP243X_GPIO1_BASE             OMAP2_IO_ADDRESS(0x4900C000)
-#define OMAP243X_GPIO2_BASE             OMAP2_IO_ADDRESS(0x4900E000)
-#define OMAP243X_GPIO3_BASE             OMAP2_IO_ADDRESS(0x49010000)
-#define OMAP243X_GPIO4_BASE             OMAP2_IO_ADDRESS(0x49012000)
-#define OMAP243X_GPIO5_BASE             OMAP2_IO_ADDRESS(0x480B6000)
+#define OMAP243X_GPIO1_BASE             0x4900C000
+#define OMAP243X_GPIO2_BASE             0x4900E000
+#define OMAP243X_GPIO3_BASE             0x49010000
+#define OMAP243X_GPIO4_BASE             0x49012000
+#define OMAP243X_GPIO5_BASE             0x480B6000
 
 #define OMAP24XX_GPIO_REVISION          0x0000
 #define OMAP24XX_GPIO_SYSCONFIG         0x0010
@@ -170,35 +154,34 @@
  * omap34xx specific GPIO registers
  */
 
-#define OMAP34XX_GPIO1_BASE             OMAP2_IO_ADDRESS(0x48310000)
-#define OMAP34XX_GPIO2_BASE             OMAP2_IO_ADDRESS(0x49050000)
-#define OMAP34XX_GPIO3_BASE             OMAP2_IO_ADDRESS(0x49052000)
-#define OMAP34XX_GPIO4_BASE             OMAP2_IO_ADDRESS(0x49054000)
-#define OMAP34XX_GPIO5_BASE             OMAP2_IO_ADDRESS(0x49056000)
-#define OMAP34XX_GPIO6_BASE             OMAP2_IO_ADDRESS(0x49058000)
+#define OMAP34XX_GPIO1_BASE             0x48310000
+#define OMAP34XX_GPIO2_BASE             0x49050000
+#define OMAP34XX_GPIO3_BASE             0x49052000
+#define OMAP34XX_GPIO4_BASE             0x49054000
+#define OMAP34XX_GPIO5_BASE             0x49056000
+#define OMAP34XX_GPIO6_BASE             0x49058000
 
 /*
  * OMAP44XX  specific GPIO registers
  */
-#define OMAP44XX_GPIO1_BASE             OMAP2_IO_ADDRESS(0x4a310000)
-#define OMAP44XX_GPIO2_BASE             OMAP2_IO_ADDRESS(0x48055000)
-#define OMAP44XX_GPIO3_BASE             OMAP2_IO_ADDRESS(0x48057000)
-#define OMAP44XX_GPIO4_BASE             OMAP2_IO_ADDRESS(0x48059000)
-#define OMAP44XX_GPIO5_BASE             OMAP2_IO_ADDRESS(0x4805B000)
-#define OMAP44XX_GPIO6_BASE             OMAP2_IO_ADDRESS(0x4805D000)
+#define OMAP44XX_GPIO1_BASE             0x4a310000
+#define OMAP44XX_GPIO2_BASE             0x48055000
+#define OMAP44XX_GPIO3_BASE             0x48057000
+#define OMAP44XX_GPIO4_BASE             0x48059000
+#define OMAP44XX_GPIO5_BASE             0x4805B000
+#define OMAP44XX_GPIO6_BASE             0x4805D000
 
 struct gpio_bank {
+        unsigned long pbase;
         void __iomem *base;
         u16 irq;
         u16 virtual_irq_start;
         int method;
-#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) ||  \
-                defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
         u32 suspend_wakeup;
         u32 saved_wakeup;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                        defined(CONFIG_ARCH_OMAP4)
+#ifdef CONFIG_ARCH_OMAP2PLUS
         u32 non_wakeup_gpios;
         u32 enabled_non_wakeup_gpios;
 
@@ -207,107 +190,142 @@ struct gpio_bank {
         u32 saved_risingdetect;
 #endif
         u32 level_mask;
+        u32 toggle_mask;
         spinlock_t lock;
         struct gpio_chip chip;
         struct clk *dbck;
+        u32 mod_usage;
 };
 
 #define METHOD_MPUIO            0
 #define METHOD_GPIO_1510        1
 #define METHOD_GPIO_1610        2
-#define METHOD_GPIO_730         3
-#define METHOD_GPIO_850         4
+#define METHOD_GPIO_7XX         3
 #define METHOD_GPIO_24XX        5
+#define METHOD_GPIO_44XX        6
 
 #ifdef CONFIG_ARCH_OMAP16XX
 static struct gpio_bank gpio_bank_1610[5] = {
-        { OMAP1_MPUIO_VBASE,    INT_MPUIO,          IH_MPUIO_BASE,     METHOD_MPUIO},
-        { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1,      IH_GPIO_BASE,      METHOD_GPIO_1610 },
-        { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
-        { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
-        { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
+        { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
+                METHOD_MPUIO },
+        { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
+                METHOD_GPIO_1610 },
+        { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16,
+                METHOD_GPIO_1610 },
+        { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32,
+                METHOD_GPIO_1610 },
+        { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48,
+                METHOD_GPIO_1610 },
 };
 #endif
 
 #ifdef CONFIG_ARCH_OMAP15XX
 static struct gpio_bank gpio_bank_1510[2] = {
-        { OMAP1_MPUIO_VBASE,   INT_MPUIO,      IH_MPUIO_BASE, METHOD_MPUIO },
-        { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE,  METHOD_GPIO_1510 }
-};
-#endif
-
-#ifdef CONFIG_ARCH_OMAP730
-static struct gpio_bank gpio_bank_730[7] = {
-        { OMAP1_MPUIO_VBASE,    INT_730_MPUIO,      IH_MPUIO_BASE,      METHOD_MPUIO },
-        { OMAP730_GPIO1_BASE,  INT_730_GPIO_BANK1,  IH_GPIO_BASE,       METHOD_GPIO_730 },
-        { OMAP730_GPIO2_BASE,  INT_730_GPIO_BANK2,  IH_GPIO_BASE + 32,  METHOD_GPIO_730 },
-        { OMAP730_GPIO3_BASE,  INT_730_GPIO_BANK3,  IH_GPIO_BASE + 64,  METHOD_GPIO_730 },
-        { OMAP730_GPIO4_BASE,  INT_730_GPIO_BANK4,  IH_GPIO_BASE + 96,  METHOD_GPIO_730 },
-        { OMAP730_GPIO5_BASE,  INT_730_GPIO_BANK5,  IH_GPIO_BASE + 128, METHOD_GPIO_730 },
-        { OMAP730_GPIO6_BASE,  INT_730_GPIO_BANK6,  IH_GPIO_BASE + 160, METHOD_GPIO_730 },
+        { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
+                METHOD_MPUIO },
+        { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
+                METHOD_GPIO_1510 }
 };
 #endif
 
-#ifdef CONFIG_ARCH_OMAP850
-static struct gpio_bank gpio_bank_850[7] = {
-        { OMAP1_MPUIO_VBASE,     INT_850_MPUIO,     IH_MPUIO_BASE,      METHOD_MPUIO },
-        { OMAP850_GPIO1_BASE,  INT_850_GPIO_BANK1,  IH_GPIO_BASE,       METHOD_GPIO_850 },
-        { OMAP850_GPIO2_BASE,  INT_850_GPIO_BANK2,  IH_GPIO_BASE + 32,  METHOD_GPIO_850 },
-        { OMAP850_GPIO3_BASE,  INT_850_GPIO_BANK3,  IH_GPIO_BASE + 64,  METHOD_GPIO_850 },
-        { OMAP850_GPIO4_BASE,  INT_850_GPIO_BANK4,  IH_GPIO_BASE + 96,  METHOD_GPIO_850 },
-        { OMAP850_GPIO5_BASE,  INT_850_GPIO_BANK5,  IH_GPIO_BASE + 128, METHOD_GPIO_850 },
-        { OMAP850_GPIO6_BASE,  INT_850_GPIO_BANK6,  IH_GPIO_BASE + 160, METHOD_GPIO_850 },
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+static struct gpio_bank gpio_bank_7xx[7] = {
+        { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE,
+                METHOD_MPUIO },
+        { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE,
+                METHOD_GPIO_7XX },
+        { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32,
+                METHOD_GPIO_7XX },
+        { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64,
+                METHOD_GPIO_7XX },
+        { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4,  IH_GPIO_BASE + 96,
+                METHOD_GPIO_7XX },
+        { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5,  IH_GPIO_BASE + 128,
+                METHOD_GPIO_7XX },
+        { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6,  IH_GPIO_BASE + 160,
+                METHOD_GPIO_7XX },
 };
 #endif
 
-
-#ifdef CONFIG_ARCH_OMAP24XX
+#ifdef CONFIG_ARCH_OMAP2
 
 static struct gpio_bank gpio_bank_242x[4] = {
-        { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,       METHOD_GPIO_24XX },
-        { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,  METHOD_GPIO_24XX },
-        { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,  METHOD_GPIO_24XX },
-        { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,  METHOD_GPIO_24XX },
+        { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
+                METHOD_GPIO_24XX },
+        { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
+                METHOD_GPIO_24XX },
+        { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
+                METHOD_GPIO_24XX },
+        { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
+                METHOD_GPIO_24XX },
 };
 
 static struct gpio_bank gpio_bank_243x[5] = {
-        { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,       METHOD_GPIO_24XX },
-        { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,  METHOD_GPIO_24XX },
-        { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,  METHOD_GPIO_24XX },
-        { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,  METHOD_GPIO_24XX },
-        { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
+        { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
+                METHOD_GPIO_24XX },
+        { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
+                METHOD_GPIO_24XX },
+        { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
+                METHOD_GPIO_24XX },
+        { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
+                METHOD_GPIO_24XX },
+        { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128,
+                METHOD_GPIO_24XX },
 };
 
 #endif
 
-#ifdef CONFIG_ARCH_OMAP34XX
+#ifdef CONFIG_ARCH_OMAP3
 static struct gpio_bank gpio_bank_34xx[6] = {
-        { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,       METHOD_GPIO_24XX },
-        { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,  METHOD_GPIO_24XX },
-        { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,  METHOD_GPIO_24XX },
-        { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,  METHOD_GPIO_24XX },
-        { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
-        { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
-};
-
-#endif
-
-#ifdef CONFIG_ARCH_OMAP4
-static struct gpio_bank gpio_bank_44xx[6] = {
-        { OMAP44XX_GPIO1_BASE, INT_44XX_GPIO_BANK1, IH_GPIO_BASE,       \
+        { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,
                 METHOD_GPIO_24XX },
-        { OMAP44XX_GPIO2_BASE, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32,  \
+        { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,
                 METHOD_GPIO_24XX },
-        { OMAP44XX_GPIO3_BASE, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64,  \
+        { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,
                 METHOD_GPIO_24XX },
-        { OMAP44XX_GPIO4_BASE, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96,  \
+        { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,
                 METHOD_GPIO_24XX },
-        { OMAP44XX_GPIO5_BASE, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128, \
+        { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128,
                 METHOD_GPIO_24XX },
-        { OMAP44XX_GPIO6_BASE, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160, \
+        { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
                 METHOD_GPIO_24XX },
 };
 
+struct omap3_gpio_regs {
+        u32 sysconfig;
+        u32 irqenable1;
+        u32 irqenable2;
+        u32 wake_en;
+        u32 ctrl;
+        u32 oe;
+        u32 leveldetect0;
+        u32 leveldetect1;
+        u32 risingdetect;
+        u32 fallingdetect;
+        u32 dataout;
+        u32 setwkuena;
+        u32 setdataout;
+};
+
+static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
+#endif
+
+#ifdef CONFIG_ARCH_OMAP4
+static struct gpio_bank gpio_bank_44xx[6] = {
+        { OMAP44XX_GPIO1_BASE, NULL, OMAP44XX_IRQ_GPIO1, IH_GPIO_BASE,
+                METHOD_GPIO_44XX },
+        { OMAP44XX_GPIO2_BASE, NULL, OMAP44XX_IRQ_GPIO2, IH_GPIO_BASE + 32,
+                METHOD_GPIO_44XX },
+        { OMAP44XX_GPIO3_BASE, NULL, OMAP44XX_IRQ_GPIO3, IH_GPIO_BASE + 64,
+                METHOD_GPIO_44XX },
+        { OMAP44XX_GPIO4_BASE, NULL, OMAP44XX_IRQ_GPIO4, IH_GPIO_BASE + 96,
+                METHOD_GPIO_44XX },
+        { OMAP44XX_GPIO5_BASE, NULL, OMAP44XX_IRQ_GPIO5, IH_GPIO_BASE + 128,
+                METHOD_GPIO_44XX },
+        { OMAP44XX_GPIO6_BASE, NULL, OMAP44XX_IRQ_GPIO6, IH_GPIO_BASE + 160,
+                METHOD_GPIO_44XX },
+};
+
 #endif
 
 static struct gpio_bank *gpio_bank;
@@ -402,23 +420,18 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
                 reg += OMAP1610_GPIO_DIRECTION;
                 break;
 #endif
-#ifdef CONFIG_ARCH_OMAP730
-        case METHOD_GPIO_730:
-                reg += OMAP730_GPIO_DIR_CONTROL;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP850
-        case METHOD_GPIO_850:
-                reg += OMAP850_GPIO_DIR_CONTROL;
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+        case METHOD_GPIO_7XX:
+                reg += OMAP7XX_GPIO_DIR_CONTROL;
                 break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
         case METHOD_GPIO_24XX:
                 reg += OMAP24XX_GPIO_OE;
                 break;
 #endif
 #if defined(CONFIG_ARCH_OMAP4)
-        case METHOD_GPIO_24XX:
+        case METHOD_GPIO_44XX:
                 reg += OMAP4_GPIO_OE;
                 break;
 #endif
@@ -469,9 +482,9 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
                 l = 1 << gpio;
                 break;
 #endif
-#ifdef CONFIG_ARCH_OMAP730
-        case METHOD_GPIO_730:
-                reg += OMAP730_GPIO_DATA_OUTPUT;
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+        case METHOD_GPIO_7XX:
+                reg += OMAP7XX_GPIO_DATA_OUTPUT;
                 l = __raw_readl(reg);
                 if (enable)
                         l |= 1 << gpio;
@@ -479,17 +492,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
                         l &= ~(1 << gpio);
                 break;
 #endif
-#ifdef CONFIG_ARCH_OMAP850
-        case METHOD_GPIO_850:
-                reg += OMAP850_GPIO_DATA_OUTPUT;
-                l = __raw_readl(reg);
-                if (enable)
-                        l |= 1 << gpio;
-                else
-                        l &= ~(1 << gpio);
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
         case METHOD_GPIO_24XX:
                 if (enable)
                         reg += OMAP24XX_GPIO_SETDATAOUT;
@@ -499,7 +502,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
                 break;
 #endif
 #ifdef CONFIG_ARCH_OMAP4
-        case METHOD_GPIO_24XX:
+        case METHOD_GPIO_44XX:
                 if (enable)
                         reg += OMAP4_GPIO_SETDATAOUT;
                 else
@@ -537,23 +540,18 @@ static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
                 reg += OMAP1610_GPIO_DATAIN;
                 break;
 #endif
-#ifdef CONFIG_ARCH_OMAP730
-        case METHOD_GPIO_730:
-                reg += OMAP730_GPIO_DATA_INPUT;
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+        case METHOD_GPIO_7XX:
+                reg += OMAP7XX_GPIO_DATA_INPUT;
                 break;
 #endif
-#ifdef CONFIG_ARCH_OMAP850
-        case METHOD_GPIO_850:
-                reg += OMAP850_GPIO_DATA_INPUT;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
         case METHOD_GPIO_24XX:
                 reg += OMAP24XX_GPIO_DATAIN;
                 break;
 #endif
 #ifdef CONFIG_ARCH_OMAP4
-        case METHOD_GPIO_24XX:
+        case METHOD_GPIO_44XX:
                 reg += OMAP4_GPIO_DATAIN;
                 break;
 #endif
@@ -588,19 +586,14 @@ static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
                 reg += OMAP1610_GPIO_DATAOUT;
                 break;
 #endif
-#ifdef CONFIG_ARCH_OMAP730
-        case METHOD_GPIO_730:
-                reg += OMAP730_GPIO_DATA_OUTPUT;
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+        case METHOD_GPIO_7XX:
+                reg += OMAP7XX_GPIO_DATA_OUTPUT;
                 break;
 #endif
-#ifdef CONFIG_ARCH_OMAP850
-        case METHOD_GPIO_850:
-                reg += OMAP850_GPIO_DATA_OUTPUT;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                defined(CONFIG_ARCH_OMAP4)
+#ifdef CONFIG_ARCH_OMAP2PLUS
         case METHOD_GPIO_24XX:
+        case METHOD_GPIO_44XX:
                 reg += OMAP24XX_GPIO_DATAOUT;
                 break;
 #endif
@@ -631,11 +624,16 @@ void omap_set_gpio_debounce(int gpio, int enable)
 
         bank = get_gpio_bank(gpio);
         reg = bank->base;
-#ifdef CONFIG_ARCH_OMAP4
-        reg += OMAP4_GPIO_DEBOUNCENABLE;
-#else
-        reg += OMAP24XX_GPIO_DEBOUNCE_EN;
-#endif
+
+        if (cpu_is_omap44xx())
+                reg += OMAP4_GPIO_DEBOUNCENABLE;
+        else
+                reg += OMAP24XX_GPIO_DEBOUNCE_EN;
+
+        if (!(bank->mod_usage & l)) {
+                printk(KERN_ERR "GPIO %d not requested\n", gpio);
+                return;
+        }
 
         spin_lock_irqsave(&bank->lock, flags);
         val = __raw_readl(reg);
@@ -671,18 +669,23 @@ void omap_set_gpio_debounce_time(int gpio, int enc_time)
         bank = get_gpio_bank(gpio);
         reg = bank->base;
 
+        if (!bank->mod_usage) {
+                printk(KERN_ERR "GPIO not requested\n");
+                return;
+        }
+
         enc_time &= 0xff;
-#ifdef CONFIG_ARCH_OMAP4
-        reg += OMAP4_GPIO_DEBOUNCINGTIME;
-#else
-        reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
-#endif
+
+        if (cpu_is_omap44xx())
+                reg += OMAP4_GPIO_DEBOUNCINGTIME;
+        else
+                reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
+
         __raw_writel(enc_time, reg);
 }
 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
 
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                                defined(CONFIG_ARCH_OMAP4)
+#ifdef CONFIG_ARCH_OMAP2PLUS
 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
                                                 int trigger)
 {
@@ -747,6 +750,44 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
 }
 #endif
 
+#ifdef CONFIG_ARCH_OMAP1
+/*
+ * This only applies to chips that can't do both rising and falling edge
+ * detection at once.  For all other chips, this function is a noop.
+ */
+static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
+{
+        void __iomem *reg = bank->base;
+        u32 l = 0;
+
+        switch (bank->method) {
+        case METHOD_MPUIO:
+                reg += OMAP_MPUIO_GPIO_INT_EDGE;
+                break;
+#ifdef CONFIG_ARCH_OMAP15XX
+        case METHOD_GPIO_1510:
+                reg += OMAP1510_GPIO_INT_CONTROL;
+                break;
+#endif
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+        case METHOD_GPIO_7XX:
+                reg += OMAP7XX_GPIO_INT_CONTROL;
+                break;
+#endif
+        default:
+                return;
+        }
+
+        l = __raw_readl(reg);
+        if ((l >> gpio) & 1)
+                l &= ~(1 << gpio);
+        else
+                l |= 1 << gpio;
+
+        __raw_writel(l, reg);
+}
+#endif
+
 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
 {
         void __iomem *reg = bank->base;
@@ -757,6 +798,8 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
         case METHOD_MPUIO:
                 reg += OMAP_MPUIO_GPIO_INT_EDGE;
                 l = __raw_readl(reg);
+                if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
+                        bank->toggle_mask |= 1 << gpio;
                 if (trigger & IRQ_TYPE_EDGE_RISING)
                         l |= 1 << gpio;
                 else if (trigger & IRQ_TYPE_EDGE_FALLING)
@@ -769,6 +812,8 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
         case METHOD_GPIO_1510:
                 reg += OMAP1510_GPIO_INT_CONTROL;
                 l = __raw_readl(reg);
+                if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
+                        bank->toggle_mask |= 1 << gpio;
                 if (trigger & IRQ_TYPE_EDGE_RISING)
                         l |= 1 << gpio;
                 else if (trigger & IRQ_TYPE_EDGE_FALLING)
@@ -797,22 +842,12 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
                         __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
                 break;
 #endif
-#ifdef CONFIG_ARCH_OMAP730
-        case METHOD_GPIO_730:
-                reg += OMAP730_GPIO_INT_CONTROL;
-                l = __raw_readl(reg);
-                if (trigger & IRQ_TYPE_EDGE_RISING)
-                        l |= 1 << gpio;
-                else if (trigger & IRQ_TYPE_EDGE_FALLING)
-                        l &= ~(1 << gpio);
-                else
-                        goto bad;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP850
-        case METHOD_GPIO_850:
-                reg += OMAP850_GPIO_INT_CONTROL;
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+        case METHOD_GPIO_7XX:
+                reg += OMAP7XX_GPIO_INT_CONTROL;
                 l = __raw_readl(reg);
+                if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
+                        bank->toggle_mask |= 1 << gpio;
                 if (trigger & IRQ_TYPE_EDGE_RISING)
                         l |= 1 << gpio;
                 else if (trigger & IRQ_TYPE_EDGE_FALLING)
@@ -821,9 +856,9 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
                         goto bad;
                 break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                                defined(CONFIG_ARCH_OMAP4)
+#ifdef CONFIG_ARCH_OMAP2PLUS
         case METHOD_GPIO_24XX:
+        case METHOD_GPIO_44XX:
                 set_24xx_gpio_triggering(bank, gpio, trigger);
                 break;
 #endif
@@ -897,23 +932,18 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
                 reg += OMAP1610_GPIO_IRQSTATUS1;
                 break;
 #endif
-#ifdef CONFIG_ARCH_OMAP730
-        case METHOD_GPIO_730:
-                reg += OMAP730_GPIO_INT_STATUS;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP850
-        case METHOD_GPIO_850:
-                reg += OMAP850_GPIO_INT_STATUS;
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+        case METHOD_GPIO_7XX:
+                reg += OMAP7XX_GPIO_INT_STATUS;
                 break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
         case METHOD_GPIO_24XX:
                 reg += OMAP24XX_GPIO_IRQSTATUS1;
                 break;
 #endif
 #if defined(CONFIG_ARCH_OMAP4)
-        case METHOD_GPIO_24XX:
+        case METHOD_GPIO_44XX:
                 reg += OMAP4_GPIO_IRQSTATUS0;
                 break;
 #endif
@@ -924,12 +954,11 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
         __raw_writel(gpio_mask, reg);
 
         /* Workaround for clearing DSP GPIO interrupts to allow retention */
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
-        reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
-#endif
-#if defined(CONFIG_ARCH_OMAP4)
-        reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
-#endif
+        if (cpu_is_omap24xx() || cpu_is_omap34xx())
+                reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
+        else if (cpu_is_omap44xx())
+                reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
+
         if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
                 __raw_writel(gpio_mask, reg);
 
@@ -971,28 +1000,21 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
                 mask = 0xffff;
                 break;
 #endif
-#ifdef CONFIG_ARCH_OMAP730
-        case METHOD_GPIO_730:
-                reg += OMAP730_GPIO_INT_MASK;
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+        case METHOD_GPIO_7XX:
+                reg += OMAP7XX_GPIO_INT_MASK;
                 mask = 0xffffffff;
                 inv = 1;
                 break;
 #endif
-#ifdef CONFIG_ARCH_OMAP850
-        case METHOD_GPIO_850:
-                reg += OMAP850_GPIO_INT_MASK;
-                mask = 0xffffffff;
-                inv = 1;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
         case METHOD_GPIO_24XX:
                 reg += OMAP24XX_GPIO_IRQENABLE1;
                 mask = 0xffffffff;
                 break;
 #endif
 #if defined(CONFIG_ARCH_OMAP4)
-        case METHOD_GPIO_24XX:
+        case METHOD_GPIO_44XX:
                 reg += OMAP4_GPIO_IRQSTATUSSET0;
                 mask = 0xffffffff;
                 break;
@@ -1044,9 +1066,9 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
                 l = gpio_mask;
                 break;
 #endif
-#ifdef CONFIG_ARCH_OMAP730
-        case METHOD_GPIO_730:
-                reg += OMAP730_GPIO_INT_MASK;
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+        case METHOD_GPIO_7XX:
+                reg += OMAP7XX_GPIO_INT_MASK;
                 l = __raw_readl(reg);
                 if (enable)
                         l &= ~(gpio_mask);
@@ -1054,17 +1076,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
                         l |= gpio_mask;
                 break;
 #endif
-#ifdef CONFIG_ARCH_OMAP850
-        case METHOD_GPIO_850:
-                reg += OMAP850_GPIO_INT_MASK;
-                l = __raw_readl(reg);
-                if (enable)
-                        l &= ~(gpio_mask);
-                else
-                        l |= gpio_mask;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
         case METHOD_GPIO_24XX:
                 if (enable)
                         reg += OMAP24XX_GPIO_SETIRQENABLE1;
@@ -1074,7 +1086,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
                 break;
 #endif
 #ifdef CONFIG_ARCH_OMAP4
-        case METHOD_GPIO_24XX:
+        case METHOD_GPIO_44XX:
                 if (enable)
                         reg += OMAP4_GPIO_IRQSTATUSSET0;
                 else
@@ -1104,7 +1116,7 @@ static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int ena
  */
 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
 {
-        unsigned long flags;
+        unsigned long uninitialized_var(flags);
 
         switch (bank->method) {
 #ifdef CONFIG_ARCH_OMAP16XX
@@ -1118,9 +1130,9 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
                 spin_unlock_irqrestore(&bank->lock, flags);
                 return 0;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                                defined(CONFIG_ARCH_OMAP4)
+#ifdef CONFIG_ARCH_OMAP2PLUS
         case METHOD_GPIO_24XX:
+        case METHOD_GPIO_44XX:
                 if (bank->non_wakeup_gpios & (1 << gpio)) {
                         printk(KERN_ERR "Unable to modify wakeup on "
                                         "non-wakeup GPIO%d\n",
@@ -1186,6 +1198,16 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
                 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
         }
 #endif
+        if (!cpu_class_is_omap1()) {
+                if (!bank->mod_usage) {
+                        u32 ctrl;
+                        ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
+                        ctrl &= 0xFFFFFFFE;
+                        /* Module is enabled, clocks are not gated */
+                        __raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL);
+                }
+                bank->mod_usage |= 1 << offset;
+        }
         spin_unlock_irqrestore(&bank->lock, flags);
 
         return 0;
@@ -1204,14 +1226,24 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
                 __raw_writel(1 << offset, reg);
         }
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                                defined(CONFIG_ARCH_OMAP4)
-        if (bank->method == METHOD_GPIO_24XX) {
+#ifdef CONFIG_ARCH_OMAP2PLUS
+        if ((bank->method == METHOD_GPIO_24XX) ||
+                        (bank->method == METHOD_GPIO_44XX)) {
                 /* Disable wake-up during idle for dynamic tick */
                 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
                 __raw_writel(1 << offset, reg);
         }
 #endif
+        if (!cpu_class_is_omap1()) {
+                bank->mod_usage &= ~(1 << offset);
+                if (!bank->mod_usage) {
+                        u32 ctrl;
+                        ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
+                        /* Module is disabled, clocks are gated */
+                        ctrl |= 1;
+                        __raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL);
+                }
+        }
         _reset_gpio(bank, bank->chip.base + offset);
         spin_unlock_irqrestore(&bank->lock, flags);
 }
@@ -1229,7 +1261,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
         void __iomem *isr_reg = NULL;
         u32 isr;
-        unsigned int gpio_irq;
+        unsigned int gpio_irq, gpio_index;
         struct gpio_bank *bank;
         u32 retrigger = 0;
         int unmasked = 0;
@@ -1249,20 +1281,16 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
         if (bank->method == METHOD_GPIO_1610)
                 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
 #endif
-#ifdef CONFIG_ARCH_OMAP730
-        if (bank->method == METHOD_GPIO_730)
-                isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
-#endif
-#ifdef CONFIG_ARCH_OMAP850
-        if (bank->method == METHOD_GPIO_850)
-                isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+        if (bank->method == METHOD_GPIO_7XX)
+                isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
         if (bank->method == METHOD_GPIO_24XX)
                 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
 #endif
 #if defined(CONFIG_ARCH_OMAP4)
-        if (bank->method == METHOD_GPIO_24XX)
+        if (bank->method == METHOD_GPIO_44XX)
                 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
 #endif
         while(1) {
@@ -1300,9 +1328,23 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 
                 gpio_irq = bank->virtual_irq_start;
                 for (; isr != 0; isr >>= 1, gpio_irq++) {
+                        gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
+
                         if (!(isr & 1))
                                 continue;
 
+#ifdef CONFIG_ARCH_OMAP1
+                        /*
+                         * Some chips can't respond to both rising and falling
+                         * at the same time.  If this irq was requested with
+                         * both flags, we need to flip the ICR data for the IRQ
+                         * to respond to the IRQ for the opposite direction.
+                         * This will be indicated in the bank toggle_mask.
+                         */
+                        if (bank->toggle_mask & (1 << gpio_index))
+                                _toggle_gpio_edge_triggering(bank, gpio_index);
+#endif
+
                         generic_handle_irq(gpio_irq);
                 }
         }
@@ -1447,7 +1489,7 @@ static int omap_mpuio_resume_noirq(struct device *dev)
         return 0;
 }
 
-static struct dev_pm_ops omap_mpuio_dev_pm_ops = {
+static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
         .suspend_noirq = omap_mpuio_suspend_noirq,
         .resume_noirq = omap_mpuio_resume_noirq,
 };
@@ -1524,13 +1566,11 @@ static int gpio_is_input(struct gpio_bank *bank, int mask)
         case METHOD_GPIO_1610:
                 reg += OMAP1610_GPIO_DIRECTION;
                 break;
-        case METHOD_GPIO_730:
-                reg += OMAP730_GPIO_DIR_CONTROL;
-                break;
-        case METHOD_GPIO_850:
-                reg += OMAP850_GPIO_DIR_CONTROL;
+        case METHOD_GPIO_7XX:
+                reg += OMAP7XX_GPIO_DIR_CONTROL;
                 break;
         case METHOD_GPIO_24XX:
+        case METHOD_GPIO_44XX:
                 reg += OMAP24XX_GPIO_OE;
                 break;
         }
@@ -1590,7 +1630,7 @@ static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
 /*---------------------------------------------------------------------*/
 
 static int initialized;
-#if !(defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4))
+#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2)
 static struct clk * gpio_ick;
 #endif
 
@@ -1607,6 +1647,23 @@ static struct clk * gpio5_fck;
 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
 #endif
 
+static void __init omap_gpio_show_rev(void)
+{
+        u32 rev;
+
+        if (cpu_is_omap16xx())
+                rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
+        else if (cpu_is_omap24xx() || cpu_is_omap34xx())
+                rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
+        else if (cpu_is_omap44xx())
+                rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
+        else
+                return;
+
+        printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
+                (rev >> 4) & 0x0f, rev & 0x0f);
+}
+
 /* This lock class tells lockdep that GPIO irqs are in a different
  * category than their parents, so it won't report false recursion.
  */
@@ -1617,6 +1674,7 @@ static int __init _omap_gpio_init(void)
         int i;
         int gpio = 0;
         struct gpio_bank *bank;
+        int bank_size = SZ_8K;  /* Module 4KB + L4 4KB except on omap1 */
         char clk_name[11];
 
         initialized = 1;
@@ -1679,77 +1737,45 @@ static int __init _omap_gpio_init(void)
 
 #ifdef CONFIG_ARCH_OMAP15XX
         if (cpu_is_omap15xx()) {
-                printk(KERN_INFO "OMAP1510 GPIO hardware\n");
                 gpio_bank_count = 2;
                 gpio_bank = gpio_bank_1510;
+                bank_size = SZ_2K;
         }
 #endif
 #if defined(CONFIG_ARCH_OMAP16XX)
         if (cpu_is_omap16xx()) {
-                u32 rev;
-
                 gpio_bank_count = 5;
                 gpio_bank = gpio_bank_1610;
-                rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
-                printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
-                       (rev >> 4) & 0x0f, rev & 0x0f);
-        }
-#endif
-#ifdef CONFIG_ARCH_OMAP730
-        if (cpu_is_omap730()) {
-                printk(KERN_INFO "OMAP730 GPIO hardware\n");
-                gpio_bank_count = 7;
-                gpio_bank = gpio_bank_730;
+                bank_size = SZ_2K;
         }
 #endif
-#ifdef CONFIG_ARCH_OMAP850
-        if (cpu_is_omap850()) {
-                printk(KERN_INFO "OMAP850 GPIO hardware\n");
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+        if (cpu_is_omap7xx()) {
                 gpio_bank_count = 7;
-                gpio_bank = gpio_bank_850;
+                gpio_bank = gpio_bank_7xx;
+                bank_size = SZ_2K;
         }
 #endif
-
-#ifdef CONFIG_ARCH_OMAP24XX
+#ifdef CONFIG_ARCH_OMAP2
         if (cpu_is_omap242x()) {
-                int rev;
-
                 gpio_bank_count = 4;
                 gpio_bank = gpio_bank_242x;
-                rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
-                printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
-                        (rev >> 4) & 0x0f, rev & 0x0f);
         }
         if (cpu_is_omap243x()) {
-                int rev;
-
                 gpio_bank_count = 5;
                 gpio_bank = gpio_bank_243x;
-                rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
-                printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
-                        (rev >> 4) & 0x0f, rev & 0x0f);
         }
 #endif
-#ifdef CONFIG_ARCH_OMAP34XX
+#ifdef CONFIG_ARCH_OMAP3
         if (cpu_is_omap34xx()) {
-                int rev;
-
                 gpio_bank_count = OMAP34XX_NR_GPIOS;
                 gpio_bank = gpio_bank_34xx;
-                rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
-                printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
-                        (rev >> 4) & 0x0f, rev & 0x0f);
         }
 #endif
 #ifdef CONFIG_ARCH_OMAP4
         if (cpu_is_omap44xx()) {
-                int rev;
-
                 gpio_bank_count = OMAP34XX_NR_GPIOS;
                 gpio_bank = gpio_bank_44xx;
-                rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
-                printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n",
-                        (rev >> 4) & 0x0f, rev & 0x0f);
         }
 #endif
         for (i = 0; i < gpio_bank_count; i++) {
@@ -1757,6 +1783,14 @@ static int __init _omap_gpio_init(void)
 
                 bank = &gpio_bank[i];
                 spin_lock_init(&bank->lock);
+
+                /* Static mapping, never released */
+                bank->base = ioremap(bank->pbase, bank_size);
+                if (!bank->base) {
+                        printk(KERN_ERR "Could not ioremap gpio bank%i\n", i);
+                        continue;
+                }
+
                 if (bank_is_mpuio(bank))
                         __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
                 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
@@ -1768,42 +1802,56 @@ static int __init _omap_gpio_init(void)
                         __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
                         __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
                 }
-                if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_730) {
-                        __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
-                        __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
+                if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
+                        __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
+                        __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
 
-                        gpio_count = 32; /* 730 has 32-bit GPIOs */
+                        gpio_count = 32; /* 7xx has 32-bit GPIOs */
                 }
 
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                                defined(CONFIG_ARCH_OMAP4)
-                if (bank->method == METHOD_GPIO_24XX) {
+#ifdef CONFIG_ARCH_OMAP2PLUS
+                if ((bank->method == METHOD_GPIO_24XX) ||
+                                (bank->method == METHOD_GPIO_44XX)) {
                         static const u32 non_wakeup_gpios[] = {
                                 0xe203ffc0, 0x08700040
                         };
-                if (cpu_is_omap44xx()) {
-                        __raw_writel(0xffffffff, bank->base +
+
+                        if (cpu_is_omap44xx()) {
+                                __raw_writel(0xffffffff, bank->base +
                                                 OMAP4_GPIO_IRQSTATUSCLR0);
-                        __raw_writew(0x0015, bank->base +
+                                __raw_writew(0x0015, bank->base +
                                                 OMAP4_GPIO_SYSCONFIG);
-                        __raw_writel(0x00000000, bank->base +
+                                __raw_writel(0x00000000, bank->base +
                                                  OMAP4_GPIO_DEBOUNCENABLE);
-                        /* Initialize interface clock ungated, module enabled */
-                        __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
-                } else {
-                        __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
-                        __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
-                        __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
-                        __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN);
-
-                        /* Initialize interface clock ungated, module enabled */
-                        __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
-                }
+                                /*
+                                 * Initialize interface clock ungated,
+                                 * module enabled
+                                 */
+                                __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
+                        } else {
+                                __raw_writel(0x00000000, bank->base +
+                                                OMAP24XX_GPIO_IRQENABLE1);
+                                __raw_writel(0xffffffff, bank->base +
+                                                OMAP24XX_GPIO_IRQSTATUS1);
+                                __raw_writew(0x0015, bank->base +
+                                                OMAP24XX_GPIO_SYSCONFIG);
+                                __raw_writel(0x00000000, bank->base +
+                                                OMAP24XX_GPIO_DEBOUNCE_EN);
+
+                                /*
+                                 * Initialize interface clock ungated,
+                                 * module enabled
+                                 */
+                                __raw_writel(0, bank->base +
+                                                OMAP24XX_GPIO_CTRL);
+                        }
                         if (i < ARRAY_SIZE(non_wakeup_gpios))
                                 bank->non_wakeup_gpios = non_wakeup_gpios[i];
                         gpio_count = 32;
                 }
 #endif
+
+                bank->mod_usage = 0;
                 /* REVISIT eventually switch from OMAP-specific gpio structs
                  * over to the generic ones
                  */
@@ -1862,11 +1910,12 @@ static int __init _omap_gpio_init(void)
         if (cpu_is_omap34xx())
                 omap_writel(1 << 0, 0x48306814);
 
+        omap_gpio_show_rev();
+
         return 0;
 }
 
-#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
-                defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
 {
         int i;
@@ -1889,7 +1938,7 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
                         wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
                         break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
                 case METHOD_GPIO_24XX:
                         wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
                         wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
@@ -1897,7 +1946,7 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
                         break;
 #endif
 #ifdef CONFIG_ARCH_OMAP4
-                case METHOD_GPIO_24XX:
+                case METHOD_GPIO_44XX:
                         wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
                         wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
                         wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
@@ -1937,14 +1986,14 @@ static int omap_gpio_resume(struct sys_device *dev)
                         wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
                         break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
                 case METHOD_GPIO_24XX:
                         wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
                         wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
                         break;
 #endif
 #ifdef CONFIG_ARCH_OMAP4
-                case METHOD_GPIO_24XX:
+                case METHOD_GPIO_44XX:
                         wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
                         wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
                         break;
@@ -1975,8 +2024,7 @@ static struct sys_device omap_gpio_device = {
 
 #endif
 
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                                defined(CONFIG_ARCH_OMAP4)
+#ifdef CONFIG_ARCH_OMAP2PLUS
 
 static int workaround_enabled;
 
@@ -1992,29 +2040,42 @@ void omap2_gpio_prepare_for_retention(void)
 
                 if (!(bank->enabled_non_wakeup_gpios))
                         continue;
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
-                bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
-                l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
-                l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-                bank->saved_datain = __raw_readl(bank->base +
-                                                        OMAP4_GPIO_DATAIN);
-                l1 = __raw_readl(bank->base + OMAP4_GPIO_FALLINGDETECT);
-                l2 = __raw_readl(bank->base + OMAP4_GPIO_RISINGDETECT);
-#endif
+
+                if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+                        bank->saved_datain = __raw_readl(bank->base +
+                                        OMAP24XX_GPIO_DATAIN);
+                        l1 = __raw_readl(bank->base +
+                                        OMAP24XX_GPIO_FALLINGDETECT);
+                        l2 = __raw_readl(bank->base +
+                                        OMAP24XX_GPIO_RISINGDETECT);
+                }
+
+                if (cpu_is_omap44xx()) {
+                        bank->saved_datain = __raw_readl(bank->base +
+                                                OMAP4_GPIO_DATAIN);
+                        l1 = __raw_readl(bank->base +
+                                                OMAP4_GPIO_FALLINGDETECT);
+                        l2 = __raw_readl(bank->base +
+                                                OMAP4_GPIO_RISINGDETECT);
+                }
+
                 bank->saved_fallingdetect = l1;
                 bank->saved_risingdetect = l2;
                 l1 &= ~bank->enabled_non_wakeup_gpios;
                 l2 &= ~bank->enabled_non_wakeup_gpios;
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
-                __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
-                __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-                __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
-                __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
-#endif
+
+                if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+                        __raw_writel(l1, bank->base +
+                                        OMAP24XX_GPIO_FALLINGDETECT);
+                        __raw_writel(l2, bank->base +
+                                        OMAP24XX_GPIO_RISINGDETECT);
+                }
+
+                if (cpu_is_omap44xx()) {
+                        __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
+                        __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
+                }
+
                 c++;
         }
         if (!c) {
@@ -2036,20 +2097,23 @@ void omap2_gpio_resume_after_retention(void)
 
                 if (!(bank->enabled_non_wakeup_gpios))
                         continue;
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
-                __raw_writel(bank->saved_fallingdetect,
+
+                if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+                        __raw_writel(bank->saved_fallingdetect,
                                  bank->base + OMAP24XX_GPIO_FALLINGDETECT);
-                __raw_writel(bank->saved_risingdetect,
+                        __raw_writel(bank->saved_risingdetect,
                                  bank->base + OMAP24XX_GPIO_RISINGDETECT);
-                l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-                __raw_writel(bank->saved_fallingdetect,
+                        l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
+                }
+
+                if (cpu_is_omap44xx()) {
+                        __raw_writel(bank->saved_fallingdetect,
                                  bank->base + OMAP4_GPIO_FALLINGDETECT);
-                __raw_writel(bank->saved_risingdetect,
+                        __raw_writel(bank->saved_risingdetect,
                                  bank->base + OMAP4_GPIO_RISINGDETECT);
-                l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
-#endif
+                        l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
+                }
+
                 /* Check if any of the non-wakeup interrupt GPIOs have changed
                  * state.  If so, generate an IRQ by software.  This is
                  * horribly racy, but it's the best we can do to work around
@@ -2075,30 +2139,36 @@ void omap2_gpio_resume_after_retention(void)
 
                 if (gen) {
                         u32 old0, old1;
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
-                        old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
-                        old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
-                        __raw_writel(old0 | gen, bank->base +
+
+                        if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+                                old0 = __raw_readl(bank->base +
                                         OMAP24XX_GPIO_LEVELDETECT0);
-                        __raw_writel(old1 | gen, bank->base +
+                                old1 = __raw_readl(bank->base +
                                         OMAP24XX_GPIO_LEVELDETECT1);
-                        __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
-                        __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-                        old0 = __raw_readl(bank->base +
+                                __raw_writel(old0 | gen, bank->base +
+                                        OMAP24XX_GPIO_LEVELDETECT0);
+                                __raw_writel(old1 | gen, bank->base +
+                                        OMAP24XX_GPIO_LEVELDETECT1);
+                                __raw_writel(old0, bank->base +
+                                        OMAP24XX_GPIO_LEVELDETECT0);
+                                __raw_writel(old1, bank->base +
+                                        OMAP24XX_GPIO_LEVELDETECT1);
+                        }
+
+                        if (cpu_is_omap44xx()) {
+                                old0 = __raw_readl(bank->base +
                                                 OMAP4_GPIO_LEVELDETECT0);
-                        old1 = __raw_readl(bank->base +
+                                old1 = __raw_readl(bank->base +
                                                 OMAP4_GPIO_LEVELDETECT1);
-                        __raw_writel(old0 | l, bank->base +
+                                __raw_writel(old0 | l, bank->base +
                                                 OMAP4_GPIO_LEVELDETECT0);
-                        __raw_writel(old1 | l, bank->base +
+                                __raw_writel(old1 | l, bank->base +
                                                 OMAP4_GPIO_LEVELDETECT1);
-                        __raw_writel(old0, bank->base +
+                                __raw_writel(old0, bank->base +
                                                 OMAP4_GPIO_LEVELDETECT0);
-                        __raw_writel(old1, bank->base +
+                                __raw_writel(old1, bank->base +
                                                 OMAP4_GPIO_LEVELDETECT1);
-#endif
+                        }
                 }
         }
 
@@ -2106,6 +2176,81 @@ void omap2_gpio_resume_after_retention(void)
 
 #endif
 
+#ifdef CONFIG_ARCH_OMAP3
+/* save the registers of bank 2-6 */
+void omap_gpio_save_context(void)
+{
+        int i;
+
+        /* saving banks from 2-6 only since GPIO1 is in WKUP */
+        for (i = 1; i < gpio_bank_count; i++) {
+                struct gpio_bank *bank = &gpio_bank[i];
+                gpio_context[i].sysconfig =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG);
+                gpio_context[i].irqenable1 =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
+                gpio_context[i].irqenable2 =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
+                gpio_context[i].wake_en =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
+                gpio_context[i].ctrl =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
+                gpio_context[i].oe =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_OE);
+                gpio_context[i].leveldetect0 =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
+                gpio_context[i].leveldetect1 =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+                gpio_context[i].risingdetect =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
+                gpio_context[i].fallingdetect =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
+                gpio_context[i].dataout =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
+                gpio_context[i].setwkuena =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_SETWKUENA);
+                gpio_context[i].setdataout =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_SETDATAOUT);
+        }
+}
+
+/* restore the required registers of bank 2-6 */
+void omap_gpio_restore_context(void)
+{
+        int i;
+
+        for (i = 1; i < gpio_bank_count; i++) {
+                struct gpio_bank *bank = &gpio_bank[i];
+                __raw_writel(gpio_context[i].sysconfig,
+                                bank->base + OMAP24XX_GPIO_SYSCONFIG);
+                __raw_writel(gpio_context[i].irqenable1,
+                                bank->base + OMAP24XX_GPIO_IRQENABLE1);
+                __raw_writel(gpio_context[i].irqenable2,
+                                bank->base + OMAP24XX_GPIO_IRQENABLE2);
+                __raw_writel(gpio_context[i].wake_en,
+                                bank->base + OMAP24XX_GPIO_WAKE_EN);
+                __raw_writel(gpio_context[i].ctrl,
+                                bank->base + OMAP24XX_GPIO_CTRL);
+                __raw_writel(gpio_context[i].oe,
+                                bank->base + OMAP24XX_GPIO_OE);
+                __raw_writel(gpio_context[i].leveldetect0,
+                                bank->base + OMAP24XX_GPIO_LEVELDETECT0);
+                __raw_writel(gpio_context[i].leveldetect1,
+                                bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+                __raw_writel(gpio_context[i].risingdetect,
+                                bank->base + OMAP24XX_GPIO_RISINGDETECT);
+                __raw_writel(gpio_context[i].fallingdetect,
+                                bank->base + OMAP24XX_GPIO_FALLINGDETECT);
+                __raw_writel(gpio_context[i].dataout,
+                                bank->base + OMAP24XX_GPIO_DATAOUT);
+                __raw_writel(gpio_context[i].setwkuena,
+                                bank->base + OMAP24XX_GPIO_SETWKUENA);
+                __raw_writel(gpio_context[i].setdataout,
+                                bank->base + OMAP24XX_GPIO_SETDATAOUT);
+        }
+}
+#endif
+
 /*
  * This may get called early from board specific init
  * for boards that have interrupts routed via FPGA.
@@ -2127,8 +2272,7 @@ static int __init omap_gpio_sysinit(void)
 
         mpuio_init();
 
-#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
-                defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
         if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
                 if (ret == 0) {
                         ret = sysdev_class_register(&omap_gpio_sysclass);
@@ -2160,8 +2304,7 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
 
                 if (bank_is_mpuio(bank))
                         gpio = OMAP_MPUIO(0);
-                else if (cpu_class_is_omap2() || cpu_is_omap730() ||
-                                cpu_is_omap850())
+                else if (cpu_class_is_omap2() || cpu_is_omap7xx())
                         bankwidth = 32;
 
                 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
@@ -2188,8 +2331,7 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
 /* FIXME for at least omap2, show pullup/pulldown state */
 
                         irqstat = irq_desc[irq].status;
-#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) ||   \
-                defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
                         if (is_in && ((bank->suspend_wakeup & mask)
                                         || irqstat & IRQ_TYPE_SENSE_MASK)) {
                                 char    *trigger = NULL;
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index 8b848391f0c8..624e26298faa 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -27,7 +27,8 @@
 #include <linux/platform_device.h>
 #include <linux/i2c.h>
 #include <mach/irqs.h>
-#include <mach/mux.h>
+#include <plat/mux.h>
+#include <plat/i2c.h>
 
 #define OMAP_I2C_SIZE           0x3f
 #define OMAP1_I2C_BASE          0xfffb3800
@@ -50,10 +51,10 @@ static const char name[] = "i2c_omap";
 
 static struct resource i2c_resources[][2] = {
         { I2C_RESOURCE_BUILDER(0, 0) },
-#if     defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if     defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
         { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, INT_24XX_I2C2_IRQ) },
 #endif
-#if     defined(CONFIG_ARCH_OMAP34XX)
+#if     defined(CONFIG_ARCH_OMAP3)
         { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, INT_34XX_I2C3_IRQ) },
 #endif
 };
@@ -72,55 +73,16 @@ static struct resource i2c_resources[][2] = {
 static u32 i2c_rate[ARRAY_SIZE(i2c_resources)];
 static struct platform_device omap_i2c_devices[] = {
         I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_rate[0]),
-#if     defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if     defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
         I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_rate[1]),
 #endif
-#if     defined(CONFIG_ARCH_OMAP34XX)
+#if     defined(CONFIG_ARCH_OMAP3)
         I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_rate[2]),
 #endif
 };
 
-#if defined(CONFIG_ARCH_OMAP24XX)
-static const int omap24xx_pins[][2] = {
-        { M19_24XX_I2C1_SCL, L15_24XX_I2C1_SDA },
-        { J15_24XX_I2C2_SCL, H19_24XX_I2C2_SDA },
-};
-#else
-static const int omap24xx_pins[][2] = {};
-#endif
-#if defined(CONFIG_ARCH_OMAP34XX)
-static const int omap34xx_pins[][2] = {
-        { K21_34XX_I2C1_SCL, J21_34XX_I2C1_SDA},
-        { AF15_34XX_I2C2_SCL, AE15_34XX_I2C2_SDA},
-        { AF14_34XX_I2C3_SCL, AG14_34XX_I2C3_SDA},
-};
-#else
-static const int omap34xx_pins[][2] = {};
-#endif
-
 #define OMAP_I2C_CMDLINE_SETUP  (BIT(31))
 
-static void __init omap_i2c_mux_pins(int bus)
-{
-        int scl, sda;
-
-        if (cpu_class_is_omap1()) {
-                scl = I2C_SCL;
-                sda = I2C_SDA;
-        } else if (cpu_is_omap24xx()) {
-                scl = omap24xx_pins[bus][0];
-                sda = omap24xx_pins[bus][1];
-        } else if (cpu_is_omap34xx()) {
-                scl = omap34xx_pins[bus][0];
-                sda = omap34xx_pins[bus][1];
-        } else {
-                return;
-        }
-
-        omap_cfg_reg(sda);
-        omap_cfg_reg(scl);
-}
-
 static int __init omap_i2c_nr_ports(void)
 {
         int ports = 0;
@@ -156,7 +118,11 @@ static int __init omap_i2c_add_bus(int bus_id)
                 res[1].start = irq;
         }
 
-        omap_i2c_mux_pins(bus_id - 1);
+        if (cpu_class_is_omap1())
+                omap1_i2c_mux_pins(bus_id);
+        if (cpu_class_is_omap2())
+                omap2_i2c_mux_pins(bus_id);
+
         return platform_device_register(pdev);
 }
 
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
deleted file mode 100644
index 4b8b0d65cbf2..000000000000
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- *  arch/arm/plat-omap/include/mach/clock.h
- *
- *  Copyright (C) 2004 - 2005 Nokia corporation
- *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
- *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_OMAP_CLOCK_H
-#define __ARCH_ARM_OMAP_CLOCK_H
-
-struct module;
-struct clk;
-struct clockdomain;
-
-struct clkops {
-        int                     (*enable)(struct clk *);
-        void                    (*disable)(struct clk *);
-        void                    (*find_idlest)(struct clk *, void __iomem **, u8 *);
-        void                    (*find_companion)(struct clk *, void __iomem **, u8 *);
-};
-
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
-                defined(CONFIG_ARCH_OMAP4)
-
-struct clksel_rate {
-        u32                     val;
-        u8                      div;
-        u8                      flags;
-};
-
-struct clksel {
-        struct clk               *parent;
-        const struct clksel_rate *rates;
-};
-
-struct dpll_data {
-        void __iomem            *mult_div1_reg;
-        u32                     mult_mask;
-        u32                     div1_mask;
-        struct clk              *clk_bypass;
-        struct clk              *clk_ref;
-        void __iomem            *control_reg;
-        u32                     enable_mask;
-        unsigned int            rate_tolerance;
-        unsigned long           last_rounded_rate;
-        u16                     last_rounded_m;
-        u8                      last_rounded_n;
-        u8                      min_divider;
-        u8                      max_divider;
-        u32                     max_tolerance;
-        u16                     max_multiplier;
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-        u8                      modes;
-        void __iomem            *autoidle_reg;
-        void __iomem            *idlest_reg;
-        u32                     autoidle_mask;
-        u32                     freqsel_mask;
-        u32                     idlest_mask;
-        u8                      auto_recal_bit;
-        u8                      recal_en_bit;
-        u8                      recal_st_bit;
-#  endif
-};
-
-#endif
-
-struct clk {
-        struct list_head        node;
-        const struct clkops     *ops;
-        const char              *name;
-        int                     id;
-        struct clk              *parent;
-        struct list_head        children;
-        struct list_head        sibling;        /* node for children */
-        unsigned long           rate;
-        __u32                   flags;
-        void __iomem            *enable_reg;
-        unsigned long           (*recalc)(struct clk *);
-        int                     (*set_rate)(struct clk *, unsigned long);
-        long                    (*round_rate)(struct clk *, unsigned long);
-        void                    (*init)(struct clk *);
-        __u8                    enable_bit;
-        __s8                    usecount;
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
-                defined(CONFIG_ARCH_OMAP4)
-        u8                      fixed_div;
-        void __iomem            *clksel_reg;
-        u32                     clksel_mask;
-        const struct clksel     *clksel;
-        struct dpll_data        *dpll_data;
-        const char              *clkdm_name;
-        struct clockdomain      *clkdm;
-#else
-        __u8                    rate_offset;
-        __u8                    src_offset;
-#endif
-#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
-        struct dentry           *dent;  /* For visible tree hierarchy */
-#endif
-};
-
-struct cpufreq_frequency_table;
-
-struct clk_functions {
-        int             (*clk_enable)(struct clk *clk);
-        void            (*clk_disable)(struct clk *clk);
-        long            (*clk_round_rate)(struct clk *clk, unsigned long rate);
-        int             (*clk_set_rate)(struct clk *clk, unsigned long rate);
-        int             (*clk_set_parent)(struct clk *clk, struct clk *parent);
-        void            (*clk_allow_idle)(struct clk *clk);
-        void            (*clk_deny_idle)(struct clk *clk);
-        void            (*clk_disable_unused)(struct clk *clk);
-#ifdef CONFIG_CPU_FREQ
-        void            (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
-#endif
-};
-
-extern unsigned int mpurate;
-
-extern int clk_init(struct clk_functions *custom_clocks);
-extern void clk_preinit(struct clk *clk);
-extern int clk_register(struct clk *clk);
-extern void clk_reparent(struct clk *child, struct clk *parent);
-extern void clk_unregister(struct clk *clk);
-extern void propagate_rate(struct clk *clk);
-extern void recalculate_root_clocks(void);
-extern unsigned long followparent_recalc(struct clk *clk);
-extern void clk_enable_init_clocks(void);
-#ifdef CONFIG_CPU_FREQ
-extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
-#endif
-
-extern const struct clkops clkops_null;
-
-/* Clock flags */
-/* bit 0 is free */
-#define RATE_FIXED              (1 << 1)        /* Fixed clock rate */
-/* bits 2-4 are free */
-#define ENABLE_REG_32BIT        (1 << 5)        /* Use 32-bit access */
-#define CLOCK_IDLE_CONTROL      (1 << 7)
-#define CLOCK_NO_IDLE_PARENT    (1 << 8)
-#define DELAYED_APP             (1 << 9)        /* Delay application of clock */
-#define CONFIG_PARTICIPANT      (1 << 10)       /* Fundamental clock */
-#define ENABLE_ON_INIT          (1 << 11)       /* Enable upon framework init */
-#define INVERT_ENABLE           (1 << 12)       /* 0 enables, 1 disables */
-/* bits 13-31 are currently free */
-
-/* Clksel_rate flags */
-#define DEFAULT_RATE            (1 << 0)
-#define RATE_IN_242X            (1 << 1)
-#define RATE_IN_243X            (1 << 2)
-#define RATE_IN_343X            (1 << 3)        /* rates common to all 343X */
-#define RATE_IN_3430ES2         (1 << 4)        /* 3430ES2 rates only */
-
-#define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
-
-
-#endif
diff --git a/arch/arm/plat-omap/include/mach/clockdomain.h b/arch/arm/plat-omap/include/mach/clockdomain.h
deleted file mode 100644
index 99ebd886f134..000000000000
--- a/arch/arm/plat-omap/include/mach/clockdomain.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/clockdomain.h
- *
- * OMAP2/3 clockdomain framework functions
- *
- * Copyright (C) 2008 Texas Instruments, Inc.
- * Copyright (C) 2008 Nokia Corporation
- *
- * Written by Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
-#define __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
-
-#include <mach/powerdomain.h>
-#include <mach/clock.h>
-#include <mach/cpu.h>
-
-/* Clockdomain capability flags */
-#define CLKDM_CAN_FORCE_SLEEP                   (1 << 0)
-#define CLKDM_CAN_FORCE_WAKEUP                  (1 << 1)
-#define CLKDM_CAN_ENABLE_AUTO                   (1 << 2)
-#define CLKDM_CAN_DISABLE_AUTO                  (1 << 3)
-
-#define CLKDM_CAN_HWSUP         (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
-#define CLKDM_CAN_SWSUP         (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
-#define CLKDM_CAN_HWSUP_SWSUP   (CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP)
-
-/* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */
-#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO         0x0
-#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO          0x1
-
-/* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */
-#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO         0x0
-#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP          0x1
-#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP         0x2
-#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO          0x3
-
-/*
- * struct clkdm_pwrdm_autodep - a powerdomain that should have wkdeps
- * and sleepdeps added when a powerdomain should stay active in hwsup mode;
- * and conversely, removed when the powerdomain should be allowed to go
- * inactive in hwsup mode.
- */
-struct clkdm_pwrdm_autodep {
-
-        union {
-                /* Name of the powerdomain to add a wkdep/sleepdep on */
-                const char *name;
-
-                /* Powerdomain pointer (looked up at clkdm_init() time) */
-                struct powerdomain *ptr;
-        } pwrdm;
-
-        /* OMAP chip types that this clockdomain dep is valid on */
-        const struct omap_chip_id omap_chip;
-
-};
-
-struct clockdomain {
-
-        /* Clockdomain name */
-        const char *name;
-
-        union {
-                /* Powerdomain enclosing this clockdomain */
-                const char *name;
-
-                /* Powerdomain pointer assigned at clkdm_register() */
-                struct powerdomain *ptr;
-        } pwrdm;
-
-        /* CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg */
-        const u16 clktrctrl_mask;
-
-        /* Clockdomain capability flags */
-        const u8 flags;
-
-        /* OMAP chip types that this clockdomain is valid on */
-        const struct omap_chip_id omap_chip;
-
-        /* Usecount tracking */
-        atomic_t usecount;
-
-        struct list_head node;
-
-};
-
-void clkdm_init(struct clockdomain **clkdms, struct clkdm_pwrdm_autodep *autodeps);
-int clkdm_register(struct clockdomain *clkdm);
-int clkdm_unregister(struct clockdomain *clkdm);
-struct clockdomain *clkdm_lookup(const char *name);
-
-int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
-                        void *user);
-struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm);
-
-void omap2_clkdm_allow_idle(struct clockdomain *clkdm);
-void omap2_clkdm_deny_idle(struct clockdomain *clkdm);
-
-int omap2_clkdm_wakeup(struct clockdomain *clkdm);
-int omap2_clkdm_sleep(struct clockdomain *clkdm);
-
-int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
-int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
-
-#endif
diff --git a/arch/arm/plat-omap/include/mach/debug-macro.S b/arch/arm/plat-omap/include/mach/debug-macro.S
deleted file mode 100644
index ac24050e3416..000000000000
--- a/arch/arm/plat-omap/include/mach/debug-macro.S
+++ /dev/null
@@ -1,70 +0,0 @@
-/* arch/arm/plat-omap/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-#ifdef CONFIG_ARCH_OMAP1
-                moveq   \rx, #0xff000000        @ physical base address
-                movne   \rx, #0xfe000000        @ virtual base
-                orr     \rx, \rx, #0x00fb0000
-#ifdef CONFIG_OMAP_LL_DEBUG_UART3
-                orr     \rx, \rx, #0x00009000   @ UART 3
-#endif
-#if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3)
-                orr     \rx, \rx, #0x00000800   @ UART 2 & 3
-#endif
-
-#elif  CONFIG_ARCH_OMAP2
-                moveq   \rx, #0x48000000        @ physical base address
-                movne   \rx, #0xd8000000        @ virtual base
-                orr     \rx, \rx, #0x0006a000
-#ifdef CONFIG_OMAP_LL_DEBUG_UART2
-                add     \rx, \rx, #0x00002000   @ UART 2
-#endif
-#ifdef CONFIG_OMAP_LL_DEBUG_UART3
-                add     \rx, \rx, #0x00004000   @ UART 3
-#endif
-
-#elif defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-                moveq   \rx, #0x48000000        @ physical base address
-                movne   \rx, #0xd8000000        @ virtual base
-                orr     \rx, \rx, #0x0006a000
-#ifdef CONFIG_OMAP_LL_DEBUG_UART2
-                add     \rx, \rx, #0x00002000   @ UART 2
-#endif
-#ifdef CONFIG_OMAP_LL_DEBUG_UART3
-                add     \rx, \rx, #0x00fb0000   @ UART 3
-                add     \rx, \rx, #0x00006000
-#endif
-#endif
-                .endm
-
-                .macro  senduart,rd,rx
-                strb    \rd, [\rx]
-                .endm
-
-                .macro  busyuart,rd,rx
-1001:           ldrb    \rd, [\rx, #(0x5 << 2)] @ OMAP-1510 and friends
-                and     \rd, \rd, #0x60
-                teq     \rd, #0x60
-                beq     1002f
-                ldrb    \rd, [\rx, #(0x5 << 0)] @ OMAP-730 only
-                and     \rd, \rd, #0x60
-                teq     \rd, #0x60
-                bne     1001b
-1002:
-                .endm
-
-                .macro  waituart,rd,rx
-                .endm
diff --git a/arch/arm/plat-omap/include/mach/entry-macro.S b/arch/arm/plat-omap/include/mach/entry-macro.S
deleted file mode 100644
index a5592991634d..000000000000
--- a/arch/arm/plat-omap/include/mach/entry-macro.S
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for OMAP-based platforms
- *
- * Copyright (C) 2009 Texas Instruments
- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/irqs.h>
-#include <asm/hardware/gic.h>
-
-#if defined(CONFIG_ARCH_OMAP1)
-
-#if defined(CONFIG_ARCH_OMAP730) && \
-        (defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX))
-#error "FIXME: OMAP730 doesn't support multiple-OMAP"
-#elif defined(CONFIG_ARCH_OMAP730)
-#define INT_IH2_IRQ             INT_730_IH2_IRQ
-#elif defined(CONFIG_ARCH_OMAP15XX)
-#define INT_IH2_IRQ             INT_1510_IH2_IRQ
-#elif defined(CONFIG_ARCH_OMAP16XX)
-#define INT_IH2_IRQ             INT_1610_IH2_IRQ
-#else
-#warning "IH2 IRQ defaulted"
-#define INT_IH2_IRQ             INT_1510_IH2_IRQ
-#endif
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \base, =OMAP1_IO_ADDRESS(OMAP_IH1_BASE)
-                ldr     \irqnr, [\base, #IRQ_ITR_REG_OFFSET]
-                ldr     \tmp, [\base, #IRQ_MIR_REG_OFFSET]
-                mov     \irqstat, #0xffffffff
-                bic     \tmp, \irqstat, \tmp
-                tst     \irqnr, \tmp
-                beq     1510f
-
-                ldr     \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET]
-                cmp     \irqnr, #0
-                ldreq   \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
-                cmpeq   \irqnr, #INT_IH2_IRQ
-                ldreq   \base, =OMAP1_IO_ADDRESS(OMAP_IH2_BASE)
-                ldreq   \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
-                addeqs  \irqnr, \irqnr, #32
-1510:
-                .endm
-
-#endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                        defined(CONFIG_ARCH_OMAP4)
-
-#include <mach/omap24xx.h>
-#include <mach/omap34xx.h>
-
-/* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */
-#if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430)
-#define OMAP2_VA_IC_BASE                OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE)
-#elif defined(CONFIG_ARCH_OMAP34XX)
-#define OMAP2_VA_IC_BASE                OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE)
-#endif
-#if defined(CONFIG_ARCH_OMAP4)
-#include <mach/omap44xx.h>
-#endif
-#define INTCPS_SIR_IRQ_OFFSET   0x0040          /* Active interrupt offset */
-#define ACTIVEIRQ_MASK          0x7f            /* Active interrupt bits */
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-#ifndef CONFIG_ARCH_OMAP4
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \base, =OMAP2_VA_IC_BASE
-                ldr     \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
-                cmp     \irqnr, #0x0
-                bne     2222f
-                ldr     \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
-                cmp     \irqnr, #0x0
-                bne     2222f
-                ldr     \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
-                cmp     \irqnr, #0x0
-2222:
-                ldrne   \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
-                and     \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
-
-                .endm
-#else
-                /*
-                 * The interrupt numbering scheme is defined in the
-                 * interrupt controller spec.  To wit:
-                 *
-                 * Interrupts 0-15 are IPI
-                 * 16-28 are reserved
-                 * 29-31 are local.  We allow 30 to be used for the watchdog.
-                 * 32-1020 are global
-                 * 1021-1022 are reserved
-                 * 1023 is "spurious" (no interrupt)
-                 *
-                 * For now, we ignore all local interrupts so only return an
-                 * interrupt if it's between 30 and 1020.  The test_for_ipi
-                 * routine below will pick up on IPIs.
-                 * A simple read from the controller will tell us the number
-                 * of the highest priority enabled interrupt.
-                 * We then just need to check whether it is in the
-                 * valid range for an IRQ (30-1020 inclusive).
-                 */
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \base, =OMAP44XX_VA_GIC_CPU_BASE
-                ldr     \irqstat, [\base, #GIC_CPU_INTACK]
-
-                ldr     \tmp, =1021
-
-                bic     \irqnr, \irqstat, #0x1c00
-
-                cmp     \irqnr, #29
-                cmpcc   \irqnr, \irqnr
-                cmpne   \irqnr, \tmp
-                cmpcs   \irqnr, \irqnr
-                .endm
-
-                /* We assume that irqstat (the raw value of the IRQ acknowledge
-                 * register) is preserved from the macro above.
-                 * If there is an IPI, we immediately signal end of interrupt
-                 * on the controller, since this requires the original irqstat
-                 * value which we won't easily be able to recreate later.
-                 */
-
-                .macro test_for_ipi, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #16
-                it      cc
-                strcc   \irqstat, [\base, #GIC_CPU_EOI]
-                it      cs
-                cmpcs   \irqnr, \irqnr
-                .endm
-
-                /* As above, this assumes that irqstat and base are preserved */
-
-                .macro test_for_ltirq, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                mov     \tmp, #0
-                cmp     \irqnr, #29
-                itt     eq
-                moveq   \tmp, #1
-                streq   \irqstat, [\base, #GIC_CPU_EOI]
-                cmp     \tmp, #0
-                .endm
-#endif
-
-                .macro  irq_prio_table
-                .endm
-
-#endif
diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h
deleted file mode 100644
index 28a165058b61..000000000000
--- a/arch/arm/plat-omap/include/mach/irqs.h
+++ /dev/null
@@ -1,568 +0,0 @@
-/*
- *  arch/arm/plat-omap/include/mach/irqs.h
- *
- *  Copyright (C) Greg Lonnon 2001
- *  Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
- *
- * Copyright (C) 2009 Texas Instruments
- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
- *       are different.
- */
-
-#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
-#define __ASM_ARCH_OMAP15XX_IRQS_H
-
-/*
- * IRQ numbers for interrupt handler 1
- *
- * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
- *
- */
-#define INT_CAMERA              1
-#define INT_FIQ                 3
-#define INT_RTDX                6
-#define INT_DSP_MMU_ABORT       7
-#define INT_HOST                8
-#define INT_ABORT               9
-#define INT_BRIDGE_PRIV         13
-#define INT_GPIO_BANK1          14
-#define INT_UART3               15
-#define INT_TIMER3              16
-#define INT_DMA_CH0_6           19
-#define INT_DMA_CH1_7           20
-#define INT_DMA_CH2_8           21
-#define INT_DMA_CH3             22
-#define INT_DMA_CH4             23
-#define INT_DMA_CH5             24
-#define INT_DMA_LCD             25
-#define INT_TIMER1              26
-#define INT_WD_TIMER            27
-#define INT_BRIDGE_PUB          28
-#define INT_TIMER2              30
-#define INT_LCD_CTRL            31
-
-/*
- * OMAP-1510 specific IRQ numbers for interrupt handler 1
- */
-#define INT_1510_IH2_IRQ        0
-#define INT_1510_RES2           2
-#define INT_1510_SPI_TX         4
-#define INT_1510_SPI_RX         5
-#define INT_1510_DSP_MAILBOX1   10
-#define INT_1510_DSP_MAILBOX2   11
-#define INT_1510_RES12          12
-#define INT_1510_LB_MMU         17
-#define INT_1510_RES18          18
-#define INT_1510_LOCAL_BUS      29
-
-/*
- * OMAP-1610 specific IRQ numbers for interrupt handler 1
- */
-#define INT_1610_IH2_IRQ        0
-#define INT_1610_IH2_FIQ        2
-#define INT_1610_McBSP2_TX      4
-#define INT_1610_McBSP2_RX      5
-#define INT_1610_DSP_MAILBOX1   10
-#define INT_1610_DSP_MAILBOX2   11
-#define INT_1610_LCD_LINE       12
-#define INT_1610_GPTIMER1       17
-#define INT_1610_GPTIMER2       18
-#define INT_1610_SSR_FIFO_0     29
-
-/*
- * OMAP-730 specific IRQ numbers for interrupt handler 1
- */
-#define INT_730_IH2_FIQ         0
-#define INT_730_IH2_IRQ         1
-#define INT_730_USB_NON_ISO     2
-#define INT_730_USB_ISO         3
-#define INT_730_ICR             4
-#define INT_730_EAC             5
-#define INT_730_GPIO_BANK1      6
-#define INT_730_GPIO_BANK2      7
-#define INT_730_GPIO_BANK3      8
-#define INT_730_McBSP2TX        10
-#define INT_730_McBSP2RX        11
-#define INT_730_McBSP2RX_OVF    12
-#define INT_730_LCD_LINE        14
-#define INT_730_GSM_PROTECT     15
-#define INT_730_TIMER3          16
-#define INT_730_GPIO_BANK5      17
-#define INT_730_GPIO_BANK6      18
-#define INT_730_SPGIO_WR        29
-
-/*
- * OMAP-850 specific IRQ numbers for interrupt handler 1
- */
-#define INT_850_IH2_FIQ         0
-#define INT_850_IH2_IRQ         1
-#define INT_850_USB_NON_ISO     2
-#define INT_850_USB_ISO         3
-#define INT_850_ICR             4
-#define INT_850_EAC             5
-#define INT_850_GPIO_BANK1      6
-#define INT_850_GPIO_BANK2      7
-#define INT_850_GPIO_BANK3      8
-#define INT_850_McBSP2TX        10
-#define INT_850_McBSP2RX        11
-#define INT_850_McBSP2RX_OVF    12
-#define INT_850_LCD_LINE        14
-#define INT_850_GSM_PROTECT     15
-#define INT_850_TIMER3          16
-#define INT_850_GPIO_BANK5      17
-#define INT_850_GPIO_BANK6      18
-#define INT_850_SPGIO_WR        29
-
-
-/*
- * IRQ numbers for interrupt handler 2
- *
- * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
- */
-#define IH2_BASE                32
-
-#define INT_KEYBOARD            (1 + IH2_BASE)
-#define INT_uWireTX             (2 + IH2_BASE)
-#define INT_uWireRX             (3 + IH2_BASE)
-#define INT_I2C                 (4 + IH2_BASE)
-#define INT_MPUIO               (5 + IH2_BASE)
-#define INT_USB_HHC_1           (6 + IH2_BASE)
-#define INT_McBSP3TX            (10 + IH2_BASE)
-#define INT_McBSP3RX            (11 + IH2_BASE)
-#define INT_McBSP1TX            (12 + IH2_BASE)
-#define INT_McBSP1RX            (13 + IH2_BASE)
-#define INT_UART1               (14 + IH2_BASE)
-#define INT_UART2               (15 + IH2_BASE)
-#define INT_BT_MCSI1TX          (16 + IH2_BASE)
-#define INT_BT_MCSI1RX          (17 + IH2_BASE)
-#define INT_SOSSI_MATCH         (19 + IH2_BASE)
-#define INT_USB_W2FC            (20 + IH2_BASE)
-#define INT_1WIRE               (21 + IH2_BASE)
-#define INT_OS_TIMER            (22 + IH2_BASE)
-#define INT_MMC                 (23 + IH2_BASE)
-#define INT_GAUGE_32K           (24 + IH2_BASE)
-#define INT_RTC_TIMER           (25 + IH2_BASE)
-#define INT_RTC_ALARM           (26 + IH2_BASE)
-#define INT_MEM_STICK           (27 + IH2_BASE)
-
-/*
- * OMAP-1510 specific IRQ numbers for interrupt handler 2
- */
-#define INT_1510_DSP_MMU        (28 + IH2_BASE)
-#define INT_1510_COM_SPI_RO     (31 + IH2_BASE)
-
-/*
- * OMAP-1610 specific IRQ numbers for interrupt handler 2
- */
-#define INT_1610_FAC            (0 + IH2_BASE)
-#define INT_1610_USB_HHC_2      (7 + IH2_BASE)
-#define INT_1610_USB_OTG        (8 + IH2_BASE)
-#define INT_1610_SoSSI          (9 + IH2_BASE)
-#define INT_1610_SoSSI_MATCH    (19 + IH2_BASE)
-#define INT_1610_DSP_MMU        (28 + IH2_BASE)
-#define INT_1610_McBSP2RX_OF    (31 + IH2_BASE)
-#define INT_1610_STI            (32 + IH2_BASE)
-#define INT_1610_STI_WAKEUP     (33 + IH2_BASE)
-#define INT_1610_GPTIMER3       (34 + IH2_BASE)
-#define INT_1610_GPTIMER4       (35 + IH2_BASE)
-#define INT_1610_GPTIMER5       (36 + IH2_BASE)
-#define INT_1610_GPTIMER6       (37 + IH2_BASE)
-#define INT_1610_GPTIMER7       (38 + IH2_BASE)
-#define INT_1610_GPTIMER8       (39 + IH2_BASE)
-#define INT_1610_GPIO_BANK2     (40 + IH2_BASE)
-#define INT_1610_GPIO_BANK3     (41 + IH2_BASE)
-#define INT_1610_MMC2           (42 + IH2_BASE)
-#define INT_1610_CF             (43 + IH2_BASE)
-#define INT_1610_WAKE_UP_REQ    (46 + IH2_BASE)
-#define INT_1610_GPIO_BANK4     (48 + IH2_BASE)
-#define INT_1610_SPI            (49 + IH2_BASE)
-#define INT_1610_DMA_CH6        (53 + IH2_BASE)
-#define INT_1610_DMA_CH7        (54 + IH2_BASE)
-#define INT_1610_DMA_CH8        (55 + IH2_BASE)
-#define INT_1610_DMA_CH9        (56 + IH2_BASE)
-#define INT_1610_DMA_CH10       (57 + IH2_BASE)
-#define INT_1610_DMA_CH11       (58 + IH2_BASE)
-#define INT_1610_DMA_CH12       (59 + IH2_BASE)
-#define INT_1610_DMA_CH13       (60 + IH2_BASE)
-#define INT_1610_DMA_CH14       (61 + IH2_BASE)
-#define INT_1610_DMA_CH15       (62 + IH2_BASE)
-#define INT_1610_NAND           (63 + IH2_BASE)
-#define INT_1610_SHA1MD5        (91 + IH2_BASE)
-
-/*
- * OMAP-730 specific IRQ numbers for interrupt handler 2
- */
-#define INT_730_HW_ERRORS       (0 + IH2_BASE)
-#define INT_730_NFIQ_PWR_FAIL   (1 + IH2_BASE)
-#define INT_730_CFCD            (2 + IH2_BASE)
-#define INT_730_CFIREQ          (3 + IH2_BASE)
-#define INT_730_I2C             (4 + IH2_BASE)
-#define INT_730_PCC             (5 + IH2_BASE)
-#define INT_730_MPU_EXT_NIRQ    (6 + IH2_BASE)
-#define INT_730_SPI_100K_1      (7 + IH2_BASE)
-#define INT_730_SYREN_SPI       (8 + IH2_BASE)
-#define INT_730_VLYNQ           (9 + IH2_BASE)
-#define INT_730_GPIO_BANK4      (10 + IH2_BASE)
-#define INT_730_McBSP1TX        (11 + IH2_BASE)
-#define INT_730_McBSP1RX        (12 + IH2_BASE)
-#define INT_730_McBSP1RX_OF     (13 + IH2_BASE)
-#define INT_730_UART_MODEM_IRDA_2 (14 + IH2_BASE)
-#define INT_730_UART_MODEM_1    (15 + IH2_BASE)
-#define INT_730_MCSI            (16 + IH2_BASE)
-#define INT_730_uWireTX         (17 + IH2_BASE)
-#define INT_730_uWireRX         (18 + IH2_BASE)
-#define INT_730_SMC_CD          (19 + IH2_BASE)
-#define INT_730_SMC_IREQ        (20 + IH2_BASE)
-#define INT_730_HDQ_1WIRE       (21 + IH2_BASE)
-#define INT_730_TIMER32K        (22 + IH2_BASE)
-#define INT_730_MMC_SDIO        (23 + IH2_BASE)
-#define INT_730_UPLD            (24 + IH2_BASE)
-#define INT_730_USB_HHC_1       (27 + IH2_BASE)
-#define INT_730_USB_HHC_2       (28 + IH2_BASE)
-#define INT_730_USB_GENI        (29 + IH2_BASE)
-#define INT_730_USB_OTG         (30 + IH2_BASE)
-#define INT_730_CAMERA_IF       (31 + IH2_BASE)
-#define INT_730_RNG             (32 + IH2_BASE)
-#define INT_730_DUAL_MODE_TIMER (33 + IH2_BASE)
-#define INT_730_DBB_RF_EN       (34 + IH2_BASE)
-#define INT_730_MPUIO_KEYPAD    (35 + IH2_BASE)
-#define INT_730_SHA1_MD5        (36 + IH2_BASE)
-#define INT_730_SPI_100K_2      (37 + IH2_BASE)
-#define INT_730_RNG_IDLE        (38 + IH2_BASE)
-#define INT_730_MPUIO           (39 + IH2_BASE)
-#define INT_730_LLPC_LCD_CTRL_CAN_BE_OFF        (40 + IH2_BASE)
-#define INT_730_LLPC_OE_FALLING (41 + IH2_BASE)
-#define INT_730_LLPC_OE_RISING  (42 + IH2_BASE)
-#define INT_730_LLPC_VSYNC      (43 + IH2_BASE)
-#define INT_730_WAKE_UP_REQ     (46 + IH2_BASE)
-#define INT_730_DMA_CH6         (53 + IH2_BASE)
-#define INT_730_DMA_CH7         (54 + IH2_BASE)
-#define INT_730_DMA_CH8         (55 + IH2_BASE)
-#define INT_730_DMA_CH9         (56 + IH2_BASE)
-#define INT_730_DMA_CH10        (57 + IH2_BASE)
-#define INT_730_DMA_CH11        (58 + IH2_BASE)
-#define INT_730_DMA_CH12        (59 + IH2_BASE)
-#define INT_730_DMA_CH13        (60 + IH2_BASE)
-#define INT_730_DMA_CH14        (61 + IH2_BASE)
-#define INT_730_DMA_CH15        (62 + IH2_BASE)
-#define INT_730_NAND            (63 + IH2_BASE)
-
-/*
- * OMAP-850 specific IRQ numbers for interrupt handler 2
- */
-#define INT_850_HW_ERRORS       (0 + IH2_BASE)
-#define INT_850_NFIQ_PWR_FAIL   (1 + IH2_BASE)
-#define INT_850_CFCD            (2 + IH2_BASE)
-#define INT_850_CFIREQ          (3 + IH2_BASE)
-#define INT_850_I2C             (4 + IH2_BASE)
-#define INT_850_PCC             (5 + IH2_BASE)
-#define INT_850_MPU_EXT_NIRQ    (6 + IH2_BASE)
-#define INT_850_SPI_100K_1      (7 + IH2_BASE)
-#define INT_850_SYREN_SPI       (8 + IH2_BASE)
-#define INT_850_VLYNQ           (9 + IH2_BASE)
-#define INT_850_GPIO_BANK4      (10 + IH2_BASE)
-#define INT_850_McBSP1TX        (11 + IH2_BASE)
-#define INT_850_McBSP1RX        (12 + IH2_BASE)
-#define INT_850_McBSP1RX_OF     (13 + IH2_BASE)
-#define INT_850_UART_MODEM_IRDA_2 (14 + IH2_BASE)
-#define INT_850_UART_MODEM_1    (15 + IH2_BASE)
-#define INT_850_MCSI            (16 + IH2_BASE)
-#define INT_850_uWireTX         (17 + IH2_BASE)
-#define INT_850_uWireRX         (18 + IH2_BASE)
-#define INT_850_SMC_CD          (19 + IH2_BASE)
-#define INT_850_SMC_IREQ        (20 + IH2_BASE)
-#define INT_850_HDQ_1WIRE       (21 + IH2_BASE)
-#define INT_850_TIMER32K        (22 + IH2_BASE)
-#define INT_850_MMC_SDIO        (23 + IH2_BASE)
-#define INT_850_UPLD            (24 + IH2_BASE)
-#define INT_850_USB_HHC_1       (27 + IH2_BASE)
-#define INT_850_USB_HHC_2       (28 + IH2_BASE)
-#define INT_850_USB_GENI        (29 + IH2_BASE)
-#define INT_850_USB_OTG         (30 + IH2_BASE)
-#define INT_850_CAMERA_IF       (31 + IH2_BASE)
-#define INT_850_RNG             (32 + IH2_BASE)
-#define INT_850_DUAL_MODE_TIMER (33 + IH2_BASE)
-#define INT_850_DBB_RF_EN       (34 + IH2_BASE)
-#define INT_850_MPUIO_KEYPAD    (35 + IH2_BASE)
-#define INT_850_SHA1_MD5        (36 + IH2_BASE)
-#define INT_850_SPI_100K_2      (37 + IH2_BASE)
-#define INT_850_RNG_IDLE        (38 + IH2_BASE)
-#define INT_850_MPUIO           (39 + IH2_BASE)
-#define INT_850_LLPC_LCD_CTRL_CAN_BE_OFF        (40 + IH2_BASE)
-#define INT_850_LLPC_OE_FALLING (41 + IH2_BASE)
-#define INT_850_LLPC_OE_RISING  (42 + IH2_BASE)
-#define INT_850_LLPC_VSYNC      (43 + IH2_BASE)
-#define INT_850_WAKE_UP_REQ     (46 + IH2_BASE)
-#define INT_850_DMA_CH6         (53 + IH2_BASE)
-#define INT_850_DMA_CH7         (54 + IH2_BASE)
-#define INT_850_DMA_CH8         (55 + IH2_BASE)
-#define INT_850_DMA_CH9         (56 + IH2_BASE)
-#define INT_850_DMA_CH10        (57 + IH2_BASE)
-#define INT_850_DMA_CH11        (58 + IH2_BASE)
-#define INT_850_DMA_CH12        (59 + IH2_BASE)
-#define INT_850_DMA_CH13        (60 + IH2_BASE)
-#define INT_850_DMA_CH14        (61 + IH2_BASE)
-#define INT_850_DMA_CH15        (62 + IH2_BASE)
-#define INT_850_NAND            (63 + IH2_BASE)
-
-#define INT_24XX_SYS_NIRQ       7
-#define INT_24XX_SDMA_IRQ0      12
-#define INT_24XX_SDMA_IRQ1      13
-#define INT_24XX_SDMA_IRQ2      14
-#define INT_24XX_SDMA_IRQ3      15
-#define INT_24XX_CAM_IRQ        24
-#define INT_24XX_DSS_IRQ        25
-#define INT_24XX_MAIL_U0_MPU    26
-#define INT_24XX_DSP_UMA        27
-#define INT_24XX_DSP_MMU        28
-#define INT_24XX_GPIO_BANK1     29
-#define INT_24XX_GPIO_BANK2     30
-#define INT_24XX_GPIO_BANK3     31
-#define INT_24XX_GPIO_BANK4     32
-#define INT_24XX_GPIO_BANK5     33
-#define INT_24XX_MAIL_U3_MPU    34
-#define INT_24XX_GPTIMER1       37
-#define INT_24XX_GPTIMER2       38
-#define INT_24XX_GPTIMER3       39
-#define INT_24XX_GPTIMER4       40
-#define INT_24XX_GPTIMER5       41
-#define INT_24XX_GPTIMER6       42
-#define INT_24XX_GPTIMER7       43
-#define INT_24XX_GPTIMER8       44
-#define INT_24XX_GPTIMER9       45
-#define INT_24XX_GPTIMER10      46
-#define INT_24XX_GPTIMER11      47
-#define INT_24XX_GPTIMER12      48
-#define INT_24XX_SHA1MD5        51
-#define INT_24XX_MCBSP4_IRQ_TX  54
-#define INT_24XX_MCBSP4_IRQ_RX  55
-#define INT_24XX_I2C1_IRQ       56
-#define INT_24XX_I2C2_IRQ       57
-#define INT_24XX_HDQ_IRQ        58
-#define INT_24XX_MCBSP1_IRQ_TX  59
-#define INT_24XX_MCBSP1_IRQ_RX  60
-#define INT_24XX_MCBSP2_IRQ_TX  62
-#define INT_24XX_MCBSP2_IRQ_RX  63
-#define INT_24XX_SPI1_IRQ       65
-#define INT_24XX_SPI2_IRQ       66
-#define INT_24XX_UART1_IRQ      72
-#define INT_24XX_UART2_IRQ      73
-#define INT_24XX_UART3_IRQ      74
-#define INT_24XX_USB_IRQ_GEN    75
-#define INT_24XX_USB_IRQ_NISO   76
-#define INT_24XX_USB_IRQ_ISO    77
-#define INT_24XX_USB_IRQ_HGEN   78
-#define INT_24XX_USB_IRQ_HSOF   79
-#define INT_24XX_USB_IRQ_OTG    80
-#define INT_24XX_MCBSP5_IRQ_TX  81
-#define INT_24XX_MCBSP5_IRQ_RX  82
-#define INT_24XX_MMC_IRQ        83
-#define INT_24XX_MMC2_IRQ       86
-#define INT_24XX_MCBSP3_IRQ_TX  89
-#define INT_24XX_MCBSP3_IRQ_RX  90
-#define INT_24XX_SPI3_IRQ       91
-
-#define INT_243X_MCBSP2_IRQ     16
-#define INT_243X_MCBSP3_IRQ     17
-#define INT_243X_MCBSP4_IRQ     18
-#define INT_243X_MCBSP5_IRQ     19
-#define INT_243X_MCBSP1_IRQ     64
-#define INT_243X_HS_USB_MC      92
-#define INT_243X_HS_USB_DMA     93
-#define INT_243X_CARKIT_IRQ     94
-
-#define INT_34XX_BENCH_MPU_EMUL 3
-#define INT_34XX_ST_MCBSP2_IRQ  4
-#define INT_34XX_ST_MCBSP3_IRQ  5
-#define INT_34XX_SSM_ABORT_IRQ  6
-#define INT_34XX_SYS_NIRQ       7
-#define INT_34XX_D2D_FW_IRQ     8
-#define INT_34XX_PRCM_MPU_IRQ   11
-#define INT_34XX_MCBSP1_IRQ     16
-#define INT_34XX_MCBSP2_IRQ     17
-#define INT_34XX_MCBSP3_IRQ     22
-#define INT_34XX_MCBSP4_IRQ     23
-#define INT_34XX_CAM_IRQ        24
-#define INT_34XX_MCBSP5_IRQ     27
-#define INT_34XX_GPIO_BANK1     29
-#define INT_34XX_GPIO_BANK2     30
-#define INT_34XX_GPIO_BANK3     31
-#define INT_34XX_GPIO_BANK4     32
-#define INT_34XX_GPIO_BANK5     33
-#define INT_34XX_GPIO_BANK6     34
-#define INT_34XX_USIM_IRQ       35
-#define INT_34XX_WDT3_IRQ       36
-#define INT_34XX_SPI4_IRQ       48
-#define INT_34XX_SHA1MD52_IRQ   49
-#define INT_34XX_FPKA_READY_IRQ 50
-#define INT_34XX_SHA1MD51_IRQ   51
-#define INT_34XX_RNG_IRQ        52
-#define INT_34XX_I2C3_IRQ       61
-#define INT_34XX_FPKA_ERROR_IRQ 64
-#define INT_34XX_PBIAS_IRQ      75
-#define INT_34XX_OHCI_IRQ       76
-#define INT_34XX_EHCI_IRQ       77
-#define INT_34XX_TLL_IRQ        78
-#define INT_34XX_PARTHASH_IRQ   79
-#define INT_34XX_MMC3_IRQ       94
-#define INT_34XX_GPT12_IRQ      95
-
-#define INT_34XX_BENCH_MPU_EMUL 3
-
-
-#define IRQ_GIC_START           32
-#define INT_44XX_LOCALTIMER_IRQ 29
-#define INT_44XX_LOCALWDT_IRQ   30
-
-#define INT_44XX_BENCH_MPU_EMUL (3 + IRQ_GIC_START)
-#define INT_44XX_SSM_ABORT_IRQ  (6 + IRQ_GIC_START)
-#define INT_44XX_SYS_NIRQ       (7 + IRQ_GIC_START)
-#define INT_44XX_D2D_FW_IRQ     (8 + IRQ_GIC_START)
-#define INT_44XX_PRCM_MPU_IRQ   (11 + IRQ_GIC_START)
-#define INT_44XX_SDMA_IRQ0      (12 + IRQ_GIC_START)
-#define INT_44XX_SDMA_IRQ1      (13 + IRQ_GIC_START)
-#define INT_44XX_SDMA_IRQ2      (14 + IRQ_GIC_START)
-#define INT_44XX_SDMA_IRQ3      (15 + IRQ_GIC_START)
-#define INT_44XX_ISS_IRQ        (24 + IRQ_GIC_START)
-#define INT_44XX_DSS_IRQ        (25 + IRQ_GIC_START)
-#define INT_44XX_MAIL_U0_MPU    (26 + IRQ_GIC_START)
-#define INT_44XX_DSP_MMU        (28 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER1       (37 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER2       (38 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER3       (39 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER4       (40 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER5       (41 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER6       (42 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER7       (43 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER8       (44 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER9       (45 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER10      (46 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER11      (47 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER12      (95 + IRQ_GIC_START)
-#define INT_44XX_SHA1MD5        (51 + IRQ_GIC_START)
-#define INT_44XX_I2C1_IRQ       (56 + IRQ_GIC_START)
-#define INT_44XX_I2C2_IRQ       (57 + IRQ_GIC_START)
-#define INT_44XX_HDQ_IRQ        (58 + IRQ_GIC_START)
-#define INT_44XX_SPI1_IRQ       (65 + IRQ_GIC_START)
-#define INT_44XX_SPI2_IRQ       (66 + IRQ_GIC_START)
-#define INT_44XX_HSI_1_IRQ0     (67 + IRQ_GIC_START)
-#define INT_44XX_HSI_2_IRQ1     (68 + IRQ_GIC_START)
-#define INT_44XX_HSI_1_DMAIRQ   (71 + IRQ_GIC_START)
-#define INT_44XX_UART1_IRQ      (72 + IRQ_GIC_START)
-#define INT_44XX_UART2_IRQ      (73 + IRQ_GIC_START)
-#define INT_44XX_UART3_IRQ      (74 + IRQ_GIC_START)
-#define INT_44XX_UART4_IRQ      (70 + IRQ_GIC_START)
-#define INT_44XX_USB_IRQ_NISO   (76 + IRQ_GIC_START)
-#define INT_44XX_USB_IRQ_ISO    (77 + IRQ_GIC_START)
-#define INT_44XX_USB_IRQ_HGEN   (78 + IRQ_GIC_START)
-#define INT_44XX_USB_IRQ_HSOF   (79 + IRQ_GIC_START)
-#define INT_44XX_USB_IRQ_OTG    (80 + IRQ_GIC_START)
-#define INT_44XX_MCBSP4_IRQ_TX  (81 + IRQ_GIC_START)
-#define INT_44XX_MCBSP4_IRQ_RX  (82 + IRQ_GIC_START)
-#define INT_44XX_MMC_IRQ        (83 + IRQ_GIC_START)
-#define INT_44XX_MMC2_IRQ       (86 + IRQ_GIC_START)
-#define INT_44XX_MCBSP2_IRQ_TX  (89 + IRQ_GIC_START)
-#define INT_44XX_MCBSP2_IRQ_RX  (90 + IRQ_GIC_START)
-#define INT_44XX_SPI3_IRQ       (91 + IRQ_GIC_START)
-#define INT_44XX_SPI5_IRQ       (69 + IRQ_GIC_START)
-
-#define INT_44XX_MCBSP5_IRQ     (16 + IRQ_GIC_START)
-#define INT_44xX_MCBSP1_IRQ     (17 + IRQ_GIC_START)
-#define INT_44XX_MCBSP2_IRQ     (22 + IRQ_GIC_START)
-#define INT_44XX_MCBSP3_IRQ     (23 + IRQ_GIC_START)
-#define INT_44XX_MCBSP4_IRQ     (27 + IRQ_GIC_START)
-#define INT_44XX_HS_USB_MC      (92 + IRQ_GIC_START)
-#define INT_44XX_HS_USB_DMA     (93 + IRQ_GIC_START)
-
-#define INT_44XX_GPIO_BANK1     (29 + IRQ_GIC_START)
-#define INT_44XX_GPIO_BANK2     (30 + IRQ_GIC_START)
-#define INT_44XX_GPIO_BANK3     (31 + IRQ_GIC_START)
-#define INT_44XX_GPIO_BANK4     (32 + IRQ_GIC_START)
-#define INT_44XX_GPIO_BANK5     (33 + IRQ_GIC_START)
-#define INT_44XX_GPIO_BANK6     (34 + IRQ_GIC_START)
-#define INT_44XX_USIM_IRQ       (35 + IRQ_GIC_START)
-#define INT_44XX_WDT3_IRQ       (36 + IRQ_GIC_START)
-#define INT_44XX_SPI4_IRQ       (48 + IRQ_GIC_START)
-#define INT_44XX_SHA1MD52_IRQ   (49 + IRQ_GIC_START)
-#define INT_44XX_FPKA_READY_IRQ (50 + IRQ_GIC_START)
-#define INT_44XX_SHA1MD51_IRQ   (51 + IRQ_GIC_START)
-#define INT_44XX_RNG_IRQ        (52 + IRQ_GIC_START)
-#define INT_44XX_MMC5_IRQ       (59 + IRQ_GIC_START)
-#define INT_44XX_I2C3_IRQ       (61 + IRQ_GIC_START)
-#define INT_44XX_FPKA_ERROR_IRQ (64 + IRQ_GIC_START)
-#define INT_44XX_PBIAS_IRQ      (75 + IRQ_GIC_START)
-#define INT_44XX_OHCI_IRQ       (76 + IRQ_GIC_START)
-#define INT_44XX_EHCI_IRQ       (77 + IRQ_GIC_START)
-#define INT_44XX_TLL_IRQ        (78 + IRQ_GIC_START)
-#define INT_44XX_PARTHASH_IRQ   (79 + IRQ_GIC_START)
-#define INT_44XX_MMC3_IRQ       (94 + IRQ_GIC_START)
-#define INT_44XX_MMC4_IRQ       (96 + IRQ_GIC_START)
-
-
-/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
- * 16 MPUIO lines */
-#define OMAP_MAX_GPIO_LINES     192
-#define IH_GPIO_BASE            (128 + IH2_BASE)
-#define IH_MPUIO_BASE           (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
-#define OMAP_IRQ_END            (IH_MPUIO_BASE + 16)
-
-/* External FPGA handles interrupts on Innovator boards */
-#define OMAP_FPGA_IRQ_BASE      (OMAP_IRQ_END)
-#ifdef  CONFIG_MACH_OMAP_INNOVATOR
-#define OMAP_FPGA_NR_IRQS       24
-#else
-#define OMAP_FPGA_NR_IRQS       0
-#endif
-#define OMAP_FPGA_IRQ_END       (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
-
-/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
-#define TWL4030_IRQ_BASE        (OMAP_FPGA_IRQ_END)
-#ifdef  CONFIG_TWL4030_CORE
-#define TWL4030_BASE_NR_IRQS    8
-#define TWL4030_PWR_NR_IRQS     8
-#else
-#define TWL4030_BASE_NR_IRQS    0
-#define TWL4030_PWR_NR_IRQS     0
-#endif
-#define TWL4030_IRQ_END         (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
-#define TWL4030_PWR_IRQ_BASE    TWL4030_IRQ_END
-#define TWL4030_PWR_IRQ_END     (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
-
-/* External TWL4030 gpio interrupts are optional */
-#define TWL4030_GPIO_IRQ_BASE   TWL4030_PWR_IRQ_END
-#ifdef  CONFIG_GPIO_TWL4030
-#define TWL4030_GPIO_NR_IRQS    18
-#else
-#define TWL4030_GPIO_NR_IRQS    0
-#endif
-#define TWL4030_GPIO_IRQ_END    (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
-
-/* Total number of interrupts depends on the enabled blocks above */
-#define NR_IRQS                 TWL4030_GPIO_IRQ_END
-
-#define OMAP_IRQ_BIT(irq)       (1 << ((irq) % 32))
-
-#ifndef __ASSEMBLY__
-extern void omap_init_irq(void);
-extern int omap_irq_pending(void);
-#endif
-
-#include <mach/hardware.h>
-
-#endif
diff --git a/arch/arm/plat-omap/include/mach/mtd-xip.h b/arch/arm/plat-omap/include/mach/mtd-xip.h
deleted file mode 100644
index f82a8dcaad94..000000000000
--- a/arch/arm/plat-omap/include/mach/mtd-xip.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * MTD primitives for XIP support. Architecture specific functions.
- *
- * Do not include this file directly. It's included from linux/mtd/xip.h
- *
- * Author: Vladimir Barinov <vbarinov@embeddedalley.com>
- *
- * (c) 2005 MontaVista Software, Inc.  This file is licensed under the
- * terms of the GNU General Public License version 2.  This program is
- * licensed "as is" without any warranty of any kind, whether express or
- * implied.
- */
-
-#ifndef __ARCH_OMAP_MTD_XIP_H__
-#define __ARCH_OMAP_MTD_XIP_H__
-
-#include <mach/hardware.h>
-#define OMAP_MPU_TIMER_BASE     (0xfffec500)
-#define OMAP_MPU_TIMER_OFFSET   0x100
-
-typedef struct {
-        u32 cntl;                       /* CNTL_TIMER, R/W */
-        u32 load_tim;                   /* LOAD_TIM,   W */
-        u32 read_tim;                   /* READ_TIM,   R */
-} xip_omap_mpu_timer_regs_t;
-
-#define xip_omap_mpu_timer_base(n)                                      \
-((volatile xip_omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE +    \
-        (n)*OMAP_MPU_TIMER_OFFSET))
-
-static inline unsigned long xip_omap_mpu_timer_read(int nr)
-{
-        volatile xip_omap_mpu_timer_regs_t* timer = xip_omap_mpu_timer_base(nr);
-        return timer->read_tim;
-}
-
-#define xip_irqpending()        \
-        (omap_readl(OMAP_IH1_ITR) & ~omap_readl(OMAP_IH1_MIR))
-#define xip_currtime()          (~xip_omap_mpu_timer_read(0))
-
-/*
- * It's permitted to do approxmation for xip_elapsed_since macro
- * (see linux/mtd/xip.h)
- */
-
-#ifdef CONFIG_MACH_OMAP_PERSEUS2
-#define xip_elapsed_since(x)    (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 7)
-#else
-#define xip_elapsed_since(x)    (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 6)
-#endif
-
-/*
- * xip_cpu_idle() is used when waiting for a delay equal or larger than
- * the system timer tick period.  This should put the CPU into idle mode
- * to save power and to be woken up only when some interrupts are pending.
- * As above, this should not rely upon standard kernel code.
- */
-
-#define xip_cpu_idle()  asm volatile ("mcr p15, 0, %0, c7, c0, 4" :: "r" (1))
-
-#endif /* __ARCH_OMAP_MTD_XIP_H__ */
diff --git a/arch/arm/plat-omap/include/mach/omapfb.h b/arch/arm/plat-omap/include/mach/omapfb.h
deleted file mode 100644
index b226bdf45739..000000000000
--- a/arch/arm/plat-omap/include/mach/omapfb.h
+++ /dev/null
@@ -1,398 +0,0 @@
-/*
- * File: arch/arm/plat-omap/include/mach/omapfb.h
- *
- * Framebuffer driver for TI OMAP boards
- *
- * Copyright (C) 2004 Nokia Corporation
- * Author: Imre Deak <imre.deak@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
- */
-
-#ifndef __OMAPFB_H
-#define __OMAPFB_H
-
-#include <asm/ioctl.h>
-#include <asm/types.h>
-
-/* IOCTL commands. */
-
-#define OMAP_IOW(num, dtype)    _IOW('O', num, dtype)
-#define OMAP_IOR(num, dtype)    _IOR('O', num, dtype)
-#define OMAP_IOWR(num, dtype)   _IOWR('O', num, dtype)
-#define OMAP_IO(num)            _IO('O', num)
-
-#define OMAPFB_MIRROR           OMAP_IOW(31, int)
-#define OMAPFB_SYNC_GFX         OMAP_IO(37)
-#define OMAPFB_VSYNC            OMAP_IO(38)
-#define OMAPFB_SET_UPDATE_MODE  OMAP_IOW(40, int)
-#define OMAPFB_GET_CAPS         OMAP_IOR(42, struct omapfb_caps)
-#define OMAPFB_GET_UPDATE_MODE  OMAP_IOW(43, int)
-#define OMAPFB_LCD_TEST         OMAP_IOW(45, int)
-#define OMAPFB_CTRL_TEST        OMAP_IOW(46, int)
-#define OMAPFB_UPDATE_WINDOW_OLD OMAP_IOW(47, struct omapfb_update_window_old)
-#define OMAPFB_SET_COLOR_KEY    OMAP_IOW(50, struct omapfb_color_key)
-#define OMAPFB_GET_COLOR_KEY    OMAP_IOW(51, struct omapfb_color_key)
-#define OMAPFB_SETUP_PLANE      OMAP_IOW(52, struct omapfb_plane_info)
-#define OMAPFB_QUERY_PLANE      OMAP_IOW(53, struct omapfb_plane_info)
-#define OMAPFB_UPDATE_WINDOW    OMAP_IOW(54, struct omapfb_update_window)
-#define OMAPFB_SETUP_MEM        OMAP_IOW(55, struct omapfb_mem_info)
-#define OMAPFB_QUERY_MEM        OMAP_IOW(56, struct omapfb_mem_info)
-
-#define OMAPFB_CAPS_GENERIC_MASK        0x00000fff
-#define OMAPFB_CAPS_LCDC_MASK           0x00fff000
-#define OMAPFB_CAPS_PANEL_MASK          0xff000000
-
-#define OMAPFB_CAPS_MANUAL_UPDATE       0x00001000
-#define OMAPFB_CAPS_TEARSYNC            0x00002000
-#define OMAPFB_CAPS_PLANE_RELOCATE_MEM  0x00004000
-#define OMAPFB_CAPS_PLANE_SCALE         0x00008000
-#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE 0x00010000
-#define OMAPFB_CAPS_WINDOW_SCALE        0x00020000
-#define OMAPFB_CAPS_WINDOW_OVERLAY      0x00040000
-#define OMAPFB_CAPS_WINDOW_ROTATE       0x00080000
-#define OMAPFB_CAPS_SET_BACKLIGHT       0x01000000
-
-/* Values from DSP must map to lower 16-bits */
-#define OMAPFB_FORMAT_MASK              0x00ff
-#define OMAPFB_FORMAT_FLAG_DOUBLE       0x0100
-#define OMAPFB_FORMAT_FLAG_TEARSYNC     0x0200
-#define OMAPFB_FORMAT_FLAG_FORCE_VSYNC  0x0400
-#define OMAPFB_FORMAT_FLAG_ENABLE_OVERLAY       0x0800
-#define OMAPFB_FORMAT_FLAG_DISABLE_OVERLAY      0x1000
-
-#define OMAPFB_EVENT_READY      1
-#define OMAPFB_EVENT_DISABLED   2
-
-#define OMAPFB_MEMTYPE_SDRAM            0
-#define OMAPFB_MEMTYPE_SRAM             1
-#define OMAPFB_MEMTYPE_MAX              1
-
-enum omapfb_color_format {
-        OMAPFB_COLOR_RGB565 = 0,
-        OMAPFB_COLOR_YUV422,
-        OMAPFB_COLOR_YUV420,
-        OMAPFB_COLOR_CLUT_8BPP,
-        OMAPFB_COLOR_CLUT_4BPP,
-        OMAPFB_COLOR_CLUT_2BPP,
-        OMAPFB_COLOR_CLUT_1BPP,
-        OMAPFB_COLOR_RGB444,
-        OMAPFB_COLOR_YUY422,
-};
-
-struct omapfb_update_window {
-        __u32 x, y;
-        __u32 width, height;
-        __u32 format;
-        __u32 out_x, out_y;
-        __u32 out_width, out_height;
-        __u32 reserved[8];
-};
-
-struct omapfb_update_window_old {
-        __u32 x, y;
-        __u32 width, height;
-        __u32 format;
-};
-
-enum omapfb_plane {
-        OMAPFB_PLANE_GFX = 0,
-        OMAPFB_PLANE_VID1,
-        OMAPFB_PLANE_VID2,
-};
-
-enum omapfb_channel_out {
-        OMAPFB_CHANNEL_OUT_LCD = 0,
-        OMAPFB_CHANNEL_OUT_DIGIT,
-};
-
-struct omapfb_plane_info {
-        __u32 pos_x;
-        __u32 pos_y;
-        __u8  enabled;
-        __u8  channel_out;
-        __u8  mirror;
-        __u8  reserved1;
-        __u32 out_width;
-        __u32 out_height;
-        __u32 reserved2[12];
-};
-
-struct omapfb_mem_info {
-        __u32 size;
-        __u8  type;
-        __u8  reserved[3];
-};
-
-struct omapfb_caps {
-        __u32 ctrl;
-        __u32 plane_color;
-        __u32 wnd_color;
-};
-
-enum omapfb_color_key_type {
-        OMAPFB_COLOR_KEY_DISABLED = 0,
-        OMAPFB_COLOR_KEY_GFX_DST,
-        OMAPFB_COLOR_KEY_VID_SRC,
-};
-
-struct omapfb_color_key {
-        __u8  channel_out;
-        __u32 background;
-        __u32 trans_key;
-        __u8  key_type;
-};
-
-enum omapfb_update_mode {
-        OMAPFB_UPDATE_DISABLED = 0,
-        OMAPFB_AUTO_UPDATE,
-        OMAPFB_MANUAL_UPDATE
-};
-
-#ifdef __KERNEL__
-
-#include <linux/completion.h>
-#include <linux/interrupt.h>
-#include <linux/fb.h>
-#include <linux/mutex.h>
-
-#include <mach/board.h>
-
-#define OMAP_LCDC_INV_VSYNC             0x0001
-#define OMAP_LCDC_INV_HSYNC             0x0002
-#define OMAP_LCDC_INV_PIX_CLOCK         0x0004
-#define OMAP_LCDC_INV_OUTPUT_EN         0x0008
-#define OMAP_LCDC_HSVS_RISING_EDGE      0x0010
-#define OMAP_LCDC_HSVS_OPPOSITE         0x0020
-
-#define OMAP_LCDC_SIGNAL_MASK           0x003f
-
-#define OMAP_LCDC_PANEL_TFT             0x0100
-
-#define OMAPFB_PLANE_XRES_MIN           8
-#define OMAPFB_PLANE_YRES_MIN           8
-
-#ifdef CONFIG_ARCH_OMAP1
-#define OMAPFB_PLANE_NUM                1
-#else
-#define OMAPFB_PLANE_NUM                3
-#endif
-
-struct omapfb_device;
-
-struct lcd_panel {
-        const char      *name;
-        int             config;         /* TFT/STN, signal inversion */
-        int             bpp;            /* Pixel format in fb mem */
-        int             data_lines;     /* Lines on LCD HW interface */
-
-        int             x_res, y_res;
-        int             pixel_clock;    /* In kHz */
-        int             hsw;            /* Horizontal synchronization
-                                           pulse width */
-        int             hfp;            /* Horizontal front porch */
-        int             hbp;            /* Horizontal back porch */
-        int             vsw;            /* Vertical synchronization
-                                           pulse width */
-        int             vfp;            /* Vertical front porch */
-        int             vbp;            /* Vertical back porch */
-        int             acb;            /* ac-bias pin frequency */
-        int             pcd;            /* pixel clock divider.
-                                           Obsolete use pixel_clock instead */
-
-        int             (*init)         (struct lcd_panel *panel,
-                                         struct omapfb_device *fbdev);
-        void            (*cleanup)      (struct lcd_panel *panel);
-        int             (*enable)       (struct lcd_panel *panel);
-        void            (*disable)      (struct lcd_panel *panel);
-        unsigned long   (*get_caps)     (struct lcd_panel *panel);
-        int             (*set_bklight_level)(struct lcd_panel *panel,
-                                             unsigned int level);
-        unsigned int    (*get_bklight_level)(struct lcd_panel *panel);
-        unsigned int    (*get_bklight_max)  (struct lcd_panel *panel);
-        int             (*run_test)     (struct lcd_panel *panel, int test_num);
-};
-
-struct extif_timings {
-        int cs_on_time;
-        int cs_off_time;
-        int we_on_time;
-        int we_off_time;
-        int re_on_time;
-        int re_off_time;
-        int we_cycle_time;
-        int re_cycle_time;
-        int cs_pulse_width;
-        int access_time;
-
-        int clk_div;
-
-        u32 tim[5];             /* set by extif->convert_timings */
-
-        int converted;
-};
-
-struct lcd_ctrl_extif {
-        int  (*init)            (struct omapfb_device *fbdev);
-        void (*cleanup)         (void);
-        void (*get_clk_info)    (u32 *clk_period, u32 *max_clk_div);
-        unsigned long (*get_max_tx_rate)(void);
-        int  (*convert_timings) (struct extif_timings *timings);
-        void (*set_timings)     (const struct extif_timings *timings);
-        void (*set_bits_per_cycle)(int bpc);
-        void (*write_command)   (const void *buf, unsigned int len);
-        void (*read_data)       (void *buf, unsigned int len);
-        void (*write_data)      (const void *buf, unsigned int len);
-        void (*transfer_area)   (int width, int height,
-                                 void (callback)(void * data), void *data);
-        int  (*setup_tearsync)  (unsigned pin_cnt,
-                                 unsigned hs_pulse_time, unsigned vs_pulse_time,
-                                 int hs_pol_inv, int vs_pol_inv, int div);
-        int  (*enable_tearsync) (int enable, unsigned line);
-
-        unsigned long           max_transmit_size;
-};
-
-struct omapfb_notifier_block {
-        struct notifier_block   nb;
-        void                    *data;
-        int                     plane_idx;
-};
-
-typedef int (*omapfb_notifier_callback_t)(struct notifier_block *,
-                                          unsigned long event,
-                                          void *fbi);
-
-struct omapfb_mem_region {
-        u32             paddr;
-        void __iomem    *vaddr;
-        unsigned long   size;
-        u8              type;           /* OMAPFB_PLANE_MEM_* */
-        unsigned        alloc:1;        /* allocated by the driver */
-        unsigned        map:1;          /* kernel mapped by the driver */
-};
-
-struct omapfb_mem_desc {
-        int                             region_cnt;
-        struct omapfb_mem_region        region[OMAPFB_PLANE_NUM];
-};
-
-struct lcd_ctrl {
-        const char      *name;
-        void            *data;
-
-        int             (*init)           (struct omapfb_device *fbdev,
-                                           int ext_mode,
-                                           struct omapfb_mem_desc *req_md);
-        void            (*cleanup)        (void);
-        void            (*bind_client)    (struct omapfb_notifier_block *nb);
-        void            (*get_caps)       (int plane, struct omapfb_caps *caps);
-        int             (*set_update_mode)(enum omapfb_update_mode mode);
-        enum omapfb_update_mode (*get_update_mode)(void);
-        int             (*setup_plane)    (int plane, int channel_out,
-                                           unsigned long offset,
-                                           int screen_width,
-                                           int pos_x, int pos_y, int width,
-                                           int height, int color_mode);
-        int             (*set_rotate)     (int angle);
-        int             (*setup_mem)      (int plane, size_t size,
-                                           int mem_type, unsigned long *paddr);
-        int             (*mmap)           (struct fb_info *info,
-                                           struct vm_area_struct *vma);
-        int             (*set_scale)      (int plane,
-                                           int orig_width, int orig_height,
-                                           int out_width, int out_height);
-        int             (*enable_plane)   (int plane, int enable);
-        int             (*update_window)  (struct fb_info *fbi,
-                                           struct omapfb_update_window *win,
-                                           void (*callback)(void *),
-                                           void *callback_data);
-        void            (*sync)           (void);
-        void            (*suspend)        (void);
-        void            (*resume)         (void);
-        int             (*run_test)       (int test_num);
-        int             (*setcolreg)      (u_int regno, u16 red, u16 green,
-                                           u16 blue, u16 transp,
-                                           int update_hw_mem);
-        int             (*set_color_key)  (struct omapfb_color_key *ck);
-        int             (*get_color_key)  (struct omapfb_color_key *ck);
-};
-
-enum omapfb_state {
-        OMAPFB_DISABLED = 0,
-        OMAPFB_SUSPENDED= 99,
-        OMAPFB_ACTIVE   = 100
-};
-
-struct omapfb_plane_struct {
-        int                             idx;
-        struct omapfb_plane_info        info;
-        enum omapfb_color_format        color_mode;
-        struct omapfb_device            *fbdev;
-};
-
-struct omapfb_device {
-        int                     state;
-        int                     ext_lcdc;               /* Using external
-                                                           LCD controller */
-        struct mutex            rqueue_mutex;
-
-        int                     palette_size;
-        u32                     pseudo_palette[17];
-
-        struct lcd_panel        *panel;                 /* LCD panel */
-        const struct lcd_ctrl   *ctrl;                  /* LCD controller */
-        const struct lcd_ctrl   *int_ctrl;              /* internal LCD ctrl */
-        struct lcd_ctrl_extif   *ext_if;                /* LCD ctrl external
-                                                           interface */
-        struct device           *dev;
-        struct fb_var_screeninfo        new_var;        /* for mode changes */
-
-        struct omapfb_mem_desc          mem_desc;
-        struct fb_info                  *fb_info[OMAPFB_PLANE_NUM];
-};
-
-struct omapfb_platform_data {
-        struct omap_lcd_config          lcd;
-        struct omapfb_mem_desc          mem_desc;
-        void                            *ctrl_platform_data;
-};
-
-#ifdef CONFIG_ARCH_OMAP1
-extern struct lcd_ctrl omap1_lcd_ctrl;
-#else
-extern struct lcd_ctrl omap2_disp_ctrl;
-#endif
-
-extern void omapfb_reserve_sdram(void);
-extern void omapfb_register_panel(struct lcd_panel *panel);
-extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
-extern void omapfb_notify_clients(struct omapfb_device *fbdev,
-                                  unsigned long event);
-extern int  omapfb_register_client(struct omapfb_notifier_block *nb,
-                                   omapfb_notifier_callback_t callback,
-                                   void *callback_data);
-extern int  omapfb_unregister_client(struct omapfb_notifier_block *nb);
-extern int  omapfb_update_window_async(struct fb_info *fbi,
-                                       struct omapfb_update_window *win,
-                                       void (*callback)(void *),
-                                       void *callback_data);
-
-/* in arch/arm/plat-omap/fb.c */
-extern void omapfb_set_ctrl_platform_data(void *pdata);
-
-#endif /* __KERNEL__ */
-
-#endif /* __OMAPFB_H */
diff --git a/arch/arm/plat-omap/include/mach/serial.h b/arch/arm/plat-omap/include/mach/serial.h
deleted file mode 100644
index e249186d26e2..000000000000
--- a/arch/arm/plat-omap/include/mach/serial.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/serial.h
- *
- * Copyright (C) 2009 Texas Instruments
- * Addded OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARCH_SERIAL_H
-#define __ASM_ARCH_SERIAL_H
-
-#include <linux/init.h>
-
-#if defined(CONFIG_ARCH_OMAP1)
-/* OMAP1 serial ports */
-#define OMAP_UART1_BASE         0xfffb0000
-#define OMAP_UART2_BASE         0xfffb0800
-#define OMAP_UART3_BASE         0xfffb9800
-#define OMAP_MAX_NR_PORTS       3
-#elif defined(CONFIG_ARCH_OMAP2)
-/* OMAP2 serial ports */
-#define OMAP_UART1_BASE         0x4806a000
-#define OMAP_UART2_BASE         0x4806c000
-#define OMAP_UART3_BASE         0x4806e000
-#define OMAP_MAX_NR_PORTS       3
-#elif defined(CONFIG_ARCH_OMAP3)
-/* OMAP3 serial ports */
-#define OMAP_UART1_BASE         0x4806a000
-#define OMAP_UART2_BASE         0x4806c000
-#define OMAP_UART3_BASE         0x49020000
-#define OMAP_MAX_NR_PORTS       3
-#elif defined(CONFIG_ARCH_OMAP4)
-/* OMAP4 serial ports */
-#define OMAP_UART1_BASE         0x4806a000
-#define OMAP_UART2_BASE         0x4806c000
-#define OMAP_UART3_BASE         0x48020000
-#define OMAP_UART4_BASE         0x4806e000
-#define OMAP_MAX_NR_PORTS       4
-#endif
-
-#define OMAP1510_BASE_BAUD      (12000000/16)
-#define OMAP16XX_BASE_BAUD      (48000000/16)
-#define OMAP24XX_BASE_BAUD      (48000000/16)
-
-#define is_omap_port(pt)        ({int __ret = 0;                        \
-                        if ((pt)->port.mapbase == OMAP_UART1_BASE ||    \
-                            (pt)->port.mapbase == OMAP_UART2_BASE ||    \
-                            (pt)->port.mapbase == OMAP_UART3_BASE)      \
-                                __ret = 1;                              \
-                        __ret;                                          \
-                        })
-
-#ifndef __ASSEMBLER__
-extern void __init omap_serial_early_init(void);
-extern void omap_serial_init(void);
-extern int omap_uart_can_sleep(void);
-extern void omap_uart_check_wakeup(void);
-extern void omap_uart_prepare_suspend(void);
-extern void omap_uart_prepare_idle(int num);
-extern void omap_uart_resume_idle(int num);
-extern void omap_uart_enable_irqs(int enable);
-#endif
-
-#endif
diff --git a/arch/arm/plat-omap/include/mach/uncompress.h b/arch/arm/plat-omap/include/mach/uncompress.h
deleted file mode 100644
index 0814c5f210c3..000000000000
--- a/arch/arm/plat-omap/include/mach/uncompress.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/uncompress.h
- *
- * Serial port stubs for kernel decompress status messages
- *
- * Initially based on:
- * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h
- * Copyright (C) 2000 RidgeRun, Inc.
- * Author: Greg Lonnon <glonnon@ridgerun.com>
- *
- * Rewritten by:
- * Author: <source@mvista.com>
- * 2004 (c) MontaVista Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/types.h>
-#include <linux/serial_reg.h>
-#include <mach/serial.h>
-
-unsigned int system_rev;
-
-#define UART_OMAP_MDR1          0x08    /* mode definition register */
-#define OMAP_ID_730             0x355F
-#define ID_MASK                 0x7fff
-#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
-#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK
-
-static void putc(int c)
-{
-        volatile u8 * uart = 0;
-        int shift = 2;
-
-#ifdef CONFIG_MACH_OMAP_PALMTE
-        return;
-#endif
-
-#ifdef CONFIG_ARCH_OMAP
-#ifdef  CONFIG_OMAP_LL_DEBUG_UART3
-        uart = (volatile u8 *)(OMAP_UART3_BASE);
-#elif defined(CONFIG_OMAP_LL_DEBUG_UART2)
-        uart = (volatile u8 *)(OMAP_UART2_BASE);
-#else
-        uart = (volatile u8 *)(OMAP_UART1_BASE);
-#endif
-
-#ifdef CONFIG_ARCH_OMAP1
-        /* Determine which serial port to use */
-        do {
-                /* MMU is not on, so cpu_is_omapXXXX() won't work here */
-                unsigned int omap_id = omap_get_id();
-
-                if (omap_id == OMAP_ID_730)
-                        shift = 0;
-
-                if (check_port(uart, shift))
-                        break;
-                /* Silent boot if no serial ports are enabled. */
-                return;
-        } while (0);
-#endif /* CONFIG_ARCH_OMAP1 */
-#endif
-
-        /*
-         * Now, xmit each character
-         */
-        while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
-                barrier();
-        uart[UART_TX << shift] = c;
-}
-
-static inline void flush(void)
-{
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/plat-omap/include/mach/vmalloc.h b/arch/arm/plat-omap/include/mach/vmalloc.h
deleted file mode 100644
index b97dfafeebda..000000000000
--- a/arch/arm/plat-omap/include/mach/vmalloc.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- *  arch/arm/plat-omap/include/mach/vmalloc.h
- *
- *  Copyright (C) 2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define VMALLOC_END       (PAGE_OFFSET + 0x18000000)
-
diff --git a/arch/arm/plat-omap/include/mach/blizzard.h b/arch/arm/plat-omap/include/plat/blizzard.h
index 8d160f171372..56e7f2e7d12f 100644
--- a/arch/arm/plat-omap/include/mach/blizzard.h
+++ b/arch/arm/plat-omap/include/plat/blizzard.h
@@ -6,7 +6,7 @@ struct blizzard_platform_data {
         void            (*power_down)(struct device *dev);
         unsigned long   (*get_clock_rate)(struct device *dev);
 
-        unsigned        te_connected : 1;
+        unsigned        te_connected:1;
 };
 
 #endif
diff --git a/arch/arm/plat-omap/include/mach/board-ams-delta.h b/arch/arm/plat-omap/include/plat/board-ams-delta.h
index 51b102dc906b..51b102dc906b 100644
--- a/arch/arm/plat-omap/include/mach/board-ams-delta.h
+++ b/arch/arm/plat-omap/include/plat/board-ams-delta.h
diff --git a/arch/arm/plat-omap/include/mach/board-sx1.h b/arch/arm/plat-omap/include/plat/board-sx1.h
index 355adbdaae33..355adbdaae33 100644
--- a/arch/arm/plat-omap/include/mach/board-sx1.h
+++ b/arch/arm/plat-omap/include/plat/board-sx1.h
diff --git a/arch/arm/plat-omap/include/mach/board-voiceblue.h b/arch/arm/plat-omap/include/plat/board-voiceblue.h
index 27916b210f57..27916b210f57 100644
--- a/arch/arm/plat-omap/include/mach/board-voiceblue.h
+++ b/arch/arm/plat-omap/include/plat/board-voiceblue.h
diff --git a/arch/arm/plat-omap/include/mach/board.h b/arch/arm/plat-omap/include/plat/board.h
index 8e913c322810..5cd622039da0 100644
--- a/arch/arm/plat-omap/include/mach/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -12,7 +12,19 @@
 
 #include <linux/types.h>
 
-#include <mach/gpio-switch.h>
+#include <plat/gpio-switch.h>
+
+/*
+ * OMAP35x EVM revision
+ * Run time detection of EVM revision is done by reading Ethernet
+ * PHY ID -
+ *      GEN_1   = 0x01150000
+ *      GEN_2   = 0x92200000
+ */
+enum {
+        OMAP3EVM_BOARD_GEN_1 = 0,       /* EVM Rev between  A - D */
+        OMAP3EVM_BOARD_GEN_2,           /* EVM Rev >= Rev E */
+};
 
 /* Different peripheral ids */
 #define OMAP_TAG_CLOCK          0x4f01
@@ -87,7 +99,6 @@ struct fb_info;
 struct omap_backlight_config {
         int default_intensity;
         int (*set_power)(struct device *dev, int state);
-        int (*check_fb)(struct fb_info *fb);
 };
 
 struct omap_fbmem_config {
@@ -102,15 +113,6 @@ struct omap_pwm_led_platform_data {
         void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
 };
 
-/* See arch/arm/plat-omap/include/mach/gpio-switch.h for definitions */
-struct omap_gpio_switch_config {
-        char name[12];
-        u16 gpio;
-        int flags:4;
-        int type:4;
-        int key_code:24; /* Linux key code */
-};
-
 struct omap_uart_config {
         /* Bit field of UARTs present; bit 0 --> UART1 */
         unsigned int enabled_uarts;
@@ -157,4 +159,10 @@ extern int omap_board_config_size;
 /* for TI reference platforms sharing the same debug card */
 extern int debug_card_init(u32 addr, unsigned gpio);
 
+/* OMAP3EVM revision */
+#if defined(CONFIG_MACH_OMAP3EVM)
+u8 get_omap3_evm_rev(void);
+#else
+#define get_omap3_evm_rev() (-EINVAL)
+#endif
 #endif
diff --git a/arch/arm/plat-omap/include/mach/clkdev.h b/arch/arm/plat-omap/include/plat/clkdev.h
index 730c49d1ebd8..730c49d1ebd8 100644
--- a/arch/arm/plat-omap/include/mach/clkdev.h
+++ b/arch/arm/plat-omap/include/plat/clkdev.h
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
new file mode 100644
index 000000000000..bb937f3fabed
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -0,0 +1,49 @@
+/*
+ * clkdev <-> OMAP integration
+ *
+ * Russell King <linux@arm.linux.org.uk>
+ *
+ */
+
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
+
+#include <asm/clkdev.h>
+
+struct omap_clk {
+        u16                             cpu;
+        struct clk_lookup               lk;
+};
+
+#define CLK(dev, con, ck, cp)           \
+        {                               \
+                 .cpu = cp,             \
+                .lk = {                 \
+                        .dev_id = dev,  \
+                        .con_id = con,  \
+                        .clk = ck,      \
+                },                      \
+        }
+
+/* Platform flags for the clkdev-OMAP integration code */
+#define CK_310          (1 << 0)
+#define CK_7XX          (1 << 1)        /* 7xx, 850 */
+#define CK_1510         (1 << 2)
+#define CK_16XX         (1 << 3)        /* 16xx, 17xx, 5912 */
+#define CK_242X         (1 << 4)
+#define CK_243X         (1 << 5)
+#define CK_3XXX         (1 << 6)        /* OMAP3 + AM3 common clocks*/
+#define CK_343X         (1 << 7)        /* OMAP34xx common clocks */
+#define CK_3430ES1      (1 << 8)        /* 34xxES1 only */
+#define CK_3430ES2      (1 << 9)        /* 34xxES2, ES3, non-Sitara 35xx only */
+#define CK_3505         (1 << 10)
+#define CK_3517         (1 << 11)
+#define CK_36XX         (1 << 12)       /* OMAP36xx/37xx-specific clocks */
+#define CK_443X         (1 << 13)
+
+#define CK_AM35XX       (CK_3505 | CK_3517)     /* all Sitara AM35xx */
+
+
+
+#endif
+
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
new file mode 100644
index 000000000000..34f7fa9ad4c0
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -0,0 +1,210 @@
+/*
+ * OMAP clock: data structure definitions, function prototypes, shared macros
+ *
+ * Copyright (C) 2004-2005, 2008-2010 Nokia Corporation
+ * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
+ * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_OMAP_CLOCK_H
+#define __ARCH_ARM_OMAP_CLOCK_H
+
+#include <linux/list.h>
+
+struct module;
+struct clk;
+struct clockdomain;
+
+struct clkops {
+        int                     (*enable)(struct clk *);
+        void                    (*disable)(struct clk *);
+        void                    (*find_idlest)(struct clk *, void __iomem **,
+                                               u8 *, u8 *);
+        void                    (*find_companion)(struct clk *, void __iomem **,
+                                                  u8 *);
+};
+
+#ifdef CONFIG_ARCH_OMAP2PLUS
+
+struct clksel_rate {
+        u32                     val;
+        u8                      div;
+        u8                      flags;
+};
+
+struct clksel {
+        struct clk               *parent;
+        const struct clksel_rate *rates;
+};
+
+/**
+ * struct dpll_data - DPLL registers and integration data
+ * @mult_div1_reg: register containing the DPLL M and N bitfields
+ * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
+ * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
+ * @clk_bypass: struct clk pointer to the clock's bypass clock input
+ * @clk_ref: struct clk pointer to the clock's reference clock input
+ * @control_reg: register containing the DPLL mode bitfield
+ * @enable_mask: mask of the DPLL mode bitfield in @control_reg
+ * @rate_tolerance: maximum variance allowed from target rate (in Hz)
+ * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
+ * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
+ * @max_multiplier: maximum valid non-bypass multiplier value (actual)
+ * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
+ * @min_divider: minimum valid non-bypass divider value (actual)
+ * @max_divider: maximum valid non-bypass divider value (actual)
+ * @modes: possible values of @enable_mask
+ * @autoidle_reg: register containing the DPLL autoidle mode bitfield
+ * @idlest_reg: register containing the DPLL idle status bitfield
+ * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
+ * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
+ * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
+ * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
+ * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
+ * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
+ * @flags: DPLL type/features (see below)
+ *
+ * Possible values for @flags:
+ * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
+ * NO_DCO_SEL: don't program DCO (only for some J-type DPLLs)
+
+ * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
+ *
+ * XXX Some DPLLs have multiple bypass inputs, so it's not technically
+ * correct to only have one @clk_bypass pointer.
+ *
+ * XXX @rate_tolerance should probably be deprecated - currently there
+ * don't seem to be any usecases for DPLL rounding that is not exact.
+ *
+ * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
+ * @last_rounded_n) should be separated from the runtime-fixed fields
+ * and placed into a differenct structure, so that the runtime-fixed data
+ * can be placed into read-only space.
+ */
+struct dpll_data {
+        void __iomem            *mult_div1_reg;
+        u32                     mult_mask;
+        u32                     div1_mask;
+        struct clk              *clk_bypass;
+        struct clk              *clk_ref;
+        void __iomem            *control_reg;
+        u32                     enable_mask;
+        unsigned int            rate_tolerance;
+        unsigned long           last_rounded_rate;
+        u16                     last_rounded_m;
+        u16                     max_multiplier;
+        u8                      last_rounded_n;
+        u8                      min_divider;
+        u8                      max_divider;
+        u8                      modes;
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
+        void __iomem            *autoidle_reg;
+        void __iomem            *idlest_reg;
+        u32                     autoidle_mask;
+        u32                     freqsel_mask;
+        u32                     idlest_mask;
+        u8                      auto_recal_bit;
+        u8                      recal_en_bit;
+        u8                      recal_st_bit;
+        u8                      flags;
+#  endif
+};
+
+#endif
+
+struct clk {
+        struct list_head        node;
+        const struct clkops     *ops;
+        const char              *name;
+        struct clk              *parent;
+        struct list_head        children;
+        struct list_head        sibling;        /* node for children */
+        unsigned long           rate;
+        void __iomem            *enable_reg;
+        unsigned long           (*recalc)(struct clk *);
+        int                     (*set_rate)(struct clk *, unsigned long);
+        long                    (*round_rate)(struct clk *, unsigned long);
+        void                    (*init)(struct clk *);
+        __u8                    enable_bit;
+        __s8                    usecount;
+        u8                      fixed_div;
+        u8                      flags;
+#ifdef CONFIG_ARCH_OMAP2PLUS
+        void __iomem            *clksel_reg;
+        u32                     clksel_mask;
+        const struct clksel     *clksel;
+        struct dpll_data        *dpll_data;
+        const char              *clkdm_name;
+        struct clockdomain      *clkdm;
+#else
+        __u8                    rate_offset;
+        __u8                    src_offset;
+#endif
+#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
+        struct dentry           *dent;  /* For visible tree hierarchy */
+#endif
+};
+
+struct cpufreq_frequency_table;
+
+struct clk_functions {
+        int             (*clk_enable)(struct clk *clk);
+        void            (*clk_disable)(struct clk *clk);
+        long            (*clk_round_rate)(struct clk *clk, unsigned long rate);
+        int             (*clk_set_rate)(struct clk *clk, unsigned long rate);
+        int             (*clk_set_parent)(struct clk *clk, struct clk *parent);
+        void            (*clk_allow_idle)(struct clk *clk);
+        void            (*clk_deny_idle)(struct clk *clk);
+        void            (*clk_disable_unused)(struct clk *clk);
+#ifdef CONFIG_CPU_FREQ
+        void            (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
+        void            (*clk_exit_cpufreq_table)(struct cpufreq_frequency_table **);
+#endif
+};
+
+extern int mpurate;
+
+extern int clk_init(struct clk_functions *custom_clocks);
+extern void clk_preinit(struct clk *clk);
+extern int clk_register(struct clk *clk);
+extern void clk_reparent(struct clk *child, struct clk *parent);
+extern void clk_unregister(struct clk *clk);
+extern void propagate_rate(struct clk *clk);
+extern void recalculate_root_clocks(void);
+extern unsigned long followparent_recalc(struct clk *clk);
+extern void clk_enable_init_clocks(void);
+unsigned long omap_fixed_divisor_recalc(struct clk *clk);
+#ifdef CONFIG_CPU_FREQ
+extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
+extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
+#endif
+extern struct clk *omap_clk_get_by_name(const char *name);
+
+extern const struct clkops clkops_null;
+
+extern struct clk dummy_ck;
+
+/* Clock flags */
+#define ENABLE_REG_32BIT        (1 << 0)        /* Use 32-bit access */
+#define CLOCK_IDLE_CONTROL      (1 << 1)
+#define CLOCK_NO_IDLE_PARENT    (1 << 2)
+#define ENABLE_ON_INIT          (1 << 3)        /* Enable upon framework init */
+#define INVERT_ENABLE           (1 << 4)        /* 0 enables, 1 disables */
+
+/* Clksel_rate flags */
+#define DEFAULT_RATE            (1 << 0)
+#define RATE_IN_242X            (1 << 1)
+#define RATE_IN_243X            (1 << 2)
+#define RATE_IN_343X            (1 << 3)        /* rates common to all 343X */
+#define RATE_IN_3430ES2         (1 << 4)        /* 3430ES2 rates only */
+#define RATE_IN_36XX            (1 << 5)
+#define RATE_IN_4430            (1 << 6)
+
+#define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
+
+
+#endif
diff --git a/arch/arm/plat-omap/include/plat/clockdomain.h b/arch/arm/plat-omap/include/plat/clockdomain.h
new file mode 100644
index 000000000000..ba0a6c07c0fe
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/clockdomain.h
@@ -0,0 +1,141 @@
+/*
+ * arch/arm/plat-omap/include/mach/clockdomain.h
+ *
+ * OMAP2/3 clockdomain framework functions
+ *
+ * Copyright (C) 2008 Texas Instruments, Inc.
+ * Copyright (C) 2008-2009 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
+#define __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
+
+#include <plat/powerdomain.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+
+/* Clockdomain capability flags */
+#define CLKDM_CAN_FORCE_SLEEP                   (1 << 0)
+#define CLKDM_CAN_FORCE_WAKEUP                  (1 << 1)
+#define CLKDM_CAN_ENABLE_AUTO                   (1 << 2)
+#define CLKDM_CAN_DISABLE_AUTO                  (1 << 3)
+
+#define CLKDM_CAN_HWSUP         (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
+#define CLKDM_CAN_SWSUP         (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
+#define CLKDM_CAN_HWSUP_SWSUP   (CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP)
+
+/* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */
+#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO         0x0
+#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO          0x1
+
+/* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */
+#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO         0x0
+#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP          0x1
+#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP         0x2
+#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO          0x3
+
+/**
+ * struct clkdm_autodep - clkdm deps to add when entering/exiting hwsup mode
+ * @clkdm: clockdomain to add wkdep+sleepdep on - set name member only
+ * @omap_chip: OMAP chip types that this autodep is valid on
+ *
+ * A clockdomain that should have wkdeps and sleepdeps added when a
+ * clockdomain should stay active in hwsup mode; and conversely,
+ * removed when the clockdomain should be allowed to go inactive in
+ * hwsup mode.
+ *
+ * Autodeps are deprecated and should be removed after
+ * omap_hwmod-based fine-grained module idle control is added.
+ */
+struct clkdm_autodep {
+        union {
+                const char *name;
+                struct clockdomain *ptr;
+        } clkdm;
+        const struct omap_chip_id omap_chip;
+};
+
+/**
+ * struct clkdm_dep - encode dependencies between clockdomains
+ * @clkdm_name: clockdomain name
+ * @clkdm: pointer to the struct clockdomain of @clkdm_name
+ * @omap_chip: OMAP chip types that this dependency is valid on
+ * @wkdep_usecount: Number of wakeup dependencies causing this clkdm to wake
+ * @sleepdep_usecount: Number of sleep deps that could prevent clkdm from idle
+ *
+ * Statically defined.  @clkdm is resolved from @clkdm_name at runtime and
+ * should not be pre-initialized.
+ *
+ * XXX Should also include hardware (fixed) dependencies.
+ */
+struct clkdm_dep {
+        const char *clkdm_name;
+        struct clockdomain *clkdm;
+        atomic_t wkdep_usecount;
+        atomic_t sleepdep_usecount;
+        const struct omap_chip_id omap_chip;
+};
+
+/**
+ * struct clockdomain - OMAP clockdomain
+ * @name: clockdomain name
+ * @pwrdm: powerdomain containing this clockdomain
+ * @clktrctrl_reg: CLKSTCTRL reg for the given clock domain
+ * @clktrctrl_mask: CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg
+ * @flags: Clockdomain capability flags
+ * @dep_bit: Bit shift of this clockdomain's PM_WKDEP/CM_SLEEPDEP bit
+ * @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up
+ * @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact
+ * @omap_chip: OMAP chip types that this clockdomain is valid on
+ * @usecount: Usecount tracking
+ * @node: list_head to link all clockdomains together
+ */
+struct clockdomain {
+        const char *name;
+        union {
+                const char *name;
+                struct powerdomain *ptr;
+        } pwrdm;
+        void __iomem *clkstctrl_reg;
+        const u16 clktrctrl_mask;
+        const u8 flags;
+        const u8 dep_bit;
+        struct clkdm_dep *wkdep_srcs;
+        struct clkdm_dep *sleepdep_srcs;
+        const struct omap_chip_id omap_chip;
+        atomic_t usecount;
+        struct list_head node;
+};
+
+void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps);
+struct clockdomain *clkdm_lookup(const char *name);
+
+int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
+                        void *user);
+struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm);
+
+int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_clear_all_wkdeps(struct clockdomain *clkdm);
+int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm);
+
+void omap2_clkdm_allow_idle(struct clockdomain *clkdm);
+void omap2_clkdm_deny_idle(struct clockdomain *clkdm);
+
+int omap2_clkdm_wakeup(struct clockdomain *clkdm);
+int omap2_clkdm_sleep(struct clockdomain *clkdm);
+
+int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
+int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
+
+#endif
diff --git a/arch/arm/plat-omap/include/mach/common.h b/arch/arm/plat-omap/include/plat/common.h
index fdeab421b4dc..7556e271942e 100644
--- a/arch/arm/plat-omap/include/mach/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -27,39 +27,40 @@
 #ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
 #define __ARCH_ARM_MACH_OMAP_COMMON_H
 
-#include <linux/i2c.h>
+#include <plat/i2c.h>
 
 struct sys_timer;
 
+/* used by omap-smp.c and board-4430sdp.c */
+extern void __iomem *gic_cpu_base_addr;
+
 extern void omap_map_common_io(void);
 extern struct sys_timer omap_timer;
-#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
-extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
-                                 struct i2c_board_info const *info,
-                                 unsigned len);
-#else
-static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
-                                 struct i2c_board_info const *info,
-                                 unsigned len)
-{
-        return 0;
-}
-#endif
 
-/* IO bases for various OMAP processors */
+/*
+ * IO bases for various OMAP processors
+ * Except the tap base, rest all the io bases
+ * listed are physical addresses.
+ */
 struct omap_globals {
         u32             class;          /* OMAP class to detect */
         void __iomem    *tap;           /* Control module ID code */
-        void __iomem    *sdrc;          /* SDRAM Controller */
-        void __iomem    *sms;           /* SDRAM Memory Scheduler */
-        void __iomem    *ctrl;          /* System Control Module */
-        void __iomem    *prm;           /* Power and Reset Management */
-        void __iomem    *cm;            /* Clock Management */
+        unsigned long   sdrc;           /* SDRAM Controller */
+        unsigned long   sms;            /* SDRAM Memory Scheduler */
+        unsigned long   ctrl;           /* System Control Module */
+        unsigned long   prm;            /* Power and Reset Management */
+        unsigned long   cm;             /* Clock Management */
+        unsigned long   cm2;
+        unsigned long   uart1_phys;
+        unsigned long   uart2_phys;
+        unsigned long   uart3_phys;
+        unsigned long   uart4_phys;
 };
 
 void omap2_set_globals_242x(void);
 void omap2_set_globals_243x(void);
 void omap2_set_globals_343x(void);
+void omap2_set_globals_36xx(void);
 void omap2_set_globals_443x(void);
 
 /* These get called from omap2_set_globals_xxxx(), do not call these */
@@ -67,5 +68,26 @@ void omap2_set_globals_tap(struct omap_globals *);
 void omap2_set_globals_sdrc(struct omap_globals *);
 void omap2_set_globals_control(struct omap_globals *);
 void omap2_set_globals_prcm(struct omap_globals *);
+void omap2_set_globals_uart(struct omap_globals *);
+
+/**
+ * omap_test_timeout - busy-loop, testing a condition
+ * @cond: condition to test until it evaluates to true
+ * @timeout: maximum number of microseconds in the timeout
+ * @index: loop index (integer)
+ *
+ * Loop waiting for @cond to become true or until at least @timeout
+ * microseconds have passed.  To use, define some integer @index in the
+ * calling code.  After running, if @index == @timeout, then the loop has
+ * timed out.
+ */
+#define omap_test_timeout(cond, timeout, index)                 \
+({                                                              \
+        for (index = 0; index < timeout; index++) {             \
+                if (cond)                                       \
+                        break;                                  \
+                udelay(1);                                      \
+        }                                                       \
+})
 
 #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/plat/control.h
index 826d317cdbec..a56deee97676 100644
--- a/arch/arm/plat-omap/include/mach/control.h
+++ b/arch/arm/plat-omap/include/plat/control.h
@@ -20,15 +20,18 @@
 
 #ifndef __ASSEMBLY__
 #define OMAP242X_CTRL_REGADDR(reg)                                      \
-        OMAP2_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
+                OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
 #define OMAP243X_CTRL_REGADDR(reg)                                      \
-        OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
+                OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
 #define OMAP343X_CTRL_REGADDR(reg)                                      \
-        OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+                OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
 #else
-#define OMAP242X_CTRL_REGADDR(reg)      OMAP2_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
-#define OMAP243X_CTRL_REGADDR(reg)      OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
-#define OMAP343X_CTRL_REGADDR(reg)      OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+#define OMAP242X_CTRL_REGADDR(reg)                                      \
+                OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
+#define OMAP243X_CTRL_REGADDR(reg)                                      \
+                OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
+#define OMAP343X_CTRL_REGADDR(reg)                                      \
+                OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
 #endif /* __ASSEMBLY__ */
 
 /*
@@ -109,6 +112,8 @@
 #define OMAP24XX_CONTROL_TEST_KEY_8     (OMAP2_CONTROL_GENERAL + 0x00e0)
 #define OMAP24XX_CONTROL_TEST_KEY_9     (OMAP2_CONTROL_GENERAL + 0x00e4)
 
+#define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
+
 /* 34xx-only CONTROL_GENERAL register offsets */
 #define OMAP343X_CONTROL_PADCONF_OFF    (OMAP2_CONTROL_GENERAL + 0x0000)
 #define OMAP343X_CONTROL_MEM_DFTRW0     (OMAP2_CONTROL_GENERAL + 0x0008)
@@ -141,13 +146,67 @@
 #define OMAP343X_CONTROL_TEST_KEY_13    (OMAP2_CONTROL_GENERAL + 0x00fc)
 #define OMAP343X_CONTROL_IVA2_BOOTADDR  (OMAP2_CONTROL_GENERAL + 0x0190)
 #define OMAP343X_CONTROL_IVA2_BOOTMOD   (OMAP2_CONTROL_GENERAL + 0x0194)
-#define OMAP343X_CONTROL_PBIAS_LITE     (OMAP2_CONTROL_GENERAL + 0x02b0)
-#define OMAP343X_CONTROL_TEMP_SENSOR    (OMAP2_CONTROL_GENERAL + 0x02b4)
+#define OMAP343X_CONTROL_DEBOBS(i)      (OMAP2_CONTROL_GENERAL + 0x01B0 \
+                                        + ((i) >> 1) * 4 + (!((i) & 1)) * 2)
+#define OMAP343X_CONTROL_PROG_IO0       (OMAP2_CONTROL_GENERAL + 0x01D4)
+#define OMAP343X_CONTROL_PROG_IO1       (OMAP2_CONTROL_GENERAL + 0x01D8)
+#define OMAP343X_CONTROL_DSS_DPLL_SPREADING     (OMAP2_CONTROL_GENERAL + 0x01E0)
+#define OMAP343X_CONTROL_CORE_DPLL_SPREADING    (OMAP2_CONTROL_GENERAL + 0x01E4)
+#define OMAP343X_CONTROL_PER_DPLL_SPREADING     (OMAP2_CONTROL_GENERAL + 0x01E8)
+#define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC)
+#define OMAP343X_CONTROL_PBIAS_LITE     (OMAP2_CONTROL_GENERAL + 0x02B0)
+#define OMAP343X_CONTROL_TEMP_SENSOR    (OMAP2_CONTROL_GENERAL + 0x02B4)
+#define OMAP343X_CONTROL_SRAMLDO4       (OMAP2_CONTROL_GENERAL + 0x02B8)
+#define OMAP343X_CONTROL_SRAMLDO5       (OMAP2_CONTROL_GENERAL + 0x02C0)
+#define OMAP343X_CONTROL_CSI            (OMAP2_CONTROL_GENERAL + 0x02C4)
+
+/* AM35XX only CONTROL_GENERAL register offsets */
+#define AM35XX_CONTROL_MSUSPENDMUX_6    (OMAP2_CONTROL_GENERAL + 0x0038)
+#define AM35XX_CONTROL_DEVCONF2         (OMAP2_CONTROL_GENERAL + 0x0310)
+#define AM35XX_CONTROL_DEVCONF3         (OMAP2_CONTROL_GENERAL + 0x0314)
+#define AM35XX_CONTROL_CBA_PRIORITY     (OMAP2_CONTROL_GENERAL + 0x0320)
+#define AM35XX_CONTROL_LVL_INTR_CLEAR   (OMAP2_CONTROL_GENERAL + 0x0324)
+#define AM35XX_CONTROL_IP_SW_RESET      (OMAP2_CONTROL_GENERAL + 0x0328)
+#define AM35XX_CONTROL_IPSS_CLK_CTRL    (OMAP2_CONTROL_GENERAL + 0x032C)
+
+/* 34xx PADCONF register offsets */
+#define OMAP343X_PADCONF_ETK(i)         (OMAP2_CONTROL_PADCONFS + 0x5a8 + \
+                                                (i)*2)
+#define OMAP343X_PADCONF_ETK_CLK        OMAP343X_PADCONF_ETK(0)
+#define OMAP343X_PADCONF_ETK_CTL        OMAP343X_PADCONF_ETK(1)
+#define OMAP343X_PADCONF_ETK_D0         OMAP343X_PADCONF_ETK(2)
+#define OMAP343X_PADCONF_ETK_D1         OMAP343X_PADCONF_ETK(3)
+#define OMAP343X_PADCONF_ETK_D2         OMAP343X_PADCONF_ETK(4)
+#define OMAP343X_PADCONF_ETK_D3         OMAP343X_PADCONF_ETK(5)
+#define OMAP343X_PADCONF_ETK_D4         OMAP343X_PADCONF_ETK(6)
+#define OMAP343X_PADCONF_ETK_D5         OMAP343X_PADCONF_ETK(7)
+#define OMAP343X_PADCONF_ETK_D6         OMAP343X_PADCONF_ETK(8)
+#define OMAP343X_PADCONF_ETK_D7         OMAP343X_PADCONF_ETK(9)
+#define OMAP343X_PADCONF_ETK_D8         OMAP343X_PADCONF_ETK(10)
+#define OMAP343X_PADCONF_ETK_D9         OMAP343X_PADCONF_ETK(11)
+#define OMAP343X_PADCONF_ETK_D10        OMAP343X_PADCONF_ETK(12)
+#define OMAP343X_PADCONF_ETK_D11        OMAP343X_PADCONF_ETK(13)
+#define OMAP343X_PADCONF_ETK_D12        OMAP343X_PADCONF_ETK(14)
+#define OMAP343X_PADCONF_ETK_D13        OMAP343X_PADCONF_ETK(15)
+#define OMAP343X_PADCONF_ETK_D14        OMAP343X_PADCONF_ETK(16)
+#define OMAP343X_PADCONF_ETK_D15        OMAP343X_PADCONF_ETK(17)
+
+/* 34xx GENERAL_WKUP regist offsets */
+#define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
+                                                0x008 + (i))
+#define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
+#define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
+#define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
+#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
+#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
 
 /* 34xx D2D idle-related pins, handled by PM core */
 #define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
 #define OMAP3_PADCONF_SAD2D_IDLEACK    0x254
 
+/* 44xx control status register offset */
+#define OMAP44XX_CONTROL_STATUS         0x2c4
+
 /*
  * REVISIT: This list of registers is not comprehensive - there are more
  * that should be added.
@@ -193,6 +252,9 @@
 #define OMAP2_PBIASLITEPWRDNZ0          (1 << 1)
 #define OMAP2_PBIASLITEVMODE0           (1 << 0)
 
+/* CONTROL_PROG_IO1 bits */
+#define OMAP3630_PRG_SDMMC1_SPEEDCTRL   (1 << 20)
+
 /* CONTROL_IVA2_BOOTMOD bits */
 #define OMAP3_IVA2_BOOTMOD_SHIFT        0
 #define OMAP3_IVA2_BOOTMOD_MASK         (0xf << 0)
@@ -202,9 +264,72 @@
 #define OMAP3_PADCONF_WAKEUPEVENT0      (1 << 15)
 #define OMAP3_PADCONF_WAKEUPENABLE0     (1 << 14)
 
+#define OMAP343X_SCRATCHPAD_ROM         (OMAP343X_CTRL_BASE + 0x860)
+#define OMAP343X_SCRATCHPAD             (OMAP343X_CTRL_BASE + 0x910)
+#define OMAP343X_SCRATCHPAD_ROM_OFFSET  0x19C
+
+/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
+#define AM35XX_USBOTG_VBUSP_CLK_SHIFT   0
+#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT   1
+#define AM35XX_VPFE_VBUSP_CLK_SHIFT     2
+#define AM35XX_HECC_VBUSP_CLK_SHIFT     3
+#define AM35XX_USBOTG_FCLK_SHIFT        8
+#define AM35XX_CPGMAC_FCLK_SHIFT        9
+#define AM35XX_VPFE_FCLK_SHIFT          10
+
+/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/
+#define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0)
+#define AM35XX_CPGMAC_C0_RX_PULSE_CLR   BIT(1)
+#define AM35XX_CPGMAC_C0_RX_THRESH_CLR  BIT(2)
+#define AM35XX_CPGMAC_C0_TX_PULSE_CLR   BIT(3)
+#define AM35XX_USBOTGSS_INT_CLR         BIT(4)
+#define AM35XX_VPFE_CCDC_VD0_INT_CLR    BIT(5)
+#define AM35XX_VPFE_CCDC_VD1_INT_CLR    BIT(6)
+#define AM35XX_VPFE_CCDC_VD2_INT_CLR    BIT(7)
+
+/*AM35XX CONTROL_IP_SW_RESET bits*/
+#define AM35XX_USBOTGSS_SW_RST          BIT(0)
+#define AM35XX_CPGMACSS_SW_RST          BIT(1)
+#define AM35XX_VPFE_VBUSP_SW_RST        BIT(2)
+#define AM35XX_HECC_SW_RST              BIT(3)
+#define AM35XX_VPFE_PCLK_SW_RST         BIT(4)
+
+/*
+ * CONTROL OMAP STATUS register to identify OMAP3 features
+ */
+#define OMAP3_CONTROL_OMAP_STATUS       0x044c
+
+#define OMAP3_SGX_SHIFT                 13
+#define OMAP3_SGX_MASK                  (3 << OMAP3_SGX_SHIFT)
+#define         FEAT_SGX_FULL           0
+#define         FEAT_SGX_HALF           1
+#define         FEAT_SGX_NONE           2
+
+#define OMAP3_IVA_SHIFT                 12
+#define OMAP3_IVA_MASK                  (1 << OMAP3_SGX_SHIFT)
+#define         FEAT_IVA                0
+#define         FEAT_IVA_NONE           1
+
+#define OMAP3_L2CACHE_SHIFT             10
+#define OMAP3_L2CACHE_MASK              (3 << OMAP3_L2CACHE_SHIFT)
+#define         FEAT_L2CACHE_NONE       0
+#define         FEAT_L2CACHE_64KB       1
+#define         FEAT_L2CACHE_128KB      2
+#define         FEAT_L2CACHE_256KB      3
+
+#define OMAP3_ISP_SHIFT                 5
+#define OMAP3_ISP_MASK                  (1<< OMAP3_ISP_SHIFT)
+#define         FEAT_ISP                0
+#define         FEAT_ISP_NONE           1
+
+#define OMAP3_NEON_SHIFT                4
+#define OMAP3_NEON_MASK                 (1<< OMAP3_NEON_SHIFT)
+#define         FEAT_NEON               0
+#define         FEAT_NEON_NONE          1
+
+
 #ifndef __ASSEMBLY__
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
-                defined(CONFIG_ARCH_OMAP4)
+#ifdef CONFIG_ARCH_OMAP2PLUS
 extern void __iomem *omap_ctrl_base_get(void);
 extern u8 omap_ctrl_readb(u16 offset);
 extern u16 omap_ctrl_readw(u16 offset);
@@ -212,6 +337,15 @@ extern u32 omap_ctrl_readl(u16 offset);
 extern void omap_ctrl_writeb(u8 val, u16 offset);
 extern void omap_ctrl_writew(u16 val, u16 offset);
 extern void omap_ctrl_writel(u32 val, u16 offset);
+
+extern void omap3_save_scratchpad_contents(void);
+extern void omap3_clear_scratchpad_contents(void);
+extern u32 *get_restore_pointer(void);
+extern u32 *get_es3_restore_pointer(void);
+extern u32 omap3_arm_context[128];
+extern void omap3_control_save_context(void);
+extern void omap3_control_restore_context(void);
+
 #else
 #define omap_ctrl_base_get()            0
 #define omap_ctrl_readb(x)              0
diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index f129efb3075e..75141742300c 100644
--- a/arch/arm/plat-omap/include/mach/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -30,6 +30,9 @@
 #ifndef __ASM_ARCH_OMAP_CPU_H
 #define __ASM_ARCH_OMAP_CPU_H
 
+#include <linux/bitops.h>
+#include <plat/multi.h>
+
 /*
  * Omap device type i.e. EMU/HS/TST/GP/BAD
  */
@@ -42,7 +45,7 @@
 int omap_type(void);
 
 struct omap_chip_id {
-        u8 oc;
+        u16 oc;
         u8 type;
 };
 
@@ -57,73 +60,21 @@ struct omap_chip_id {
 unsigned int omap_rev(void);
 
 /*
- * Test if multicore OMAP support is needed
+ * Define CPU revision bits
+ *
+ * Verbose meaning of the revision bits may be different for a silicon
+ * family. This difference can be handled separately.
  */
-#undef MULTI_OMAP1
-#undef MULTI_OMAP2
-#undef OMAP_NAME
-
-#ifdef CONFIG_ARCH_OMAP730
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP1
-#  define MULTI_OMAP1
-# else
-#  define OMAP_NAME omap730
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP850
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP1
-#  define MULTI_OMAP1
-# else
-#  define OMAP_NAME omap850
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP1
-#  define MULTI_OMAP1
-# else
-#  define OMAP_NAME omap1510
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP1
-#  define MULTI_OMAP1
-# else
-#  define OMAP_NAME omap16xx
-# endif
-#endif
-#if (defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX))
-# if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
-#  error "OMAP1 and OMAP2 can't be selected at the same time"
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP2420
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP2
-#  define MULTI_OMAP2
-# else
-#  define OMAP_NAME omap2420
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP2430
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP2
-#  define MULTI_OMAP2
-# else
-#  define OMAP_NAME omap2430
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP3430
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP2
-#  define MULTI_OMAP2
-# else
-#  define OMAP_NAME omap3430
-# endif
-#endif
+#define OMAP_REVBITS_00         0x00
+#define OMAP_REVBITS_10         0x10
+#define OMAP_REVBITS_20         0x20
+#define OMAP_REVBITS_30         0x30
+#define OMAP_REVBITS_40         0x40
+
+/*
+ * Get the CPU revision for OMAP devices
+ */
+#define GET_OMAP_REVISION()     ((omap_rev() >> 8) & 0xff)
 
 /*
  * Macros to group OMAP into cpu classes.
@@ -135,6 +86,7 @@ unsigned int omap_rev(void);
  * cpu_is_omap242x():   True for OMAP2420, OMAP2422, OMAP2423
  * cpu_is_omap243x():   True for OMAP2430
  * cpu_is_omap343x():   True for OMAP3430
+ * cpu_is_omap443x():   True for OMAP4430
  */
 #define GET_OMAP_CLASS  (omap_rev() & 0xff)
 
@@ -157,10 +109,13 @@ IS_OMAP_CLASS(15xx, 0x15)
 IS_OMAP_CLASS(16xx, 0x16)
 IS_OMAP_CLASS(24xx, 0x24)
 IS_OMAP_CLASS(34xx, 0x34)
+IS_OMAP_CLASS(44xx, 0x44)
 
 IS_OMAP_SUBCLASS(242x, 0x242)
 IS_OMAP_SUBCLASS(243x, 0x243)
 IS_OMAP_SUBCLASS(343x, 0x343)
+IS_OMAP_SUBCLASS(363x, 0x363)
+IS_OMAP_SUBCLASS(443x, 0x443)
 
 #define cpu_is_omap7xx()                0
 #define cpu_is_omap15xx()               0
@@ -210,22 +165,26 @@ IS_OMAP_SUBCLASS(343x, 0x343)
 #endif
 
 #if defined(MULTI_OMAP2)
-# if defined(CONFIG_ARCH_OMAP24XX)
+# if defined(CONFIG_ARCH_OMAP2)
 #  undef  cpu_is_omap24xx
-#  undef  cpu_is_omap242x
-#  undef  cpu_is_omap243x
 #  define cpu_is_omap24xx()             is_omap24xx()
+# endif
+# if defined (CONFIG_ARCH_OMAP2420)
+#  undef  cpu_is_omap242x
 #  define cpu_is_omap242x()             is_omap242x()
+# endif
+# if defined (CONFIG_ARCH_OMAP2430)
+#  undef  cpu_is_omap243x
 #  define cpu_is_omap243x()             is_omap243x()
 # endif
-# if defined(CONFIG_ARCH_OMAP34XX)
+# if defined(CONFIG_ARCH_OMAP3)
 #  undef  cpu_is_omap34xx
 #  undef  cpu_is_omap343x
 #  define cpu_is_omap34xx()             is_omap34xx()
 #  define cpu_is_omap343x()             is_omap343x()
 # endif
 #else
-# if defined(CONFIG_ARCH_OMAP24XX)
+# if defined(CONFIG_ARCH_OMAP2)
 #  undef  cpu_is_omap24xx
 #  define cpu_is_omap24xx()             1
 # endif
@@ -237,7 +196,7 @@ IS_OMAP_SUBCLASS(343x, 0x343)
 #  undef  cpu_is_omap243x
 #  define cpu_is_omap243x()             1
 # endif
-# if defined(CONFIG_ARCH_OMAP34XX)
+# if defined(CONFIG_ARCH_OMAP3)
 #  undef  cpu_is_omap34xx
 #  define cpu_is_omap34xx()             1
 # endif
@@ -264,6 +223,9 @@ IS_OMAP_SUBCLASS(343x, 0x343)
  * cpu_is_omap2423():   True for OMAP2423
  * cpu_is_omap2430():   True for OMAP2430
  * cpu_is_omap3430():   True for OMAP3430
+ * cpu_is_omap4430():   True for OMAP4430
+ * cpu_is_omap3505():   True for OMAP3505
+ * cpu_is_omap3517():   True for OMAP3517
  */
 #define GET_OMAP_TYPE   ((omap_rev() >> 16) & 0xffff)
 
@@ -287,6 +249,8 @@ IS_OMAP_TYPE(2422, 0x2422)
 IS_OMAP_TYPE(2423, 0x2423)
 IS_OMAP_TYPE(2430, 0x2430)
 IS_OMAP_TYPE(3430, 0x3430)
+IS_OMAP_TYPE(3505, 0x3505)
+IS_OMAP_TYPE(3517, 0x3517)
 
 #define cpu_is_omap310()                0
 #define cpu_is_omap730()                0
@@ -301,7 +265,15 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define cpu_is_omap2422()               0
 #define cpu_is_omap2423()               0
 #define cpu_is_omap2430()               0
+#define cpu_is_omap3503()               0
+#define cpu_is_omap3515()               0
+#define cpu_is_omap3525()               0
+#define cpu_is_omap3530()               0
+#define cpu_is_omap3505()               0
+#define cpu_is_omap3517()               0
 #define cpu_is_omap3430()               0
+#define cpu_is_omap4430()               0
+#define cpu_is_omap3630()               0
 
 /*
  * Whether we have MULTI_OMAP1 or not, we still need to distinguish
@@ -338,7 +310,7 @@ IS_OMAP_TYPE(3430, 0x3430)
 # define cpu_is_omap1710()              is_omap1710()
 #endif
 
-#if defined(CONFIG_ARCH_OMAP24XX)
+#if defined(CONFIG_ARCH_OMAP2)
 # undef  cpu_is_omap2420
 # undef  cpu_is_omap2422
 # undef  cpu_is_omap2423
@@ -349,16 +321,36 @@ IS_OMAP_TYPE(3430, 0x3430)
 # define cpu_is_omap2430()              is_omap2430()
 #endif
 
-#if defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP3)
 # undef cpu_is_omap3430
+# undef cpu_is_omap3503
+# undef cpu_is_omap3515
+# undef cpu_is_omap3525
+# undef cpu_is_omap3530
+# undef cpu_is_omap3505
+# undef cpu_is_omap3517
 # define cpu_is_omap3430()              is_omap3430()
+# define cpu_is_omap3503()              (cpu_is_omap3430() &&           \
+                                                (!omap3_has_iva()) &&   \
+                                                (!omap3_has_sgx()))
+# define cpu_is_omap3515()              (cpu_is_omap3430() &&           \
+                                                (!omap3_has_iva()) &&   \
+                                                (omap3_has_sgx()))
+# define cpu_is_omap3525()              (cpu_is_omap3430() &&           \
+                                                (!omap3_has_sgx()) &&   \
+                                                (omap3_has_iva()))
+# define cpu_is_omap3530()              (cpu_is_omap3430())
+# define cpu_is_omap3505()              is_omap3505()
+# define cpu_is_omap3517()              is_omap3517()
+# undef cpu_is_omap3630
+# define cpu_is_omap3630()              is_omap363x()
 #endif
 
 # if defined(CONFIG_ARCH_OMAP4)
 # undef cpu_is_omap44xx
 # undef cpu_is_omap443x
-# define cpu_is_omap44xx()              1
-# define cpu_is_omap443x()              1
+# define cpu_is_omap44xx()              is_omap44xx()
+# define cpu_is_omap443x()              is_omap443x()
 # endif
 
 /* Macros to detect if we have OMAP1 or OMAP2 */
@@ -381,8 +373,20 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define OMAP3430_REV_ES2_1      0x34302034
 #define OMAP3430_REV_ES3_0      0x34303034
 #define OMAP3430_REV_ES3_1      0x34304034
+#define OMAP3430_REV_ES3_1_2    0x34305034
 
-#define OMAP443X_CLASS          0x44300034
+#define OMAP3630_REV_ES1_0      0x36300034
+
+#define OMAP35XX_CLASS          0x35000034
+#define OMAP3503_REV(v)         (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8))
+#define OMAP3515_REV(v)         (OMAP35XX_CLASS | (0x3515 << 16) | (v << 8))
+#define OMAP3525_REV(v)         (OMAP35XX_CLASS | (0x3525 << 16) | (v << 8))
+#define OMAP3530_REV(v)         (OMAP35XX_CLASS | (0x3530 << 16) | (v << 8))
+#define OMAP3505_REV(v)         (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8))
+#define OMAP3517_REV(v)         (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
+
+#define OMAP443X_CLASS          0x44300044
+#define OMAP4430_REV_ES1_0      0x44300044
 
 /*
  * omap_chip bits
@@ -405,9 +409,13 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define CHIP_IS_OMAP3430ES2             (1 << 4)
 #define CHIP_IS_OMAP3430ES3_0           (1 << 5)
 #define CHIP_IS_OMAP3430ES3_1           (1 << 6)
+#define CHIP_IS_OMAP3630ES1             (1 << 7)
+#define CHIP_IS_OMAP4430ES1             (1 << 8)
 
 #define CHIP_IS_OMAP24XX                (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
 
+#define CHIP_IS_OMAP4430                (CHIP_IS_OMAP4430ES1)
+
 /*
  * "GE" here represents "greater than or equal to" in terms of ES
  * levels.  So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430
@@ -416,11 +424,38 @@ IS_OMAP_TYPE(3430, 0x3430)
  */
 #define CHIP_GE_OMAP3430ES2             (CHIP_IS_OMAP3430ES2 | \
                                          CHIP_IS_OMAP3430ES3_0 | \
-                                         CHIP_IS_OMAP3430ES3_1)
-#define CHIP_GE_OMAP3430ES3_1           (CHIP_IS_OMAP3430ES3_1)
+                                         CHIP_IS_OMAP3430ES3_1 | \
+                                         CHIP_IS_OMAP3630ES1)
+#define CHIP_GE_OMAP3430ES3_1           (CHIP_IS_OMAP3430ES3_1 | \
+                                         CHIP_IS_OMAP3630ES1)
 
 
 int omap_chip_is(struct omap_chip_id oci);
 void omap2_check_revision(void);
 
+/*
+ * Runtime detection of OMAP3 features
+ */
+extern u32 omap3_features;
+
+#define OMAP3_HAS_L2CACHE               BIT(0)
+#define OMAP3_HAS_IVA                   BIT(1)
+#define OMAP3_HAS_SGX                   BIT(2)
+#define OMAP3_HAS_NEON                  BIT(3)
+#define OMAP3_HAS_ISP                   BIT(4)
+#define OMAP3_HAS_192MHZ_CLK            BIT(5)
+
+#define OMAP3_HAS_FEATURE(feat,flag)                    \
+static inline unsigned int omap3_has_ ##feat(void)      \
+{                                                       \
+        return (omap3_features & OMAP3_HAS_ ##flag);    \
+}                                                       \
+
+OMAP3_HAS_FEATURE(l2cache, L2CACHE)
+OMAP3_HAS_FEATURE(sgx, SGX)
+OMAP3_HAS_FEATURE(iva, IVA)
+OMAP3_HAS_FEATURE(neon, NEON)
+OMAP3_HAS_FEATURE(isp, ISP)
+OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
+
 #endif
diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h
new file mode 100644
index 000000000000..1c529ce9dc11
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/display.h
@@ -0,0 +1,590 @@
+/*
+ * linux/include/asm-arm/arch-omap/display.h
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ASM_ARCH_OMAP_DISPLAY_H
+#define __ASM_ARCH_OMAP_DISPLAY_H
+
+#include <linux/list.h>
+#include <linux/kobject.h>
+#include <linux/device.h>
+#include <asm/atomic.h>
+
+#define DISPC_IRQ_FRAMEDONE             (1 << 0)
+#define DISPC_IRQ_VSYNC                 (1 << 1)
+#define DISPC_IRQ_EVSYNC_EVEN           (1 << 2)
+#define DISPC_IRQ_EVSYNC_ODD            (1 << 3)
+#define DISPC_IRQ_ACBIAS_COUNT_STAT     (1 << 4)
+#define DISPC_IRQ_PROG_LINE_NUM         (1 << 5)
+#define DISPC_IRQ_GFX_FIFO_UNDERFLOW    (1 << 6)
+#define DISPC_IRQ_GFX_END_WIN           (1 << 7)
+#define DISPC_IRQ_PAL_GAMMA_MASK        (1 << 8)
+#define DISPC_IRQ_OCP_ERR               (1 << 9)
+#define DISPC_IRQ_VID1_FIFO_UNDERFLOW   (1 << 10)
+#define DISPC_IRQ_VID1_END_WIN          (1 << 11)
+#define DISPC_IRQ_VID2_FIFO_UNDERFLOW   (1 << 12)
+#define DISPC_IRQ_VID2_END_WIN          (1 << 13)
+#define DISPC_IRQ_SYNC_LOST             (1 << 14)
+#define DISPC_IRQ_SYNC_LOST_DIGIT       (1 << 15)
+#define DISPC_IRQ_WAKEUP                (1 << 16)
+
+struct omap_dss_device;
+struct omap_overlay_manager;
+
+enum omap_display_type {
+        OMAP_DISPLAY_TYPE_NONE          = 0,
+        OMAP_DISPLAY_TYPE_DPI           = 1 << 0,
+        OMAP_DISPLAY_TYPE_DBI           = 1 << 1,
+        OMAP_DISPLAY_TYPE_SDI           = 1 << 2,
+        OMAP_DISPLAY_TYPE_DSI           = 1 << 3,
+        OMAP_DISPLAY_TYPE_VENC          = 1 << 4,
+};
+
+enum omap_plane {
+        OMAP_DSS_GFX    = 0,
+        OMAP_DSS_VIDEO1 = 1,
+        OMAP_DSS_VIDEO2 = 2
+};
+
+enum omap_channel {
+        OMAP_DSS_CHANNEL_LCD    = 0,
+        OMAP_DSS_CHANNEL_DIGIT  = 1,
+};
+
+enum omap_color_mode {
+        OMAP_DSS_COLOR_CLUT1    = 1 << 0,  /* BITMAP 1 */
+        OMAP_DSS_COLOR_CLUT2    = 1 << 1,  /* BITMAP 2 */
+        OMAP_DSS_COLOR_CLUT4    = 1 << 2,  /* BITMAP 4 */
+        OMAP_DSS_COLOR_CLUT8    = 1 << 3,  /* BITMAP 8 */
+        OMAP_DSS_COLOR_RGB12U   = 1 << 4,  /* RGB12, 16-bit container */
+        OMAP_DSS_COLOR_ARGB16   = 1 << 5,  /* ARGB16 */
+        OMAP_DSS_COLOR_RGB16    = 1 << 6,  /* RGB16 */
+        OMAP_DSS_COLOR_RGB24U   = 1 << 7,  /* RGB24, 32-bit container */
+        OMAP_DSS_COLOR_RGB24P   = 1 << 8,  /* RGB24, 24-bit container */
+        OMAP_DSS_COLOR_YUV2     = 1 << 9,  /* YUV2 4:2:2 co-sited */
+        OMAP_DSS_COLOR_UYVY     = 1 << 10, /* UYVY 4:2:2 co-sited */
+        OMAP_DSS_COLOR_ARGB32   = 1 << 11, /* ARGB32 */
+        OMAP_DSS_COLOR_RGBA32   = 1 << 12, /* RGBA32 */
+        OMAP_DSS_COLOR_RGBX32   = 1 << 13, /* RGBx32 */
+
+        OMAP_DSS_COLOR_GFX_OMAP2 =
+                OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
+                OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
+                OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
+                OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
+
+        OMAP_DSS_COLOR_VID_OMAP2 =
+                OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
+                OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
+                OMAP_DSS_COLOR_UYVY,
+
+        OMAP_DSS_COLOR_GFX_OMAP3 =
+                OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
+                OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
+                OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
+                OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
+                OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
+                OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
+
+        OMAP_DSS_COLOR_VID1_OMAP3 =
+                OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
+                OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
+                OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
+
+        OMAP_DSS_COLOR_VID2_OMAP3 =
+                OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
+                OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
+                OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
+                OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
+                OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
+};
+
+enum omap_lcd_display_type {
+        OMAP_DSS_LCD_DISPLAY_STN,
+        OMAP_DSS_LCD_DISPLAY_TFT,
+};
+
+enum omap_dss_load_mode {
+        OMAP_DSS_LOAD_CLUT_AND_FRAME    = 0,
+        OMAP_DSS_LOAD_CLUT_ONLY         = 1,
+        OMAP_DSS_LOAD_FRAME_ONLY        = 2,
+        OMAP_DSS_LOAD_CLUT_ONCE_FRAME   = 3,
+};
+
+enum omap_dss_trans_key_type {
+        OMAP_DSS_COLOR_KEY_GFX_DST = 0,
+        OMAP_DSS_COLOR_KEY_VID_SRC = 1,
+};
+
+enum omap_rfbi_te_mode {
+        OMAP_DSS_RFBI_TE_MODE_1 = 1,
+        OMAP_DSS_RFBI_TE_MODE_2 = 2,
+};
+
+enum omap_panel_config {
+        OMAP_DSS_LCD_IVS                = 1<<0,
+        OMAP_DSS_LCD_IHS                = 1<<1,
+        OMAP_DSS_LCD_IPC                = 1<<2,
+        OMAP_DSS_LCD_IEO                = 1<<3,
+        OMAP_DSS_LCD_RF                 = 1<<4,
+        OMAP_DSS_LCD_ONOFF              = 1<<5,
+
+        OMAP_DSS_LCD_TFT                = 1<<20,
+};
+
+enum omap_dss_venc_type {
+        OMAP_DSS_VENC_TYPE_COMPOSITE,
+        OMAP_DSS_VENC_TYPE_SVIDEO,
+};
+
+enum omap_display_caps {
+        OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE      = 1 << 0,
+        OMAP_DSS_DISPLAY_CAP_TEAR_ELIM          = 1 << 1,
+};
+
+enum omap_dss_update_mode {
+        OMAP_DSS_UPDATE_DISABLED = 0,
+        OMAP_DSS_UPDATE_AUTO,
+        OMAP_DSS_UPDATE_MANUAL,
+};
+
+enum omap_dss_display_state {
+        OMAP_DSS_DISPLAY_DISABLED = 0,
+        OMAP_DSS_DISPLAY_ACTIVE,
+        OMAP_DSS_DISPLAY_SUSPENDED,
+};
+
+/* XXX perhaps this should be removed */
+enum omap_dss_overlay_managers {
+        OMAP_DSS_OVL_MGR_LCD,
+        OMAP_DSS_OVL_MGR_TV,
+};
+
+enum omap_dss_rotation_type {
+        OMAP_DSS_ROT_DMA = 0,
+        OMAP_DSS_ROT_VRFB = 1,
+};
+
+/* clockwise rotation angle */
+enum omap_dss_rotation_angle {
+        OMAP_DSS_ROT_0   = 0,
+        OMAP_DSS_ROT_90  = 1,
+        OMAP_DSS_ROT_180 = 2,
+        OMAP_DSS_ROT_270 = 3,
+};
+
+enum omap_overlay_caps {
+        OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
+        OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
+};
+
+enum omap_overlay_manager_caps {
+        OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
+};
+
+/* RFBI */
+
+struct rfbi_timings {
+        int cs_on_time;
+        int cs_off_time;
+        int we_on_time;
+        int we_off_time;
+        int re_on_time;
+        int re_off_time;
+        int we_cycle_time;
+        int re_cycle_time;
+        int cs_pulse_width;
+        int access_time;
+
+        int clk_div;
+
+        u32 tim[5];             /* set by rfbi_convert_timings() */
+
+        int converted;
+};
+
+void omap_rfbi_write_command(const void *buf, u32 len);
+void omap_rfbi_read_data(void *buf, u32 len);
+void omap_rfbi_write_data(const void *buf, u32 len);
+void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
+                u16 x, u16 y,
+                u16 w, u16 h);
+int omap_rfbi_enable_te(bool enable, unsigned line);
+int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
+                             unsigned hs_pulse_time, unsigned vs_pulse_time,
+                             int hs_pol_inv, int vs_pol_inv, int extif_div);
+
+/* DSI */
+void dsi_bus_lock(void);
+void dsi_bus_unlock(void);
+int dsi_vc_dcs_write(int channel, u8 *data, int len);
+int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd);
+int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param);
+int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len);
+int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen);
+int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data);
+int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u16 *data);
+int dsi_vc_set_max_rx_packet_size(int channel, u16 len);
+int dsi_vc_send_null(int channel);
+int dsi_vc_send_bta_sync(int channel);
+
+/* Board specific data */
+struct omap_dss_board_info {
+        int (*get_last_off_on_transaction_id)(struct device *dev);
+        int num_devices;
+        struct omap_dss_device **devices;
+        struct omap_dss_device *default_device;
+};
+
+struct omap_video_timings {
+        /* Unit: pixels */
+        u16 x_res;
+        /* Unit: pixels */
+        u16 y_res;
+        /* Unit: KHz */
+        u32 pixel_clock;
+        /* Unit: pixel clocks */
+        u16 hsw;        /* Horizontal synchronization pulse width */
+        /* Unit: pixel clocks */
+        u16 hfp;        /* Horizontal front porch */
+        /* Unit: pixel clocks */
+        u16 hbp;        /* Horizontal back porch */
+        /* Unit: line clocks */
+        u16 vsw;        /* Vertical synchronization pulse width */
+        /* Unit: line clocks */
+        u16 vfp;        /* Vertical front porch */
+        /* Unit: line clocks */
+        u16 vbp;        /* Vertical back porch */
+};
+
+#ifdef CONFIG_OMAP2_DSS_VENC
+/* Hardcoded timings for tv modes. Venc only uses these to
+ * identify the mode, and does not actually use the configs
+ * itself. However, the configs should be something that
+ * a normal monitor can also show */
+const extern struct omap_video_timings omap_dss_pal_timings;
+const extern struct omap_video_timings omap_dss_ntsc_timings;
+#endif
+
+struct omap_overlay_info {
+        bool enabled;
+
+        u32 paddr;
+        void __iomem *vaddr;
+        u16 screen_width;
+        u16 width;
+        u16 height;
+        enum omap_color_mode color_mode;
+        u8 rotation;
+        enum omap_dss_rotation_type rotation_type;
+        bool mirror;
+
+        u16 pos_x;
+        u16 pos_y;
+        u16 out_width;  /* if 0, out_width == width */
+        u16 out_height; /* if 0, out_height == height */
+        u8 global_alpha;
+};
+
+struct omap_overlay {
+        struct kobject kobj;
+        struct list_head list;
+
+        /* static fields */
+        const char *name;
+        int id;
+        enum omap_color_mode supported_modes;
+        enum omap_overlay_caps caps;
+
+        /* dynamic fields */
+        struct omap_overlay_manager *manager;
+        struct omap_overlay_info info;
+
+        /* if true, info has been changed, but not applied() yet */
+        bool info_dirty;
+
+        int (*set_manager)(struct omap_overlay *ovl,
+                struct omap_overlay_manager *mgr);
+        int (*unset_manager)(struct omap_overlay *ovl);
+
+        int (*set_overlay_info)(struct omap_overlay *ovl,
+                        struct omap_overlay_info *info);
+        void (*get_overlay_info)(struct omap_overlay *ovl,
+                        struct omap_overlay_info *info);
+
+        int (*wait_for_go)(struct omap_overlay *ovl);
+};
+
+struct omap_overlay_manager_info {
+        u32 default_color;
+
+        enum omap_dss_trans_key_type trans_key_type;
+        u32 trans_key;
+        bool trans_enabled;
+
+        bool alpha_enabled;
+};
+
+struct omap_overlay_manager {
+        struct kobject kobj;
+        struct list_head list;
+
+        /* static fields */
+        const char *name;
+        int id;
+        enum omap_overlay_manager_caps caps;
+        int num_overlays;
+        struct omap_overlay **overlays;
+        enum omap_display_type supported_displays;
+
+        /* dynamic fields */
+        struct omap_dss_device *device;
+        struct omap_overlay_manager_info info;
+
+        bool device_changed;
+        /* if true, info has been changed but not applied() yet */
+        bool info_dirty;
+
+        int (*set_device)(struct omap_overlay_manager *mgr,
+                struct omap_dss_device *dssdev);
+        int (*unset_device)(struct omap_overlay_manager *mgr);
+
+        int (*set_manager_info)(struct omap_overlay_manager *mgr,
+                        struct omap_overlay_manager_info *info);
+        void (*get_manager_info)(struct omap_overlay_manager *mgr,
+                        struct omap_overlay_manager_info *info);
+
+        int (*apply)(struct omap_overlay_manager *mgr);
+        int (*wait_for_go)(struct omap_overlay_manager *mgr);
+        int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
+
+        int (*enable)(struct omap_overlay_manager *mgr);
+        int (*disable)(struct omap_overlay_manager *mgr);
+};
+
+struct omap_dss_device {
+        struct device dev;
+
+        enum omap_display_type type;
+
+        union {
+                struct {
+                        u8 data_lines;
+                } dpi;
+
+                struct {
+                        u8 channel;
+                        u8 data_lines;
+                } rfbi;
+
+                struct {
+                        u8 datapairs;
+                } sdi;
+
+                struct {
+                        u8 clk_lane;
+                        u8 clk_pol;
+                        u8 data1_lane;
+                        u8 data1_pol;
+                        u8 data2_lane;
+                        u8 data2_pol;
+
+                        struct {
+                                u16 regn;
+                                u16 regm;
+                                u16 regm3;
+                                u16 regm4;
+
+                                u16 lp_clk_div;
+
+                                u16 lck_div;
+                                u16 pck_div;
+                        } div;
+
+                        bool ext_te;
+                        u8 ext_te_gpio;
+                } dsi;
+
+                struct {
+                        enum omap_dss_venc_type type;
+                        bool invert_polarity;
+                } venc;
+        } phy;
+
+        struct {
+                struct omap_video_timings timings;
+
+                int acbi;       /* ac-bias pin transitions per interrupt */
+                /* Unit: line clocks */
+                int acb;        /* ac-bias pin frequency */
+
+                enum omap_panel_config config;
+        } panel;
+
+        struct {
+                u8 pixel_size;
+                struct rfbi_timings rfbi_timings;
+        } ctrl;
+
+        int reset_gpio;
+
+        int max_backlight_level;
+
+        const char *name;
+
+        /* used to match device to driver */
+        const char *driver_name;
+
+        void *data;
+
+        struct omap_dss_driver *driver;
+
+        /* helper variable for driver suspend/resume */
+        bool activate_after_resume;
+
+        enum omap_display_caps caps;
+
+        struct omap_overlay_manager *manager;
+
+        enum omap_dss_display_state state;
+
+        /* platform specific  */
+        int (*platform_enable)(struct omap_dss_device *dssdev);
+        void (*platform_disable)(struct omap_dss_device *dssdev);
+        int (*set_backlight)(struct omap_dss_device *dssdev, int level);
+        int (*get_backlight)(struct omap_dss_device *dssdev);
+};
+
+struct omap_dss_driver {
+        struct device_driver driver;
+
+        int (*probe)(struct omap_dss_device *);
+        void (*remove)(struct omap_dss_device *);
+
+        int (*enable)(struct omap_dss_device *display);
+        void (*disable)(struct omap_dss_device *display);
+        int (*suspend)(struct omap_dss_device *display);
+        int (*resume)(struct omap_dss_device *display);
+        int (*run_test)(struct omap_dss_device *display, int test);
+
+        int (*set_update_mode)(struct omap_dss_device *dssdev,
+                        enum omap_dss_update_mode);
+        enum omap_dss_update_mode (*get_update_mode)(
+                        struct omap_dss_device *dssdev);
+
+        int (*update)(struct omap_dss_device *dssdev,
+                               u16 x, u16 y, u16 w, u16 h);
+        int (*sync)(struct omap_dss_device *dssdev);
+
+        int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
+        int (*get_te)(struct omap_dss_device *dssdev);
+
+        u8 (*get_rotate)(struct omap_dss_device *dssdev);
+        int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
+
+        bool (*get_mirror)(struct omap_dss_device *dssdev);
+        int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
+
+        int (*memory_read)(struct omap_dss_device *dssdev,
+                        void *buf, size_t size,
+                        u16 x, u16 y, u16 w, u16 h);
+
+        void (*get_resolution)(struct omap_dss_device *dssdev,
+                        u16 *xres, u16 *yres);
+        int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
+
+        int (*check_timings)(struct omap_dss_device *dssdev,
+                        struct omap_video_timings *timings);
+        void (*set_timings)(struct omap_dss_device *dssdev,
+                        struct omap_video_timings *timings);
+        void (*get_timings)(struct omap_dss_device *dssdev,
+                        struct omap_video_timings *timings);
+
+        int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
+        u32 (*get_wss)(struct omap_dss_device *dssdev);
+};
+
+int omap_dss_register_driver(struct omap_dss_driver *);
+void omap_dss_unregister_driver(struct omap_dss_driver *);
+
+int omap_dss_register_device(struct omap_dss_device *);
+void omap_dss_unregister_device(struct omap_dss_device *);
+
+void omap_dss_get_device(struct omap_dss_device *dssdev);
+void omap_dss_put_device(struct omap_dss_device *dssdev);
+#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
+struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
+struct omap_dss_device *omap_dss_find_device(void *data,
+                int (*match)(struct omap_dss_device *dssdev, void *data));
+
+int omap_dss_start_device(struct omap_dss_device *dssdev);
+void omap_dss_stop_device(struct omap_dss_device *dssdev);
+
+int omap_dss_get_num_overlay_managers(void);
+struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
+
+int omap_dss_get_num_overlays(void);
+struct omap_overlay *omap_dss_get_overlay(int num);
+
+void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
+                u16 *xres, u16 *yres);
+int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
+
+typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
+int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
+int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
+
+int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
+int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
+                unsigned long timeout);
+
+#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
+#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
+
+void omapdss_dsi_vc_enable_hs(int channel, bool enable);
+int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
+
+int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
+                                    u16 *x, u16 *y, u16 *w, u16 *h);
+int omap_dsi_update(struct omap_dss_device *dssdev,
+                int channel,
+                u16 x, u16 y, u16 w, u16 h,
+                void (*callback)(int, void *), void *data);
+
+int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
+void omapdss_dsi_display_disable(struct omap_dss_device *dssdev);
+
+int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
+void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
+void dpi_set_timings(struct omap_dss_device *dssdev,
+                        struct omap_video_timings *timings);
+int dpi_check_timings(struct omap_dss_device *dssdev,
+                        struct omap_video_timings *timings);
+
+int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
+void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
+
+int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
+void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
+int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
+                u16 *x, u16 *y, u16 *w, u16 *h);
+int omap_rfbi_update(struct omap_dss_device *dssdev,
+                u16 x, u16 y, u16 w, u16 h,
+                void (*callback)(void *), void *data);
+
+#endif
diff --git a/arch/arm/plat-omap/include/plat/dma-44xx.h b/arch/arm/plat-omap/include/plat/dma-44xx.h
new file mode 100644
index 000000000000..1f767cb2f38a
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/dma-44xx.h
@@ -0,0 +1,147 @@
+/*
+ * OMAP4 SDMA channel definitions
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Santosh Shilimkar (santosh.shilimkar@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ * Paul Walmsley (paul@pwsan.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_OMAP44XX_DMA_H
+#define __ARCH_ARM_MACH_OMAP2_OMAP44XX_DMA_H
+
+#define OMAP44XX_DMA_SYS_REQ0                   2
+#define OMAP44XX_DMA_SYS_REQ1                   3
+#define OMAP44XX_DMA_GPMC                       4
+#define OMAP44XX_DMA_DSS_DISPC_REQ              6
+#define OMAP44XX_DMA_SYS_REQ2                   7
+#define OMAP44XX_DMA_MCASP1_AXEVT               8
+#define OMAP44XX_DMA_ISS_REQ1                   9
+#define OMAP44XX_DMA_ISS_REQ2                   10
+#define OMAP44XX_DMA_MCASP1_AREVT               11
+#define OMAP44XX_DMA_ISS_REQ3                   12
+#define OMAP44XX_DMA_ISS_REQ4                   13
+#define OMAP44XX_DMA_DSS_RFBI_REQ               14
+#define OMAP44XX_DMA_SPI3_TX0                   15
+#define OMAP44XX_DMA_SPI3_RX0                   16
+#define OMAP44XX_DMA_MCBSP2_TX                  17
+#define OMAP44XX_DMA_MCBSP2_RX                  18
+#define OMAP44XX_DMA_MCBSP3_TX                  19
+#define OMAP44XX_DMA_MCBSP3_RX                  20
+#define OMAP44XX_DMA_C2C_SSCM_GPO0              21
+#define OMAP44XX_DMA_C2C_SSCM_GPO1              22
+#define OMAP44XX_DMA_SPI3_TX1                   23
+#define OMAP44XX_DMA_SPI3_RX1                   24
+#define OMAP44XX_DMA_I2C3_TX                    25
+#define OMAP44XX_DMA_I2C3_RX                    26
+#define OMAP44XX_DMA_I2C1_TX                    27
+#define OMAP44XX_DMA_I2C1_RX                    28
+#define OMAP44XX_DMA_I2C2_TX                    29
+#define OMAP44XX_DMA_I2C2_RX                    30
+#define OMAP44XX_DMA_MCBSP4_TX                  31
+#define OMAP44XX_DMA_MCBSP4_RX                  32
+#define OMAP44XX_DMA_MCBSP1_TX                  33
+#define OMAP44XX_DMA_MCBSP1_RX                  34
+#define OMAP44XX_DMA_SPI1_TX0                   35
+#define OMAP44XX_DMA_SPI1_RX0                   36
+#define OMAP44XX_DMA_SPI1_TX1                   37
+#define OMAP44XX_DMA_SPI1_RX1                   38
+#define OMAP44XX_DMA_SPI1_TX2                   39
+#define OMAP44XX_DMA_SPI1_RX2                   40
+#define OMAP44XX_DMA_SPI1_TX3                   41
+#define OMAP44XX_DMA_SPI1_RX3                   42
+#define OMAP44XX_DMA_SPI2_TX0                   43
+#define OMAP44XX_DMA_SPI2_RX0                   44
+#define OMAP44XX_DMA_SPI2_TX1                   45
+#define OMAP44XX_DMA_SPI2_RX1                   46
+#define OMAP44XX_DMA_MMC2_TX                    47
+#define OMAP44XX_DMA_MMC2_RX                    48
+#define OMAP44XX_DMA_UART1_TX                   49
+#define OMAP44XX_DMA_UART1_RX                   50
+#define OMAP44XX_DMA_UART2_TX                   51
+#define OMAP44XX_DMA_UART2_RX                   52
+#define OMAP44XX_DMA_UART3_TX                   53
+#define OMAP44XX_DMA_UART3_RX                   54
+#define OMAP44XX_DMA_UART4_TX                   55
+#define OMAP44XX_DMA_UART4_RX                   56
+#define OMAP44XX_DMA_MMC4_TX                    57
+#define OMAP44XX_DMA_MMC4_RX                    58
+#define OMAP44XX_DMA_MMC5_TX                    59
+#define OMAP44XX_DMA_MMC5_RX                    60
+#define OMAP44XX_DMA_MMC1_TX                    61
+#define OMAP44XX_DMA_MMC1_RX                    62
+#define OMAP44XX_DMA_SYS_REQ3                   64
+#define OMAP44XX_DMA_MCPDM_UP                   65
+#define OMAP44XX_DMA_MCPDM_DL                   66
+#define OMAP44XX_DMA_DMIC_REQ                   67
+#define OMAP44XX_DMA_C2C_SSCM_GPO2              68
+#define OMAP44XX_DMA_C2C_SSCM_GPO3              69
+#define OMAP44XX_DMA_SPI4_TX0                   70
+#define OMAP44XX_DMA_SPI4_RX0                   71
+#define OMAP44XX_DMA_DSS_DSI1_REQ0              72
+#define OMAP44XX_DMA_DSS_DSI1_REQ1              73
+#define OMAP44XX_DMA_DSS_DSI1_REQ2              74
+#define OMAP44XX_DMA_DSS_DSI1_REQ3              75
+#define OMAP44XX_DMA_DSS_HDMI_REQ               76
+#define OMAP44XX_DMA_MMC3_TX                    77
+#define OMAP44XX_DMA_MMC3_RX                    78
+#define OMAP44XX_DMA_USIM_TX                    79
+#define OMAP44XX_DMA_USIM_RX                    80
+#define OMAP44XX_DMA_DSS_DSI2_REQ0              81
+#define OMAP44XX_DMA_DSS_DSI2_REQ1              82
+#define OMAP44XX_DMA_DSS_DSI2_REQ2              83
+#define OMAP44XX_DMA_DSS_DSI2_REQ3              84
+#define OMAP44XX_DMA_SLIMBUS1_TX0               85
+#define OMAP44XX_DMA_SLIMBUS1_TX1               86
+#define OMAP44XX_DMA_SLIMBUS1_TX2               87
+#define OMAP44XX_DMA_SLIMBUS1_TX3               88
+#define OMAP44XX_DMA_SLIMBUS1_RX0               89
+#define OMAP44XX_DMA_SLIMBUS1_RX1               90
+#define OMAP44XX_DMA_SLIMBUS1_RX2               91
+#define OMAP44XX_DMA_SLIMBUS1_RX3               92
+#define OMAP44XX_DMA_SLIMBUS2_TX0               93
+#define OMAP44XX_DMA_SLIMBUS2_TX1               94
+#define OMAP44XX_DMA_SLIMBUS2_TX2               95
+#define OMAP44XX_DMA_SLIMBUS2_TX3               96
+#define OMAP44XX_DMA_SLIMBUS2_RX0               97
+#define OMAP44XX_DMA_SLIMBUS2_RX1               98
+#define OMAP44XX_DMA_SLIMBUS2_RX2               99
+#define OMAP44XX_DMA_SLIMBUS2_RX3               100
+#define OMAP44XX_DMA_ABE_REQ_0                  101
+#define OMAP44XX_DMA_ABE_REQ_1                  102
+#define OMAP44XX_DMA_ABE_REQ_2                  103
+#define OMAP44XX_DMA_ABE_REQ_3                  104
+#define OMAP44XX_DMA_ABE_REQ_4                  105
+#define OMAP44XX_DMA_ABE_REQ_5                  106
+#define OMAP44XX_DMA_ABE_REQ_6                  107
+#define OMAP44XX_DMA_ABE_REQ_7                  108
+#define OMAP44XX_DMA_AES1_P_CTX_IN_REQ          109
+#define OMAP44XX_DMA_AES1_P_DATA_IN_REQ         110
+#define OMAP44XX_DMA_AES1_P_DATA_OUT_REQ        111
+#define OMAP44XX_DMA_AES2_P_CTX_IN_REQ          112
+#define OMAP44XX_DMA_AES2_P_DATA_IN_REQ         113
+#define OMAP44XX_DMA_AES2_P_DATA_OUT_REQ        114
+#define OMAP44XX_DMA_DES_P_CTX_IN_REQ           115
+#define OMAP44XX_DMA_DES_P_DATA_IN_REQ          116
+#define OMAP44XX_DMA_DES_P_DATA_OUT_REQ         117
+#define OMAP44XX_DMA_SHA2_CTXIN_P               118
+#define OMAP44XX_DMA_SHA2_DIN_P                 119
+#define OMAP44XX_DMA_SHA2_CTXOUT_P              120
+#define OMAP44XX_DMA_AES1_P_CONTEXT_OUT_REQ     121
+#define OMAP44XX_DMA_AES2_P_CONTEXT_OUT_REQ     122
+#define OMAP44XX_DMA_I2C4_TX                    124
+#define OMAP44XX_DMA_I2C4_RX                    125
+
+#endif
diff --git a/arch/arm/plat-omap/include/mach/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index 72f680b7180d..02232ca2c37f 100644
--- a/arch/arm/plat-omap/include/mach/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -21,6 +21,9 @@
 #ifndef __ASM_ARCH_DMA_H
 #define __ASM_ARCH_DMA_H
 
+/* Move omap4 specific defines to dma-44xx.h */
+#include "dma-44xx.h"
+
 /* Hardware registers for omap1 */
 #define OMAP1_DMA_BASE                  (0xfffed800)
 
@@ -316,118 +319,8 @@
 #define OMAP34XX_DMA_USIM_TX            79      /* S_DMA_78 */
 #define OMAP34XX_DMA_USIM_RX            80      /* S_DMA_79 */
 
-/* DMA request lines for 44xx */
-#define OMAP44XX_DMA_DSS_DISPC_REQ      6       /* S_DMA_5 */
-#define OMAP44XX_DMA_SYS_REQ2           7       /* S_DMA_6 */
-#define OMAP44XX_DMA_ISS_REQ1           9       /* S_DMA_8 */
-#define OMAP44XX_DMA_ISS_REQ2           10      /* S_DMA_9 */
-#define OMAP44XX_DMA_ISS_REQ3           12      /* S_DMA_11 */
-#define OMAP44XX_DMA_ISS_REQ4           13      /* S_DMA_12 */
-#define OMAP44XX_DMA_DSS_RFBI_REQ       14      /* S_DMA_13 */
-#define OMAP44XX_DMA_SPI3_TX0           15      /* S_DMA_14 */
-#define OMAP44XX_DMA_SPI3_RX0           16      /* S_DMA_15 */
-#define OMAP44XX_DMA_MCBSP2_TX          17      /* S_DMA_16 */
-#define OMAP44XX_DMA_MCBSP2_RX          18      /* S_DMA_17 */
-#define OMAP44XX_DMA_MCBSP3_TX          19      /* S_DMA_18 */
-#define OMAP44XX_DMA_MCBSP3_RX          20      /* S_DMA_19 */
-#define OMAP44XX_DMA_SPI3_TX1           23      /* S_DMA_22 */
-#define OMAP44XX_DMA_SPI3_RX1           24      /* S_DMA_23 */
-#define OMAP44XX_DMA_I2C3_TX            25      /* S_DMA_24 */
-#define OMAP44XX_DMA_I2C3_RX            26      /* S_DMA_25 */
-#define OMAP44XX_DMA_I2C1_TX            27      /* S_DMA_26 */
-#define OMAP44XX_DMA_I2C1_RX            28      /* S_DMA_27 */
-#define OMAP44XX_DMA_I2C2_TX            29      /* S_DMA_28 */
-#define OMAP44XX_DMA_I2C2_RX            30      /* S_DMA_29 */
-#define OMAP44XX_DMA_MCBSP4_TX          31      /* S_DMA_30 */
-#define OMAP44XX_DMA_MCBSP4_RX          32      /* S_DMA_31 */
-#define OMAP44XX_DMA_MCBSP1_TX          33      /* S_DMA_32 */
-#define OMAP44XX_DMA_MCBSP1_RX          34      /* S_DMA_33 */
-#define OMAP44XX_DMA_SPI1_TX0           35      /* S_DMA_34 */
-#define OMAP44XX_DMA_SPI1_RX0           36      /* S_DMA_35 */
-#define OMAP44XX_DMA_SPI1_TX1           37      /* S_DMA_36 */
-#define OMAP44XX_DMA_SPI1_RX1           38      /* S_DMA_37 */
-#define OMAP44XX_DMA_SPI1_TX2           39      /* S_DMA_38 */
-#define OMAP44XX_DMA_SPI1_RX2           40      /* S_DMA_39 */
-#define OMAP44XX_DMA_SPI1_TX3           41      /* S_DMA_40 */
-#define OMAP44XX_DMA_SPI1_RX3           42      /* S_DMA_41 */
-#define OMAP44XX_DMA_SPI2_TX0           43      /* S_DMA_42 */
-#define OMAP44XX_DMA_SPI2_RX0           44      /* S_DMA_43 */
-#define OMAP44XX_DMA_SPI2_TX1           45      /* S_DMA_44 */
-#define OMAP44XX_DMA_SPI2_RX1           46      /* S_DMA_45 */
-#define OMAP44XX_DMA_MMC2_TX            47      /* S_DMA_46 */
-#define OMAP44XX_DMA_MMC2_RX            48      /* S_DMA_47 */
-#define OMAP44XX_DMA_UART1_TX           49      /* S_DMA_48 */
-#define OMAP44XX_DMA_UART1_RX           50      /* S_DMA_49 */
-#define OMAP44XX_DMA_UART2_TX           51      /* S_DMA_50 */
-#define OMAP44XX_DMA_UART2_RX           52      /* S_DMA_51 */
-#define OMAP44XX_DMA_UART3_TX           53      /* S_DMA_52 */
-#define OMAP44XX_DMA_UART3_RX           54      /* S_DMA_53 */
-#define OMAP44XX_DMA_UART4_TX           55      /* S_DMA_54 */
-#define OMAP44XX_DMA_UART4_RX           56      /* S_DMA_55 */
-#define OMAP44XX_DMA_MMC4_TX            57      /* S_DMA_56 */
-#define OMAP44XX_DMA_MMC4_RX            58      /* S_DMA_57 */
-#define OMAP44XX_DMA_MMC5_TX            59      /* S_DMA_58 */
-#define OMAP44XX_DMA_MMC5_RX            60      /* S_DMA_59 */
-#define OMAP44XX_DMA_MMC1_TX            61      /* S_DMA_60 */
-#define OMAP44XX_DMA_MMC1_RX            62      /* S_DMA_61 */
-#define OMAP44XX_DMA_SYS_REQ3           64      /* S_DMA_63 */
-#define OMAP44XX_DMA_MCPDM_UP           65      /* S_DMA_64 */
-#define OMAP44XX_DMA_MCPDM_DL           66      /* S_DMA_65 */
-#define OMAP44XX_DMA_SPI4_TX0           70      /* S_DMA_69 */
-#define OMAP44XX_DMA_SPI4_RX0           71      /* S_DMA_70 */
-#define OMAP44XX_DMA_DSS_DSI1_REQ0      72      /* S_DMA_71 */
-#define OMAP44XX_DMA_DSS_DSI1_REQ1      73      /* S_DMA_72 */
-#define OMAP44XX_DMA_DSS_DSI1_REQ2      74      /* S_DMA_73 */
-#define OMAP44XX_DMA_DSS_DSI1_REQ3      75      /* S_DMA_74 */
-#define OMAP44XX_DMA_DSS_HDMI_REQ       76      /* S_DMA_75 */
-#define OMAP44XX_DMA_MMC3_TX            77      /* S_DMA_76 */
-#define OMAP44XX_DMA_MMC3_RX            78      /* S_DMA_77 */
-#define OMAP44XX_DMA_USIM_TX            79      /* S_DMA_78 */
-#define OMAP44XX_DMA_USIM_RX            80      /* S_DMA_79 */
-#define OMAP44XX_DMA_DSS_DSI2_REQ0      81      /* S_DMA_80 */
-#define OMAP44XX_DMA_DSS_DSI2_REQ1      82      /* S_DMA_81 */
-#define OMAP44XX_DMA_DSS_DSI2_REQ2      83      /* S_DMA_82 */
-#define OMAP44XX_DMA_DSS_DSI2_REQ3      84      /* S_DMA_83 */
-#define OMAP44XX_DMA_ABE_REQ0           101     /* S_DMA_100 */
-#define OMAP44XX_DMA_ABE_REQ1           102     /* S_DMA_101 */
-#define OMAP44XX_DMA_ABE_REQ2           103     /* S_DMA_102 */
-#define OMAP44XX_DMA_ABE_REQ3           104     /* S_DMA_103 */
-#define OMAP44XX_DMA_ABE_REQ4           105     /* S_DMA_104 */
-#define OMAP44XX_DMA_ABE_REQ5           106     /* S_DMA_105 */
-#define OMAP44XX_DMA_ABE_REQ6           107     /* S_DMA_106 */
-#define OMAP44XX_DMA_ABE_REQ7           108     /* S_DMA_107 */
-#define OMAP44XX_DMA_I2C4_TX            124     /* S_DMA_123 */
-#define OMAP44XX_DMA_I2C4_RX            125     /* S_DMA_124 */
-
 /*----------------------------------------------------------------------------*/
 
-/* Hardware registers for LCD DMA */
-#define OMAP1510_DMA_LCD_BASE           (0xfffedb00)
-#define OMAP1510_DMA_LCD_CTRL           (OMAP1510_DMA_LCD_BASE + 0x00)
-#define OMAP1510_DMA_LCD_TOP_F1_L       (OMAP1510_DMA_LCD_BASE + 0x02)
-#define OMAP1510_DMA_LCD_TOP_F1_U       (OMAP1510_DMA_LCD_BASE + 0x04)
-#define OMAP1510_DMA_LCD_BOT_F1_L       (OMAP1510_DMA_LCD_BASE + 0x06)
-#define OMAP1510_DMA_LCD_BOT_F1_U       (OMAP1510_DMA_LCD_BASE + 0x08)
-
-#define OMAP1610_DMA_LCD_BASE           (0xfffee300)
-#define OMAP1610_DMA_LCD_CSDP           (OMAP1610_DMA_LCD_BASE + 0xc0)
-#define OMAP1610_DMA_LCD_CCR            (OMAP1610_DMA_LCD_BASE + 0xc2)
-#define OMAP1610_DMA_LCD_CTRL           (OMAP1610_DMA_LCD_BASE + 0xc4)
-#define OMAP1610_DMA_LCD_TOP_B1_L       (OMAP1610_DMA_LCD_BASE + 0xc8)
-#define OMAP1610_DMA_LCD_TOP_B1_U       (OMAP1610_DMA_LCD_BASE + 0xca)
-#define OMAP1610_DMA_LCD_BOT_B1_L       (OMAP1610_DMA_LCD_BASE + 0xcc)
-#define OMAP1610_DMA_LCD_BOT_B1_U       (OMAP1610_DMA_LCD_BASE + 0xce)
-#define OMAP1610_DMA_LCD_TOP_B2_L       (OMAP1610_DMA_LCD_BASE + 0xd0)
-#define OMAP1610_DMA_LCD_TOP_B2_U       (OMAP1610_DMA_LCD_BASE + 0xd2)
-#define OMAP1610_DMA_LCD_BOT_B2_L       (OMAP1610_DMA_LCD_BASE + 0xd4)
-#define OMAP1610_DMA_LCD_BOT_B2_U       (OMAP1610_DMA_LCD_BASE + 0xd6)
-#define OMAP1610_DMA_LCD_SRC_EI_B1      (OMAP1610_DMA_LCD_BASE + 0xd8)
-#define OMAP1610_DMA_LCD_SRC_FI_B1_L    (OMAP1610_DMA_LCD_BASE + 0xda)
-#define OMAP1610_DMA_LCD_SRC_EN_B1      (OMAP1610_DMA_LCD_BASE + 0xe0)
-#define OMAP1610_DMA_LCD_SRC_FN_B1      (OMAP1610_DMA_LCD_BASE + 0xe4)
-#define OMAP1610_DMA_LCD_LCH_CTRL       (OMAP1610_DMA_LCD_BASE + 0xea)
-#define OMAP1610_DMA_LCD_SRC_FI_B1_U    (OMAP1610_DMA_LCD_BASE + 0xf4)
-
 #define OMAP1_DMA_TOUT_IRQ              (1 << 0)
 #define OMAP_DMA_DROP_IRQ               (1 << 1)
 #define OMAP_DMA_HALF_IRQ               (1 << 2)
@@ -441,6 +334,8 @@
 #define OMAP2_DMA_SUPERVISOR_ERR_IRQ    (1 << 10)
 #define OMAP2_DMA_MISALIGNED_ERR_IRQ    (1 << 11)
 
+#define OMAP_DMA_CCR_EN                 (1 << 7)
+
 #define OMAP_DMA_DATA_TYPE_S8           0x00
 #define OMAP_DMA_DATA_TYPE_S16          0x01
 #define OMAP_DMA_DATA_TYPE_S32          0x02
@@ -503,14 +398,6 @@
 #define DMA_CH_PRIO_HIGH                0x1
 #define DMA_CH_PRIO_LOW                 0x0 /* Def */
 
-/* LCD DMA block numbers */
-enum {
-        OMAP_LCD_DMA_B1_TOP,
-        OMAP_LCD_DMA_B1_BOTTOM,
-        OMAP_LCD_DMA_B2_TOP,
-        OMAP_LCD_DMA_B2_BOTTOM
-};
-
 enum omap_dma_burst_mode {
         OMAP_DMA_DATA_BURST_DIS = 0,
         OMAP_DMA_DATA_BURST_4,
@@ -633,6 +520,11 @@ extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
 extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
 extern int omap_get_dma_index(int lch, int *ei, int *fi);
 
+void omap_dma_global_context_save(void);
+void omap_dma_global_context_restore(void);
+
+extern void omap_dma_disable_irq(int lch);
+
 /* Chaining APIs */
 #ifndef CONFIG_ARCH_OMAP1
 extern int omap_request_dma_chain(int dev_id, const char *dev_name,
@@ -656,20 +548,13 @@ extern int omap_modify_dma_chain_params(int chain_id,
 extern int omap_dma_chain_status(int chain_id);
 #endif
 
-/* LCD DMA functions */
-extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
-                                void *data);
-extern void omap_free_lcd_dma(void);
-extern void omap_setup_lcd_dma(void);
-extern void omap_enable_lcd_dma(void);
-extern void omap_stop_lcd_dma(void);
-extern void omap_set_lcd_dma_ext_controller(int external);
-extern void omap_set_lcd_dma_single_transfer(int single);
-extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
-                                int data_type);
-extern void omap_set_lcd_dma_b1_rotation(int rotate);
-extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres);
-extern void omap_set_lcd_dma_b1_mirror(int mirror);
-extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale);
+#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_FB_OMAP)
+#include <mach/lcd_dma.h>
+#else
+static inline int omap_lcd_dma_running(void)
+{
+        return 0;
+}
+#endif
 
 #endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/plat-omap/include/mach/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 20f1054c0a80..20f1054c0a80 100644
--- a/arch/arm/plat-omap/include/mach/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
diff --git a/arch/arm/plat-omap/include/mach/dsp_common.h b/arch/arm/plat-omap/include/plat/dsp_common.h
index da97736f3efa..da97736f3efa 100644
--- a/arch/arm/plat-omap/include/mach/dsp_common.h
+++ b/arch/arm/plat-omap/include/plat/dsp_common.h
diff --git a/arch/arm/plat-omap/include/plat/flash.h b/arch/arm/plat-omap/include/plat/flash.h
new file mode 100644
index 000000000000..3e6327016b40
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/flash.h
@@ -0,0 +1,16 @@
+/*
+ * Flash support for OMAP1
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __OMAP_FLASH_H
+#define __OMAP_FLASH_H
+
+#include <linux/mtd/map.h>
+
+extern void omap1_set_vpp(struct map_info *map, int enable);
+
+#endif
diff --git a/arch/arm/plat-omap/include/mach/fpga.h b/arch/arm/plat-omap/include/plat/fpga.h
index f1864a652f7a..f1864a652f7a 100644
--- a/arch/arm/plat-omap/include/mach/fpga.h
+++ b/arch/arm/plat-omap/include/plat/fpga.h
diff --git a/arch/arm/plat-omap/include/mach/gpio-switch.h b/arch/arm/plat-omap/include/plat/gpio-switch.h
index 10da0e07c0cf..10da0e07c0cf 100644
--- a/arch/arm/plat-omap/include/mach/gpio-switch.h
+++ b/arch/arm/plat-omap/include/plat/gpio-switch.h
diff --git a/arch/arm/plat-omap/include/mach/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index 633ff688b928..de7c54731cbe 100644
--- a/arch/arm/plat-omap/include/mach/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -76,7 +76,8 @@ extern void omap2_gpio_prepare_for_retention(void);
 extern void omap2_gpio_resume_after_retention(void);
 extern void omap_set_gpio_debounce(int gpio, int enable);
 extern void omap_set_gpio_debounce_time(int gpio, int enable);
-
+extern void omap_gpio_save_context(void);
+extern void omap_gpio_restore_context(void);
 /*-------------------------------------------------------------------------*/
 
 /* Wrappers for "new style" GPIO calls, using the new infrastructure
diff --git a/arch/arm/plat-omap/include/mach/gpmc-smc91x.h b/arch/arm/plat-omap/include/plat/gpmc-smc91x.h
index b64fbee4d567..b64fbee4d567 100644
--- a/arch/arm/plat-omap/include/mach/gpmc-smc91x.h
+++ b/arch/arm/plat-omap/include/plat/gpmc-smc91x.h
diff --git a/arch/arm/plat-omap/include/mach/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index 9c99cda77ba6..145838a81ef6 100644
--- a/arch/arm/plat-omap/include/mach/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -27,6 +27,8 @@
 
 #define GPMC_CONFIG             0x50
 #define GPMC_STATUS             0x54
+#define GPMC_CS0_BASE           0x60
+#define GPMC_CS_SIZE            0x30
 
 #define GPMC_CONFIG1_WRAPBURST_SUPP     (1 << 31)
 #define GPMC_CONFIG1_READMULTIPLE_SUPP  (1 << 30)
@@ -45,13 +47,14 @@
 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
-#define GPMC_CONFIG1_DEVICETYPE_NAND    GPMC_CONFIG1_DEVICETYPE(1)
+#define GPMC_CONFIG1_DEVICETYPE_NAND    GPMC_CONFIG1_DEVICETYPE(2)
 #define GPMC_CONFIG1_MUXADDDATA         (1 << 9)
 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
 #define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))
 #define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
+#define GPMC_CONFIG7_CSVALID            (1 << 6)
 
 /*
  * Note that all values in this struct are in nanoseconds, while
@@ -107,6 +110,8 @@ extern int gpmc_prefetch_enable(int cs, int dma_mode,
                                         unsigned int u32_count, int is_write);
 extern void gpmc_prefetch_reset(void);
 extern int gpmc_prefetch_status(void);
-extern void __init gpmc_init(void);
+extern void omap3_gpmc_save_context(void);
+extern void omap3_gpmc_restore_context(void);
+extern void gpmc_init(void);
 
 #endif
diff --git a/arch/arm/plat-omap/include/mach/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
index 26c1fbff08aa..d5b26adfb890 100644
--- a/arch/arm/plat-omap/include/mach/hardware.h
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -39,9 +39,9 @@
 #include <asm/sizes.h>
 #ifndef __ASSEMBLER__
 #include <asm/types.h>
-#include <mach/cpu.h>
+#include <plat/cpu.h>
 #endif
-#include <mach/serial.h>
+#include <plat/serial.h>
 
 /*
  * ---------------------------------------------------------------------------
@@ -280,11 +280,11 @@
  * ---------------------------------------------------------------------------
  */
 
-#include "omap730.h"
-#include "omap1510.h"
-#include "omap16xx.h"
-#include "omap24xx.h"
-#include "omap34xx.h"
-#include "omap44xx.h"
+#include <plat/omap7xx.h>
+#include <plat/omap1510.h>
+#include <plat/omap16xx.h>
+#include <plat/omap24xx.h>
+#include <plat/omap34xx.h>
+#include <plat/omap44xx.h>
 
 #endif  /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/mach/hwa742.h b/arch/arm/plat-omap/include/plat/hwa742.h
index 886248d32b49..886248d32b49 100644
--- a/arch/arm/plat-omap/include/mach/hwa742.h
+++ b/arch/arm/plat-omap/include/plat/hwa742.h
diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
new file mode 100644
index 000000000000..87f6bf2ea4fa
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/i2c.h
@@ -0,0 +1,38 @@
+/*
+ * Helper module for board specific I2C bus registration
+ *
+ * Copyright (C) 2009 Nokia Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/i2c.h>
+
+#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
+extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
+                                 struct i2c_board_info const *info,
+                                 unsigned len);
+#else
+static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
+                                 struct i2c_board_info const *info,
+                                 unsigned len)
+{
+        return 0;
+}
+#endif
+
+void __init omap1_i2c_mux_pins(int bus_id);
+void __init omap2_i2c_mux_pins(int bus_id);
diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/plat/io.h
index 8d32df32b0b1..128b549c2796 100644
--- a/arch/arm/plat-omap/include/mach/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -63,8 +63,24 @@
 #define OMAP1_IO_OFFSET         0x01000000      /* Virtual IO = 0xfefb0000 */
 #define OMAP1_IO_ADDRESS(pa)    IOMEM((pa) - OMAP1_IO_OFFSET)
 
-#define OMAP2_IO_OFFSET         0x90000000
-#define OMAP2_IO_ADDRESS(pa)    IOMEM((pa) + OMAP2_IO_OFFSET) /* L3 and L4 */
+#define OMAP2_L3_IO_OFFSET      0x90000000
+#define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
+
+
+#define OMAP2_L4_IO_OFFSET      0xb2000000
+#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
+
+#define OMAP4_L3_IO_OFFSET      0xb4000000
+#define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
+
+#define OMAP4_L3_PER_IO_OFFSET  0xb1100000
+#define OMAP4_L3_PER_IO_ADDRESS(pa)     IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
+
+#define OMAP4_GPMC_IO_OFFSET            0xa9000000
+#define OMAP4_GPMC_IO_ADDRESS(pa)       IOMEM((pa) + OMAP4_GPMC_IO_OFFSET)
+
+#define OMAP2_EMU_IO_OFFSET             0xaa800000      /* Emulation */
+#define OMAP2_EMU_IO_ADDRESS(pa)        IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
 
 /*
  * ----------------------------------------------------------------------------
@@ -83,36 +99,44 @@
  */
 
 /* We map both L3 and L4 on OMAP2 */
-#define L3_24XX_PHYS    L3_24XX_BASE    /* 0x68000000 */
-#define L3_24XX_VIRT    0xf8000000
+#define L3_24XX_PHYS    L3_24XX_BASE    /* 0x68000000 --> 0xf8000000*/
+#define L3_24XX_VIRT    (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET)
 #define L3_24XX_SIZE    SZ_1M           /* 44kB of 128MB used, want 1MB sect */
-#define L4_24XX_PHYS    L4_24XX_BASE    /* 0x48000000 */
-#define L4_24XX_VIRT    0xd8000000
+#define L4_24XX_PHYS    L4_24XX_BASE    /* 0x48000000 --> 0xfa000000 */
+#define L4_24XX_VIRT    (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET)
 #define L4_24XX_SIZE    SZ_1M           /* 1MB of 128MB used, want 1MB sect */
 
-#define L4_WK_243X_PHYS         L4_WK_243X_BASE         /* 0x49000000 */
-#define L4_WK_243X_VIRT         0xd9000000
+#define L4_WK_243X_PHYS         L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
+#define L4_WK_243X_VIRT         (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET)
 #define L4_WK_243X_SIZE         SZ_1M
-#define OMAP243X_GPMC_PHYS      OMAP243X_GPMC_BASE      /* 0x49000000 */
-#define OMAP243X_GPMC_VIRT      0xFE000000
+#define OMAP243X_GPMC_PHYS      OMAP243X_GPMC_BASE
+#define OMAP243X_GPMC_VIRT      (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
+                                                /* 0x6e000000 --> 0xfe000000 */
 #define OMAP243X_GPMC_SIZE      SZ_1M
 #define OMAP243X_SDRC_PHYS      OMAP243X_SDRC_BASE
-#define OMAP243X_SDRC_VIRT      0xFD000000
+                                                /* 0x6D000000 --> 0xfd000000 */
+#define OMAP243X_SDRC_VIRT      (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
 #define OMAP243X_SDRC_SIZE      SZ_1M
 #define OMAP243X_SMS_PHYS       OMAP243X_SMS_BASE
-#define OMAP243X_SMS_VIRT       0xFC000000
+                                                /* 0x6c000000 --> 0xfc000000 */
+#define OMAP243X_SMS_VIRT       (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
 #define OMAP243X_SMS_SIZE       SZ_1M
 
-/* DSP */
-#define DSP_MEM_24XX_PHYS       OMAP2420_DSP_MEM_BASE   /* 0x58000000 */
-#define DSP_MEM_24XX_VIRT       0xe0000000
-#define DSP_MEM_24XX_SIZE       0x28000
-#define DSP_IPI_24XX_PHYS       OMAP2420_DSP_IPI_BASE   /* 0x59000000 */
-#define DSP_IPI_24XX_VIRT       0xe1000000
-#define DSP_IPI_24XX_SIZE       SZ_4K
-#define DSP_MMU_24XX_PHYS       OMAP2420_DSP_MMU_BASE   /* 0x5a000000 */
-#define DSP_MMU_24XX_VIRT       0xe2000000
-#define DSP_MMU_24XX_SIZE       SZ_4K
+/* 2420 IVA */
+#define DSP_MEM_2420_PHYS       OMAP2420_DSP_MEM_BASE
+                                                /* 0x58000000 --> 0xfc100000 */
+#define DSP_MEM_2420_VIRT       0xfc100000
+#define DSP_MEM_2420_SIZE       0x28000
+#define DSP_IPI_2420_PHYS       OMAP2420_DSP_IPI_BASE
+                                                /* 0x59000000 --> 0xfc128000 */
+#define DSP_IPI_2420_VIRT       0xfc128000
+#define DSP_IPI_2420_SIZE       SZ_4K
+#define DSP_MMU_2420_PHYS       OMAP2420_DSP_MMU_BASE
+                                                /* 0x5a000000 --> 0xfc129000 */
+#define DSP_MMU_2420_VIRT       0xfc129000
+#define DSP_MMU_2420_SIZE       SZ_4K
+
+/* 2430 IVA2.1 - currently unmapped */
 
 /*
  * ----------------------------------------------------------------------------
@@ -121,12 +145,12 @@
  */
 
 /* We map both L3 and L4 on OMAP3 */
-#define L3_34XX_PHYS            L3_34XX_BASE    /* 0x68000000 */
-#define L3_34XX_VIRT            0xf8000000
+#define L3_34XX_PHYS            L3_34XX_BASE    /* 0x68000000 --> 0xf8000000 */
+#define L3_34XX_VIRT            (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET)
 #define L3_34XX_SIZE            SZ_1M   /* 44kB of 128MB used, want 1MB sect */
 
-#define L4_34XX_PHYS            L4_34XX_BASE    /* 0x48000000 */
-#define L4_34XX_VIRT            0xd8000000
+#define L4_34XX_PHYS            L4_34XX_BASE    /* 0x48000000 --> 0xfa000000 */
+#define L4_34XX_VIRT            (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET)
 #define L4_34XX_SIZE            SZ_4M   /* 1MB of 128MB used, want 1MB sect */
 
 /*
@@ -134,40 +158,32 @@
  * VPOM3430 was not working for Int controller
  */
 
-#define L4_WK_34XX_PHYS         L4_WK_34XX_BASE /* 0x48300000 */
-#define L4_WK_34XX_VIRT         0xd8300000
-#define L4_WK_34XX_SIZE         SZ_1M
-
-#define L4_PER_34XX_PHYS        L4_PER_34XX_BASE /* 0x49000000 */
-#define L4_PER_34XX_VIRT        0xd9000000
+#define L4_PER_34XX_PHYS        L4_PER_34XX_BASE
+                                                /* 0x49000000 --> 0xfb000000 */
+#define L4_PER_34XX_VIRT        (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET)
 #define L4_PER_34XX_SIZE        SZ_1M
 
-#define L4_EMU_34XX_PHYS        L4_EMU_34XX_BASE /* 0x54000000 */
-#define L4_EMU_34XX_VIRT        0xe4000000
-#define L4_EMU_34XX_SIZE        SZ_64M
+#define L4_EMU_34XX_PHYS        L4_EMU_34XX_BASE
+                                                /* 0x54000000 --> 0xfe800000 */
+#define L4_EMU_34XX_VIRT        (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET)
+#define L4_EMU_34XX_SIZE        SZ_8M
 
-#define OMAP34XX_GPMC_PHYS      OMAP34XX_GPMC_BASE /* 0x6E000000 */
-#define OMAP34XX_GPMC_VIRT      0xFE000000
+#define OMAP34XX_GPMC_PHYS      OMAP34XX_GPMC_BASE
+                                                /* 0x6e000000 --> 0xfe000000 */
+#define OMAP34XX_GPMC_VIRT      (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
 #define OMAP34XX_GPMC_SIZE      SZ_1M
 
-#define OMAP343X_SMS_PHYS       OMAP343X_SMS_BASE /* 0x6C000000 */
-#define OMAP343X_SMS_VIRT       0xFC000000
+#define OMAP343X_SMS_PHYS       OMAP343X_SMS_BASE
+                                                /* 0x6c000000 --> 0xfc000000 */
+#define OMAP343X_SMS_VIRT       (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
 #define OMAP343X_SMS_SIZE       SZ_1M
 
-#define OMAP343X_SDRC_PHYS      OMAP343X_SDRC_BASE /* 0x6D000000 */
-#define OMAP343X_SDRC_VIRT      0xFD000000
+#define OMAP343X_SDRC_PHYS      OMAP343X_SDRC_BASE
+                                                /* 0x6D000000 --> 0xfd000000 */
+#define OMAP343X_SDRC_VIRT      (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
 #define OMAP343X_SDRC_SIZE      SZ_1M
 
-/* DSP */
-#define DSP_MEM_34XX_PHYS       OMAP34XX_DSP_MEM_BASE   /* 0x58000000 */
-#define DSP_MEM_34XX_VIRT       0xe0000000
-#define DSP_MEM_34XX_SIZE       0x28000
-#define DSP_IPI_34XX_PHYS       OMAP34XX_DSP_IPI_BASE   /* 0x59000000 */
-#define DSP_IPI_34XX_VIRT       0xe1000000
-#define DSP_IPI_34XX_SIZE       SZ_4K
-#define DSP_MMU_34XX_PHYS       OMAP34XX_DSP_MMU_BASE   /* 0x5a000000 */
-#define DSP_MMU_34XX_VIRT       0xe2000000
-#define DSP_MMU_34XX_SIZE       SZ_4K
+/* 3430 IVA - currently unmapped */
 
 /*
  * ----------------------------------------------------------------------------
@@ -176,32 +192,49 @@
  */
 
 /* We map both L3 and L4 on OMAP4 */
-#define L3_44XX_PHYS            L3_44XX_BASE
-#define L3_44XX_VIRT            0xd4000000
+#define L3_44XX_PHYS            L3_44XX_BASE    /* 0x44000000 --> 0xf8000000 */
+#define L3_44XX_VIRT            (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET)
 #define L3_44XX_SIZE            SZ_1M
 
-#define L4_44XX_PHYS            L4_44XX_BASE
-#define L4_44XX_VIRT            0xda000000
+#define L4_44XX_PHYS            L4_44XX_BASE    /* 0x4a000000 --> 0xfc000000 */
+#define L4_44XX_VIRT            (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET)
 #define L4_44XX_SIZE            SZ_4M
 
-
-#define L4_WK_44XX_PHYS         L4_WK_44XX_BASE
-#define L4_WK_44XX_VIRT         0xda300000
-#define L4_WK_44XX_SIZE         SZ_1M
-
 #define L4_PER_44XX_PHYS        L4_PER_44XX_BASE
-#define L4_PER_44XX_VIRT        0xd8000000
+                                                /* 0x48000000 --> 0xfa000000 */
+#define L4_PER_44XX_VIRT        (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET)
 #define L4_PER_44XX_SIZE        SZ_4M
 
+#define L4_ABE_44XX_PHYS        L4_ABE_44XX_BASE
+                                                /* 0x49000000 --> 0xfb000000 */
+#define L4_ABE_44XX_VIRT        (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
+#define L4_ABE_44XX_SIZE        SZ_1M
+
 #define L4_EMU_44XX_PHYS        L4_EMU_44XX_BASE
-#define L4_EMU_44XX_VIRT        0xe4000000
-#define L4_EMU_44XX_SIZE        SZ_64M
+                                                /* 0x54000000 --> 0xfe800000 */
+#define L4_EMU_44XX_VIRT        (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET)
+#define L4_EMU_44XX_SIZE        SZ_8M
 
 #define OMAP44XX_GPMC_PHYS      OMAP44XX_GPMC_BASE
-#define OMAP44XX_GPMC_VIRT      0xe0000000
+                                                /* 0x50000000 --> 0xf9000000 */
+#define OMAP44XX_GPMC_VIRT      (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET)
 #define OMAP44XX_GPMC_SIZE      SZ_1M
 
 
+#define OMAP44XX_EMIF1_PHYS     OMAP44XX_EMIF1_BASE
+                                                /* 0x4c000000 --> 0xfd100000 */
+#define OMAP44XX_EMIF1_VIRT     (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET)
+#define OMAP44XX_EMIF1_SIZE     SZ_1M
+
+#define OMAP44XX_EMIF2_PHYS     OMAP44XX_EMIF2_BASE
+                                                /* 0x4d000000 --> 0xfd200000 */
+#define OMAP44XX_EMIF2_VIRT     (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET)
+#define OMAP44XX_EMIF2_SIZE     SZ_1M
+
+#define OMAP44XX_DMM_PHYS       OMAP44XX_DMM_BASE
+                                                /* 0x4e000000 --> 0xfd300000 */
+#define OMAP44XX_DMM_VIRT       (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
+#define OMAP44XX_DMM_SIZE       SZ_1M
 /*
  * ----------------------------------------------------------------------------
  * Omap specific register access
@@ -226,7 +259,38 @@ struct omap_sdrc_params;
 extern void omap1_map_common_io(void);
 extern void omap1_init_common_hw(void);
 
-extern void omap2_map_common_io(void);
+#ifdef CONFIG_ARCH_OMAP2420
+extern void omap242x_map_common_io(void);
+#else
+static inline void omap242x_map_common_io(void)
+{
+}
+#endif
+
+#ifdef CONFIG_ARCH_OMAP2430
+extern void omap243x_map_common_io(void);
+#else
+static inline void omap243x_map_common_io(void)
+{
+}
+#endif
+
+#ifdef CONFIG_ARCH_OMAP3
+extern void omap34xx_map_common_io(void);
+#else
+static inline void omap34xx_map_common_io(void)
+{
+}
+#endif
+
+#ifdef CONFIG_ARCH_OMAP4
+extern void omap44xx_map_common_io(void);
+#else
+static inline void omap44xx_map_common_io(void)
+{
+}
+#endif
+
 extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
                                  struct omap_sdrc_params *sdrc_cs1);
 
diff --git a/arch/arm/plat-omap/include/mach/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index 46d41ac83dbf..0752af9d099e 100644
--- a/arch/arm/plat-omap/include/mach/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -107,7 +107,7 @@ struct iommu_platform_data {
 #if defined(CONFIG_ARCH_OMAP1)
 #error "iommu for this processor not implemented yet"
 #else
-#include <mach/iommu2.h>
+#include <plat/iommu2.h>
 #endif
 
 /*
diff --git a/arch/arm/plat-omap/include/mach/iommu2.h b/arch/arm/plat-omap/include/plat/iommu2.h
index 10ad05f410e9..10ad05f410e9 100644
--- a/arch/arm/plat-omap/include/mach/iommu2.h
+++ b/arch/arm/plat-omap/include/plat/iommu2.h
diff --git a/arch/arm/plat-omap/include/mach/iovmm.h b/arch/arm/plat-omap/include/plat/iovmm.h
index bdc7ce5d7a4a..bdc7ce5d7a4a 100644
--- a/arch/arm/plat-omap/include/mach/iovmm.h
+++ b/arch/arm/plat-omap/include/plat/iovmm.h
diff --git a/arch/arm/plat-omap/include/mach/irda.h b/arch/arm/plat-omap/include/plat/irda.h
index 40f60339d1c6..40f60339d1c6 100644
--- a/arch/arm/plat-omap/include/mach/irda.h
+++ b/arch/arm/plat-omap/include/plat/irda.h
diff --git a/arch/arm/plat-omap/include/plat/irqs-44xx.h b/arch/arm/plat-omap/include/plat/irqs-44xx.h
new file mode 100644
index 000000000000..518322c80116
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/irqs-44xx.h
@@ -0,0 +1,144 @@
+/*
+ * OMAP4 Interrupt lines definitions
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Santosh Shilimkar (santosh.shilimkar@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H
+#define __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H
+
+/* OMAP44XX IRQs numbers definitions */
+#define OMAP44XX_IRQ_LOCALTIMER                 29
+#define OMAP44XX_IRQ_LOCALWDT                   30
+
+#define OMAP44XX_IRQ_GIC_START                  32
+
+#define OMAP44XX_IRQ_PL310                      (0 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_CTI0                       (1 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_CTI1                       (2 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_ELM                        (4 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SYS_1N                     (7 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SECURITY_EVENTS            (8 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_L3_DBG                     (9 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_L3_APP                     (10 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_PRCM                       (11 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SDMA_0                     (12 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SDMA_1                     (13 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SDMA_2                     (14 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SDMA_3                     (15 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_MCBSP4                     (16 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_MCBSP1                     (17 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SR_MCU                     (18 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SR_CORE                    (19 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPMC                       (20 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GFX                        (21 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_MCBSP2                     (22 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_MCBSP3                     (23 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_ISS_5                      (24 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_DSS_DISPC                  (25 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_MAIL_U0                    (26 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_C2C_SSCM_0                 (27 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_TESLA_MMU                  (28 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPIO1                      (29 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPIO2                      (30 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPIO3                      (31 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPIO4                      (32 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPIO5                      (33 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPIO6                      (34 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_USIM                       (35 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_WDT3                       (36 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPT1                       (37 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPT2                       (38 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPT3                       (39 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPT4                       (40 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPT5                       (41 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPT6                       (42 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPT7                       (43 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPT8                       (44 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPT9                       (45 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPT10                      (46 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPT11                      (47 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SPI4                       (48 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SHA1_S                     (49 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_FPKA_SINTREQUEST_S         (50 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SHA1_P                     (51 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_RNG                        (52 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_DSS_DSI1                   (53 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_I2C1                       (56 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_I2C2                       (57 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_HDQ                        (58 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_MMC5                       (59 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_I2C3                       (61 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_I2C4                       (62 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_AES2_S                     (63 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_AES2_P                     (64 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SPI1                       (65 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SPI2                       (66 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_HSI_P1                     (67 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_HSI_P2                     (68 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_FDIF_3                     (69 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_UART4                      (70 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_HSI_DMA                    (71 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_UART1                      (72 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_UART2                      (73 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_UART3                      (74 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_PBIAS                      (75 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_OHCI                       (76 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_EHCI                       (77 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_TLL                        (78 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_AES1_S                     (79 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_WDT2                       (80 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_DES_S                      (81 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_DES_P                      (82 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_MMC1                       (83 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_DSS_DSI2                   (84 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_AES1_P                     (85 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_MMC2                       (86 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_MPU_ICR                    (87 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_C2C_SSCM_1                 (88 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_FSUSB                      (89 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_FSUSB_SMI                  (90 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SPI3                       (91 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_HS_USB_MC_N                (92 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_HS_USB_DMA_N               (93 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_MMC3                       (94 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPT12                      (95 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_MMC4                       (96 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SLIMBUS1                   (97 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SLIMBUS2                   (98 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_ABE                        (99 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_DUCATI_MMU                 (100 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_DSS_HDMI                   (101 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SR_IVA                     (102 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_1     (103 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_0     (104 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_IVA_HD_POMBINTRPEND_0      (107 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_MCASP1_AR                  (108 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_MCASP1_AX                  (109 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_EMIF4_1                    (110 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_EMIF4_2                    (111 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_MCPDM                      (112 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_DMM                        (113 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_DMIC                       (114 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_CDMA_0                     (115 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_CDMA_1                     (116 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_CDMA_2                     (117 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_CDMA_3                     (118 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SYS_2N                     (119 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_KBD_CTL                    (120 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_UNIPRO1                    (124 + OMAP44XX_IRQ_GIC_START)
+
+#endif
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
new file mode 100644
index 000000000000..401701977dbb
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -0,0 +1,431 @@
+/*
+ *  arch/arm/plat-omap/include/mach/irqs.h
+ *
+ *  Copyright (C) Greg Lonnon 2001
+ *  Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
+ *
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
+ *       are different.
+ */
+
+#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
+#define __ASM_ARCH_OMAP15XX_IRQS_H
+
+/* All OMAP4 specific defines are moved to irqs-44xx.h */
+#include "irqs-44xx.h"
+
+/*
+ * IRQ numbers for interrupt handler 1
+ *
+ * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
+ *
+ */
+#define INT_CAMERA              1
+#define INT_FIQ                 3
+#define INT_RTDX                6
+#define INT_DSP_MMU_ABORT       7
+#define INT_HOST                8
+#define INT_ABORT               9
+#define INT_BRIDGE_PRIV         13
+#define INT_GPIO_BANK1          14
+#define INT_UART3               15
+#define INT_TIMER3              16
+#define INT_DMA_CH0_6           19
+#define INT_DMA_CH1_7           20
+#define INT_DMA_CH2_8           21
+#define INT_DMA_CH3             22
+#define INT_DMA_CH4             23
+#define INT_DMA_CH5             24
+#define INT_DMA_LCD             25
+#define INT_TIMER1              26
+#define INT_WD_TIMER            27
+#define INT_BRIDGE_PUB          28
+#define INT_TIMER2              30
+#define INT_LCD_CTRL            31
+
+/*
+ * OMAP-1510 specific IRQ numbers for interrupt handler 1
+ */
+#define INT_1510_IH2_IRQ        0
+#define INT_1510_RES2           2
+#define INT_1510_SPI_TX         4
+#define INT_1510_SPI_RX         5
+#define INT_1510_DSP_MAILBOX1   10
+#define INT_1510_DSP_MAILBOX2   11
+#define INT_1510_RES12          12
+#define INT_1510_LB_MMU         17
+#define INT_1510_RES18          18
+#define INT_1510_LOCAL_BUS      29
+
+/*
+ * OMAP-1610 specific IRQ numbers for interrupt handler 1
+ */
+#define INT_1610_IH2_IRQ        0
+#define INT_1610_IH2_FIQ        2
+#define INT_1610_McBSP2_TX      4
+#define INT_1610_McBSP2_RX      5
+#define INT_1610_DSP_MAILBOX1   10
+#define INT_1610_DSP_MAILBOX2   11
+#define INT_1610_LCD_LINE       12
+#define INT_1610_GPTIMER1       17
+#define INT_1610_GPTIMER2       18
+#define INT_1610_SSR_FIFO_0     29
+
+/*
+ * OMAP-7xx specific IRQ numbers for interrupt handler 1
+ */
+#define INT_7XX_IH2_FIQ         0
+#define INT_7XX_IH2_IRQ         1
+#define INT_7XX_USB_NON_ISO     2
+#define INT_7XX_USB_ISO         3
+#define INT_7XX_ICR             4
+#define INT_7XX_EAC             5
+#define INT_7XX_GPIO_BANK1      6
+#define INT_7XX_GPIO_BANK2      7
+#define INT_7XX_GPIO_BANK3      8
+#define INT_7XX_McBSP2TX        10
+#define INT_7XX_McBSP2RX        11
+#define INT_7XX_McBSP2RX_OVF    12
+#define INT_7XX_LCD_LINE        14
+#define INT_7XX_GSM_PROTECT     15
+#define INT_7XX_TIMER3          16
+#define INT_7XX_GPIO_BANK5      17
+#define INT_7XX_GPIO_BANK6      18
+#define INT_7XX_SPGIO_WR        29
+
+/*
+ * IRQ numbers for interrupt handler 2
+ *
+ * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
+ */
+#define IH2_BASE                32
+
+#define INT_KEYBOARD            (1 + IH2_BASE)
+#define INT_uWireTX             (2 + IH2_BASE)
+#define INT_uWireRX             (3 + IH2_BASE)
+#define INT_I2C                 (4 + IH2_BASE)
+#define INT_MPUIO               (5 + IH2_BASE)
+#define INT_USB_HHC_1           (6 + IH2_BASE)
+#define INT_McBSP3TX            (10 + IH2_BASE)
+#define INT_McBSP3RX            (11 + IH2_BASE)
+#define INT_McBSP1TX            (12 + IH2_BASE)
+#define INT_McBSP1RX            (13 + IH2_BASE)
+#define INT_UART1               (14 + IH2_BASE)
+#define INT_UART2               (15 + IH2_BASE)
+#define INT_BT_MCSI1TX          (16 + IH2_BASE)
+#define INT_BT_MCSI1RX          (17 + IH2_BASE)
+#define INT_SOSSI_MATCH         (19 + IH2_BASE)
+#define INT_USB_W2FC            (20 + IH2_BASE)
+#define INT_1WIRE               (21 + IH2_BASE)
+#define INT_OS_TIMER            (22 + IH2_BASE)
+#define INT_MMC                 (23 + IH2_BASE)
+#define INT_GAUGE_32K           (24 + IH2_BASE)
+#define INT_RTC_TIMER           (25 + IH2_BASE)
+#define INT_RTC_ALARM           (26 + IH2_BASE)
+#define INT_MEM_STICK           (27 + IH2_BASE)
+
+/*
+ * OMAP-1510 specific IRQ numbers for interrupt handler 2
+ */
+#define INT_1510_DSP_MMU        (28 + IH2_BASE)
+#define INT_1510_COM_SPI_RO     (31 + IH2_BASE)
+
+/*
+ * OMAP-1610 specific IRQ numbers for interrupt handler 2
+ */
+#define INT_1610_FAC            (0 + IH2_BASE)
+#define INT_1610_USB_HHC_2      (7 + IH2_BASE)
+#define INT_1610_USB_OTG        (8 + IH2_BASE)
+#define INT_1610_SoSSI          (9 + IH2_BASE)
+#define INT_1610_SoSSI_MATCH    (19 + IH2_BASE)
+#define INT_1610_DSP_MMU        (28 + IH2_BASE)
+#define INT_1610_McBSP2RX_OF    (31 + IH2_BASE)
+#define INT_1610_STI            (32 + IH2_BASE)
+#define INT_1610_STI_WAKEUP     (33 + IH2_BASE)
+#define INT_1610_GPTIMER3       (34 + IH2_BASE)
+#define INT_1610_GPTIMER4       (35 + IH2_BASE)
+#define INT_1610_GPTIMER5       (36 + IH2_BASE)
+#define INT_1610_GPTIMER6       (37 + IH2_BASE)
+#define INT_1610_GPTIMER7       (38 + IH2_BASE)
+#define INT_1610_GPTIMER8       (39 + IH2_BASE)
+#define INT_1610_GPIO_BANK2     (40 + IH2_BASE)
+#define INT_1610_GPIO_BANK3     (41 + IH2_BASE)
+#define INT_1610_MMC2           (42 + IH2_BASE)
+#define INT_1610_CF             (43 + IH2_BASE)
+#define INT_1610_WAKE_UP_REQ    (46 + IH2_BASE)
+#define INT_1610_GPIO_BANK4     (48 + IH2_BASE)
+#define INT_1610_SPI            (49 + IH2_BASE)
+#define INT_1610_DMA_CH6        (53 + IH2_BASE)
+#define INT_1610_DMA_CH7        (54 + IH2_BASE)
+#define INT_1610_DMA_CH8        (55 + IH2_BASE)
+#define INT_1610_DMA_CH9        (56 + IH2_BASE)
+#define INT_1610_DMA_CH10       (57 + IH2_BASE)
+#define INT_1610_DMA_CH11       (58 + IH2_BASE)
+#define INT_1610_DMA_CH12       (59 + IH2_BASE)
+#define INT_1610_DMA_CH13       (60 + IH2_BASE)
+#define INT_1610_DMA_CH14       (61 + IH2_BASE)
+#define INT_1610_DMA_CH15       (62 + IH2_BASE)
+#define INT_1610_NAND           (63 + IH2_BASE)
+#define INT_1610_SHA1MD5        (91 + IH2_BASE)
+
+/*
+ * OMAP-7xx specific IRQ numbers for interrupt handler 2
+ */
+#define INT_7XX_HW_ERRORS       (0 + IH2_BASE)
+#define INT_7XX_NFIQ_PWR_FAIL   (1 + IH2_BASE)
+#define INT_7XX_CFCD            (2 + IH2_BASE)
+#define INT_7XX_CFIREQ          (3 + IH2_BASE)
+#define INT_7XX_I2C             (4 + IH2_BASE)
+#define INT_7XX_PCC             (5 + IH2_BASE)
+#define INT_7XX_MPU_EXT_NIRQ    (6 + IH2_BASE)
+#define INT_7XX_SPI_100K_1      (7 + IH2_BASE)
+#define INT_7XX_SYREN_SPI       (8 + IH2_BASE)
+#define INT_7XX_VLYNQ           (9 + IH2_BASE)
+#define INT_7XX_GPIO_BANK4      (10 + IH2_BASE)
+#define INT_7XX_McBSP1TX        (11 + IH2_BASE)
+#define INT_7XX_McBSP1RX        (12 + IH2_BASE)
+#define INT_7XX_McBSP1RX_OF     (13 + IH2_BASE)
+#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
+#define INT_7XX_UART_MODEM_1    (15 + IH2_BASE)
+#define INT_7XX_MCSI            (16 + IH2_BASE)
+#define INT_7XX_uWireTX         (17 + IH2_BASE)
+#define INT_7XX_uWireRX         (18 + IH2_BASE)
+#define INT_7XX_SMC_CD          (19 + IH2_BASE)
+#define INT_7XX_SMC_IREQ        (20 + IH2_BASE)
+#define INT_7XX_HDQ_1WIRE       (21 + IH2_BASE)
+#define INT_7XX_TIMER32K        (22 + IH2_BASE)
+#define INT_7XX_MMC_SDIO        (23 + IH2_BASE)
+#define INT_7XX_UPLD            (24 + IH2_BASE)
+#define INT_7XX_USB_HHC_1       (27 + IH2_BASE)
+#define INT_7XX_USB_HHC_2       (28 + IH2_BASE)
+#define INT_7XX_USB_GENI        (29 + IH2_BASE)
+#define INT_7XX_USB_OTG         (30 + IH2_BASE)
+#define INT_7XX_CAMERA_IF       (31 + IH2_BASE)
+#define INT_7XX_RNG             (32 + IH2_BASE)
+#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
+#define INT_7XX_DBB_RF_EN       (34 + IH2_BASE)
+#define INT_7XX_MPUIO_KEYPAD    (35 + IH2_BASE)
+#define INT_7XX_SHA1_MD5        (36 + IH2_BASE)
+#define INT_7XX_SPI_100K_2      (37 + IH2_BASE)
+#define INT_7XX_RNG_IDLE        (38 + IH2_BASE)
+#define INT_7XX_MPUIO           (39 + IH2_BASE)
+#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF        (40 + IH2_BASE)
+#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
+#define INT_7XX_LLPC_OE_RISING  (42 + IH2_BASE)
+#define INT_7XX_LLPC_VSYNC      (43 + IH2_BASE)
+#define INT_7XX_WAKE_UP_REQ     (46 + IH2_BASE)
+#define INT_7XX_DMA_CH6         (53 + IH2_BASE)
+#define INT_7XX_DMA_CH7         (54 + IH2_BASE)
+#define INT_7XX_DMA_CH8         (55 + IH2_BASE)
+#define INT_7XX_DMA_CH9         (56 + IH2_BASE)
+#define INT_7XX_DMA_CH10        (57 + IH2_BASE)
+#define INT_7XX_DMA_CH11        (58 + IH2_BASE)
+#define INT_7XX_DMA_CH12        (59 + IH2_BASE)
+#define INT_7XX_DMA_CH13        (60 + IH2_BASE)
+#define INT_7XX_DMA_CH14        (61 + IH2_BASE)
+#define INT_7XX_DMA_CH15        (62 + IH2_BASE)
+#define INT_7XX_NAND            (63 + IH2_BASE)
+
+#define INT_24XX_SYS_NIRQ       7
+#define INT_24XX_SDMA_IRQ0      12
+#define INT_24XX_SDMA_IRQ1      13
+#define INT_24XX_SDMA_IRQ2      14
+#define INT_24XX_SDMA_IRQ3      15
+#define INT_24XX_CAM_IRQ        24
+#define INT_24XX_DSS_IRQ        25
+#define INT_24XX_MAIL_U0_MPU    26
+#define INT_24XX_DSP_UMA        27
+#define INT_24XX_DSP_MMU        28
+#define INT_24XX_GPIO_BANK1     29
+#define INT_24XX_GPIO_BANK2     30
+#define INT_24XX_GPIO_BANK3     31
+#define INT_24XX_GPIO_BANK4     32
+#define INT_24XX_GPIO_BANK5     33
+#define INT_24XX_MAIL_U3_MPU    34
+#define INT_24XX_GPTIMER1       37
+#define INT_24XX_GPTIMER2       38
+#define INT_24XX_GPTIMER3       39
+#define INT_24XX_GPTIMER4       40
+#define INT_24XX_GPTIMER5       41
+#define INT_24XX_GPTIMER6       42
+#define INT_24XX_GPTIMER7       43
+#define INT_24XX_GPTIMER8       44
+#define INT_24XX_GPTIMER9       45
+#define INT_24XX_GPTIMER10      46
+#define INT_24XX_GPTIMER11      47
+#define INT_24XX_GPTIMER12      48
+#define INT_24XX_SHA1MD5        51
+#define INT_24XX_MCBSP4_IRQ_TX  54
+#define INT_24XX_MCBSP4_IRQ_RX  55
+#define INT_24XX_I2C1_IRQ       56
+#define INT_24XX_I2C2_IRQ       57
+#define INT_24XX_HDQ_IRQ        58
+#define INT_24XX_MCBSP1_IRQ_TX  59
+#define INT_24XX_MCBSP1_IRQ_RX  60
+#define INT_24XX_MCBSP2_IRQ_TX  62
+#define INT_24XX_MCBSP2_IRQ_RX  63
+#define INT_24XX_SPI1_IRQ       65
+#define INT_24XX_SPI2_IRQ       66
+#define INT_24XX_UART1_IRQ      72
+#define INT_24XX_UART2_IRQ      73
+#define INT_24XX_UART3_IRQ      74
+#define INT_24XX_USB_IRQ_GEN    75
+#define INT_24XX_USB_IRQ_NISO   76
+#define INT_24XX_USB_IRQ_ISO    77
+#define INT_24XX_USB_IRQ_HGEN   78
+#define INT_24XX_USB_IRQ_HSOF   79
+#define INT_24XX_USB_IRQ_OTG    80
+#define INT_24XX_MCBSP5_IRQ_TX  81
+#define INT_24XX_MCBSP5_IRQ_RX  82
+#define INT_24XX_MMC_IRQ        83
+#define INT_24XX_MMC2_IRQ       86
+#define INT_24XX_MCBSP3_IRQ_TX  89
+#define INT_24XX_MCBSP3_IRQ_RX  90
+#define INT_24XX_SPI3_IRQ       91
+
+#define INT_243X_MCBSP2_IRQ     16
+#define INT_243X_MCBSP3_IRQ     17
+#define INT_243X_MCBSP4_IRQ     18
+#define INT_243X_MCBSP5_IRQ     19
+#define INT_243X_MCBSP1_IRQ     64
+#define INT_243X_HS_USB_MC      92
+#define INT_243X_HS_USB_DMA     93
+#define INT_243X_CARKIT_IRQ     94
+
+#define INT_34XX_BENCH_MPU_EMUL 3
+#define INT_34XX_ST_MCBSP2_IRQ  4
+#define INT_34XX_ST_MCBSP3_IRQ  5
+#define INT_34XX_SSM_ABORT_IRQ  6
+#define INT_34XX_SYS_NIRQ       7
+#define INT_34XX_D2D_FW_IRQ     8
+#define INT_34XX_PRCM_MPU_IRQ   11
+#define INT_34XX_MCBSP1_IRQ     16
+#define INT_34XX_MCBSP2_IRQ     17
+#define INT_34XX_MCBSP3_IRQ     22
+#define INT_34XX_MCBSP4_IRQ     23
+#define INT_34XX_CAM_IRQ        24
+#define INT_34XX_MCBSP5_IRQ     27
+#define INT_34XX_GPIO_BANK1     29
+#define INT_34XX_GPIO_BANK2     30
+#define INT_34XX_GPIO_BANK3     31
+#define INT_34XX_GPIO_BANK4     32
+#define INT_34XX_GPIO_BANK5     33
+#define INT_34XX_GPIO_BANK6     34
+#define INT_34XX_USIM_IRQ       35
+#define INT_34XX_WDT3_IRQ       36
+#define INT_34XX_SPI4_IRQ       48
+#define INT_34XX_SHA1MD52_IRQ   49
+#define INT_34XX_FPKA_READY_IRQ 50
+#define INT_34XX_SHA1MD51_IRQ   51
+#define INT_34XX_RNG_IRQ        52
+#define INT_34XX_I2C3_IRQ       61
+#define INT_34XX_FPKA_ERROR_IRQ 64
+#define INT_34XX_PBIAS_IRQ      75
+#define INT_34XX_OHCI_IRQ       76
+#define INT_34XX_EHCI_IRQ       77
+#define INT_34XX_TLL_IRQ        78
+#define INT_34XX_PARTHASH_IRQ   79
+#define INT_34XX_MMC3_IRQ       94
+#define INT_34XX_GPT12_IRQ      95
+
+#define INT_35XX_HECC0_IRQ              24
+#define INT_35XX_HECC1_IRQ              28
+#define INT_35XX_EMAC_C0_RXTHRESH_IRQ   67
+#define INT_35XX_EMAC_C0_RX_PULSE_IRQ   68
+#define INT_35XX_EMAC_C0_TX_PULSE_IRQ   69
+#define INT_35XX_EMAC_C0_MISC_PULSE_IRQ 70
+#define INT_35XX_USBOTG_IRQ             71
+#define INT_35XX_CCDC_VD0_IRQ           88
+#define INT_35XX_CCDC_VD1_IRQ           92
+#define INT_35XX_CCDC_VD2_IRQ           93
+
+/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
+ * 16 MPUIO lines */
+#define OMAP_MAX_GPIO_LINES     192
+#define IH_GPIO_BASE            (128 + IH2_BASE)
+#define IH_MPUIO_BASE           (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
+#define OMAP_IRQ_END            (IH_MPUIO_BASE + 16)
+
+/* External FPGA handles interrupts on Innovator boards */
+#define OMAP_FPGA_IRQ_BASE      (OMAP_IRQ_END)
+#ifdef  CONFIG_MACH_OMAP_INNOVATOR
+#define OMAP_FPGA_NR_IRQS       24
+#else
+#define OMAP_FPGA_NR_IRQS       0
+#endif
+#define OMAP_FPGA_IRQ_END       (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
+
+/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
+#define TWL4030_IRQ_BASE        (OMAP_FPGA_IRQ_END)
+#ifdef  CONFIG_TWL4030_CORE
+#define TWL4030_BASE_NR_IRQS    8
+#define TWL4030_PWR_NR_IRQS     8
+#else
+#define TWL4030_BASE_NR_IRQS    0
+#define TWL4030_PWR_NR_IRQS     0
+#endif
+#define TWL4030_IRQ_END         (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
+#define TWL4030_PWR_IRQ_BASE    TWL4030_IRQ_END
+#define TWL4030_PWR_IRQ_END     (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
+
+/* External TWL4030 gpio interrupts are optional */
+#define TWL4030_GPIO_IRQ_BASE   TWL4030_PWR_IRQ_END
+#ifdef  CONFIG_GPIO_TWL4030
+#define TWL4030_GPIO_NR_IRQS    18
+#else
+#define TWL4030_GPIO_NR_IRQS    0
+#endif
+#define TWL4030_GPIO_IRQ_END    (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
+
+#define TWL6030_IRQ_BASE        (OMAP_FPGA_IRQ_END)
+#ifdef CONFIG_TWL4030_CORE
+#define TWL6030_BASE_NR_IRQS    20
+#else
+#define TWL6030_BASE_NR_IRQS    0
+#endif
+#define TWL6030_IRQ_END         (TWL6030_IRQ_BASE + TWL6030_BASE_NR_IRQS)
+
+/* Total number of interrupts depends on the enabled blocks above */
+#if (TWL4030_GPIO_IRQ_END > TWL6030_IRQ_END)
+#define TWL_IRQ_END             TWL4030_GPIO_IRQ_END
+#else
+#define TWL_IRQ_END             TWL6030_IRQ_END
+#endif
+
+#define NR_IRQS                 TWL_IRQ_END
+
+#define OMAP_IRQ_BIT(irq)       (1 << ((irq) % 32))
+
+#define INTCPS_NR_MIR_REGS      3
+#define INTCPS_NR_IRQS          96
+
+#ifndef __ASSEMBLY__
+extern void omap_init_irq(void);
+extern int omap_irq_pending(void);
+void omap_intc_save_context(void);
+void omap_intc_restore_context(void);
+void omap3_intc_suspend(void);
+void omap3_intc_prepare_idle(void);
+void omap3_intc_resume_idle(void);
+#endif
+
+#include <mach/hardware.h>
+
+#endif
diff --git a/arch/arm/plat-omap/include/mach/keypad.h b/arch/arm/plat-omap/include/plat/keypad.h
index 3ae52ccc793c..3ae52ccc793c 100644
--- a/arch/arm/plat-omap/include/mach/keypad.h
+++ b/arch/arm/plat-omap/include/plat/keypad.h
diff --git a/arch/arm/plat-omap/include/mach/lcd_mipid.h b/arch/arm/plat-omap/include/plat/lcd_mipid.h
index 8e52c6572281..8e52c6572281 100644
--- a/arch/arm/plat-omap/include/mach/lcd_mipid.h
+++ b/arch/arm/plat-omap/include/plat/lcd_mipid.h
diff --git a/arch/arm/plat-omap/include/mach/led.h b/arch/arm/plat-omap/include/plat/led.h
index 25e451e7e2fd..25e451e7e2fd 100644
--- a/arch/arm/plat-omap/include/mach/led.h
+++ b/arch/arm/plat-omap/include/plat/led.h
diff --git a/arch/arm/plat-omap/include/mach/mailbox.h b/arch/arm/plat-omap/include/plat/mailbox.h
index b7a6991814ec..729166b76a7c 100644
--- a/arch/arm/plat-omap/include/mach/mailbox.h
+++ b/arch/arm/plat-omap/include/plat/mailbox.h
@@ -6,9 +6,9 @@
 #include <linux/wait.h>
 #include <linux/workqueue.h>
 #include <linux/blkdev.h>
+#include <linux/interrupt.h>
 
 typedef u32 mbox_msg_t;
-typedef void (mbox_receiver_t)(mbox_msg_t msg);
 struct omap_mbox;
 
 typedef int __bitwise omap_mbox_irq_t;
@@ -29,8 +29,10 @@ struct omap_mbox_ops {
         int             (*fifo_empty)(struct omap_mbox *mbox);
         int             (*fifo_full)(struct omap_mbox *mbox);
         /* irq */
-        void            (*enable_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
-        void            (*disable_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
+        void            (*enable_irq)(struct omap_mbox *mbox,
+                                                omap_mbox_irq_t irq);
+        void            (*disable_irq)(struct omap_mbox *mbox,
+                                                omap_mbox_irq_t irq);
         void            (*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
         int             (*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
         /* ctx */
@@ -42,6 +44,7 @@ struct omap_mbox_queue {
         spinlock_t              lock;
         struct request_queue    *queue;
         struct work_struct      work;
+        struct tasklet_struct   tasklet;
         int     (*callback)(void *);
         struct omap_mbox        *mbox;
 };
@@ -64,7 +67,7 @@ struct omap_mbox {
         void                    (*err_notify)(void);
 };
 
-int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg, void *);
+int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg);
 void omap_mbox_init_seq(struct omap_mbox *);
 
 struct omap_mbox *omap_mbox_get(const char *);
@@ -93,4 +96,16 @@ static inline void omap_mbox_restore_ctx(struct omap_mbox *mbox)
         mbox->ops->restore_ctx(mbox);
 }
 
+static inline void omap_mbox_enable_irq(struct omap_mbox *mbox,
+                                        omap_mbox_irq_t irq)
+{
+        mbox->ops->enable_irq(mbox, irq);
+}
+
+static inline void omap_mbox_disable_irq(struct omap_mbox *mbox,
+                                         omap_mbox_irq_t irq)
+{
+        mbox->ops->disable_irq(mbox, irq);
+}
+
 #endif /* MAILBOX_H */
diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index e0d6eca222cc..7de903d7c1ce 100644
--- a/arch/arm/plat-omap/include/mach/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -28,10 +28,10 @@
 #include <linux/spinlock.h>
 
 #include <mach/hardware.h>
-#include <mach/clock.h>
+#include <plat/clock.h>
 
-#define OMAP730_MCBSP1_BASE     0xfffb1000
-#define OMAP730_MCBSP2_BASE     0xfffb1800
+#define OMAP7XX_MCBSP1_BASE     0xfffb1000
+#define OMAP7XX_MCBSP2_BASE     0xfffb1800
 
 #define OMAP1510_MCBSP1_BASE    0xe1011800
 #define OMAP1510_MCBSP2_BASE    0xfffb1000
@@ -49,6 +49,9 @@
 
 #define OMAP34XX_MCBSP1_BASE    0x48074000
 #define OMAP34XX_MCBSP2_BASE    0x49022000
+#define OMAP34XX_MCBSP2_ST_BASE 0x49028000
+#define OMAP34XX_MCBSP3_BASE    0x49024000
+#define OMAP34XX_MCBSP3_ST_BASE 0x4902A000
 #define OMAP34XX_MCBSP3_BASE    0x49024000
 #define OMAP34XX_MCBSP4_BASE    0x49026000
 #define OMAP34XX_MCBSP5_BASE    0x48096000
@@ -56,9 +59,9 @@
 #define OMAP44XX_MCBSP1_BASE    0x49022000
 #define OMAP44XX_MCBSP2_BASE    0x49024000
 #define OMAP44XX_MCBSP3_BASE    0x49026000
-#define OMAP44XX_MCBSP4_BASE    0x48074000
+#define OMAP44XX_MCBSP4_BASE    0x48096000
 
-#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
+#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
 
 #define OMAP_MCBSP_REG_DRR2     0x00
 #define OMAP_MCBSP_REG_DRR1     0x02
@@ -103,8 +106,7 @@
 #define AUDIO_DMA_TX            OMAP_DMA_MCBSP1_TX
 #define AUDIO_DMA_RX            OMAP_DMA_MCBSP1_RX
 
-#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-        defined(CONFIG_ARCH_OMAP4)
+#else
 
 #define OMAP_MCBSP_REG_DRR2     0x00
 #define OMAP_MCBSP_REG_DRR1     0x04
@@ -147,6 +149,15 @@
 #define OMAP_MCBSP_REG_WAKEUPEN 0xA8
 #define OMAP_MCBSP_REG_XCCR     0xAC
 #define OMAP_MCBSP_REG_RCCR     0xB0
+#define OMAP_MCBSP_REG_SSELCR   0xBC
+
+#define OMAP_ST_REG_REV         0x00
+#define OMAP_ST_REG_SYSCONFIG   0x10
+#define OMAP_ST_REG_IRQSTATUS   0x18
+#define OMAP_ST_REG_IRQENABLE   0x1C
+#define OMAP_ST_REG_SGAINCR     0x24
+#define OMAP_ST_REG_SFIRCR      0x28
+#define OMAP_ST_REG_SSELCR      0x2C
 
 #define AUDIO_MCBSP_DATAWRITE   (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
 #define AUDIO_MCBSP_DATAREAD    (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
@@ -265,6 +276,24 @@
 #define ENAWAKEUP               0x0004
 #define SOFTRST                 0x0002
 
+/********************** McBSP SSELCR bit definitions ***********************/
+#define SIDETONEEN              0x0400
+
+/********************** McBSP Sidetone SYSCONFIG bit definitions ***********/
+#define ST_AUTOIDLE             0x0001
+
+/********************** McBSP Sidetone SGAINCR bit definitions *************/
+#define ST_CH1GAIN(value)       ((value<<16))   /* Bits 16:31 */
+#define ST_CH0GAIN(value)       (value)         /* Bits 0:15 */
+
+/********************** McBSP Sidetone SFIRCR bit definitions **************/
+#define ST_FIRCOEFF(value)      (value)         /* Bits 0:15 */
+
+/********************** McBSP Sidetone SSELCR bit definitions **************/
+#define ST_COEFFWRDONE          0x0004
+#define ST_COEFFWREN            0x0002
+#define ST_SIDETONEEN           0x0001
+
 /********************** McBSP DMA operating modes **************************/
 #define MCBSP_DMA_MODE_ELEMENT          0
 #define MCBSP_DMA_MODE_THRESHOLD        1
@@ -374,11 +403,23 @@ struct omap_mcbsp_platform_data {
         u8 dma_rx_sync, dma_tx_sync;
         u16 rx_irq, tx_irq;
         struct omap_mcbsp_ops *ops;
-#ifdef CONFIG_ARCH_OMAP34XX
+#ifdef CONFIG_ARCH_OMAP3
+        /* Sidetone block for McBSP 2 and 3 */
+        unsigned long phys_base_st;
         u16 buffer_size;
 #endif
 };
 
+struct omap_mcbsp_st_data {
+        void __iomem *io_base_st;
+        bool running;
+        bool enabled;
+        s16 taps[128];  /* Sidetone filter coefficients */
+        int nr_taps;    /* Number of filter coefficients in use */
+        s16 ch0gain;
+        s16 ch1gain;
+};
+
 struct omap_mcbsp {
         struct device *dev;
         unsigned long phys_base;
@@ -410,20 +451,22 @@ struct omap_mcbsp {
         struct omap_mcbsp_platform_data *pdata;
         struct clk *iclk;
         struct clk *fclk;
-#ifdef CONFIG_ARCH_OMAP34XX
+#ifdef CONFIG_ARCH_OMAP3
+        struct omap_mcbsp_st_data *st_data;
         int dma_op_mode;
         u16 max_tx_thres;
         u16 max_rx_thres;
 #endif
+        void *reg_cache;
 };
 extern struct omap_mcbsp **mcbsp_ptr;
-extern int omap_mcbsp_count;
+extern int omap_mcbsp_count, omap_mcbsp_cache_size;
 
 int omap_mcbsp_init(void);
 void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
                                         int size);
 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
-#ifdef CONFIG_ARCH_OMAP34XX
+#ifdef CONFIG_ARCH_OMAP3
 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
@@ -459,4 +502,21 @@ int omap_mcbsp_pollread(unsigned int id, u16 * buf);
 int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
 
+#ifdef CONFIG_ARCH_OMAP3
+/* Sidetone specific API */
+int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
+int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain);
+int omap_st_enable(unsigned int id);
+int omap_st_disable(unsigned int id);
+int omap_st_is_enabled(unsigned int id);
+#else
+static inline int omap_st_set_chgain(unsigned int id, int channel,
+                                     s16 chgain) { return 0; }
+static inline int omap_st_get_chgain(unsigned int id, int channel,
+                                     s16 *chgain) { return 0; }
+static inline int omap_st_enable(unsigned int id) { return 0; }
+static inline int omap_st_disable(unsigned int id) { return 0; }
+static inline int omap_st_is_enabled(unsigned int id) {  return 0; }
+#endif
+
 #endif
diff --git a/arch/arm/plat-omap/include/mach/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h
index 1254e4945b6f..1254e4945b6f 100644
--- a/arch/arm/plat-omap/include/mach/mcspi.h
+++ b/arch/arm/plat-omap/include/plat/mcspi.h
diff --git a/arch/arm/plat-omap/include/mach/memory.h b/arch/arm/plat-omap/include/plat/memory.h
index 9ad41dc484c1..d5306bee44b2 100644
--- a/arch/arm/plat-omap/include/mach/memory.h
+++ b/arch/arm/plat-omap/include/plat/memory.h
@@ -38,8 +38,7 @@
  */
 #if defined(CONFIG_ARCH_OMAP1)
 #define PHYS_OFFSET             UL(0x10000000)
-#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
-                        defined(CONFIG_ARCH_OMAP4)
+#else
 #define PHYS_OFFSET             UL(0x80000000)
 #endif
 
@@ -68,6 +67,13 @@
                 __dma = __dma - PHYS_OFFSET + OMAP1510_LB_OFFSET; \
            __dma; })
 
+#define __arch_dma_to_page(dev, addr)   \
+        ({ dma_addr_t __dma = addr;                             \
+           if (is_lbus_device(dev))                             \
+                __dma += PHYS_OFFSET - OMAP1510_LB_OFFSET;      \
+           phys_to_page(__dma);                                 \
+        })
+
 #define __arch_dma_to_virt(dev, addr)   ({ (void *) (is_lbus_device(dev) ? \
                                                 lbus_to_virt(addr) : \
                                                 __phys_to_virt(addr)); })
diff --git a/arch/arm/plat-omap/include/mach/menelaus.h b/arch/arm/plat-omap/include/plat/menelaus.h
index 3122bf68c7ce..4a970ec62dd1 100644
--- a/arch/arm/plat-omap/include/mach/menelaus.h
+++ b/arch/arm/plat-omap/include/plat/menelaus.h
@@ -40,7 +40,7 @@ extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV);
 
 extern int menelaus_set_regulator_sleep(int enable, u32 val);
 
-#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_MENELAUS)
+#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_MENELAUS)
 #define omap_has_menelaus()     1
 #else
 #define omap_has_menelaus()     0
diff --git a/arch/arm/plat-omap/include/mach/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index 7229b9593301..a1bac07c89eb 100644
--- a/arch/arm/plat-omap/include/mach/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -15,7 +15,7 @@
 #include <linux/device.h>
 #include <linux/mmc/host.h>
 
-#include <mach/board.h>
+#include <plat/board.h>
 
 #define OMAP15XX_NR_MMC         1
 #define OMAP16XX_NR_MMC         2
@@ -55,12 +55,12 @@ struct omap_mmc_platform_data {
         unsigned int max_freq;
 
         /* switch the bus to a new slot */
-        int (* switch_slot)(struct device *dev, int slot);
+        int (*switch_slot)(struct device *dev, int slot);
         /* initialize board-specific MMC functionality, can be NULL if
          * not supported */
-        int (* init)(struct device *dev);
-        void (* cleanup)(struct device *dev);
-        void (* shutdown)(struct device *dev);
+        int (*init)(struct device *dev);
+        void (*cleanup)(struct device *dev);
+        void (*shutdown)(struct device *dev);
 
         /* To handle board related suspend/resume functionality for MMC */
         int (*suspend)(struct device *dev, int slot);
@@ -96,14 +96,28 @@ struct omap_mmc_platform_data {
                 /* Try to sleep or power off when possible */
                 unsigned power_saving:1;
 
+                /* If using power_saving and the MMC power is not to go off */
+                unsigned no_off:1;
+
+                /* Regulator off remapped to sleep */
+                unsigned vcc_aux_disable_is_sleep:1;
+
                 int switch_pin;                 /* gpio (card detect) */
                 int gpio_wp;                    /* gpio (write protect) */
 
-                int (* set_bus_mode)(struct device *dev, int slot, int bus_mode);
-                int (* set_power)(struct device *dev, int slot, int power_on, int vdd);
-                int (* get_ro)(struct device *dev, int slot);
+                int (*set_bus_mode)(struct device *dev, int slot, int bus_mode);
+                int (*set_power)(struct device *dev, int slot,
+                                 int power_on, int vdd);
+                int (*get_ro)(struct device *dev, int slot);
                 int (*set_sleep)(struct device *dev, int slot, int sleep,
                                  int vdd, int cardsleep);
+                void (*remux)(struct device *dev, int slot, int power_on);
+                /* Call back before enabling / disabling regulators */
+                void (*before_set_reg)(struct device *dev, int slot,
+                                       int power_on, int vdd);
+                /* Call back after enabling / disabling regulators */
+                void (*after_set_reg)(struct device *dev, int slot,
+                                      int power_on, int vdd);
 
                 /* return MMC cover switch state, can be NULL if not supported.
                  *
@@ -111,14 +125,14 @@ struct omap_mmc_platform_data {
                  *   0 - closed
                  *   1 - open
                  */
-                int (* get_cover_state)(struct device *dev, int slot);
+                int (*get_cover_state)(struct device *dev, int slot);
 
                 const char *name;
                 u32 ocr_mask;
 
                 /* Card detection IRQs */
                 int card_detect_irq;
-                int (* card_detect)(int irq);
+                int (*card_detect)(struct device *dev, int slot);
 
                 unsigned int ban_openended:1;
 
@@ -126,7 +140,8 @@ struct omap_mmc_platform_data {
 };
 
 /* called from board-specific card detection service routine */
-extern void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed);
+extern void omap_mmc_notify_cover_event(struct device *dev, int slot,
+                                        int is_closed);
 
 #if     defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
         defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h
new file mode 100644
index 000000000000..f235d32cd942
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/multi.h
@@ -0,0 +1,94 @@
+/*
+ * Support for compiling in multiple OMAP processors
+ *
+ * Copyright (C) 2010 Nokia Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __PLAT_OMAP_MULTI_H
+#define __PLAT_OMAP_MULTI_H
+
+/*
+ * Test if multicore OMAP support is needed
+ */
+#undef MULTI_OMAP1
+#undef MULTI_OMAP2
+#undef OMAP_NAME
+
+#ifdef CONFIG_ARCH_OMAP730
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP1
+#  define MULTI_OMAP1
+# else
+#  define OMAP_NAME omap730
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP850
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP1
+#  define MULTI_OMAP1
+# else
+#  define OMAP_NAME omap850
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP15XX
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP1
+#  define MULTI_OMAP1
+# else
+#  define OMAP_NAME omap1510
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP16XX
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP1
+#  define MULTI_OMAP1
+# else
+#  define OMAP_NAME omap16xx
+# endif
+#endif
+#if (defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
+# if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
+#  error "OMAP1 and OMAP2 can't be selected at the same time"
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP2420
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME omap2420
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP2430
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME omap2430
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP3430
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME omap3430
+# endif
+#endif
+
+#endif  /* __PLAT_OMAP_MULTI_H */
diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/plat/mux.h
index 0f49d2d563d9..c7472a28ce24 100644
--- a/arch/arm/plat-omap/include/mach/mux.h
+++ b/arch/arm/plat-omap/include/plat/mux.h
@@ -51,23 +51,13 @@
                                         .pu_pd_reg = PU_PD_SEL_##reg, \
                                         .pu_pd_val = status,
 
-#define MUX_REG_730(reg, mode_offset, mode) .mux_reg_name = "OMAP730_IO_CONF_"#reg, \
-                                        .mux_reg = OMAP730_IO_CONF_##reg, \
+#define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
+                                        .mux_reg = OMAP7XX_IO_CONF_##reg, \
                                         .mask_offset = mode_offset, \
                                         .mask = mode,
 
-#define PULL_REG_730(reg, bit, status)  .pull_name = "OMAP730_IO_CONF_"#reg, \
-                                        .pull_reg = OMAP730_IO_CONF_##reg, \
-                                        .pull_bit = bit, \
-                                        .pull_val = status,
-
-#define MUX_REG_850(reg, mode_offset, mode) .mux_reg_name = "OMAP850_IO_CONF_"#reg, \
-                                        .mux_reg = OMAP850_IO_CONF_##reg, \
-                                        .mask_offset = mode_offset, \
-                                        .mask = mode,
-
-#define PULL_REG_850(reg, bit, status)  .pull_name = "OMAP850_IO_CONF_"#reg, \
-                                        .pull_reg = OMAP850_IO_CONF_##reg, \
+#define PULL_REG_7XX(reg, bit, status)  .pull_name = "OMAP7XX_IO_CONF_"#reg, \
+                                        .pull_reg = OMAP7XX_IO_CONF_##reg, \
                                         .pull_bit = bit, \
                                         .pull_val = status,
 
@@ -84,21 +74,12 @@
 #define PU_PD_REG(reg, status)          .pu_pd_reg = PU_PD_SEL_##reg, \
                                         .pu_pd_val = status,
 
-#define MUX_REG_730(reg, mode_offset, mode) \
-                                        .mux_reg = OMAP730_IO_CONF_##reg, \
-                                        .mask_offset = mode_offset, \
-                                        .mask = mode,
-
-#define PULL_REG_730(reg, bit, status)  .pull_reg = OMAP730_IO_CONF_##reg, \
-                                        .pull_bit = bit, \
-                                        .pull_val = status,
-
-#define MUX_REG_850(reg, mode_offset, mode) \
-                                        .mux_reg = OMAP850_IO_CONF_##reg, \
+#define MUX_REG_7XX(reg, mode_offset, mode) \
+                                        .mux_reg = OMAP7XX_IO_CONF_##reg, \
                                         .mask_offset = mode_offset, \
                                         .mask = mode,
 
-#define PULL_REG_850(reg, bit, status)  .pull_reg = OMAP850_IO_CONF_##reg, \
+#define PULL_REG_7XX(reg, bit, status)  .pull_reg = OMAP7XX_IO_CONF_##reg, \
                                         .pull_bit = bit, \
                                         .pull_val = status,
 
@@ -118,32 +99,21 @@
 
 /*
  * OMAP730/850 has a slightly different config for the pin mux.
- * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and
+ * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and
  *   not the FUNC_MUX_CTRL_x regs from hardware.h
  * - for pull-up/down, only has one enable bit which is is in the same register
  *   as mux config
  */
-#define MUX_CFG_730(desc, mux_reg, mode_offset, mode,   \
-                   pull_bit, pull_status, debug_status)\
-{                                                       \
-        .name =  desc,                                  \
-        .debug = debug_status,                          \
-        MUX_REG_730(mux_reg, mode_offset, mode)         \
-        PULL_REG_730(mux_reg, pull_bit, pull_status)    \
-        PU_PD_REG(NA, 0)                \
-},
-
-#define MUX_CFG_850(desc, mux_reg, mode_offset, mode,   \
+#define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode,   \
                    pull_bit, pull_status, debug_status)\
 {                                                       \
         .name =  desc,                                  \
         .debug = debug_status,                          \
-        MUX_REG_850(mux_reg, mode_offset, mode)         \
-        PULL_REG_850(mux_reg, pull_bit, pull_status)    \
+        MUX_REG_7XX(mux_reg, mode_offset, mode)         \
+        PULL_REG_7XX(mux_reg, pull_bit, pull_status)    \
         PU_PD_REG(NA, 0)                \
 },
 
-
 #define MUX_CFG_24XX(desc, reg_offset, mode,                    \
                                 pull_en, pull_mode, dbg)        \
 {                                                               \
@@ -160,59 +130,12 @@
 #define OMAP2_PULL_UP           (1 << 4)
 #define OMAP2_ALTELECTRICALSEL  (1 << 5)
 
-/* 34xx specific mux bit defines */
-#define OMAP3_INPUT_EN          (1 << 8)
-#define OMAP3_OFF_EN            (1 << 9)
-#define OMAP3_OFFOUT_EN         (1 << 10)
-#define OMAP3_OFFOUT_VAL        (1 << 11)
-#define OMAP3_OFF_PULL_EN       (1 << 12)
-#define OMAP3_OFF_PULL_UP       (1 << 13)
-#define OMAP3_WAKEUP_EN         (1 << 14)
-
-/* 34xx mux mode options for each pin. See TRM for options */
-#define OMAP34XX_MUX_MODE0      0
-#define OMAP34XX_MUX_MODE1      1
-#define OMAP34XX_MUX_MODE2      2
-#define OMAP34XX_MUX_MODE3      3
-#define OMAP34XX_MUX_MODE4      4
-#define OMAP34XX_MUX_MODE5      5
-#define OMAP34XX_MUX_MODE6      6
-#define OMAP34XX_MUX_MODE7      7
-
-/* 34xx active pin states */
-#define OMAP34XX_PIN_OUTPUT             0
-#define OMAP34XX_PIN_INPUT              OMAP3_INPUT_EN
-#define OMAP34XX_PIN_INPUT_PULLUP       (OMAP2_PULL_ENA | OMAP3_INPUT_EN \
-                                                | OMAP2_PULL_UP)
-#define OMAP34XX_PIN_INPUT_PULLDOWN     (OMAP2_PULL_ENA | OMAP3_INPUT_EN)
-
-/* 34xx off mode states */
-#define OMAP34XX_PIN_OFF_NONE           0
-#define OMAP34XX_PIN_OFF_OUTPUT_HIGH    (OMAP3_OFF_EN | OMAP3_OFFOUT_EN \
-                                                | OMAP3_OFFOUT_VAL)
-#define OMAP34XX_PIN_OFF_OUTPUT_LOW     (OMAP3_OFF_EN | OMAP3_OFFOUT_EN)
-#define OMAP34XX_PIN_OFF_INPUT_PULLUP   (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN \
-                                                | OMAP3_OFF_PULL_UP)
-#define OMAP34XX_PIN_OFF_INPUT_PULLDOWN (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN)
-#define OMAP34XX_PIN_OFF_WAKEUPENABLE   OMAP3_WAKEUP_EN
-
-#define MUX_CFG_34XX(desc, reg_offset, mux_value) {             \
-        .name           = desc,                                 \
-        .debug          = 0,                                    \
-        .mux_reg        = reg_offset,                           \
-        .mux_val        = mux_value                             \
-},
-
 struct pin_config {
         char                    *name;
         const unsigned int      mux_reg;
         unsigned char           debug;
 
-#if     defined(CONFIG_ARCH_OMAP34XX)
-        u16                     mux_val; /* Wake-up, off mode, pull, mux mode */
-#endif
-
-#if     defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
+#if     defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2)
         const unsigned char mask_offset;
         const unsigned char mask;
 
@@ -232,45 +155,44 @@ struct pin_config {
 
 };
 
-enum omap730_index {
+enum omap7xx_index {
         /* OMAP 730 keyboard */
-        E2_730_KBR0,
-        J7_730_KBR1,
-        E1_730_KBR2,
-        F3_730_KBR3,
-        D2_730_KBR4,
-        C2_730_KBC0,
-        D3_730_KBC1,
-        E4_730_KBC2,
-        F4_730_KBC3,
-        E3_730_KBC4,
-
-        /* USB */
-        AA17_730_USB_DM,
-        W16_730_USB_PU_EN,
-        W17_730_USB_VBUSI,
-};
-
-enum omap850_index {
-        /* OMAP 850 keyboard */
-        E2_850_KBR0,
-        J7_850_KBR1,
-        E1_850_KBR2,
-        F3_850_KBR3,
-        D2_850_KBR4,
-        C2_850_KBC0,
-        D3_850_KBC1,
-        E4_850_KBC2,
-        F4_850_KBC3,
-        E3_850_KBC4,
+        E2_7XX_KBR0,
+        J7_7XX_KBR1,
+        E1_7XX_KBR2,
+        F3_7XX_KBR3,
+        D2_7XX_KBR4,
+        C2_7XX_KBC0,
+        D3_7XX_KBC1,
+        E4_7XX_KBC2,
+        F4_7XX_KBC3,
+        E3_7XX_KBC4,
 
         /* USB */
-        AA17_850_USB_DM,
-        W16_850_USB_PU_EN,
-        W17_850_USB_VBUSI,
+        AA17_7XX_USB_DM,
+        W16_7XX_USB_PU_EN,
+        W17_7XX_USB_VBUSI,
+        W18_7XX_USB_DMCK_OUT,
+        W19_7XX_USB_DCRST,
+
+        /* MMC */
+        MMC_7XX_CMD,
+        MMC_7XX_CLK,
+        MMC_7XX_DAT0,
+
+        /* I2C */
+        I2C_7XX_SCL,
+        I2C_7XX_SDA,
+
+        /* SPI */
+        SPI_7XX_1,
+        SPI_7XX_2,
+        SPI_7XX_3,
+        SPI_7XX_4,
+        SPI_7XX_5,
+        SPI_7XX_6,
 };
 
-
 enum omap1xxx_index {
         /* UART1 (BT_UART_GATING)*/
         UART1_TX = 0,
@@ -726,172 +648,6 @@ enum omap24xx_index {
 
 };
 
-enum omap34xx_index {
-        /* 34xx I2C */
-        K21_34XX_I2C1_SCL,
-        J21_34XX_I2C1_SDA,
-        AF15_34XX_I2C2_SCL,
-        AE15_34XX_I2C2_SDA,
-        AF14_34XX_I2C3_SCL,
-        AG14_34XX_I2C3_SDA,
-        AD26_34XX_I2C4_SCL,
-        AE26_34XX_I2C4_SDA,
-
-        /* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
-        Y8_3430_USB1HS_PHY_CLK,
-        Y9_3430_USB1HS_PHY_STP,
-        AA14_3430_USB1HS_PHY_DIR,
-        AA11_3430_USB1HS_PHY_NXT,
-        W13_3430_USB1HS_PHY_DATA0,
-        W12_3430_USB1HS_PHY_DATA1,
-        W11_3430_USB1HS_PHY_DATA2,
-        Y11_3430_USB1HS_PHY_DATA3,
-        W9_3430_USB1HS_PHY_DATA4,
-        Y12_3430_USB1HS_PHY_DATA5,
-        W8_3430_USB1HS_PHY_DATA6,
-        Y13_3430_USB1HS_PHY_DATA7,
-
-        /* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
-        AA8_3430_USB2HS_PHY_CLK,
-        AA10_3430_USB2HS_PHY_STP,
-        AA9_3430_USB2HS_PHY_DIR,
-        AB11_3430_USB2HS_PHY_NXT,
-        AB10_3430_USB2HS_PHY_DATA0,
-        AB9_3430_USB2HS_PHY_DATA1,
-        W3_3430_USB2HS_PHY_DATA2,
-        T4_3430_USB2HS_PHY_DATA3,
-        T3_3430_USB2HS_PHY_DATA4,
-        R3_3430_USB2HS_PHY_DATA5,
-        R4_3430_USB2HS_PHY_DATA6,
-        T2_3430_USB2HS_PHY_DATA7,
-
-
-        /* TLL - HSUSB: 12-pin TLL Port 1*/
-        Y8_3430_USB1HS_TLL_CLK,
-        Y9_3430_USB1HS_TLL_STP,
-        AA14_3430_USB1HS_TLL_DIR,
-        AA11_3430_USB1HS_TLL_NXT,
-        W13_3430_USB1HS_TLL_DATA0,
-        W12_3430_USB1HS_TLL_DATA1,
-        W11_3430_USB1HS_TLL_DATA2,
-        Y11_3430_USB1HS_TLL_DATA3,
-        W9_3430_USB1HS_TLL_DATA4,
-        Y12_3430_USB1HS_TLL_DATA5,
-        W8_3430_USB1HS_TLL_DATA6,
-        Y13_3430_USB1HS_TLL_DATA7,
-
-        /* TLL - HSUSB: 12-pin TLL Port 2*/
-        AA8_3430_USB2HS_TLL_CLK,
-        AA10_3430_USB2HS_TLL_STP,
-        AA9_3430_USB2HS_TLL_DIR,
-        AB11_3430_USB2HS_TLL_NXT,
-        AB10_3430_USB2HS_TLL_DATA0,
-        AB9_3430_USB2HS_TLL_DATA1,
-        W3_3430_USB2HS_TLL_DATA2,
-        T4_3430_USB2HS_TLL_DATA3,
-        T3_3430_USB2HS_TLL_DATA4,
-        R3_3430_USB2HS_TLL_DATA5,
-        R4_3430_USB2HS_TLL_DATA6,
-        T2_3430_USB2HS_TLL_DATA7,
-
-        /* TLL - HSUSB: 12-pin TLL Port 3*/
-        AA6_3430_USB3HS_TLL_CLK,
-        AB3_3430_USB3HS_TLL_STP,
-        AA3_3430_USB3HS_TLL_DIR,
-        Y3_3430_USB3HS_TLL_NXT,
-        AA5_3430_USB3HS_TLL_DATA0,
-        Y4_3430_USB3HS_TLL_DATA1,
-        Y5_3430_USB3HS_TLL_DATA2,
-        W5_3430_USB3HS_TLL_DATA3,
-        AB12_3430_USB3HS_TLL_DATA4,
-        AB13_3430_USB3HS_TLL_DATA5,
-        AA13_3430_USB3HS_TLL_DATA6,
-        AA12_3430_USB3HS_TLL_DATA7,
-
-        /* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
-        AF10_3430_USB1FS_PHY_MM1_RXDP,
-        AG9_3430_USB1FS_PHY_MM1_RXDM,
-        W13_3430_USB1FS_PHY_MM1_RXRCV,
-        W12_3430_USB1FS_PHY_MM1_TXSE0,
-        W11_3430_USB1FS_PHY_MM1_TXDAT,
-        Y11_3430_USB1FS_PHY_MM1_TXEN_N,
-
-        /* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
-        AF7_3430_USB2FS_PHY_MM2_RXDP,
-        AH7_3430_USB2FS_PHY_MM2_RXDM,
-        AB10_3430_USB2FS_PHY_MM2_RXRCV,
-        AB9_3430_USB2FS_PHY_MM2_TXSE0,
-        W3_3430_USB2FS_PHY_MM2_TXDAT,
-        T4_3430_USB2FS_PHY_MM2_TXEN_N,
-
-        /* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
-        AH3_3430_USB3FS_PHY_MM3_RXDP,
-        AE3_3430_USB3FS_PHY_MM3_RXDM,
-        AD1_3430_USB3FS_PHY_MM3_RXRCV,
-        AE1_3430_USB3FS_PHY_MM3_TXSE0,
-        AD2_3430_USB3FS_PHY_MM3_TXDAT,
-        AC1_3430_USB3FS_PHY_MM3_TXEN_N,
-
-        /* 34xx GPIO
-         *  - normally these are bidirectional, no internal pullup/pulldown
-         *  - "_UP" suffix (GPIO3_UP) if internal pullup is configured
-         *  - "_DOWN" suffix (GPIO3_DOWN) with internal pulldown
-         *  - "_OUT" suffix (GPIO3_OUT) for output-only pins (unlike 24xx)
-         */
-        AF26_34XX_GPIO0,
-        AF22_34XX_GPIO9,
-        AG9_34XX_GPIO23,
-        AH8_34XX_GPIO29,
-        U8_34XX_GPIO54_OUT,
-        U8_34XX_GPIO54_DOWN,
-        L8_34XX_GPIO63,
-        G25_34XX_GPIO86_OUT,
-        AG4_34XX_GPIO134_OUT,
-        AF4_34XX_GPIO135_OUT,
-        AE4_34XX_GPIO136_OUT,
-        AF6_34XX_GPIO140_UP,
-        AE6_34XX_GPIO141,
-        AF5_34XX_GPIO142,
-        AE5_34XX_GPIO143,
-        H19_34XX_GPIO164_OUT,
-        J25_34XX_GPIO170,
-
-        /* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
-        H16_34XX_SDRC_CKE0,
-        H17_34XX_SDRC_CKE1,
-
-        /* MMC1 */
-        N28_3430_MMC1_CLK,
-        M27_3430_MMC1_CMD,
-        N27_3430_MMC1_DAT0,
-        N26_3430_MMC1_DAT1,
-        N25_3430_MMC1_DAT2,
-        P28_3430_MMC1_DAT3,
-        P27_3430_MMC1_DAT4,
-        P26_3430_MMC1_DAT5,
-        R27_3430_MMC1_DAT6,
-        R25_3430_MMC1_DAT7,
-
-        /* MMC2 */
-        AE2_3430_MMC2_CLK,
-        AG5_3430_MMC2_CMD,
-        AH5_3430_MMC2_DAT0,
-        AH4_3430_MMC2_DAT1,
-        AG4_3430_MMC2_DAT2,
-        AF4_3430_MMC2_DAT3,
-
-        /* MMC3 */
-        AF10_3430_MMC3_CLK,
-        AC3_3430_MMC3_CMD,
-        AE11_3430_MMC3_DAT0,
-        AH9_3430_MMC3_DAT1,
-        AF13_3430_MMC3_DAT2,
-        AF13_3430_MMC3_DAT3,
-
-        /* SYS_NIRQ T2 INT1 */
-        AF26_34XX_SYS_NIRQ,
-};
-
 struct omap_mux_cfg {
         struct pin_config       *pins;
         unsigned long           size;
@@ -901,14 +657,14 @@ struct omap_mux_cfg {
 #ifdef  CONFIG_OMAP_MUX
 /* setup pin muxing in Linux */
 extern int omap1_mux_init(void);
-extern int omap2_mux_init(void);
 extern int omap_mux_register(struct omap_mux_cfg *);
 extern int omap_cfg_reg(unsigned long reg_cfg);
 #else
 /* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
 static inline int omap1_mux_init(void) { return 0; }
-static inline int omap2_mux_init(void) { return 0; }
 static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
 #endif
 
+extern int omap2_mux_init(void);
+
 #endif
diff --git a/arch/arm/plat-omap/include/mach/nand.h b/arch/arm/plat-omap/include/plat/nand.h
index 631a7bed1eef..f8efd5466b1d 100644
--- a/arch/arm/plat-omap/include/mach/nand.h
+++ b/arch/arm/plat-omap/include/plat/nand.h
@@ -15,10 +15,25 @@ struct omap_nand_platform_data {
         int                     cs;
         int                     gpio_irq;
         struct mtd_partition    *parts;
+        struct gpmc_timings     *gpmc_t;
         int                     nr_parts;
-        int                     (*nand_setup)(void __iomem *);
+        int                     (*nand_setup)(void);
         int                     (*dev_ready)(struct omap_nand_platform_data *);
         int                     dma_channel;
+        unsigned long           phys_base;
         void __iomem            *gpmc_cs_baseaddr;
         void __iomem            *gpmc_baseaddr;
+        int                     devsize;
 };
+
+/* size (4 KiB) for IO mapping */
+#define NAND_IO_SIZE    SZ_4K
+
+#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
+extern int gpmc_nand_init(struct omap_nand_platform_data *d);
+#else
+static inline int gpmc_nand_init(struct omap_nand_platform_data *d)
+{
+        return 0;
+}
+#endif
diff --git a/arch/arm/plat-omap/include/mach/omap-alsa.h b/arch/arm/plat-omap/include/plat/omap-alsa.h
index bdf30a0f87f2..b53055b390d0 100644
--- a/arch/arm/plat-omap/include/mach/omap-alsa.h
+++ b/arch/arm/plat-omap/include/plat/omap-alsa.h
@@ -40,10 +40,10 @@
 #ifndef __OMAP_ALSA_H
 #define __OMAP_ALSA_H
 
-#include <mach/dma.h>
+#include <plat/dma.h>
 #include <sound/core.h>
 #include <sound/pcm.h>
-#include <mach/mcbsp.h>
+#include <plat/mcbsp.h>
 #include <linux/platform_device.h>
 
 #define DMA_BUF_SIZE    (1024 * 8)
diff --git a/arch/arm/plat-omap/include/mach/omap-pm.h b/arch/arm/plat-omap/include/plat/omap-pm.h
index 3ee41d711492..3ee41d711492 100644
--- a/arch/arm/plat-omap/include/mach/omap-pm.h
+++ b/arch/arm/plat-omap/include/plat/omap-pm.h
diff --git a/arch/arm/plat-omap/include/mach/omap1510.h b/arch/arm/plat-omap/include/plat/omap1510.h
index d24004668138..d24004668138 100644
--- a/arch/arm/plat-omap/include/mach/omap1510.h
+++ b/arch/arm/plat-omap/include/plat/omap1510.h
diff --git a/arch/arm/plat-omap/include/mach/omap16xx.h b/arch/arm/plat-omap/include/plat/omap16xx.h
index 0e69b504c25f..e69e1d857b45 100644
--- a/arch/arm/plat-omap/include/mach/omap16xx.h
+++ b/arch/arm/plat-omap/include/plat/omap16xx.h
@@ -124,44 +124,44 @@
 #define TIPB_SWITCH_BASE                 (0xfffbc800)
 #define OMAP16XX_MMCSD2_SSW_MPU_CONF    (TIPB_SWITCH_BASE + 0x160)
 
-/* UART3 Registers Maping through MPU bus */
-#define UART3_RHR               (OMAP_UART3_BASE + 0)
-#define UART3_THR               (OMAP_UART3_BASE + 0)
-#define UART3_DLL               (OMAP_UART3_BASE + 0)
-#define UART3_IER               (OMAP_UART3_BASE + 4)
-#define UART3_DLH               (OMAP_UART3_BASE + 4)
-#define UART3_IIR               (OMAP_UART3_BASE + 8)
-#define UART3_FCR               (OMAP_UART3_BASE + 8)
-#define UART3_EFR               (OMAP_UART3_BASE + 8)
-#define UART3_LCR               (OMAP_UART3_BASE + 0x0C)
-#define UART3_MCR               (OMAP_UART3_BASE + 0x10)
-#define UART3_XON1_ADDR1        (OMAP_UART3_BASE + 0x10)
-#define UART3_XON2_ADDR2        (OMAP_UART3_BASE + 0x14)
-#define UART3_LSR               (OMAP_UART3_BASE + 0x14)
-#define UART3_TCR               (OMAP_UART3_BASE + 0x18)
-#define UART3_MSR               (OMAP_UART3_BASE + 0x18)
-#define UART3_XOFF1             (OMAP_UART3_BASE + 0x18)
-#define UART3_XOFF2             (OMAP_UART3_BASE + 0x1C)
-#define UART3_SPR               (OMAP_UART3_BASE + 0x1C)
-#define UART3_TLR               (OMAP_UART3_BASE + 0x1C)
-#define UART3_MDR1              (OMAP_UART3_BASE + 0x20)
-#define UART3_MDR2              (OMAP_UART3_BASE + 0x24)
-#define UART3_SFLSR             (OMAP_UART3_BASE + 0x28)
-#define UART3_TXFLL             (OMAP_UART3_BASE + 0x28)
-#define UART3_RESUME            (OMAP_UART3_BASE + 0x2C)
-#define UART3_TXFLH             (OMAP_UART3_BASE + 0x2C)
-#define UART3_SFREGL            (OMAP_UART3_BASE + 0x30)
-#define UART3_RXFLL             (OMAP_UART3_BASE + 0x30)
-#define UART3_SFREGH            (OMAP_UART3_BASE + 0x34)
-#define UART3_RXFLH             (OMAP_UART3_BASE + 0x34)
-#define UART3_BLR               (OMAP_UART3_BASE + 0x38)
-#define UART3_ACREG             (OMAP_UART3_BASE + 0x3C)
-#define UART3_DIV16             (OMAP_UART3_BASE + 0x3C)
-#define UART3_SCR               (OMAP_UART3_BASE + 0x40)
-#define UART3_SSR               (OMAP_UART3_BASE + 0x44)
-#define UART3_EBLR              (OMAP_UART3_BASE + 0x48)
-#define UART3_OSC_12M_SEL       (OMAP_UART3_BASE + 0x4C)
-#define UART3_MVR               (OMAP_UART3_BASE + 0x50)
+/* UART3 Registers Mapping through MPU bus */
+#define UART3_RHR               (OMAP1_UART3_BASE + 0)
+#define UART3_THR               (OMAP1_UART3_BASE + 0)
+#define UART3_DLL               (OMAP1_UART3_BASE + 0)
+#define UART3_IER               (OMAP1_UART3_BASE + 4)
+#define UART3_DLH               (OMAP1_UART3_BASE + 4)
+#define UART3_IIR               (OMAP1_UART3_BASE + 8)
+#define UART3_FCR               (OMAP1_UART3_BASE + 8)
+#define UART3_EFR               (OMAP1_UART3_BASE + 8)
+#define UART3_LCR               (OMAP1_UART3_BASE + 0x0C)
+#define UART3_MCR               (OMAP1_UART3_BASE + 0x10)
+#define UART3_XON1_ADDR1        (OMAP1_UART3_BASE + 0x10)
+#define UART3_XON2_ADDR2        (OMAP1_UART3_BASE + 0x14)
+#define UART3_LSR               (OMAP1_UART3_BASE + 0x14)
+#define UART3_TCR               (OMAP1_UART3_BASE + 0x18)
+#define UART3_MSR               (OMAP1_UART3_BASE + 0x18)
+#define UART3_XOFF1             (OMAP1_UART3_BASE + 0x18)
+#define UART3_XOFF2             (OMAP1_UART3_BASE + 0x1C)
+#define UART3_SPR               (OMAP1_UART3_BASE + 0x1C)
+#define UART3_TLR               (OMAP1_UART3_BASE + 0x1C)
+#define UART3_MDR1              (OMAP1_UART3_BASE + 0x20)
+#define UART3_MDR2              (OMAP1_UART3_BASE + 0x24)
+#define UART3_SFLSR             (OMAP1_UART3_BASE + 0x28)
+#define UART3_TXFLL             (OMAP1_UART3_BASE + 0x28)
+#define UART3_RESUME            (OMAP1_UART3_BASE + 0x2C)
+#define UART3_TXFLH             (OMAP1_UART3_BASE + 0x2C)
+#define UART3_SFREGL            (OMAP1_UART3_BASE + 0x30)
+#define UART3_RXFLL             (OMAP1_UART3_BASE + 0x30)
+#define UART3_SFREGH            (OMAP1_UART3_BASE + 0x34)
+#define UART3_RXFLH             (OMAP1_UART3_BASE + 0x34)
+#define UART3_BLR               (OMAP1_UART3_BASE + 0x38)
+#define UART3_ACREG             (OMAP1_UART3_BASE + 0x3C)
+#define UART3_DIV16             (OMAP1_UART3_BASE + 0x3C)
+#define UART3_SCR               (OMAP1_UART3_BASE + 0x40)
+#define UART3_SSR               (OMAP1_UART3_BASE + 0x44)
+#define UART3_EBLR              (OMAP1_UART3_BASE + 0x48)
+#define UART3_OSC_12M_SEL       (OMAP1_UART3_BASE + 0x4C)
+#define UART3_MVR               (OMAP1_UART3_BASE + 0x50)
 
 /*
  * ---------------------------------------------------------------------------
diff --git a/arch/arm/plat-omap/include/mach/omap24xx.h b/arch/arm/plat-omap/include/plat/omap24xx.h
index 696edfc145a6..7055672a8c68 100644
--- a/arch/arm/plat-omap/include/mach/omap24xx.h
+++ b/arch/arm/plat-omap/include/plat/omap24xx.h
@@ -23,8 +23,8 @@
  *
  */
 
-#ifndef __ASM_ARCH_OMAP24XX_H
-#define __ASM_ARCH_OMAP24XX_H
+#ifndef __ASM_ARCH_OMAP2_H
+#define __ASM_ARCH_OMAP2_H
 
 /*
  * Please place only base defines here and put the rest in device
@@ -85,5 +85,5 @@
 #define OMAP24XX_SEC_AES_BASE   (OMAP24XX_SEC_BASE + 0x6000)
 #define OMAP24XX_SEC_PKA_BASE   (OMAP24XX_SEC_BASE + 0x8000)
 
-#endif /* __ASM_ARCH_OMAP24XX_H */
+#endif /* __ASM_ARCH_OMAP2_H */
 
diff --git a/arch/arm/plat-omap/include/mach/omap34xx.h b/arch/arm/plat-omap/include/plat/omap34xx.h
index f8d186a73712..2845fdc658b0 100644
--- a/arch/arm/plat-omap/include/mach/omap34xx.h
+++ b/arch/arm/plat-omap/include/plat/omap34xx.h
@@ -21,8 +21,8 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
-#ifndef __ASM_ARCH_OMAP34XX_H
-#define __ASM_ARCH_OMAP34XX_H
+#ifndef __ASM_ARCH_OMAP3_H
+#define __ASM_ARCH_OMAP3_H
 
 /*
  * Please place only base defines here and put the rest in device
@@ -72,16 +72,15 @@
 #define OMAP3430_ISP_CSI2A_END          (OMAP3430_ISP_CSI2A_BASE   + 0x16F)
 #define OMAP3430_ISP_CSI2PHY_END        (OMAP3430_ISP_CSI2PHY_BASE + 0x007)
 
-#define OMAP34XX_IVA_INTC_BASE  0x40000000
 #define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
-#define OMAP34XX_HSUSB_HOST_BASE        (L4_34XX_BASE + 0x64000)
 #define OMAP34XX_USBTLL_BASE    (L4_34XX_BASE + 0x62000)
+#define OMAP34XX_UHH_CONFIG_BASE        (L4_34XX_BASE + 0x64000)
+#define OMAP34XX_OHCI_BASE      (L4_34XX_BASE + 0x64400)
+#define OMAP34XX_EHCI_BASE      (L4_34XX_BASE + 0x64800)
+#define OMAP34XX_SR1_BASE       0x480C9000
+#define OMAP34XX_SR2_BASE       0x480CB000
 
 #define OMAP34XX_MAILBOX_BASE           (L4_34XX_BASE + 0x94000)
 
-#define OMAP34XX_DSP_BASE       0x58000000
-#define OMAP34XX_DSP_MEM_BASE   (OMAP34XX_DSP_BASE + 0x0)
-#define OMAP34XX_DSP_IPI_BASE   (OMAP34XX_DSP_BASE + 0x1000000)
-#define OMAP34XX_DSP_MMU_BASE   (OMAP34XX_DSP_BASE + 0x2000000)
-#endif /* __ASM_ARCH_OMAP34XX_H */
+#endif /* __ASM_ARCH_OMAP3_H */
 
diff --git a/arch/arm/plat-omap/include/mach/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
index b3ba5ac7b4a4..b3ef1a7f53cc 100644
--- a/arch/arm/plat-omap/include/mach/omap44xx.h
+++ b/arch/arm/plat-omap/include/plat/omap44xx.h
@@ -22,25 +22,31 @@
 #define L4_PER_44XX_BASE                0x48000000
 #define L4_EMU_44XX_BASE                0x54000000
 #define L3_44XX_BASE                    0x44000000
+#define OMAP44XX_EMIF1_BASE             0x4c000000
+#define OMAP44XX_EMIF2_BASE             0x4d000000
+#define OMAP44XX_DMM_BASE               0x4e000000
 #define OMAP4430_32KSYNCT_BASE          0x4a304000
-#define OMAP4430_CM_BASE                0x4a004000
-#define OMAP4430_PRM_BASE               0x48306000
+#define OMAP4430_CM1_BASE               0x4a004000
+#define OMAP4430_CM_BASE                OMAP4430_CM1_BASE
+#define OMAP4430_CM2_BASE               0x4a008000
+#define OMAP4430_PRM_BASE               0x4a306000
 #define OMAP44XX_GPMC_BASE              0x50000000
 #define OMAP443X_SCM_BASE               0x4a002000
-#define OMAP443X_CTRL_BASE              OMAP443X_SCM_BASE
+#define OMAP443X_CTRL_BASE              0x4a100000
 #define OMAP44XX_IC_BASE                0x48200000
 #define OMAP44XX_IVA_INTC_BASE          0x40000000
 #define IRQ_SIR_IRQ                     0x0040
 #define OMAP44XX_GIC_DIST_BASE          0x48241000
 #define OMAP44XX_GIC_CPU_BASE           0x48240100
-#define OMAP44XX_VA_GIC_CPU_BASE        OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
 #define OMAP44XX_SCU_BASE               0x48240000
-#define OMAP44XX_VA_SCU_BASE            OMAP2_IO_ADDRESS(OMAP44XX_SCU_BASE)
 #define OMAP44XX_LOCAL_TWD_BASE         0x48240600
-#define OMAP44XX_VA_LOCAL_TWD_BASE      OMAP2_IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE)
-#define OMAP44XX_LOCAL_TWD_SIZE         0x00000100
+#define OMAP44XX_L2CACHE_BASE           0x48242000
 #define OMAP44XX_WKUPGEN_BASE           0x48281000
-#define OMAP44XX_VA_WKUPGEN_BASE        OMAP2_IO_ADDRESS(OMAP44XX_WKUPGEN_BASE)
+#define OMAP44XX_MCPDM_BASE             0x40132000
+#define OMAP44XX_MCPDM_L3_BASE          0x49032000
+
+#define OMAP44XX_MAILBOX_BASE           (L4_44XX_BASE + 0xF4000)
+#define OMAP44XX_HSUSB_OTG_BASE         (L4_44XX_BASE + 0xAB000)
 
 #endif /* __ASM_ARCH_OMAP44XX_H */
 
diff --git a/arch/arm/plat-omap/include/mach/omap730.h b/arch/arm/plat-omap/include/plat/omap730.h
index 14272bc1a6fd..14272bc1a6fd 100644
--- a/arch/arm/plat-omap/include/mach/omap730.h
+++ b/arch/arm/plat-omap/include/plat/omap730.h
diff --git a/arch/arm/plat-omap/include/plat/omap7xx.h b/arch/arm/plat-omap/include/plat/omap7xx.h
new file mode 100644
index 000000000000..48e4757e1e30
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap7xx.h
@@ -0,0 +1,107 @@
+/* arch/arm/plat-omap/include/mach/omap7xx.h
+ *
+ * Hardware definitions for TI OMAP7XX processor.
+ *
+ * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
+ * Adapted for omap850 by Zebediah C. McClure <zmc@lurian.net>
+ * Adapted for omap7xx by Alistair Buxton <a.j.buxton@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP7XX_H
+#define __ASM_ARCH_OMAP7XX_H
+
+/*
+ * ----------------------------------------------------------------------------
+ * Base addresses
+ * ----------------------------------------------------------------------------
+ */
+
+/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
+
+#define OMAP7XX_DSP_BASE        0xE0000000
+#define OMAP7XX_DSP_SIZE        0x50000
+#define OMAP7XX_DSP_START       0xE0000000
+
+#define OMAP7XX_DSPREG_BASE     0xE1000000
+#define OMAP7XX_DSPREG_SIZE     SZ_128K
+#define OMAP7XX_DSPREG_START    0xE1000000
+
+#define OMAP7XX_SPI1_BASE       0xfffc0800
+#define OMAP7XX_SPI2_BASE       0xfffc1000
+
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP7XX specific configuration registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP7XX_CONFIG_BASE     0xfffe1000
+#define OMAP7XX_IO_CONF_0       0xfffe1070
+#define OMAP7XX_IO_CONF_1       0xfffe1074
+#define OMAP7XX_IO_CONF_2       0xfffe1078
+#define OMAP7XX_IO_CONF_3       0xfffe107c
+#define OMAP7XX_IO_CONF_4       0xfffe1080
+#define OMAP7XX_IO_CONF_5       0xfffe1084
+#define OMAP7XX_IO_CONF_6       0xfffe1088
+#define OMAP7XX_IO_CONF_7       0xfffe108c
+#define OMAP7XX_IO_CONF_8       0xfffe1090
+#define OMAP7XX_IO_CONF_9       0xfffe1094
+#define OMAP7XX_IO_CONF_10      0xfffe1098
+#define OMAP7XX_IO_CONF_11      0xfffe109c
+#define OMAP7XX_IO_CONF_12      0xfffe10a0
+#define OMAP7XX_IO_CONF_13      0xfffe10a4
+
+#define OMAP7XX_MODE_1          0xfffe1010
+#define OMAP7XX_MODE_2          0xfffe1014
+
+/* CSMI specials: in terms of base + offset */
+#define OMAP7XX_MODE2_OFFSET    0x14
+
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP7XX traffic controller configuration registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP7XX_FLASH_CFG_0     0xfffecc10
+#define OMAP7XX_FLASH_ACFG_0    0xfffecc50
+#define OMAP7XX_FLASH_CFG_1     0xfffecc14
+#define OMAP7XX_FLASH_ACFG_1    0xfffecc54
+
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP7XX DSP control registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP7XX_ICR_BASE        0xfffbb800
+#define OMAP7XX_DSP_M_CTL       0xfffbb804
+#define OMAP7XX_DSP_MMU_BASE    0xfffed200
+
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP7XX PCC_UPLD configuration registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP7XX_PCC_UPLD_CTRL_BASE      (0xfffe0900)
+#define OMAP7XX_PCC_UPLD_CTRL           (OMAP7XX_PCC_UPLD_CTRL_BASE + 0x00)
+
+#endif /*  __ASM_ARCH_OMAP7XX_H */
+
diff --git a/arch/arm/plat-omap/include/mach/omap850.h b/arch/arm/plat-omap/include/plat/omap850.h
index c33f67981712..c33f67981712 100644
--- a/arch/arm/plat-omap/include/mach/omap850.h
+++ b/arch/arm/plat-omap/include/plat/omap850.h
diff --git a/arch/arm/plat-omap/include/mach/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index bd0e136db337..3694b622c4ac 100644
--- a/arch/arm/plat-omap/include/mach/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -34,7 +34,7 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 
-#include <mach/omap_hwmod.h>
+#include <plat/omap_hwmod.h>
 
 /* omap_device._state values */
 #define OMAP_DEVICE_STATE_UNKNOWN       0
@@ -50,8 +50,8 @@
  * @pm_lats: ptr to an omap_device_pm_latency table
  * @pm_lats_cnt: ARRAY_SIZE() of what is passed to @pm_lats
  * @pm_lat_level: array index of the last odpl entry executed - -1 if never
- * @dev_wakeup_lat: dev wakeup latency in microseconds
- * @_dev_wakeup_lat_limit: dev wakeup latency limit in usec - set by OMAP PM
+ * @dev_wakeup_lat: dev wakeup latency in nanoseconds
+ * @_dev_wakeup_lat_limit: dev wakeup latency limit in nsec - set by OMAP PM
  * @_state: one of OMAP_DEVICE_STATE_* (see above)
  * @flags: device flags
  *
@@ -62,6 +62,7 @@
  *
  */
 struct omap_device {
+        u32                             magic;
         struct platform_device          pdev;
         struct omap_hwmod               **hwmods;
         struct omap_device_pm_latency   *pm_lats;
@@ -81,6 +82,7 @@ int omap_device_shutdown(struct platform_device *pdev);
 
 /* Core code interface */
 
+bool omap_device_is_valid(struct omap_device *od);
 int omap_device_count_resources(struct omap_device *od);
 int omap_device_fill_resources(struct omap_device *od, struct resource *res);
 
@@ -88,15 +90,16 @@ struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
                                       struct omap_hwmod *oh, void *pdata,
                                       int pdata_len,
                                       struct omap_device_pm_latency *pm_lats,
-                                      int pm_lats_cnt);
+                                      int pm_lats_cnt, int is_early_device);
 
 struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
                                          struct omap_hwmod **oh, int oh_cnt,
                                          void *pdata, int pdata_len,
                                          struct omap_device_pm_latency *pm_lats,
-                                         int pm_lats_cnt);
+                                         int pm_lats_cnt, int is_early_device);
 
 int omap_device_register(struct omap_device *od);
+int omap_early_device_register(struct omap_device *od);
 
 /* OMAP PM interface */
 int omap_device_align_pm_lat(struct platform_device *pdev,
@@ -131,11 +134,17 @@ int omap_device_enable_clocks(struct omap_device *od);
  */
 struct omap_device_pm_latency {
         u32 deactivate_lat;
+        u32 deactivate_lat_worst;
         int (*deactivate_func)(struct omap_device *od);
         u32 activate_lat;
+        u32 activate_lat_worst;
         int (*activate_func)(struct omap_device *od);
+        u32 flags;
 };
 
+#define OMAP_DEVICE_LATENCY_AUTO_ADJUST BIT(1)
 
-#endif
+/* Get omap_device pointer from platform_device pointer */
+#define to_omap_device(x) container_of((x), struct omap_device, pdev)
 
+#endif
diff --git a/arch/arm/plat-omap/include/mach/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 1f79c20e2929..36d6ea56ab51 100644
--- a/arch/arm/plat-omap/include/mach/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -4,7 +4,7 @@
  * Copyright (C) 2009 Nokia Corporation
  * Paul Walmsley
  *
- * Created in collaboration with (alphabetical order): Benoit Cousson,
+ * Created in collaboration with (alphabetical order): Benoît Cousson,
  * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari
  * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff
  *
@@ -33,23 +33,42 @@
 #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
 
 #include <linux/kernel.h>
+#include <linux/list.h>
 #include <linux/ioport.h>
-
-#include <mach/cpu.h>
+#include <plat/cpu.h>
 
 struct omap_device;
 
-/* OCP SYSCONFIG bit shifts/masks */
-#define SYSC_MIDLEMODE_SHIFT            12
-#define SYSC_MIDLEMODE_MASK             (0x3 << SYSC_MIDLEMODE_SHIFT)
-#define SYSC_CLOCKACTIVITY_SHIFT        8
-#define SYSC_CLOCKACTIVITY_MASK         (0x3 << SYSC_CLOCKACTIVITY_SHIFT)
-#define SYSC_SIDLEMODE_SHIFT            3
-#define SYSC_SIDLEMODE_MASK             (0x3 << SYSC_SIDLEMODE_SHIFT)
-#define SYSC_ENAWAKEUP_SHIFT            2
-#define SYSC_ENAWAKEUP_MASK             (1 << SYSC_ENAWAKEUP_SHIFT)
-#define SYSC_SOFTRESET_SHIFT            1
-#define SYSC_SOFTRESET_MASK             (1 << SYSC_SOFTRESET_SHIFT)
+extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1;
+extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
+
+/*
+ * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant
+ * with the original PRCM protocol defined for OMAP2420
+ */
+#define SYSC_TYPE1_MIDLEMODE_SHIFT      12
+#define SYSC_TYPE1_MIDLEMODE_MASK       (0x3 << SYSC_MIDLEMODE_SHIFT)
+#define SYSC_TYPE1_CLOCKACTIVITY_SHIFT  8
+#define SYSC_TYPE1_CLOCKACTIVITY_MASK   (0x3 << SYSC_CLOCKACTIVITY_SHIFT)
+#define SYSC_TYPE1_SIDLEMODE_SHIFT      3
+#define SYSC_TYPE1_SIDLEMODE_MASK       (0x3 << SYSC_SIDLEMODE_SHIFT)
+#define SYSC_TYPE1_ENAWAKEUP_SHIFT      2
+#define SYSC_TYPE1_ENAWAKEUP_MASK       (1 << SYSC_ENAWAKEUP_SHIFT)
+#define SYSC_TYPE1_SOFTRESET_SHIFT      1
+#define SYSC_TYPE1_SOFTRESET_MASK       (1 << SYSC_SOFTRESET_SHIFT)
+#define SYSC_TYPE1_AUTOIDLE_SHIFT       0
+#define SYSC_TYPE1_AUTOIDLE_MASK        (1 << SYSC_AUTOIDLE_SHIFT)
+
+/*
+ * OCP SYSCONFIG bit shifts/masks TYPE2. These are for IPs compliant
+ * with the new PRCM protocol defined for new OMAP4 IPs.
+ */
+#define SYSC_TYPE2_SOFTRESET_SHIFT      0
+#define SYSC_TYPE2_SOFTRESET_MASK       (1 << SYSC_TYPE2_SOFTRESET_SHIFT)
+#define SYSC_TYPE2_SIDLEMODE_SHIFT      2
+#define SYSC_TYPE2_SIDLEMODE_MASK       (0x3 << SYSC_TYPE2_SIDLEMODE_SHIFT)
+#define SYSC_TYPE2_MIDLEMODE_SHIFT      4
+#define SYSC_TYPE2_MIDLEMODE_MASK       (0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT)
 
 /* OCP SYSSTATUS bit shifts/masks */
 #define SYSS_RESETDONE_SHIFT            0
@@ -60,9 +79,22 @@ struct omap_device;
 #define HWMOD_IDLEMODE_NO               (1 << 1)
 #define HWMOD_IDLEMODE_SMART            (1 << 2)
 
+/**
+ * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod
+ * @name: name of the IRQ channel (module local name)
+ * @irq_ch: IRQ channel ID
+ *
+ * @name should be something short, e.g., "tx" or "rx".  It is for use
+ * by platform_get_resource_byname().  It is defined locally to the
+ * hwmod.
+ */
+struct omap_hwmod_irq_info {
+        const char      *name;
+        u16             irq;
+};
 
 /**
- * struct omap_hwmod_dma_info - MPU address space handled by the hwmod
+ * struct omap_hwmod_dma_info - DMA channels used by the hwmod
  * @name: name of the DMA channel (module local name)
  * @dma_ch: DMA channel ID
  *
@@ -78,8 +110,7 @@ struct omap_hwmod_dma_info {
 /**
  * struct omap_hwmod_opt_clk - optional clocks used by this hwmod
  * @role: "sys", "32k", "tv", etc -- for use in clk_get()
- * @clkdev_dev_id: opt clock: clkdev dev_id string
- * @clkdev_con_id: opt clock: clkdev con_id string
+ * @clk: opt clock: OMAP clock name
  * @_clk: pointer to the struct clk (filled in at runtime)
  *
  * The module's interface clock and main functional clock should not
@@ -87,8 +118,7 @@ struct omap_hwmod_dma_info {
  */
 struct omap_hwmod_opt_clk {
         const char      *role;
-        const char      *clkdev_dev_id;
-        const char      *clkdev_con_id;
+        const char      *clk;
         struct clk      *_clk;
 };
 
@@ -155,8 +185,7 @@ struct omap_hwmod_addr_space {
  * @master: struct omap_hwmod that initiates OCP transactions on this link
  * @slave: struct omap_hwmod that responds to OCP transactions on this link
  * @addr: address space associated with this link
- * @clkdev_dev_id: interface clock: clkdev dev_id string
- * @clkdev_con_id: interface clock: clkdev con_id string
+ * @clk: interface clock: OMAP clock name
  * @_clk: pointer to the interface struct clk (filled in at runtime)
  * @fw: interface firewall data
  * @addr_cnt: ARRAY_SIZE(@addr)
@@ -175,8 +204,7 @@ struct omap_hwmod_ocp_if {
         struct omap_hwmod               *master;
         struct omap_hwmod               *slave;
         struct omap_hwmod_addr_space    *addr;
-        const char                      *clkdev_dev_id;
-        const char                      *clkdev_con_id;
+        const char                      *clk;
         struct clk                      *_clk;
         union {
                 struct omap_hwmod_omap2_firewall omap2;
@@ -211,6 +239,7 @@ struct omap_hwmod_ocp_if {
 #define SYSC_HAS_SIDLEMODE      (1 << 5)
 #define SYSC_HAS_MIDLEMODE      (1 << 6)
 #define SYSS_MISSING            (1 << 7)
+#define SYSC_NO_CACHE           (1 << 8)  /* XXX SW flag, belongs elsewhere */
 
 /* omap_hwmod_sysconfig.clockact flags */
 #define CLOCKACT_TEST_BOTH      0x0
@@ -219,7 +248,25 @@ struct omap_hwmod_ocp_if {
 #define CLOCKACT_TEST_NONE      0x3
 
 /**
- * struct omap_hwmod_sysconfig - hwmod OCP_SYSCONFIG/OCP_SYSSTATUS data
+ * struct omap_hwmod_sysc_fields - hwmod OCP_SYSCONFIG register field offsets.
+ * @midle_shift: Offset of the midle bit
+ * @clkact_shift: Offset of the clockactivity bit
+ * @sidle_shift: Offset of the sidle bit
+ * @enwkup_shift: Offset of the enawakeup bit
+ * @srst_shift: Offset of the softreset bit
+ * @autoidle_shift: Offset of the autoidle bit
+ */
+struct omap_hwmod_sysc_fields {
+        u8 midle_shift;
+        u8 clkact_shift;
+        u8 sidle_shift;
+        u8 enwkup_shift;
+        u8 srst_shift;
+        u8 autoidle_shift;
+};
+
+/**
+ * struct omap_hwmod_class_sysconfig - hwmod class OCP_SYS* data
  * @rev_offs: IP block revision register offset (from module base addr)
  * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr)
  * @syss_offs: OCP_SYSSTATUS register offset (from module base addr)
@@ -235,14 +282,22 @@ struct omap_hwmod_ocp_if {
  * been associated with the clocks marked in @clockact.  This field is
  * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below)
  *
+ * @sysc_fields: structure containing the offset positions of various bits in
+ * SYSCONFIG register. This can be populated using omap_hwmod_sysc_type1 or
+ * omap_hwmod_sysc_type2 defined in omap_hwmod_common_data.c depending on
+ * whether the device ip is compliant with the original PRCM protocol
+ * defined for OMAP2420 or the new PRCM protocol for new OMAP4 IPs.
+ * If the device follows a different scheme for the sysconfig register ,
+ * then this field has to be populated with the correct offset structure.
  */
-struct omap_hwmod_sysconfig {
+struct omap_hwmod_class_sysconfig {
         u16 rev_offs;
         u16 sysc_offs;
         u16 syss_offs;
+        u16 sysc_flags;
         u8 idlemodes;
-        u8 sysc_flags;
         u8 clockact;
+        struct omap_hwmod_sysc_fields *sysc_fields;
 };
 
 /**
@@ -294,13 +349,17 @@ struct omap_hwmod_omap4_prcm {
  *     SDRAM controller, etc.
  * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
  *     controller, etc.
+ * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
+ *     when module is enabled, rather than the default, which is to
+ *     enable autoidle
  * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
  */
 #define HWMOD_SWSUP_SIDLE                       (1 << 0)
 #define HWMOD_SWSUP_MSTANDBY                    (1 << 1)
 #define HWMOD_INIT_NO_RESET                     (1 << 2)
 #define HWMOD_INIT_NO_IDLE                      (1 << 3)
-#define HWMOD_SET_DEFAULT_CLOCKACT              (1 << 4)
+#define HWMOD_NO_OCP_AUTOIDLE                   (1 << 4)
+#define HWMOD_SET_DEFAULT_CLOCKACT              (1 << 5)
 
 /*
  * omap_hwmod._int_flags definitions
@@ -331,19 +390,33 @@ struct omap_hwmod_omap4_prcm {
 #define _HWMOD_STATE_DISABLED                   6
 
 /**
+ * struct omap_hwmod_class - the type of an IP block
+ * @name: name of the hwmod_class
+ * @sysc: device SYSCONFIG/SYSSTATUS register data
+ * @rev: revision of the IP class
+ *
+ * Represent the class of a OMAP hardware "modules" (e.g. timer,
+ * smartreflex, gpio, uart...)
+ */
+struct omap_hwmod_class {
+        const char                              *name;
+        struct omap_hwmod_class_sysconfig       *sysc;
+        u32                                     rev;
+};
+
+/**
  * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks)
  * @name: name of the hwmod
+ * @class: struct omap_hwmod_class * to the class of this hwmod
  * @od: struct omap_device currently associated with this hwmod (internal use)
  * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt)
  * @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt)
  * @prcm: PRCM data pertaining to this hwmod
- * @clkdev_dev_id: main clock: clkdev dev_id string
- * @clkdev_con_id: main clock: clkdev con_id string
+ * @main_clk: main clock: OMAP clock name
  * @_clk: pointer to the main struct clk (filled in at runtime)
  * @opt_clks: other device clocks that drivers can request (0..*)
  * @masters: ptr to array of OCP ifs that this hwmod can initiate on
  * @slaves: ptr to array of OCP ifs that this hwmod can respond on
- * @sysconfig: device SYSCONFIG/SYSSTATUS register data
  * @dev_attr: arbitrary device attributes that can be passed to the driver
  * @_sysc_cache: internal-use hwmod flags
  * @_rt_va: cached register target start address (internal use)
@@ -362,30 +435,29 @@ struct omap_hwmod_omap4_prcm {
  * @omap_chip: OMAP chips this hwmod is present on
  * @node: list node for hwmod list (internal use)
  *
- * @clkdev_dev_id, @clkdev_con_id, and @clk all refer to this module's "main
- * clock," which for our purposes is defined as "the functional clock needed
- * for register accesses to complete."  Modules may not have a main clock if
- * the interface clock also serves as a main clock.
+ * @main_clk refers to this module's "main clock," which for our
+ * purposes is defined as "the functional clock needed for register
+ * accesses to complete."  Modules may not have a main clock if the
+ * interface clock also serves as a main clock.
  *
  * Parameter names beginning with an underscore are managed internally by
  * the omap_hwmod code and should not be set during initialization.
  */
 struct omap_hwmod {
         const char                      *name;
+        struct omap_hwmod_class         *class;
         struct omap_device              *od;
-        u8                              *mpu_irqs;
+        struct omap_hwmod_irq_info      *mpu_irqs;
         struct omap_hwmod_dma_info      *sdma_chs;
         union {
                 struct omap_hwmod_omap2_prcm omap2;
                 struct omap_hwmod_omap4_prcm omap4;
         }                               prcm;
-        const char                      *clkdev_dev_id;
-        const char                      *clkdev_con_id;
+        const char                      *main_clk;
         struct clk                      *_clk;
         struct omap_hwmod_opt_clk       *opt_clks;
         struct omap_hwmod_ocp_if        **masters; /* connect to *_IA */
         struct omap_hwmod_ocp_if        **slaves;  /* connect to *_TA */
-        struct omap_hwmod_sysconfig     *sysconfig;
         void                            *dev_attr;
         u32                             _sysc_cache;
         void __iomem                    *_rt_va;
@@ -420,6 +492,8 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh);
 int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
 int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
 
+int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode);
+
 int omap_hwmod_reset(struct omap_hwmod *oh);
 void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
 
@@ -444,4 +518,17 @@ int omap_hwmod_set_clockact_none(struct omap_hwmod *oh);
 int omap_hwmod_enable_wakeup(struct omap_hwmod *oh);
 int omap_hwmod_disable_wakeup(struct omap_hwmod *oh);
 
+int omap_hwmod_for_each_by_class(const char *classname,
+                                 int (*fn)(struct omap_hwmod *oh,
+                                           void *user),
+                                 void *user);
+
+/*
+ * Chip variant-specific hwmod init routines - XXX should be converted
+ * to use initcalls once the initial boot ordering is straightened out
+ */
+extern int omap2420_hwmod_init(void);
+extern int omap2430_hwmod_init(void);
+extern int omap3xxx_hwmod_init(void);
+
 #endif
diff --git a/arch/arm/plat-omap/include/mach/onenand.h b/arch/arm/plat-omap/include/plat/onenand.h
index 72f433d7d827..72f433d7d827 100644
--- a/arch/arm/plat-omap/include/mach/onenand.h
+++ b/arch/arm/plat-omap/include/plat/onenand.h
diff --git a/arch/arm/plat-omap/include/mach/param.h b/arch/arm/plat-omap/include/plat/param.h
index 1eb4dc326979..1eb4dc326979 100644
--- a/arch/arm/plat-omap/include/mach/param.h
+++ b/arch/arm/plat-omap/include/plat/param.h
diff --git a/arch/arm/plat-omap/include/mach/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
index fa6461423bd0..d82b2c00d4f1 100644
--- a/arch/arm/plat-omap/include/mach/powerdomain.h
+++ b/arch/arm/plat-omap/include/plat/powerdomain.h
@@ -1,8 +1,8 @@
 /*
  * OMAP2/3 powerdomain control
  *
- * Copyright (C) 2007-8 Texas Instruments, Inc.
- * Copyright (C) 2007-8 Nokia Corporation
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Nokia Corporation
  *
  * Written by Paul Walmsley
  *
@@ -19,7 +19,7 @@
 
 #include <asm/atomic.h>
 
-#include <mach/cpu.h>
+#include <plat/cpu.h>
 
 
 /* Powerdomain basic power states */
@@ -28,6 +28,8 @@
 #define PWRDM_POWER_INACTIVE    0x2
 #define PWRDM_POWER_ON          0x3
 
+#define PWRDM_MAX_PWRSTS        4
+
 /* Powerdomain allowable state bitfields */
 #define PWRSTS_OFF_ON           ((1 << PWRDM_POWER_OFF) | \
                                  (1 << PWRDM_POWER_ON))
@@ -35,24 +37,30 @@
 #define PWRSTS_OFF_RET          ((1 << PWRDM_POWER_OFF) | \
                                  (1 << PWRDM_POWER_RET))
 
+#define PWRSTS_RET_ON           ((1 << PWRDM_POWER_RET) | \
+                                 (1 << PWRDM_POWER_ON))
+
 #define PWRSTS_OFF_RET_ON       (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
 
 
 /* Powerdomain flags */
 #define PWRDM_HAS_HDWR_SAR      (1 << 0) /* hardware save-and-restore support */
-
+#define PWRDM_HAS_MPU_QUIRK     (1 << 1) /* MPU pwr domain has MEM bank 0 bits
+                                          * in MEM bank 1 position. This is
+                                          * true for OMAP3430
+                                          */
 
 /*
- * Number of memory banks that are power-controllable.  On OMAP3430, the
- * maximum is 4.
+ * Number of memory banks that are power-controllable.  On OMAP4430, the
+ * maximum is 5.
  */
-#define PWRDM_MAX_MEM_BANKS     4
+#define PWRDM_MAX_MEM_BANKS     5
 
 /*
  * Maximum number of clockdomains that can be associated with a powerdomain.
- * CORE powerdomain on OMAP3 is the worst case
+ * CORE powerdomain on OMAP4 is the worst case
  */
-#define PWRDM_MAX_CLKDMS        4
+#define PWRDM_MAX_CLKDMS        9
 
 /* XXX A completely arbitrary number. What is reasonable here? */
 #define PWRDM_TRANSITION_BAILOUT 100000
@@ -60,77 +68,50 @@
 struct clockdomain;
 struct powerdomain;
 
-/* Encodes dependencies between powerdomains - statically defined */
-struct pwrdm_dep {
-
-        /* Powerdomain name */
-        const char *pwrdm_name;
-
-        /* Powerdomain pointer - resolved by the powerdomain code */
-        struct powerdomain *pwrdm;
-
-        /* Flags to mark OMAP chip restrictions, etc. */
-        const struct omap_chip_id omap_chip;
-
-};
-
+/**
+ * struct powerdomain - OMAP powerdomain
+ * @name: Powerdomain name
+ * @omap_chip: represents the OMAP chip types containing this pwrdm
+ * @prcm_offs: the address offset from CM_BASE/PRM_BASE
+ * @pwrsts: Possible powerdomain power states
+ * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
+ * @flags: Powerdomain flags
+ * @banks: Number of software-controllable memory banks in this powerdomain
+ * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
+ * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
+ * @pwrdm_clkdms: Clockdomains in this powerdomain
+ * @node: list_head linking all powerdomains
+ * @state:
+ * @state_counter:
+ * @timer:
+ * @state_timer:
+ */
 struct powerdomain {
-
-        /* Powerdomain name */
         const char *name;
-
-        /* the address offset from CM_BASE/PRM_BASE */
-        const s16 prcm_offs;
-
-        /* Used to represent the OMAP chip types containing this pwrdm */
         const struct omap_chip_id omap_chip;
-
-        /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
-        const u8 dep_bit;
-
-        /* Powerdomains that can be told to wake this powerdomain up */
-        struct pwrdm_dep *wkdep_srcs;
-
-        /* Powerdomains that can be told to keep this pwrdm from inactivity */
-        struct pwrdm_dep *sleepdep_srcs;
-
-        /* Possible powerdomain power states */
+        const s16 prcm_offs;
         const u8 pwrsts;
-
-        /* Possible logic power states when pwrdm in RETENTION */
         const u8 pwrsts_logic_ret;
-
-        /* Powerdomain flags */
         const u8 flags;
-
-        /* Number of software-controllable memory banks in this powerdomain */
         const u8 banks;
-
-        /* Possible memory bank pwrstates when pwrdm in RETENTION */
         const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
-
-        /* Possible memory bank pwrstates when pwrdm is ON */
         const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
-
-        /* Clockdomains in this powerdomain */
         struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
-
         struct list_head node;
-
         int state;
-        unsigned state_counter[4];
+        unsigned state_counter[PWRDM_MAX_PWRSTS];
+        unsigned ret_logic_off_counter;
+        unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
 
 #ifdef CONFIG_PM_DEBUG
         s64 timer;
-        s64 state_timer[4];
+        s64 state_timer[PWRDM_MAX_PWRSTS];
 #endif
 };
 
 
 void pwrdm_init(struct powerdomain **pwrdm_list);
 
-int pwrdm_register(struct powerdomain *pwrdm);
-int pwrdm_unregister(struct powerdomain *pwrdm);
 struct powerdomain *pwrdm_lookup(const char *name);
 
 int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
@@ -144,13 +125,6 @@ int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
                          int (*fn)(struct powerdomain *pwrdm,
                                    struct clockdomain *clkdm));
 
-int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
-int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
-int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
-int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
-int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
-int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
-
 int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
 
 int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
@@ -165,8 +139,10 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
 
 int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
 int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
+int pwrdm_read_logic_retst(struct powerdomain *pwrdm);
 int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
 int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
+int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
 
 int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
 int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
diff --git a/arch/arm/plat-omap/include/mach/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h
index cda2a70397b4..9fbd91419cd1 100644
--- a/arch/arm/plat-omap/include/mach/prcm.h
+++ b/arch/arm/plat-omap/include/plat/prcm.h
@@ -24,12 +24,25 @@
 #define __ASM_ARM_ARCH_OMAP_PRCM_H
 
 u32 omap_prcm_get_reset_sources(void);
-void omap_prcm_arch_reset(char mode);
-int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name);
+void omap_prcm_arch_reset(char mode, const char *cmd);
+int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
+                         const char *name);
 
-#endif
+#define START_PADCONF_SAVE 0x2
+#define PADCONF_SAVE_DONE  0x1
+
+void omap3_prcm_save_context(void);
+void omap3_prcm_restore_context(void);
 
+u32 prm_read_mod_reg(s16 module, u16 idx);
+void prm_write_mod_reg(u32 val, s16 module, u16 idx);
+u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
+u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
+u32 cm_read_mod_reg(s16 module, u16 idx);
+void cm_write_mod_reg(u32 val, s16 module, u16 idx);
+u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
 
+#endif
 
 
 
diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h
index 1c09c78a48f2..7b76f50564ba 100644
--- a/arch/arm/plat-omap/include/mach/sdrc.h
+++ b/arch/arm/plat-omap/include/plat/sdrc.h
@@ -44,6 +44,12 @@
 #define SDRC_RFR_CTRL_1         0x0D4
 #define SDRC_MANUAL_1           0x0D8
 
+#define SDRC_POWER_AUTOCOUNT_SHIFT      8
+#define SDRC_POWER_AUTOCOUNT_MASK       (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
+#define SDRC_POWER_CLKCTRL_SHIFT        4
+#define SDRC_POWER_CLKCTRL_MASK         (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
+#define SDRC_SELF_REFRESH_ON_AUTOCOUNT  (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
+
 /*
  * These values represent the number of memory clock cycles between
  * autorefresh initiation.  They assume 1 refresh per 64 ms (JEDEC), 8192
@@ -80,15 +86,18 @@
  */
 
 #define OMAP242X_SMS_REGADDR(reg)                                       \
-                        (void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
+                (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
 #define OMAP243X_SMS_REGADDR(reg)                                       \
-                        (void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
+                (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
 #define OMAP343X_SMS_REGADDR(reg)                                       \
-                        (void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
+                (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
 
 /* SMS register offsets - read/write with sms_{read,write}_reg() */
 
-#define SMS_SYSCONFIG           0x010
+#define SMS_SYSCONFIG                   0x010
+#define SMS_ROT_CONTROL(context)        (0x180 + 0x10 * context)
+#define SMS_ROT_SIZE(context)           (0x184 + 0x10 * context)
+#define SMS_ROT_PHYSICAL_BA(context)    (0x188 + 0x10 * context)
 /* REVISIT: fill in other SMS registers here */
 
 
@@ -120,6 +129,12 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
 int omap2_sdrc_get_params(unsigned long r,
                           struct omap_sdrc_params **sdrc_cs0,
                           struct omap_sdrc_params **sdrc_cs1);
+void omap2_sms_save_context(void);
+void omap2_sms_restore_context(void);
+
+void omap2_sms_write_rot_control(u32 val, unsigned ctx);
+void omap2_sms_write_rot_size(u32 val, unsigned ctx);
+void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx);
 
 #ifdef CONFIG_ARCH_OMAP2
 
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
new file mode 100644
index 000000000000..83dce4c4f7e6
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -0,0 +1,93 @@
+/*
+ * arch/arm/plat-omap/include/mach/serial.h
+ *
+ * Copyright (C) 2009 Texas Instruments
+ * Addded OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_SERIAL_H
+#define __ASM_ARCH_SERIAL_H
+
+#include <linux/init.h>
+
+/* OMAP1 serial ports */
+#define OMAP1_UART1_BASE        0xfffb0000
+#define OMAP1_UART2_BASE        0xfffb0800
+#define OMAP1_UART3_BASE        0xfffb9800
+
+/* OMAP2 serial ports */
+#define OMAP2_UART1_BASE        0x4806a000
+#define OMAP2_UART2_BASE        0x4806c000
+#define OMAP2_UART3_BASE        0x4806e000
+
+/* OMAP3 serial ports */
+#define OMAP3_UART1_BASE        OMAP2_UART1_BASE
+#define OMAP3_UART2_BASE        OMAP2_UART2_BASE
+#define OMAP3_UART3_BASE        0x49020000
+#define OMAP3_UART4_BASE        0x49042000      /* Only on 36xx */
+
+/* OMAP4 serial ports */
+#define OMAP4_UART1_BASE        OMAP2_UART1_BASE
+#define OMAP4_UART2_BASE        OMAP2_UART2_BASE
+#define OMAP4_UART3_BASE        0x48020000
+#define OMAP4_UART4_BASE        0x4806e000
+
+/* External port on Zoom2/3 */
+#define ZOOM_UART_BASE          0x10000000
+#define ZOOM_UART_VIRT          0xfb000000
+
+#define OMAP_PORT_SHIFT         2
+#define OMAP7XX_PORT_SHIFT      0
+#define ZOOM_PORT_SHIFT         1
+
+#define OMAP1510_BASE_BAUD      (12000000/16)
+#define OMAP16XX_BASE_BAUD      (48000000/16)
+#define OMAP24XX_BASE_BAUD      (48000000/16)
+
+/*
+ * DEBUG_LL port encoding stored into the UART1 scratchpad register by
+ * decomp_setup in uncompress.h
+ */
+#define OMAP1UART1              11
+#define OMAP1UART2              12
+#define OMAP1UART3              13
+#define OMAP2UART1              21
+#define OMAP2UART2              22
+#define OMAP2UART3              23
+#define OMAP3UART1              OMAP2UART1
+#define OMAP3UART2              OMAP2UART2
+#define OMAP3UART3              33
+#define OMAP3UART4              34              /* Only on 36xx */
+#define OMAP4UART1              OMAP2UART1
+#define OMAP4UART2              OMAP2UART2
+#define OMAP4UART3              43
+#define OMAP4UART4              44
+#define ZOOM_UART               95              /* Only on zoom2/3 */
+
+/* This is only used by 8250.c for omap1510 */
+#define is_omap_port(pt)        ({int __ret = 0;                        \
+                        if ((pt)->port.mapbase == OMAP1_UART1_BASE ||   \
+                            (pt)->port.mapbase == OMAP1_UART2_BASE ||   \
+                            (pt)->port.mapbase == OMAP1_UART3_BASE)     \
+                                __ret = 1;                              \
+                        __ret;                                          \
+                        })
+
+#ifndef __ASSEMBLER__
+extern void __init omap_serial_early_init(void);
+extern void omap_serial_init(void);
+extern void omap_serial_init_port(int port);
+extern int omap_uart_can_sleep(void);
+extern void omap_uart_check_wakeup(void);
+extern void omap_uart_prepare_suspend(void);
+extern void omap_uart_prepare_idle(int num);
+extern void omap_uart_resume_idle(int num);
+extern void omap_uart_enable_irqs(int enable);
+#endif
+
+#endif
diff --git a/arch/arm/plat-omap/include/mach/smp.h b/arch/arm/plat-omap/include/plat/smp.h
index dcaa8fde7063..8983d54c4fd2 100644
--- a/arch/arm/plat-omap/include/mach/smp.h
+++ b/arch/arm/plat-omap/include/plat/smp.h
@@ -28,6 +28,8 @@
 
 /* Needed for secondary core boot */
 extern void omap_secondary_startup(void);
+extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
+extern void omap_auxcoreboot_addr(u32 cpu_addr);
 
 /*
  * We use Soft IRQ1 as the IPI
diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index 8974e3fc2691..16a1b458d53c 100644
--- a/arch/arm/plat-omap/include/mach/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -27,6 +27,7 @@ extern u32 omap3_configure_core_dpll(
                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
+extern void omap3_sram_restore_context(void);
 
 /* Do not use these */
 extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
@@ -68,4 +69,10 @@ extern u32 omap3_sram_configure_core_dpll(
                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
 extern unsigned long omap3_sram_configure_core_dpll_sz;
 
+#ifdef CONFIG_PM
+extern void omap_push_sram_idle(void);
+#else
+static inline void omap_push_sram_idle(void) {}
+#endif /* CONFIG_PM */
+
 #endif
diff --git a/arch/arm/plat-omap/include/mach/system.h b/arch/arm/plat-omap/include/plat/system.h
index ed8ec7477261..d0a119f735b4 100644
--- a/arch/arm/plat-omap/include/mach/system.h
+++ b/arch/arm/plat-omap/include/plat/system.h
@@ -9,7 +9,7 @@
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
 
-#include <mach/prcm.h>
+#include <plat/prcm.h>
 
 #ifndef CONFIG_MACH_VOICEBLUE
 #define voiceblue_reset()               do {} while (0)
@@ -22,7 +22,7 @@ static inline void arch_idle(void)
         cpu_do_idle();
 }
 
-static inline void omap1_arch_reset(char mode)
+static inline void omap1_arch_reset(char mode, const char *cmd)
 {
         /*
          * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
@@ -43,9 +43,9 @@ static inline void omap1_arch_reset(char mode)
 static inline void arch_reset(char mode, const char *cmd)
 {
         if (!cpu_class_is_omap2())
-                omap1_arch_reset(mode);
+                omap1_arch_reset(mode, cmd);
         else
-                omap_prcm_arch_reset(mode);
+                omap_prcm_arch_reset(mode, cmd);
 }
 
 #endif
diff --git a/arch/arm/plat-omap/include/mach/tc.h b/arch/arm/plat-omap/include/plat/tc.h
index d2fcd789bb9a..d2fcd789bb9a 100644
--- a/arch/arm/plat-omap/include/mach/tc.h
+++ b/arch/arm/plat-omap/include/plat/tc.h
diff --git a/arch/arm/plat-omap/include/mach/timer-gp.h b/arch/arm/plat-omap/include/plat/timer-gp.h
index c88d346b59d9..c88d346b59d9 100644
--- a/arch/arm/plat-omap/include/mach/timer-gp.h
+++ b/arch/arm/plat-omap/include/plat/timer-gp.h
diff --git a/arch/arm/plat-omap/include/mach/timex.h b/arch/arm/plat-omap/include/plat/timex.h
index 6d35767bc48f..6d35767bc48f 100644
--- a/arch/arm/plat-omap/include/mach/timex.h
+++ b/arch/arm/plat-omap/include/plat/timex.h
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
new file mode 100644
index 000000000000..81d9ec540fcf
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -0,0 +1,173 @@
+/*
+ * arch/arm/plat-omap/include/mach/uncompress.h
+ *
+ * Serial port stubs for kernel decompress status messages
+ *
+ * Initially based on:
+ * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * Rewritten by:
+ * Author: <source@mvista.com>
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/types.h>
+#include <linux/serial_reg.h>
+
+#include <asm/mach-types.h>
+
+#include <plat/serial.h>
+
+static volatile u8 *uart1_base;
+static int uart1_shift;
+
+static volatile u8 *uart_base;
+static int uart_shift;
+
+/*
+ * Store the DEBUG_LL uart number into UART1 scratchpad register.
+ * See also debug-macro.S, and serial.c for related code.
+ *
+ * Please note that we currently assume that:
+ * - UART1 clocks are enabled for register access
+ * - UART1 scratchpad register can be used
+ */
+static void set_uart1_scratchpad(unsigned char port)
+{
+        uart1_base[UART_SCR << uart1_shift] = port;
+}
+
+static void putc(int c)
+{
+        if (!uart_base)
+                return;
+
+        while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE))
+                barrier();
+        uart_base[UART_TX << uart_shift] = c;
+}
+
+static inline void flush(void)
+{
+}
+
+/*
+ * Macros to configure UART1 and debug UART
+ */
+#define _DEBUG_LL_ENTRY(mach, uart1_phys, uart1_shft,                   \
+                        dbg_uart, dbg_shft, dbg_id)                     \
+        if (machine_is_##mach()) {                                      \
+                uart1_base = (volatile u8 *)(uart1_phys);               \
+                uart1_shift = (uart1_shft);                             \
+                uart_base = (volatile u8 *)(dbg_uart);                  \
+                uart_shift = (dbg_shft);                                \
+                port = (dbg_id);                                        \
+                set_uart1_scratchpad(port);                             \
+                break;                                                  \
+        }
+
+#define DEBUG_LL_OMAP7XX(p, mach)                                       \
+        _DEBUG_LL_ENTRY(mach, OMAP1_UART1_BASE, OMAP7XX_PORT_SHIFT,     \
+                OMAP1_UART##p##_BASE, OMAP7XX_PORT_SHIFT, OMAP1UART##p)
+
+#define DEBUG_LL_OMAP1(p, mach)                                         \
+        _DEBUG_LL_ENTRY(mach, OMAP1_UART1_BASE, OMAP_PORT_SHIFT,        \
+                OMAP1_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP1UART##p)
+
+#define DEBUG_LL_OMAP2(p, mach)                                         \
+        _DEBUG_LL_ENTRY(mach, OMAP2_UART1_BASE, OMAP_PORT_SHIFT,        \
+                OMAP2_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP2UART##p)
+
+#define DEBUG_LL_OMAP3(p, mach)                                         \
+        _DEBUG_LL_ENTRY(mach, OMAP3_UART1_BASE, OMAP_PORT_SHIFT,        \
+                OMAP3_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP3UART##p)
+
+#define DEBUG_LL_OMAP4(p, mach)                                         \
+        _DEBUG_LL_ENTRY(mach, OMAP4_UART1_BASE, OMAP_PORT_SHIFT,        \
+                OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP4UART##p)
+
+/* Zoom2/3 shift is different for UART1 and external port */
+#define DEBUG_LL_ZOOM(mach)                                             \
+        _DEBUG_LL_ENTRY(mach, OMAP2_UART1_BASE, OMAP_PORT_SHIFT,        \
+                ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
+
+static inline void __arch_decomp_setup(unsigned long arch_id)
+{
+        int port = 0;
+
+        /*
+         * Initialize the port based on the machine ID from the bootloader.
+         * Note that we're using macros here instead of switch statement
+         * as machine_is functions are optimized out for the boards that
+         * are not selected.
+         */
+        do {
+                /* omap7xx/8xx based boards using UART1 with shift 0 */
+                DEBUG_LL_OMAP7XX(1, herald);
+                DEBUG_LL_OMAP7XX(1, omap_perseus2);
+
+                /* omap15xx/16xx based boards using UART1 */
+                DEBUG_LL_OMAP1(1, ams_delta);
+                DEBUG_LL_OMAP1(1, nokia770);
+                DEBUG_LL_OMAP1(1, omap_h2);
+                DEBUG_LL_OMAP1(1, omap_h3);
+                DEBUG_LL_OMAP1(1, omap_innovator);
+                DEBUG_LL_OMAP1(1, omap_osk);
+                DEBUG_LL_OMAP1(1, omap_palmte);
+                DEBUG_LL_OMAP1(1, omap_palmz71);
+
+                /* omap15xx/16xx based boards using UART2 */
+                DEBUG_LL_OMAP1(2, omap_palmtt);
+
+                /* omap15xx/16xx based boards using UART3 */
+                DEBUG_LL_OMAP1(3, sx1);
+
+                /* omap2 based boards using UART1 */
+                DEBUG_LL_OMAP2(1, omap2evm);
+                DEBUG_LL_OMAP2(1, omap_2430sdp);
+                DEBUG_LL_OMAP2(1, omap_apollon);
+                DEBUG_LL_OMAP2(1, omap_h4);
+
+                /* omap2 based boards using UART3 */
+                DEBUG_LL_OMAP2(3, nokia_n800);
+                DEBUG_LL_OMAP2(3, nokia_n810);
+                DEBUG_LL_OMAP2(3, nokia_n810_wimax);
+
+                /* omap3 based boards using UART1 */
+                DEBUG_LL_OMAP2(1, omap3evm);
+                DEBUG_LL_OMAP3(1, omap_3430sdp);
+                DEBUG_LL_OMAP3(1, omap_3630sdp);
+
+                /* omap3 based boards using UART3 */
+                DEBUG_LL_OMAP3(3, cm_t35);
+                DEBUG_LL_OMAP3(3, igep0020);
+                DEBUG_LL_OMAP3(3, nokia_rx51);
+                DEBUG_LL_OMAP3(3, omap3517evm);
+                DEBUG_LL_OMAP3(3, omap3_beagle);
+                DEBUG_LL_OMAP3(3, omap3_pandora);
+                DEBUG_LL_OMAP3(3, omap_ldp);
+                DEBUG_LL_OMAP3(3, overo);
+                DEBUG_LL_OMAP3(3, touchbook);
+
+                /* omap4 based boards using UART3 */
+                DEBUG_LL_OMAP4(3, omap_4430sdp);
+
+                /* zoom2/3 external uart */
+                DEBUG_LL_ZOOM(omap_zoom2);
+                DEBUG_LL_ZOOM(omap_zoom3);
+
+        } while (0);
+}
+
+#define arch_decomp_setup()     __arch_decomp_setup(arch_id)
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_wdog()
diff --git a/arch/arm/plat-omap/include/mach/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index f337e1761e2c..876ca8d5e927 100644
--- a/arch/arm/plat-omap/include/mach/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -3,7 +3,23 @@
 #ifndef __ASM_ARCH_OMAP_USB_H
 #define __ASM_ARCH_OMAP_USB_H
 
-#include <mach/board.h>
+#include <linux/usb/musb.h>
+#include <plat/board.h>
+
+#define OMAP3_HS_USB_PORTS      3
+enum ehci_hcd_omap_mode {
+        EHCI_HCD_OMAP_MODE_UNKNOWN,
+        EHCI_HCD_OMAP_MODE_PHY,
+        EHCI_HCD_OMAP_MODE_TLL,
+};
+
+struct ehci_hcd_omap_platform_data {
+        enum ehci_hcd_omap_mode         port_mode[OMAP3_HS_USB_PORTS];
+        unsigned                        phy_reset:1;
+
+        /* have to be valid if phy_reset is true and portx is in phy mode */
+        int     reset_gpio_port[OMAP3_HS_USB_PORTS];
+};
 
 /*-------------------------------------------------------------------------*/
 
@@ -27,7 +43,17 @@
 #define UDC_BASE                        OMAP2_UDC_BASE
 #define OMAP_OHCI_BASE                  OMAP2_OHCI_BASE
 
-extern void usb_musb_init(void);
+struct omap_musb_board_data {
+        u8      interface_type;
+        u8      mode;
+        u16     power;
+};
+
+enum musb_interface    {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
+
+extern void usb_musb_init(struct omap_musb_board_data *board_data);
+
+extern void usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata);
 
 #endif
 
diff --git a/arch/arm/plat-omap/include/plat/vram.h b/arch/arm/plat-omap/include/plat/vram.h
new file mode 100644
index 000000000000..edd4987758a6
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/vram.h
@@ -0,0 +1,62 @@
+/*
+ * VRAM manager for OMAP
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+
+#ifndef __OMAP_VRAM_H__
+#define __OMAP_VRAM_H__
+
+#include <linux/types.h>
+
+#define OMAP_VRAM_MEMTYPE_SDRAM         0
+#define OMAP_VRAM_MEMTYPE_SRAM          1
+#define OMAP_VRAM_MEMTYPE_MAX           1
+
+extern int omap_vram_add_region(unsigned long paddr, size_t size);
+extern int omap_vram_free(unsigned long paddr, size_t size);
+extern int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr);
+extern int omap_vram_reserve(unsigned long paddr, size_t size);
+extern void omap_vram_get_info(unsigned long *vram, unsigned long *free_vram,
+                unsigned long *largest_free_block);
+
+#ifdef CONFIG_OMAP2_VRAM
+extern void omap_vram_set_sdram_vram(u32 size, u32 start);
+extern void omap_vram_set_sram_vram(u32 size, u32 start);
+
+extern void omap_vram_reserve_sdram(void);
+extern unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
+                                            unsigned long sram_vstart,
+                                            unsigned long sram_size,
+                                            unsigned long pstart_avail,
+                                            unsigned long size_avail);
+#else
+static inline void omap_vram_set_sdram_vram(u32 size, u32 start) { }
+static inline void omap_vram_set_sram_vram(u32 size, u32 start) { }
+
+static inline void omap_vram_reserve_sdram(void) { }
+static inline unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
+                                            unsigned long sram_vstart,
+                                            unsigned long sram_size,
+                                            unsigned long pstart_avail,
+                                            unsigned long size_avail)
+{
+        return 0;
+}
+#endif
+
+#endif
diff --git a/arch/arm/plat-omap/include/plat/vrfb.h b/arch/arm/plat-omap/include/plat/vrfb.h
new file mode 100644
index 000000000000..d8a03ced3b10
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/vrfb.h
@@ -0,0 +1,50 @@
+/*
+ * VRFB Rotation Engine
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+
+#ifndef __OMAP_VRFB_H__
+#define __OMAP_VRFB_H__
+
+#define OMAP_VRFB_LINE_LEN 2048
+
+struct vrfb {
+        u8 context;
+        void __iomem *vaddr[4];
+        unsigned long paddr[4];
+        u16 xres;
+        u16 yres;
+        u16 xoffset;
+        u16 yoffset;
+        u8 bytespp;
+        bool yuv_mode;
+};
+
+extern int omap_vrfb_request_ctx(struct vrfb *vrfb);
+extern void omap_vrfb_release_ctx(struct vrfb *vrfb);
+extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
+                u8 bytespp);
+extern u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp);
+extern u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp);
+extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
+                u16 width, u16 height,
+                unsigned bytespp, bool yuv_mode);
+extern int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot);
+extern void omap_vrfb_restore_context(void);
+
+#endif /* __VRFB_H */
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
index b6defa23e77e..b0078cf96281 100644
--- a/arch/arm/plat-omap/io.c
+++ b/arch/arm/plat-omap/io.c
@@ -13,12 +13,12 @@
 #include <linux/io.h>
 #include <linux/mm.h>
 
-#include <mach/omap730.h>
-#include <mach/omap1510.h>
-#include <mach/omap16xx.h>
-#include <mach/omap24xx.h>
-#include <mach/omap34xx.h>
-#include <mach/omap44xx.h>
+#include <plat/omap7xx.h>
+#include <plat/omap1510.h>
+#include <plat/omap16xx.h>
+#include <plat/omap24xx.h>
+#include <plat/omap34xx.h>
+#include <plat/omap44xx.h>
 
 #define BETWEEN(p,st,sz)        ((p) >= (st) && (p) < ((st) + (sz)))
 #define XLATE(p,pst,vst)        ((void __iomem *)((p) - (pst) + (vst)))
@@ -33,13 +33,13 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
                 if (BETWEEN(p, OMAP1_IO_PHYS, OMAP1_IO_SIZE))
                         return XLATE(p, OMAP1_IO_PHYS, OMAP1_IO_VIRT);
         }
-        if (cpu_is_omap730()) {
-                if (BETWEEN(p, OMAP730_DSP_BASE, OMAP730_DSP_SIZE))
-                        return XLATE(p, OMAP730_DSP_BASE, OMAP730_DSP_START);
+        if (cpu_is_omap7xx()) {
+                if (BETWEEN(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_SIZE))
+                        return XLATE(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_START);
 
-                if (BETWEEN(p, OMAP730_DSPREG_BASE, OMAP730_DSPREG_SIZE))
-                        return XLATE(p, OMAP730_DSPREG_BASE,
-                                        OMAP730_DSPREG_START);
+                if (BETWEEN(p, OMAP7XX_DSPREG_BASE, OMAP7XX_DSPREG_SIZE))
+                        return XLATE(p, OMAP7XX_DSPREG_BASE,
+                                        OMAP7XX_DSPREG_START);
         }
         if (cpu_is_omap15xx()) {
                 if (BETWEEN(p, OMAP1510_DSP_BASE, OMAP1510_DSP_SIZE))
@@ -66,12 +66,12 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
                         return XLATE(p, L4_24XX_PHYS, L4_24XX_VIRT);
         }
         if (cpu_is_omap2420()) {
-                if (BETWEEN(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_SIZE))
-                        return XLATE(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_VIRT);
-                if (BETWEEN(p, DSP_IPI_24XX_PHYS, DSP_IPI_24XX_SIZE))
-                        return XLATE(p, DSP_IPI_24XX_PHYS, DSP_IPI_24XX_SIZE);
-                if (BETWEEN(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_SIZE))
-                        return XLATE(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_VIRT);
+                if (BETWEEN(p, DSP_MEM_2420_PHYS, DSP_MEM_2420_SIZE))
+                        return XLATE(p, DSP_MEM_2420_PHYS, DSP_MEM_2420_VIRT);
+                if (BETWEEN(p, DSP_IPI_2420_PHYS, DSP_IPI_2420_SIZE))
+                        return XLATE(p, DSP_IPI_2420_PHYS, DSP_IPI_2420_SIZE);
+                if (BETWEEN(p, DSP_MMU_2420_PHYS, DSP_MMU_2420_SIZE))
+                        return XLATE(p, DSP_MMU_2420_PHYS, DSP_MMU_2420_VIRT);
         }
         if (cpu_is_omap2430()) {
                 if (BETWEEN(p, L4_WK_243X_PHYS, L4_WK_243X_SIZE))
@@ -90,8 +90,6 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
                         return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT);
                 if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
                         return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
-                if (BETWEEN(p, L4_WK_34XX_PHYS, L4_WK_34XX_SIZE))
-                        return XLATE(p, L4_WK_34XX_PHYS, L4_WK_34XX_VIRT);
                 if (BETWEEN(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_SIZE))
                         return XLATE(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_VIRT);
                 if (BETWEEN(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_SIZE))
@@ -110,17 +108,23 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
                         return XLATE(p, L3_44XX_PHYS, L3_44XX_VIRT);
                 if (BETWEEN(p, L4_44XX_PHYS, L4_44XX_SIZE))
                         return XLATE(p, L4_44XX_PHYS, L4_44XX_VIRT);
-                if (BETWEEN(p, L4_WK_44XX_PHYS, L4_WK_44XX_SIZE))
-                        return XLATE(p, L4_WK_44XX_PHYS, L4_WK_44XX_VIRT);
                 if (BETWEEN(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_SIZE))
                         return XLATE(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_VIRT);
+                if (BETWEEN(p, OMAP44XX_EMIF1_PHYS, OMAP44XX_EMIF1_SIZE))
+                        return XLATE(p, OMAP44XX_EMIF1_PHYS,            \
+                                                        OMAP44XX_EMIF1_VIRT);
+                if (BETWEEN(p, OMAP44XX_EMIF2_PHYS, OMAP44XX_EMIF2_SIZE))
+                        return XLATE(p, OMAP44XX_EMIF2_PHYS,            \
+                                                        OMAP44XX_EMIF2_VIRT);
+                if (BETWEEN(p, OMAP44XX_DMM_PHYS, OMAP44XX_DMM_SIZE))
+                        return XLATE(p, OMAP44XX_DMM_PHYS, OMAP44XX_DMM_VIRT);
                 if (BETWEEN(p, L4_PER_44XX_PHYS, L4_PER_44XX_SIZE))
                         return XLATE(p, L4_PER_44XX_PHYS, L4_PER_44XX_VIRT);
                 if (BETWEEN(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_SIZE))
                         return XLATE(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_VIRT);
         }
 #endif
-        return __arm_ioremap(p, size, type);
+        return __arm_ioremap_caller(p, size, type, __builtin_return_address(0));
 }
 EXPORT_SYMBOL(omap_ioremap);
 
@@ -142,7 +146,7 @@ u8 omap_readb(u32 pa)
         if (cpu_class_is_omap1())
                 return __raw_readb(OMAP1_IO_ADDRESS(pa));
         else
-                return __raw_readb(OMAP2_IO_ADDRESS(pa));
+                return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
 }
 EXPORT_SYMBOL(omap_readb);
 
@@ -151,7 +155,7 @@ u16 omap_readw(u32 pa)
         if (cpu_class_is_omap1())
                 return __raw_readw(OMAP1_IO_ADDRESS(pa));
         else
-                return __raw_readw(OMAP2_IO_ADDRESS(pa));
+                return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
 }
 EXPORT_SYMBOL(omap_readw);
 
@@ -160,7 +164,7 @@ u32 omap_readl(u32 pa)
         if (cpu_class_is_omap1())
                 return __raw_readl(OMAP1_IO_ADDRESS(pa));
         else
-                return __raw_readl(OMAP2_IO_ADDRESS(pa));
+                return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
 }
 EXPORT_SYMBOL(omap_readl);
 
@@ -169,7 +173,7 @@ void omap_writeb(u8 v, u32 pa)
         if (cpu_class_is_omap1())
                 __raw_writeb(v, OMAP1_IO_ADDRESS(pa));
         else
-                __raw_writeb(v, OMAP2_IO_ADDRESS(pa));
+                __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
 }
 EXPORT_SYMBOL(omap_writeb);
 
@@ -178,7 +182,7 @@ void omap_writew(u16 v, u32 pa)
         if (cpu_class_is_omap1())
                 __raw_writew(v, OMAP1_IO_ADDRESS(pa));
         else
-                __raw_writew(v, OMAP2_IO_ADDRESS(pa));
+                __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
 }
 EXPORT_SYMBOL(omap_writew);
 
@@ -187,6 +191,6 @@ void omap_writel(u32 v, u32 pa)
         if (cpu_class_is_omap1())
                 __raw_writel(v, OMAP1_IO_ADDRESS(pa));
         else
-                __raw_writel(v, OMAP2_IO_ADDRESS(pa));
+                __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
 }
 EXPORT_SYMBOL(omap_writel);
diff --git a/arch/arm/plat-omap/iommu-debug.c b/arch/arm/plat-omap/iommu-debug.c
index c799b3b0d709..e6c0d536899c 100644
--- a/arch/arm/plat-omap/iommu-debug.c
+++ b/arch/arm/plat-omap/iommu-debug.c
@@ -13,12 +13,13 @@
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/slab.h>
 #include <linux/uaccess.h>
 #include <linux/platform_device.h>
 #include <linux/debugfs.h>
 
-#include <mach/iommu.h>
-#include <mach/iovmm.h>
+#include <plat/iommu.h>
+#include <plat/iovmm.h>
 
 #include "iopgtable.h"
 
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index 94584f167a82..0e137663349c 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -1,7 +1,7 @@
 /*
  * omap iommu: tlb and pagetable primitives
  *
- * Copyright (C) 2008-2009 Nokia Corporation
+ * Copyright (C) 2008-2010 Nokia Corporation
  *
  * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
  *              Paul Mundt and Toshihiro Kobayashi
@@ -13,6 +13,7 @@
 
 #include <linux/err.h>
 #include <linux/module.h>
+#include <linux/slab.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/clk.h>
@@ -20,7 +21,7 @@
 
 #include <asm/cacheflush.h>
 
-#include <mach/iommu.h>
+#include <plat/iommu.h>
 
 #include "iopgtable.h"
 
@@ -646,7 +647,7 @@ static size_t iopgtable_clear_entry_core(struct iommu *obj, u32 da)
                 if (*iopte & IOPTE_LARGE) {
                         nent *= 16;
                         /* rewind to the 1st entry */
-                        iopte = (u32 *)((u32)iopte & IOLARGE_MASK);
+                        iopte = iopte_offset(iopgd, (da & IOLARGE_MASK));
                 }
                 bytes *= nent;
                 memset(iopte, 0, nent * sizeof(*iopte));
@@ -667,7 +668,7 @@ static size_t iopgtable_clear_entry_core(struct iommu *obj, u32 da)
                 if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) {
                         nent *= 16;
                         /* rewind to the 1st entry */
-                        iopgd = (u32 *)((u32)iopgd & IOSUPER_MASK);
+                        iopgd = iopgd_offset(obj, (da & IOSUPER_MASK));
                 }
                 bytes *= nent;
         }
@@ -827,7 +828,7 @@ EXPORT_SYMBOL_GPL(iommu_get);
  **/
 void iommu_put(struct iommu *obj)
 {
-        if (!obj && IS_ERR(obj))
+        if (!obj || IS_ERR(obj))
                 return;
 
         mutex_lock(&obj->iommu_lock);
diff --git a/arch/arm/plat-omap/iopgtable.h b/arch/arm/plat-omap/iopgtable.h
index 37dac434c7a1..ab23b6a140fd 100644
--- a/arch/arm/plat-omap/iopgtable.h
+++ b/arch/arm/plat-omap/iopgtable.h
@@ -1,7 +1,7 @@
 /*
  * omap iommu: pagetable definitions
  *
- * Copyright (C) 2008-2009 Nokia Corporation
+ * Copyright (C) 2008-2010 Nokia Corporation
  *
  * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
  *
@@ -13,26 +13,52 @@
 #ifndef __PLAT_OMAP_IOMMU_H
 #define __PLAT_OMAP_IOMMU_H
 
+/*
+ * "L2 table" address mask and size definitions.
+ */
 #define IOPGD_SHIFT             20
-#define IOPGD_SIZE              (1 << IOPGD_SHIFT)
+#define IOPGD_SIZE              (1UL << IOPGD_SHIFT)
 #define IOPGD_MASK              (~(IOPGD_SIZE - 1))
-#define IOSECTION_MASK          IOPGD_MASK
-#define PTRS_PER_IOPGD          (1 << (32 - IOPGD_SHIFT))
-#define IOPGD_TABLE_SIZE        (PTRS_PER_IOPGD * sizeof(u32))
 
-#define IOSUPER_SIZE            (IOPGD_SIZE << 4)
+/*
+ * "section" address mask and size definitions.
+ */
+#define IOSECTION_SHIFT         20
+#define IOSECTION_SIZE          (1UL << IOSECTION_SHIFT)
+#define IOSECTION_MASK          (~(IOSECTION_SIZE - 1))
+
+/*
+ * "supersection" address mask and size definitions.
+ */
+#define IOSUPER_SHIFT           24
+#define IOSUPER_SIZE            (1UL << IOSUPER_SHIFT)
 #define IOSUPER_MASK            (~(IOSUPER_SIZE - 1))
 
+#define PTRS_PER_IOPGD          (1UL << (32 - IOPGD_SHIFT))
+#define IOPGD_TABLE_SIZE        (PTRS_PER_IOPGD * sizeof(u32))
+
+/*
+ * "small page" address mask and size definitions.
+ */
 #define IOPTE_SHIFT             12
-#define IOPTE_SIZE              (1 << IOPTE_SHIFT)
+#define IOPTE_SIZE              (1UL << IOPTE_SHIFT)
 #define IOPTE_MASK              (~(IOPTE_SIZE - 1))
-#define IOPAGE_MASK             IOPTE_MASK
-#define PTRS_PER_IOPTE          (1 << (IOPGD_SHIFT - IOPTE_SHIFT))
-#define IOPTE_TABLE_SIZE        (PTRS_PER_IOPTE * sizeof(u32))
 
-#define IOLARGE_SIZE            (IOPTE_SIZE << 4)
+/*
+ * "large page" address mask and size definitions.
+ */
+#define IOLARGE_SHIFT           16
+#define IOLARGE_SIZE            (1UL << IOLARGE_SHIFT)
 #define IOLARGE_MASK            (~(IOLARGE_SIZE - 1))
 
+#define PTRS_PER_IOPTE          (1UL << (IOPGD_SHIFT - IOPTE_SHIFT))
+#define IOPTE_TABLE_SIZE        (PTRS_PER_IOPTE * sizeof(u32))
+
+#define IOPAGE_MASK             IOPTE_MASK
+
+/*
+ * some descriptor attributes.
+ */
 #define IOPGD_TABLE             (1 << 0)
 #define IOPGD_SECTION           (2 << 0)
 #define IOPGD_SUPER             (1 << 18 | 2 << 0)
@@ -40,12 +66,14 @@
 #define IOPTE_SMALL             (2 << 0)
 #define IOPTE_LARGE             (1 << 0)
 
+/* to find an entry in a page-table-directory */
 #define iopgd_index(da)         (((da) >> IOPGD_SHIFT) & (PTRS_PER_IOPGD - 1))
 #define iopgd_offset(obj, da)   ((obj)->iopgd + iopgd_index(da))
 
 #define iopte_paddr(iopgd)      (*iopgd & ~((1 << 10) - 1))
 #define iopte_vaddr(iopgd)      ((u32 *)phys_to_virt(iopte_paddr(iopgd)))
 
+/* to find an entry in the second-level page table. */
 #define iopte_index(da)         (((da) >> IOPTE_SHIFT) & (PTRS_PER_IOPTE - 1))
 #define iopte_offset(iopgd, da) (iopte_vaddr(iopgd) + iopte_index(da))
 
diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c
index dc3fac3dd0ea..65c6d1ff7237 100644
--- a/arch/arm/plat-omap/iovmm.c
+++ b/arch/arm/plat-omap/iovmm.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/err.h>
+#include <linux/slab.h>
 #include <linux/vmalloc.h>
 #include <linux/device.h>
 #include <linux/scatterlist.h>
@@ -18,8 +19,8 @@
 #include <asm/cacheflush.h>
 #include <asm/mach/map.h>
 
-#include <mach/iommu.h>
-#include <mach/iovmm.h>
+#include <plat/iommu.h>
+#include <plat/iovmm.h>
 
 #include "iopgtable.h"
 
@@ -392,7 +393,6 @@ static void sgtable_fill_vmalloc(struct sg_table *sgt, void *_va)
         }
 
         va_end = _va + PAGE_SIZE * i;
-        flush_cache_vmap((unsigned long)_va, (unsigned long)va_end);
 }
 
 static inline void sgtable_drain_vmalloc(struct sg_table *sgt)
@@ -427,8 +427,6 @@ static void sgtable_fill_kmalloc(struct sg_table *sgt, u32 pa, size_t len)
                 len -= bytes;
         }
         BUG_ON(len);
-
-        clean_dcache_area(va, len);
 }
 
 static inline void sgtable_drain_kmalloc(struct sg_table *sgt)
@@ -449,7 +447,7 @@ static int map_iovm_area(struct iommu *obj, struct iovm_struct *new,
         struct scatterlist *sg;
         u32 da = new->da_start;
 
-        if (!obj || !new || !sgt)
+        if (!obj || !sgt)
                 return -EINVAL;
 
         BUG_ON(!sgtable_ok(sgt));
@@ -617,7 +615,7 @@ u32 iommu_vmap(struct iommu *obj, u32 da, const struct sg_table *sgt,
                  u32 flags)
 {
         size_t bytes;
-        void *va;
+        void *va = NULL;
 
         if (!obj || !obj->dev || !sgt)
                 return -EINVAL;
@@ -627,9 +625,11 @@ u32 iommu_vmap(struct iommu *obj, u32 da, const struct sg_table *sgt,
                 return -EINVAL;
         bytes = PAGE_ALIGN(bytes);
 
-        va = vmap_sg(sgt);
-        if (IS_ERR(va))
-                return PTR_ERR(va);
+        if (flags & IOVMF_MMIO) {
+                va = vmap_sg(sgt);
+                if (IS_ERR(va))
+                        return PTR_ERR(va);
+        }
 
         flags &= IOVMF_HW_MASK;
         flags |= IOVMF_DISCONT;
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index 40424edae939..08a2df766289 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -25,56 +25,15 @@
 #include <linux/interrupt.h>
 #include <linux/device.h>
 #include <linux/delay.h>
+#include <linux/slab.h>
 
-#include <mach/mailbox.h>
-
-static int enable_seq_bit;
-module_param(enable_seq_bit, bool, 0);
-MODULE_PARM_DESC(enable_seq_bit, "Enable sequence bit checking.");
+#include <plat/mailbox.h>
 
+static struct workqueue_struct *mboxd;
 static struct omap_mbox *mboxes;
 static DEFINE_RWLOCK(mboxes_lock);
 
-/*
- * Mailbox sequence bit API
- */
-
-/* seq_rcv should be initialized with any value other than
- * 0 and 1 << 31, to allow either value for the first
- * message.  */
-static inline void mbox_seq_init(struct omap_mbox *mbox)
-{
-        if (!enable_seq_bit)
-                return;
-
-        /* any value other than 0 and 1 << 31 */
-        mbox->seq_rcv = 0xffffffff;
-}
-
-static inline void mbox_seq_toggle(struct omap_mbox *mbox, mbox_msg_t * msg)
-{
-        if (!enable_seq_bit)
-                return;
-
-        /* add seq_snd to msg */
-        *msg = (*msg & 0x7fffffff) | mbox->seq_snd;
-        /* flip seq_snd */
-        mbox->seq_snd ^= 1 << 31;
-}
-
-static inline int mbox_seq_test(struct omap_mbox *mbox, mbox_msg_t msg)
-{
-        mbox_msg_t seq;
-
-        if (!enable_seq_bit)
-                return 0;
-
-        seq = msg & (1 << 31);
-        if (seq == mbox->seq_rcv)
-                return -1;
-        mbox->seq_rcv = seq;
-        return 0;
-}
+static int mbox_configured;
 
 /* Mailbox FIFO handle functions */
 static inline mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox)
@@ -95,14 +54,6 @@ static inline int mbox_fifo_full(struct omap_mbox *mbox)
 }
 
 /* Mailbox IRQ handle functions */
-static inline void enable_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
-{
-        mbox->ops->enable_irq(mbox, irq);
-}
-static inline void disable_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
-{
-        mbox->ops->disable_irq(mbox, irq);
-}
 static inline void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
 {
         if (mbox->ops->ack_irq)
@@ -113,17 +64,10 @@ static inline int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
         return mbox->ops->is_irq(mbox, irq);
 }
 
-/* Mailbox Sequence Bit function */
-void omap_mbox_init_seq(struct omap_mbox *mbox)
-{
-        mbox_seq_init(mbox);
-}
-EXPORT_SYMBOL(omap_mbox_init_seq);
-
 /*
  * message sender
  */
-static int __mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg, void *arg)
+static int __mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg)
 {
         int ret = 0, i = 1000;
 
@@ -134,89 +78,49 @@ static int __mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg, void *arg)
                         return -1;
                 udelay(1);
         }
-
-        if (arg && mbox->txq->callback) {
-                ret = mbox->txq->callback(arg);
-                if (ret)
-                        goto out;
-        }
-
-        mbox_seq_toggle(mbox, &msg);
         mbox_fifo_write(mbox, msg);
- out:
         return ret;
 }
 
-struct omap_msg_tx_data {
-        mbox_msg_t      msg;
-        void            *arg;
-};
 
-static void omap_msg_tx_end_io(struct request *rq, int error)
+int omap_mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg)
 {
-        kfree(rq->special);
-        __blk_put_request(rq->q, rq);
-}
 
-int omap_mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg, void* arg)
-{
-        struct omap_msg_tx_data *tx_data;
         struct request *rq;
         struct request_queue *q = mbox->txq->queue;
 
-        tx_data = kmalloc(sizeof(*tx_data), GFP_ATOMIC);
-        if (unlikely(!tx_data))
-                return -ENOMEM;
-
         rq = blk_get_request(q, WRITE, GFP_ATOMIC);
-        if (unlikely(!rq)) {
-                kfree(tx_data);
+        if (unlikely(!rq))
                 return -ENOMEM;
-        }
 
-        tx_data->msg = msg;
-        tx_data->arg = arg;
-        rq->end_io = omap_msg_tx_end_io;
-        blk_insert_request(q, rq, 0, tx_data);
+        blk_insert_request(q, rq, 0, (void *) msg);
+        tasklet_schedule(&mbox->txq->tasklet);
 
-        schedule_work(&mbox->txq->work);
         return 0;
 }
 EXPORT_SYMBOL(omap_mbox_msg_send);
 
-static void mbox_tx_work(struct work_struct *work)
+static void mbox_tx_tasklet(unsigned long tx_data)
 {
         int ret;
         struct request *rq;
-        struct omap_mbox_queue *mq = container_of(work,
-                                struct omap_mbox_queue, work);
-        struct omap_mbox *mbox = mq->queue->queuedata;
+        struct omap_mbox *mbox = (struct omap_mbox *)tx_data;
         struct request_queue *q = mbox->txq->queue;
 
         while (1) {
-                struct omap_msg_tx_data *tx_data;
 
-                spin_lock(q->queue_lock);
                 rq = blk_fetch_request(q);
-                spin_unlock(q->queue_lock);
 
                 if (!rq)
                         break;
 
-                tx_data = rq->special;
-
-                ret = __mbox_msg_send(mbox, tx_data->msg, tx_data->arg);
+                ret = __mbox_msg_send(mbox, (mbox_msg_t)rq->special);
                 if (ret) {
-                        enable_mbox_irq(mbox, IRQ_TX);
-                        spin_lock(q->queue_lock);
+                        omap_mbox_enable_irq(mbox, IRQ_TX);
                         blk_requeue_request(q, rq);
-                        spin_unlock(q->queue_lock);
                         return;
                 }
-
-                spin_lock(q->queue_lock);
-                __blk_end_request_all(rq, 0);
-                spin_unlock(q->queue_lock);
+                blk_end_request_all(rq, 0);
         }
 }
 
@@ -233,11 +137,6 @@ static void mbox_rx_work(struct work_struct *work)
         mbox_msg_t msg;
         unsigned long flags;
 
-        if (mbox->rxq->callback == NULL) {
-                sysfs_notify(&mbox->dev->kobj, NULL, "mbox");
-                return;
-        }
-
         while (1) {
                 spin_lock_irqsave(q->queue_lock, flags);
                 rq = blk_fetch_request(q);
@@ -254,19 +153,19 @@ static void mbox_rx_work(struct work_struct *work)
 /*
  * Mailbox interrupt handler
  */
-static void mbox_txq_fn(struct request_queue * q)
+static void mbox_txq_fn(struct request_queue *q)
 {
 }
 
-static void mbox_rxq_fn(struct request_queue * q)
+static void mbox_rxq_fn(struct request_queue *q)
 {
 }
 
 static void __mbox_tx_interrupt(struct omap_mbox *mbox)
 {
-        disable_mbox_irq(mbox, IRQ_TX);
+        omap_mbox_disable_irq(mbox, IRQ_TX);
         ack_mbox_irq(mbox, IRQ_TX);
-        schedule_work(&mbox->txq->work);
+        tasklet_schedule(&mbox->txq->tasklet);
 }
 
 static void __mbox_rx_interrupt(struct omap_mbox *mbox)
@@ -275,8 +174,6 @@ static void __mbox_rx_interrupt(struct omap_mbox *mbox)
         mbox_msg_t msg;
         struct request_queue *q = mbox->rxq->queue;
 
-        disable_mbox_irq(mbox, IRQ_RX);
-
         while (!mbox_fifo_empty(mbox)) {
                 rq = blk_get_request(q, WRITE, GFP_ATOMIC);
                 if (unlikely(!rq))
@@ -284,11 +181,6 @@ static void __mbox_rx_interrupt(struct omap_mbox *mbox)
 
                 msg = mbox_fifo_read(mbox);
 
-                if (unlikely(mbox_seq_test(mbox, msg))) {
-                        pr_info("mbox: Illegal seq bit!(%08x)\n", msg);
-                        if (mbox->err_notify)
-                                mbox->err_notify();
-                }
 
                 blk_insert_request(q, rq, 0, (void *)msg);
                 if (mbox->ops->type == OMAP_MBOX_TYPE1)
@@ -297,9 +189,8 @@ static void __mbox_rx_interrupt(struct omap_mbox *mbox)
 
         /* no more messages in the fifo. clear IRQ source. */
         ack_mbox_irq(mbox, IRQ_RX);
-        enable_mbox_irq(mbox, IRQ_RX);
 nomem:
-        schedule_work(&mbox->rxq->work);
+        queue_work(mboxd, &mbox->rxq->work);
 }
 
 static irqreturn_t mbox_interrupt(int irq, void *p)
@@ -315,76 +206,10 @@ static irqreturn_t mbox_interrupt(int irq, void *p)
         return IRQ_HANDLED;
 }
 
-/*
- * sysfs files
- */
-static ssize_t
-omap_mbox_write(struct device *dev, struct device_attribute *attr,
-                const char * buf, size_t count)
-{
-        int ret;
-        mbox_msg_t *p = (mbox_msg_t *)buf;
-        struct omap_mbox *mbox = dev_get_drvdata(dev);
-
-        for (; count >= sizeof(mbox_msg_t); count -= sizeof(mbox_msg_t)) {
-                ret = omap_mbox_msg_send(mbox, be32_to_cpu(*p), NULL);
-                if (ret)
-                        return -EAGAIN;
-                p++;
-        }
-
-        return (size_t)((char *)p - buf);
-}
-
-static ssize_t
-omap_mbox_read(struct device *dev, struct device_attribute *attr, char *buf)
-{
-        unsigned long flags;
-        struct request *rq;
-        mbox_msg_t *p = (mbox_msg_t *) buf;
-        struct omap_mbox *mbox = dev_get_drvdata(dev);
-        struct request_queue *q = mbox->rxq->queue;
-
-        while (1) {
-                spin_lock_irqsave(q->queue_lock, flags);
-                rq = blk_fetch_request(q);
-                spin_unlock_irqrestore(q->queue_lock, flags);
-
-                if (!rq)
-                        break;
-
-                *p = (mbox_msg_t)rq->special;
-
-                blk_end_request_all(rq, 0);
-
-                if (unlikely(mbox_seq_test(mbox, *p))) {
-                        pr_info("mbox: Illegal seq bit!(%08x) ignored\n", *p);
-                        continue;
-                }
-                p++;
-        }
-
-        pr_debug("%02x %02x %02x %02x\n", buf[0], buf[1], buf[2], buf[3]);
-
-        return (size_t) ((char *)p - buf);
-}
-
-static DEVICE_ATTR(mbox, S_IRUGO | S_IWUSR, omap_mbox_read, omap_mbox_write);
-
-static ssize_t mbox_show(struct class *class, char *buf)
-{
-        return sprintf(buf, "mbox");
-}
-
-static CLASS_ATTR(mbox, S_IRUGO, mbox_show, NULL);
-
-static struct class omap_mbox_class = {
-        .name = "omap-mailbox",
-};
-
 static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
-                                        request_fn_proc * proc,
-                                        void (*work) (struct work_struct *))
+                                        request_fn_proc *proc,
+                                        void (*work) (struct work_struct *),
+                                        void (*tasklet)(unsigned long))
 {
         struct request_queue *q;
         struct omap_mbox_queue *mq;
@@ -401,8 +226,11 @@ static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
         q->queuedata = mbox;
         mq->queue = q;
 
-        INIT_WORK(&mq->work, work);
+        if (work)
+                INIT_WORK(&mq->work, work);
 
+        if (tasklet)
+                tasklet_init(&mq->tasklet, tasklet, (unsigned long)mbox);
         return mq;
 error:
         kfree(mq);
@@ -415,18 +243,25 @@ static void mbox_queue_free(struct omap_mbox_queue *q)
         kfree(q);
 }
 
-static int omap_mbox_init(struct omap_mbox *mbox)
+static int omap_mbox_startup(struct omap_mbox *mbox)
 {
-        int ret;
+        int ret = 0;
         struct omap_mbox_queue *mq;
 
         if (likely(mbox->ops->startup)) {
-                ret = mbox->ops->startup(mbox);
-                if (unlikely(ret))
+                write_lock(&mboxes_lock);
+                if (!mbox_configured)
+                        ret = mbox->ops->startup(mbox);
+
+                if (unlikely(ret)) {
+                        write_unlock(&mboxes_lock);
                         return ret;
+                }
+                mbox_configured++;
+                write_unlock(&mboxes_lock);
         }
 
-        ret = request_irq(mbox->irq, mbox_interrupt, IRQF_DISABLED,
+        ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED,
                                 mbox->name, mbox);
         if (unlikely(ret)) {
                 printk(KERN_ERR
@@ -434,14 +269,14 @@ static int omap_mbox_init(struct omap_mbox *mbox)
                 goto fail_request_irq;
         }
 
-        mq = mbox_queue_alloc(mbox, mbox_txq_fn, mbox_tx_work);
+        mq = mbox_queue_alloc(mbox, mbox_txq_fn, NULL, mbox_tx_tasklet);
         if (!mq) {
                 ret = -ENOMEM;
                 goto fail_alloc_txq;
         }
         mbox->txq = mq;
 
-        mq = mbox_queue_alloc(mbox, mbox_rxq_fn, mbox_rx_work);
+        mq = mbox_queue_alloc(mbox, mbox_rxq_fn, mbox_rx_work, NULL);
         if (!mq) {
                 ret = -ENOMEM;
                 goto fail_alloc_rxq;
@@ -468,8 +303,14 @@ static void omap_mbox_fini(struct omap_mbox *mbox)
 
         free_irq(mbox->irq, mbox);
 
-        if (unlikely(mbox->ops->shutdown))
-                mbox->ops->shutdown(mbox);
+        if (unlikely(mbox->ops->shutdown)) {
+                write_lock(&mboxes_lock);
+                if (mbox_configured > 0)
+                        mbox_configured--;
+                if (!mbox_configured)
+                        mbox->ops->shutdown(mbox);
+                write_unlock(&mboxes_lock);
+        }
 }
 
 static struct omap_mbox **find_mboxes(const char *name)
@@ -498,7 +339,7 @@ struct omap_mbox *omap_mbox_get(const char *name)
 
         read_unlock(&mboxes_lock);
 
-        ret = omap_mbox_init(mbox);
+        ret = omap_mbox_startup(mbox);
         if (ret)
                 return ERR_PTR(-ENODEV);
 
@@ -522,15 +363,6 @@ int omap_mbox_register(struct device *parent, struct omap_mbox *mbox)
         if (mbox->next)
                 return -EBUSY;
 
-        mbox->dev = device_create(&omap_mbox_class,
-                                  parent, 0, mbox, "%s", mbox->name);
-        if (IS_ERR(mbox->dev))
-                return PTR_ERR(mbox->dev);
-
-        ret = device_create_file(mbox->dev, &dev_attr_mbox);
-        if (ret)
-                goto err_sysfs;
-
         write_lock(&mboxes_lock);
         tmp = find_mboxes(mbox->name);
         if (*tmp) {
@@ -544,9 +376,6 @@ int omap_mbox_register(struct device *parent, struct omap_mbox *mbox)
         return 0;
 
 err_find:
-        device_remove_file(mbox->dev, &dev_attr_mbox);
-err_sysfs:
-        device_unregister(mbox->dev);
         return ret;
 }
 EXPORT_SYMBOL(omap_mbox_register);
@@ -562,8 +391,6 @@ int omap_mbox_unregister(struct omap_mbox *mbox)
                         *tmp = mbox->next;
                         mbox->next = NULL;
                         write_unlock(&mboxes_lock);
-                        device_remove_file(mbox->dev, &dev_attr_mbox);
-                        device_unregister(mbox->dev);
                         return 0;
                 }
                 tmp = &(*tmp)->next;
@@ -574,23 +401,21 @@ int omap_mbox_unregister(struct omap_mbox *mbox)
 }
 EXPORT_SYMBOL(omap_mbox_unregister);
 
-static int __init omap_mbox_class_init(void)
+static int __init omap_mbox_init(void)
 {
-        int ret = class_register(&omap_mbox_class);
-        if (!ret)
-                ret = class_create_file(&omap_mbox_class, &class_attr_mbox);
+        mboxd = create_workqueue("mboxd");
+        if (!mboxd)
+                return -ENOMEM;
 
-        return ret;
+        return 0;
 }
+module_init(omap_mbox_init);
 
-static void __exit omap_mbox_class_exit(void)
+static void __exit omap_mbox_exit(void)
 {
-        class_remove_file(&omap_mbox_class, &class_attr_mbox);
-        class_unregister(&omap_mbox_class);
+        destroy_workqueue(mboxd);
 }
-
-subsys_initcall(omap_mbox_class_init);
-module_exit(omap_mbox_class_exit);
+module_exit(omap_mbox_exit);
 
 MODULE_LICENSE("GPL v2");
 MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging");
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index e664b912d7bb..e1d0440fd4a8 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -23,68 +23,102 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/io.h>
+#include <linux/slab.h>
 
-#include <mach/dma.h>
-#include <mach/mcbsp.h>
+#include <plat/dma.h>
+#include <plat/mcbsp.h>
+
+#include "../mach-omap2/cm-regbits-34xx.h"
 
 struct omap_mcbsp **mcbsp_ptr;
-int omap_mcbsp_count;
+int omap_mcbsp_count, omap_mcbsp_cache_size;
 
-void omap_mcbsp_write(void __iomem *io_base, u16 reg, u32 val)
+void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
 {
-        if (cpu_class_is_omap1() || cpu_is_omap2420())
-                __raw_writew((u16)val, io_base + reg);
-        else
-                __raw_writel(val, io_base + reg);
+        if (cpu_class_is_omap1()) {
+                ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
+                __raw_writew((u16)val, mcbsp->io_base + reg);
+        } else if (cpu_is_omap2420()) {
+                ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val;
+                __raw_writew((u16)val, mcbsp->io_base + reg);
+        } else {
+                ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val;
+                __raw_writel(val, mcbsp->io_base + reg);
+        }
 }
 
-int omap_mcbsp_read(void __iomem *io_base, u16 reg)
+int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
 {
-        if (cpu_class_is_omap1() || cpu_is_omap2420())
-                return __raw_readw(io_base + reg);
-        else
-                return __raw_readl(io_base + reg);
+        if (cpu_class_is_omap1()) {
+                return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
+                                ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)];
+        } else if (cpu_is_omap2420()) {
+                return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
+                                ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
+        } else {
+                return !from_cache ? __raw_readl(mcbsp->io_base + reg) :
+                                ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)];
+        }
+}
+
+#ifdef CONFIG_ARCH_OMAP3
+void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
+{
+        __raw_writel(val, mcbsp->st_data->io_base_st + reg);
 }
 
-#define OMAP_MCBSP_READ(base, reg) \
-                        omap_mcbsp_read(base, OMAP_MCBSP_REG_##reg)
-#define OMAP_MCBSP_WRITE(base, reg, val) \
-                        omap_mcbsp_write(base, OMAP_MCBSP_REG_##reg, val)
+int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
+{
+        return __raw_readl(mcbsp->st_data->io_base_st + reg);
+}
+#endif
+
+#define MCBSP_READ(mcbsp, reg) \
+                omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
+#define MCBSP_WRITE(mcbsp, reg, val) \
+                omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
+#define MCBSP_READ_CACHE(mcbsp, reg) \
+                omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
 
 #define omap_mcbsp_check_valid_id(id)   (id < omap_mcbsp_count)
 #define id_to_mcbsp_ptr(id)             mcbsp_ptr[id];
 
+#define MCBSP_ST_READ(mcbsp, reg) \
+                        omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
+#define MCBSP_ST_WRITE(mcbsp, reg, val) \
+                        omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
+
 static void omap_mcbsp_dump_reg(u8 id)
 {
         struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
 
         dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
         dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n",
-                        OMAP_MCBSP_READ(mcbsp->io_base, DRR2));
+                        MCBSP_READ(mcbsp, DRR2));
         dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n",
-                        OMAP_MCBSP_READ(mcbsp->io_base, DRR1));
+                        MCBSP_READ(mcbsp, DRR1));
         dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n",
-                        OMAP_MCBSP_READ(mcbsp->io_base, DXR2));
+                        MCBSP_READ(mcbsp, DXR2));
         dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n",
-                        OMAP_MCBSP_READ(mcbsp->io_base, DXR1));
+                        MCBSP_READ(mcbsp, DXR1));
         dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
-                        OMAP_MCBSP_READ(mcbsp->io_base, SPCR2));
+                        MCBSP_READ(mcbsp, SPCR2));
         dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
-                        OMAP_MCBSP_READ(mcbsp->io_base, SPCR1));
+                        MCBSP_READ(mcbsp, SPCR1));
         dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n",
-                        OMAP_MCBSP_READ(mcbsp->io_base, RCR2));
+                        MCBSP_READ(mcbsp, RCR2));
         dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n",
-                        OMAP_MCBSP_READ(mcbsp->io_base, RCR1));
+                        MCBSP_READ(mcbsp, RCR1));
         dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n",
-                        OMAP_MCBSP_READ(mcbsp->io_base, XCR2));
+                        MCBSP_READ(mcbsp, XCR2));
         dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n",
-                        OMAP_MCBSP_READ(mcbsp->io_base, XCR1));
+                        MCBSP_READ(mcbsp, XCR1));
         dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
-                        OMAP_MCBSP_READ(mcbsp->io_base, SRGR2));
+                        MCBSP_READ(mcbsp, SRGR2));
         dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
-                        OMAP_MCBSP_READ(mcbsp->io_base, SRGR1));
+                        MCBSP_READ(mcbsp, SRGR1));
         dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n",
-                        OMAP_MCBSP_READ(mcbsp->io_base, PCR0));
+                        MCBSP_READ(mcbsp, PCR0));
         dev_dbg(mcbsp->dev, "***********************\n");
 }
 
@@ -93,15 +127,14 @@ static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
         struct omap_mcbsp *mcbsp_tx = dev_id;
         u16 irqst_spcr2;
 
-        irqst_spcr2 = OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2);
+        irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
         dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
 
         if (irqst_spcr2 & XSYNC_ERR) {
                 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
                         irqst_spcr2);
                 /* Writing zero to XSYNC_ERR clears the IRQ */
-                OMAP_MCBSP_WRITE(mcbsp_tx->io_base, SPCR2,
-                        irqst_spcr2 & ~(XSYNC_ERR));
+                MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
         } else {
                 complete(&mcbsp_tx->tx_irq_completion);
         }
@@ -114,15 +147,14 @@ static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
         struct omap_mcbsp *mcbsp_rx = dev_id;
         u16 irqst_spcr1;
 
-        irqst_spcr1 = OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR1);
+        irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
         dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
 
         if (irqst_spcr1 & RSYNC_ERR) {
                 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
                         irqst_spcr1);
                 /* Writing zero to RSYNC_ERR clears the IRQ */
-                OMAP_MCBSP_WRITE(mcbsp_rx->io_base, SPCR1,
-                        irqst_spcr1 & ~(RSYNC_ERR));
+                MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
         } else {
                 complete(&mcbsp_rx->tx_irq_completion);
         }
@@ -135,7 +167,7 @@ static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
         struct omap_mcbsp *mcbsp_dma_tx = data;
 
         dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
-                OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
+                MCBSP_READ(mcbsp_dma_tx, SPCR2));
 
         /* We can free the channels */
         omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
@@ -149,7 +181,7 @@ static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
         struct omap_mcbsp *mcbsp_dma_rx = data;
 
         dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
-                OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
+                MCBSP_READ(mcbsp_dma_rx, SPCR2));
 
         /* We can free the channels */
         omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
@@ -167,7 +199,6 @@ static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
 {
         struct omap_mcbsp *mcbsp;
-        void __iomem *io_base;
 
         if (!omap_mcbsp_check_valid_id(id)) {
                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
@@ -175,30 +206,280 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
         }
         mcbsp = id_to_mcbsp_ptr(id);
 
-        io_base = mcbsp->io_base;
         dev_dbg(mcbsp->dev, "Configuring McBSP%d  phys_base: 0x%08lx\n",
                         mcbsp->id, mcbsp->phys_base);
 
         /* We write the given config */
-        OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
-        OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
-        OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
-        OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
-        OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
-        OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
-        OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
-        OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
-        OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
-        OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
-        OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
+        MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
+        MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
+        MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
+        MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
+        MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
+        MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
+        MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
+        MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
+        MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
+        MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
+        MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
-                OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr);
-                OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr);
+                MCBSP_WRITE(mcbsp, XCCR, config->xccr);
+                MCBSP_WRITE(mcbsp, RCCR, config->rccr);
         }
 }
 EXPORT_SYMBOL(omap_mcbsp_config);
 
-#ifdef CONFIG_ARCH_OMAP34XX
+#ifdef CONFIG_ARCH_OMAP3
+static void omap_st_on(struct omap_mcbsp *mcbsp)
+{
+        unsigned int w;
+
+        /*
+         * Sidetone uses McBSP ICLK - which must not idle when sidetones
+         * are enabled or sidetones start sounding ugly.
+         */
+        w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
+        w &= ~(1 << (mcbsp->id - 2));
+        cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
+
+        /* Enable McBSP Sidetone */
+        w = MCBSP_READ(mcbsp, SSELCR);
+        MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
+
+        w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
+        MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
+
+        /* Enable Sidetone from Sidetone Core */
+        w = MCBSP_ST_READ(mcbsp, SSELCR);
+        MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
+}
+
+static void omap_st_off(struct omap_mcbsp *mcbsp)
+{
+        unsigned int w;
+
+        w = MCBSP_ST_READ(mcbsp, SSELCR);
+        MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
+
+        w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
+        MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w | ST_AUTOIDLE);
+
+        w = MCBSP_READ(mcbsp, SSELCR);
+        MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
+
+        w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
+        w |= 1 << (mcbsp->id - 2);
+        cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
+}
+
+static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
+{
+        u16 val, i;
+
+        val = MCBSP_ST_READ(mcbsp, SYSCONFIG);
+        MCBSP_ST_WRITE(mcbsp, SYSCONFIG, val & ~(ST_AUTOIDLE));
+
+        val = MCBSP_ST_READ(mcbsp, SSELCR);
+
+        if (val & ST_COEFFWREN)
+                MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
+
+        MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
+
+        for (i = 0; i < 128; i++)
+                MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
+
+        i = 0;
+
+        val = MCBSP_ST_READ(mcbsp, SSELCR);
+        while (!(val & ST_COEFFWRDONE) && (++i < 1000))
+                val = MCBSP_ST_READ(mcbsp, SSELCR);
+
+        MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
+
+        if (i == 1000)
+                dev_err(mcbsp->dev, "McBSP FIR load error!\n");
+}
+
+static void omap_st_chgain(struct omap_mcbsp *mcbsp)
+{
+        u16 w;
+        struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
+
+        w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
+        MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
+
+        w = MCBSP_ST_READ(mcbsp, SSELCR);
+
+        MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
+                      ST_CH1GAIN(st_data->ch1gain));
+}
+
+int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
+{
+        struct omap_mcbsp *mcbsp;
+        struct omap_mcbsp_st_data *st_data;
+        int ret = 0;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+
+        mcbsp = id_to_mcbsp_ptr(id);
+        st_data = mcbsp->st_data;
+
+        if (!st_data)
+                return -ENOENT;
+
+        spin_lock_irq(&mcbsp->lock);
+        if (channel == 0)
+                st_data->ch0gain = chgain;
+        else if (channel == 1)
+                st_data->ch1gain = chgain;
+        else
+                ret = -EINVAL;
+
+        if (st_data->enabled)
+                omap_st_chgain(mcbsp);
+        spin_unlock_irq(&mcbsp->lock);
+
+        return ret;
+}
+EXPORT_SYMBOL(omap_st_set_chgain);
+
+int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
+{
+        struct omap_mcbsp *mcbsp;
+        struct omap_mcbsp_st_data *st_data;
+        int ret = 0;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+
+        mcbsp = id_to_mcbsp_ptr(id);
+        st_data = mcbsp->st_data;
+
+        if (!st_data)
+                return -ENOENT;
+
+        spin_lock_irq(&mcbsp->lock);
+        if (channel == 0)
+                *chgain = st_data->ch0gain;
+        else if (channel == 1)
+                *chgain = st_data->ch1gain;
+        else
+                ret = -EINVAL;
+        spin_unlock_irq(&mcbsp->lock);
+
+        return ret;
+}
+EXPORT_SYMBOL(omap_st_get_chgain);
+
+static int omap_st_start(struct omap_mcbsp *mcbsp)
+{
+        struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
+
+        if (st_data && st_data->enabled && !st_data->running) {
+                omap_st_fir_write(mcbsp, st_data->taps);
+                omap_st_chgain(mcbsp);
+
+                if (!mcbsp->free) {
+                        omap_st_on(mcbsp);
+                        st_data->running = 1;
+                }
+        }
+
+        return 0;
+}
+
+int omap_st_enable(unsigned int id)
+{
+        struct omap_mcbsp *mcbsp;
+        struct omap_mcbsp_st_data *st_data;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+
+        mcbsp = id_to_mcbsp_ptr(id);
+        st_data = mcbsp->st_data;
+
+        if (!st_data)
+                return -ENODEV;
+
+        spin_lock_irq(&mcbsp->lock);
+        st_data->enabled = 1;
+        omap_st_start(mcbsp);
+        spin_unlock_irq(&mcbsp->lock);
+
+        return 0;
+}
+EXPORT_SYMBOL(omap_st_enable);
+
+static int omap_st_stop(struct omap_mcbsp *mcbsp)
+{
+        struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
+
+        if (st_data && st_data->running) {
+                if (!mcbsp->free) {
+                        omap_st_off(mcbsp);
+                        st_data->running = 0;
+                }
+        }
+
+        return 0;
+}
+
+int omap_st_disable(unsigned int id)
+{
+        struct omap_mcbsp *mcbsp;
+        struct omap_mcbsp_st_data *st_data;
+        int ret = 0;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+
+        mcbsp = id_to_mcbsp_ptr(id);
+        st_data = mcbsp->st_data;
+
+        if (!st_data)
+                return -ENODEV;
+
+        spin_lock_irq(&mcbsp->lock);
+        omap_st_stop(mcbsp);
+        st_data->enabled = 0;
+        spin_unlock_irq(&mcbsp->lock);
+
+        return ret;
+}
+EXPORT_SYMBOL(omap_st_disable);
+
+int omap_st_is_enabled(unsigned int id)
+{
+        struct omap_mcbsp *mcbsp;
+        struct omap_mcbsp_st_data *st_data;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+
+        mcbsp = id_to_mcbsp_ptr(id);
+        st_data = mcbsp->st_data;
+
+        if (!st_data)
+                return -ENODEV;
+
+
+        return st_data->enabled;
+}
+EXPORT_SYMBOL(omap_st_is_enabled);
+
 /*
  * omap_mcbsp_set_tx_threshold configures how to deal
  * with transmit threshold. the threshold value and handler can be
@@ -207,7 +488,6 @@ EXPORT_SYMBOL(omap_mcbsp_config);
 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
 {
         struct omap_mcbsp *mcbsp;
-        void __iomem *io_base;
 
         if (!cpu_is_omap34xx())
                 return;
@@ -217,9 +497,8 @@ void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
                 return;
         }
         mcbsp = id_to_mcbsp_ptr(id);
-        io_base = mcbsp->io_base;
 
-        OMAP_MCBSP_WRITE(io_base, THRSH2, threshold);
+        MCBSP_WRITE(mcbsp, THRSH2, threshold);
 }
 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
 
@@ -231,7 +510,6 @@ EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
 {
         struct omap_mcbsp *mcbsp;
-        void __iomem *io_base;
 
         if (!cpu_is_omap34xx())
                 return;
@@ -241,9 +519,8 @@ void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
                 return;
         }
         mcbsp = id_to_mcbsp_ptr(id);
-        io_base = mcbsp->io_base;
 
-        OMAP_MCBSP_WRITE(io_base, THRSH1, threshold);
+        MCBSP_WRITE(mcbsp, THRSH1, threshold);
 }
 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
 
@@ -298,9 +575,7 @@ int omap_mcbsp_get_dma_op_mode(unsigned int id)
         }
         mcbsp = id_to_mcbsp_ptr(id);
 
-        spin_lock_irq(&mcbsp->lock);
         dma_op_mode = mcbsp->dma_op_mode;
-        spin_unlock_irq(&mcbsp->lock);
 
         return dma_op_mode;
 }
@@ -315,21 +590,18 @@ static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
         if (cpu_is_omap34xx()) {
                 u16 syscon;
 
-                syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
+                syscon = MCBSP_READ(mcbsp, SYSCON);
                 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
 
-                spin_lock_irq(&mcbsp->lock);
                 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
                         syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
                                         CLOCKACTIVITY(0x02));
-                        OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN,
-                                        XRDYEN | RRDYEN);
+                        MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
                 } else {
                         syscon |= SIDLEMODE(0x01);
                 }
-                spin_unlock_irq(&mcbsp->lock);
 
-                OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
+                MCBSP_WRITE(mcbsp, SYSCON, syscon);
         }
 }
 
@@ -341,7 +613,7 @@ static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
         if (cpu_is_omap34xx()) {
                 u16 syscon;
 
-                syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
+                syscon = MCBSP_READ(mcbsp, SYSCON);
                 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
                 /*
                  * HW bug workaround - If no_idle mode is taken, we need to
@@ -349,17 +621,19 @@ static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
                  * device will not hit retention anymore.
                  */
                 syscon |= SIDLEMODE(0x02);
-                OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
+                MCBSP_WRITE(mcbsp, SYSCON, syscon);
 
                 syscon &= ~(SIDLEMODE(0x03));
-                OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
+                MCBSP_WRITE(mcbsp, SYSCON, syscon);
 
-                OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN, 0);
+                MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
         }
 }
 #else
 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
+static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
+static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
 #endif
 
 /*
@@ -396,6 +670,7 @@ EXPORT_SYMBOL(omap_mcbsp_set_io_type);
 int omap_mcbsp_request(unsigned int id)
 {
         struct omap_mcbsp *mcbsp;
+        void *reg_cache;
         int err;
 
         if (!omap_mcbsp_check_valid_id(id)) {
@@ -404,15 +679,21 @@ int omap_mcbsp_request(unsigned int id)
         }
         mcbsp = id_to_mcbsp_ptr(id);
 
+        reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL);
+        if (!reg_cache) {
+                return -ENOMEM;
+        }
+
         spin_lock(&mcbsp->lock);
         if (!mcbsp->free) {
                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
                         mcbsp->id);
-                spin_unlock(&mcbsp->lock);
-                return -EBUSY;
+                err = -EBUSY;
+                goto err_kfree;
         }
 
         mcbsp->free = 0;
+        mcbsp->reg_cache = reg_cache;
         spin_unlock(&mcbsp->lock);
 
         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
@@ -428,8 +709,8 @@ int omap_mcbsp_request(unsigned int id)
          * Make sure that transmitter, receiver and sample-rate generator are
          * not running before activating IRQs.
          */
-        OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR1, 0);
-        OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR2, 0);
+        MCBSP_WRITE(mcbsp, SPCR1, 0);
+        MCBSP_WRITE(mcbsp, SPCR2, 0);
 
         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
                 /* We need to get IRQs here */
@@ -440,7 +721,7 @@ int omap_mcbsp_request(unsigned int id)
                         dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
                                         "for McBSP%d\n", mcbsp->tx_irq,
                                         mcbsp->id);
-                        return err;
+                        goto err_clk_disable;
                 }
 
                 init_completion(&mcbsp->rx_irq_completion);
@@ -450,18 +731,38 @@ int omap_mcbsp_request(unsigned int id)
                         dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
                                         "for McBSP%d\n", mcbsp->rx_irq,
                                         mcbsp->id);
-                        free_irq(mcbsp->tx_irq, (void *)mcbsp);
-                        return err;
+                        goto err_free_irq;
                 }
         }
 
         return 0;
+err_free_irq:
+        free_irq(mcbsp->tx_irq, (void *)mcbsp);
+err_clk_disable:
+        if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
+                mcbsp->pdata->ops->free(id);
+
+        /* Do procedure specific to omap34xx arch, if applicable */
+        omap34xx_mcbsp_free(mcbsp);
+
+        clk_disable(mcbsp->fclk);
+        clk_disable(mcbsp->iclk);
+
+        spin_lock(&mcbsp->lock);
+        mcbsp->free = 1;
+        mcbsp->reg_cache = NULL;
+err_kfree:
+        spin_unlock(&mcbsp->lock);
+        kfree(reg_cache);
+
+        return err;
 }
 EXPORT_SYMBOL(omap_mcbsp_request);
 
 void omap_mcbsp_free(unsigned int id)
 {
         struct omap_mcbsp *mcbsp;
+        void *reg_cache;
 
         if (!omap_mcbsp_check_valid_id(id)) {
                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
@@ -484,16 +785,18 @@ void omap_mcbsp_free(unsigned int id)
                 free_irq(mcbsp->tx_irq, (void *)mcbsp);
         }
 
-        spin_lock(&mcbsp->lock);
-        if (mcbsp->free) {
-                dev_err(mcbsp->dev, "McBSP%d was not reserved\n",
-                        mcbsp->id);
-                spin_unlock(&mcbsp->lock);
-                return;
-        }
+        reg_cache = mcbsp->reg_cache;
 
-        mcbsp->free = 1;
+        spin_lock(&mcbsp->lock);
+        if (mcbsp->free)
+                dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
+        else
+                mcbsp->free = 1;
+        mcbsp->reg_cache = NULL;
         spin_unlock(&mcbsp->lock);
+
+        if (reg_cache)
+                kfree(reg_cache);
 }
 EXPORT_SYMBOL(omap_mcbsp_free);
 
@@ -505,7 +808,6 @@ EXPORT_SYMBOL(omap_mcbsp_free);
 void omap_mcbsp_start(unsigned int id, int tx, int rx)
 {
         struct omap_mcbsp *mcbsp;
-        void __iomem *io_base;
         int idle;
         u16 w;
 
@@ -514,28 +816,30 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
                 return;
         }
         mcbsp = id_to_mcbsp_ptr(id);
-        io_base = mcbsp->io_base;
 
-        mcbsp->rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
-        mcbsp->tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
+        if (cpu_is_omap34xx())
+                omap_st_start(mcbsp);
+
+        mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
+        mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
 
-        idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
-                  OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
+        idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
+                        MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 
         if (idle) {
                 /* Start the sample generator */
-                w = OMAP_MCBSP_READ(io_base, SPCR2);
-                OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
+                w = MCBSP_READ_CACHE(mcbsp, SPCR2);
+                MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
         }
 
         /* Enable transmitter and receiver */
         tx &= 1;
-        w = OMAP_MCBSP_READ(io_base, SPCR2);
-        OMAP_MCBSP_WRITE(io_base, SPCR2, w | tx);
+        w = MCBSP_READ_CACHE(mcbsp, SPCR2);
+        MCBSP_WRITE(mcbsp, SPCR2, w | tx);
 
         rx &= 1;
-        w = OMAP_MCBSP_READ(io_base, SPCR1);
-        OMAP_MCBSP_WRITE(io_base, SPCR1, w | rx);
+        w = MCBSP_READ_CACHE(mcbsp, SPCR1);
+        MCBSP_WRITE(mcbsp, SPCR1, w | rx);
 
         /*
          * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
@@ -547,18 +851,18 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
 
         if (idle) {
                 /* Start frame sync */
-                w = OMAP_MCBSP_READ(io_base, SPCR2);
-                OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
+                w = MCBSP_READ_CACHE(mcbsp, SPCR2);
+                MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
         }
 
         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
                 /* Release the transmitter and receiver */
-                w = OMAP_MCBSP_READ(io_base, XCCR);
+                w = MCBSP_READ_CACHE(mcbsp, XCCR);
                 w &= ~(tx ? XDISABLE : 0);
-                OMAP_MCBSP_WRITE(io_base, XCCR, w);
-                w = OMAP_MCBSP_READ(io_base, RCCR);
+                MCBSP_WRITE(mcbsp, XCCR, w);
+                w = MCBSP_READ_CACHE(mcbsp, RCCR);
                 w &= ~(rx ? RDISABLE : 0);
-                OMAP_MCBSP_WRITE(io_base, RCCR, w);
+                MCBSP_WRITE(mcbsp, RCCR, w);
         }
 
         /* Dump McBSP Regs */
@@ -569,7 +873,6 @@ EXPORT_SYMBOL(omap_mcbsp_start);
 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
 {
         struct omap_mcbsp *mcbsp;
-        void __iomem *io_base;
         int idle;
         u16 w;
 
@@ -579,36 +882,38 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
         }
 
         mcbsp = id_to_mcbsp_ptr(id);
-        io_base = mcbsp->io_base;
 
         /* Reset transmitter */
         tx &= 1;
         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
-                w = OMAP_MCBSP_READ(io_base, XCCR);
+                w = MCBSP_READ_CACHE(mcbsp, XCCR);
                 w |= (tx ? XDISABLE : 0);
-                OMAP_MCBSP_WRITE(io_base, XCCR, w);
+                MCBSP_WRITE(mcbsp, XCCR, w);
         }
-        w = OMAP_MCBSP_READ(io_base, SPCR2);
-        OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~tx);
+        w = MCBSP_READ_CACHE(mcbsp, SPCR2);
+        MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
 
         /* Reset receiver */
         rx &= 1;
         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
-                w = OMAP_MCBSP_READ(io_base, RCCR);
+                w = MCBSP_READ_CACHE(mcbsp, RCCR);
                 w |= (rx ? RDISABLE : 0);
-                OMAP_MCBSP_WRITE(io_base, RCCR, w);
+                MCBSP_WRITE(mcbsp, RCCR, w);
         }
-        w = OMAP_MCBSP_READ(io_base, SPCR1);
-        OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~rx);
+        w = MCBSP_READ_CACHE(mcbsp, SPCR1);
+        MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
 
-        idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
-                  OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
+        idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
+                        MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 
         if (idle) {
                 /* Reset the sample rate generator */
-                w = OMAP_MCBSP_READ(io_base, SPCR2);
-                OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
+                w = MCBSP_READ_CACHE(mcbsp, SPCR2);
+                MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
         }
+
+        if (cpu_is_omap34xx())
+                omap_st_stop(mcbsp);
 }
 EXPORT_SYMBOL(omap_mcbsp_stop);
 
@@ -616,7 +921,6 @@ EXPORT_SYMBOL(omap_mcbsp_stop);
 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
 {
         struct omap_mcbsp *mcbsp;
-        void __iomem *base;
 
         if (!omap_mcbsp_check_valid_id(id)) {
                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
@@ -624,28 +928,26 @@ int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
         }
 
         mcbsp = id_to_mcbsp_ptr(id);
-        base = mcbsp->io_base;
 
-        writew(buf, base + OMAP_MCBSP_REG_DXR1);
+        MCBSP_WRITE(mcbsp, DXR1, buf);
         /* if frame sync error - clear the error */
-        if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
+        if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) {
                 /* clear error */
-                writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
-                       base + OMAP_MCBSP_REG_SPCR2);
+                MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
                 /* resend */
                 return -1;
         } else {
                 /* wait for transmit confirmation */
                 int attemps = 0;
-                while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
+                while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) {
                         if (attemps++ > 1000) {
-                                writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
-                                       (~XRST),
-                                       base + OMAP_MCBSP_REG_SPCR2);
+                                MCBSP_WRITE(mcbsp, SPCR2,
+                                                MCBSP_READ_CACHE(mcbsp, SPCR2) &
+                                                (~XRST));
                                 udelay(10);
-                                writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
-                                       (XRST),
-                                       base + OMAP_MCBSP_REG_SPCR2);
+                                MCBSP_WRITE(mcbsp, SPCR2,
+                                                MCBSP_READ_CACHE(mcbsp, SPCR2) |
+                                                (XRST));
                                 udelay(10);
                                 dev_err(mcbsp->dev, "Could not write to"
                                         " McBSP%d Register\n", mcbsp->id);
@@ -661,7 +963,6 @@ EXPORT_SYMBOL(omap_mcbsp_pollwrite);
 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
 {
         struct omap_mcbsp *mcbsp;
-        void __iomem *base;
 
         if (!omap_mcbsp_check_valid_id(id)) {
                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
@@ -669,26 +970,24 @@ int omap_mcbsp_pollread(unsigned int id, u16 *buf)
         }
         mcbsp = id_to_mcbsp_ptr(id);
 
-        base = mcbsp->io_base;
         /* if frame sync error - clear the error */
-        if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
+        if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) {
                 /* clear error */
-                writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
-                       base + OMAP_MCBSP_REG_SPCR1);
+                MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
                 /* resend */
                 return -1;
         } else {
                 /* wait for recieve confirmation */
                 int attemps = 0;
-                while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
+                while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
                         if (attemps++ > 1000) {
-                                writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
-                                       (~RRST),
-                                       base + OMAP_MCBSP_REG_SPCR1);
+                                MCBSP_WRITE(mcbsp, SPCR1,
+                                                MCBSP_READ_CACHE(mcbsp, SPCR1) &
+                                                (~RRST));
                                 udelay(10);
-                                writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
-                                       (RRST),
-                                       base + OMAP_MCBSP_REG_SPCR1);
+                                MCBSP_WRITE(mcbsp, SPCR1,
+                                                MCBSP_READ_CACHE(mcbsp, SPCR1) |
+                                                (RRST));
                                 udelay(10);
                                 dev_err(mcbsp->dev, "Could not read from"
                                         " McBSP%d Register\n", mcbsp->id);
@@ -696,7 +995,7 @@ int omap_mcbsp_pollread(unsigned int id, u16 *buf)
                         }
                 }
         }
-        *buf = readw(base + OMAP_MCBSP_REG_DRR1);
+        *buf = MCBSP_READ(mcbsp, DRR1);
 
         return 0;
 }
@@ -708,7 +1007,6 @@ EXPORT_SYMBOL(omap_mcbsp_pollread);
 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
 {
         struct omap_mcbsp *mcbsp;
-        void __iomem *io_base;
         omap_mcbsp_word_length word_length;
 
         if (!omap_mcbsp_check_valid_id(id)) {
@@ -717,21 +1015,19 @@ void omap_mcbsp_xmit_word(unsigned int id, u32 word)
         }
 
         mcbsp = id_to_mcbsp_ptr(id);
-        io_base = mcbsp->io_base;
         word_length = mcbsp->tx_word_length;
 
         wait_for_completion(&mcbsp->tx_irq_completion);
 
         if (word_length > OMAP_MCBSP_WORD_16)
-                OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
-        OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
+                MCBSP_WRITE(mcbsp, DXR2, word >> 16);
+        MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
 }
 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
 
 u32 omap_mcbsp_recv_word(unsigned int id)
 {
         struct omap_mcbsp *mcbsp;
-        void __iomem *io_base;
         u16 word_lsb, word_msb = 0;
         omap_mcbsp_word_length word_length;
 
@@ -742,13 +1038,12 @@ u32 omap_mcbsp_recv_word(unsigned int id)
         mcbsp = id_to_mcbsp_ptr(id);
 
         word_length = mcbsp->rx_word_length;
-        io_base = mcbsp->io_base;
 
         wait_for_completion(&mcbsp->rx_irq_completion);
 
         if (word_length > OMAP_MCBSP_WORD_16)
-                word_msb = OMAP_MCBSP_READ(io_base, DRR2);
-        word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
+                word_msb = MCBSP_READ(mcbsp, DRR2);
+        word_lsb = MCBSP_READ(mcbsp, DRR1);
 
         return (word_lsb | (word_msb << 16));
 }
@@ -757,7 +1052,6 @@ EXPORT_SYMBOL(omap_mcbsp_recv_word);
 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
 {
         struct omap_mcbsp *mcbsp;
-        void __iomem *io_base;
         omap_mcbsp_word_length tx_word_length;
         omap_mcbsp_word_length rx_word_length;
         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
@@ -767,7 +1061,6 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
                 return -ENODEV;
         }
         mcbsp = id_to_mcbsp_ptr(id);
-        io_base = mcbsp->io_base;
         tx_word_length = mcbsp->tx_word_length;
         rx_word_length = mcbsp->rx_word_length;
 
@@ -775,14 +1068,16 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
                 return -EINVAL;
 
         /* First we wait for the transmitter to be ready */
-        spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
+        spcr2 = MCBSP_READ(mcbsp, SPCR2);
         while (!(spcr2 & XRDY)) {
-                spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
+                spcr2 = MCBSP_READ(mcbsp, SPCR2);
                 if (attempts++ > 1000) {
                         /* We must reset the transmitter */
-                        OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
+                        MCBSP_WRITE(mcbsp, SPCR2,
+                                    MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
                         udelay(10);
-                        OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
+                        MCBSP_WRITE(mcbsp, SPCR2,
+                                    MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
                         udelay(10);
                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
                                 "ready\n", mcbsp->id);
@@ -792,18 +1087,20 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
 
         /* Now we can push the data */
         if (tx_word_length > OMAP_MCBSP_WORD_16)
-                OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
-        OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
+                MCBSP_WRITE(mcbsp, DXR2, word >> 16);
+        MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
 
         /* We wait for the receiver to be ready */
-        spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
+        spcr1 = MCBSP_READ(mcbsp, SPCR1);
         while (!(spcr1 & RRDY)) {
-                spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
+                spcr1 = MCBSP_READ(mcbsp, SPCR1);
                 if (attempts++ > 1000) {
                         /* We must reset the receiver */
-                        OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
+                        MCBSP_WRITE(mcbsp, SPCR1,
+                                    MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
                         udelay(10);
-                        OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
+                        MCBSP_WRITE(mcbsp, SPCR1,
+                                    MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
                         udelay(10);
                         dev_err(mcbsp->dev, "McBSP%d receiver not "
                                 "ready\n", mcbsp->id);
@@ -813,8 +1110,8 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
 
         /* Receiver is ready, let's read the dummy data */
         if (rx_word_length > OMAP_MCBSP_WORD_16)
-                word_msb = OMAP_MCBSP_READ(io_base, DRR2);
-        word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
+                word_msb = MCBSP_READ(mcbsp, DRR2);
+        word_lsb = MCBSP_READ(mcbsp, DRR1);
 
         return 0;
 }
@@ -824,7 +1121,6 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
 {
         struct omap_mcbsp *mcbsp;
         u32 clock_word = 0;
-        void __iomem *io_base;
         omap_mcbsp_word_length tx_word_length;
         omap_mcbsp_word_length rx_word_length;
         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
@@ -835,7 +1131,6 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
         }
 
         mcbsp = id_to_mcbsp_ptr(id);
-        io_base = mcbsp->io_base;
 
         tx_word_length = mcbsp->tx_word_length;
         rx_word_length = mcbsp->rx_word_length;
@@ -844,14 +1139,16 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
                 return -EINVAL;
 
         /* First we wait for the transmitter to be ready */
-        spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
+        spcr2 = MCBSP_READ(mcbsp, SPCR2);
         while (!(spcr2 & XRDY)) {
-                spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
+                spcr2 = MCBSP_READ(mcbsp, SPCR2);
                 if (attempts++ > 1000) {
                         /* We must reset the transmitter */
-                        OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
+                        MCBSP_WRITE(mcbsp, SPCR2,
+                                    MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
                         udelay(10);
-                        OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
+                        MCBSP_WRITE(mcbsp, SPCR2,
+                                    MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
                         udelay(10);
                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
                                 "ready\n", mcbsp->id);
@@ -861,18 +1158,20 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
 
         /* We first need to enable the bus clock */
         if (tx_word_length > OMAP_MCBSP_WORD_16)
-                OMAP_MCBSP_WRITE(io_base, DXR2, clock_word >> 16);
-        OMAP_MCBSP_WRITE(io_base, DXR1, clock_word & 0xffff);
+                MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16);
+        MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff);
 
         /* We wait for the receiver to be ready */
-        spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
+        spcr1 = MCBSP_READ(mcbsp, SPCR1);
         while (!(spcr1 & RRDY)) {
-                spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
+                spcr1 = MCBSP_READ(mcbsp, SPCR1);
                 if (attempts++ > 1000) {
                         /* We must reset the receiver */
-                        OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
+                        MCBSP_WRITE(mcbsp, SPCR1,
+                                    MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
                         udelay(10);
-                        OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
+                        MCBSP_WRITE(mcbsp, SPCR1,
+                                    MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
                         udelay(10);
                         dev_err(mcbsp->dev, "McBSP%d receiver not "
                                 "ready\n", mcbsp->id);
@@ -882,8 +1181,8 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
 
         /* Receiver is ready, there is something for us */
         if (rx_word_length > OMAP_MCBSP_WORD_16)
-                word_msb = OMAP_MCBSP_READ(io_base, DRR2);
-        word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
+                word_msb = MCBSP_READ(mcbsp, DRR2);
+        word_lsb = MCBSP_READ(mcbsp, DRR1);
 
         word[0] = (word_lsb | (word_msb << 16));
 
@@ -1097,7 +1396,7 @@ void omap_mcbsp_set_spi_mode(unsigned int id,
 }
 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
 
-#ifdef CONFIG_ARCH_OMAP34XX
+#ifdef CONFIG_ARCH_OMAP3
 #define max_thres(m)                    (mcbsp->pdata->buffer_size)
 #define valid_threshold(m, val)         ((val) <= max_thres(m))
 #define THRESHOLD_PROP_BUILDER(prop)                                    \
@@ -1145,9 +1444,7 @@ static ssize_t dma_op_mode_show(struct device *dev,
         ssize_t len = 0;
         const char * const *s;
 
-        spin_lock_irq(&mcbsp->lock);
         dma_op_mode = mcbsp->dma_op_mode;
-        spin_unlock_irq(&mcbsp->lock);
 
         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
                 if (dma_op_mode == i)
@@ -1190,6 +1487,64 @@ unlock:
 
 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
 
+static ssize_t st_taps_show(struct device *dev,
+                            struct device_attribute *attr, char *buf)
+{
+        struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
+        struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
+        ssize_t status = 0;
+        int i;
+
+        spin_lock_irq(&mcbsp->lock);
+        for (i = 0; i < st_data->nr_taps; i++)
+                status += sprintf(&buf[status], (i ? ", %d" : "%d"),
+                                  st_data->taps[i]);
+        if (i)
+                status += sprintf(&buf[status], "\n");
+        spin_unlock_irq(&mcbsp->lock);
+
+        return status;
+}
+
+static ssize_t st_taps_store(struct device *dev,
+                             struct device_attribute *attr,
+                             const char *buf, size_t size)
+{
+        struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
+        struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
+        int val, tmp, status, i = 0;
+
+        spin_lock_irq(&mcbsp->lock);
+        memset(st_data->taps, 0, sizeof(st_data->taps));
+        st_data->nr_taps = 0;
+
+        do {
+                status = sscanf(buf, "%d%n", &val, &tmp);
+                if (status < 0 || status == 0) {
+                        size = -EINVAL;
+                        goto out;
+                }
+                if (val < -32768 || val > 32767) {
+                        size = -EINVAL;
+                        goto out;
+                }
+                st_data->taps[i++] = val;
+                buf += tmp;
+                if (*buf != ',')
+                        break;
+                buf++;
+        } while (1);
+
+        st_data->nr_taps = i;
+
+out:
+        spin_unlock_irq(&mcbsp->lock);
+
+        return size;
+}
+
+static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
+
 static const struct attribute *additional_attrs[] = {
         &dev_attr_max_tx_thres.attr,
         &dev_attr_max_rx_thres.attr,
@@ -1211,6 +1566,60 @@ static inline void __devexit omap_additional_remove(struct device *dev)
         sysfs_remove_group(&dev->kobj, &additional_attr_group);
 }
 
+static const struct attribute *sidetone_attrs[] = {
+        &dev_attr_st_taps.attr,
+        NULL,
+};
+
+static const struct attribute_group sidetone_attr_group = {
+        .attrs = (struct attribute **)sidetone_attrs,
+};
+
+int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
+{
+        struct omap_mcbsp_platform_data *pdata = mcbsp->pdata;
+        struct omap_mcbsp_st_data *st_data;
+        int err;
+
+        st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
+        if (!st_data) {
+                err = -ENOMEM;
+                goto err1;
+        }
+
+        st_data->io_base_st = ioremap(pdata->phys_base_st, SZ_4K);
+        if (!st_data->io_base_st) {
+                err = -ENOMEM;
+                goto err2;
+        }
+
+        err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
+        if (err)
+                goto err3;
+
+        mcbsp->st_data = st_data;
+        return 0;
+
+err3:
+        iounmap(st_data->io_base_st);
+err2:
+        kfree(st_data);
+err1:
+        return err;
+
+}
+
+static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
+{
+        struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
+
+        if (st_data) {
+                sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
+                iounmap(st_data->io_base_st);
+                kfree(st_data);
+        }
+}
+
 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
 {
         mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
@@ -1224,6 +1633,12 @@ static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
                 if (omap_additional_add(mcbsp->dev))
                         dev_warn(mcbsp->dev,
                                 "Unable to create additional controls\n");
+
+                if (mcbsp->id == 2 || mcbsp->id == 3)
+                        if (omap_st_add(mcbsp))
+                                dev_warn(mcbsp->dev,
+                                 "Unable to create sidetone controls\n");
+
         } else {
                 mcbsp->max_tx_thres = -EINVAL;
                 mcbsp->max_rx_thres = -EINVAL;
@@ -1232,13 +1647,17 @@ static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
 
 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
 {
-        if (cpu_is_omap34xx())
+        if (cpu_is_omap34xx()) {
                 omap_additional_remove(mcbsp->dev);
+
+                if (mcbsp->id == 2 || mcbsp->id == 3)
+                        omap_st_remove(mcbsp);
+        }
 }
 #else
 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
-#endif /* CONFIG_ARCH_OMAP34XX */
+#endif /* CONFIG_ARCH_OMAP3 */
 
 /*
  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
index 8d329fb20740..06703635ace1 100644
--- a/arch/arm/plat-omap/mux.c
+++ b/arch/arm/plat-omap/mux.c
@@ -28,7 +28,7 @@
 #include <linux/io.h>
 #include <asm/system.h>
 #include <linux/spinlock.h>
-#include <mach/mux.h>
+#include <plat/mux.h>
 
 #ifdef CONFIG_OMAP_MUX
 
@@ -54,8 +54,12 @@ int __init_or_module omap_cfg_reg(const unsigned long index)
 {
         struct pin_config *reg;
 
-        if (cpu_is_omap44xx())
-                return 0;
+        if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+                printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n",
+                                index);
+                WARN_ON(1);
+                return -EINVAL;
+        }
 
         if (mux_cfg == NULL) {
                 printk(KERN_ERR "Pin mux table not initialized\n");
diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c
index e98f0a2a6c26..186bca82cfab 100644
--- a/arch/arm/plat-omap/omap-pm-noop.c
+++ b/arch/arm/plat-omap/omap-pm-noop.c
@@ -22,9 +22,9 @@
 #include <linux/device.h>
 
 /* Interface documentation is in mach/omap-pm.h */
-#include <mach/omap-pm.h>
+#include <plat/omap-pm.h>
 
-#include <mach/powerdomain.h>
+#include <plat/powerdomain.h>
 
 struct omap_opp *dsp_opps;
 struct omap_opp *mpu_opps;
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 2c409fc6dd21..0f5197479513 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -79,43 +79,21 @@
 
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
+#include <linux/slab.h>
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include <mach/omap_device.h>
-#include <mach/omap_hwmod.h>
+#include <plat/omap_device.h>
+#include <plat/omap_hwmod.h>
 
 /* These parameters are passed to _omap_device_{de,}activate() */
 #define USE_WAKEUP_LAT                  0
 #define IGNORE_WAKEUP_LAT               1
 
-/* XXX this should be moved into a separate file */
-#if defined(CONFIG_ARCH_OMAP2420)
-# define OMAP_32KSYNCT_BASE             0x48004000
-#elif defined(CONFIG_ARCH_OMAP2430)
-# define OMAP_32KSYNCT_BASE             0x49020000
-#elif defined(CONFIG_ARCH_OMAP3430)
-# define OMAP_32KSYNCT_BASE             0x48320000
-#else
-# error Unknown OMAP device
-#endif
 
-/* Private functions */
-
-/**
- * _read_32ksynct - read the OMAP 32K sync timer
- *
- * Returns the current value of the 32KiHz synchronization counter.
- * XXX this should be generalized to simply read the system clocksource.
- * XXX this should be moved to a separate synctimer32k.c file
- */
-static u32 _read_32ksynct(void)
-{
-        if (!cpu_class_is_omap2())
-                BUG();
+#define OMAP_DEVICE_MAGIC 0xf00dcafe
 
-        return __raw_readl(OMAP2_IO_ADDRESS(OMAP_32KSYNCT_BASE + 0x010));
-}
+/* Private functions */
 
 /**
  * _omap_device_activate - increase device readiness
@@ -133,13 +111,13 @@ static u32 _read_32ksynct(void)
  */
 static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
 {
-        u32 a, b;
+        struct timespec a, b, c;
 
         pr_debug("omap_device: %s: activating\n", od->pdev.name);
 
         while (od->pm_lat_level > 0) {
                 struct omap_device_pm_latency *odpl;
-                int act_lat = 0;
+                unsigned long long act_lat = 0;
 
                 od->pm_lat_level--;
 
@@ -149,22 +127,36 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
                     (od->dev_wakeup_lat <= od->_dev_wakeup_lat_limit))
                         break;
 
-                a = _read_32ksynct();
+                read_persistent_clock(&a);
 
                 /* XXX check return code */
                 odpl->activate_func(od);
 
-                b = _read_32ksynct();
+                read_persistent_clock(&b);
 
-                act_lat = (b - a) >> 15; /* 32KiHz cycles to microseconds */
+                c = timespec_sub(b, a);
+                act_lat = timespec_to_ns(&c);
 
                 pr_debug("omap_device: %s: pm_lat %d: activate: elapsed time "
-                         "%d usec\n", od->pdev.name, od->pm_lat_level, act_lat);
-
-                WARN(act_lat > odpl->activate_lat, "omap_device: %s.%d: "
-                     "activate step %d took longer than expected (%d > %d)\n",
-                     od->pdev.name, od->pdev.id, od->pm_lat_level,
-                     act_lat, odpl->activate_lat);
+                         "%llu nsec\n", od->pdev.name, od->pm_lat_level,
+                         act_lat);
+
+                if (act_lat > odpl->activate_lat) {
+                        odpl->activate_lat_worst = act_lat;
+                        if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
+                                odpl->activate_lat = act_lat;
+                                pr_warning("omap_device: %s.%d: new worst case "
+                                           "activate latency %d: %llu\n",
+                                           od->pdev.name, od->pdev.id,
+                                           od->pm_lat_level, act_lat);
+                        } else
+                                pr_warning("omap_device: %s.%d: activate "
+                                           "latency %d higher than exptected. "
+                                           "(%llu > %d)\n",
+                                           od->pdev.name, od->pdev.id,
+                                           od->pm_lat_level, act_lat,
+                                           odpl->activate_lat);
+                }
 
                 od->dev_wakeup_lat -= odpl->activate_lat;
         }
@@ -188,13 +180,13 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
  */
 static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
 {
-        u32 a, b;
+        struct timespec a, b, c;
 
         pr_debug("omap_device: %s: deactivating\n", od->pdev.name);
 
         while (od->pm_lat_level < od->pm_lats_cnt) {
                 struct omap_device_pm_latency *odpl;
-                int deact_lat = 0;
+                unsigned long long deact_lat = 0;
 
                 odpl = od->pm_lats + od->pm_lat_level;
 
@@ -203,23 +195,37 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
                      od->_dev_wakeup_lat_limit))
                         break;
 
-                a = _read_32ksynct();
+                read_persistent_clock(&a);
 
                 /* XXX check return code */
                 odpl->deactivate_func(od);
 
-                b = _read_32ksynct();
+                read_persistent_clock(&b);
 
-                deact_lat = (b - a) >> 15; /* 32KiHz cycles to microseconds */
+                c = timespec_sub(b, a);
+                deact_lat = timespec_to_ns(&c);
 
                 pr_debug("omap_device: %s: pm_lat %d: deactivate: elapsed time "
-                         "%d usec\n", od->pdev.name, od->pm_lat_level,
+                         "%llu nsec\n", od->pdev.name, od->pm_lat_level,
                          deact_lat);
 
-                WARN(deact_lat > odpl->deactivate_lat, "omap_device: %s.%d: "
-                     "deactivate step %d took longer than expected (%d > %d)\n",
-                     od->pdev.name, od->pdev.id, od->pm_lat_level,
-                     deact_lat, odpl->deactivate_lat);
+                if (deact_lat > odpl->deactivate_lat) {
+                        odpl->deactivate_lat_worst = deact_lat;
+                        if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
+                                odpl->deactivate_lat = deact_lat;
+                                pr_warning("omap_device: %s.%d: new worst case "
+                                           "deactivate latency %d: %llu\n",
+                                           od->pdev.name, od->pdev.id,
+                                           od->pm_lat_level, deact_lat);
+                        } else
+                                pr_warning("omap_device: %s.%d: deactivate "
+                                           "latency %d higher than exptected. "
+                                           "(%llu > %d)\n",
+                                           od->pdev.name, od->pdev.id,
+                                           od->pm_lat_level, deact_lat,
+                                           odpl->deactivate_lat);
+                }
+
 
                 od->dev_wakeup_lat += odpl->activate_lat;
 
@@ -302,6 +308,7 @@ int omap_device_fill_resources(struct omap_device *od, struct resource *res)
  * @pdata_len: amount of memory pointed to by @pdata
  * @pm_lats: pointer to a omap_device_pm_latency array for this device
  * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
+ * @is_early_device: should the device be registered as an early device or not
  *
  * Convenience function for building and registering a single
  * omap_device record, which in turn builds and registers a
@@ -313,7 +320,7 @@ struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
                                       struct omap_hwmod *oh, void *pdata,
                                       int pdata_len,
                                       struct omap_device_pm_latency *pm_lats,
-                                      int pm_lats_cnt)
+                                      int pm_lats_cnt, int is_early_device)
 {
         struct omap_hwmod *ohs[] = { oh };
 
@@ -321,7 +328,8 @@ struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
                 return ERR_PTR(-EINVAL);
 
         return omap_device_build_ss(pdev_name, pdev_id, ohs, 1, pdata,
-                                    pdata_len, pm_lats, pm_lats_cnt);
+                                    pdata_len, pm_lats, pm_lats_cnt,
+                                    is_early_device);
 }
 
 /**
@@ -333,6 +341,7 @@ struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
  * @pdata_len: amount of memory pointed to by @pdata
  * @pm_lats: pointer to a omap_device_pm_latency array for this device
  * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
+ * @is_early_device: should the device be registered as an early device or not
  *
  * Convenience function for building and registering an omap_device
  * subsystem record.  Subsystem records consist of multiple
@@ -344,7 +353,7 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
                                          struct omap_hwmod **ohs, int oh_cnt,
                                          void *pdata, int pdata_len,
                                          struct omap_device_pm_latency *pm_lats,
-                                         int pm_lats_cnt)
+                                         int pm_lats_cnt, int is_early_device)
 {
         int ret = -ENOMEM;
         struct omap_device *od;
@@ -400,7 +409,13 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
         od->pm_lats = pm_lats;
         od->pm_lats_cnt = pm_lats_cnt;
 
-        ret = omap_device_register(od);
+        od->magic = OMAP_DEVICE_MAGIC;
+
+        if (is_early_device)
+                ret = omap_early_device_register(od);
+        else
+                ret = omap_device_register(od);
+
         if (ret)
                 goto odbs_exit4;
 
@@ -421,6 +436,24 @@ odbs_exit1:
 }
 
 /**
+ * omap_early_device_register - register an omap_device as an early platform
+ * device.
+ * @od: struct omap_device * to register
+ *
+ * Register the omap_device structure.  This currently just calls
+ * platform_early_add_device() on the underlying platform_device.
+ * Returns 0 by default.
+ */
+int omap_early_device_register(struct omap_device *od)
+{
+        struct platform_device *devices[1];
+
+        devices[0] = &(od->pdev);
+        early_platform_add_devices(devices, 1);
+        return 0;
+}
+
+/**
  * omap_device_register - register an omap_device with one omap_hwmod
  * @od: struct omap_device * to register
  *
@@ -459,8 +492,8 @@ int omap_device_enable(struct platform_device *pdev)
         od = _find_by_pdev(pdev);
 
         if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
-                WARN(1, "omap_device: %s.%d: omap_device_enable() called from "
-                     "invalid state\n", od->pdev.name, od->pdev.id);
+                WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n",
+                     od->pdev.name, od->pdev.id, __func__, od->_state);
                 return -EINVAL;
         }
 
@@ -471,7 +504,7 @@ int omap_device_enable(struct platform_device *pdev)
         ret = _omap_device_activate(od, IGNORE_WAKEUP_LAT);
 
         od->dev_wakeup_lat = 0;
-        od->_dev_wakeup_lat_limit = INT_MAX;
+        od->_dev_wakeup_lat_limit = UINT_MAX;
         od->_state = OMAP_DEVICE_STATE_ENABLED;
 
         return ret;
@@ -498,8 +531,8 @@ int omap_device_idle(struct platform_device *pdev)
         od = _find_by_pdev(pdev);
 
         if (od->_state != OMAP_DEVICE_STATE_ENABLED) {
-                WARN(1, "omap_device: %s.%d: omap_device_idle() called from "
-                     "invalid state\n", od->pdev.name, od->pdev.id);
+                WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n",
+                     od->pdev.name, od->pdev.id, __func__, od->_state);
                 return -EINVAL;
         }
 
@@ -531,8 +564,8 @@ int omap_device_shutdown(struct platform_device *pdev)
 
         if (od->_state != OMAP_DEVICE_STATE_ENABLED &&
             od->_state != OMAP_DEVICE_STATE_IDLE) {
-                WARN(1, "omap_device: %s.%d: omap_device_shutdown() called "
-                     "from invalid state\n", od->pdev.name, od->pdev.id);
+                WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n",
+                     od->pdev.name, od->pdev.id, __func__, od->_state);
                 return -EINVAL;
         }
 
@@ -586,6 +619,18 @@ int omap_device_align_pm_lat(struct platform_device *pdev,
 }
 
 /**
+ * omap_device_is_valid - Check if pointer is a valid omap_device
+ * @od: struct omap_device *
+ *
+ * Return whether struct omap_device pointer @od points to a valid
+ * omap_device.
+ */
+bool omap_device_is_valid(struct omap_device *od)
+{
+        return (od && od->magic == OMAP_DEVICE_MAGIC);
+}
+
+/**
  * omap_device_get_pwrdm - return the powerdomain * associated with @od
  * @od: struct omap_device *
  *
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 75d1f26e5b17..51f4dfb82e2b 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -25,11 +25,12 @@
 
 #include <asm/mach/map.h>
 
-#include <mach/sram.h>
-#include <mach/board.h>
-#include <mach/cpu.h>
+#include <plat/sram.h>
+#include <plat/board.h>
+#include <plat/cpu.h>
+#include <plat/vram.h>
 
-#include <mach/control.h>
+#include <plat/control.h>
 
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
 # include "../mach-omap2/prm.h"
@@ -41,31 +42,33 @@
 #define OMAP1_SRAM_VA           VMALLOC_END
 #define OMAP2_SRAM_PA           0x40200000
 #define OMAP2_SRAM_PUB_PA       0x4020f800
-#define OMAP2_SRAM_VA           0xe3000000
+#define OMAP2_SRAM_VA           0xfe400000
 #define OMAP2_SRAM_PUB_VA       (OMAP2_SRAM_VA + 0x800)
 #define OMAP3_SRAM_PA           0x40200000
-#define OMAP3_SRAM_VA           0xe3000000
+#define OMAP3_SRAM_VA           0xfe400000
 #define OMAP3_SRAM_PUB_PA       0x40208000
 #define OMAP3_SRAM_PUB_VA       (OMAP3_SRAM_VA + 0x8000)
-#define OMAP4_SRAM_PA           0x40200000              /*0x402f0000*/
-#define OMAP4_SRAM_VA           0xd7000000              /*0xd70f0000*/
+#define OMAP4_SRAM_PA           0x40300000
+#define OMAP4_SRAM_VA           0xfe400000
+#define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
+#define OMAP4_SRAM_PUB_VA       (OMAP4_SRAM_VA + 0x4000)
 
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
 #define SRAM_BOOTLOADER_SZ      0x00
 #else
 #define SRAM_BOOTLOADER_SZ      0x80
 #endif
 
-#define OMAP24XX_VA_REQINFOPERM0        OMAP2_IO_ADDRESS(0x68005048)
-#define OMAP24XX_VA_READPERM0           OMAP2_IO_ADDRESS(0x68005050)
-#define OMAP24XX_VA_WRITEPERM0          OMAP2_IO_ADDRESS(0x68005058)
+#define OMAP24XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68005048)
+#define OMAP24XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68005050)
+#define OMAP24XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68005058)
 
-#define OMAP34XX_VA_REQINFOPERM0        OMAP2_IO_ADDRESS(0x68012848)
-#define OMAP34XX_VA_READPERM0           OMAP2_IO_ADDRESS(0x68012850)
-#define OMAP34XX_VA_WRITEPERM0          OMAP2_IO_ADDRESS(0x68012858)
-#define OMAP34XX_VA_ADDR_MATCH2         OMAP2_IO_ADDRESS(0x68012880)
-#define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_IO_ADDRESS(0x6C000048)
-#define OMAP34XX_VA_CONTROL_STAT        OMAP2_IO_ADDRESS(0x480022F0)
+#define OMAP34XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68012848)
+#define OMAP34XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68012850)
+#define OMAP34XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68012858)
+#define OMAP34XX_VA_ADDR_MATCH2         OMAP2_L3_IO_ADDRESS(0x68012880)
+#define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_L3_IO_ADDRESS(0x6C000048)
+#define OMAP34XX_VA_CONTROL_STAT        OMAP2_L4_IO_ADDRESS(0x480022F0)
 
 #define GP_DEVICE               0x300
 
@@ -139,6 +142,10 @@ void __init omap_detect_sram(void)
                                 } else {
                                         omap_sram_size = 0x8000; /* 32K */
                                 }
+                        } else if (cpu_is_omap44xx()) {
+                                omap_sram_base = OMAP4_SRAM_PUB_VA;
+                                omap_sram_start = OMAP4_SRAM_PUB_PA;
+                                omap_sram_size = 0xa000; /* 40K */
                         } else {
                                 omap_sram_base = OMAP2_SRAM_PUB_VA;
                                 omap_sram_start = OMAP2_SRAM_PUB_PA;
@@ -152,7 +159,7 @@ void __init omap_detect_sram(void)
                         } else if (cpu_is_omap44xx()) {
                                 omap_sram_base = OMAP4_SRAM_VA;
                                 omap_sram_start = OMAP4_SRAM_PA;
-                                omap_sram_size = 0x8000; /* 32K */
+                                omap_sram_size = 0xe000; /* 56K */
                         } else {
                                 omap_sram_base = OMAP2_SRAM_VA;
                                 omap_sram_start = OMAP2_SRAM_PA;
@@ -185,6 +192,13 @@ void __init omap_detect_sram(void)
                                        omap_sram_start + SRAM_BOOTLOADER_SZ,
                                        omap_sram_size - SRAM_BOOTLOADER_SZ);
         omap_sram_size -= reserved;
+
+        reserved = omap_vram_reserve_sram(omap_sram_start, omap_sram_base,
+                        omap_sram_size,
+                        omap_sram_start + SRAM_BOOTLOADER_SZ,
+                        omap_sram_size - SRAM_BOOTLOADER_SZ);
+        omap_sram_size -= reserved;
+
         omap_sram_ceil = omap_sram_base + omap_sram_size;
 }
 
@@ -396,22 +410,24 @@ u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
                         sdrc_actim_ctrl_b_1, sdrc_mr_1);
 }
 
-/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
-void restore_sram_functions(void)
+#ifdef CONFIG_PM
+void omap3_sram_restore_context(void)
 {
         omap_sram_ceil = omap_sram_base + omap_sram_size;
 
         _omap3_sram_configure_core_dpll =
                 omap_sram_push(omap3_sram_configure_core_dpll,
                                omap3_sram_configure_core_dpll_sz);
+        omap_push_sram_idle();
 }
+#endif /* CONFIG_PM */
 
 int __init omap34xx_sram_init(void)
 {
         _omap3_sram_configure_core_dpll =
                 omap_sram_push(omap3_sram_configure_core_dpll,
                                omap3_sram_configure_core_dpll_sz);
-
+        omap_push_sram_idle();
         return 0;
 }
 #else
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index 509f2ed99e21..d3bf17cd36f3 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -33,10 +33,10 @@
 #include <asm/system.h>
 #include <mach/hardware.h>
 
-#include <mach/control.h>
-#include <mach/mux.h>
-#include <mach/usb.h>
-#include <mach/board.h>
+#include <plat/control.h>
+#include <plat/mux.h>
+#include <plat/usb.h>
+#include <plat/board.h>
 
 #ifdef CONFIG_ARCH_OMAP1
 
@@ -137,7 +137,13 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
         if (is_device) {
                 if (cpu_is_omap24xx())
                         omap_cfg_reg(J20_24XX_USB0_PUEN);
-                else
+                else if (cpu_is_omap7xx()) {
+                        omap_cfg_reg(AA17_7XX_USB_DM);
+                        omap_cfg_reg(W16_7XX_USB_PU_EN);
+                        omap_cfg_reg(W17_7XX_USB_VBUSI);
+                        omap_cfg_reg(W18_7XX_USB_DMCK_OUT);
+                        omap_cfg_reg(W19_7XX_USB_DCRST);
+                } else
                         omap_cfg_reg(W4_USB_PUEN);
         }
 
@@ -159,11 +165,14 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
                  *  - OTG support on this port not yet written
                  */
 
-                l = omap_readl(USB_TRANSCEIVER_CTRL);
-                l &= ~(7 << 4);
-                if (!is_device)
-                        l |= (3 << 1);
-                omap_writel(l, USB_TRANSCEIVER_CTRL);
+                /* Don't do this for omap7xx -- it causes USB to not work correctly */
+                if (!cpu_is_omap7xx()) {
+                        l = omap_readl(USB_TRANSCEIVER_CTRL);
+                        l &= ~(7 << 4);
+                        if (!is_device)
+                                l |= (3 << 1);
+                        omap_writel(l, USB_TRANSCEIVER_CTRL);
+                }
 
                 return 3 << 16;
         }
@@ -603,7 +612,12 @@ omap_otg_init(struct omap_usb_config *config)
         if (config->otg || config->register_dev) {
                 syscon &= ~DEV_IDLE_EN;
                 udc_device.dev.platform_data = config;
-                /* FIXME patch IRQ numbers for omap730 */
+                /* IRQ numbers for omap7xx */
+                if(cpu_is_omap7xx()) {
+                        udc_resources[1].start = INT_7XX_USB_GENI;
+                        udc_resources[2].start = INT_7XX_USB_NON_ISO;
+                        udc_resources[3].start = INT_7XX_USB_ISO;
+                }
                 status = platform_device_register(&udc_device);
                 if (status)
                         pr_debug("can't register UDC device, %d\n", status);
@@ -614,8 +628,8 @@ omap_otg_init(struct omap_usb_config *config)
         if (config->otg || config->register_host) {
                 syscon &= ~HST_IDLE_EN;
                 ohci_device.dev.platform_data = config;
-                if (cpu_is_omap730())
-                        ohci_resources[1].start = INT_730_USB_HHC_1;
+                if (cpu_is_omap7xx())
+                        ohci_resources[1].start = INT_7XX_USB_HHC_1;
                 status = platform_device_register(&ohci_device);
                 if (status)
                         pr_debug("can't register OHCI device, %d\n", status);
@@ -626,8 +640,8 @@ omap_otg_init(struct omap_usb_config *config)
         if (config->otg) {
                 syscon &= ~OTG_IDLE_EN;
                 otg_device.dev.platform_data = config;
-                if (cpu_is_omap730())
-                        otg_resources[1].start = INT_730_USB_OTG;
+                if (cpu_is_omap7xx())
+                        otg_resources[1].start = INT_7XX_USB_OTG;
                 status = platform_device_register(&otg_device);
                 if (status)
                         pr_debug("can't register OTG device, %d\n", status);
@@ -731,7 +745,7 @@ static inline void omap_1510_usb_init(struct omap_usb_config *config) {}
 
 void __init omap_usb_init(struct omap_usb_config *pdata)
 {
-        if (cpu_is_omap730() || cpu_is_omap16xx() || cpu_is_omap24xx())
+        if (cpu_is_omap7xx() || cpu_is_omap16xx() || cpu_is_omap24xx())
                 omap_otg_init(pdata);
         else if (cpu_is_omap15xx())
                 omap_1510_usb_init(pdata);