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-rw-r--r--arch/arm/plat-omap/gpio.c906
1 files changed, 524 insertions, 382 deletions
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 7c345b757df1..45a225d09125 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -31,7 +31,7 @@
31/* 31/*
32 * OMAP1510 GPIO registers 32 * OMAP1510 GPIO registers
33 */ 33 */
34#define OMAP1510_GPIO_BASE OMAP1_IO_ADDRESS(0xfffce000) 34#define OMAP1510_GPIO_BASE 0xfffce000
35#define OMAP1510_GPIO_DATA_INPUT 0x00 35#define OMAP1510_GPIO_DATA_INPUT 0x00
36#define OMAP1510_GPIO_DATA_OUTPUT 0x04 36#define OMAP1510_GPIO_DATA_OUTPUT 0x04
37#define OMAP1510_GPIO_DIR_CONTROL 0x08 37#define OMAP1510_GPIO_DIR_CONTROL 0x08
@@ -45,10 +45,10 @@
45/* 45/*
46 * OMAP1610 specific GPIO registers 46 * OMAP1610 specific GPIO registers
47 */ 47 */
48#define OMAP1610_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbe400) 48#define OMAP1610_GPIO1_BASE 0xfffbe400
49#define OMAP1610_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbec00) 49#define OMAP1610_GPIO2_BASE 0xfffbec00
50#define OMAP1610_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbb400) 50#define OMAP1610_GPIO3_BASE 0xfffbb400
51#define OMAP1610_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbbc00) 51#define OMAP1610_GPIO4_BASE 0xfffbbc00
52#define OMAP1610_GPIO_REVISION 0x0000 52#define OMAP1610_GPIO_REVISION 0x0000
53#define OMAP1610_GPIO_SYSCONFIG 0x0010 53#define OMAP1610_GPIO_SYSCONFIG 0x0010
54#define OMAP1610_GPIO_SYSSTATUS 0x0014 54#define OMAP1610_GPIO_SYSSTATUS 0x0014
@@ -68,52 +68,36 @@
68#define OMAP1610_GPIO_SET_DATAOUT 0x00f0 68#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
69 69
70/* 70/*
71 * OMAP730 specific GPIO registers 71 * OMAP7XX specific GPIO registers
72 */ 72 */
73#define OMAP730_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000) 73#define OMAP7XX_GPIO1_BASE 0xfffbc000
74#define OMAP730_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800) 74#define OMAP7XX_GPIO2_BASE 0xfffbc800
75#define OMAP730_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000) 75#define OMAP7XX_GPIO3_BASE 0xfffbd000
76#define OMAP730_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800) 76#define OMAP7XX_GPIO4_BASE 0xfffbd800
77#define OMAP730_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000) 77#define OMAP7XX_GPIO5_BASE 0xfffbe000
78#define OMAP730_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800) 78#define OMAP7XX_GPIO6_BASE 0xfffbe800
79#define OMAP730_GPIO_DATA_INPUT 0x00 79#define OMAP7XX_GPIO_DATA_INPUT 0x00
80#define OMAP730_GPIO_DATA_OUTPUT 0x04 80#define OMAP7XX_GPIO_DATA_OUTPUT 0x04
81#define OMAP730_GPIO_DIR_CONTROL 0x08 81#define OMAP7XX_GPIO_DIR_CONTROL 0x08
82#define OMAP730_GPIO_INT_CONTROL 0x0c 82#define OMAP7XX_GPIO_INT_CONTROL 0x0c
83#define OMAP730_GPIO_INT_MASK 0x10 83#define OMAP7XX_GPIO_INT_MASK 0x10
84#define OMAP730_GPIO_INT_STATUS 0x14 84#define OMAP7XX_GPIO_INT_STATUS 0x14
85 85
86/* 86#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
87 * OMAP850 specific GPIO registers
88 */
89#define OMAP850_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000)
90#define OMAP850_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800)
91#define OMAP850_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000)
92#define OMAP850_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800)
93#define OMAP850_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000)
94#define OMAP850_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800)
95#define OMAP850_GPIO_DATA_INPUT 0x00
96#define OMAP850_GPIO_DATA_OUTPUT 0x04
97#define OMAP850_GPIO_DIR_CONTROL 0x08
98#define OMAP850_GPIO_INT_CONTROL 0x0c
99#define OMAP850_GPIO_INT_MASK 0x10
100#define OMAP850_GPIO_INT_STATUS 0x14
101
102#define OMAP1_MPUIO_VBASE OMAP1_IO_ADDRESS(OMAP1_MPUIO_BASE)
103 87
104/* 88/*
105 * omap24xx specific GPIO registers 89 * omap24xx specific GPIO registers
106 */ 90 */
107#define OMAP242X_GPIO1_BASE OMAP2_IO_ADDRESS(0x48018000) 91#define OMAP242X_GPIO1_BASE 0x48018000
108#define OMAP242X_GPIO2_BASE OMAP2_IO_ADDRESS(0x4801a000) 92#define OMAP242X_GPIO2_BASE 0x4801a000
109#define OMAP242X_GPIO3_BASE OMAP2_IO_ADDRESS(0x4801c000) 93#define OMAP242X_GPIO3_BASE 0x4801c000
110#define OMAP242X_GPIO4_BASE OMAP2_IO_ADDRESS(0x4801e000) 94#define OMAP242X_GPIO4_BASE 0x4801e000
111 95
112#define OMAP243X_GPIO1_BASE OMAP2_IO_ADDRESS(0x4900C000) 96#define OMAP243X_GPIO1_BASE 0x4900C000
113#define OMAP243X_GPIO2_BASE OMAP2_IO_ADDRESS(0x4900E000) 97#define OMAP243X_GPIO2_BASE 0x4900E000
114#define OMAP243X_GPIO3_BASE OMAP2_IO_ADDRESS(0x49010000) 98#define OMAP243X_GPIO3_BASE 0x49010000
115#define OMAP243X_GPIO4_BASE OMAP2_IO_ADDRESS(0x49012000) 99#define OMAP243X_GPIO4_BASE 0x49012000
116#define OMAP243X_GPIO5_BASE OMAP2_IO_ADDRESS(0x480B6000) 100#define OMAP243X_GPIO5_BASE 0x480B6000
117 101
118#define OMAP24XX_GPIO_REVISION 0x0000 102#define OMAP24XX_GPIO_REVISION 0x0000
119#define OMAP24XX_GPIO_SYSCONFIG 0x0010 103#define OMAP24XX_GPIO_SYSCONFIG 0x0010
@@ -170,35 +154,34 @@
170 * omap34xx specific GPIO registers 154 * omap34xx specific GPIO registers
171 */ 155 */
172 156
173#define OMAP34XX_GPIO1_BASE OMAP2_IO_ADDRESS(0x48310000) 157#define OMAP34XX_GPIO1_BASE 0x48310000
174#define OMAP34XX_GPIO2_BASE OMAP2_IO_ADDRESS(0x49050000) 158#define OMAP34XX_GPIO2_BASE 0x49050000
175#define OMAP34XX_GPIO3_BASE OMAP2_IO_ADDRESS(0x49052000) 159#define OMAP34XX_GPIO3_BASE 0x49052000
176#define OMAP34XX_GPIO4_BASE OMAP2_IO_ADDRESS(0x49054000) 160#define OMAP34XX_GPIO4_BASE 0x49054000
177#define OMAP34XX_GPIO5_BASE OMAP2_IO_ADDRESS(0x49056000) 161#define OMAP34XX_GPIO5_BASE 0x49056000
178#define OMAP34XX_GPIO6_BASE OMAP2_IO_ADDRESS(0x49058000) 162#define OMAP34XX_GPIO6_BASE 0x49058000
179 163
180/* 164/*
181 * OMAP44XX specific GPIO registers 165 * OMAP44XX specific GPIO registers
182 */ 166 */
183#define OMAP44XX_GPIO1_BASE OMAP2_IO_ADDRESS(0x4a310000) 167#define OMAP44XX_GPIO1_BASE 0x4a310000
184#define OMAP44XX_GPIO2_BASE OMAP2_IO_ADDRESS(0x48055000) 168#define OMAP44XX_GPIO2_BASE 0x48055000
185#define OMAP44XX_GPIO3_BASE OMAP2_IO_ADDRESS(0x48057000) 169#define OMAP44XX_GPIO3_BASE 0x48057000
186#define OMAP44XX_GPIO4_BASE OMAP2_IO_ADDRESS(0x48059000) 170#define OMAP44XX_GPIO4_BASE 0x48059000
187#define OMAP44XX_GPIO5_BASE OMAP2_IO_ADDRESS(0x4805B000) 171#define OMAP44XX_GPIO5_BASE 0x4805B000
188#define OMAP44XX_GPIO6_BASE OMAP2_IO_ADDRESS(0x4805D000) 172#define OMAP44XX_GPIO6_BASE 0x4805D000
189 173
190struct gpio_bank { 174struct gpio_bank {
175 unsigned long pbase;
191 void __iomem *base; 176 void __iomem *base;
192 u16 irq; 177 u16 irq;
193 u16 virtual_irq_start; 178 u16 virtual_irq_start;
194 int method; 179 int method;
195#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \ 180#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
196 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
197 u32 suspend_wakeup; 181 u32 suspend_wakeup;
198 u32 saved_wakeup; 182 u32 saved_wakeup;
199#endif 183#endif
200#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 184#ifdef CONFIG_ARCH_OMAP2PLUS
201 defined(CONFIG_ARCH_OMAP4)
202 u32 non_wakeup_gpios; 185 u32 non_wakeup_gpios;
203 u32 enabled_non_wakeup_gpios; 186 u32 enabled_non_wakeup_gpios;
204 187
@@ -207,107 +190,142 @@ struct gpio_bank {
207 u32 saved_risingdetect; 190 u32 saved_risingdetect;
208#endif 191#endif
209 u32 level_mask; 192 u32 level_mask;
193 u32 toggle_mask;
210 spinlock_t lock; 194 spinlock_t lock;
211 struct gpio_chip chip; 195 struct gpio_chip chip;
212 struct clk *dbck; 196 struct clk *dbck;
197 u32 mod_usage;
213}; 198};
214 199
215#define METHOD_MPUIO 0 200#define METHOD_MPUIO 0
216#define METHOD_GPIO_1510 1 201#define METHOD_GPIO_1510 1
217#define METHOD_GPIO_1610 2 202#define METHOD_GPIO_1610 2
218#define METHOD_GPIO_730 3 203#define METHOD_GPIO_7XX 3
219#define METHOD_GPIO_850 4
220#define METHOD_GPIO_24XX 5 204#define METHOD_GPIO_24XX 5
205#define METHOD_GPIO_44XX 6
221 206
222#ifdef CONFIG_ARCH_OMAP16XX 207#ifdef CONFIG_ARCH_OMAP16XX
223static struct gpio_bank gpio_bank_1610[5] = { 208static struct gpio_bank gpio_bank_1610[5] = {
224 { OMAP1_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO}, 209 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
225 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 }, 210 METHOD_MPUIO },
226 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 }, 211 { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
227 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 }, 212 METHOD_GPIO_1610 },
228 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 }, 213 { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16,
214 METHOD_GPIO_1610 },
215 { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32,
216 METHOD_GPIO_1610 },
217 { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48,
218 METHOD_GPIO_1610 },
229}; 219};
230#endif 220#endif
231 221
232#ifdef CONFIG_ARCH_OMAP15XX 222#ifdef CONFIG_ARCH_OMAP15XX
233static struct gpio_bank gpio_bank_1510[2] = { 223static struct gpio_bank gpio_bank_1510[2] = {
234 { OMAP1_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, 224 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
235 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 } 225 METHOD_MPUIO },
236}; 226 { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
237#endif 227 METHOD_GPIO_1510 }
238
239#ifdef CONFIG_ARCH_OMAP730
240static struct gpio_bank gpio_bank_730[7] = {
241 { OMAP1_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
242 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
243 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
244 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
245 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
246 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
247 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
248}; 228};
249#endif 229#endif
250 230
251#ifdef CONFIG_ARCH_OMAP850 231#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
252static struct gpio_bank gpio_bank_850[7] = { 232static struct gpio_bank gpio_bank_7xx[7] = {
253 { OMAP1_MPUIO_VBASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, 233 { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE,
254 { OMAP850_GPIO1_BASE, INT_850_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_850 }, 234 METHOD_MPUIO },
255 { OMAP850_GPIO2_BASE, INT_850_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_850 }, 235 { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE,
256 { OMAP850_GPIO3_BASE, INT_850_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_850 }, 236 METHOD_GPIO_7XX },
257 { OMAP850_GPIO4_BASE, INT_850_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_850 }, 237 { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32,
258 { OMAP850_GPIO5_BASE, INT_850_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_850 }, 238 METHOD_GPIO_7XX },
259 { OMAP850_GPIO6_BASE, INT_850_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_850 }, 239 { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64,
240 METHOD_GPIO_7XX },
241 { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96,
242 METHOD_GPIO_7XX },
243 { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128,
244 METHOD_GPIO_7XX },
245 { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160,
246 METHOD_GPIO_7XX },
260}; 247};
261#endif 248#endif
262 249
263 250#ifdef CONFIG_ARCH_OMAP2
264#ifdef CONFIG_ARCH_OMAP24XX
265 251
266static struct gpio_bank gpio_bank_242x[4] = { 252static struct gpio_bank gpio_bank_242x[4] = {
267 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, 253 { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
268 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, 254 METHOD_GPIO_24XX },
269 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, 255 { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
270 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, 256 METHOD_GPIO_24XX },
257 { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
258 METHOD_GPIO_24XX },
259 { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
260 METHOD_GPIO_24XX },
271}; 261};
272 262
273static struct gpio_bank gpio_bank_243x[5] = { 263static struct gpio_bank gpio_bank_243x[5] = {
274 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, 264 { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
275 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, 265 METHOD_GPIO_24XX },
276 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, 266 { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
277 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, 267 METHOD_GPIO_24XX },
278 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX }, 268 { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
269 METHOD_GPIO_24XX },
270 { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
271 METHOD_GPIO_24XX },
272 { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128,
273 METHOD_GPIO_24XX },
279}; 274};
280 275
281#endif 276#endif
282 277
283#ifdef CONFIG_ARCH_OMAP34XX 278#ifdef CONFIG_ARCH_OMAP3
284static struct gpio_bank gpio_bank_34xx[6] = { 279static struct gpio_bank gpio_bank_34xx[6] = {
285 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, 280 { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,
286 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
287 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
288 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
289 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
290 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
291};
292
293#endif
294
295#ifdef CONFIG_ARCH_OMAP4
296static struct gpio_bank gpio_bank_44xx[6] = {
297 { OMAP44XX_GPIO1_BASE, INT_44XX_GPIO_BANK1, IH_GPIO_BASE, \
298 METHOD_GPIO_24XX }, 281 METHOD_GPIO_24XX },
299 { OMAP44XX_GPIO2_BASE, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32, \ 282 { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,
300 METHOD_GPIO_24XX }, 283 METHOD_GPIO_24XX },
301 { OMAP44XX_GPIO3_BASE, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64, \ 284 { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,
302 METHOD_GPIO_24XX }, 285 METHOD_GPIO_24XX },
303 { OMAP44XX_GPIO4_BASE, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96, \ 286 { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,
304 METHOD_GPIO_24XX }, 287 METHOD_GPIO_24XX },
305 { OMAP44XX_GPIO5_BASE, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128, \ 288 { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128,
306 METHOD_GPIO_24XX }, 289 METHOD_GPIO_24XX },
307 { OMAP44XX_GPIO6_BASE, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160, \ 290 { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
308 METHOD_GPIO_24XX }, 291 METHOD_GPIO_24XX },
309}; 292};
310 293
294struct omap3_gpio_regs {
295 u32 sysconfig;
296 u32 irqenable1;
297 u32 irqenable2;
298 u32 wake_en;
299 u32 ctrl;
300 u32 oe;
301 u32 leveldetect0;
302 u32 leveldetect1;
303 u32 risingdetect;
304 u32 fallingdetect;
305 u32 dataout;
306 u32 setwkuena;
307 u32 setdataout;
308};
309
310static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
311#endif
312
313#ifdef CONFIG_ARCH_OMAP4
314static struct gpio_bank gpio_bank_44xx[6] = {
315 { OMAP44XX_GPIO1_BASE, NULL, OMAP44XX_IRQ_GPIO1, IH_GPIO_BASE,
316 METHOD_GPIO_44XX },
317 { OMAP44XX_GPIO2_BASE, NULL, OMAP44XX_IRQ_GPIO2, IH_GPIO_BASE + 32,
318 METHOD_GPIO_44XX },
319 { OMAP44XX_GPIO3_BASE, NULL, OMAP44XX_IRQ_GPIO3, IH_GPIO_BASE + 64,
320 METHOD_GPIO_44XX },
321 { OMAP44XX_GPIO4_BASE, NULL, OMAP44XX_IRQ_GPIO4, IH_GPIO_BASE + 96,
322 METHOD_GPIO_44XX },
323 { OMAP44XX_GPIO5_BASE, NULL, OMAP44XX_IRQ_GPIO5, IH_GPIO_BASE + 128,
324 METHOD_GPIO_44XX },
325 { OMAP44XX_GPIO6_BASE, NULL, OMAP44XX_IRQ_GPIO6, IH_GPIO_BASE + 160,
326 METHOD_GPIO_44XX },
327};
328
311#endif 329#endif
312 330
313static struct gpio_bank *gpio_bank; 331static struct gpio_bank *gpio_bank;
@@ -402,23 +420,18 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
402 reg += OMAP1610_GPIO_DIRECTION; 420 reg += OMAP1610_GPIO_DIRECTION;
403 break; 421 break;
404#endif 422#endif
405#ifdef CONFIG_ARCH_OMAP730 423#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
406 case METHOD_GPIO_730: 424 case METHOD_GPIO_7XX:
407 reg += OMAP730_GPIO_DIR_CONTROL; 425 reg += OMAP7XX_GPIO_DIR_CONTROL;
408 break;
409#endif
410#ifdef CONFIG_ARCH_OMAP850
411 case METHOD_GPIO_850:
412 reg += OMAP850_GPIO_DIR_CONTROL;
413 break; 426 break;
414#endif 427#endif
415#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 428#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
416 case METHOD_GPIO_24XX: 429 case METHOD_GPIO_24XX:
417 reg += OMAP24XX_GPIO_OE; 430 reg += OMAP24XX_GPIO_OE;
418 break; 431 break;
419#endif 432#endif
420#if defined(CONFIG_ARCH_OMAP4) 433#if defined(CONFIG_ARCH_OMAP4)
421 case METHOD_GPIO_24XX: 434 case METHOD_GPIO_44XX:
422 reg += OMAP4_GPIO_OE; 435 reg += OMAP4_GPIO_OE;
423 break; 436 break;
424#endif 437#endif
@@ -469,9 +482,9 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
469 l = 1 << gpio; 482 l = 1 << gpio;
470 break; 483 break;
471#endif 484#endif
472#ifdef CONFIG_ARCH_OMAP730 485#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
473 case METHOD_GPIO_730: 486 case METHOD_GPIO_7XX:
474 reg += OMAP730_GPIO_DATA_OUTPUT; 487 reg += OMAP7XX_GPIO_DATA_OUTPUT;
475 l = __raw_readl(reg); 488 l = __raw_readl(reg);
476 if (enable) 489 if (enable)
477 l |= 1 << gpio; 490 l |= 1 << gpio;
@@ -479,17 +492,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
479 l &= ~(1 << gpio); 492 l &= ~(1 << gpio);
480 break; 493 break;
481#endif 494#endif
482#ifdef CONFIG_ARCH_OMAP850 495#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
483 case METHOD_GPIO_850:
484 reg += OMAP850_GPIO_DATA_OUTPUT;
485 l = __raw_readl(reg);
486 if (enable)
487 l |= 1 << gpio;
488 else
489 l &= ~(1 << gpio);
490 break;
491#endif
492#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
493 case METHOD_GPIO_24XX: 496 case METHOD_GPIO_24XX:
494 if (enable) 497 if (enable)
495 reg += OMAP24XX_GPIO_SETDATAOUT; 498 reg += OMAP24XX_GPIO_SETDATAOUT;
@@ -499,7 +502,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
499 break; 502 break;
500#endif 503#endif
501#ifdef CONFIG_ARCH_OMAP4 504#ifdef CONFIG_ARCH_OMAP4
502 case METHOD_GPIO_24XX: 505 case METHOD_GPIO_44XX:
503 if (enable) 506 if (enable)
504 reg += OMAP4_GPIO_SETDATAOUT; 507 reg += OMAP4_GPIO_SETDATAOUT;
505 else 508 else
@@ -537,23 +540,18 @@ static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
537 reg += OMAP1610_GPIO_DATAIN; 540 reg += OMAP1610_GPIO_DATAIN;
538 break; 541 break;
539#endif 542#endif
540#ifdef CONFIG_ARCH_OMAP730 543#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
541 case METHOD_GPIO_730: 544 case METHOD_GPIO_7XX:
542 reg += OMAP730_GPIO_DATA_INPUT; 545 reg += OMAP7XX_GPIO_DATA_INPUT;
543 break; 546 break;
544#endif 547#endif
545#ifdef CONFIG_ARCH_OMAP850 548#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
546 case METHOD_GPIO_850:
547 reg += OMAP850_GPIO_DATA_INPUT;
548 break;
549#endif
550#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
551 case METHOD_GPIO_24XX: 549 case METHOD_GPIO_24XX:
552 reg += OMAP24XX_GPIO_DATAIN; 550 reg += OMAP24XX_GPIO_DATAIN;
553 break; 551 break;
554#endif 552#endif
555#ifdef CONFIG_ARCH_OMAP4 553#ifdef CONFIG_ARCH_OMAP4
556 case METHOD_GPIO_24XX: 554 case METHOD_GPIO_44XX:
557 reg += OMAP4_GPIO_DATAIN; 555 reg += OMAP4_GPIO_DATAIN;
558 break; 556 break;
559#endif 557#endif
@@ -588,19 +586,14 @@ static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
588 reg += OMAP1610_GPIO_DATAOUT; 586 reg += OMAP1610_GPIO_DATAOUT;
589 break; 587 break;
590#endif 588#endif
591#ifdef CONFIG_ARCH_OMAP730 589#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
592 case METHOD_GPIO_730: 590 case METHOD_GPIO_7XX:
593 reg += OMAP730_GPIO_DATA_OUTPUT; 591 reg += OMAP7XX_GPIO_DATA_OUTPUT;
594 break; 592 break;
595#endif 593#endif
596#ifdef CONFIG_ARCH_OMAP850 594#ifdef CONFIG_ARCH_OMAP2PLUS
597 case METHOD_GPIO_850:
598 reg += OMAP850_GPIO_DATA_OUTPUT;
599 break;
600#endif
601#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
602 defined(CONFIG_ARCH_OMAP4)
603 case METHOD_GPIO_24XX: 595 case METHOD_GPIO_24XX:
596 case METHOD_GPIO_44XX:
604 reg += OMAP24XX_GPIO_DATAOUT; 597 reg += OMAP24XX_GPIO_DATAOUT;
605 break; 598 break;
606#endif 599#endif
@@ -631,11 +624,16 @@ void omap_set_gpio_debounce(int gpio, int enable)
631 624
632 bank = get_gpio_bank(gpio); 625 bank = get_gpio_bank(gpio);
633 reg = bank->base; 626 reg = bank->base;
634#ifdef CONFIG_ARCH_OMAP4 627
635 reg += OMAP4_GPIO_DEBOUNCENABLE; 628 if (cpu_is_omap44xx())
636#else 629 reg += OMAP4_GPIO_DEBOUNCENABLE;
637 reg += OMAP24XX_GPIO_DEBOUNCE_EN; 630 else
638#endif 631 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
632
633 if (!(bank->mod_usage & l)) {
634 printk(KERN_ERR "GPIO %d not requested\n", gpio);
635 return;
636 }
639 637
640 spin_lock_irqsave(&bank->lock, flags); 638 spin_lock_irqsave(&bank->lock, flags);
641 val = __raw_readl(reg); 639 val = __raw_readl(reg);
@@ -671,18 +669,23 @@ void omap_set_gpio_debounce_time(int gpio, int enc_time)
671 bank = get_gpio_bank(gpio); 669 bank = get_gpio_bank(gpio);
672 reg = bank->base; 670 reg = bank->base;
673 671
672 if (!bank->mod_usage) {
673 printk(KERN_ERR "GPIO not requested\n");
674 return;
675 }
676
674 enc_time &= 0xff; 677 enc_time &= 0xff;
675#ifdef CONFIG_ARCH_OMAP4 678
676 reg += OMAP4_GPIO_DEBOUNCINGTIME; 679 if (cpu_is_omap44xx())
677#else 680 reg += OMAP4_GPIO_DEBOUNCINGTIME;
678 reg += OMAP24XX_GPIO_DEBOUNCE_VAL; 681 else
679#endif 682 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
683
680 __raw_writel(enc_time, reg); 684 __raw_writel(enc_time, reg);
681} 685}
682EXPORT_SYMBOL(omap_set_gpio_debounce_time); 686EXPORT_SYMBOL(omap_set_gpio_debounce_time);
683 687
684#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 688#ifdef CONFIG_ARCH_OMAP2PLUS
685 defined(CONFIG_ARCH_OMAP4)
686static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, 689static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
687 int trigger) 690 int trigger)
688{ 691{
@@ -747,6 +750,44 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
747} 750}
748#endif 751#endif
749 752
753#ifdef CONFIG_ARCH_OMAP1
754/*
755 * This only applies to chips that can't do both rising and falling edge
756 * detection at once. For all other chips, this function is a noop.
757 */
758static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
759{
760 void __iomem *reg = bank->base;
761 u32 l = 0;
762
763 switch (bank->method) {
764 case METHOD_MPUIO:
765 reg += OMAP_MPUIO_GPIO_INT_EDGE;
766 break;
767#ifdef CONFIG_ARCH_OMAP15XX
768 case METHOD_GPIO_1510:
769 reg += OMAP1510_GPIO_INT_CONTROL;
770 break;
771#endif
772#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
773 case METHOD_GPIO_7XX:
774 reg += OMAP7XX_GPIO_INT_CONTROL;
775 break;
776#endif
777 default:
778 return;
779 }
780
781 l = __raw_readl(reg);
782 if ((l >> gpio) & 1)
783 l &= ~(1 << gpio);
784 else
785 l |= 1 << gpio;
786
787 __raw_writel(l, reg);
788}
789#endif
790
750static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) 791static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
751{ 792{
752 void __iomem *reg = bank->base; 793 void __iomem *reg = bank->base;
@@ -757,6 +798,8 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
757 case METHOD_MPUIO: 798 case METHOD_MPUIO:
758 reg += OMAP_MPUIO_GPIO_INT_EDGE; 799 reg += OMAP_MPUIO_GPIO_INT_EDGE;
759 l = __raw_readl(reg); 800 l = __raw_readl(reg);
801 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
802 bank->toggle_mask |= 1 << gpio;
760 if (trigger & IRQ_TYPE_EDGE_RISING) 803 if (trigger & IRQ_TYPE_EDGE_RISING)
761 l |= 1 << gpio; 804 l |= 1 << gpio;
762 else if (trigger & IRQ_TYPE_EDGE_FALLING) 805 else if (trigger & IRQ_TYPE_EDGE_FALLING)
@@ -769,6 +812,8 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
769 case METHOD_GPIO_1510: 812 case METHOD_GPIO_1510:
770 reg += OMAP1510_GPIO_INT_CONTROL; 813 reg += OMAP1510_GPIO_INT_CONTROL;
771 l = __raw_readl(reg); 814 l = __raw_readl(reg);
815 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
816 bank->toggle_mask |= 1 << gpio;
772 if (trigger & IRQ_TYPE_EDGE_RISING) 817 if (trigger & IRQ_TYPE_EDGE_RISING)
773 l |= 1 << gpio; 818 l |= 1 << gpio;
774 else if (trigger & IRQ_TYPE_EDGE_FALLING) 819 else if (trigger & IRQ_TYPE_EDGE_FALLING)
@@ -797,22 +842,12 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
797 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); 842 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
798 break; 843 break;
799#endif 844#endif
800#ifdef CONFIG_ARCH_OMAP730 845#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
801 case METHOD_GPIO_730: 846 case METHOD_GPIO_7XX:
802 reg += OMAP730_GPIO_INT_CONTROL; 847 reg += OMAP7XX_GPIO_INT_CONTROL;
803 l = __raw_readl(reg);
804 if (trigger & IRQ_TYPE_EDGE_RISING)
805 l |= 1 << gpio;
806 else if (trigger & IRQ_TYPE_EDGE_FALLING)
807 l &= ~(1 << gpio);
808 else
809 goto bad;
810 break;
811#endif
812#ifdef CONFIG_ARCH_OMAP850
813 case METHOD_GPIO_850:
814 reg += OMAP850_GPIO_INT_CONTROL;
815 l = __raw_readl(reg); 848 l = __raw_readl(reg);
849 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
850 bank->toggle_mask |= 1 << gpio;
816 if (trigger & IRQ_TYPE_EDGE_RISING) 851 if (trigger & IRQ_TYPE_EDGE_RISING)
817 l |= 1 << gpio; 852 l |= 1 << gpio;
818 else if (trigger & IRQ_TYPE_EDGE_FALLING) 853 else if (trigger & IRQ_TYPE_EDGE_FALLING)
@@ -821,9 +856,9 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
821 goto bad; 856 goto bad;
822 break; 857 break;
823#endif 858#endif
824#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 859#ifdef CONFIG_ARCH_OMAP2PLUS
825 defined(CONFIG_ARCH_OMAP4)
826 case METHOD_GPIO_24XX: 860 case METHOD_GPIO_24XX:
861 case METHOD_GPIO_44XX:
827 set_24xx_gpio_triggering(bank, gpio, trigger); 862 set_24xx_gpio_triggering(bank, gpio, trigger);
828 break; 863 break;
829#endif 864#endif
@@ -897,23 +932,18 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
897 reg += OMAP1610_GPIO_IRQSTATUS1; 932 reg += OMAP1610_GPIO_IRQSTATUS1;
898 break; 933 break;
899#endif 934#endif
900#ifdef CONFIG_ARCH_OMAP730 935#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
901 case METHOD_GPIO_730: 936 case METHOD_GPIO_7XX:
902 reg += OMAP730_GPIO_INT_STATUS; 937 reg += OMAP7XX_GPIO_INT_STATUS;
903 break;
904#endif
905#ifdef CONFIG_ARCH_OMAP850
906 case METHOD_GPIO_850:
907 reg += OMAP850_GPIO_INT_STATUS;
908 break; 938 break;
909#endif 939#endif
910#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 940#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
911 case METHOD_GPIO_24XX: 941 case METHOD_GPIO_24XX:
912 reg += OMAP24XX_GPIO_IRQSTATUS1; 942 reg += OMAP24XX_GPIO_IRQSTATUS1;
913 break; 943 break;
914#endif 944#endif
915#if defined(CONFIG_ARCH_OMAP4) 945#if defined(CONFIG_ARCH_OMAP4)
916 case METHOD_GPIO_24XX: 946 case METHOD_GPIO_44XX:
917 reg += OMAP4_GPIO_IRQSTATUS0; 947 reg += OMAP4_GPIO_IRQSTATUS0;
918 break; 948 break;
919#endif 949#endif
@@ -924,12 +954,11 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
924 __raw_writel(gpio_mask, reg); 954 __raw_writel(gpio_mask, reg);
925 955
926 /* Workaround for clearing DSP GPIO interrupts to allow retention */ 956 /* Workaround for clearing DSP GPIO interrupts to allow retention */
927#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 957 if (cpu_is_omap24xx() || cpu_is_omap34xx())
928 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2; 958 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
929#endif 959 else if (cpu_is_omap44xx())
930#if defined(CONFIG_ARCH_OMAP4) 960 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
931 reg = bank->base + OMAP4_GPIO_IRQSTATUS1; 961
932#endif
933 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) { 962 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
934 __raw_writel(gpio_mask, reg); 963 __raw_writel(gpio_mask, reg);
935 964
@@ -971,28 +1000,21 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
971 mask = 0xffff; 1000 mask = 0xffff;
972 break; 1001 break;
973#endif 1002#endif
974#ifdef CONFIG_ARCH_OMAP730 1003#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
975 case METHOD_GPIO_730: 1004 case METHOD_GPIO_7XX:
976 reg += OMAP730_GPIO_INT_MASK; 1005 reg += OMAP7XX_GPIO_INT_MASK;
977 mask = 0xffffffff; 1006 mask = 0xffffffff;
978 inv = 1; 1007 inv = 1;
979 break; 1008 break;
980#endif 1009#endif
981#ifdef CONFIG_ARCH_OMAP850 1010#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
982 case METHOD_GPIO_850:
983 reg += OMAP850_GPIO_INT_MASK;
984 mask = 0xffffffff;
985 inv = 1;
986 break;
987#endif
988#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
989 case METHOD_GPIO_24XX: 1011 case METHOD_GPIO_24XX:
990 reg += OMAP24XX_GPIO_IRQENABLE1; 1012 reg += OMAP24XX_GPIO_IRQENABLE1;
991 mask = 0xffffffff; 1013 mask = 0xffffffff;
992 break; 1014 break;
993#endif 1015#endif
994#if defined(CONFIG_ARCH_OMAP4) 1016#if defined(CONFIG_ARCH_OMAP4)
995 case METHOD_GPIO_24XX: 1017 case METHOD_GPIO_44XX:
996 reg += OMAP4_GPIO_IRQSTATUSSET0; 1018 reg += OMAP4_GPIO_IRQSTATUSSET0;
997 mask = 0xffffffff; 1019 mask = 0xffffffff;
998 break; 1020 break;
@@ -1044,9 +1066,9 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
1044 l = gpio_mask; 1066 l = gpio_mask;
1045 break; 1067 break;
1046#endif 1068#endif
1047#ifdef CONFIG_ARCH_OMAP730 1069#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1048 case METHOD_GPIO_730: 1070 case METHOD_GPIO_7XX:
1049 reg += OMAP730_GPIO_INT_MASK; 1071 reg += OMAP7XX_GPIO_INT_MASK;
1050 l = __raw_readl(reg); 1072 l = __raw_readl(reg);
1051 if (enable) 1073 if (enable)
1052 l &= ~(gpio_mask); 1074 l &= ~(gpio_mask);
@@ -1054,17 +1076,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
1054 l |= gpio_mask; 1076 l |= gpio_mask;
1055 break; 1077 break;
1056#endif 1078#endif
1057#ifdef CONFIG_ARCH_OMAP850 1079#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1058 case METHOD_GPIO_850:
1059 reg += OMAP850_GPIO_INT_MASK;
1060 l = __raw_readl(reg);
1061 if (enable)
1062 l &= ~(gpio_mask);
1063 else
1064 l |= gpio_mask;
1065 break;
1066#endif
1067#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1068 case METHOD_GPIO_24XX: 1080 case METHOD_GPIO_24XX:
1069 if (enable) 1081 if (enable)
1070 reg += OMAP24XX_GPIO_SETIRQENABLE1; 1082 reg += OMAP24XX_GPIO_SETIRQENABLE1;
@@ -1074,7 +1086,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
1074 break; 1086 break;
1075#endif 1087#endif
1076#ifdef CONFIG_ARCH_OMAP4 1088#ifdef CONFIG_ARCH_OMAP4
1077 case METHOD_GPIO_24XX: 1089 case METHOD_GPIO_44XX:
1078 if (enable) 1090 if (enable)
1079 reg += OMAP4_GPIO_IRQSTATUSSET0; 1091 reg += OMAP4_GPIO_IRQSTATUSSET0;
1080 else 1092 else
@@ -1104,7 +1116,7 @@ static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int ena
1104 */ 1116 */
1105static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) 1117static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
1106{ 1118{
1107 unsigned long flags; 1119 unsigned long uninitialized_var(flags);
1108 1120
1109 switch (bank->method) { 1121 switch (bank->method) {
1110#ifdef CONFIG_ARCH_OMAP16XX 1122#ifdef CONFIG_ARCH_OMAP16XX
@@ -1118,9 +1130,9 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
1118 spin_unlock_irqrestore(&bank->lock, flags); 1130 spin_unlock_irqrestore(&bank->lock, flags);
1119 return 0; 1131 return 0;
1120#endif 1132#endif
1121#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 1133#ifdef CONFIG_ARCH_OMAP2PLUS
1122 defined(CONFIG_ARCH_OMAP4)
1123 case METHOD_GPIO_24XX: 1134 case METHOD_GPIO_24XX:
1135 case METHOD_GPIO_44XX:
1124 if (bank->non_wakeup_gpios & (1 << gpio)) { 1136 if (bank->non_wakeup_gpios & (1 << gpio)) {
1125 printk(KERN_ERR "Unable to modify wakeup on " 1137 printk(KERN_ERR "Unable to modify wakeup on "
1126 "non-wakeup GPIO%d\n", 1138 "non-wakeup GPIO%d\n",
@@ -1186,6 +1198,16 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1186 __raw_writel(__raw_readl(reg) | (1 << offset), reg); 1198 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
1187 } 1199 }
1188#endif 1200#endif
1201 if (!cpu_class_is_omap1()) {
1202 if (!bank->mod_usage) {
1203 u32 ctrl;
1204 ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1205 ctrl &= 0xFFFFFFFE;
1206 /* Module is enabled, clocks are not gated */
1207 __raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL);
1208 }
1209 bank->mod_usage |= 1 << offset;
1210 }
1189 spin_unlock_irqrestore(&bank->lock, flags); 1211 spin_unlock_irqrestore(&bank->lock, flags);
1190 1212
1191 return 0; 1213 return 0;
@@ -1204,14 +1226,24 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1204 __raw_writel(1 << offset, reg); 1226 __raw_writel(1 << offset, reg);
1205 } 1227 }
1206#endif 1228#endif
1207#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 1229#ifdef CONFIG_ARCH_OMAP2PLUS
1208 defined(CONFIG_ARCH_OMAP4) 1230 if ((bank->method == METHOD_GPIO_24XX) ||
1209 if (bank->method == METHOD_GPIO_24XX) { 1231 (bank->method == METHOD_GPIO_44XX)) {
1210 /* Disable wake-up during idle for dynamic tick */ 1232 /* Disable wake-up during idle for dynamic tick */
1211 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 1233 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1212 __raw_writel(1 << offset, reg); 1234 __raw_writel(1 << offset, reg);
1213 } 1235 }
1214#endif 1236#endif
1237 if (!cpu_class_is_omap1()) {
1238 bank->mod_usage &= ~(1 << offset);
1239 if (!bank->mod_usage) {
1240 u32 ctrl;
1241 ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1242 /* Module is disabled, clocks are gated */
1243 ctrl |= 1;
1244 __raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL);
1245 }
1246 }
1215 _reset_gpio(bank, bank->chip.base + offset); 1247 _reset_gpio(bank, bank->chip.base + offset);
1216 spin_unlock_irqrestore(&bank->lock, flags); 1248 spin_unlock_irqrestore(&bank->lock, flags);
1217} 1249}
@@ -1229,7 +1261,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1229{ 1261{
1230 void __iomem *isr_reg = NULL; 1262 void __iomem *isr_reg = NULL;
1231 u32 isr; 1263 u32 isr;
1232 unsigned int gpio_irq; 1264 unsigned int gpio_irq, gpio_index;
1233 struct gpio_bank *bank; 1265 struct gpio_bank *bank;
1234 u32 retrigger = 0; 1266 u32 retrigger = 0;
1235 int unmasked = 0; 1267 int unmasked = 0;
@@ -1249,20 +1281,16 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1249 if (bank->method == METHOD_GPIO_1610) 1281 if (bank->method == METHOD_GPIO_1610)
1250 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1; 1282 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1251#endif 1283#endif
1252#ifdef CONFIG_ARCH_OMAP730 1284#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1253 if (bank->method == METHOD_GPIO_730) 1285 if (bank->method == METHOD_GPIO_7XX)
1254 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS; 1286 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1255#endif
1256#ifdef CONFIG_ARCH_OMAP850
1257 if (bank->method == METHOD_GPIO_850)
1258 isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
1259#endif 1287#endif
1260#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 1288#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1261 if (bank->method == METHOD_GPIO_24XX) 1289 if (bank->method == METHOD_GPIO_24XX)
1262 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; 1290 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1263#endif 1291#endif
1264#if defined(CONFIG_ARCH_OMAP4) 1292#if defined(CONFIG_ARCH_OMAP4)
1265 if (bank->method == METHOD_GPIO_24XX) 1293 if (bank->method == METHOD_GPIO_44XX)
1266 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0; 1294 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1267#endif 1295#endif
1268 while(1) { 1296 while(1) {
@@ -1300,9 +1328,23 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1300 1328
1301 gpio_irq = bank->virtual_irq_start; 1329 gpio_irq = bank->virtual_irq_start;
1302 for (; isr != 0; isr >>= 1, gpio_irq++) { 1330 for (; isr != 0; isr >>= 1, gpio_irq++) {
1331 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1332
1303 if (!(isr & 1)) 1333 if (!(isr & 1))
1304 continue; 1334 continue;
1305 1335
1336#ifdef CONFIG_ARCH_OMAP1
1337 /*
1338 * Some chips can't respond to both rising and falling
1339 * at the same time. If this irq was requested with
1340 * both flags, we need to flip the ICR data for the IRQ
1341 * to respond to the IRQ for the opposite direction.
1342 * This will be indicated in the bank toggle_mask.
1343 */
1344 if (bank->toggle_mask & (1 << gpio_index))
1345 _toggle_gpio_edge_triggering(bank, gpio_index);
1346#endif
1347
1306 generic_handle_irq(gpio_irq); 1348 generic_handle_irq(gpio_irq);
1307 } 1349 }
1308 } 1350 }
@@ -1447,7 +1489,7 @@ static int omap_mpuio_resume_noirq(struct device *dev)
1447 return 0; 1489 return 0;
1448} 1490}
1449 1491
1450static struct dev_pm_ops omap_mpuio_dev_pm_ops = { 1492static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1451 .suspend_noirq = omap_mpuio_suspend_noirq, 1493 .suspend_noirq = omap_mpuio_suspend_noirq,
1452 .resume_noirq = omap_mpuio_resume_noirq, 1494 .resume_noirq = omap_mpuio_resume_noirq,
1453}; 1495};
@@ -1524,13 +1566,11 @@ static int gpio_is_input(struct gpio_bank *bank, int mask)
1524 case METHOD_GPIO_1610: 1566 case METHOD_GPIO_1610:
1525 reg += OMAP1610_GPIO_DIRECTION; 1567 reg += OMAP1610_GPIO_DIRECTION;
1526 break; 1568 break;
1527 case METHOD_GPIO_730: 1569 case METHOD_GPIO_7XX:
1528 reg += OMAP730_GPIO_DIR_CONTROL; 1570 reg += OMAP7XX_GPIO_DIR_CONTROL;
1529 break;
1530 case METHOD_GPIO_850:
1531 reg += OMAP850_GPIO_DIR_CONTROL;
1532 break; 1571 break;
1533 case METHOD_GPIO_24XX: 1572 case METHOD_GPIO_24XX:
1573 case METHOD_GPIO_44XX:
1534 reg += OMAP24XX_GPIO_OE; 1574 reg += OMAP24XX_GPIO_OE;
1535 break; 1575 break;
1536 } 1576 }
@@ -1590,7 +1630,7 @@ static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1590/*---------------------------------------------------------------------*/ 1630/*---------------------------------------------------------------------*/
1591 1631
1592static int initialized; 1632static int initialized;
1593#if !(defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)) 1633#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2)
1594static struct clk * gpio_ick; 1634static struct clk * gpio_ick;
1595#endif 1635#endif
1596 1636
@@ -1607,6 +1647,23 @@ static struct clk * gpio5_fck;
1607static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS]; 1647static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1608#endif 1648#endif
1609 1649
1650static void __init omap_gpio_show_rev(void)
1651{
1652 u32 rev;
1653
1654 if (cpu_is_omap16xx())
1655 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1656 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1657 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1658 else if (cpu_is_omap44xx())
1659 rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
1660 else
1661 return;
1662
1663 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1664 (rev >> 4) & 0x0f, rev & 0x0f);
1665}
1666
1610/* This lock class tells lockdep that GPIO irqs are in a different 1667/* This lock class tells lockdep that GPIO irqs are in a different
1611 * category than their parents, so it won't report false recursion. 1668 * category than their parents, so it won't report false recursion.
1612 */ 1669 */
@@ -1617,6 +1674,7 @@ static int __init _omap_gpio_init(void)
1617 int i; 1674 int i;
1618 int gpio = 0; 1675 int gpio = 0;
1619 struct gpio_bank *bank; 1676 struct gpio_bank *bank;
1677 int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
1620 char clk_name[11]; 1678 char clk_name[11];
1621 1679
1622 initialized = 1; 1680 initialized = 1;
@@ -1679,77 +1737,45 @@ static int __init _omap_gpio_init(void)
1679 1737
1680#ifdef CONFIG_ARCH_OMAP15XX 1738#ifdef CONFIG_ARCH_OMAP15XX
1681 if (cpu_is_omap15xx()) { 1739 if (cpu_is_omap15xx()) {
1682 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1683 gpio_bank_count = 2; 1740 gpio_bank_count = 2;
1684 gpio_bank = gpio_bank_1510; 1741 gpio_bank = gpio_bank_1510;
1742 bank_size = SZ_2K;
1685 } 1743 }
1686#endif 1744#endif
1687#if defined(CONFIG_ARCH_OMAP16XX) 1745#if defined(CONFIG_ARCH_OMAP16XX)
1688 if (cpu_is_omap16xx()) { 1746 if (cpu_is_omap16xx()) {
1689 u32 rev;
1690
1691 gpio_bank_count = 5; 1747 gpio_bank_count = 5;
1692 gpio_bank = gpio_bank_1610; 1748 gpio_bank = gpio_bank_1610;
1693 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION); 1749 bank_size = SZ_2K;
1694 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1695 (rev >> 4) & 0x0f, rev & 0x0f);
1696 }
1697#endif
1698#ifdef CONFIG_ARCH_OMAP730
1699 if (cpu_is_omap730()) {
1700 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1701 gpio_bank_count = 7;
1702 gpio_bank = gpio_bank_730;
1703 } 1750 }
1704#endif 1751#endif
1705#ifdef CONFIG_ARCH_OMAP850 1752#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1706 if (cpu_is_omap850()) { 1753 if (cpu_is_omap7xx()) {
1707 printk(KERN_INFO "OMAP850 GPIO hardware\n");
1708 gpio_bank_count = 7; 1754 gpio_bank_count = 7;
1709 gpio_bank = gpio_bank_850; 1755 gpio_bank = gpio_bank_7xx;
1756 bank_size = SZ_2K;
1710 } 1757 }
1711#endif 1758#endif
1712 1759#ifdef CONFIG_ARCH_OMAP2
1713#ifdef CONFIG_ARCH_OMAP24XX
1714 if (cpu_is_omap242x()) { 1760 if (cpu_is_omap242x()) {
1715 int rev;
1716
1717 gpio_bank_count = 4; 1761 gpio_bank_count = 4;
1718 gpio_bank = gpio_bank_242x; 1762 gpio_bank = gpio_bank_242x;
1719 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1720 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1721 (rev >> 4) & 0x0f, rev & 0x0f);
1722 } 1763 }
1723 if (cpu_is_omap243x()) { 1764 if (cpu_is_omap243x()) {
1724 int rev;
1725
1726 gpio_bank_count = 5; 1765 gpio_bank_count = 5;
1727 gpio_bank = gpio_bank_243x; 1766 gpio_bank = gpio_bank_243x;
1728 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1729 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1730 (rev >> 4) & 0x0f, rev & 0x0f);
1731 } 1767 }
1732#endif 1768#endif
1733#ifdef CONFIG_ARCH_OMAP34XX 1769#ifdef CONFIG_ARCH_OMAP3
1734 if (cpu_is_omap34xx()) { 1770 if (cpu_is_omap34xx()) {
1735 int rev;
1736
1737 gpio_bank_count = OMAP34XX_NR_GPIOS; 1771 gpio_bank_count = OMAP34XX_NR_GPIOS;
1738 gpio_bank = gpio_bank_34xx; 1772 gpio_bank = gpio_bank_34xx;
1739 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1740 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1741 (rev >> 4) & 0x0f, rev & 0x0f);
1742 } 1773 }
1743#endif 1774#endif
1744#ifdef CONFIG_ARCH_OMAP4 1775#ifdef CONFIG_ARCH_OMAP4
1745 if (cpu_is_omap44xx()) { 1776 if (cpu_is_omap44xx()) {
1746 int rev;
1747
1748 gpio_bank_count = OMAP34XX_NR_GPIOS; 1777 gpio_bank_count = OMAP34XX_NR_GPIOS;
1749 gpio_bank = gpio_bank_44xx; 1778 gpio_bank = gpio_bank_44xx;
1750 rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
1751 printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n",
1752 (rev >> 4) & 0x0f, rev & 0x0f);
1753 } 1779 }
1754#endif 1780#endif
1755 for (i = 0; i < gpio_bank_count; i++) { 1781 for (i = 0; i < gpio_bank_count; i++) {
@@ -1757,6 +1783,14 @@ static int __init _omap_gpio_init(void)
1757 1783
1758 bank = &gpio_bank[i]; 1784 bank = &gpio_bank[i];
1759 spin_lock_init(&bank->lock); 1785 spin_lock_init(&bank->lock);
1786
1787 /* Static mapping, never released */
1788 bank->base = ioremap(bank->pbase, bank_size);
1789 if (!bank->base) {
1790 printk(KERN_ERR "Could not ioremap gpio bank%i\n", i);
1791 continue;
1792 }
1793
1760 if (bank_is_mpuio(bank)) 1794 if (bank_is_mpuio(bank))
1761 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT); 1795 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1762 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { 1796 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
@@ -1768,42 +1802,56 @@ static int __init _omap_gpio_init(void)
1768 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); 1802 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1769 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); 1803 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1770 } 1804 }
1771 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_730) { 1805 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1772 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK); 1806 __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
1773 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS); 1807 __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
1774 1808
1775 gpio_count = 32; /* 730 has 32-bit GPIOs */ 1809 gpio_count = 32; /* 7xx has 32-bit GPIOs */
1776 } 1810 }
1777 1811
1778#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 1812#ifdef CONFIG_ARCH_OMAP2PLUS
1779 defined(CONFIG_ARCH_OMAP4) 1813 if ((bank->method == METHOD_GPIO_24XX) ||
1780 if (bank->method == METHOD_GPIO_24XX) { 1814 (bank->method == METHOD_GPIO_44XX)) {
1781 static const u32 non_wakeup_gpios[] = { 1815 static const u32 non_wakeup_gpios[] = {
1782 0xe203ffc0, 0x08700040 1816 0xe203ffc0, 0x08700040
1783 }; 1817 };
1784 if (cpu_is_omap44xx()) { 1818
1785 __raw_writel(0xffffffff, bank->base + 1819 if (cpu_is_omap44xx()) {
1820 __raw_writel(0xffffffff, bank->base +
1786 OMAP4_GPIO_IRQSTATUSCLR0); 1821 OMAP4_GPIO_IRQSTATUSCLR0);
1787 __raw_writew(0x0015, bank->base + 1822 __raw_writew(0x0015, bank->base +
1788 OMAP4_GPIO_SYSCONFIG); 1823 OMAP4_GPIO_SYSCONFIG);
1789 __raw_writel(0x00000000, bank->base + 1824 __raw_writel(0x00000000, bank->base +
1790 OMAP4_GPIO_DEBOUNCENABLE); 1825 OMAP4_GPIO_DEBOUNCENABLE);
1791 /* Initialize interface clock ungated, module enabled */ 1826 /*
1792 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL); 1827 * Initialize interface clock ungated,
1793 } else { 1828 * module enabled
1794 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1); 1829 */
1795 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1); 1830 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1796 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG); 1831 } else {
1797 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN); 1832 __raw_writel(0x00000000, bank->base +
1798 1833 OMAP24XX_GPIO_IRQENABLE1);
1799 /* Initialize interface clock ungated, module enabled */ 1834 __raw_writel(0xffffffff, bank->base +
1800 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); 1835 OMAP24XX_GPIO_IRQSTATUS1);
1801 } 1836 __raw_writew(0x0015, bank->base +
1837 OMAP24XX_GPIO_SYSCONFIG);
1838 __raw_writel(0x00000000, bank->base +
1839 OMAP24XX_GPIO_DEBOUNCE_EN);
1840
1841 /*
1842 * Initialize interface clock ungated,
1843 * module enabled
1844 */
1845 __raw_writel(0, bank->base +
1846 OMAP24XX_GPIO_CTRL);
1847 }
1802 if (i < ARRAY_SIZE(non_wakeup_gpios)) 1848 if (i < ARRAY_SIZE(non_wakeup_gpios))
1803 bank->non_wakeup_gpios = non_wakeup_gpios[i]; 1849 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1804 gpio_count = 32; 1850 gpio_count = 32;
1805 } 1851 }
1806#endif 1852#endif
1853
1854 bank->mod_usage = 0;
1807 /* REVISIT eventually switch from OMAP-specific gpio structs 1855 /* REVISIT eventually switch from OMAP-specific gpio structs
1808 * over to the generic ones 1856 * over to the generic ones
1809 */ 1857 */
@@ -1862,11 +1910,12 @@ static int __init _omap_gpio_init(void)
1862 if (cpu_is_omap34xx()) 1910 if (cpu_is_omap34xx())
1863 omap_writel(1 << 0, 0x48306814); 1911 omap_writel(1 << 0, 0x48306814);
1864 1912
1913 omap_gpio_show_rev();
1914
1865 return 0; 1915 return 0;
1866} 1916}
1867 1917
1868#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \ 1918#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1869 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
1870static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) 1919static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1871{ 1920{
1872 int i; 1921 int i;
@@ -1889,7 +1938,7 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1889 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; 1938 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1890 break; 1939 break;
1891#endif 1940#endif
1892#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 1941#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1893 case METHOD_GPIO_24XX: 1942 case METHOD_GPIO_24XX:
1894 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN; 1943 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1895 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 1944 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
@@ -1897,7 +1946,7 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1897 break; 1946 break;
1898#endif 1947#endif
1899#ifdef CONFIG_ARCH_OMAP4 1948#ifdef CONFIG_ARCH_OMAP4
1900 case METHOD_GPIO_24XX: 1949 case METHOD_GPIO_44XX:
1901 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0; 1950 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1902 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; 1951 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1903 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; 1952 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
@@ -1937,14 +1986,14 @@ static int omap_gpio_resume(struct sys_device *dev)
1937 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; 1986 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1938 break; 1987 break;
1939#endif 1988#endif
1940#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 1989#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1941 case METHOD_GPIO_24XX: 1990 case METHOD_GPIO_24XX:
1942 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 1991 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1943 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; 1992 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1944 break; 1993 break;
1945#endif 1994#endif
1946#ifdef CONFIG_ARCH_OMAP4 1995#ifdef CONFIG_ARCH_OMAP4
1947 case METHOD_GPIO_24XX: 1996 case METHOD_GPIO_44XX:
1948 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; 1997 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1949 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; 1998 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1950 break; 1999 break;
@@ -1975,8 +2024,7 @@ static struct sys_device omap_gpio_device = {
1975 2024
1976#endif 2025#endif
1977 2026
1978#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 2027#ifdef CONFIG_ARCH_OMAP2PLUS
1979 defined(CONFIG_ARCH_OMAP4)
1980 2028
1981static int workaround_enabled; 2029static int workaround_enabled;
1982 2030
@@ -1992,29 +2040,42 @@ void omap2_gpio_prepare_for_retention(void)
1992 2040
1993 if (!(bank->enabled_non_wakeup_gpios)) 2041 if (!(bank->enabled_non_wakeup_gpios))
1994 continue; 2042 continue;
1995#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 2043
1996 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); 2044 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1997 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); 2045 bank->saved_datain = __raw_readl(bank->base +
1998 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); 2046 OMAP24XX_GPIO_DATAIN);
1999#endif 2047 l1 = __raw_readl(bank->base +
2000#ifdef CONFIG_ARCH_OMAP4 2048 OMAP24XX_GPIO_FALLINGDETECT);
2001 bank->saved_datain = __raw_readl(bank->base + 2049 l2 = __raw_readl(bank->base +
2002 OMAP4_GPIO_DATAIN); 2050 OMAP24XX_GPIO_RISINGDETECT);
2003 l1 = __raw_readl(bank->base + OMAP4_GPIO_FALLINGDETECT); 2051 }
2004 l2 = __raw_readl(bank->base + OMAP4_GPIO_RISINGDETECT); 2052
2005#endif 2053 if (cpu_is_omap44xx()) {
2054 bank->saved_datain = __raw_readl(bank->base +
2055 OMAP4_GPIO_DATAIN);
2056 l1 = __raw_readl(bank->base +
2057 OMAP4_GPIO_FALLINGDETECT);
2058 l2 = __raw_readl(bank->base +
2059 OMAP4_GPIO_RISINGDETECT);
2060 }
2061
2006 bank->saved_fallingdetect = l1; 2062 bank->saved_fallingdetect = l1;
2007 bank->saved_risingdetect = l2; 2063 bank->saved_risingdetect = l2;
2008 l1 &= ~bank->enabled_non_wakeup_gpios; 2064 l1 &= ~bank->enabled_non_wakeup_gpios;
2009 l2 &= ~bank->enabled_non_wakeup_gpios; 2065 l2 &= ~bank->enabled_non_wakeup_gpios;
2010#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 2066
2011 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT); 2067 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2012 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT); 2068 __raw_writel(l1, bank->base +
2013#endif 2069 OMAP24XX_GPIO_FALLINGDETECT);
2014#ifdef CONFIG_ARCH_OMAP4 2070 __raw_writel(l2, bank->base +
2015 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT); 2071 OMAP24XX_GPIO_RISINGDETECT);
2016 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT); 2072 }
2017#endif 2073
2074 if (cpu_is_omap44xx()) {
2075 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
2076 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
2077 }
2078
2018 c++; 2079 c++;
2019 } 2080 }
2020 if (!c) { 2081 if (!c) {
@@ -2036,20 +2097,23 @@ void omap2_gpio_resume_after_retention(void)
2036 2097
2037 if (!(bank->enabled_non_wakeup_gpios)) 2098 if (!(bank->enabled_non_wakeup_gpios))
2038 continue; 2099 continue;
2039#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 2100
2040 __raw_writel(bank->saved_fallingdetect, 2101 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2102 __raw_writel(bank->saved_fallingdetect,
2041 bank->base + OMAP24XX_GPIO_FALLINGDETECT); 2103 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2042 __raw_writel(bank->saved_risingdetect, 2104 __raw_writel(bank->saved_risingdetect,
2043 bank->base + OMAP24XX_GPIO_RISINGDETECT); 2105 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2044 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); 2106 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
2045#endif 2107 }
2046#ifdef CONFIG_ARCH_OMAP4 2108
2047 __raw_writel(bank->saved_fallingdetect, 2109 if (cpu_is_omap44xx()) {
2110 __raw_writel(bank->saved_fallingdetect,
2048 bank->base + OMAP4_GPIO_FALLINGDETECT); 2111 bank->base + OMAP4_GPIO_FALLINGDETECT);
2049 __raw_writel(bank->saved_risingdetect, 2112 __raw_writel(bank->saved_risingdetect,
2050 bank->base + OMAP4_GPIO_RISINGDETECT); 2113 bank->base + OMAP4_GPIO_RISINGDETECT);
2051 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN); 2114 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
2052#endif 2115 }
2116
2053 /* Check if any of the non-wakeup interrupt GPIOs have changed 2117 /* Check if any of the non-wakeup interrupt GPIOs have changed
2054 * state. If so, generate an IRQ by software. This is 2118 * state. If so, generate an IRQ by software. This is
2055 * horribly racy, but it's the best we can do to work around 2119 * horribly racy, but it's the best we can do to work around
@@ -2075,30 +2139,36 @@ void omap2_gpio_resume_after_retention(void)
2075 2139
2076 if (gen) { 2140 if (gen) {
2077 u32 old0, old1; 2141 u32 old0, old1;
2078#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 2142
2079 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); 2143 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2080 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); 2144 old0 = __raw_readl(bank->base +
2081 __raw_writel(old0 | gen, bank->base +
2082 OMAP24XX_GPIO_LEVELDETECT0); 2145 OMAP24XX_GPIO_LEVELDETECT0);
2083 __raw_writel(old1 | gen, bank->base + 2146 old1 = __raw_readl(bank->base +
2084 OMAP24XX_GPIO_LEVELDETECT1); 2147 OMAP24XX_GPIO_LEVELDETECT1);
2085 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0); 2148 __raw_writel(old0 | gen, bank->base +
2086 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1); 2149 OMAP24XX_GPIO_LEVELDETECT0);
2087#endif 2150 __raw_writel(old1 | gen, bank->base +
2088#ifdef CONFIG_ARCH_OMAP4 2151 OMAP24XX_GPIO_LEVELDETECT1);
2089 old0 = __raw_readl(bank->base + 2152 __raw_writel(old0, bank->base +
2153 OMAP24XX_GPIO_LEVELDETECT0);
2154 __raw_writel(old1, bank->base +
2155 OMAP24XX_GPIO_LEVELDETECT1);
2156 }
2157
2158 if (cpu_is_omap44xx()) {
2159 old0 = __raw_readl(bank->base +
2090 OMAP4_GPIO_LEVELDETECT0); 2160 OMAP4_GPIO_LEVELDETECT0);
2091 old1 = __raw_readl(bank->base + 2161 old1 = __raw_readl(bank->base +
2092 OMAP4_GPIO_LEVELDETECT1); 2162 OMAP4_GPIO_LEVELDETECT1);
2093 __raw_writel(old0 | l, bank->base + 2163 __raw_writel(old0 | l, bank->base +
2094 OMAP4_GPIO_LEVELDETECT0); 2164 OMAP4_GPIO_LEVELDETECT0);
2095 __raw_writel(old1 | l, bank->base + 2165 __raw_writel(old1 | l, bank->base +
2096 OMAP4_GPIO_LEVELDETECT1); 2166 OMAP4_GPIO_LEVELDETECT1);
2097 __raw_writel(old0, bank->base + 2167 __raw_writel(old0, bank->base +
2098 OMAP4_GPIO_LEVELDETECT0); 2168 OMAP4_GPIO_LEVELDETECT0);
2099 __raw_writel(old1, bank->base + 2169 __raw_writel(old1, bank->base +
2100 OMAP4_GPIO_LEVELDETECT1); 2170 OMAP4_GPIO_LEVELDETECT1);
2101#endif 2171 }
2102 } 2172 }
2103 } 2173 }
2104 2174
@@ -2106,6 +2176,81 @@ void omap2_gpio_resume_after_retention(void)
2106 2176
2107#endif 2177#endif
2108 2178
2179#ifdef CONFIG_ARCH_OMAP3
2180/* save the registers of bank 2-6 */
2181void omap_gpio_save_context(void)
2182{
2183 int i;
2184
2185 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2186 for (i = 1; i < gpio_bank_count; i++) {
2187 struct gpio_bank *bank = &gpio_bank[i];
2188 gpio_context[i].sysconfig =
2189 __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG);
2190 gpio_context[i].irqenable1 =
2191 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
2192 gpio_context[i].irqenable2 =
2193 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
2194 gpio_context[i].wake_en =
2195 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
2196 gpio_context[i].ctrl =
2197 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
2198 gpio_context[i].oe =
2199 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
2200 gpio_context[i].leveldetect0 =
2201 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2202 gpio_context[i].leveldetect1 =
2203 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2204 gpio_context[i].risingdetect =
2205 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
2206 gpio_context[i].fallingdetect =
2207 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2208 gpio_context[i].dataout =
2209 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
2210 gpio_context[i].setwkuena =
2211 __raw_readl(bank->base + OMAP24XX_GPIO_SETWKUENA);
2212 gpio_context[i].setdataout =
2213 __raw_readl(bank->base + OMAP24XX_GPIO_SETDATAOUT);
2214 }
2215}
2216
2217/* restore the required registers of bank 2-6 */
2218void omap_gpio_restore_context(void)
2219{
2220 int i;
2221
2222 for (i = 1; i < gpio_bank_count; i++) {
2223 struct gpio_bank *bank = &gpio_bank[i];
2224 __raw_writel(gpio_context[i].sysconfig,
2225 bank->base + OMAP24XX_GPIO_SYSCONFIG);
2226 __raw_writel(gpio_context[i].irqenable1,
2227 bank->base + OMAP24XX_GPIO_IRQENABLE1);
2228 __raw_writel(gpio_context[i].irqenable2,
2229 bank->base + OMAP24XX_GPIO_IRQENABLE2);
2230 __raw_writel(gpio_context[i].wake_en,
2231 bank->base + OMAP24XX_GPIO_WAKE_EN);
2232 __raw_writel(gpio_context[i].ctrl,
2233 bank->base + OMAP24XX_GPIO_CTRL);
2234 __raw_writel(gpio_context[i].oe,
2235 bank->base + OMAP24XX_GPIO_OE);
2236 __raw_writel(gpio_context[i].leveldetect0,
2237 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2238 __raw_writel(gpio_context[i].leveldetect1,
2239 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2240 __raw_writel(gpio_context[i].risingdetect,
2241 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2242 __raw_writel(gpio_context[i].fallingdetect,
2243 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2244 __raw_writel(gpio_context[i].dataout,
2245 bank->base + OMAP24XX_GPIO_DATAOUT);
2246 __raw_writel(gpio_context[i].setwkuena,
2247 bank->base + OMAP24XX_GPIO_SETWKUENA);
2248 __raw_writel(gpio_context[i].setdataout,
2249 bank->base + OMAP24XX_GPIO_SETDATAOUT);
2250 }
2251}
2252#endif
2253
2109/* 2254/*
2110 * This may get called early from board specific init 2255 * This may get called early from board specific init
2111 * for boards that have interrupts routed via FPGA. 2256 * for boards that have interrupts routed via FPGA.
@@ -2127,8 +2272,7 @@ static int __init omap_gpio_sysinit(void)
2127 2272
2128 mpuio_init(); 2273 mpuio_init();
2129 2274
2130#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \ 2275#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
2131 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
2132 if (cpu_is_omap16xx() || cpu_class_is_omap2()) { 2276 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
2133 if (ret == 0) { 2277 if (ret == 0) {
2134 ret = sysdev_class_register(&omap_gpio_sysclass); 2278 ret = sysdev_class_register(&omap_gpio_sysclass);
@@ -2160,8 +2304,7 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
2160 2304
2161 if (bank_is_mpuio(bank)) 2305 if (bank_is_mpuio(bank))
2162 gpio = OMAP_MPUIO(0); 2306 gpio = OMAP_MPUIO(0);
2163 else if (cpu_class_is_omap2() || cpu_is_omap730() || 2307 else if (cpu_class_is_omap2() || cpu_is_omap7xx())
2164 cpu_is_omap850())
2165 bankwidth = 32; 2308 bankwidth = 32;
2166 2309
2167 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { 2310 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
@@ -2188,8 +2331,7 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
2188/* FIXME for at least omap2, show pullup/pulldown state */ 2331/* FIXME for at least omap2, show pullup/pulldown state */
2189 2332
2190 irqstat = irq_desc[irq].status; 2333 irqstat = irq_desc[irq].status;
2191#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \ 2334#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
2192 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
2193 if (is_in && ((bank->suspend_wakeup & mask) 2335 if (is_in && ((bank->suspend_wakeup & mask)
2194 || irqstat & IRQ_TYPE_SENSE_MASK)) { 2336 || irqstat & IRQ_TYPE_SENSE_MASK)) {
2195 char *trigger = NULL; 2337 char *trigger = NULL;
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-10 07:43:51 -0400