Merge branch 'master' into for-next

author: Jiri Kosina <jkosina@suse.cz> 2010-04-22 20:08:44 -0400
committer: Jiri Kosina <jkosina@suse.cz> 2010-04-22 20:08:44 -0400
commit: 6c9468e9eb1252eaefd94ce7f06e1be9b0b641b1 (patch)
tree: 797676a336b050bfa1ef879377c07e541b9075d6 /drivers/gpu/drm/radeon
parent: 4cb3ca7cd7e2cae8d1daf5345ec99a1e8502cf3f (diff)
parent: c81eddb0e3728661d1585fbc564449c94165cc36 (diff)
62 files changed, 2353 insertions, 1592 deletions
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index ed38262d9985..3c91312dea9a 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -50,7 +50,7 @@ $(obj)/r600_cs.o: $(obj)/r600_reg_safe.h
 radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \
        radeon_irq.o r300_cmdbuf.o r600_cp.o
 # add KMS driver
-radeon-y += radeon_device.o radeon_kms.o \
+radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
        radeon_atombios.o radeon_agp.o atombios_crtc.o radeon_combios.o \
        atom.o radeon_fence.o radeon_ttm.o radeon_object.o radeon_gart.o \
        radeon_legacy_crtc.o radeon_legacy_encoders.o radeon_connectors.o \
diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c
index d75788feac6c..1d569830ed99 100644
--- a/drivers/gpu/drm/radeon/atom.c
+++ b/drivers/gpu/drm/radeon/atom.c
@@ -24,6 +24,7 @@
 #include <linux/module.h>
 #include <linux/sched.h>
+#include <linux/slab.h>
 #include <asm/unaligned.h>
 #define ATOM_DEBUG
@@ -52,15 +53,17 @@
 typedef struct {
        struct atom_context *ctx;
        uint32_t *ps, *ws;
        int ps_shift;
        uint16_t start;
+        unsigned last_jump;
+        unsigned long last_jump_jiffies;
+        bool abort;
 } atom_exec_context;
 int atom_debug = 0;
-static void atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params);
+static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params);
-void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params);
+int atom_execute_table(struct atom_context *ctx, int index, uint32_t * params);
 static uint32_t atom_arg_mask[8] =
    { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000,
@@ -604,12 +607,17 @@ static void atom_op_beep(atom_exec_context *ctx, int *ptr, int arg)
 static void atom_op_calltable(atom_exec_context *ctx, int *ptr, int arg)
 {
        int idx = U8((*ptr)++);
+        int r = 0;
        if (idx < ATOM_TABLE_NAMES_CNT)
                SDEBUG("   table: %d (%s)\n", idx, atom_table_names[idx]);
        else
                SDEBUG("   table: %d\n", idx);
        if (U16(ctx->ctx->cmd_table + 4 + 2 * idx))
-                atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift);
+                r = atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift);
+        if (r) {
+                ctx->abort = true;
+        }
 }
 static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg)
@@ -673,6 +681,8 @@ static void atom_op_eot(atom_exec_context *ctx, int *ptr, int arg)
 static void atom_op_jump(atom_exec_context *ctx, int *ptr, int arg)
 {
        int execute = 0, target = U16(*ptr);
+        unsigned long cjiffies;
        (*ptr) += 2;
        switch (arg) {
        case ATOM_COND_ABOVE:
@@ -700,8 +710,25 @@ static void atom_op_jump(atom_exec_context *ctx, int *ptr, int arg)
        if (arg != ATOM_COND_ALWAYS)
                SDEBUG("   taken: %s\n", execute ? "yes" : "no");
        SDEBUG("   target: 0x%04X\n", target);
-        if (execute)
+        if (execute) {
+                if (ctx->last_jump == (ctx->start + target)) {
+                        cjiffies = jiffies;
+                        if (time_after(cjiffies, ctx->last_jump_jiffies)) {
+                                cjiffies -= ctx->last_jump_jiffies;
+                                if ((jiffies_to_msecs(cjiffies) > 1000)) {
+                                        DRM_ERROR("atombios stuck in loop for more than 1sec aborting\n");
+                                        ctx->abort = true;
+                                }
+                        } else {
+                                /* jiffies wrap around we will just wait a little longer */
+                                ctx->last_jump_jiffies = jiffies;
+                        }
+                } else {
+                        ctx->last_jump = ctx->start + target;
+                        ctx->last_jump_jiffies = jiffies;
+                }
                *ptr = ctx->start + target;
+        }
 }
 static void atom_op_mask(atom_exec_context *ctx, int *ptr, int arg)
@@ -881,11 +908,16 @@ static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg)
        uint8_t attr = U8((*ptr)++), shift;
        uint32_t saved, dst;
        int dptr = *ptr;
+        uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];
        SDEBUG("   dst: ");
        dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
+        /* op needs to full dst value */
+        dst = saved;
        shift = atom_get_src(ctx, attr, ptr);
        SDEBUG("   shift: %d\n", shift);
        dst <<= shift;
+        dst &= atom_arg_mask[dst_align];
+        dst >>= atom_arg_shift[dst_align];
        SDEBUG("   dst: ");
        atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
 }
@@ -895,11 +927,16 @@ static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg)
        uint8_t attr = U8((*ptr)++), shift;
        uint32_t saved, dst;
        int dptr = *ptr;
+        uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];
        SDEBUG("   dst: ");
        dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
+        /* op needs to full dst value */
+        dst = saved;
        shift = atom_get_src(ctx, attr, ptr);
        SDEBUG("   shift: %d\n", shift);
        dst >>= shift;
+        dst &= atom_arg_mask[dst_align];
+        dst >>= atom_arg_shift[dst_align];
        SDEBUG("   dst: ");
        atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
 }
@@ -1104,15 +1141,16 @@ static struct {
        atom_op_shr, ATOM_ARG_MC}, {
 atom_op_debug, 0},};
-static void atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params)
+static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params)
 {
        int base = CU16(ctx->cmd_table + 4 + 2 * index);
        int len, ws, ps, ptr;
        unsigned char op;
        atom_exec_context ectx;
+        int ret = 0;
        if (!base)
-                return;
+                return -EINVAL;
        len = CU16(base + ATOM_CT_SIZE_PTR);
        ws = CU8(base + ATOM_CT_WS_PTR);
@@ -1125,6 +1163,8 @@ static void atom_execute_table_locked(struct atom_context *ctx, int index, uint3
        ectx.ps_shift = ps / 4;
        ectx.start = base;
        ectx.ps = params;
+        ectx.abort = false;
+        ectx.last_jump = 0;
        if (ws)
                ectx.ws = kzalloc(4 * ws, GFP_KERNEL);
        else
@@ -1137,6 +1177,12 @@ static void atom_execute_table_locked(struct atom_context *ctx, int index, uint3
                        SDEBUG("%s @ 0x%04X\n", atom_op_names[op], ptr - 1);
                else
                        SDEBUG("[%d] @ 0x%04X\n", op, ptr - 1);
+                if (ectx.abort) {
+                        DRM_ERROR("atombios stuck executing %04X (len %d, WS %d, PS %d) @ 0x%04X\n",
+                                base, len, ws, ps, ptr - 1);
+                        ret = -EINVAL;
+                        goto free;
+                }
                if (op < ATOM_OP_CNT && op > 0)
                        opcode_table[op].func(&ectx, &ptr,
@@ -1150,12 +1196,16 @@ static void atom_execute_table_locked(struct atom_context *ctx, int index, uint3
        debug_depth--;
        SDEBUG("<<\n");
+free:
        if (ws)
                kfree(ectx.ws);
+        return ret;
 }
-void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params)
+int atom_execute_table(struct atom_context *ctx, int index, uint32_t * params)
 {
+        int r;
        mutex_lock(&ctx->mutex);
        /* reset reg block */
        ctx->reg_block = 0;
@@ -1163,8 +1213,9 @@ void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params)
        ctx->fb_base = 0;
        /* reset io mode */
        ctx->io_mode = ATOM_IO_MM;
-        atom_execute_table_locked(ctx, index, params);
+        r = atom_execute_table_locked(ctx, index, params);
        mutex_unlock(&ctx->mutex);
+        return r;
 }
 static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 };
@@ -1248,9 +1299,7 @@ int atom_asic_init(struct atom_context *ctx)
        if (!CU16(ctx->cmd_table + 4 + 2 * ATOM_CMD_INIT))
                return 1;
-        atom_execute_table(ctx, ATOM_CMD_INIT, ps);
+        return atom_execute_table(ctx, ATOM_CMD_INIT, ps);
-        return 0;
 }
 void atom_destroy(struct atom_context *ctx)
@@ -1260,12 +1309,16 @@ void atom_destroy(struct atom_context *ctx)
        kfree(ctx);
 }
-void atom_parse_data_header(struct atom_context *ctx, int index,
+bool atom_parse_data_header(struct atom_context *ctx, int index,
                            uint16_t * size, uint8_t * frev, uint8_t * crev,
                            uint16_t * data_start)
 {
        int offset = index * 2 + 4;
        int idx = CU16(ctx->data_table + offset);
+        u16 *mdt = (u16 *)(ctx->bios + ctx->data_table + 4);
+        if (!mdt[index])
+                return false;
        if (size)
                *size = CU16(idx);
@@ -1274,38 +1327,42 @@ void atom_parse_data_header(struct atom_context *ctx, int index,
        if (crev)
                *crev = CU8(idx + 3);
        *data_start = idx;
-        return;
+        return true;
 }
-void atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t * frev,
+bool atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t * frev,
                           uint8_t * crev)
 {
        int offset = index * 2 + 4;
        int idx = CU16(ctx->cmd_table + offset);
+        u16 *mct = (u16 *)(ctx->bios + ctx->cmd_table + 4);
+        if (!mct[index])
+                return false;
        if (frev)
                *frev = CU8(idx + 2);
        if (crev)
                *crev = CU8(idx + 3);
-        return;
+        return true;
 }
 int atom_allocate_fb_scratch(struct atom_context *ctx)
 {
        int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware);
        uint16_t data_offset;
-        int usage_bytes;
+        int usage_bytes = 0;
        struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage;
-        atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
+        if (atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
+                firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset);
-        firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset);
+                DRM_DEBUG("atom firmware requested %08x %dkb\n",
+                          firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware,
+                          firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb);
-        DRM_DEBUG("atom firmware requested %08x %dkb\n",
+                usage_bytes = firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb * 1024;
-                  firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware,
+        }
-                  firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb);
-        usage_bytes = firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb * 1024;
        if (usage_bytes == 0)
                usage_bytes = 20 * 1024;
        /* allocate some scratch memory */
diff --git a/drivers/gpu/drm/radeon/atom.h b/drivers/gpu/drm/radeon/atom.h
index bc73781423a1..cd1b64ab5ca7 100644
--- a/drivers/gpu/drm/radeon/atom.h
+++ b/drivers/gpu/drm/radeon/atom.h
@@ -140,11 +140,13 @@ struct atom_context {
 extern int atom_debug;
 struct atom_context *atom_parse(struct card_info *, void *);
-void atom_execute_table(struct atom_context *, int, uint32_t *);
+int atom_execute_table(struct atom_context *, int, uint32_t *);
 int atom_asic_init(struct atom_context *);
 void atom_destroy(struct atom_context *);
-void atom_parse_data_header(struct atom_context *ctx, int index, uint16_t *size, uint8_t *frev, uint8_t *crev, uint16_t *data_start);
+bool atom_parse_data_header(struct atom_context *ctx, int index, uint16_t *size,
-void atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t *frev, uint8_t *crev);
+                            uint8_t *frev, uint8_t *crev, uint16_t *data_start);
+bool atom_parse_cmd_header(struct atom_context *ctx, int index,
+                           uint8_t *frev, uint8_t *crev);
 int atom_allocate_fb_scratch(struct atom_context *ctx);
 #include "atom-types.h"
 #include "atombios.h"
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index dd9fdf560611..a87990b3ae84 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -353,12 +353,55 @@ static void atombios_crtc_set_timing(struct drm_crtc *crtc,
        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 }
+static void atombios_disable_ss(struct drm_crtc *crtc)
+{
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+        struct drm_device *dev = crtc->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        u32 ss_cntl;
+        if (ASIC_IS_DCE4(rdev)) {
+                switch (radeon_crtc->pll_id) {
+                case ATOM_PPLL1:
+                        ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
+                        ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
+                        WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
+                        break;
+                case ATOM_PPLL2:
+                        ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
+                        ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
+                        WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
+                        break;
+                case ATOM_DCPLL:
+                case ATOM_PPLL_INVALID:
+                        return;
+                }
+        } else if (ASIC_IS_AVIVO(rdev)) {
+                switch (radeon_crtc->pll_id) {
+                case ATOM_PPLL1:
+                        ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
+                        ss_cntl &= ~1;
+                        WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
+                        break;
+                case ATOM_PPLL2:
+                        ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
+                        ss_cntl &= ~1;
+                        WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
+                        break;
+                case ATOM_DCPLL:
+                case ATOM_PPLL_INVALID:
+                        return;
+                }
+        }
+}
 union atom_enable_ss {
        ENABLE_LVDS_SS_PARAMETERS legacy;
        ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
 };
-static void atombios_set_ss(struct drm_crtc *crtc, int enable)
+static void atombios_enable_ss(struct drm_crtc *crtc)
 {
        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
        struct drm_device *dev = crtc->dev;
@@ -387,9 +430,9 @@ static void atombios_set_ss(struct drm_crtc *crtc, int enable)
                                        step = dig->ss->step;
                                        delay = dig->ss->delay;
                                        range = dig->ss->range;
-                                } else if (enable)
+                                } else
                                        return;
-                        } else if (enable)
+                        } else
                                return;
                        break;
                }
@@ -406,13 +449,13 @@ static void atombios_set_ss(struct drm_crtc *crtc, int enable)
                args.v1.ucSpreadSpectrumDelay = delay;
                args.v1.ucSpreadSpectrumRange = range;
                args.v1.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
-                args.v1.ucEnable = enable;
+                args.v1.ucEnable = ATOM_ENABLE;
        } else {
                args.legacy.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
                args.legacy.ucSpreadSpectrumType = type;
                args.legacy.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2;
                args.legacy.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4;
-                args.legacy.ucEnable = enable;
+                args.legacy.ucEnable = ATOM_ENABLE;
        }
        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 }
@@ -478,10 +521,9 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
                                /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
                                if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
                                        adjusted_clock = mode->clock * 2;
-                                /* LVDS PLL quirks */
+                                if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
-                                if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
+                                        pll->algo = PLL_ALGO_LEGACY;
-                                        struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
+                                        pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
-                                        pll->algo = dig->pll_algo;
                                }
                        } else {
                                if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
@@ -503,8 +545,9 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
                int index;
                index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
-                atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
+                if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
-                                      &crev);
+                                           &crev))
+                        return adjusted_clock;
                memset(&args, 0, sizeof(args));
@@ -542,11 +585,16 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
                                        }
                                } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
                                        /* may want to enable SS on DP/eDP eventually */
-                                        args.v3.sInput.ucDispPllConfig |=
+                                        /*args.v3.sInput.ucDispPllConfig |=
-                                                DISPPLL_CONFIG_SS_ENABLE;
+                                                DISPPLL_CONFIG_SS_ENABLE;*/
-                                        if (mode->clock > 165000)
+                                        if (encoder_mode == ATOM_ENCODER_MODE_DP)
                                                args.v3.sInput.ucDispPllConfig |=
-                                                        DISPPLL_CONFIG_DUAL_LINK;
+                                                        DISPPLL_CONFIG_COHERENT_MODE;
+                                        else {
+                                                if (mode->clock > 165000)
+                                                        args.v3.sInput.ucDispPllConfig |=
+                                                                DISPPLL_CONFIG_DUAL_LINK;
+                                        }
                                }
                                atom_execute_table(rdev->mode_info.atom_context,
                                                   index, (uint32_t *)&args);
@@ -592,8 +640,9 @@ static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)
        memset(&args, 0, sizeof(args));
        index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
-        atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
+        if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
-                              &crev);
+                                   &crev))
+                return;
        switch (frev) {
        case 1:
@@ -667,8 +716,9 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
                           &ref_div, &post_div);
        index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
-        atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
+        if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
-                              &crev);
+                                   &crev))
+                return;
        switch (frev) {
        case 1:
@@ -1083,15 +1133,12 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
        /* TODO color tiling */
-        /* pick pll */
+        atombios_disable_ss(crtc);
-        radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
-        atombios_set_ss(crtc, 0);
        /* always set DCPLL */
        if (ASIC_IS_DCE4(rdev))
                atombios_crtc_set_dcpll(crtc);
        atombios_crtc_set_pll(crtc, adjusted_mode);
-        atombios_set_ss(crtc, 1);
+        atombios_enable_ss(crtc);
        if (ASIC_IS_DCE4(rdev))
                atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
@@ -1120,6 +1167,11 @@ static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
 static void atombios_crtc_prepare(struct drm_crtc *crtc)
 {
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+        /* pick pll */
+        radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
        atombios_lock_crtc(crtc, ATOM_ENABLE);
        atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 }
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 8a133bda00a2..28b31c64f48d 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -745,14 +745,14 @@ void dp_link_train(struct drm_encoder *encoder,
                          >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
        /* disable the training pattern on the sink */
+        dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE);
+        /* disable the training pattern on the source */
        if (ASIC_IS_DCE4(rdev))
                atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE);
        else
                radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
                                          dig_connector->dp_clock, enc_id, 0);
-        radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
-                                  dig_connector->dp_clock, enc_id, 0);
 }
 int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index bd2e7aa85c1d..e8f447e20507 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -23,8 +23,10 @@
 */
 #include <linux/firmware.h>
 #include <linux/platform_device.h>
+#include <linux/slab.h>
 #include "drmP.h"
 #include "radeon.h"
+#include "radeon_asic.h"
 #include "radeon_drm.h"
 #include "rv770d.h"
 #include "atom.h"
@@ -436,7 +438,6 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
 int evergreen_mc_init(struct radeon_device *rdev)
 {
-        fixed20_12 a;
        u32 tmp;
        int chansize, numchan;
@@ -481,12 +482,8 @@ int evergreen_mc_init(struct radeon_device *rdev)
                rdev->mc.real_vram_size = rdev->mc.aper_size;
        }
        r600_vram_gtt_location(rdev, &rdev->mc);
-        /* FIXME: we should enforce default clock in case GPU is not in
+        radeon_update_bandwidth_info(rdev);
-         * default setup
-         */
-        a.full = rfixed_const(100);
-        rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
-        rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
        return 0;
 }
@@ -746,6 +743,7 @@ int evergreen_init(struct radeon_device *rdev)
 void evergreen_fini(struct radeon_device *rdev)
 {
+        radeon_pm_fini(rdev);
        evergreen_suspend(rdev);
 #if 0
        r600_blit_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 91eb762eb3f9..d7388fdb6d0b 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -26,11 +26,13 @@
 *          Jerome Glisse
 */
 #include <linux/seq_file.h>
+#include <linux/slab.h>
 #include "drmP.h"
 #include "drm.h"
 #include "radeon_drm.h"
 #include "radeon_reg.h"
 #include "radeon.h"
+#include "radeon_asic.h"
 #include "r100d.h"
 #include "rs100d.h"
 #include "rv200d.h"
@@ -235,9 +237,9 @@ int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 void r100_pci_gart_fini(struct radeon_device *rdev)
 {
+        radeon_gart_fini(rdev);
        r100_pci_gart_disable(rdev);
        radeon_gart_table_ram_free(rdev);
-        radeon_gart_fini(rdev);
 }
 int r100_irq_set(struct radeon_device *rdev)
@@ -312,10 +314,12 @@ int r100_irq_process(struct radeon_device *rdev)
                /* Vertical blank interrupts */
                if (status & RADEON_CRTC_VBLANK_STAT) {
                        drm_handle_vblank(rdev->ddev, 0);
+                        rdev->pm.vblank_sync = true;
                        wake_up(&rdev->irq.vblank_queue);
                }
                if (status & RADEON_CRTC2_VBLANK_STAT) {
                        drm_handle_vblank(rdev->ddev, 1);
+                        rdev->pm.vblank_sync = true;
                        wake_up(&rdev->irq.vblank_queue);
                }
                if (status & RADEON_FP_DETECT_STAT) {
@@ -741,6 +745,8 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
        udelay(10);
        rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
        rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
+        /* protect against crazy HW on resume */
+        rdev->cp.wptr &= rdev->cp.ptr_mask;
        /* Set cp mode to bus mastering & enable cp*/
        WREG32(RADEON_CP_CSQ_MODE,
               REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
@@ -1804,6 +1810,7 @@ void r100_set_common_regs(struct radeon_device *rdev)
 {
        struct drm_device *dev = rdev->ddev;
        bool force_dac2 = false;
+        u32 tmp;
        /* set these so they don't interfere with anything */
        WREG32(RADEON_OV0_SCALE_CNTL, 0);
@@ -1875,6 +1882,12 @@ void r100_set_common_regs(struct radeon_device *rdev)
                WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
                WREG32(RADEON_DAC_CNTL2, dac2_cntl);
        }
+        /* switch PM block to ACPI mode */
+        tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
+        tmp &= ~RADEON_PM_MODE_SEL;
+        WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
 }
 /*
@@ -2022,6 +2035,7 @@ void r100_mc_init(struct radeon_device *rdev)
        radeon_vram_location(rdev, &rdev->mc, base);
        if (!(rdev->flags & RADEON_IS_AGP))
                radeon_gtt_location(rdev, &rdev->mc);
+        radeon_update_bandwidth_info(rdev);
 }
@@ -2385,6 +2399,8 @@ void r100_bandwidth_update(struct radeon_device *rdev)
        uint32_t pixel_bytes1 = 0;
        uint32_t pixel_bytes2 = 0;
+        radeon_update_display_priority(rdev);
        if (rdev->mode_info.crtcs[0]->base.enabled) {
                mode1 = &rdev->mode_info.crtcs[0]->base.mode;
                pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
@@ -2413,11 +2429,8 @@ void r100_bandwidth_update(struct radeon_device *rdev)
        /*
         * determine is there is enough bw for current mode
         */
-        mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
+        sclk_ff = rdev->pm.sclk;
-        temp_ff.full = rfixed_const(100);
+        mclk_ff = rdev->pm.mclk;
-        mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
-        sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
-        sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
        temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
        temp_ff.full = rfixed_const(temp);
@@ -2878,7 +2891,7 @@ static int r100_cs_track_texture_check(struct radeon_device *rdev,
 {
        struct radeon_bo *robj;
        unsigned long size;
-        unsigned u, i, w, h;
+        unsigned u, i, w, h, d;
        int ret;
        for (u = 0; u < track->num_texture; u++) {
@@ -2910,20 +2923,25 @@ static int r100_cs_track_texture_check(struct radeon_device *rdev,
                        h = h / (1 << i);
                        if (track->textures[u].roundup_h)
                                h = roundup_pow_of_two(h);
+                        if (track->textures[u].tex_coord_type == 1) {
+                                d = (1 << track->textures[u].txdepth) / (1 << i);
+                                if (!d)
+                                        d = 1;
+                        } else {
+                                d = 1;
+                        }
                        if (track->textures[u].compress_format) {
-                                size += r100_track_compress_size(track->textures[u].compress_format, w, h);
+                                size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
                                /* compressed textures are block based */
                        } else
-                                size += w * h;
+                                size += w * h * d;
                }
                size *= track->textures[u].cpp;
                switch (track->textures[u].tex_coord_type) {
                case 0:
-                        break;
                case 1:
-                        size *= (1 << track->textures[u].txdepth);
                        break;
                case 2:
                        if (track->separate_cube) {
@@ -2994,7 +3012,11 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
                }
        }
        prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
-        nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
+        if (track->vap_vf_cntl & (1 << 14)) {
+                nverts = track->vap_alt_nverts;
+        } else {
+                nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
+        }
        switch (prim_walk) {
        case 1:
                for (i = 0; i < track->num_arrays; i++) {
@@ -3440,6 +3462,7 @@ int r100_suspend(struct radeon_device *rdev)
 void r100_fini(struct radeon_device *rdev)
 {
+        radeon_pm_fini(rdev);
        r100_cp_fini(rdev);
        r100_wb_fini(rdev);
        r100_ib_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/r100_track.h b/drivers/gpu/drm/radeon/r100_track.h
index b27a6999d219..fadfe68de9cc 100644
--- a/drivers/gpu/drm/radeon/r100_track.h
+++ b/drivers/gpu/drm/radeon/r100_track.h
@@ -64,6 +64,7 @@ struct r100_cs_track {
        unsigned                        maxy;
        unsigned                        vtx_size;
        unsigned                        vap_vf_cntl;
+        unsigned                        vap_alt_nverts;
        unsigned                        immd_dwords;
        unsigned                        num_arrays;
        unsigned                        max_indx;
diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c
index 1146c9909c2c..85617c311212 100644
--- a/drivers/gpu/drm/radeon/r200.c
+++ b/drivers/gpu/drm/radeon/r200.c
@@ -30,6 +30,7 @@
 #include "radeon_drm.h"
 #include "radeon_reg.h"
 #include "radeon.h"
+#include "radeon_asic.h"
 #include "r100d.h"
 #include "r200_reg_safe.h"
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 4cef90cd74e5..bd75f99bd65e 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -26,10 +26,12 @@
 *          Jerome Glisse
 */
 #include <linux/seq_file.h>
+#include <linux/slab.h>
 #include "drmP.h"
 #include "drm.h"
 #include "radeon_reg.h"
 #include "radeon.h"
+#include "radeon_asic.h"
 #include "radeon_drm.h"
 #include "r100_track.h"
 #include "r300d.h"
@@ -164,9 +166,9 @@ void rv370_pcie_gart_disable(struct radeon_device *rdev)
 void rv370_pcie_gart_fini(struct radeon_device *rdev)
 {
+        radeon_gart_fini(rdev);
        rv370_pcie_gart_disable(rdev);
        radeon_gart_table_vram_free(rdev);
-        radeon_gart_fini(rdev);
 }
 void r300_fence_ring_emit(struct radeon_device *rdev,
@@ -323,11 +325,12 @@ void r300_gpu_init(struct radeon_device *rdev)
        r100_hdp_reset(rdev);
        /* FIXME: rv380 one pipes ? */
-        if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) {
+        if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
+            (rdev->family == CHIP_R350)) {
                /* r300,r350 */
                rdev->num_gb_pipes = 2;
        } else {
-                /* rv350,rv370,rv380 */
+                /* rv350,rv370,rv380,r300 AD */
                rdev->num_gb_pipes = 1;
        }
        rdev->num_z_pipes = 1;
@@ -481,6 +484,7 @@ void r300_mc_init(struct radeon_device *rdev)
        radeon_vram_location(rdev, &rdev->mc, base);
        if (!(rdev->flags & RADEON_IS_AGP))
                radeon_gtt_location(rdev, &rdev->mc);
+        radeon_update_bandwidth_info(rdev);
 }
 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
@@ -726,6 +730,12 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                /* VAP_VF_MAX_VTX_INDX */
                track->max_indx = idx_value & 0x00FFFFFFUL;
                break;
+        case 0x2088:
+                /* VAP_ALT_NUM_VERTICES - only valid on r500 */
+                if (p->rdev->family < CHIP_RV515)
+                        goto fail;
+                track->vap_alt_nverts = idx_value & 0xFFFFFF;
+                break;
        case 0x43E4:
                /* SC_SCISSOR1 */
                track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
@@ -763,7 +773,6 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                tmp = idx_value & ~(0x7 << 16);
                tmp |= tile_flags;
                ib[idx] = tmp;
                i = (reg - 0x4E38) >> 2;
                track->cb[i].pitch = idx_value & 0x3FFE;
                switch (((idx_value >> 21) & 0xF)) {
@@ -1048,11 +1057,13 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                        break;
                /* fallthrough do not move */
        default:
-                printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
+                goto fail;
-                       reg, idx);
-                return -EINVAL;
        }
        return 0;
+fail:
+        printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
+               reg, idx);
+        return -EINVAL;
 }
 static int r300_packet3_check(struct radeon_cs_parser *p,
@@ -1334,6 +1345,7 @@ int r300_suspend(struct radeon_device *rdev)
 void r300_fini(struct radeon_device *rdev)
 {
+        radeon_pm_fini(rdev);
        r100_cp_fini(rdev);
        r100_wb_fini(rdev);
        r100_ib_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index c7593b8f58ee..3dc968c9f5a4 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -26,9 +26,11 @@
 *          Jerome Glisse
 */
 #include <linux/seq_file.h>
+#include <linux/slab.h>
 #include "drmP.h"
 #include "radeon_reg.h"
 #include "radeon.h"
+#include "radeon_asic.h"
 #include "atom.h"
 #include "r100d.h"
 #include "r420d.h"
@@ -266,6 +268,7 @@ int r420_suspend(struct radeon_device *rdev)
 void r420_fini(struct radeon_device *rdev)
 {
+        radeon_pm_fini(rdev);
        r100_cp_fini(rdev);
        r100_wb_fini(rdev);
        r100_ib_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index 2b8a5dd13516..3c44b8d39318 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -27,6 +27,7 @@
 */
 #include "drmP.h"
 #include "radeon.h"
+#include "radeon_asic.h"
 #include "atom.h"
 #include "r520d.h"
@@ -121,19 +122,13 @@ static void r520_vram_get_type(struct radeon_device *rdev)
 void r520_mc_init(struct radeon_device *rdev)
 {
-        fixed20_12 a;
        r520_vram_get_type(rdev);
        r100_vram_init_sizes(rdev);
        radeon_vram_location(rdev, &rdev->mc, 0);
        if (!(rdev->flags & RADEON_IS_AGP))
                radeon_gtt_location(rdev, &rdev->mc);
-        /* FIXME: we should enforce default clock in case GPU is not in
+        radeon_update_bandwidth_info(rdev);
-         * default setup
-         */
-        a.full = rfixed_const(100);
-        rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
-        rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
 }
 void r520_mc_program(struct radeon_device *rdev)
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index c52290197292..8f3454e2056a 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -25,12 +25,14 @@
 *          Alex Deucher
 *          Jerome Glisse
 */
+#include <linux/slab.h>
 #include <linux/seq_file.h>
 #include <linux/firmware.h>
 #include <linux/platform_device.h>
 #include "drmP.h"
 #include "radeon_drm.h"
 #include "radeon.h"
+#include "radeon_asic.h"
 #include "radeon_mode.h"
 #include "r600d.h"
 #include "atom.h"
@@ -491,9 +493,9 @@ void r600_pcie_gart_disable(struct radeon_device *rdev)
 void r600_pcie_gart_fini(struct radeon_device *rdev)
 {
+        radeon_gart_fini(rdev);
        r600_pcie_gart_disable(rdev);
        radeon_gart_table_vram_free(rdev);
-        radeon_gart_fini(rdev);
 }
 void r600_agp_enable(struct radeon_device *rdev)
@@ -675,7 +677,6 @@ void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
 int r600_mc_init(struct radeon_device *rdev)
 {
-        fixed20_12 a;
        u32 tmp;
        int chansize, numchan;
@@ -719,14 +720,10 @@ int r600_mc_init(struct radeon_device *rdev)
                rdev->mc.real_vram_size = rdev->mc.aper_size;
        }
        r600_vram_gtt_location(rdev, &rdev->mc);
-        /* FIXME: we should enforce default clock in case GPU is not in
-         * default setup
-         */
-        a.full = rfixed_const(100);
-        rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
-        rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
        if (rdev->flags & RADEON_IS_IGP)
                rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
+        radeon_update_bandwidth_info(rdev);
        return 0;
 }
@@ -1132,6 +1129,7 @@ void r600_gpu_init(struct radeon_device *rdev)
        /* Setup pipes */
        WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
        WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
+        WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
        tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
        WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
@@ -2119,6 +2117,7 @@ int r600_init(struct radeon_device *rdev)
 void r600_fini(struct radeon_device *rdev)
 {
+        radeon_pm_fini(rdev);
        r600_audio_fini(rdev);
        r600_blit_fini(rdev);
        r600_cp_fini(rdev);
@@ -2398,19 +2397,19 @@ static void r600_disable_interrupt_state(struct radeon_device *rdev)
                WREG32(DC_HPD4_INT_CONTROL, tmp);
                if (ASIC_IS_DCE32(rdev)) {
                        tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
-                        WREG32(DC_HPD5_INT_CONTROL, 0);
+                        WREG32(DC_HPD5_INT_CONTROL, tmp);
                        tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
-                        WREG32(DC_HPD6_INT_CONTROL, 0);
+                        WREG32(DC_HPD6_INT_CONTROL, tmp);
                }
        } else {
                WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
                WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
                tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
-                WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, 0);
+                WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
                tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
-                WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, 0);
+                WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
                tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
-                WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, 0);
+                WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
        }
 }
@@ -2765,6 +2764,7 @@ restart_ih:
                        case 0: /* D1 vblank */
                                if (disp_int & LB_D1_VBLANK_INTERRUPT) {
                                        drm_handle_vblank(rdev->ddev, 0);
+                                        rdev->pm.vblank_sync = true;
                                        wake_up(&rdev->irq.vblank_queue);
                                        disp_int &= ~LB_D1_VBLANK_INTERRUPT;
                                        DRM_DEBUG("IH: D1 vblank\n");
@@ -2786,6 +2786,7 @@ restart_ih:
                        case 0: /* D2 vblank */
                                if (disp_int & LB_D2_VBLANK_INTERRUPT) {
                                        drm_handle_vblank(rdev->ddev, 1);
+                                        rdev->pm.vblank_sync = true;
                                        wake_up(&rdev->irq.vblank_queue);
                                        disp_int &= ~LB_D2_VBLANK_INTERRUPT;
                                        DRM_DEBUG("IH: D2 vblank\n");
@@ -2834,14 +2835,14 @@ restart_ih:
                                break;
                        case 10:
                                if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
-                                        disp_int_cont &= ~DC_HPD5_INTERRUPT;
+                                        disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
                                        queue_hotplug = true;
                                        DRM_DEBUG("IH: HPD5\n");
                                }
                                break;
                        case 12:
                                if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
-                                        disp_int_cont &= ~DC_HPD6_INTERRUPT;
+                                        disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
                                        queue_hotplug = true;
                                        DRM_DEBUG("IH: HPD6\n");
                                }
diff --git a/drivers/gpu/drm/radeon/r600_audio.c b/drivers/gpu/drm/radeon/r600_audio.c
index db928016d034..1d898051c631 100644
--- a/drivers/gpu/drm/radeon/r600_audio.c
+++ b/drivers/gpu/drm/radeon/r600_audio.c
@@ -35,7 +35,7 @@
 */
 static int r600_audio_chipset_supported(struct radeon_device *rdev)
 {
-        return rdev->family >= CHIP_R600
+        return (rdev->family >= CHIP_R600 && rdev->family < CHIP_CEDAR)
                || rdev->family == CHIP_RS600
                || rdev->family == CHIP_RS690
                || rdev->family == CHIP_RS740;
@@ -182,41 +182,6 @@ int r600_audio_init(struct radeon_device *rdev)
 }
 /*
- * determin how the encoders and audio interface is wired together
- */
-int r600_audio_tmds_index(struct drm_encoder *encoder)
-{
-        struct drm_device *dev = encoder->dev;
-        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
-        struct drm_encoder *other;
-        switch (radeon_encoder->encoder_id) {
-        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
-        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
-        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
-                return 0;
-        case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
-                /* special case check if an TMDS1 is present */
-                list_for_each_entry(other, &dev->mode_config.encoder_list, head) {
-                        if (to_radeon_encoder(other)->encoder_id ==
-                                ENCODER_OBJECT_ID_INTERNAL_TMDS1)
-                                return 1;
-                }
-                return 0;
-        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
-        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
-                return 1;
-        default:
-                DRM_ERROR("Unsupported encoder type 0x%02X\n",
-                          radeon_encoder->encoder_id);
-                return -1;
-        }
-}
-/*
 * atach the audio codec to the clock source of the encoder
 */
 void r600_audio_set_clock(struct drm_encoder *encoder, int clock)
@@ -224,6 +189,7 @@ void r600_audio_set_clock(struct drm_encoder *encoder, int clock)
        struct drm_device *dev = encoder->dev;
        struct radeon_device *rdev = dev->dev_private;
        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
        int base_rate = 48000;
        switch (radeon_encoder->encoder_id) {
@@ -231,32 +197,34 @@ void r600_audio_set_clock(struct drm_encoder *encoder, int clock)
        case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
                WREG32_P(R600_AUDIO_TIMING, 0, ~0x301);
                break;
        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
                WREG32_P(R600_AUDIO_TIMING, 0x100, ~0x301);
                break;
        default:
                DRM_ERROR("Unsupported encoder type 0x%02X\n",
                          radeon_encoder->encoder_id);
                return;
        }
-        switch (r600_audio_tmds_index(encoder)) {
+        switch (dig->dig_encoder) {
        case 0:
-                WREG32(R600_AUDIO_PLL1_MUL, base_rate*50);
+                WREG32(R600_AUDIO_PLL1_MUL, base_rate * 50);
-                WREG32(R600_AUDIO_PLL1_DIV, clock*100);
+                WREG32(R600_AUDIO_PLL1_DIV, clock * 100);
                WREG32(R600_AUDIO_CLK_SRCSEL, 0);
                break;
        case 1:
-                WREG32(R600_AUDIO_PLL2_MUL, base_rate*50);
+                WREG32(R600_AUDIO_PLL2_MUL, base_rate * 50);
-                WREG32(R600_AUDIO_PLL2_DIV, clock*100);
+                WREG32(R600_AUDIO_PLL2_DIV, clock * 100);
                WREG32(R600_AUDIO_CLK_SRCSEL, 1);
                break;
+        default:
+                dev_err(rdev->dev, "Unsupported DIG on encoder 0x%02X\n",
+                          radeon_encoder->encoder_id);
+                return;
        }
 }
diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.c b/drivers/gpu/drm/radeon/r600_blit_shaders.c
index a112c59f9d82..0271b53fa2dd 100644
--- a/drivers/gpu/drm/radeon/r600_blit_shaders.c
+++ b/drivers/gpu/drm/radeon/r600_blit_shaders.c
@@ -1,7 +1,42 @@
+/*
+ * Copyright 2009 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *     Alex Deucher <alexander.deucher@amd.com>
+ */
 #include <linux/types.h>
 #include <linux/kernel.h>
+/*
+ * R6xx+ cards need to use the 3D engine to blit data which requires
+ * quite a bit of hw state setup.  Rather than pull the whole 3D driver
+ * (which normally generates the 3D state) into the DRM, we opt to use
+ * statically generated state tables.  The regsiter state and shaders
+ * were hand generated to support blitting functionality.  See the 3D
+ * driver or documentation for descriptions of the registers and
+ * shader instructions.
+ */
 const u32 r6xx_default_state[] =
 {
        0xc0002400,
diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c
index 40416c068d9f..68e6f4349309 100644
--- a/drivers/gpu/drm/radeon/r600_cp.c
+++ b/drivers/gpu/drm/radeon/r600_cp.c
@@ -1548,10 +1548,13 @@ static void r700_gfx_init(struct drm_device *dev,
        RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
        RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
+        RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
        RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
        RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0);
        RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0);
+        RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0);
+        RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0);
        num_qd_pipes =
                R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8);
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index cd2c63bce501..c39c1bc13016 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -45,6 +45,7 @@ struct r600_cs_track {
        u32                     nbanks;
        u32                     npipes;
        /* value we track */
+        u32                     sq_config;
        u32                     nsamples;
        u32                     cb_color_base_last[8];
        struct radeon_bo        *cb_color_bo[8];
@@ -141,6 +142,8 @@ static void r600_cs_track_init(struct r600_cs_track *track)
 {
        int i;
+        /* assume DX9 mode */
+        track->sq_config = DX9_CONSTS;
        for (i = 0; i < 8; i++) {
                track->cb_color_base_last[i] = 0;
                track->cb_color_size[i] = 0;
@@ -715,6 +718,9 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
                tmp =radeon_get_ib_value(p, idx);
                ib[idx] = 0;
                break;
+        case SQ_CONFIG:
+                track->sq_config = radeon_get_ib_value(p, idx);
+                break;
        case R_028800_DB_DEPTH_CONTROL:
                track->db_depth_control = radeon_get_ib_value(p, idx);
                break;
@@ -869,6 +875,54 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
        case SQ_PGM_START_VS:
        case SQ_PGM_START_GS:
        case SQ_PGM_START_PS:
+        case SQ_ALU_CONST_CACHE_GS_0:
+        case SQ_ALU_CONST_CACHE_GS_1:
+        case SQ_ALU_CONST_CACHE_GS_2:
+        case SQ_ALU_CONST_CACHE_GS_3:
+        case SQ_ALU_CONST_CACHE_GS_4:
+        case SQ_ALU_CONST_CACHE_GS_5:
+        case SQ_ALU_CONST_CACHE_GS_6:
+        case SQ_ALU_CONST_CACHE_GS_7:
+        case SQ_ALU_CONST_CACHE_GS_8:
+        case SQ_ALU_CONST_CACHE_GS_9:
+        case SQ_ALU_CONST_CACHE_GS_10:
+        case SQ_ALU_CONST_CACHE_GS_11:
+        case SQ_ALU_CONST_CACHE_GS_12:
+        case SQ_ALU_CONST_CACHE_GS_13:
+        case SQ_ALU_CONST_CACHE_GS_14:
+        case SQ_ALU_CONST_CACHE_GS_15:
+        case SQ_ALU_CONST_CACHE_PS_0:
+        case SQ_ALU_CONST_CACHE_PS_1:
+        case SQ_ALU_CONST_CACHE_PS_2:
+        case SQ_ALU_CONST_CACHE_PS_3:
+        case SQ_ALU_CONST_CACHE_PS_4:
+        case SQ_ALU_CONST_CACHE_PS_5:
+        case SQ_ALU_CONST_CACHE_PS_6:
+        case SQ_ALU_CONST_CACHE_PS_7:
+        case SQ_ALU_CONST_CACHE_PS_8:
+        case SQ_ALU_CONST_CACHE_PS_9:
+        case SQ_ALU_CONST_CACHE_PS_10:
+        case SQ_ALU_CONST_CACHE_PS_11:
+        case SQ_ALU_CONST_CACHE_PS_12:
+        case SQ_ALU_CONST_CACHE_PS_13:
+        case SQ_ALU_CONST_CACHE_PS_14:
+        case SQ_ALU_CONST_CACHE_PS_15:
+        case SQ_ALU_CONST_CACHE_VS_0:
+        case SQ_ALU_CONST_CACHE_VS_1:
+        case SQ_ALU_CONST_CACHE_VS_2:
+        case SQ_ALU_CONST_CACHE_VS_3:
+        case SQ_ALU_CONST_CACHE_VS_4:
+        case SQ_ALU_CONST_CACHE_VS_5:
+        case SQ_ALU_CONST_CACHE_VS_6:
+        case SQ_ALU_CONST_CACHE_VS_7:
+        case SQ_ALU_CONST_CACHE_VS_8:
+        case SQ_ALU_CONST_CACHE_VS_9:
+        case SQ_ALU_CONST_CACHE_VS_10:
+        case SQ_ALU_CONST_CACHE_VS_11:
+        case SQ_ALU_CONST_CACHE_VS_12:
+        case SQ_ALU_CONST_CACHE_VS_13:
+        case SQ_ALU_CONST_CACHE_VS_14:
+        case SQ_ALU_CONST_CACHE_VS_15:
                r = r600_cs_packet_next_reloc(p, &reloc);
                if (r) {
                        dev_warn(p->dev, "bad SET_CONTEXT_REG "
@@ -1226,13 +1280,15 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                }
                break;
        case PACKET3_SET_ALU_CONST:
-                start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
+                if (track->sq_config & DX9_CONSTS) {
-                end_reg = 4 * pkt->count + start_reg - 4;
+                        start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
-                if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
+                        end_reg = 4 * pkt->count + start_reg - 4;
-                    (start_reg >= PACKET3_SET_ALU_CONST_END) ||
+                        if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
-                    (end_reg >= PACKET3_SET_ALU_CONST_END)) {
+                            (start_reg >= PACKET3_SET_ALU_CONST_END) ||
-                        DRM_ERROR("bad SET_ALU_CONST\n");
+                            (end_reg >= PACKET3_SET_ALU_CONST_END)) {
-                        return -EINVAL;
+                                DRM_ERROR("bad SET_ALU_CONST\n");
+                                return -EINVAL;
+                        }
                }
                break;
        case PACKET3_SET_BOOL_CONST:
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index fcc949df0e5d..2616b822ba68 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -42,13 +42,13 @@ enum r600_hdmi_color_format {
 */
 enum r600_hdmi_iec_status_bits {
        AUDIO_STATUS_DIG_ENABLE   = 0x01,
-        AUDIO_STATUS_V      = 0x02,
+        AUDIO_STATUS_V            = 0x02,
-        AUDIO_STATUS_VCFG        = 0x04,
+        AUDIO_STATUS_VCFG         = 0x04,
        AUDIO_STATUS_EMPHASIS     = 0x08,
        AUDIO_STATUS_COPYRIGHT    = 0x10,
        AUDIO_STATUS_NONAUDIO     = 0x20,
        AUDIO_STATUS_PROFESSIONAL = 0x40,
-        AUDIO_STATUS_LEVEL      = 0x80
+        AUDIO_STATUS_LEVEL        = 0x80
 };
 struct {
@@ -85,7 +85,7 @@ struct {
 static void r600_hdmi_calc_CTS(uint32_t clock, int *CTS, int N, int freq)
 {
        if (*CTS == 0)
-                *CTS = clock*N/(128*freq)*1000;
+                *CTS = clock * N / (128 * freq) * 1000;
        DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n",
                  N, *CTS, freq);
 }
@@ -131,11 +131,11 @@ static void r600_hdmi_infoframe_checksum(uint8_t packetType,
                                         uint8_t length,
                                         uint8_t *frame)
 {
-    int i;
+        int i;
-    frame[0] = packetType + versionNumber + length;
+        frame[0] = packetType + versionNumber + length;
-    for (i = 1; i <= length; i++)
+        for (i = 1; i <= length; i++)
-        frame[0] += frame[i];
+                frame[0] += frame[i];
-    frame[0] = 0x100 - frame[0];
+        frame[0] = 0x100 - frame[0];
 }
 /*
@@ -314,6 +314,9 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
        struct radeon_device *rdev = dev->dev_private;
        uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
+        if (ASIC_IS_DCE4(rdev))
+                return;
        if (!offset)
                return;
@@ -417,90 +420,147 @@ void r600_hdmi_update_audio_settings(struct drm_encoder *encoder,
        WREG32_P(offset+R600_HDMI_CNTL, 0x04000000, ~0x04000000);
 }
-/*
+static int r600_hdmi_find_free_block(struct drm_device *dev)
- * enable/disable the HDMI engine
+{
- */
+        struct radeon_device *rdev = dev->dev_private;
-void r600_hdmi_enable(struct drm_encoder *encoder, int enable)
+        struct drm_encoder *encoder;
+        struct radeon_encoder *radeon_encoder;
+        bool free_blocks[3] = { true, true, true };
+        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+                radeon_encoder = to_radeon_encoder(encoder);
+                switch (radeon_encoder->hdmi_offset) {
+                case R600_HDMI_BLOCK1:
+                        free_blocks[0] = false;
+                        break;
+                case R600_HDMI_BLOCK2:
+                        free_blocks[1] = false;
+                        break;
+                case R600_HDMI_BLOCK3:
+                        free_blocks[2] = false;
+                        break;
+                }
+        }
+        if (rdev->family == CHIP_RS600 || rdev->family == CHIP_RS690) {
+                return free_blocks[0] ? R600_HDMI_BLOCK1 : 0;
+        } else if (rdev->family >= CHIP_R600) {
+                if (free_blocks[0])
+                        return R600_HDMI_BLOCK1;
+                else if (free_blocks[1])
+                        return R600_HDMI_BLOCK2;
+        }
+        return 0;
+}
+static void r600_hdmi_assign_block(struct drm_encoder *encoder)
 {
        struct drm_device *dev = encoder->dev;
        struct radeon_device *rdev = dev->dev_private;
        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
-        uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
+        struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
-        if (!offset)
+        if (!dig) {
+                dev_err(rdev->dev, "Enabling HDMI on non-dig encoder\n");
                return;
+        }
-        DRM_DEBUG("%s HDMI interface @ 0x%04X\n", enable ? "Enabling" : "Disabling", offset);
+        if (ASIC_IS_DCE4(rdev)) {
+                /* TODO */
-        /* some version of atombios ignore the enable HDMI flag
+        } else if (ASIC_IS_DCE3(rdev)) {
-         * so enabling/disabling HDMI was moved here for TMDS1+2 */
+                radeon_encoder->hdmi_offset = dig->dig_encoder ?
-        switch (radeon_encoder->encoder_id) {
+                        R600_HDMI_BLOCK3 : R600_HDMI_BLOCK1;
-        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
+                if (ASIC_IS_DCE32(rdev))
-                WREG32_P(AVIVO_TMDSA_CNTL, enable ? 0x4 : 0x0, ~0x4);
+                        radeon_encoder->hdmi_config_offset = dig->dig_encoder ?
-                WREG32(offset+R600_HDMI_ENABLE, enable ? 0x101 : 0x0);
+                                R600_HDMI_CONFIG2 : R600_HDMI_CONFIG1;
-                break;
+        } else if (rdev->family >= CHIP_R600) {
+                radeon_encoder->hdmi_offset = r600_hdmi_find_free_block(dev);
-        case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
-                WREG32_P(AVIVO_LVTMA_CNTL, enable ? 0x4 : 0x0, ~0x4);
-                WREG32(offset+R600_HDMI_ENABLE, enable ? 0x105 : 0x0);
-                break;
-        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
-        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
-        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
-        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
-                /* This part is doubtfull in my opinion */
-                WREG32(offset+R600_HDMI_ENABLE, enable ? 0x110 : 0x0);
-                break;
-        default:
-                DRM_ERROR("unknown HDMI output type\n");
-                break;
        }
 }
 /*
- * determin at which register offset the HDMI encoder is
+ * enable the HDMI engine
 */
-void r600_hdmi_init(struct drm_encoder *encoder)
+void r600_hdmi_enable(struct drm_encoder *encoder)
 {
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
-        switch (radeon_encoder->encoder_id) {
+        if (ASIC_IS_DCE4(rdev))
-        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
+                return;
-        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
-        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+        if (!radeon_encoder->hdmi_offset) {
-                radeon_encoder->hdmi_offset = R600_HDMI_TMDS1;
+                r600_hdmi_assign_block(encoder);
-                break;
+                if (!radeon_encoder->hdmi_offset) {
+                        dev_warn(rdev->dev, "Could not find HDMI block for "
-        case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
+                                "0x%x encoder\n", radeon_encoder->encoder_id);
-                switch (r600_audio_tmds_index(encoder)) {
+                        return;
-                case 0:
+                }
-                        radeon_encoder->hdmi_offset = R600_HDMI_TMDS1;
+        }
+        if (ASIC_IS_DCE32(rdev) && !ASIC_IS_DCE4(rdev)) {
+                WREG32_P(radeon_encoder->hdmi_config_offset + 0x4, 0x1, ~0x1);
+        } else if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {
+                int offset = radeon_encoder->hdmi_offset;
+                switch (radeon_encoder->encoder_id) {
+                case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
+                        WREG32_P(AVIVO_TMDSA_CNTL, 0x4, ~0x4);
+                        WREG32(offset + R600_HDMI_ENABLE, 0x101);
                        break;
-                case 1:
+                case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
-                        radeon_encoder->hdmi_offset = R600_HDMI_TMDS2;
+                        WREG32_P(AVIVO_LVTMA_CNTL, 0x4, ~0x4);
+                        WREG32(offset + R600_HDMI_ENABLE, 0x105);
                        break;
                default:
-                        radeon_encoder->hdmi_offset = 0;
+                        dev_err(rdev->dev, "Unknown HDMI output type\n");
                        break;
                }
-        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+        }
-                radeon_encoder->hdmi_offset = R600_HDMI_TMDS2;
-                break;
+        DRM_DEBUG("Enabling HDMI interface @ 0x%04X for encoder 0x%x\n",
+                radeon_encoder->hdmi_offset, radeon_encoder->encoder_id);
+}
+/*
+ * disable the HDMI engine
+ */
+void r600_hdmi_disable(struct drm_encoder *encoder)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
-        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
+        if (ASIC_IS_DCE4(rdev))
-                radeon_encoder->hdmi_offset = R600_HDMI_DIG;
+                return;
-                break;
-        default:
+        if (!radeon_encoder->hdmi_offset) {
-                radeon_encoder->hdmi_offset = 0;
+                dev_err(rdev->dev, "Disabling not enabled HDMI\n");
-                break;
+                return;
        }
-        DRM_DEBUG("using HDMI engine at offset 0x%04X for encoder 0x%x\n",
+        DRM_DEBUG("Disabling HDMI interface @ 0x%04X for encoder 0x%x\n",
-                  radeon_encoder->hdmi_offset, radeon_encoder->encoder_id);
+                radeon_encoder->hdmi_offset, radeon_encoder->encoder_id);
+        if (ASIC_IS_DCE32(rdev) && !ASIC_IS_DCE4(rdev)) {
+                WREG32_P(radeon_encoder->hdmi_config_offset + 0x4, 0, ~0x1);
+        } else if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {
+                int offset = radeon_encoder->hdmi_offset;
+                switch (radeon_encoder->encoder_id) {
+                case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
+                        WREG32_P(AVIVO_TMDSA_CNTL, 0, ~0x4);
+                        WREG32(offset + R600_HDMI_ENABLE, 0);
+                        break;
+                case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
+                        WREG32_P(AVIVO_LVTMA_CNTL, 0, ~0x4);
+                        WREG32(offset + R600_HDMI_ENABLE, 0);
+                        break;
+                default:
+                        dev_err(rdev->dev, "Unknown HDMI output type\n");
+                        break;
+                }
+        }
-        /* TODO: make this configureable */
+        radeon_encoder->hdmi_offset = 0;
-        radeon_encoder->hdmi_audio_workaround = 0;
+        radeon_encoder->hdmi_config_offset = 0;
 }
diff --git a/drivers/gpu/drm/radeon/r600_reg.h b/drivers/gpu/drm/radeon/r600_reg.h
index d0e28ffdeda9..7b1d22370f6e 100644
--- a/drivers/gpu/drm/radeon/r600_reg.h
+++ b/drivers/gpu/drm/radeon/r600_reg.h
@@ -152,9 +152,9 @@
 #define R600_AUDIO_STATUS_BITS            0x73d8
 /* HDMI base register addresses */
-#define R600_HDMI_TMDS1                   0x7400
+#define R600_HDMI_BLOCK1                  0x7400
-#define R600_HDMI_TMDS2                   0x7700
+#define R600_HDMI_BLOCK2                  0x7700
-#define R600_HDMI_DIG                     0x7800
+#define R600_HDMI_BLOCK3                  0x7800
 /* HDMI registers */
 #define R600_HDMI_ENABLE           0x00
@@ -185,4 +185,8 @@
 #define R600_HDMI_AUDIO_DEBUG_2    0xe8
 #define R600_HDMI_AUDIO_DEBUG_3    0xec
+/* HDMI additional config base register addresses */
+#define R600_HDMI_CONFIG1                 0x7600
+#define R600_HDMI_CONFIG2                 0x7a00
 #endif
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index 5b2e4d442823..59c1f8793e60 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -77,6 +77,55 @@
 #define CB_COLOR0_FRAG                                  0x280e0
 #define CB_COLOR0_MASK                                  0x28100
+#define SQ_ALU_CONST_CACHE_PS_0                         0x28940
+#define SQ_ALU_CONST_CACHE_PS_1                         0x28944
+#define SQ_ALU_CONST_CACHE_PS_2                         0x28948
+#define SQ_ALU_CONST_CACHE_PS_3                         0x2894c
+#define SQ_ALU_CONST_CACHE_PS_4                         0x28950
+#define SQ_ALU_CONST_CACHE_PS_5                         0x28954
+#define SQ_ALU_CONST_CACHE_PS_6                         0x28958
+#define SQ_ALU_CONST_CACHE_PS_7                         0x2895c
+#define SQ_ALU_CONST_CACHE_PS_8                         0x28960
+#define SQ_ALU_CONST_CACHE_PS_9                         0x28964
+#define SQ_ALU_CONST_CACHE_PS_10                        0x28968
+#define SQ_ALU_CONST_CACHE_PS_11                        0x2896c
+#define SQ_ALU_CONST_CACHE_PS_12                        0x28970
+#define SQ_ALU_CONST_CACHE_PS_13                        0x28974
+#define SQ_ALU_CONST_CACHE_PS_14                        0x28978
+#define SQ_ALU_CONST_CACHE_PS_15                        0x2897c
+#define SQ_ALU_CONST_CACHE_VS_0                         0x28980
+#define SQ_ALU_CONST_CACHE_VS_1                         0x28984
+#define SQ_ALU_CONST_CACHE_VS_2                         0x28988
+#define SQ_ALU_CONST_CACHE_VS_3                         0x2898c
+#define SQ_ALU_CONST_CACHE_VS_4                         0x28990
+#define SQ_ALU_CONST_CACHE_VS_5                         0x28994
+#define SQ_ALU_CONST_CACHE_VS_6                         0x28998
+#define SQ_ALU_CONST_CACHE_VS_7                         0x2899c
+#define SQ_ALU_CONST_CACHE_VS_8                         0x289a0
+#define SQ_ALU_CONST_CACHE_VS_9                         0x289a4
+#define SQ_ALU_CONST_CACHE_VS_10                        0x289a8
+#define SQ_ALU_CONST_CACHE_VS_11                        0x289ac
+#define SQ_ALU_CONST_CACHE_VS_12                        0x289b0
+#define SQ_ALU_CONST_CACHE_VS_13                        0x289b4
+#define SQ_ALU_CONST_CACHE_VS_14                        0x289b8
+#define SQ_ALU_CONST_CACHE_VS_15                        0x289bc
+#define SQ_ALU_CONST_CACHE_GS_0                         0x289c0
+#define SQ_ALU_CONST_CACHE_GS_1                         0x289c4
+#define SQ_ALU_CONST_CACHE_GS_2                         0x289c8
+#define SQ_ALU_CONST_CACHE_GS_3                         0x289cc
+#define SQ_ALU_CONST_CACHE_GS_4                         0x289d0
+#define SQ_ALU_CONST_CACHE_GS_5                         0x289d4
+#define SQ_ALU_CONST_CACHE_GS_6                         0x289d8
+#define SQ_ALU_CONST_CACHE_GS_7                         0x289dc
+#define SQ_ALU_CONST_CACHE_GS_8                         0x289e0
+#define SQ_ALU_CONST_CACHE_GS_9                         0x289e4
+#define SQ_ALU_CONST_CACHE_GS_10                        0x289e8
+#define SQ_ALU_CONST_CACHE_GS_11                        0x289ec
+#define SQ_ALU_CONST_CACHE_GS_12                        0x289f0
+#define SQ_ALU_CONST_CACHE_GS_13                        0x289f4
+#define SQ_ALU_CONST_CACHE_GS_14                        0x289f8
+#define SQ_ALU_CONST_CACHE_GS_15                        0x289fc
 #define CONFIG_MEMSIZE                                  0x5428
 #define CONFIG_CNTL                                     0x5424
 #define CP_STAT                                         0x8680
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 829e26e8a4bb..034218c3dbbb 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -91,6 +91,8 @@ extern int radeon_tv;
 extern int radeon_new_pll;
 extern int radeon_dynpm;
 extern int radeon_audio;
+extern int radeon_disp_priority;
+extern int radeon_hw_i2c;
 /*
 * Copy from radeon_drv.h so we don't have to include both and have conflicting
@@ -168,6 +170,7 @@ struct radeon_clock {
 * Power management
 */
 int radeon_pm_init(struct radeon_device *rdev);
+void radeon_pm_fini(struct radeon_device *rdev);
 void radeon_pm_compute_clocks(struct radeon_device *rdev);
 void radeon_combios_get_power_modes(struct radeon_device *rdev);
 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
@@ -687,6 +690,7 @@ struct radeon_pm {
        bool                    downclocked;
        int                     active_crtcs;
        int                     req_vblank;
+        bool                    vblank_sync;
        fixed20_12              max_bandwidth;
        fixed20_12              igp_sideport_mclk;
        fixed20_12              igp_system_mclk;
@@ -697,6 +701,7 @@ struct radeon_pm {
        fixed20_12              ht_bandwidth;
        fixed20_12              core_bandwidth;
        fixed20_12              sclk;
+        fixed20_12              mclk;
        fixed20_12              needed_bandwidth;
        /* XXX: use a define for num power modes */
        struct radeon_power_state power_state[8];
@@ -707,6 +712,7 @@ struct radeon_pm {
        struct radeon_power_state *requested_power_state;
        struct radeon_pm_clock_info *requested_clock_mode;
        struct radeon_power_state *default_power_state;
+        struct radeon_i2c_chan *i2c_bus;
 };
@@ -729,8 +735,6 @@ int radeon_debugfs_add_files(struct radeon_device *rdev,
                             struct drm_info_list *files,
                             unsigned nfiles);
 int radeon_debugfs_fence_init(struct radeon_device *rdev);
-int r100_debugfs_rbbm_init(struct radeon_device *rdev);
-int r100_debugfs_cp_init(struct radeon_device *rdev);
 /*
@@ -782,7 +786,7 @@ struct radeon_asic {
        int (*set_surface_reg)(struct radeon_device *rdev, int reg,
                               uint32_t tiling_flags, uint32_t pitch,
                               uint32_t offset, uint32_t obj_size);
-        int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
+        void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
        void (*bandwidth_update)(struct radeon_device *rdev);
        void (*hpd_init)(struct radeon_device *rdev);
        void (*hpd_fini)(struct radeon_device *rdev);
@@ -862,6 +866,12 @@ union radeon_asic_config {
        struct rv770_asic       rv770;
 };
+/*
+ * asic initizalization from radeon_asic.c
+ */
+void radeon_agp_disable(struct radeon_device *rdev);
+int radeon_asic_init(struct radeon_device *rdev);
 /*
 * IOCTL.
@@ -1172,6 +1182,8 @@ extern void radeon_gart_restore(struct radeon_device *rdev);
 extern int radeon_modeset_init(struct radeon_device *rdev);
 extern void radeon_modeset_fini(struct radeon_device *rdev);
 extern bool radeon_card_posted(struct radeon_device *rdev);
+extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
+extern void radeon_update_display_priority(struct radeon_device *rdev);
 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
 extern int radeon_clocks_init(struct radeon_device *rdev);
 extern void radeon_clocks_fini(struct radeon_device *rdev);
@@ -1188,51 +1200,6 @@ extern int radeon_resume_kms(struct drm_device *dev);
 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
-struct r100_mc_save {
-        u32     GENMO_WT;
-        u32     CRTC_EXT_CNTL;
-        u32     CRTC_GEN_CNTL;
-        u32     CRTC2_GEN_CNTL;
-        u32     CUR_OFFSET;
-        u32     CUR2_OFFSET;
-};
-extern void r100_cp_disable(struct radeon_device *rdev);
-extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
-extern void r100_cp_fini(struct radeon_device *rdev);
-extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
-extern int r100_pci_gart_init(struct radeon_device *rdev);
-extern void r100_pci_gart_fini(struct radeon_device *rdev);
-extern int r100_pci_gart_enable(struct radeon_device *rdev);
-extern void r100_pci_gart_disable(struct radeon_device *rdev);
-extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
-extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
-extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
-extern void r100_ib_fini(struct radeon_device *rdev);
-extern int r100_ib_init(struct radeon_device *rdev);
-extern void r100_irq_disable(struct radeon_device *rdev);
-extern int r100_irq_set(struct radeon_device *rdev);
-extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
-extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
-extern void r100_vram_init_sizes(struct radeon_device *rdev);
-extern void r100_wb_disable(struct radeon_device *rdev);
-extern void r100_wb_fini(struct radeon_device *rdev);
-extern int r100_wb_init(struct radeon_device *rdev);
-extern void r100_hdp_reset(struct radeon_device *rdev);
-extern int r100_rb2d_reset(struct radeon_device *rdev);
-extern int r100_cp_reset(struct radeon_device *rdev);
-extern void r100_vga_render_disable(struct radeon_device *rdev);
-extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
-                                                struct radeon_cs_packet *pkt,
-                                                struct radeon_bo *robj);
-extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
-                                struct radeon_cs_packet *pkt,
-                                const unsigned *auth, unsigned n,
-                                radeon_packet0_check_t check);
-extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
-                                struct radeon_cs_packet *pkt,
-                                unsigned idx);
-extern void r100_enable_bm(struct radeon_device *rdev);
-extern void r100_set_common_regs(struct radeon_device *rdev);
 /* rv200,rv250,rv280 */
 extern void r200_set_safe_registers(struct radeon_device *rdev);
@@ -1322,7 +1289,8 @@ extern int r600_audio_tmds_index(struct drm_encoder *encoder);
 extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
 extern void r600_audio_fini(struct radeon_device *rdev);
 extern void r600_hdmi_init(struct drm_encoder *encoder);
-extern void r600_hdmi_enable(struct drm_encoder *encoder, int enable);
+extern void r600_hdmi_enable(struct drm_encoder *encoder);
+extern void r600_hdmi_disable(struct drm_encoder *encoder);
 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
 extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
 extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder,
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
new file mode 100644
index 000000000000..a4b4bc9fa322
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -0,0 +1,772 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#include <linux/console.h>
+#include <drm/drmP.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/radeon_drm.h>
+#include <linux/vgaarb.h>
+#include <linux/vga_switcheroo.h>
+#include "radeon_reg.h"
+#include "radeon.h"
+#include "radeon_asic.h"
+#include "atom.h"
+/*
+ * Registers accessors functions.
+ */
+static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
+{
+        DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
+        BUG_ON(1);
+        return 0;
+}
+static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
+{
+        DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
+                  reg, v);
+        BUG_ON(1);
+}
+static void radeon_register_accessor_init(struct radeon_device *rdev)
+{
+        rdev->mc_rreg = &radeon_invalid_rreg;
+        rdev->mc_wreg = &radeon_invalid_wreg;
+        rdev->pll_rreg = &radeon_invalid_rreg;
+        rdev->pll_wreg = &radeon_invalid_wreg;
+        rdev->pciep_rreg = &radeon_invalid_rreg;
+        rdev->pciep_wreg = &radeon_invalid_wreg;
+        /* Don't change order as we are overridding accessor. */
+        if (rdev->family < CHIP_RV515) {
+                rdev->pcie_reg_mask = 0xff;
+        } else {
+                rdev->pcie_reg_mask = 0x7ff;
+        }
+        /* FIXME: not sure here */
+        if (rdev->family <= CHIP_R580) {
+                rdev->pll_rreg = &r100_pll_rreg;
+                rdev->pll_wreg = &r100_pll_wreg;
+        }
+        if (rdev->family >= CHIP_R420) {
+                rdev->mc_rreg = &r420_mc_rreg;
+                rdev->mc_wreg = &r420_mc_wreg;
+        }
+        if (rdev->family >= CHIP_RV515) {
+                rdev->mc_rreg = &rv515_mc_rreg;
+                rdev->mc_wreg = &rv515_mc_wreg;
+        }
+        if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
+                rdev->mc_rreg = &rs400_mc_rreg;
+                rdev->mc_wreg = &rs400_mc_wreg;
+        }
+        if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
+                rdev->mc_rreg = &rs690_mc_rreg;
+                rdev->mc_wreg = &rs690_mc_wreg;
+        }
+        if (rdev->family == CHIP_RS600) {
+                rdev->mc_rreg = &rs600_mc_rreg;
+                rdev->mc_wreg = &rs600_mc_wreg;
+        }
+        if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_RV740)) {
+                rdev->pciep_rreg = &r600_pciep_rreg;
+                rdev->pciep_wreg = &r600_pciep_wreg;
+        }
+}
+/* helper to disable agp */
+void radeon_agp_disable(struct radeon_device *rdev)
+{
+        rdev->flags &= ~RADEON_IS_AGP;
+        if (rdev->family >= CHIP_R600) {
+                DRM_INFO("Forcing AGP to PCIE mode\n");
+                rdev->flags |= RADEON_IS_PCIE;
+        } else if (rdev->family >= CHIP_RV515 ||
+                        rdev->family == CHIP_RV380 ||
+                        rdev->family == CHIP_RV410 ||
+                        rdev->family == CHIP_R423) {
+                DRM_INFO("Forcing AGP to PCIE mode\n");
+                rdev->flags |= RADEON_IS_PCIE;
+                rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
+                rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
+        } else {
+                DRM_INFO("Forcing AGP to PCI mode\n");
+                rdev->flags |= RADEON_IS_PCI;
+                rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
+                rdev->asic->gart_set_page = &r100_pci_gart_set_page;
+        }
+        rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
+}
+/*
+ * ASIC
+ */
+static struct radeon_asic r100_asic = {
+        .init = &r100_init,
+        .fini = &r100_fini,
+        .suspend = &r100_suspend,
+        .resume = &r100_resume,
+        .vga_set_state = &r100_vga_set_state,
+        .gpu_reset = &r100_gpu_reset,
+        .gart_tlb_flush = &r100_pci_gart_tlb_flush,
+        .gart_set_page = &r100_pci_gart_set_page,
+        .cp_commit = &r100_cp_commit,
+        .ring_start = &r100_ring_start,
+        .ring_test = &r100_ring_test,
+        .ring_ib_execute = &r100_ring_ib_execute,
+        .irq_set = &r100_irq_set,
+        .irq_process = &r100_irq_process,
+        .get_vblank_counter = &r100_get_vblank_counter,
+        .fence_ring_emit = &r100_fence_ring_emit,
+        .cs_parse = &r100_cs_parse,
+        .copy_blit = &r100_copy_blit,
+        .copy_dma = NULL,
+        .copy = &r100_copy_blit,
+        .get_engine_clock = &radeon_legacy_get_engine_clock,
+        .set_engine_clock = &radeon_legacy_set_engine_clock,
+        .get_memory_clock = &radeon_legacy_get_memory_clock,
+        .set_memory_clock = NULL,
+        .get_pcie_lanes = NULL,
+        .set_pcie_lanes = NULL,
+        .set_clock_gating = &radeon_legacy_set_clock_gating,
+        .set_surface_reg = r100_set_surface_reg,
+        .clear_surface_reg = r100_clear_surface_reg,
+        .bandwidth_update = &r100_bandwidth_update,
+        .hpd_init = &r100_hpd_init,
+        .hpd_fini = &r100_hpd_fini,
+        .hpd_sense = &r100_hpd_sense,
+        .hpd_set_polarity = &r100_hpd_set_polarity,
+        .ioctl_wait_idle = NULL,
+};
+static struct radeon_asic r200_asic = {
+        .init = &r100_init,
+        .fini = &r100_fini,
+        .suspend = &r100_suspend,
+        .resume = &r100_resume,
+        .vga_set_state = &r100_vga_set_state,
+        .gpu_reset = &r100_gpu_reset,
+        .gart_tlb_flush = &r100_pci_gart_tlb_flush,
+        .gart_set_page = &r100_pci_gart_set_page,
+        .cp_commit = &r100_cp_commit,
+        .ring_start = &r100_ring_start,
+        .ring_test = &r100_ring_test,
+        .ring_ib_execute = &r100_ring_ib_execute,
+        .irq_set = &r100_irq_set,
+        .irq_process = &r100_irq_process,
+        .get_vblank_counter = &r100_get_vblank_counter,
+        .fence_ring_emit = &r100_fence_ring_emit,
+        .cs_parse = &r100_cs_parse,
+        .copy_blit = &r100_copy_blit,
+        .copy_dma = &r200_copy_dma,
+        .copy = &r100_copy_blit,
+        .get_engine_clock = &radeon_legacy_get_engine_clock,
+        .set_engine_clock = &radeon_legacy_set_engine_clock,
+        .get_memory_clock = &radeon_legacy_get_memory_clock,
+        .set_memory_clock = NULL,
+        .set_pcie_lanes = NULL,
+        .set_clock_gating = &radeon_legacy_set_clock_gating,
+        .set_surface_reg = r100_set_surface_reg,
+        .clear_surface_reg = r100_clear_surface_reg,
+        .bandwidth_update = &r100_bandwidth_update,
+        .hpd_init = &r100_hpd_init,
+        .hpd_fini = &r100_hpd_fini,
+        .hpd_sense = &r100_hpd_sense,
+        .hpd_set_polarity = &r100_hpd_set_polarity,
+        .ioctl_wait_idle = NULL,
+};
+static struct radeon_asic r300_asic = {
+        .init = &r300_init,
+        .fini = &r300_fini,
+        .suspend = &r300_suspend,
+        .resume = &r300_resume,
+        .vga_set_state = &r100_vga_set_state,
+        .gpu_reset = &r300_gpu_reset,
+        .gart_tlb_flush = &r100_pci_gart_tlb_flush,
+        .gart_set_page = &r100_pci_gart_set_page,
+        .cp_commit = &r100_cp_commit,
+        .ring_start = &r300_ring_start,
+        .ring_test = &r100_ring_test,
+        .ring_ib_execute = &r100_ring_ib_execute,
+        .irq_set = &r100_irq_set,
+        .irq_process = &r100_irq_process,
+        .get_vblank_counter = &r100_get_vblank_counter,
+        .fence_ring_emit = &r300_fence_ring_emit,
+        .cs_parse = &r300_cs_parse,
+        .copy_blit = &r100_copy_blit,
+        .copy_dma = &r200_copy_dma,
+        .copy = &r100_copy_blit,
+        .get_engine_clock = &radeon_legacy_get_engine_clock,
+        .set_engine_clock = &radeon_legacy_set_engine_clock,
+        .get_memory_clock = &radeon_legacy_get_memory_clock,
+        .set_memory_clock = NULL,
+        .get_pcie_lanes = &rv370_get_pcie_lanes,
+        .set_pcie_lanes = &rv370_set_pcie_lanes,
+        .set_clock_gating = &radeon_legacy_set_clock_gating,
+        .set_surface_reg = r100_set_surface_reg,
+        .clear_surface_reg = r100_clear_surface_reg,
+        .bandwidth_update = &r100_bandwidth_update,
+        .hpd_init = &r100_hpd_init,
+        .hpd_fini = &r100_hpd_fini,
+        .hpd_sense = &r100_hpd_sense,
+        .hpd_set_polarity = &r100_hpd_set_polarity,
+        .ioctl_wait_idle = NULL,
+};
+static struct radeon_asic r300_asic_pcie = {
+        .init = &r300_init,
+        .fini = &r300_fini,
+        .suspend = &r300_suspend,
+        .resume = &r300_resume,
+        .vga_set_state = &r100_vga_set_state,
+        .gpu_reset = &r300_gpu_reset,
+        .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
+        .gart_set_page = &rv370_pcie_gart_set_page,
+        .cp_commit = &r100_cp_commit,
+        .ring_start = &r300_ring_start,
+        .ring_test = &r100_ring_test,
+        .ring_ib_execute = &r100_ring_ib_execute,
+        .irq_set = &r100_irq_set,
+        .irq_process = &r100_irq_process,
+        .get_vblank_counter = &r100_get_vblank_counter,
+        .fence_ring_emit = &r300_fence_ring_emit,
+        .cs_parse = &r300_cs_parse,
+        .copy_blit = &r100_copy_blit,
+        .copy_dma = &r200_copy_dma,
+        .copy = &r100_copy_blit,
+        .get_engine_clock = &radeon_legacy_get_engine_clock,
+        .set_engine_clock = &radeon_legacy_set_engine_clock,
+        .get_memory_clock = &radeon_legacy_get_memory_clock,
+        .set_memory_clock = NULL,
+        .set_pcie_lanes = &rv370_set_pcie_lanes,
+        .set_clock_gating = &radeon_legacy_set_clock_gating,
+        .set_surface_reg = r100_set_surface_reg,
+        .clear_surface_reg = r100_clear_surface_reg,
+        .bandwidth_update = &r100_bandwidth_update,
+        .hpd_init = &r100_hpd_init,
+        .hpd_fini = &r100_hpd_fini,
+        .hpd_sense = &r100_hpd_sense,
+        .hpd_set_polarity = &r100_hpd_set_polarity,
+        .ioctl_wait_idle = NULL,
+};
+static struct radeon_asic r420_asic = {
+        .init = &r420_init,
+        .fini = &r420_fini,
+        .suspend = &r420_suspend,
+        .resume = &r420_resume,
+        .vga_set_state = &r100_vga_set_state,
+        .gpu_reset = &r300_gpu_reset,
+        .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
+        .gart_set_page = &rv370_pcie_gart_set_page,
+        .cp_commit = &r100_cp_commit,
+        .ring_start = &r300_ring_start,
+        .ring_test = &r100_ring_test,
+        .ring_ib_execute = &r100_ring_ib_execute,
+        .irq_set = &r100_irq_set,
+        .irq_process = &r100_irq_process,
+        .get_vblank_counter = &r100_get_vblank_counter,
+        .fence_ring_emit = &r300_fence_ring_emit,
+        .cs_parse = &r300_cs_parse,
+        .copy_blit = &r100_copy_blit,
+        .copy_dma = &r200_copy_dma,
+        .copy = &r100_copy_blit,
+        .get_engine_clock = &radeon_atom_get_engine_clock,
+        .set_engine_clock = &radeon_atom_set_engine_clock,
+        .get_memory_clock = &radeon_atom_get_memory_clock,
+        .set_memory_clock = &radeon_atom_set_memory_clock,
+        .get_pcie_lanes = &rv370_get_pcie_lanes,
+        .set_pcie_lanes = &rv370_set_pcie_lanes,
+        .set_clock_gating = &radeon_atom_set_clock_gating,
+        .set_surface_reg = r100_set_surface_reg,
+        .clear_surface_reg = r100_clear_surface_reg,
+        .bandwidth_update = &r100_bandwidth_update,
+        .hpd_init = &r100_hpd_init,
+        .hpd_fini = &r100_hpd_fini,
+        .hpd_sense = &r100_hpd_sense,
+        .hpd_set_polarity = &r100_hpd_set_polarity,
+        .ioctl_wait_idle = NULL,
+};
+static struct radeon_asic rs400_asic = {
+        .init = &rs400_init,
+        .fini = &rs400_fini,
+        .suspend = &rs400_suspend,
+        .resume = &rs400_resume,
+        .vga_set_state = &r100_vga_set_state,
+        .gpu_reset = &r300_gpu_reset,
+        .gart_tlb_flush = &rs400_gart_tlb_flush,
+        .gart_set_page = &rs400_gart_set_page,
+        .cp_commit = &r100_cp_commit,
+        .ring_start = &r300_ring_start,
+        .ring_test = &r100_ring_test,
+        .ring_ib_execute = &r100_ring_ib_execute,
+        .irq_set = &r100_irq_set,
+        .irq_process = &r100_irq_process,
+        .get_vblank_counter = &r100_get_vblank_counter,
+        .fence_ring_emit = &r300_fence_ring_emit,
+        .cs_parse = &r300_cs_parse,
+        .copy_blit = &r100_copy_blit,
+        .copy_dma = &r200_copy_dma,
+        .copy = &r100_copy_blit,
+        .get_engine_clock = &radeon_legacy_get_engine_clock,
+        .set_engine_clock = &radeon_legacy_set_engine_clock,
+        .get_memory_clock = &radeon_legacy_get_memory_clock,
+        .set_memory_clock = NULL,
+        .get_pcie_lanes = NULL,
+        .set_pcie_lanes = NULL,
+        .set_clock_gating = &radeon_legacy_set_clock_gating,
+        .set_surface_reg = r100_set_surface_reg,
+        .clear_surface_reg = r100_clear_surface_reg,
+        .bandwidth_update = &r100_bandwidth_update,
+        .hpd_init = &r100_hpd_init,
+        .hpd_fini = &r100_hpd_fini,
+        .hpd_sense = &r100_hpd_sense,
+        .hpd_set_polarity = &r100_hpd_set_polarity,
+        .ioctl_wait_idle = NULL,
+};
+static struct radeon_asic rs600_asic = {
+        .init = &rs600_init,
+        .fini = &rs600_fini,
+        .suspend = &rs600_suspend,
+        .resume = &rs600_resume,
+        .vga_set_state = &r100_vga_set_state,
+        .gpu_reset = &r300_gpu_reset,
+        .gart_tlb_flush = &rs600_gart_tlb_flush,
+        .gart_set_page = &rs600_gart_set_page,
+        .cp_commit = &r100_cp_commit,
+        .ring_start = &r300_ring_start,
+        .ring_test = &r100_ring_test,
+        .ring_ib_execute = &r100_ring_ib_execute,
+        .irq_set = &rs600_irq_set,
+        .irq_process = &rs600_irq_process,
+        .get_vblank_counter = &rs600_get_vblank_counter,
+        .fence_ring_emit = &r300_fence_ring_emit,
+        .cs_parse = &r300_cs_parse,
+        .copy_blit = &r100_copy_blit,
+        .copy_dma = &r200_copy_dma,
+        .copy = &r100_copy_blit,
+        .get_engine_clock = &radeon_atom_get_engine_clock,
+        .set_engine_clock = &radeon_atom_set_engine_clock,
+        .get_memory_clock = &radeon_atom_get_memory_clock,
+        .set_memory_clock = &radeon_atom_set_memory_clock,
+        .get_pcie_lanes = NULL,
+        .set_pcie_lanes = NULL,
+        .set_clock_gating = &radeon_atom_set_clock_gating,
+        .set_surface_reg = r100_set_surface_reg,
+        .clear_surface_reg = r100_clear_surface_reg,
+        .bandwidth_update = &rs600_bandwidth_update,
+        .hpd_init = &rs600_hpd_init,
+        .hpd_fini = &rs600_hpd_fini,
+        .hpd_sense = &rs600_hpd_sense,
+        .hpd_set_polarity = &rs600_hpd_set_polarity,
+        .ioctl_wait_idle = NULL,
+};
+static struct radeon_asic rs690_asic = {
+        .init = &rs690_init,
+        .fini = &rs690_fini,
+        .suspend = &rs690_suspend,
+        .resume = &rs690_resume,
+        .vga_set_state = &r100_vga_set_state,
+        .gpu_reset = &r300_gpu_reset,
+        .gart_tlb_flush = &rs400_gart_tlb_flush,
+        .gart_set_page = &rs400_gart_set_page,
+        .cp_commit = &r100_cp_commit,
+        .ring_start = &r300_ring_start,
+        .ring_test = &r100_ring_test,
+        .ring_ib_execute = &r100_ring_ib_execute,
+        .irq_set = &rs600_irq_set,
+        .irq_process = &rs600_irq_process,
+        .get_vblank_counter = &rs600_get_vblank_counter,
+        .fence_ring_emit = &r300_fence_ring_emit,
+        .cs_parse = &r300_cs_parse,
+        .copy_blit = &r100_copy_blit,
+        .copy_dma = &r200_copy_dma,
+        .copy = &r200_copy_dma,
+        .get_engine_clock = &radeon_atom_get_engine_clock,
+        .set_engine_clock = &radeon_atom_set_engine_clock,
+        .get_memory_clock = &radeon_atom_get_memory_clock,
+        .set_memory_clock = &radeon_atom_set_memory_clock,
+        .get_pcie_lanes = NULL,
+        .set_pcie_lanes = NULL,
+        .set_clock_gating = &radeon_atom_set_clock_gating,
+        .set_surface_reg = r100_set_surface_reg,
+        .clear_surface_reg = r100_clear_surface_reg,
+        .bandwidth_update = &rs690_bandwidth_update,
+        .hpd_init = &rs600_hpd_init,
+        .hpd_fini = &rs600_hpd_fini,
+        .hpd_sense = &rs600_hpd_sense,
+        .hpd_set_polarity = &rs600_hpd_set_polarity,
+        .ioctl_wait_idle = NULL,
+};
+static struct radeon_asic rv515_asic = {
+        .init = &rv515_init,
+        .fini = &rv515_fini,
+        .suspend = &rv515_suspend,
+        .resume = &rv515_resume,
+        .vga_set_state = &r100_vga_set_state,
+        .gpu_reset = &rv515_gpu_reset,
+        .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
+        .gart_set_page = &rv370_pcie_gart_set_page,
+        .cp_commit = &r100_cp_commit,
+        .ring_start = &rv515_ring_start,
+        .ring_test = &r100_ring_test,
+        .ring_ib_execute = &r100_ring_ib_execute,
+        .irq_set = &rs600_irq_set,
+        .irq_process = &rs600_irq_process,
+        .get_vblank_counter = &rs600_get_vblank_counter,
+        .fence_ring_emit = &r300_fence_ring_emit,
+        .cs_parse = &r300_cs_parse,
+        .copy_blit = &r100_copy_blit,
+        .copy_dma = &r200_copy_dma,
+        .copy = &r100_copy_blit,
+        .get_engine_clock = &radeon_atom_get_engine_clock,
+        .set_engine_clock = &radeon_atom_set_engine_clock,
+        .get_memory_clock = &radeon_atom_get_memory_clock,
+        .set_memory_clock = &radeon_atom_set_memory_clock,
+        .get_pcie_lanes = &rv370_get_pcie_lanes,
+        .set_pcie_lanes = &rv370_set_pcie_lanes,
+        .set_clock_gating = &radeon_atom_set_clock_gating,
+        .set_surface_reg = r100_set_surface_reg,
+        .clear_surface_reg = r100_clear_surface_reg,
+        .bandwidth_update = &rv515_bandwidth_update,
+        .hpd_init = &rs600_hpd_init,
+        .hpd_fini = &rs600_hpd_fini,
+        .hpd_sense = &rs600_hpd_sense,
+        .hpd_set_polarity = &rs600_hpd_set_polarity,
+        .ioctl_wait_idle = NULL,
+};
+static struct radeon_asic r520_asic = {
+        .init = &r520_init,
+        .fini = &rv515_fini,
+        .suspend = &rv515_suspend,
+        .resume = &r520_resume,
+        .vga_set_state = &r100_vga_set_state,
+        .gpu_reset = &rv515_gpu_reset,
+        .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
+        .gart_set_page = &rv370_pcie_gart_set_page,
+        .cp_commit = &r100_cp_commit,
+        .ring_start = &rv515_ring_start,
+        .ring_test = &r100_ring_test,
+        .ring_ib_execute = &r100_ring_ib_execute,
+        .irq_set = &rs600_irq_set,
+        .irq_process = &rs600_irq_process,
+        .get_vblank_counter = &rs600_get_vblank_counter,
+        .fence_ring_emit = &r300_fence_ring_emit,
+        .cs_parse = &r300_cs_parse,
+        .copy_blit = &r100_copy_blit,
+        .copy_dma = &r200_copy_dma,
+        .copy = &r100_copy_blit,
+        .get_engine_clock = &radeon_atom_get_engine_clock,
+        .set_engine_clock = &radeon_atom_set_engine_clock,
+        .get_memory_clock = &radeon_atom_get_memory_clock,
+        .set_memory_clock = &radeon_atom_set_memory_clock,
+        .get_pcie_lanes = &rv370_get_pcie_lanes,
+        .set_pcie_lanes = &rv370_set_pcie_lanes,
+        .set_clock_gating = &radeon_atom_set_clock_gating,
+        .set_surface_reg = r100_set_surface_reg,
+        .clear_surface_reg = r100_clear_surface_reg,
+        .bandwidth_update = &rv515_bandwidth_update,
+        .hpd_init = &rs600_hpd_init,
+        .hpd_fini = &rs600_hpd_fini,
+        .hpd_sense = &rs600_hpd_sense,
+        .hpd_set_polarity = &rs600_hpd_set_polarity,
+        .ioctl_wait_idle = NULL,
+};
+static struct radeon_asic r600_asic = {
+        .init = &r600_init,
+        .fini = &r600_fini,
+        .suspend = &r600_suspend,
+        .resume = &r600_resume,
+        .cp_commit = &r600_cp_commit,
+        .vga_set_state = &r600_vga_set_state,
+        .gpu_reset = &r600_gpu_reset,
+        .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
+        .gart_set_page = &rs600_gart_set_page,
+        .ring_test = &r600_ring_test,
+        .ring_ib_execute = &r600_ring_ib_execute,
+        .irq_set = &r600_irq_set,
+        .irq_process = &r600_irq_process,
+        .get_vblank_counter = &rs600_get_vblank_counter,
+        .fence_ring_emit = &r600_fence_ring_emit,
+        .cs_parse = &r600_cs_parse,
+        .copy_blit = &r600_copy_blit,
+        .copy_dma = &r600_copy_blit,
+        .copy = &r600_copy_blit,
+        .get_engine_clock = &radeon_atom_get_engine_clock,
+        .set_engine_clock = &radeon_atom_set_engine_clock,
+        .get_memory_clock = &radeon_atom_get_memory_clock,
+        .set_memory_clock = &radeon_atom_set_memory_clock,
+        .get_pcie_lanes = &rv370_get_pcie_lanes,
+        .set_pcie_lanes = NULL,
+        .set_clock_gating = NULL,
+        .set_surface_reg = r600_set_surface_reg,
+        .clear_surface_reg = r600_clear_surface_reg,
+        .bandwidth_update = &rv515_bandwidth_update,
+        .hpd_init = &r600_hpd_init,
+        .hpd_fini = &r600_hpd_fini,
+        .hpd_sense = &r600_hpd_sense,
+        .hpd_set_polarity = &r600_hpd_set_polarity,
+        .ioctl_wait_idle = r600_ioctl_wait_idle,
+};
+static struct radeon_asic rs780_asic = {
+        .init = &r600_init,
+        .fini = &r600_fini,
+        .suspend = &r600_suspend,
+        .resume = &r600_resume,
+        .cp_commit = &r600_cp_commit,
+        .vga_set_state = &r600_vga_set_state,
+        .gpu_reset = &r600_gpu_reset,
+        .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
+        .gart_set_page = &rs600_gart_set_page,
+        .ring_test = &r600_ring_test,
+        .ring_ib_execute = &r600_ring_ib_execute,
+        .irq_set = &r600_irq_set,
+        .irq_process = &r600_irq_process,
+        .get_vblank_counter = &rs600_get_vblank_counter,
+        .fence_ring_emit = &r600_fence_ring_emit,
+        .cs_parse = &r600_cs_parse,
+        .copy_blit = &r600_copy_blit,
+        .copy_dma = &r600_copy_blit,
+        .copy = &r600_copy_blit,
+        .get_engine_clock = &radeon_atom_get_engine_clock,
+        .set_engine_clock = &radeon_atom_set_engine_clock,
+        .get_memory_clock = NULL,
+        .set_memory_clock = NULL,
+        .get_pcie_lanes = NULL,
+        .set_pcie_lanes = NULL,
+        .set_clock_gating = NULL,
+        .set_surface_reg = r600_set_surface_reg,
+        .clear_surface_reg = r600_clear_surface_reg,
+        .bandwidth_update = &rs690_bandwidth_update,
+        .hpd_init = &r600_hpd_init,
+        .hpd_fini = &r600_hpd_fini,
+        .hpd_sense = &r600_hpd_sense,
+        .hpd_set_polarity = &r600_hpd_set_polarity,
+        .ioctl_wait_idle = r600_ioctl_wait_idle,
+};
+static struct radeon_asic rv770_asic = {
+        .init = &rv770_init,
+        .fini = &rv770_fini,
+        .suspend = &rv770_suspend,
+        .resume = &rv770_resume,
+        .cp_commit = &r600_cp_commit,
+        .gpu_reset = &rv770_gpu_reset,
+        .vga_set_state = &r600_vga_set_state,
+        .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
+        .gart_set_page = &rs600_gart_set_page,
+        .ring_test = &r600_ring_test,
+        .ring_ib_execute = &r600_ring_ib_execute,
+        .irq_set = &r600_irq_set,
+        .irq_process = &r600_irq_process,
+        .get_vblank_counter = &rs600_get_vblank_counter,
+        .fence_ring_emit = &r600_fence_ring_emit,
+        .cs_parse = &r600_cs_parse,
+        .copy_blit = &r600_copy_blit,
+        .copy_dma = &r600_copy_blit,
+        .copy = &r600_copy_blit,
+        .get_engine_clock = &radeon_atom_get_engine_clock,
+        .set_engine_clock = &radeon_atom_set_engine_clock,
+        .get_memory_clock = &radeon_atom_get_memory_clock,
+        .set_memory_clock = &radeon_atom_set_memory_clock,
+        .get_pcie_lanes = &rv370_get_pcie_lanes,
+        .set_pcie_lanes = NULL,
+        .set_clock_gating = &radeon_atom_set_clock_gating,
+        .set_surface_reg = r600_set_surface_reg,
+        .clear_surface_reg = r600_clear_surface_reg,
+        .bandwidth_update = &rv515_bandwidth_update,
+        .hpd_init = &r600_hpd_init,
+        .hpd_fini = &r600_hpd_fini,
+        .hpd_sense = &r600_hpd_sense,
+        .hpd_set_polarity = &r600_hpd_set_polarity,
+        .ioctl_wait_idle = r600_ioctl_wait_idle,
+};
+static struct radeon_asic evergreen_asic = {
+        .init = &evergreen_init,
+        .fini = &evergreen_fini,
+        .suspend = &evergreen_suspend,
+        .resume = &evergreen_resume,
+        .cp_commit = NULL,
+        .gpu_reset = &evergreen_gpu_reset,
+        .vga_set_state = &r600_vga_set_state,
+        .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
+        .gart_set_page = &rs600_gart_set_page,
+        .ring_test = NULL,
+        .ring_ib_execute = NULL,
+        .irq_set = NULL,
+        .irq_process = NULL,
+        .get_vblank_counter = NULL,
+        .fence_ring_emit = NULL,
+        .cs_parse = NULL,
+        .copy_blit = NULL,
+        .copy_dma = NULL,
+        .copy = NULL,
+        .get_engine_clock = &radeon_atom_get_engine_clock,
+        .set_engine_clock = &radeon_atom_set_engine_clock,
+        .get_memory_clock = &radeon_atom_get_memory_clock,
+        .set_memory_clock = &radeon_atom_set_memory_clock,
+        .set_pcie_lanes = NULL,
+        .set_clock_gating = NULL,
+        .set_surface_reg = r600_set_surface_reg,
+        .clear_surface_reg = r600_clear_surface_reg,
+        .bandwidth_update = &evergreen_bandwidth_update,
+        .hpd_init = &evergreen_hpd_init,
+        .hpd_fini = &evergreen_hpd_fini,
+        .hpd_sense = &evergreen_hpd_sense,
+        .hpd_set_polarity = &evergreen_hpd_set_polarity,
+};
+int radeon_asic_init(struct radeon_device *rdev)
+{
+        radeon_register_accessor_init(rdev);
+        switch (rdev->family) {
+        case CHIP_R100:
+        case CHIP_RV100:
+        case CHIP_RS100:
+        case CHIP_RV200:
+        case CHIP_RS200:
+                rdev->asic = &r100_asic;
+                break;
+        case CHIP_R200:
+        case CHIP_RV250:
+        case CHIP_RS300:
+        case CHIP_RV280:
+                rdev->asic = &r200_asic;
+                break;
+        case CHIP_R300:
+        case CHIP_R350:
+        case CHIP_RV350:
+        case CHIP_RV380:
+                if (rdev->flags & RADEON_IS_PCIE)
+                        rdev->asic = &r300_asic_pcie;
+                else
+                        rdev->asic = &r300_asic;
+                break;
+        case CHIP_R420:
+        case CHIP_R423:
+        case CHIP_RV410:
+                rdev->asic = &r420_asic;
+                break;
+        case CHIP_RS400:
+        case CHIP_RS480:
+                rdev->asic = &rs400_asic;
+                break;
+        case CHIP_RS600:
+                rdev->asic = &rs600_asic;
+                break;
+        case CHIP_RS690:
+        case CHIP_RS740:
+                rdev->asic = &rs690_asic;
+                break;
+        case CHIP_RV515:
+                rdev->asic = &rv515_asic;
+                break;
+        case CHIP_R520:
+        case CHIP_RV530:
+        case CHIP_RV560:
+        case CHIP_RV570:
+        case CHIP_R580:
+                rdev->asic = &r520_asic;
+                break;
+        case CHIP_R600:
+        case CHIP_RV610:
+        case CHIP_RV630:
+        case CHIP_RV620:
+        case CHIP_RV635:
+        case CHIP_RV670:
+                rdev->asic = &r600_asic;
+                break;
+        case CHIP_RS780:
+        case CHIP_RS880:
+                rdev->asic = &rs780_asic;
+                break;
+        case CHIP_RV770:
+        case CHIP_RV730:
+        case CHIP_RV710:
+        case CHIP_RV740:
+                rdev->asic = &rv770_asic;
+                break;
+        case CHIP_CEDAR:
+        case CHIP_REDWOOD:
+        case CHIP_JUNIPER:
+        case CHIP_CYPRESS:
+        case CHIP_HEMLOCK:
+                rdev->asic = &evergreen_asic;
+                break;
+        default:
+                /* FIXME: not supported yet */
+                return -EINVAL;
+        }
+        if (rdev->flags & RADEON_IS_IGP) {
+                rdev->asic->get_memory_clock = NULL;
+                rdev->asic->set_memory_clock = NULL;
+        }
+        /* set the number of crtcs */
+        if (rdev->flags & RADEON_SINGLE_CRTC)
+                rdev->num_crtc = 1;
+        else {
+                if (ASIC_IS_DCE4(rdev))
+                        rdev->num_crtc = 6;
+                else
+                        rdev->num_crtc = 2;
+        }
+        return 0;
+}
+/*
+ * Wrapper around modesetting bits. Move to radeon_clocks.c?
+ */
+int radeon_clocks_init(struct radeon_device *rdev)
+{
+        int r;
+        r = radeon_static_clocks_init(rdev->ddev);
+        if (r) {
+                return r;
+        }
+        DRM_INFO("Clocks initialized !\n");
+        return 0;
+}
+void radeon_clocks_fini(struct radeon_device *rdev)
+{
+}
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index d3a157b2bcb7..a0b8280663d1 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -45,10 +45,18 @@ void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
 /*
 * r100,rv100,rs100,rv200,rs200
 */
-extern int r100_init(struct radeon_device *rdev);
+struct r100_mc_save {
-extern void r100_fini(struct radeon_device *rdev);
+        u32     GENMO_WT;
-extern int r100_suspend(struct radeon_device *rdev);
+        u32     CRTC_EXT_CNTL;
-extern int r100_resume(struct radeon_device *rdev);
+        u32     CRTC_GEN_CNTL;
+        u32     CRTC2_GEN_CNTL;
+        u32     CUR_OFFSET;
+        u32     CUR2_OFFSET;
+};
+int r100_init(struct radeon_device *rdev);
+void r100_fini(struct radeon_device *rdev);
+int r100_suspend(struct radeon_device *rdev);
+int r100_resume(struct radeon_device *rdev);
 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 void r100_vga_set_state(struct radeon_device *rdev, bool state);
@@ -73,7 +81,7 @@ int r100_copy_blit(struct radeon_device *rdev,
 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
                         uint32_t tiling_flags, uint32_t pitch,
                         uint32_t offset, uint32_t obj_size);
-int r100_clear_surface_reg(struct radeon_device *rdev, int reg);
+void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
 void r100_bandwidth_update(struct radeon_device *rdev);
 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 int r100_ring_test(struct radeon_device *rdev);
@@ -82,44 +90,42 @@ void r100_hpd_fini(struct radeon_device *rdev);
 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 void r100_hpd_set_polarity(struct radeon_device *rdev,
                           enum radeon_hpd_id hpd);
+int r100_debugfs_rbbm_init(struct radeon_device *rdev);
-static struct radeon_asic r100_asic = {
+int r100_debugfs_cp_init(struct radeon_device *rdev);
-        .init = &r100_init,
+void r100_cp_disable(struct radeon_device *rdev);
-        .fini = &r100_fini,
+int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
-        .suspend = &r100_suspend,
+void r100_cp_fini(struct radeon_device *rdev);
-        .resume = &r100_resume,
+int r100_pci_gart_init(struct radeon_device *rdev);
-        .vga_set_state = &r100_vga_set_state,
+void r100_pci_gart_fini(struct radeon_device *rdev);
-        .gpu_reset = &r100_gpu_reset,
+int r100_pci_gart_enable(struct radeon_device *rdev);
-        .gart_tlb_flush = &r100_pci_gart_tlb_flush,
+void r100_pci_gart_disable(struct radeon_device *rdev);
-        .gart_set_page = &r100_pci_gart_set_page,
+int r100_debugfs_mc_info_init(struct radeon_device *rdev);
-        .cp_commit = &r100_cp_commit,
+int r100_gui_wait_for_idle(struct radeon_device *rdev);
-        .ring_start = &r100_ring_start,
+void r100_ib_fini(struct radeon_device *rdev);
-        .ring_test = &r100_ring_test,
+int r100_ib_init(struct radeon_device *rdev);
-        .ring_ib_execute = &r100_ring_ib_execute,
+void r100_irq_disable(struct radeon_device *rdev);
-        .irq_set = &r100_irq_set,
+void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
-        .irq_process = &r100_irq_process,
+void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
-        .get_vblank_counter = &r100_get_vblank_counter,
+void r100_vram_init_sizes(struct radeon_device *rdev);
-        .fence_ring_emit = &r100_fence_ring_emit,
+void r100_wb_disable(struct radeon_device *rdev);
-        .cs_parse = &r100_cs_parse,
+void r100_wb_fini(struct radeon_device *rdev);
-        .copy_blit = &r100_copy_blit,
+int r100_wb_init(struct radeon_device *rdev);
-        .copy_dma = NULL,
+void r100_hdp_reset(struct radeon_device *rdev);
-        .copy = &r100_copy_blit,
+int r100_rb2d_reset(struct radeon_device *rdev);
-        .get_engine_clock = &radeon_legacy_get_engine_clock,
+int r100_cp_reset(struct radeon_device *rdev);
-        .set_engine_clock = &radeon_legacy_set_engine_clock,
+void r100_vga_render_disable(struct radeon_device *rdev);
-        .get_memory_clock = &radeon_legacy_get_memory_clock,
+int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
-        .set_memory_clock = NULL,
+                                         struct radeon_cs_packet *pkt,
-        .get_pcie_lanes = NULL,
+                                         struct radeon_bo *robj);
-        .set_pcie_lanes = NULL,
+int r100_cs_parse_packet0(struct radeon_cs_parser *p,
-        .set_clock_gating = &radeon_legacy_set_clock_gating,
+                          struct radeon_cs_packet *pkt,
-        .set_surface_reg = r100_set_surface_reg,
+                          const unsigned *auth, unsigned n,
-        .clear_surface_reg = r100_clear_surface_reg,
+                          radeon_packet0_check_t check);
-        .bandwidth_update = &r100_bandwidth_update,
+int r100_cs_packet_parse(struct radeon_cs_parser *p,
-        .hpd_init = &r100_hpd_init,
+                         struct radeon_cs_packet *pkt,
-        .hpd_fini = &r100_hpd_fini,
+                         unsigned idx);
-        .hpd_sense = &r100_hpd_sense,
+void r100_enable_bm(struct radeon_device *rdev);
-        .hpd_set_polarity = &r100_hpd_set_polarity,
+void r100_set_common_regs(struct radeon_device *rdev);
-        .ioctl_wait_idle = NULL,
-};
 /*
 * r200,rv250,rs300,rv280
@@ -129,43 +135,6 @@ extern int r200_copy_dma(struct radeon_device *rdev,
                        uint64_t dst_offset,
                        unsigned num_pages,
                        struct radeon_fence *fence);
-static struct radeon_asic r200_asic = {
-        .init = &r100_init,
-        .fini = &r100_fini,
-        .suspend = &r100_suspend,
-        .resume = &r100_resume,
-        .vga_set_state = &r100_vga_set_state,
-        .gpu_reset = &r100_gpu_reset,
-        .gart_tlb_flush = &r100_pci_gart_tlb_flush,
-        .gart_set_page = &r100_pci_gart_set_page,
-        .cp_commit = &r100_cp_commit,
-        .ring_start = &r100_ring_start,
-        .ring_test = &r100_ring_test,
-        .ring_ib_execute = &r100_ring_ib_execute,
-        .irq_set = &r100_irq_set,
-        .irq_process = &r100_irq_process,
-        .get_vblank_counter = &r100_get_vblank_counter,
-        .fence_ring_emit = &r100_fence_ring_emit,
-        .cs_parse = &r100_cs_parse,
-        .copy_blit = &r100_copy_blit,
-        .copy_dma = &r200_copy_dma,
-        .copy = &r100_copy_blit,
-        .get_engine_clock = &radeon_legacy_get_engine_clock,
-        .set_engine_clock = &radeon_legacy_set_engine_clock,
-        .get_memory_clock = &radeon_legacy_get_memory_clock,
-        .set_memory_clock = NULL,
-        .set_pcie_lanes = NULL,
-        .set_clock_gating = &radeon_legacy_set_clock_gating,
-        .set_surface_reg = r100_set_surface_reg,
-        .clear_surface_reg = r100_clear_surface_reg,
-        .bandwidth_update = &r100_bandwidth_update,
-        .hpd_init = &r100_hpd_init,
-        .hpd_fini = &r100_hpd_fini,
-        .hpd_sense = &r100_hpd_sense,
-        .hpd_set_polarity = &r100_hpd_set_polarity,
-        .ioctl_wait_idle = NULL,
-};
 /*
 * r300,r350,rv350,rv380
@@ -186,82 +155,6 @@ extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v
 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
 extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
-static struct radeon_asic r300_asic = {
-        .init = &r300_init,
-        .fini = &r300_fini,
-        .suspend = &r300_suspend,
-        .resume = &r300_resume,
-        .vga_set_state = &r100_vga_set_state,
-        .gpu_reset = &r300_gpu_reset,
-        .gart_tlb_flush = &r100_pci_gart_tlb_flush,
-        .gart_set_page = &r100_pci_gart_set_page,
-        .cp_commit = &r100_cp_commit,
-        .ring_start = &r300_ring_start,
-        .ring_test = &r100_ring_test,
-        .ring_ib_execute = &r100_ring_ib_execute,
-        .irq_set = &r100_irq_set,
-        .irq_process = &r100_irq_process,
-        .get_vblank_counter = &r100_get_vblank_counter,
-        .fence_ring_emit = &r300_fence_ring_emit,
-        .cs_parse = &r300_cs_parse,
-        .copy_blit = &r100_copy_blit,
-        .copy_dma = &r200_copy_dma,
-        .copy = &r100_copy_blit,
-        .get_engine_clock = &radeon_legacy_get_engine_clock,
-        .set_engine_clock = &radeon_legacy_set_engine_clock,
-        .get_memory_clock = &radeon_legacy_get_memory_clock,
-        .set_memory_clock = NULL,
-        .get_pcie_lanes = &rv370_get_pcie_lanes,
-        .set_pcie_lanes = &rv370_set_pcie_lanes,
-        .set_clock_gating = &radeon_legacy_set_clock_gating,
-        .set_surface_reg = r100_set_surface_reg,
-        .clear_surface_reg = r100_clear_surface_reg,
-        .bandwidth_update = &r100_bandwidth_update,
-        .hpd_init = &r100_hpd_init,
-        .hpd_fini = &r100_hpd_fini,
-        .hpd_sense = &r100_hpd_sense,
-        .hpd_set_polarity = &r100_hpd_set_polarity,
-        .ioctl_wait_idle = NULL,
-};
-static struct radeon_asic r300_asic_pcie = {
-        .init = &r300_init,
-        .fini = &r300_fini,
-        .suspend = &r300_suspend,
-        .resume = &r300_resume,
-        .vga_set_state = &r100_vga_set_state,
-        .gpu_reset = &r300_gpu_reset,
-        .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
-        .gart_set_page = &rv370_pcie_gart_set_page,
-        .cp_commit = &r100_cp_commit,
-        .ring_start = &r300_ring_start,
-        .ring_test = &r100_ring_test,
-        .ring_ib_execute = &r100_ring_ib_execute,
-        .irq_set = &r100_irq_set,
-        .irq_process = &r100_irq_process,
-        .get_vblank_counter = &r100_get_vblank_counter,
-        .fence_ring_emit = &r300_fence_ring_emit,
-        .cs_parse = &r300_cs_parse,
-        .copy_blit = &r100_copy_blit,
-        .copy_dma = &r200_copy_dma,
-        .copy = &r100_copy_blit,
-        .get_engine_clock = &radeon_legacy_get_engine_clock,
-        .set_engine_clock = &radeon_legacy_set_engine_clock,
-        .get_memory_clock = &radeon_legacy_get_memory_clock,
-        .set_memory_clock = NULL,
-        .set_pcie_lanes = &rv370_set_pcie_lanes,
-        .set_clock_gating = &radeon_legacy_set_clock_gating,
-        .set_surface_reg = r100_set_surface_reg,
-        .clear_surface_reg = r100_clear_surface_reg,
-        .bandwidth_update = &r100_bandwidth_update,
-        .hpd_init = &r100_hpd_init,
-        .hpd_fini = &r100_hpd_fini,
-        .hpd_sense = &r100_hpd_sense,
-        .hpd_set_polarity = &r100_hpd_set_polarity,
-        .ioctl_wait_idle = NULL,
-};
 /*
 * r420,r423,rv410
 */
@@ -269,44 +162,6 @@ extern int r420_init(struct radeon_device *rdev);
 extern void r420_fini(struct radeon_device *rdev);
 extern int r420_suspend(struct radeon_device *rdev);
 extern int r420_resume(struct radeon_device *rdev);
-static struct radeon_asic r420_asic = {
-        .init = &r420_init,
-        .fini = &r420_fini,
-        .suspend = &r420_suspend,
-        .resume = &r420_resume,
-        .vga_set_state = &r100_vga_set_state,
-        .gpu_reset = &r300_gpu_reset,
-        .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
-        .gart_set_page = &rv370_pcie_gart_set_page,
-        .cp_commit = &r100_cp_commit,
-        .ring_start = &r300_ring_start,
-        .ring_test = &r100_ring_test,
-        .ring_ib_execute = &r100_ring_ib_execute,
-        .irq_set = &r100_irq_set,
-        .irq_process = &r100_irq_process,
-        .get_vblank_counter = &r100_get_vblank_counter,
-        .fence_ring_emit = &r300_fence_ring_emit,
-        .cs_parse = &r300_cs_parse,
-        .copy_blit = &r100_copy_blit,
-        .copy_dma = &r200_copy_dma,
-        .copy = &r100_copy_blit,
-        .get_engine_clock = &radeon_atom_get_engine_clock,
-        .set_engine_clock = &radeon_atom_set_engine_clock,
-        .get_memory_clock = &radeon_atom_get_memory_clock,
-        .set_memory_clock = &radeon_atom_set_memory_clock,
-        .get_pcie_lanes = &rv370_get_pcie_lanes,
-        .set_pcie_lanes = &rv370_set_pcie_lanes,
-        .set_clock_gating = &radeon_atom_set_clock_gating,
-        .set_surface_reg = r100_set_surface_reg,
-        .clear_surface_reg = r100_clear_surface_reg,
-        .bandwidth_update = &r100_bandwidth_update,
-        .hpd_init = &r100_hpd_init,
-        .hpd_fini = &r100_hpd_fini,
-        .hpd_sense = &r100_hpd_sense,
-        .hpd_set_polarity = &r100_hpd_set_polarity,
-        .ioctl_wait_idle = NULL,
-};
 /*
 * rs400,rs480
@@ -319,44 +174,6 @@ void rs400_gart_tlb_flush(struct radeon_device *rdev);
 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
-static struct radeon_asic rs400_asic = {
-        .init = &rs400_init,
-        .fini = &rs400_fini,
-        .suspend = &rs400_suspend,
-        .resume = &rs400_resume,
-        .vga_set_state = &r100_vga_set_state,
-        .gpu_reset = &r300_gpu_reset,
-        .gart_tlb_flush = &rs400_gart_tlb_flush,
-        .gart_set_page = &rs400_gart_set_page,
-        .cp_commit = &r100_cp_commit,
-        .ring_start = &r300_ring_start,
-        .ring_test = &r100_ring_test,
-        .ring_ib_execute = &r100_ring_ib_execute,
-        .irq_set = &r100_irq_set,
-        .irq_process = &r100_irq_process,
-        .get_vblank_counter = &r100_get_vblank_counter,
-        .fence_ring_emit = &r300_fence_ring_emit,
-        .cs_parse = &r300_cs_parse,
-        .copy_blit = &r100_copy_blit,
-        .copy_dma = &r200_copy_dma,
-        .copy = &r100_copy_blit,
-        .get_engine_clock = &radeon_legacy_get_engine_clock,
-        .set_engine_clock = &radeon_legacy_set_engine_clock,
-        .get_memory_clock = &radeon_legacy_get_memory_clock,
-        .set_memory_clock = NULL,
-        .get_pcie_lanes = NULL,
-        .set_pcie_lanes = NULL,
-        .set_clock_gating = &radeon_legacy_set_clock_gating,
-        .set_surface_reg = r100_set_surface_reg,
-        .clear_surface_reg = r100_clear_surface_reg,
-        .bandwidth_update = &r100_bandwidth_update,
-        .hpd_init = &r100_hpd_init,
-        .hpd_fini = &r100_hpd_fini,
-        .hpd_sense = &r100_hpd_sense,
-        .hpd_set_polarity = &r100_hpd_set_polarity,
-        .ioctl_wait_idle = NULL,
-};
 /*
 * rs600.
@@ -379,45 +196,6 @@ bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 void rs600_hpd_set_polarity(struct radeon_device *rdev,
                            enum radeon_hpd_id hpd);
-static struct radeon_asic rs600_asic = {
-        .init = &rs600_init,
-        .fini = &rs600_fini,
-        .suspend = &rs600_suspend,
-        .resume = &rs600_resume,
-        .vga_set_state = &r100_vga_set_state,
-        .gpu_reset = &r300_gpu_reset,
-        .gart_tlb_flush = &rs600_gart_tlb_flush,
-        .gart_set_page = &rs600_gart_set_page,
-        .cp_commit = &r100_cp_commit,
-        .ring_start = &r300_ring_start,
-        .ring_test = &r100_ring_test,
-        .ring_ib_execute = &r100_ring_ib_execute,
-        .irq_set = &rs600_irq_set,
-        .irq_process = &rs600_irq_process,
-        .get_vblank_counter = &rs600_get_vblank_counter,
-        .fence_ring_emit = &r300_fence_ring_emit,
-        .cs_parse = &r300_cs_parse,
-        .copy_blit = &r100_copy_blit,
-        .copy_dma = &r200_copy_dma,
-        .copy = &r100_copy_blit,
-        .get_engine_clock = &radeon_atom_get_engine_clock,
-        .set_engine_clock = &radeon_atom_set_engine_clock,
-        .get_memory_clock = &radeon_atom_get_memory_clock,
-        .set_memory_clock = &radeon_atom_set_memory_clock,
-        .get_pcie_lanes = NULL,
-        .set_pcie_lanes = NULL,
-        .set_clock_gating = &radeon_atom_set_clock_gating,
-        .set_surface_reg = r100_set_surface_reg,
-        .clear_surface_reg = r100_clear_surface_reg,
-        .bandwidth_update = &rs600_bandwidth_update,
-        .hpd_init = &rs600_hpd_init,
-        .hpd_fini = &rs600_hpd_fini,
-        .hpd_sense = &rs600_hpd_sense,
-        .hpd_set_polarity = &rs600_hpd_set_polarity,
-        .ioctl_wait_idle = NULL,
-};
 /*
 * rs690,rs740
 */
@@ -428,44 +206,6 @@ int rs690_suspend(struct radeon_device *rdev);
 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 void rs690_bandwidth_update(struct radeon_device *rdev);
-static struct radeon_asic rs690_asic = {
-        .init = &rs690_init,
-        .fini = &rs690_fini,
-        .suspend = &rs690_suspend,
-        .resume = &rs690_resume,
-        .vga_set_state = &r100_vga_set_state,
-        .gpu_reset = &r300_gpu_reset,
-        .gart_tlb_flush = &rs400_gart_tlb_flush,
-        .gart_set_page = &rs400_gart_set_page,
-        .cp_commit = &r100_cp_commit,
-        .ring_start = &r300_ring_start,
-        .ring_test = &r100_ring_test,
-        .ring_ib_execute = &r100_ring_ib_execute,
-        .irq_set = &rs600_irq_set,
-        .irq_process = &rs600_irq_process,
-        .get_vblank_counter = &rs600_get_vblank_counter,
-        .fence_ring_emit = &r300_fence_ring_emit,
-        .cs_parse = &r300_cs_parse,
-        .copy_blit = &r100_copy_blit,
-        .copy_dma = &r200_copy_dma,
-        .copy = &r200_copy_dma,
-        .get_engine_clock = &radeon_atom_get_engine_clock,
-        .set_engine_clock = &radeon_atom_set_engine_clock,
-        .get_memory_clock = &radeon_atom_get_memory_clock,
-        .set_memory_clock = &radeon_atom_set_memory_clock,
-        .get_pcie_lanes = NULL,
-        .set_pcie_lanes = NULL,
-        .set_clock_gating = &radeon_atom_set_clock_gating,
-        .set_surface_reg = r100_set_surface_reg,
-        .clear_surface_reg = r100_clear_surface_reg,
-        .bandwidth_update = &rs690_bandwidth_update,
-        .hpd_init = &rs600_hpd_init,
-        .hpd_fini = &rs600_hpd_fini,
-        .hpd_sense = &rs600_hpd_sense,
-        .hpd_set_polarity = &rs600_hpd_set_polarity,
-        .ioctl_wait_idle = NULL,
-};
 /*
 * rv515
@@ -481,87 +221,12 @@ void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 void rv515_bandwidth_update(struct radeon_device *rdev);
 int rv515_resume(struct radeon_device *rdev);
 int rv515_suspend(struct radeon_device *rdev);
-static struct radeon_asic rv515_asic = {
-        .init = &rv515_init,
-        .fini = &rv515_fini,
-        .suspend = &rv515_suspend,
-        .resume = &rv515_resume,
-        .vga_set_state = &r100_vga_set_state,
-        .gpu_reset = &rv515_gpu_reset,
-        .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
-        .gart_set_page = &rv370_pcie_gart_set_page,
-        .cp_commit = &r100_cp_commit,
-        .ring_start = &rv515_ring_start,
-        .ring_test = &r100_ring_test,
-        .ring_ib_execute = &r100_ring_ib_execute,
-        .irq_set = &rs600_irq_set,
-        .irq_process = &rs600_irq_process,
-        .get_vblank_counter = &rs600_get_vblank_counter,
-        .fence_ring_emit = &r300_fence_ring_emit,
-        .cs_parse = &r300_cs_parse,
-        .copy_blit = &r100_copy_blit,
-        .copy_dma = &r200_copy_dma,
-        .copy = &r100_copy_blit,
-        .get_engine_clock = &radeon_atom_get_engine_clock,
-        .set_engine_clock = &radeon_atom_set_engine_clock,
-        .get_memory_clock = &radeon_atom_get_memory_clock,
-        .set_memory_clock = &radeon_atom_set_memory_clock,
-        .get_pcie_lanes = &rv370_get_pcie_lanes,
-        .set_pcie_lanes = &rv370_set_pcie_lanes,
-        .set_clock_gating = &radeon_atom_set_clock_gating,
-        .set_surface_reg = r100_set_surface_reg,
-        .clear_surface_reg = r100_clear_surface_reg,
-        .bandwidth_update = &rv515_bandwidth_update,
-        .hpd_init = &rs600_hpd_init,
-        .hpd_fini = &rs600_hpd_fini,
-        .hpd_sense = &rs600_hpd_sense,
-        .hpd_set_polarity = &rs600_hpd_set_polarity,
-        .ioctl_wait_idle = NULL,
-};
 /*
 * r520,rv530,rv560,rv570,r580
 */
 int r520_init(struct radeon_device *rdev);
 int r520_resume(struct radeon_device *rdev);
-static struct radeon_asic r520_asic = {
-        .init = &r520_init,
-        .fini = &rv515_fini,
-        .suspend = &rv515_suspend,
-        .resume = &r520_resume,
-        .vga_set_state = &r100_vga_set_state,
-        .gpu_reset = &rv515_gpu_reset,
-        .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
-        .gart_set_page = &rv370_pcie_gart_set_page,
-        .cp_commit = &r100_cp_commit,
-        .ring_start = &rv515_ring_start,
-        .ring_test = &r100_ring_test,
-        .ring_ib_execute = &r100_ring_ib_execute,
-        .irq_set = &rs600_irq_set,
-        .irq_process = &rs600_irq_process,
-        .get_vblank_counter = &rs600_get_vblank_counter,
-        .fence_ring_emit = &r300_fence_ring_emit,
-        .cs_parse = &r300_cs_parse,
-        .copy_blit = &r100_copy_blit,
-        .copy_dma = &r200_copy_dma,
-        .copy = &r100_copy_blit,
-        .get_engine_clock = &radeon_atom_get_engine_clock,
-        .set_engine_clock = &radeon_atom_set_engine_clock,
-        .get_memory_clock = &radeon_atom_get_memory_clock,
-        .set_memory_clock = &radeon_atom_set_memory_clock,
-        .get_pcie_lanes = &rv370_get_pcie_lanes,
-        .set_pcie_lanes = &rv370_set_pcie_lanes,
-        .set_clock_gating = &radeon_atom_set_clock_gating,
-        .set_surface_reg = r100_set_surface_reg,
-        .clear_surface_reg = r100_clear_surface_reg,
-        .bandwidth_update = &rv515_bandwidth_update,
-        .hpd_init = &rs600_hpd_init,
-        .hpd_fini = &rs600_hpd_fini,
-        .hpd_sense = &rs600_hpd_sense,
-        .hpd_set_polarity = &rs600_hpd_set_polarity,
-        .ioctl_wait_idle = NULL,
-};
 /*
 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
@@ -591,7 +256,7 @@ int r600_gpu_reset(struct radeon_device *rdev);
 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
                         uint32_t tiling_flags, uint32_t pitch,
                         uint32_t offset, uint32_t obj_size);
-int r600_clear_surface_reg(struct radeon_device *rdev, int reg);
+void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 int r600_ring_test(struct radeon_device *rdev);
 int r600_copy_blit(struct radeon_device *rdev,
@@ -604,43 +269,6 @@ void r600_hpd_set_polarity(struct radeon_device *rdev,
                           enum radeon_hpd_id hpd);
 extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
-static struct radeon_asic r600_asic = {
-        .init = &r600_init,
-        .fini = &r600_fini,
-        .suspend = &r600_suspend,
-        .resume = &r600_resume,
-        .cp_commit = &r600_cp_commit,
-        .vga_set_state = &r600_vga_set_state,
-        .gpu_reset = &r600_gpu_reset,
-        .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
-        .gart_set_page = &rs600_gart_set_page,
-        .ring_test = &r600_ring_test,
-        .ring_ib_execute = &r600_ring_ib_execute,
-        .irq_set = &r600_irq_set,
-        .irq_process = &r600_irq_process,
-        .get_vblank_counter = &rs600_get_vblank_counter,
-        .fence_ring_emit = &r600_fence_ring_emit,
-        .cs_parse = &r600_cs_parse,
-        .copy_blit = &r600_copy_blit,
-        .copy_dma = &r600_copy_blit,
-        .copy = &r600_copy_blit,
-        .get_engine_clock = &radeon_atom_get_engine_clock,
-        .set_engine_clock = &radeon_atom_set_engine_clock,
-        .get_memory_clock = &radeon_atom_get_memory_clock,
-        .set_memory_clock = &radeon_atom_set_memory_clock,
-        .get_pcie_lanes = &rv370_get_pcie_lanes,
-        .set_pcie_lanes = NULL,
-        .set_clock_gating = NULL,
-        .set_surface_reg = r600_set_surface_reg,
-        .clear_surface_reg = r600_clear_surface_reg,
-        .bandwidth_update = &rv515_bandwidth_update,
-        .hpd_init = &r600_hpd_init,
-        .hpd_fini = &r600_hpd_fini,
-        .hpd_sense = &r600_hpd_sense,
-        .hpd_set_polarity = &r600_hpd_set_polarity,
-        .ioctl_wait_idle = r600_ioctl_wait_idle,
-};
 /*
 * rv770,rv730,rv710,rv740
 */
@@ -650,43 +278,6 @@ int rv770_suspend(struct radeon_device *rdev);
 int rv770_resume(struct radeon_device *rdev);
 int rv770_gpu_reset(struct radeon_device *rdev);
-static struct radeon_asic rv770_asic = {
-        .init = &rv770_init,
-        .fini = &rv770_fini,
-        .suspend = &rv770_suspend,
-        .resume = &rv770_resume,
-        .cp_commit = &r600_cp_commit,
-        .gpu_reset = &rv770_gpu_reset,
-        .vga_set_state = &r600_vga_set_state,
-        .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
-        .gart_set_page = &rs600_gart_set_page,
-        .ring_test = &r600_ring_test,
-        .ring_ib_execute = &r600_ring_ib_execute,
-        .irq_set = &r600_irq_set,
-        .irq_process = &r600_irq_process,
-        .get_vblank_counter = &rs600_get_vblank_counter,
-        .fence_ring_emit = &r600_fence_ring_emit,
-        .cs_parse = &r600_cs_parse,
-        .copy_blit = &r600_copy_blit,
-        .copy_dma = &r600_copy_blit,
-        .copy = &r600_copy_blit,
-        .get_engine_clock = &radeon_atom_get_engine_clock,
-        .set_engine_clock = &radeon_atom_set_engine_clock,
-        .get_memory_clock = &radeon_atom_get_memory_clock,
-        .set_memory_clock = &radeon_atom_set_memory_clock,
-        .get_pcie_lanes = &rv370_get_pcie_lanes,
-        .set_pcie_lanes = NULL,
-        .set_clock_gating = &radeon_atom_set_clock_gating,
-        .set_surface_reg = r600_set_surface_reg,
-        .clear_surface_reg = r600_clear_surface_reg,
-        .bandwidth_update = &rv515_bandwidth_update,
-        .hpd_init = &r600_hpd_init,
-        .hpd_fini = &r600_hpd_fini,
-        .hpd_sense = &r600_hpd_sense,
-        .hpd_set_polarity = &r600_hpd_set_polarity,
-        .ioctl_wait_idle = r600_ioctl_wait_idle,
-};
 /*
 * evergreen
 */
@@ -701,40 +292,4 @@ void evergreen_hpd_fini(struct radeon_device *rdev);
 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
                                enum radeon_hpd_id hpd);
-static struct radeon_asic evergreen_asic = {
-        .init = &evergreen_init,
-        .fini = &evergreen_fini,
-        .suspend = &evergreen_suspend,
-        .resume = &evergreen_resume,
-        .cp_commit = NULL,
-        .gpu_reset = &evergreen_gpu_reset,
-        .vga_set_state = &r600_vga_set_state,
-        .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
-        .gart_set_page = &rs600_gart_set_page,
-        .ring_test = NULL,
-        .ring_ib_execute = NULL,
-        .irq_set = NULL,
-        .irq_process = NULL,
-        .get_vblank_counter = NULL,
-        .fence_ring_emit = NULL,
-        .cs_parse = NULL,
-        .copy_blit = NULL,
-        .copy_dma = NULL,
-        .copy = NULL,
-        .get_engine_clock = &radeon_atom_get_engine_clock,
-        .set_engine_clock = &radeon_atom_set_engine_clock,
-        .get_memory_clock = &radeon_atom_get_memory_clock,
-        .set_memory_clock = &radeon_atom_set_memory_clock,
-        .set_pcie_lanes = NULL,
-        .set_clock_gating = NULL,
-        .set_surface_reg = r600_set_surface_reg,
-        .clear_surface_reg = r600_clear_surface_reg,
-        .bandwidth_update = &evergreen_bandwidth_update,
-        .hpd_init = &evergreen_hpd_init,
-        .hpd_fini = &evergreen_hpd_fini,
-        .hpd_sense = &evergreen_hpd_sense,
-        .hpd_set_polarity = &evergreen_hpd_set_polarity,
-};
 #endif
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 93783b15c81d..5673665ff216 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -69,52 +69,54 @@ static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_dev
        struct radeon_i2c_bus_rec i2c;
        int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
        struct _ATOM_GPIO_I2C_INFO *i2c_info;
-        uint16_t data_offset;
+        uint16_t data_offset, size;
-        int i;
+        int i, num_indices;
        memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
        i2c.valid = false;
-        atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
+        if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
+                i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
-        i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
+                num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
+                        sizeof(ATOM_GPIO_I2C_ASSIGMENT);
-        for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
-                gpio = &i2c_info->asGPIO_Info[i];
+                for (i = 0; i < num_indices; i++) {
+                        gpio = &i2c_info->asGPIO_Info[i];
-                if (gpio->sucI2cId.ucAccess == id) {
-                        i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
+                        if (gpio->sucI2cId.ucAccess == id) {
-                        i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
+                                i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
-                        i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
+                                i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
-                        i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
+                                i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
-                        i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
+                                i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
-                        i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
+                                i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
-                        i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
+                                i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
-                        i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
+                                i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
-                        i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
+                                i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
-                        i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
+                                i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
-                        i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
+                                i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
-                        i2c.en_data_mask = (1 << gpio->ucDataEnShift);
+                                i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
-                        i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
+                                i2c.en_data_mask = (1 << gpio->ucDataEnShift);
-                        i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
+                                i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
-                        i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
+                                i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
-                        i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
+                                i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
+                                i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
-                        if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
-                                i2c.hw_capable = true;
+                                if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
-                        else
+                                        i2c.hw_capable = true;
-                                i2c.hw_capable = false;
+                                else
+                                        i2c.hw_capable = false;
-                        if (gpio->sucI2cId.ucAccess == 0xa0)
-                                i2c.mm_i2c = true;
+                                if (gpio->sucI2cId.ucAccess == 0xa0)
-                        else
+                                        i2c.mm_i2c = true;
-                                i2c.mm_i2c = false;
+                                else
+                                        i2c.mm_i2c = false;
-                        i2c.i2c_id = gpio->sucI2cId.ucAccess;
+                                i2c.i2c_id = gpio->sucI2cId.ucAccess;
-                        i2c.valid = true;
-                        break;
+                                i2c.valid = true;
+                                break;
+                        }
                }
        }
@@ -135,20 +137,21 @@ static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rd
        memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
        gpio.valid = false;
-        atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset);
+        if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
+                gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
-        gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
+                num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
+                        sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
-        num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
+                for (i = 0; i < num_indices; i++) {
+                        pin = &gpio_info->asGPIO_Pin[i];
-        for (i = 0; i < num_indices; i++) {
+                        if (id == pin->ucGPIO_ID) {
-                pin = &gpio_info->asGPIO_Pin[i];
+                                gpio.id = pin->ucGPIO_ID;
-                if (id == pin->ucGPIO_ID) {
+                                gpio.reg = pin->usGpioPin_AIndex * 4;
-                        gpio.id = pin->ucGPIO_ID;
+                                gpio.mask = (1 << pin->ucGpioPinBitShift);
-                        gpio.reg = pin->usGpioPin_AIndex * 4;
+                                gpio.valid = true;
-                        gpio.mask = (1 << pin->ucGpioPinBitShift);
+                                break;
-                        gpio.valid = true;
+                        }
-                        break;
                }
        }
@@ -264,6 +267,8 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
                if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
                    (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
                        return false;
+                if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
+                        *line_mux = 0x90;
        }
        /* ASUS HD 3600 XT board lists the DVI port as HDMI */
@@ -395,9 +400,7 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
        struct radeon_gpio_rec gpio;
        struct radeon_hpd hpd;
-        atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
+        if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
-        if (data_offset == 0)
                return false;
        if (crev < 2)
@@ -449,37 +452,43 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
                                    GetIndexIntoMasterTable(DATA,
                                                            IntegratedSystemInfo);
-                                atom_parse_data_header(ctx, index, &size, &frev,
+                                if (atom_parse_data_header(ctx, index, &size, &frev,
-                                                       &crev, &igp_offset);
+                                                           &crev, &igp_offset)) {
-                                if (crev >= 2) {
+                                        if (crev >= 2) {
-                                        igp_obj =
+                                                igp_obj =
-                                            (ATOM_INTEGRATED_SYSTEM_INFO_V2
+                                                        (ATOM_INTEGRATED_SYSTEM_INFO_V2
-                                             *) (ctx->bios + igp_offset);
+                                                         *) (ctx->bios + igp_offset);
-                                        if (igp_obj) {
+                                                if (igp_obj) {
-                                                uint32_t slot_config, ct;
+                                                        uint32_t slot_config, ct;
-                                                if (con_obj_num == 1)
+                                                        if (con_obj_num == 1)
-                                                        slot_config =
+                                                                slot_config =
-                                                            igp_obj->
+                                                                        igp_obj->
-                                                            ulDDISlot1Config;
+                                                                        ulDDISlot1Config;
-                                                else
+                                                        else
-                                                        slot_config =
+                                                                slot_config =
-                                                            igp_obj->
+                                                                        igp_obj->
-                                                            ulDDISlot2Config;
+                                                                        ulDDISlot2Config;
-                                                ct = (slot_config >> 16) & 0xff;
+                                                        ct = (slot_config >> 16) & 0xff;
-                                                connector_type =
+                                                        connector_type =
-                                                    object_connector_convert
+                                                                object_connector_convert
-                                                    [ct];
+                                                                [ct];
-                                                connector_object_id = ct;
+                                                        connector_object_id = ct;
-                                                igp_lane_info =
+                                                        igp_lane_info =
-                                                    slot_config & 0xffff;
+                                                                slot_config & 0xffff;
+                                                } else
+                                                        continue;
                                        } else
                                                continue;
-                                } else
+                                } else {
-                                        continue;
+                                        igp_lane_info = 0;
+                                        connector_type =
+                                                object_connector_convert[con_obj_id];
+                                        connector_object_id = con_obj_id;
+                                }
                        } else {
                                igp_lane_info = 0;
                                connector_type =
@@ -627,20 +636,23 @@ static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
                uint8_t frev, crev;
                ATOM_XTMDS_INFO *xtmds;
-                atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
+                if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
-                xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
+                        xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
-                if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
+                        if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
-                        if (connector_type == DRM_MODE_CONNECTOR_DVII)
+                                if (connector_type == DRM_MODE_CONNECTOR_DVII)
-                                return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
+                                        return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
-                        else
+                                else
-                                return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
+                                        return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
-                } else {
+                        } else {
-                        if (connector_type == DRM_MODE_CONNECTOR_DVII)
+                                if (connector_type == DRM_MODE_CONNECTOR_DVII)
-                                return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
+                                        return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
-                        else
+                                else
-                                return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
+                                        return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
-                }
+                        }
+                } else
+                        return supported_devices_connector_object_id_convert
+                                [connector_type];
        } else {
                return supported_devices_connector_object_id_convert
                        [connector_type];
@@ -672,7 +684,8 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct
        int i, j, max_device;
        struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
-        atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
+        if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
+                return false;
        supported_devices =
            (union atom_supported_devices *)(ctx->bios + data_offset);
@@ -865,14 +878,11 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
        struct radeon_pll *mpll = &rdev->clock.mpll;
        uint16_t data_offset;
-        atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
+        if (atom_parse_data_header(mode_info->atom_context, index, NULL,
-                               &crev, &data_offset);
+                                   &frev, &crev, &data_offset)) {
+                firmware_info =
-        firmware_info =
+                        (union firmware_info *)(mode_info->atom_context->bios +
-            (union firmware_info *)(mode_info->atom_context->bios +
+                                                data_offset);
-                                    data_offset);
-        if (firmware_info) {
                /* pixel clocks */
                p1pll->reference_freq =
                    le16_to_cpu(firmware_info->info.usReferenceClock);
@@ -887,6 +897,20 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
                p1pll->pll_out_max =
                    le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
+                if (crev >= 4) {
+                        p1pll->lcd_pll_out_min =
+                                le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
+                        if (p1pll->lcd_pll_out_min == 0)
+                                p1pll->lcd_pll_out_min = p1pll->pll_out_min;
+                        p1pll->lcd_pll_out_max =
+                                le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
+                        if (p1pll->lcd_pll_out_max == 0)
+                                p1pll->lcd_pll_out_max = p1pll->pll_out_max;
+                } else {
+                        p1pll->lcd_pll_out_min = p1pll->pll_out_min;
+                        p1pll->lcd_pll_out_max = p1pll->pll_out_max;
+                }
                if (p1pll->pll_out_min == 0) {
                        if (ASIC_IS_AVIVO(rdev))
                                p1pll->pll_out_min = 64800;
@@ -992,13 +1016,10 @@ bool radeon_atombios_sideport_present(struct radeon_device *rdev)
        u8 frev, crev;
        u16 data_offset;
-        atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
+        if (atom_parse_data_header(mode_info->atom_context, index, NULL,
-                               &crev, &data_offset);
+                                   &frev, &crev, &data_offset)) {
+                igp_info = (union igp_info *)(mode_info->atom_context->bios +
-        igp_info = (union igp_info *)(mode_info->atom_context->bios +
                                      data_offset);
-        if (igp_info) {
                switch (crev) {
                case 1:
                        if (igp_info->info.ucMemoryType & 0xf0)
@@ -1029,14 +1050,12 @@ bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
        uint16_t maxfreq;
        int i;
-        atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
+        if (atom_parse_data_header(mode_info->atom_context, index, NULL,
-                               &crev, &data_offset);
+                                   &frev, &crev, &data_offset)) {
+                tmds_info =
+                        (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
+                                                   data_offset);
-        tmds_info =
-            (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
-                                       data_offset);
-        if (tmds_info) {
                maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
                for (i = 0; i < 4; i++) {
                        tmds->tmds_pll[i].freq =
@@ -1085,13 +1104,11 @@ static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
        if (id > ATOM_MAX_SS_ENTRY)
                return NULL;
-        atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
+        if (atom_parse_data_header(mode_info->atom_context, index, NULL,
-                               &crev, &data_offset);
+                                   &frev, &crev, &data_offset)) {
+                ss_info =
-        ss_info =
+                        (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
-            (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
-        if (ss_info) {
                ss =
                    kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
@@ -1114,30 +1131,6 @@ static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
        return ss;
 }
-static void radeon_atom_apply_lvds_quirks(struct drm_device *dev,
-                                          struct radeon_encoder_atom_dig *lvds)
-{
-        /* Toshiba A300-1BU laptop panel doesn't like new pll divider algo */
-        if ((dev->pdev->device == 0x95c4) &&
-            (dev->pdev->subsystem_vendor == 0x1179) &&
-            (dev->pdev->subsystem_device == 0xff50)) {
-                if ((lvds->native_mode.hdisplay == 1280) &&
-                    (lvds->native_mode.vdisplay == 800))
-                        lvds->pll_algo = PLL_ALGO_LEGACY;
-        }
-        /* Dell Studio 15 laptop panel doesn't like new pll divider algo */
-        if ((dev->pdev->device == 0x95c4) &&
-            (dev->pdev->subsystem_vendor == 0x1028) &&
-            (dev->pdev->subsystem_device == 0x029f)) {
-                if ((lvds->native_mode.hdisplay == 1280) &&
-                    (lvds->native_mode.vdisplay == 800))
-                        lvds->pll_algo = PLL_ALGO_LEGACY;
-        }
-}
 union lvds_info {
        struct _ATOM_LVDS_INFO info;
        struct _ATOM_LVDS_INFO_V12 info_12;
@@ -1156,13 +1149,10 @@ struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
        uint8_t frev, crev;
        struct radeon_encoder_atom_dig *lvds = NULL;
-        atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
+        if (atom_parse_data_header(mode_info->atom_context, index, NULL,
-                               &crev, &data_offset);
+                                   &frev, &crev, &data_offset)) {
+                lvds_info =
-        lvds_info =
+                        (union lvds_info *)(mode_info->atom_context->bios + data_offset);
-            (union lvds_info *)(mode_info->atom_context->bios + data_offset);
-        if (lvds_info) {
                lvds =
                    kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
@@ -1220,9 +1210,6 @@ struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
                                lvds->pll_algo = PLL_ALGO_LEGACY;
                }
-                /* LVDS quirks */
-                radeon_atom_apply_lvds_quirks(dev, lvds);
                encoder->native_mode = lvds->native_mode;
        }
        return lvds;
@@ -1241,11 +1228,11 @@ radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
        uint8_t bg, dac;
        struct radeon_encoder_primary_dac *p_dac = NULL;
-        atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
+        if (atom_parse_data_header(mode_info->atom_context, index, NULL,
+                                   &frev, &crev, &data_offset)) {
-        dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
+                dac_info = (struct _COMPASSIONATE_DATA *)
+                        (mode_info->atom_context->bios + data_offset);
-        if (dac_info) {
                p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
                if (!p_dac)
@@ -1270,7 +1257,9 @@ bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
        u8 frev, crev;
        u16 data_offset, misc;
-        atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
+        if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
+                                    &frev, &crev, &data_offset))
+                return false;
        switch (crev) {
        case 1:
@@ -1362,47 +1351,50 @@ radeon_atombios_get_tv_info(struct radeon_device *rdev)
        struct _ATOM_ANALOG_TV_INFO *tv_info;
        enum radeon_tv_std tv_std = TV_STD_NTSC;
-        atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
+        if (atom_parse_data_header(mode_info->atom_context, index, NULL,
+                                   &frev, &crev, &data_offset)) {
-        tv_info = (struct _ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
+                tv_info = (struct _ATOM_ANALOG_TV_INFO *)
+                        (mode_info->atom_context->bios + data_offset);
-        switch (tv_info->ucTV_BootUpDefaultStandard) {
+                switch (tv_info->ucTV_BootUpDefaultStandard) {
-        case ATOM_TV_NTSC:
+                case ATOM_TV_NTSC:
-                tv_std = TV_STD_NTSC;
+                        tv_std = TV_STD_NTSC;
-                DRM_INFO("Default TV standard: NTSC\n");
+                        DRM_INFO("Default TV standard: NTSC\n");
-                break;
+                        break;
-        case ATOM_TV_NTSCJ:
+                case ATOM_TV_NTSCJ:
-                tv_std = TV_STD_NTSC_J;
+                        tv_std = TV_STD_NTSC_J;
-                DRM_INFO("Default TV standard: NTSC-J\n");
+                        DRM_INFO("Default TV standard: NTSC-J\n");
-                break;
+                        break;
-        case ATOM_TV_PAL:
+                case ATOM_TV_PAL:
-                tv_std = TV_STD_PAL;
+                        tv_std = TV_STD_PAL;
-                DRM_INFO("Default TV standard: PAL\n");
+                        DRM_INFO("Default TV standard: PAL\n");
-                break;
+                        break;
-        case ATOM_TV_PALM:
+                case ATOM_TV_PALM:
-                tv_std = TV_STD_PAL_M;
+                        tv_std = TV_STD_PAL_M;
-                DRM_INFO("Default TV standard: PAL-M\n");
+                        DRM_INFO("Default TV standard: PAL-M\n");
-                break;
+                        break;
-        case ATOM_TV_PALN:
+                case ATOM_TV_PALN:
-                tv_std = TV_STD_PAL_N;
+                        tv_std = TV_STD_PAL_N;
-                DRM_INFO("Default TV standard: PAL-N\n");
+                        DRM_INFO("Default TV standard: PAL-N\n");
-                break;
+                        break;
-        case ATOM_TV_PALCN:
+                case ATOM_TV_PALCN:
-                tv_std = TV_STD_PAL_CN;
+                        tv_std = TV_STD_PAL_CN;
-                DRM_INFO("Default TV standard: PAL-CN\n");
+                        DRM_INFO("Default TV standard: PAL-CN\n");
-                break;
+                        break;
-        case ATOM_TV_PAL60:
+                case ATOM_TV_PAL60:
-                tv_std = TV_STD_PAL_60;
+                        tv_std = TV_STD_PAL_60;
-                DRM_INFO("Default TV standard: PAL-60\n");
+                        DRM_INFO("Default TV standard: PAL-60\n");
-                break;
+                        break;
-        case ATOM_TV_SECAM:
+                case ATOM_TV_SECAM:
-                tv_std = TV_STD_SECAM;
+                        tv_std = TV_STD_SECAM;
-                DRM_INFO("Default TV standard: SECAM\n");
+                        DRM_INFO("Default TV standard: SECAM\n");
-                break;
+                        break;
-        default:
+                default:
-                tv_std = TV_STD_NTSC;
+                        tv_std = TV_STD_NTSC;
-                DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
+                        DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
-                break;
+                        break;
+                }
        }
        return tv_std;
 }
@@ -1420,11 +1412,12 @@ radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
        uint8_t bg, dac;
        struct radeon_encoder_tv_dac *tv_dac = NULL;
-        atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
+        if (atom_parse_data_header(mode_info->atom_context, index, NULL,
+                                   &frev, &crev, &data_offset)) {
-        dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
+                dac_info = (struct _COMPASSIONATE_DATA *)
+                        (mode_info->atom_context->bios + data_offset);
-        if (dac_info) {
                tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
                if (!tv_dac)
@@ -1447,6 +1440,30 @@ radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
        return tv_dac;
 }
+static const char *thermal_controller_names[] = {
+        "NONE",
+        "LM63",
+        "ADM1032",
+        "ADM1030",
+        "MUA6649",
+        "LM64",
+        "F75375",
+        "ASC7512",
+};
+static const char *pp_lib_thermal_controller_names[] = {
+        "NONE",
+        "LM63",
+        "ADM1032",
+        "ADM1030",
+        "MUA6649",
+        "LM64",
+        "F75375",
+        "RV6xx",
+        "RV770",
+        "ADT7473",
+};
 union power_info {
        struct _ATOM_POWERPLAY_INFO info;
        struct _ATOM_POWERPLAY_INFO_V2 info_2;
@@ -1466,15 +1483,22 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
        struct _ATOM_PPLIB_STATE *power_state;
        int num_modes = 0, i, j;
        int state_index = 0, mode_index = 0;
+        struct radeon_i2c_bus_rec i2c_bus;
-        atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
-        power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
        rdev->pm.default_power_state = NULL;
-        if (power_info) {
+        if (atom_parse_data_header(mode_info->atom_context, index, NULL,
+                                   &frev, &crev, &data_offset)) {
+                power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
                if (frev < 4) {
+                        /* add the i2c bus for thermal/fan chip */
+                        if (power_info->info.ucOverdriveThermalController > 0) {
+                                DRM_INFO("Possible %s thermal controller at 0x%02x\n",
+                                         thermal_controller_names[power_info->info.ucOverdriveThermalController],
+                                         power_info->info.ucOverdriveControllerAddress >> 1);
+                                i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
+                                rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
+                        }
                        num_modes = power_info->info.ucNumOfPowerModeEntries;
                        if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
                                num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
@@ -1684,6 +1708,24 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
                                }
                        }
                } else if (frev == 4) {
+                        /* add the i2c bus for thermal/fan chip */
+                        /* no support for internal controller yet */
+                        if (power_info->info_4.sThermalController.ucType > 0) {
+                                if ((power_info->info_4.sThermalController.ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) ||
+                                    (power_info->info_4.sThermalController.ucType == ATOM_PP_THERMALCONTROLLER_RV770)) {
+                                        DRM_INFO("Internal thermal controller %s fan control\n",
+                                                 (power_info->info_4.sThermalController.ucFanParameters &
+                                                  ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
+                                } else {
+                                        DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
+                                                 pp_lib_thermal_controller_names[power_info->info_4.sThermalController.ucType],
+                                                 power_info->info_4.sThermalController.ucI2cAddress >> 1,
+                                                 (power_info->info_4.sThermalController.ucFanParameters &
+                                                  ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
+                                        i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info_4.sThermalController.ucI2cLine);
+                                        rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
+                                }
+                        }
                        for (i = 0; i < power_info->info_4.ucNumStates; i++) {
                                mode_index = 0;
                                power_state = (struct _ATOM_PPLIB_STATE *)
diff --git a/drivers/gpu/drm/radeon/radeon_atpx_handler.c b/drivers/gpu/drm/radeon/radeon_atpx_handler.c
index 3f557c4151e0..ed5dfe58f29c 100644
--- a/drivers/gpu/drm/radeon/radeon_atpx_handler.c
+++ b/drivers/gpu/drm/radeon/radeon_atpx_handler.c
@@ -7,6 +7,7 @@
 * ATPX support for both Intel/ATI
 */
 #include <linux/vga_switcheroo.h>
+#include <linux/slab.h>
 #include <acpi/acpi.h>
 #include <acpi/acpi_bus.h>
 #include <linux/pci.h>
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
index 557240460526..8ad71f701316 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -31,6 +31,7 @@
 #include "atom.h"
 #include <linux/vga_switcheroo.h>
+#include <linux/slab.h>
 /*
 * BIOS.
 */
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index e9ea38ece375..37db8adb2748 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -531,10 +531,7 @@ static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rde
        case CHIP_RS300:
                switch (ddc_line) {
                case RADEON_GPIO_DVI_DDC:
-                        /* in theory this should be hw capable,
+                        i2c.hw_capable = true;
-                         * but it doesn't seem to work
-                         */
-                        i2c.hw_capable = false;
                        break;
                default:
                        i2c.hw_capable = false;
@@ -633,6 +630,8 @@ bool radeon_combios_get_clock_info(struct drm_device *dev)
                p1pll->reference_div = RBIOS16(pll_info + 0x10);
                p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
                p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
+                p1pll->lcd_pll_out_min = p1pll->pll_out_min;
+                p1pll->lcd_pll_out_max = p1pll->pll_out_max;
                if (rev > 9) {
                        p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
@@ -761,7 +760,9 @@ struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
                        dac = RBIOS8(dac_info + 0x3) & 0xf;
                        p_dac->ps2_pdac_adj = (bg << 8) | (dac);
                }
-                found = 1;
+                /* if the values are all zeros, use the table */
+                if (p_dac->ps2_pdac_adj)
+                        found = 1;
        }
        if (!found) /* fallback to defaults */
@@ -896,7 +897,9 @@ struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
                        bg = RBIOS8(dac_info + 0x10) & 0xf;
                        dac = RBIOS8(dac_info + 0x11) & 0xf;
                        tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
-                        found = 1;
+                        /* if the values are all zeros, use the table */
+                        if (tv_dac->ps2_tvdac_adj)
+                                found = 1;
                } else if (rev > 1) {
                        bg = RBIOS8(dac_info + 0xc) & 0xf;
                        dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
@@ -909,7 +912,9 @@ struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
                        bg = RBIOS8(dac_info + 0xe) & 0xf;
                        dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
                        tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
-                        found = 1;
+                        /* if the values are all zeros, use the table */
+                        if (tv_dac->ps2_tvdac_adj)
+                                found = 1;
                }
                tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
        }
@@ -926,7 +931,9 @@ struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
                                    (bg << 16) | (dac << 20);
                                tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
                                tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
-                                found = 1;
+                                /* if the values are all zeros, use the table */
+                                if (tv_dac->ps2_tvdac_adj)
+                                        found = 1;
                        } else {
                                bg = RBIOS8(dac_info + 0x4) & 0xf;
                                dac = RBIOS8(dac_info + 0x5) & 0xf;
@@ -934,7 +941,9 @@ struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
                                    (bg << 16) | (dac << 20);
                                tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
                                tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
-                                found = 1;
+                                /* if the values are all zeros, use the table */
+                                if (tv_dac->ps2_tvdac_adj)
+                                        found = 1;
                        }
                } else {
                        DRM_INFO("No TV DAC info found in BIOS\n");
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index ee0083f982d8..1331351c5178 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -162,12 +162,14 @@ radeon_connector_analog_encoder_conflict_solve(struct drm_connector *connector,
 {
        struct drm_device *dev = connector->dev;
        struct drm_connector *conflict;
+        struct radeon_connector *radeon_conflict;
        int i;
        list_for_each_entry(conflict, &dev->mode_config.connector_list, head) {
                if (conflict == connector)
                        continue;
+                radeon_conflict = to_radeon_connector(conflict);
                for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
                        if (conflict->encoder_ids[i] == 0)
                                break;
@@ -177,6 +179,9 @@ radeon_connector_analog_encoder_conflict_solve(struct drm_connector *connector,
                                if (conflict->status != connector_status_connected)
                                        continue;
+                                if (radeon_conflict->use_digital)
+                                        continue;
                                if (priority == true) {
                                        DRM_INFO("1: conflicting encoders switching off %s\n", drm_get_connector_name(conflict));
                                        DRM_INFO("in favor of %s\n", drm_get_connector_name(connector));
@@ -287,6 +292,7 @@ int radeon_connector_set_property(struct drm_connector *connector, struct drm_pr
        if (property == rdev->mode_info.coherent_mode_property) {
                struct radeon_encoder_atom_dig *dig;
+                bool new_coherent_mode;
                /* need to find digital encoder on connector */
                encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
@@ -299,8 +305,11 @@ int radeon_connector_set_property(struct drm_connector *connector, struct drm_pr
                        return 0;
                dig = radeon_encoder->enc_priv;
-                dig->coherent_mode = val ? true : false;
+                new_coherent_mode = val ? true : false;
-                radeon_property_change_mode(&radeon_encoder->base);
+                if (dig->coherent_mode != new_coherent_mode) {
+                        dig->coherent_mode = new_coherent_mode;
+                        radeon_property_change_mode(&radeon_encoder->base);
+                }
        }
        if (property == rdev->mode_info.tv_std_property) {
@@ -315,7 +324,7 @@ int radeon_connector_set_property(struct drm_connector *connector, struct drm_pr
                radeon_encoder = to_radeon_encoder(encoder);
                if (!radeon_encoder->enc_priv)
                        return 0;
-                if (rdev->is_atom_bios) {
+                if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) {
                        struct radeon_encoder_atom_dac *dac_int;
                        dac_int = radeon_encoder->enc_priv;
                        dac_int->tv_std = val;
@@ -940,7 +949,7 @@ static void radeon_dp_connector_destroy(struct drm_connector *connector)
        if (radeon_connector->edid)
                kfree(radeon_connector->edid);
        if (radeon_dig_connector->dp_i2c_bus)
-                radeon_i2c_destroy_dp(radeon_dig_connector->dp_i2c_bus);
+                radeon_i2c_destroy(radeon_dig_connector->dp_i2c_bus);
        kfree(radeon_connector->con_priv);
        drm_sysfs_connector_remove(connector);
        drm_connector_cleanup(connector);
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
index dc6eba6b96dd..419630dd2075 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -417,8 +417,9 @@ static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
        return -EBUSY;
 }
-static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
+static void radeon_init_pipes(struct drm_device *dev)
 {
+        drm_radeon_private_t *dev_priv = dev->dev_private;
        uint32_t gb_tile_config, gb_pipe_sel = 0;
        if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
@@ -436,11 +437,12 @@ static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
                dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
        } else {
                /* R3xx */
-                if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
+                if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300 &&
+                     dev->pdev->device != 0x4144) ||
                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
                        dev_priv->num_gb_pipes = 2;
                } else {
-                        /* R3Vxx */
+                        /* RV3xx/R300 AD */
                        dev_priv->num_gb_pipes = 1;
                }
        }
@@ -736,7 +738,7 @@ static int radeon_do_engine_reset(struct drm_device * dev)
        /* setup the raster pipes */
        if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
-            radeon_init_pipes(dev_priv);
+            radeon_init_pipes(dev);
        /* Reset the CP ring */
        radeon_do_cp_reset(dev_priv);
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index 70ba02ed7723..f9b0fe002c0a 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -193,9 +193,11 @@ static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
                radeon_bo_list_fence(&parser->validated, parser->ib->fence);
        }
        radeon_bo_list_unreserve(&parser->validated);
-        for (i = 0; i < parser->nrelocs; i++) {
+        if (parser->relocs != NULL) {
-                if (parser->relocs[i].gobj)
+                for (i = 0; i < parser->nrelocs; i++) {
-                        drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
+                        if (parser->relocs[i].gobj)
+                                drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
+                }
        }
        kfree(parser->track);
        kfree(parser->relocs);
@@ -243,7 +245,8 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
        }
        r = radeon_cs_parser_relocs(&parser);
        if (r) {
-                DRM_ERROR("Failed to parse relocation !\n");
+                if (r != -ERESTARTSYS)
+                        DRM_ERROR("Failed to parse relocation %d!\n", r);
                radeon_cs_parser_fini(&parser, r);
                mutex_unlock(&rdev->cs_mutex);
                return r;
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index e28e4ed5f720..7b629e305560 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -26,6 +26,7 @@
 *          Jerome Glisse
 */
 #include <linux/console.h>
+#include <linux/slab.h>
 #include <drm/drmP.h>
 #include <drm/drm_crtc_helper.h>
 #include <drm/radeon_drm.h>
@@ -33,9 +34,56 @@
 #include <linux/vga_switcheroo.h>
 #include "radeon_reg.h"
 #include "radeon.h"
-#include "radeon_asic.h"
 #include "atom.h"
+static const char radeon_family_name[][16] = {
+        "R100",
+        "RV100",
+        "RS100",
+        "RV200",
+        "RS200",
+        "R200",
+        "RV250",
+        "RS300",
+        "RV280",
+        "R300",
+        "R350",
+        "RV350",
+        "RV380",
+        "R420",
+        "R423",
+        "RV410",
+        "RS400",
+        "RS480",
+        "RS600",
+        "RS690",
+        "RS740",
+        "RV515",
+        "R520",
+        "RV530",
+        "RV560",
+        "RV570",
+        "R580",
+        "R600",
+        "RV610",
+        "RV630",
+        "RV670",
+        "RV620",
+        "RV635",
+        "RS780",
+        "RS880",
+        "RV770",
+        "RV730",
+        "RV710",
+        "RV740",
+        "CEDAR",
+        "REDWOOD",
+        "JUNIPER",
+        "CYPRESS",
+        "HEMLOCK",
+        "LAST",
+};
 /*
 * Clear GPU surface registers.
 */
@@ -242,6 +290,36 @@ bool radeon_card_posted(struct radeon_device *rdev)
 }
+void radeon_update_bandwidth_info(struct radeon_device *rdev)
+{
+        fixed20_12 a;
+        u32 sclk, mclk;
+        if (rdev->flags & RADEON_IS_IGP) {
+                sclk = radeon_get_engine_clock(rdev);
+                mclk = rdev->clock.default_mclk;
+                a.full = rfixed_const(100);
+                rdev->pm.sclk.full = rfixed_const(sclk);
+                rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
+                rdev->pm.mclk.full = rfixed_const(mclk);
+                rdev->pm.mclk.full = rfixed_div(rdev->pm.mclk, a);
+                a.full = rfixed_const(16);
+                /* core_bandwidth = sclk(Mhz) * 16 */
+                rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a);
+        } else {
+                sclk = radeon_get_engine_clock(rdev);
+                mclk = radeon_get_memory_clock(rdev);
+                a.full = rfixed_const(100);
+                rdev->pm.sclk.full = rfixed_const(sclk);
+                rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
+                rdev->pm.mclk.full = rfixed_const(mclk);
+                rdev->pm.mclk.full = rfixed_div(rdev->pm.mclk, a);
+        }
+}
 bool radeon_boot_test_post_card(struct radeon_device *rdev)
 {
        if (radeon_card_posted(rdev))
@@ -288,181 +366,6 @@ void radeon_dummy_page_fini(struct radeon_device *rdev)
 }
-/*
- * Registers accessors functions.
- */
-uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
-{
-        DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
-        BUG_ON(1);
-        return 0;
-}
-void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
-{
-        DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
-                  reg, v);
-        BUG_ON(1);
-}
-void radeon_register_accessor_init(struct radeon_device *rdev)
-{
-        rdev->mc_rreg = &radeon_invalid_rreg;
-        rdev->mc_wreg = &radeon_invalid_wreg;
-        rdev->pll_rreg = &radeon_invalid_rreg;
-        rdev->pll_wreg = &radeon_invalid_wreg;
-        rdev->pciep_rreg = &radeon_invalid_rreg;
-        rdev->pciep_wreg = &radeon_invalid_wreg;
-        /* Don't change order as we are overridding accessor. */
-        if (rdev->family < CHIP_RV515) {
-                rdev->pcie_reg_mask = 0xff;
-        } else {
-                rdev->pcie_reg_mask = 0x7ff;
-        }
-        /* FIXME: not sure here */
-        if (rdev->family <= CHIP_R580) {
-                rdev->pll_rreg = &r100_pll_rreg;
-                rdev->pll_wreg = &r100_pll_wreg;
-        }
-        if (rdev->family >= CHIP_R420) {
-                rdev->mc_rreg = &r420_mc_rreg;
-                rdev->mc_wreg = &r420_mc_wreg;
-        }
-        if (rdev->family >= CHIP_RV515) {
-                rdev->mc_rreg = &rv515_mc_rreg;
-                rdev->mc_wreg = &rv515_mc_wreg;
-        }
-        if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
-                rdev->mc_rreg = &rs400_mc_rreg;
-                rdev->mc_wreg = &rs400_mc_wreg;
-        }
-        if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
-                rdev->mc_rreg = &rs690_mc_rreg;
-                rdev->mc_wreg = &rs690_mc_wreg;
-        }
-        if (rdev->family == CHIP_RS600) {
-                rdev->mc_rreg = &rs600_mc_rreg;
-                rdev->mc_wreg = &rs600_mc_wreg;
-        }
-        if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_RV740)) {
-                rdev->pciep_rreg = &r600_pciep_rreg;
-                rdev->pciep_wreg = &r600_pciep_wreg;
-        }
-}
-/*
- * ASIC
- */
-int radeon_asic_init(struct radeon_device *rdev)
-{
-        radeon_register_accessor_init(rdev);
-        switch (rdev->family) {
-        case CHIP_R100:
-        case CHIP_RV100:
-        case CHIP_RS100:
-        case CHIP_RV200:
-        case CHIP_RS200:
-                rdev->asic = &r100_asic;
-                break;
-        case CHIP_R200:
-        case CHIP_RV250:
-        case CHIP_RS300:
-        case CHIP_RV280:
-                rdev->asic = &r200_asic;
-                break;
-        case CHIP_R300:
-        case CHIP_R350:
-        case CHIP_RV350:
-        case CHIP_RV380:
-                if (rdev->flags & RADEON_IS_PCIE)
-                        rdev->asic = &r300_asic_pcie;
-                else
-                        rdev->asic = &r300_asic;
-                break;
-        case CHIP_R420:
-        case CHIP_R423:
-        case CHIP_RV410:
-                rdev->asic = &r420_asic;
-                break;
-        case CHIP_RS400:
-        case CHIP_RS480:
-                rdev->asic = &rs400_asic;
-                break;
-        case CHIP_RS600:
-                rdev->asic = &rs600_asic;
-                break;
-        case CHIP_RS690:
-        case CHIP_RS740:
-                rdev->asic = &rs690_asic;
-                break;
-        case CHIP_RV515:
-                rdev->asic = &rv515_asic;
-                break;
-        case CHIP_R520:
-        case CHIP_RV530:
-        case CHIP_RV560:
-        case CHIP_RV570:
-        case CHIP_R580:
-                rdev->asic = &r520_asic;
-                break;
-        case CHIP_R600:
-        case CHIP_RV610:
-        case CHIP_RV630:
-        case CHIP_RV620:
-        case CHIP_RV635:
-        case CHIP_RV670:
-        case CHIP_RS780:
-        case CHIP_RS880:
-                rdev->asic = &r600_asic;
-                break;
-        case CHIP_RV770:
-        case CHIP_RV730:
-        case CHIP_RV710:
-        case CHIP_RV740:
-                rdev->asic = &rv770_asic;
-                break;
-        case CHIP_CEDAR:
-        case CHIP_REDWOOD:
-        case CHIP_JUNIPER:
-        case CHIP_CYPRESS:
-        case CHIP_HEMLOCK:
-                rdev->asic = &evergreen_asic;
-                break;
-        default:
-                /* FIXME: not supported yet */
-                return -EINVAL;
-        }
-        if (rdev->flags & RADEON_IS_IGP) {
-                rdev->asic->get_memory_clock = NULL;
-                rdev->asic->set_memory_clock = NULL;
-        }
-        return 0;
-}
-/*
- * Wrapper around modesetting bits.
- */
-int radeon_clocks_init(struct radeon_device *rdev)
-{
-        int r;
-        r = radeon_static_clocks_init(rdev->ddev);
-        if (r) {
-                return r;
-        }
-        DRM_INFO("Clocks initialized !\n");
-        return 0;
-}
-void radeon_clocks_fini(struct radeon_device *rdev)
-{
-}
 /* ATOM accessor methods */
 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 {
@@ -567,29 +470,6 @@ static unsigned int radeon_vga_set_decode(void *cookie, bool state)
                return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 }
-void radeon_agp_disable(struct radeon_device *rdev)
-{
-        rdev->flags &= ~RADEON_IS_AGP;
-        if (rdev->family >= CHIP_R600) {
-                DRM_INFO("Forcing AGP to PCIE mode\n");
-                rdev->flags |= RADEON_IS_PCIE;
-        } else if (rdev->family >= CHIP_RV515 ||
-                        rdev->family == CHIP_RV380 ||
-                        rdev->family == CHIP_RV410 ||
-                        rdev->family == CHIP_R423) {
-                DRM_INFO("Forcing AGP to PCIE mode\n");
-                rdev->flags |= RADEON_IS_PCIE;
-                rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
-                rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
-        } else {
-                DRM_INFO("Forcing AGP to PCI mode\n");
-                rdev->flags |= RADEON_IS_PCI;
-                rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
-                rdev->asic->gart_set_page = &r100_pci_gart_set_page;
-        }
-        rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
-}
 void radeon_check_arguments(struct radeon_device *rdev)
 {
        /* vramlimit must be a power of two */
@@ -694,7 +574,6 @@ int radeon_device_init(struct radeon_device *rdev,
        int r;
        int dma_bits;
-        DRM_INFO("radeon: Initializing kernel modesetting.\n");
        rdev->shutdown = false;
        rdev->dev = &pdev->dev;
        rdev->ddev = ddev;
@@ -706,6 +585,10 @@ int radeon_device_init(struct radeon_device *rdev,
        rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
        rdev->gpu_lockup = false;
        rdev->accel_working = false;
+        DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X).\n",
+                radeon_family_name[rdev->family], pdev->vendor, pdev->device);
        /* mutex initialization are all done here so we
         * can recall function without having locking issues */
        mutex_init(&rdev->cs_mutex);
@@ -731,6 +614,14 @@ int radeon_device_init(struct radeon_device *rdev,
                return r;
        radeon_check_arguments(rdev);
+        /* all of the newer IGP chips have an internal gart
+         * However some rs4xx report as AGP, so remove that here.
+         */
+        if ((rdev->family >= CHIP_RS400) &&
+            (rdev->flags & RADEON_IS_IGP)) {
+                rdev->flags &= ~RADEON_IS_AGP;
+        }
        if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
                radeon_agp_disable(rdev);
        }
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index ba8d806dcf39..b8d672828246 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -368,10 +368,9 @@ static bool radeon_setup_enc_conn(struct drm_device *dev)
        if (rdev->bios) {
                if (rdev->is_atom_bios) {
-                        if (rdev->family >= CHIP_R600)
+                        ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
+                        if (ret == false)
                                ret = radeon_get_atom_connector_info_from_object_table(dev);
-                        else
-                                ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
                } else {
                        ret = radeon_get_legacy_connector_info_from_bios(dev);
                        if (ret == false)
@@ -469,10 +468,19 @@ static void radeon_compute_pll_legacy(struct radeon_pll *pll,
        uint32_t best_error = 0xffffffff;
        uint32_t best_vco_diff = 1;
        uint32_t post_div;
+        u32 pll_out_min, pll_out_max;
        DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
        freq = freq * 1000;
+        if (pll->flags & RADEON_PLL_IS_LCD) {
+                pll_out_min = pll->lcd_pll_out_min;
+                pll_out_max = pll->lcd_pll_out_max;
+        } else {
+                pll_out_min = pll->pll_out_min;
+                pll_out_max = pll->pll_out_max;
+        }
        if (pll->flags & RADEON_PLL_USE_REF_DIV)
                min_ref_div = max_ref_div = pll->reference_div;
        else {
@@ -536,10 +544,10 @@ static void radeon_compute_pll_legacy(struct radeon_pll *pll,
                                tmp = (uint64_t)pll->reference_freq * feedback_div;
                                vco = radeon_div(tmp, ref_div);
-                                if (vco < pll->pll_out_min) {
+                                if (vco < pll_out_min) {
                                        min_feed_div = feedback_div + 1;
                                        continue;
-                                } else if (vco > pll->pll_out_max) {
+                                } else if (vco > pll_out_max) {
                                        max_feed_div = feedback_div;
                                        continue;
                                }
@@ -675,6 +683,15 @@ calc_fb_ref_div(struct radeon_pll *pll,
 {
        fixed20_12 ffreq, max_error, error, pll_out, a;
        u32 vco;
+        u32 pll_out_min, pll_out_max;
+        if (pll->flags & RADEON_PLL_IS_LCD) {
+                pll_out_min = pll->lcd_pll_out_min;
+                pll_out_max = pll->lcd_pll_out_max;
+        } else {
+                pll_out_min = pll->pll_out_min;
+                pll_out_max = pll->pll_out_max;
+        }
        ffreq.full = rfixed_const(freq);
        /* max_error = ffreq * 0.0025; */
@@ -686,7 +703,7 @@ calc_fb_ref_div(struct radeon_pll *pll,
                        vco = pll->reference_freq * (((*fb_div) * 10) + (*fb_div_frac));
                        vco = vco / ((*ref_div) * 10);
-                        if ((vco < pll->pll_out_min) || (vco > pll->pll_out_max))
+                        if ((vco < pll_out_min) || (vco > pll_out_max))
                                continue;
                        /* pll_out = vco / post_div; */
@@ -714,6 +731,15 @@ static void radeon_compute_pll_new(struct radeon_pll *pll,
 {
        u32 fb_div = 0, fb_div_frac = 0, post_div = 0, ref_div = 0;
        u32 best_freq = 0, vco_frequency;
+        u32 pll_out_min, pll_out_max;
+        if (pll->flags & RADEON_PLL_IS_LCD) {
+                pll_out_min = pll->lcd_pll_out_min;
+                pll_out_max = pll->lcd_pll_out_max;
+        } else {
+                pll_out_min = pll->pll_out_min;
+                pll_out_max = pll->pll_out_max;
+        }
        /* freq = freq / 10; */
        do_div(freq, 10);
@@ -724,7 +750,7 @@ static void radeon_compute_pll_new(struct radeon_pll *pll,
                        goto done;
                vco_frequency = freq * post_div;
-                if ((vco_frequency < pll->pll_out_min) || (vco_frequency > pll->pll_out_max))
+                if ((vco_frequency < pll_out_min) || (vco_frequency > pll_out_max))
                        goto done;
                if (pll->flags & RADEON_PLL_USE_REF_DIV) {
@@ -749,7 +775,7 @@ static void radeon_compute_pll_new(struct radeon_pll *pll,
                                continue;
                        vco_frequency = freq * post_div;
-                        if ((vco_frequency < pll->pll_out_min) || (vco_frequency > pll->pll_out_max))
+                        if ((vco_frequency < pll_out_min) || (vco_frequency > pll_out_max))
                                continue;
                        if (pll->flags & RADEON_PLL_USE_REF_DIV) {
                                ref_div = pll->reference_div;
@@ -945,6 +971,23 @@ static int radeon_modeset_create_props(struct radeon_device *rdev)
        return 0;
 }
+void radeon_update_display_priority(struct radeon_device *rdev)
+{
+        /* adjustment options for the display watermarks */
+        if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
+                /* set display priority to high for r3xx, rv515 chips
+                 * this avoids flickering due to underflow to the
+                 * display controllers during heavy acceleration.
+                 */
+                if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515))
+                        rdev->disp_priority = 2;
+                else
+                        rdev->disp_priority = 0;
+        } else
+                rdev->disp_priority = radeon_disp_priority;
+}
 int radeon_modeset_init(struct radeon_device *rdev)
 {
        int i;
@@ -976,15 +1019,6 @@ int radeon_modeset_init(struct radeon_device *rdev)
                radeon_combios_check_hardcoded_edid(rdev);
        }
-        if (rdev->flags & RADEON_SINGLE_CRTC)
-                rdev->num_crtc = 1;
-        else {
-                if (ASIC_IS_DCE4(rdev))
-                        rdev->num_crtc = 6;
-                else
-                        rdev->num_crtc = 2;
-        }
        /* allocate crtcs */
        for (i = 0; i < rdev->num_crtc; i++) {
                radeon_crtc_init(rdev->ddev, i);
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 6eec0ece6a6c..4b05563d99e1 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -42,9 +42,11 @@
 * KMS wrapper.
 * - 2.0.0 - initial interface
 * - 2.1.0 - add square tiling interface
+ * - 2.2.0 - add r6xx/r7xx const buffer support
+ * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
 */
 #define KMS_DRIVER_MAJOR        2
-#define KMS_DRIVER_MINOR        1
+#define KMS_DRIVER_MINOR        3
 #define KMS_DRIVER_PATCHLEVEL   0
 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
 int radeon_driver_unload_kms(struct drm_device *dev);
@@ -91,6 +93,8 @@ int radeon_tv = 1;
 int radeon_new_pll = -1;
 int radeon_dynpm = -1;
 int radeon_audio = 1;
+int radeon_disp_priority = 0;
+int radeon_hw_i2c = 0;
 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
 module_param_named(no_wb, radeon_no_wb, int, 0444);
@@ -134,6 +138,12 @@ module_param_named(dynpm, radeon_dynpm, int, 0444);
 MODULE_PARM_DESC(audio, "Audio enable (0 = disable)");
 module_param_named(audio, radeon_audio, int, 0444);
+MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
+module_param_named(disp_priority, radeon_disp_priority, int, 0444);
+MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
+module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
 static int radeon_suspend(struct drm_device *dev, pm_message_t state)
 {
        drm_radeon_private_t *dev_priv = dev->dev_private;
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index ec55f2b23c22..448eba89d1e6 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -107,9 +107,10 @@
 * 1.30- Add support for occlusion queries
 * 1.31- Add support for num Z pipes from GET_PARAM
 * 1.32- fixes for rv740 setup
+ * 1.33- Add r6xx/r7xx const buffer support
 */
 #define DRIVER_MAJOR            1
-#define DRIVER_MINOR            32
+#define DRIVER_MINOR            33
 #define DRIVER_PATCHLEVEL       0
 enum radeon_cp_microcode_version {
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index bc926ea0a530..30293bec0801 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -302,7 +302,7 @@ static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
        }
        if (ASIC_IS_DCE3(rdev) &&
-            (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT))) {
+            (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
                struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
                radeon_dp_set_link_config(connector, mode);
        }
@@ -317,12 +317,8 @@ atombios_dac_setup(struct drm_encoder *encoder, int action)
        struct radeon_device *rdev = dev->dev_private;
        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
        DAC_ENCODER_CONTROL_PS_ALLOCATION args;
-        int index = 0, num = 0;
+        int index = 0;
        struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
-        enum radeon_tv_std tv_std = TV_STD_NTSC;
-        if (dac_info->tv_std)
-                tv_std = dac_info->tv_std;
        memset(&args, 0, sizeof(args));
@@ -330,12 +326,10 @@ atombios_dac_setup(struct drm_encoder *encoder, int action)
        case ENCODER_OBJECT_ID_INTERNAL_DAC1:
        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
                index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
-                num = 1;
                break;
        case ENCODER_OBJECT_ID_INTERNAL_DAC2:
        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
                index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
-                num = 2;
                break;
        }
@@ -346,7 +340,7 @@ atombios_dac_setup(struct drm_encoder *encoder, int action)
        else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
                args.ucDacStandard = ATOM_DAC1_CV;
        else {
-                switch (tv_std) {
+                switch (dac_info->tv_std) {
                case TV_STD_PAL:
                case TV_STD_PAL_M:
                case TV_STD_SCART_PAL:
@@ -377,10 +371,6 @@ atombios_tv_setup(struct drm_encoder *encoder, int action)
        TV_ENCODER_CONTROL_PS_ALLOCATION args;
        int index = 0;
        struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
-        enum radeon_tv_std tv_std = TV_STD_NTSC;
-        if (dac_info->tv_std)
-                tv_std = dac_info->tv_std;
        memset(&args, 0, sizeof(args));
@@ -391,7 +381,7 @@ atombios_tv_setup(struct drm_encoder *encoder, int action)
        if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
                args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
        else {
-                switch (tv_std) {
+                switch (dac_info->tv_std) {
                case TV_STD_NTSC:
                        args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
                        break;
@@ -519,7 +509,8 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
                break;
        }
-        atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
+        if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
+                return;
        switch (frev) {
        case 1:
@@ -593,7 +584,6 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
        }
        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
-        r600_hdmi_enable(encoder, hdmi_detected);
 }
 int
@@ -708,7 +698,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
        struct radeon_connector_atom_dig *dig_connector =
                radeon_get_atom_connector_priv_from_encoder(encoder);
        union dig_encoder_control args;
-        int index = 0, num = 0;
+        int index = 0;
        uint8_t frev, crev;
        if (!dig || !dig_connector)
@@ -724,9 +714,9 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
                else
                        index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
        }
-        num = dig->dig_encoder + 1;
-        atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
+        if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
+                return;
        args.v1.ucAction = action;
        args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
@@ -785,7 +775,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
        struct drm_connector *connector;
        struct radeon_connector *radeon_connector;
        union dig_transmitter_control args;
-        int index = 0, num = 0;
+        int index = 0;
        uint8_t frev, crev;
        bool is_dp = false;
        int pll_id = 0;
@@ -814,7 +804,8 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
                }
        }
-        atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
+        if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
+                return;
        args.v1.ucAction = action;
        if (action == ATOM_TRANSMITTER_ACTION_INIT) {
@@ -860,15 +851,12 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
                switch (radeon_encoder->encoder_id) {
                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
                        args.v3.acConfig.ucTransmitterSel = 0;
-                        num = 0;
                        break;
                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
                        args.v3.acConfig.ucTransmitterSel = 1;
-                        num = 1;
                        break;
                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
                        args.v3.acConfig.ucTransmitterSel = 2;
-                        num = 2;
                        break;
                }
@@ -877,25 +865,23 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
                else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
                        if (dig->coherent_mode)
                                args.v3.acConfig.fCoherentMode = 1;
+                        if (radeon_encoder->pixel_clock > 165000)
+                                args.v3.acConfig.fDualLinkConnector = 1;
                }
        } else if (ASIC_IS_DCE32(rdev)) {
-                if (dig->dig_encoder == 1)
+                args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
-                        args.v2.acConfig.ucEncoderSel = 1;
                if (dig_connector->linkb)
                        args.v2.acConfig.ucLinkSel = 1;
                switch (radeon_encoder->encoder_id) {
                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
                        args.v2.acConfig.ucTransmitterSel = 0;
-                        num = 0;
                        break;
                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
                        args.v2.acConfig.ucTransmitterSel = 1;
-                        num = 1;
                        break;
                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
                        args.v2.acConfig.ucTransmitterSel = 2;
-                        num = 2;
                        break;
                }
@@ -904,6 +890,8 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
                else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
                        if (dig->coherent_mode)
                                args.v2.acConfig.fCoherentMode = 1;
+                        if (radeon_encoder->pixel_clock > 165000)
+                                args.v2.acConfig.fDualLinkConnector = 1;
                }
        } else {
                args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
@@ -913,31 +901,25 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
                else
                        args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
-                switch (radeon_encoder->encoder_id) {
+                if ((rdev->flags & RADEON_IS_IGP) &&
-                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+                    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
-                        if (rdev->flags & RADEON_IS_IGP) {
+                        if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
-                                if (radeon_encoder->pixel_clock > 165000) {
+                                if (dig_connector->igp_lane_info & 0x1)
-                                        if (dig_connector->igp_lane_info & 0x3)
+                                        args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
-                                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
+                                else if (dig_connector->igp_lane_info & 0x2)
-                                        else if (dig_connector->igp_lane_info & 0xc)
+                                        args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
-                                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
+                                else if (dig_connector->igp_lane_info & 0x4)
-                                } else {
+                                        args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
-                                        if (dig_connector->igp_lane_info & 0x1)
+                                else if (dig_connector->igp_lane_info & 0x8)
-                                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
+                                        args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
-                                        else if (dig_connector->igp_lane_info & 0x2)
+                        } else {
-                                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
+                                if (dig_connector->igp_lane_info & 0x3)
-                                        else if (dig_connector->igp_lane_info & 0x4)
+                                        args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
-                                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
+                                else if (dig_connector->igp_lane_info & 0xc)
-                                        else if (dig_connector->igp_lane_info & 0x8)
+                                        args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
-                                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
-                                }
                        }
-                        break;
                }
-                if (radeon_encoder->pixel_clock > 165000)
-                        args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
                if (dig_connector->linkb)
                        args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
                else
@@ -948,6 +930,8 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
                else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
                        if (dig->coherent_mode)
                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
+                        if (radeon_encoder->pixel_clock > 165000)
+                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
                }
        }
@@ -1054,16 +1038,25 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
        if (is_dig) {
                switch (mode) {
                case DRM_MODE_DPMS_ON:
-                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
+                        if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
-                        {
                                struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
                                dp_link_train(encoder, connector);
+                                if (ASIC_IS_DCE4(rdev))
+                                        atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON);
                        }
+                        if (!ASIC_IS_DCE4(rdev))
+                                atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
                        break;
                case DRM_MODE_DPMS_STANDBY:
                case DRM_MODE_DPMS_SUSPEND:
                case DRM_MODE_DPMS_OFF:
-                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
+                        if (!ASIC_IS_DCE4(rdev))
+                                atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
+                        if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
+                                if (ASIC_IS_DCE4(rdev))
+                                        atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF);
+                        }
                        break;
                }
        } else {
@@ -1104,7 +1097,8 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
        memset(&args, 0, sizeof(args));
-        atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
+        if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
+                return;
        switch (frev) {
        case 1:
@@ -1216,6 +1210,9 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
        }
        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+        /* update scratch regs with new routing */
+        radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 }
 static void
@@ -1326,19 +1323,9 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
        struct drm_device *dev = encoder->dev;
        struct radeon_device *rdev = dev->dev_private;
        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
-        struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
-        if (radeon_encoder->active_device &
-            (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
-                struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
-                if (dig)
-                        dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
-        }
        radeon_encoder->pixel_clock = adjusted_mode->clock;
-        radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
-        atombios_set_encoder_crtc_source(encoder);
        if (ASIC_IS_AVIVO(rdev)) {
                if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
                        atombios_yuv_setup(encoder, true);
@@ -1390,15 +1377,20 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
        case ENCODER_OBJECT_ID_INTERNAL_DAC2:
        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
                atombios_dac_setup(encoder, ATOM_ENABLE);
-                if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
+                if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
-                        atombios_tv_setup(encoder, ATOM_ENABLE);
+                        if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
+                                atombios_tv_setup(encoder, ATOM_ENABLE);
+                        else
+                                atombios_tv_setup(encoder, ATOM_DISABLE);
+                }
                break;
        }
        atombios_apply_encoder_quirks(encoder, adjusted_mode);
-        /* XXX */
+        if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
-        if (!ASIC_IS_DCE4(rdev))
+                r600_hdmi_enable(encoder);
                r600_hdmi_setmode(encoder, adjusted_mode);
+        }
 }
 static bool
@@ -1418,7 +1410,8 @@ atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *conn
                memset(&args, 0, sizeof(args));
-                atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
+                if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
+                        return false;
                args.sDacload.ucMisc = 0;
@@ -1492,8 +1485,20 @@ radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connec
 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
 {
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        if (radeon_encoder->active_device &
+            (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
+                struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
+                if (dig)
+                        dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
+        }
        radeon_atom_output_lock(encoder, true);
        radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
+        /* this is needed for the pll/ss setup to work correctly in some cases */
+        atombios_set_encoder_crtc_source(encoder);
 }
 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
@@ -1509,6 +1514,8 @@ static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
        radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
        if (radeon_encoder_is_digital(encoder)) {
+                if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
+                        r600_hdmi_disable(encoder);
                dig = radeon_encoder->enc_priv;
                dig->dig_encoder = -1;
        }
@@ -1549,12 +1556,14 @@ static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
 struct radeon_encoder_atom_dac *
 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
 {
+        struct drm_device *dev = radeon_encoder->base.dev;
+        struct radeon_device *rdev = dev->dev_private;
        struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
        if (!dac)
                return NULL;
-        dac->tv_std = TV_STD_NTSC;
+        dac->tv_std = radeon_atombios_get_tv_info(rdev);
        return dac;
 }
@@ -1632,6 +1641,7 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su
                break;
        case ENCODER_OBJECT_ID_INTERNAL_DAC1:
                drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
+                radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
                drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
                break;
        case ENCODER_OBJECT_ID_INTERNAL_DAC2:
@@ -1659,6 +1669,4 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su
                drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
                break;
        }
-        r600_hdmi_init(encoder);
 }
diff --git a/drivers/gpu/drm/radeon/radeon_family.h b/drivers/gpu/drm/radeon/radeon_family.h
index 93c7d5d41914..e329066dcabd 100644
--- a/drivers/gpu/drm/radeon/radeon_family.h
+++ b/drivers/gpu/drm/radeon/radeon_family.h
@@ -36,7 +36,7 @@
 * Radeon chip families
 */
 enum radeon_family {
-        CHIP_R100,
+        CHIP_R100 = 0,
        CHIP_RV100,
        CHIP_RS100,
        CHIP_RV200,
@@ -99,4 +99,5 @@ enum radeon_chip_flags {
        RADEON_IS_PCI = 0x00800000UL,
        RADEON_IS_IGPGART = 0x01000000UL,
 };
 #endif
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index 8fccbf29235e..9ac57a09784b 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -28,6 +28,7 @@
     */
 #include <linux/module.h>
+#include <linux/slab.h>
 #include <linux/fb.h>
 #include "drmP.h"
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index 8495d4e32e18..d90f95b405c5 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -33,6 +33,7 @@
 #include <linux/wait.h>
 #include <linux/list.h>
 #include <linux/kref.h>
+#include <linux/slab.h>
 #include "drmP.h"
 #include "drm.h"
 #include "radeon_reg.h"
diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c
index 4ae50c19589f..5def6f5dff38 100644
--- a/drivers/gpu/drm/radeon/radeon_i2c.c
+++ b/drivers/gpu/drm/radeon/radeon_i2c.c
@@ -59,6 +59,7 @@ bool radeon_ddc_probe(struct radeon_connector *radeon_connector)
        return false;
 }
+/* bit banging i2c */
 static void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state)
 {
@@ -181,13 +182,30 @@ static void set_data(void *i2c_priv, int data)
        WREG32(rec->en_data_reg, val);
 }
+static int pre_xfer(struct i2c_adapter *i2c_adap)
+{
+        struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
+        radeon_i2c_do_lock(i2c, 1);
+        return 0;
+}
+static void post_xfer(struct i2c_adapter *i2c_adap)
+{
+        struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
+        radeon_i2c_do_lock(i2c, 0);
+}
+/* hw i2c */
 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
 {
-        struct radeon_pll *spll = &rdev->clock.spll;
        u32 sclk = radeon_get_engine_clock(rdev);
        u32 prescale = 0;
-        u32 n, m;
+        u32 nm;
-        u8 loop;
+        u8 n, m, loop;
        int i2c_clock;
        switch (rdev->family) {
@@ -203,13 +221,15 @@ static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
        case CHIP_R300:
        case CHIP_R350:
        case CHIP_RV350:
-                n = (spll->reference_freq) / (4 * 6);
+                i2c_clock = 60;
+                nm = (sclk * 10) / (i2c_clock * 4);
                for (loop = 1; loop < 255; loop++) {
-                        if ((loop * (loop - 1)) > n)
+                        if ((nm / loop) < loop)
                                break;
                }
-                m = loop - 1;
+                n = loop - 1;
-                prescale = m | (loop << 8);
+                m = loop - 2;
+                prescale = m | (n << 8);
                break;
        case CHIP_RV380:
        case CHIP_RS400:
@@ -217,7 +237,6 @@ static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
        case CHIP_R420:
        case CHIP_R423:
        case CHIP_RV410:
-                sclk = radeon_get_engine_clock(rdev);
                prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
                break;
        case CHIP_RS600:
@@ -232,7 +251,6 @@ static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
        case CHIP_RV570:
        case CHIP_R580:
                i2c_clock = 50;
-                sclk = radeon_get_engine_clock(rdev);
                if (rdev->family == CHIP_R520)
                        prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
                else
@@ -291,6 +309,7 @@ static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
        prescale = radeon_get_i2c_prescale(rdev);
        reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |
+               RADEON_I2C_DRIVE_EN |
               RADEON_I2C_START |
               RADEON_I2C_STOP |
               RADEON_I2C_GO);
@@ -757,26 +776,13 @@ done:
        return ret;
 }
-static int radeon_sw_i2c_xfer(struct i2c_adapter *i2c_adap,
+static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
                              struct i2c_msg *msgs, int num)
 {
        struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
-        int ret;
-        radeon_i2c_do_lock(i2c, 1);
-        ret = i2c_transfer(&i2c->algo.radeon.bit_adapter, msgs, num);
-        radeon_i2c_do_lock(i2c, 0);
-        return ret;
-}
-static int radeon_i2c_xfer(struct i2c_adapter *i2c_adap,
-                           struct i2c_msg *msgs, int num)
-{
-        struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
        struct radeon_device *rdev = i2c->dev->dev_private;
        struct radeon_i2c_bus_rec *rec = &i2c->rec;
-        int ret;
+        int ret = 0;
        switch (rdev->family) {
        case CHIP_R100:
@@ -797,16 +803,12 @@ static int radeon_i2c_xfer(struct i2c_adapter *i2c_adap,
        case CHIP_RV410:
        case CHIP_RS400:
        case CHIP_RS480:
-                if (rec->hw_capable)
+                ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
-                        ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
-                else
-                        ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
                break;
        case CHIP_RS600:
        case CHIP_RS690:
        case CHIP_RS740:
                /* XXX fill in hw i2c implementation */
-                ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
                break;
        case CHIP_RV515:
        case CHIP_R520:
@@ -814,20 +816,16 @@ static int radeon_i2c_xfer(struct i2c_adapter *i2c_adap,
        case CHIP_RV560:
        case CHIP_RV570:
        case CHIP_R580:
-                if (rec->hw_capable) {
+                if (rec->mm_i2c)
-                        if (rec->mm_i2c)
+                        ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
-                                ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
+                else
-                        else
+                        ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);
-                                ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);
-                } else
-                        ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
                break;
        case CHIP_R600:
        case CHIP_RV610:
        case CHIP_RV630:
        case CHIP_RV670:
                /* XXX fill in hw i2c implementation */
-                ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
                break;
        case CHIP_RV620:
        case CHIP_RV635:
@@ -838,7 +836,6 @@ static int radeon_i2c_xfer(struct i2c_adapter *i2c_adap,
        case CHIP_RV710:
        case CHIP_RV740:
                /* XXX fill in hw i2c implementation */
-                ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
                break;
        case CHIP_CEDAR:
        case CHIP_REDWOOD:
@@ -846,7 +843,6 @@ static int radeon_i2c_xfer(struct i2c_adapter *i2c_adap,
        case CHIP_CYPRESS:
        case CHIP_HEMLOCK:
                /* XXX fill in hw i2c implementation */
-                ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
                break;
        default:
                DRM_ERROR("i2c: unhandled radeon chip\n");
@@ -857,20 +853,21 @@ static int radeon_i2c_xfer(struct i2c_adapter *i2c_adap,
        return ret;
 }
-static u32 radeon_i2c_func(struct i2c_adapter *adap)
+static u32 radeon_hw_i2c_func(struct i2c_adapter *adap)
 {
        return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 }
 static const struct i2c_algorithm radeon_i2c_algo = {
-        .master_xfer = radeon_i2c_xfer,
+        .master_xfer = radeon_hw_i2c_xfer,
-        .functionality = radeon_i2c_func,
+        .functionality = radeon_hw_i2c_func,
 };
 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
                                          struct radeon_i2c_bus_rec *rec,
                                          const char *name)
 {
+        struct radeon_device *rdev = dev->dev_private;
        struct radeon_i2c_chan *i2c;
        int ret;
@@ -878,37 +875,43 @@ struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
        if (i2c == NULL)
                return NULL;
-        /* set the internal bit adapter */
-        i2c->algo.radeon.bit_adapter.owner = THIS_MODULE;
-        i2c_set_adapdata(&i2c->algo.radeon.bit_adapter, i2c);
-        sprintf(i2c->algo.radeon.bit_adapter.name, "Radeon internal i2c bit bus %s", name);
-        i2c->algo.radeon.bit_adapter.algo_data = &i2c->algo.radeon.bit_data;
-        i2c->algo.radeon.bit_data.setsda = set_data;
-        i2c->algo.radeon.bit_data.setscl = set_clock;
-        i2c->algo.radeon.bit_data.getsda = get_data;
-        i2c->algo.radeon.bit_data.getscl = get_clock;
-        i2c->algo.radeon.bit_data.udelay = 20;
-        /* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always
-         * make this, 2 jiffies is a lot more reliable */
-        i2c->algo.radeon.bit_data.timeout = 2;
-        i2c->algo.radeon.bit_data.data = i2c;
-        ret = i2c_bit_add_bus(&i2c->algo.radeon.bit_adapter);
-        if (ret) {
-                DRM_ERROR("Failed to register internal bit i2c %s\n", name);
-                goto out_free;
-        }
-        /* set the radeon i2c adapter */
-        i2c->dev = dev;
        i2c->rec = *rec;
        i2c->adapter.owner = THIS_MODULE;
+        i2c->dev = dev;
        i2c_set_adapdata(&i2c->adapter, i2c);
-        sprintf(i2c->adapter.name, "Radeon i2c %s", name);
+        if (rec->mm_i2c ||
-        i2c->adapter.algo_data = &i2c->algo.radeon;
+            (rec->hw_capable &&
-        i2c->adapter.algo = &radeon_i2c_algo;
+             radeon_hw_i2c &&
-        ret = i2c_add_adapter(&i2c->adapter);
+             ((rdev->family <= CHIP_RS480) ||
-        if (ret) {
+              ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) {
-                DRM_ERROR("Failed to register i2c %s\n", name);
+                /* set the radeon hw i2c adapter */
-                goto out_free;
+                sprintf(i2c->adapter.name, "Radeon i2c hw bus %s", name);
+                i2c->adapter.algo = &radeon_i2c_algo;
+                ret = i2c_add_adapter(&i2c->adapter);
+                if (ret) {
+                        DRM_ERROR("Failed to register hw i2c %s\n", name);
+                        goto out_free;
+                }
+        } else {
+                /* set the radeon bit adapter */
+                sprintf(i2c->adapter.name, "Radeon i2c bit bus %s", name);
+                i2c->adapter.algo_data = &i2c->algo.bit;
+                i2c->algo.bit.pre_xfer = pre_xfer;
+                i2c->algo.bit.post_xfer = post_xfer;
+                i2c->algo.bit.setsda = set_data;
+                i2c->algo.bit.setscl = set_clock;
+                i2c->algo.bit.getsda = get_data;
+                i2c->algo.bit.getscl = get_clock;
+                i2c->algo.bit.udelay = 20;
+                /* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always
+                 * make this, 2 jiffies is a lot more reliable */
+                i2c->algo.bit.timeout = 2;
+                i2c->algo.bit.data = i2c;
+                ret = i2c_bit_add_bus(&i2c->adapter);
+                if (ret) {
+                        DRM_ERROR("Failed to register bit i2c %s\n", name);
+                        goto out_free;
+                }
        }
        return i2c;
@@ -953,16 +956,6 @@ void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
 {
        if (!i2c)
                return;
-        i2c_del_adapter(&i2c->algo.radeon.bit_adapter);
-        i2c_del_adapter(&i2c->adapter);
-        kfree(i2c);
-}
-void radeon_i2c_destroy_dp(struct radeon_i2c_chan *i2c)
-{
-        if (!i2c)
-                return;
        i2c_del_adapter(&i2c->adapter);
        kfree(i2c);
 }
diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
index 3cfd60fd0083..a212041e8b0b 100644
--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -67,9 +67,10 @@ void radeon_driver_irq_preinstall_kms(struct drm_device *dev)
        /* Disable *all* interrupts */
        rdev->irq.sw_int = false;
-        for (i = 0; i < 2; i++) {
+        for (i = 0; i < rdev->num_crtc; i++)
                rdev->irq.crtc_vblank_int[i] = false;
-        }
+        for (i = 0; i < 6; i++)
+                rdev->irq.hpd[i] = false;
        radeon_irq_set(rdev);
        /* Clear bits */
        radeon_irq_process(rdev);
@@ -95,34 +96,29 @@ void radeon_driver_irq_uninstall_kms(struct drm_device *dev)
        }
        /* Disable *all* interrupts */
        rdev->irq.sw_int = false;
-        for (i = 0; i < 2; i++) {
+        for (i = 0; i < rdev->num_crtc; i++)
                rdev->irq.crtc_vblank_int[i] = false;
+        for (i = 0; i < 6; i++)
                rdev->irq.hpd[i] = false;
-        }
        radeon_irq_set(rdev);
 }
 int radeon_irq_kms_init(struct radeon_device *rdev)
 {
        int r = 0;
-        int num_crtc = 2;
-        if (rdev->flags & RADEON_SINGLE_CRTC)
-                num_crtc = 1;
        spin_lock_init(&rdev->irq.sw_lock);
-        r = drm_vblank_init(rdev->ddev, num_crtc);
+        r = drm_vblank_init(rdev->ddev, rdev->num_crtc);
        if (r) {
                return r;
        }
        /* enable msi */
        rdev->msi_enabled = 0;
-        /* MSIs don't seem to work on my rs780;
+        /* MSIs don't seem to work reliably on all IGP
-         * not sure about rs880 or other rs780s.
+         * chips.  Disable MSI on them for now.
-         * Needs more investigation.
         */
        if ((rdev->family >= CHIP_RV380) &&
-            (rdev->family != CHIP_RS780) &&
+            (!(rdev->flags & RADEON_IS_IGP))) {
-            (rdev->family != CHIP_RS880)) {
                int ret = pci_enable_msi(rdev->pdev);
                if (!ret) {
                        rdev->msi_enabled = 1;
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index 20ec276e7596..d3657dcfdd26 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -31,6 +31,7 @@
 #include "radeon_drm.h"
 #include <linux/vga_switcheroo.h>
+#include <linux/slab.h>
 int radeon_driver_unload_kms(struct drm_device *dev)
 {
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index df23d6a01d02..88865e38fe30 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -603,6 +603,10 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
                                      ? RADEON_CRTC2_INTERLACE_EN
                                      : 0));
+                /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
+                if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
+                        crtc2_gen_cntl |= RADEON_CRTC2_EN;
                disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
                disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
@@ -630,6 +634,10 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
                                    ? RADEON_CRTC_INTERLACE_EN
                                    : 0));
+                /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
+                if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
+                        crtc_gen_cntl |= RADEON_CRTC_EN;
                crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
                crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
                                  RADEON_CRTC_VSYNC_DIS |
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index cf389ce50a8a..2441cca7d775 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -830,8 +830,8 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
                                crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
                        if (rdev->family == CHIP_R420 ||
-                                        rdev->family == CHIP_R423 ||
+                            rdev->family == CHIP_R423 ||
-                                        rdev->family == CHIP_RV410)
+                            rdev->family == CHIP_RV410)
                                tv_dac_cntl |= (R420_TV_DAC_RDACPD |
                                                R420_TV_DAC_GDACPD |
                                                R420_TV_DAC_BDACPD |
@@ -907,35 +907,43 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
        if (rdev->family != CHIP_R200) {
                tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
                if (rdev->family == CHIP_R420 ||
-                                rdev->family == CHIP_R423 ||
+                    rdev->family == CHIP_R423 ||
-                                rdev->family == CHIP_RV410) {
+                    rdev->family == CHIP_RV410) {
                        tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
-                                        RADEON_TV_DAC_BGADJ_MASK |
+                                         RADEON_TV_DAC_BGADJ_MASK |
-                                        R420_TV_DAC_DACADJ_MASK |
+                                         R420_TV_DAC_DACADJ_MASK |
-                                        R420_TV_DAC_RDACPD |
+                                         R420_TV_DAC_RDACPD |
-                                        R420_TV_DAC_GDACPD |
+                                         R420_TV_DAC_GDACPD |
-                                        R420_TV_DAC_BDACPD |
+                                         R420_TV_DAC_BDACPD |
-                                        R420_TV_DAC_TVENABLE);
+                                         R420_TV_DAC_TVENABLE);
                } else {
                        tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
-                                        RADEON_TV_DAC_BGADJ_MASK |
+                                         RADEON_TV_DAC_BGADJ_MASK |
-                                        RADEON_TV_DAC_DACADJ_MASK |
+                                         RADEON_TV_DAC_DACADJ_MASK |
-                                        RADEON_TV_DAC_RDACPD |
+                                         RADEON_TV_DAC_RDACPD |
-                                        RADEON_TV_DAC_GDACPD |
+                                         RADEON_TV_DAC_GDACPD |
-                                        RADEON_TV_DAC_BDACPD);
+                                         RADEON_TV_DAC_BDACPD);
                }
-                /*  FIXME TV */
+                tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
-                if (tv_dac) {
-                        struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
+                if (is_tv) {
-                        tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
+                        if (tv_dac->tv_std == TV_STD_NTSC ||
-                                        RADEON_TV_DAC_NHOLD |
+                            tv_dac->tv_std == TV_STD_NTSC_J ||
-                                        RADEON_TV_DAC_STD_PS2 |
+                            tv_dac->tv_std == TV_STD_PAL_M ||
-                                        tv_dac->ps2_tvdac_adj);
+                            tv_dac->tv_std == TV_STD_PAL_60)
+                                tv_dac_cntl |= tv_dac->ntsc_tvdac_adj;
+                        else
+                                tv_dac_cntl |= tv_dac->pal_tvdac_adj;
+                        if (tv_dac->tv_std == TV_STD_NTSC ||
+                            tv_dac->tv_std == TV_STD_NTSC_J)
+                                tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
+                        else
+                                tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
                } else
-                        tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
+                        tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 |
-                                        RADEON_TV_DAC_NHOLD |
+                                        tv_dac->ps2_tvdac_adj);
-                                        RADEON_TV_DAC_STD_PS2);
                WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
        }
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_tv.c b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
index 417684daef4c..f2ed27c8055b 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_tv.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
@@ -57,6 +57,10 @@
 #define NTSC_TV_PLL_N_14 693
 #define NTSC_TV_PLL_P_14 7
+#define PAL_TV_PLL_M_14 19
+#define PAL_TV_PLL_N_14 353
+#define PAL_TV_PLL_P_14 5
 #define VERT_LEAD_IN_LINES 2
 #define FRAC_BITS 0xe
 #define FRAC_MASK 0x3fff
@@ -205,9 +209,24 @@ static const struct radeon_tv_mode_constants available_tv_modes[] = {
                630627,             /* defRestart */
                347,                /* crtcPLL_N */
                14,                 /* crtcPLL_M */
-                        8,                  /* crtcPLL_postDiv */
+                8,                  /* crtcPLL_postDiv */
                1022,               /* pixToTV */
        },
+        { /* PAL timing for 14 Mhz ref clk */
+                800,                /* horResolution */
+                600,                /* verResolution */
+                TV_STD_PAL,         /* standard */
+                1131,               /* horTotal */
+                742,                /* verTotal */
+                813,                /* horStart */
+                840,                /* horSyncStart */
+                633,                /* verSyncStart */
+                708369,             /* defRestart */
+                211,                /* crtcPLL_N */
+                9,                  /* crtcPLL_M */
+                8,                  /* crtcPLL_postDiv */
+                759,                /* pixToTV */
+        },
 };
 #define N_AVAILABLE_MODES ARRAY_SIZE(available_tv_modes)
@@ -242,7 +261,7 @@ static const struct radeon_tv_mode_constants *radeon_legacy_tv_get_std_mode(stru
                if (pll->reference_freq == 2700)
                        const_ptr = &available_tv_modes[1];
                else
-                        const_ptr = &available_tv_modes[1]; /* FIX ME */
+                        const_ptr = &available_tv_modes[3];
        }
        return const_ptr;
 }
@@ -685,9 +704,9 @@ void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
                        n = PAL_TV_PLL_N_27;
                        p = PAL_TV_PLL_P_27;
                } else {
-                        m = PAL_TV_PLL_M_27;
+                        m = PAL_TV_PLL_M_14;
-                        n = PAL_TV_PLL_N_27;
+                        n = PAL_TV_PLL_N_14;
-                        p = PAL_TV_PLL_P_27;
+                        p = PAL_TV_PLL_P_14;
                }
        }
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 1702b820aa4d..0b8e32776b10 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -129,6 +129,7 @@ struct radeon_tmds_pll {
 #define RADEON_PLL_USE_FRAC_FB_DIV      (1 << 10)
 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
 #define RADEON_PLL_USE_POST_DIV         (1 << 12)
+#define RADEON_PLL_IS_LCD               (1 << 13)
 /* pll algo */
 enum radeon_pll_algo {
@@ -149,6 +150,8 @@ struct radeon_pll {
        uint32_t pll_in_max;
        uint32_t pll_out_min;
        uint32_t pll_out_max;
+        uint32_t lcd_pll_out_min;
+        uint32_t lcd_pll_out_max;
        uint32_t best_vco;
        /* divider limits */
@@ -170,17 +173,12 @@ struct radeon_pll {
        enum radeon_pll_algo algo;
 };
-struct i2c_algo_radeon_data {
-        struct i2c_adapter bit_adapter;
-        struct i2c_algo_bit_data bit_data;
-};
 struct radeon_i2c_chan {
        struct i2c_adapter adapter;
        struct drm_device *dev;
        union {
+                struct i2c_algo_bit_data bit;
                struct i2c_algo_dp_aux_data dp;
-                struct i2c_algo_radeon_data radeon;
        } algo;
        struct radeon_i2c_bus_rec rec;
 };
@@ -342,6 +340,7 @@ struct radeon_encoder {
        struct drm_display_mode native_mode;
        void *enc_priv;
        int hdmi_offset;
+        int hdmi_config_offset;
        int hdmi_audio_workaround;
        int hdmi_buffer_status;
 };
@@ -431,7 +430,6 @@ extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
                                                 struct radeon_i2c_bus_rec *rec,
                                                 const char *name);
 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
-extern void radeon_i2c_destroy_dp(struct radeon_i2c_chan *i2c);
 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
                                u8 slave_addr,
                                u8 addr,
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index fc9d00ac6b15..122774742bd5 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -30,6 +30,7 @@
 *    Dave Airlie
 */
 #include <linux/list.h>
+#include <linux/slab.h>
 #include <drm/drmP.h>
 #include "radeon_drm.h"
 #include "radeon.h"
@@ -185,8 +186,10 @@ int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
                return 0;
        }
        radeon_ttm_placement_from_domain(bo, domain);
-        /* force to pin into visible video ram */
+        if (domain == RADEON_GEM_DOMAIN_VRAM) {
-        bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
+                /* force to pin into visible video ram */
+                bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
+        }
        for (i = 0; i < bo->placement.num_placement; i++)
                bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
        r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index d4d1c39a0e99..a4b57493aa78 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -28,6 +28,7 @@
 #define RADEON_RECLOCK_DELAY_MS 200
 #define RADEON_WAIT_VBLANK_TIMEOUT 200
+static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
 static void radeon_pm_set_clocks_locked(struct radeon_device *rdev);
 static void radeon_pm_set_clocks(struct radeon_device *rdev);
 static void radeon_pm_idle_work_handler(struct work_struct *work);
@@ -179,6 +180,16 @@ static void radeon_get_power_state(struct radeon_device *rdev,
                 rdev->pm.requested_power_state->non_clock_info.pcie_lanes);
 }
+static inline void radeon_sync_with_vblank(struct radeon_device *rdev)
+{
+        if (rdev->pm.active_crtcs) {
+                rdev->pm.vblank_sync = false;
+                wait_event_timeout(
+                        rdev->irq.vblank_queue, rdev->pm.vblank_sync,
+                        msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
+        }
+}
 static void radeon_set_power_state(struct radeon_device *rdev)
 {
        /* if *_clock_mode are the same, *_power_state are as well */
@@ -189,11 +200,28 @@ static void radeon_set_power_state(struct radeon_device *rdev)
                 rdev->pm.requested_clock_mode->sclk,
                 rdev->pm.requested_clock_mode->mclk,
                 rdev->pm.requested_power_state->non_clock_info.pcie_lanes);
        /* set pcie lanes */
+        /* TODO */
        /* set voltage */
+        /* TODO */
        /* set engine clock */
+        radeon_sync_with_vblank(rdev);
+        radeon_pm_debug_check_in_vbl(rdev, false);
        radeon_set_engine_clock(rdev, rdev->pm.requested_clock_mode->sclk);
+        radeon_pm_debug_check_in_vbl(rdev, true);
+#if 0
        /* set memory clock */
+        if (rdev->asic->set_memory_clock) {
+                radeon_sync_with_vblank(rdev);
+                radeon_pm_debug_check_in_vbl(rdev, false);
+                radeon_set_memory_clock(rdev, rdev->pm.requested_clock_mode->mclk);
+                radeon_pm_debug_check_in_vbl(rdev, true);
+        }
+#endif
        rdev->pm.current_power_state = rdev->pm.requested_power_state;
        rdev->pm.current_clock_mode = rdev->pm.requested_clock_mode;
@@ -229,6 +257,12 @@ int radeon_pm_init(struct radeon_device *rdev)
        return 0;
 }
+void radeon_pm_fini(struct radeon_device *rdev)
+{
+        if (rdev->pm.i2c_bus)
+                radeon_i2c_destroy(rdev->pm.i2c_bus);
+}
 void radeon_pm_compute_clocks(struct radeon_device *rdev)
 {
        struct drm_device *ddev = rdev->ddev;
@@ -245,7 +279,8 @@ void radeon_pm_compute_clocks(struct radeon_device *rdev)
        list_for_each_entry(connector,
                &ddev->mode_config.connector_list, head) {
                if (connector->encoder &&
-                        connector->dpms != DRM_MODE_DPMS_OFF) {
+                    connector->encoder->crtc &&
+                    connector->dpms != DRM_MODE_DPMS_OFF) {
                        radeon_crtc = to_radeon_crtc(connector->encoder->crtc);
                        rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
                        ++count;
@@ -333,10 +368,7 @@ static void radeon_pm_set_clocks_locked(struct radeon_device *rdev)
                break;
        }
-        /* check if we are in vblank */
-        radeon_pm_debug_check_in_vbl(rdev, false);
        radeon_set_power_state(rdev);
-        radeon_pm_debug_check_in_vbl(rdev, true);
        rdev->pm.planned_action = PM_ACTION_NONE;
 }
@@ -353,10 +385,7 @@ static void radeon_pm_set_clocks(struct radeon_device *rdev)
                rdev->pm.req_vblank |= (1 << 1);
                drm_vblank_get(rdev->ddev, 1);
        }
-        if (rdev->pm.active_crtcs)
+        radeon_pm_set_clocks_locked(rdev);
-                wait_event_interruptible_timeout(
-                        rdev->irq.vblank_queue, 0,
-                        msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
        if (rdev->pm.req_vblank & (1 << 0)) {
                rdev->pm.req_vblank &= ~(1 << 0);
                drm_vblank_put(rdev->ddev, 0);
@@ -366,7 +395,6 @@ static void radeon_pm_set_clocks(struct radeon_device *rdev)
                drm_vblank_put(rdev->ddev, 1);
        }
-        radeon_pm_set_clocks_locked(rdev);
        mutex_unlock(&rdev->cp.mutex);
 }
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
index 5c0dc082d330..eabbc9cf30a7 100644
--- a/drivers/gpu/drm/radeon/radeon_reg.h
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
@@ -346,6 +346,7 @@
 #       define RADEON_TVPLL_PWRMGT_OFF      (1 << 30)
 #       define RADEON_TVCLK_TURNOFF         (1 << 31)
 #define RADEON_PLL_PWRMGT_CNTL              0x0015 /* PLL */
+#       define RADEON_PM_MODE_SEL           (1 << 13)
 #       define RADEON_TCL_BYPASS_DISABLE    (1 << 20)
 #define RADEON_CLR_CMP_CLR_3D               0x1a24
 #define RADEON_CLR_CMP_CLR_DST              0x15c8
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index e50513a62735..f6e1e8d4d986 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -26,6 +26,7 @@
 *          Jerome Glisse
 */
 #include <linux/seq_file.h>
+#include <linux/slab.h>
 #include "drmP.h"
 #include "radeon_drm.h"
 #include "radeon_reg.h"
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index 43c5ab34b634..d031b6863082 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -36,6 +36,7 @@
 #include <drm/drmP.h>
 #include <drm/radeon_drm.h>
 #include <linux/seq_file.h>
+#include <linux/slab.h>
 #include "radeon_reg.h"
 #include "radeon.h"
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r300 b/drivers/gpu/drm/radeon/reg_srcs/r300
index 19c4663fa9c6..1e97b2d129fd 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/r300
+++ b/drivers/gpu/drm/radeon/reg_srcs/r300
@@ -125,6 +125,8 @@ r300 0x4f60
 0x4000 GB_VAP_RASTER_VTX_FMT_0
 0x4004 GB_VAP_RASTER_VTX_FMT_1
 0x4008 GB_ENABLE
+0x4010 GB_MSPOS0
+0x4014 GB_MSPOS1
 0x401C GB_SELECT
 0x4020 GB_AA_CONFIG
 0x4024 GB_FIFO_SIZE
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r420 b/drivers/gpu/drm/radeon/reg_srcs/r420
index 989f7a020832..e958980d00f1 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/r420
+++ b/drivers/gpu/drm/radeon/reg_srcs/r420
@@ -125,6 +125,8 @@ r420 0x4f60
 0x4000 GB_VAP_RASTER_VTX_FMT_0
 0x4004 GB_VAP_RASTER_VTX_FMT_1
 0x4008 GB_ENABLE
+0x4010 GB_MSPOS0
+0x4014 GB_MSPOS1
 0x401C GB_SELECT
 0x4020 GB_AA_CONFIG
 0x4024 GB_FIFO_SIZE
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r600 b/drivers/gpu/drm/radeon/reg_srcs/r600
index 8f414a5f520f..af0da4ae3f55 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/r600
+++ b/drivers/gpu/drm/radeon/reg_srcs/r600
@@ -26,20 +26,16 @@ r600 0x9400
 0x00028408 VGT_INDX_OFFSET
 0x00028AA0 VGT_INSTANCE_STEP_RATE_0
 0x00028AA4 VGT_INSTANCE_STEP_RATE_1
-0x000088C0 VGT_LAST_COPY_STATE
 0x00028400 VGT_MAX_VTX_INDX
-0x000088D8 VGT_MC_LAT_CNTL
 0x00028404 VGT_MIN_VTX_INDX
 0x00028A94 VGT_MULTI_PRIM_IB_RESET_EN
 0x0002840C VGT_MULTI_PRIM_IB_RESET_INDX
 0x00008970 VGT_NUM_INDICES
 0x00008974 VGT_NUM_INSTANCES
 0x00028A10 VGT_OUTPUT_PATH_CNTL
-0x00028C5C VGT_OUT_DEALLOC_CNTL
 0x00028A84 VGT_PRIMITIVEID_EN
 0x00008958 VGT_PRIMITIVE_TYPE
 0x00028AB4 VGT_REUSE_OFF
-0x00028C58 VGT_VERTEX_REUSE_BLOCK_CNTL
 0x00028AB8 VGT_VTX_CNT_EN
 0x000088B0 VGT_VTX_VECT_EJECT_REG
 0x00028810 PA_CL_CLIP_CNTL
@@ -280,7 +276,6 @@ r600 0x9400
 0x00028E00 PA_SU_POLY_OFFSET_FRONT_SCALE
 0x00028814 PA_SU_SC_MODE_CNTL
 0x00028C08 PA_SU_VTX_CNTL
-0x00008C00 SQ_CONFIG
 0x00008C04 SQ_GPR_RESOURCE_MGMT_1
 0x00008C08 SQ_GPR_RESOURCE_MGMT_2
 0x00008C10 SQ_STACK_RESOURCE_MGMT_1
@@ -320,18 +315,6 @@ r600 0x9400
 0x000283FC SQ_VTX_SEMANTIC_31
 0x000288E0 SQ_VTX_SEMANTIC_CLEAR
 0x0003CFF4 SQ_VTX_START_INST_LOC
-0x0003C000 SQ_TEX_SAMPLER_WORD0_0
-0x0003C004 SQ_TEX_SAMPLER_WORD1_0
-0x0003C008 SQ_TEX_SAMPLER_WORD2_0
-0x00030000 SQ_ALU_CONSTANT0_0
-0x00030004 SQ_ALU_CONSTANT1_0
-0x00030008 SQ_ALU_CONSTANT2_0
-0x0003000C SQ_ALU_CONSTANT3_0
-0x0003E380 SQ_BOOL_CONST_0
-0x0003E384 SQ_BOOL_CONST_1
-0x0003E388 SQ_BOOL_CONST_2
-0x0003E200 SQ_LOOP_CONST_0
-0x0003E200 SQ_LOOP_CONST_DX10_0
 0x000281C0 SQ_ALU_CONST_BUFFER_SIZE_GS_0
 0x000281C4 SQ_ALU_CONST_BUFFER_SIZE_GS_1
 0x000281C8 SQ_ALU_CONST_BUFFER_SIZE_GS_2
@@ -380,54 +363,6 @@ r600 0x9400
 0x000281B4 SQ_ALU_CONST_BUFFER_SIZE_VS_13
 0x000281B8 SQ_ALU_CONST_BUFFER_SIZE_VS_14
 0x000281BC SQ_ALU_CONST_BUFFER_SIZE_VS_15
-0x000289C0 SQ_ALU_CONST_CACHE_GS_0
-0x000289C4 SQ_ALU_CONST_CACHE_GS_1
-0x000289C8 SQ_ALU_CONST_CACHE_GS_2
-0x000289CC SQ_ALU_CONST_CACHE_GS_3
-0x000289D0 SQ_ALU_CONST_CACHE_GS_4
-0x000289D4 SQ_ALU_CONST_CACHE_GS_5
-0x000289D8 SQ_ALU_CONST_CACHE_GS_6
-0x000289DC SQ_ALU_CONST_CACHE_GS_7
-0x000289E0 SQ_ALU_CONST_CACHE_GS_8
-0x000289E4 SQ_ALU_CONST_CACHE_GS_9
-0x000289E8 SQ_ALU_CONST_CACHE_GS_10
-0x000289EC SQ_ALU_CONST_CACHE_GS_11
-0x000289F0 SQ_ALU_CONST_CACHE_GS_12
-0x000289F4 SQ_ALU_CONST_CACHE_GS_13
-0x000289F8 SQ_ALU_CONST_CACHE_GS_14
-0x000289FC SQ_ALU_CONST_CACHE_GS_15
-0x00028940 SQ_ALU_CONST_CACHE_PS_0
-0x00028944 SQ_ALU_CONST_CACHE_PS_1
-0x00028948 SQ_ALU_CONST_CACHE_PS_2
-0x0002894C SQ_ALU_CONST_CACHE_PS_3
-0x00028950 SQ_ALU_CONST_CACHE_PS_4
-0x00028954 SQ_ALU_CONST_CACHE_PS_5
-0x00028958 SQ_ALU_CONST_CACHE_PS_6
-0x0002895C SQ_ALU_CONST_CACHE_PS_7
-0x00028960 SQ_ALU_CONST_CACHE_PS_8
-0x00028964 SQ_ALU_CONST_CACHE_PS_9
-0x00028968 SQ_ALU_CONST_CACHE_PS_10
-0x0002896C SQ_ALU_CONST_CACHE_PS_11
-0x00028970 SQ_ALU_CONST_CACHE_PS_12
-0x00028974 SQ_ALU_CONST_CACHE_PS_13
-0x00028978 SQ_ALU_CONST_CACHE_PS_14
-0x0002897C SQ_ALU_CONST_CACHE_PS_15
-0x00028980 SQ_ALU_CONST_CACHE_VS_0
-0x00028984 SQ_ALU_CONST_CACHE_VS_1
-0x00028988 SQ_ALU_CONST_CACHE_VS_2
-0x0002898C SQ_ALU_CONST_CACHE_VS_3
-0x00028990 SQ_ALU_CONST_CACHE_VS_4
-0x00028994 SQ_ALU_CONST_CACHE_VS_5
-0x00028998 SQ_ALU_CONST_CACHE_VS_6
-0x0002899C SQ_ALU_CONST_CACHE_VS_7
-0x000289A0 SQ_ALU_CONST_CACHE_VS_8
-0x000289A4 SQ_ALU_CONST_CACHE_VS_9
-0x000289A8 SQ_ALU_CONST_CACHE_VS_10
-0x000289AC SQ_ALU_CONST_CACHE_VS_11
-0x000289B0 SQ_ALU_CONST_CACHE_VS_12
-0x000289B4 SQ_ALU_CONST_CACHE_VS_13
-0x000289B8 SQ_ALU_CONST_CACHE_VS_14
-0x000289BC SQ_ALU_CONST_CACHE_VS_15
 0x000288D8 SQ_PGM_CF_OFFSET_ES
 0x000288DC SQ_PGM_CF_OFFSET_FS
 0x000288D4 SQ_PGM_CF_OFFSET_GS
@@ -494,12 +429,7 @@ r600 0x9400
 0x00028438 SX_ALPHA_REF
 0x00028410 SX_ALPHA_TEST_CONTROL
 0x00028350 SX_MISC
-0x0000A020 SMX_DC_CTL0
-0x0000A024 SMX_DC_CTL1
-0x0000A028 SMX_DC_CTL2
-0x00009608 TC_CNTL
 0x00009604 TC_INVALIDATE
-0x00009490 TD_CNTL
 0x00009400 TD_FILTER4
 0x00009404 TD_FILTER4_1
 0x00009408 TD_FILTER4_2
@@ -824,14 +754,9 @@ r600 0x9400
 0x00028428 CB_FOG_GREEN
 0x00028424 CB_FOG_RED
 0x00008040 WAIT_UNTIL
-0x00008950 CC_GC_SHADER_PIPE_CONFIG
-0x00008954 GC_USER_SHADER_PIPE_CONFIG
 0x00009714 VC_ENHANCE
 0x00009830 DB_DEBUG
 0x00009838 DB_WATERMARKS
 0x00028D28 DB_SRESULTS_COMPARE_STATE0
 0x00028D44 DB_ALPHA_TO_MASK
-0x00009504 TA_CNTL
 0x00009700 VC_CNTL
-0x00009718 VC_CONFIG
-0x0000A02C SMX_DC_MC_INTF_CTL
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rs600 b/drivers/gpu/drm/radeon/reg_srcs/rs600
index 6801b865d1c4..83e8bc0c2bb2 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/rs600
+++ b/drivers/gpu/drm/radeon/reg_srcs/rs600
@@ -125,6 +125,8 @@ rs600 0x6d40
 0x4000 GB_VAP_RASTER_VTX_FMT_0
 0x4004 GB_VAP_RASTER_VTX_FMT_1
 0x4008 GB_ENABLE
+0x4010 GB_MSPOS0
+0x4014 GB_MSPOS1
 0x401C GB_SELECT
 0x4020 GB_AA_CONFIG
 0x4024 GB_FIFO_SIZE
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rv515 b/drivers/gpu/drm/radeon/reg_srcs/rv515
index 38abf63bf2cd..1e46233985eb 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/rv515
+++ b/drivers/gpu/drm/radeon/reg_srcs/rv515
@@ -35,6 +35,7 @@ rv515 0x6d40
 0x1DA8 VAP_VPORT_ZSCALE
 0x1DAC VAP_VPORT_ZOFFSET
 0x2080 VAP_CNTL
+0x208C VAP_INDEX_OFFSET
 0x2090 VAP_OUT_VTX_FMT_0
 0x2094 VAP_OUT_VTX_FMT_1
 0x20B0 VAP_VTE_CNTL
@@ -158,6 +159,8 @@ rv515 0x6d40
 0x4000 GB_VAP_RASTER_VTX_FMT_0
 0x4004 GB_VAP_RASTER_VTX_FMT_1
 0x4008 GB_ENABLE
+0x4010 GB_MSPOS0
+0x4014 GB_MSPOS1
 0x401C GB_SELECT
 0x4020 GB_AA_CONFIG
 0x4024 GB_FIFO_SIZE
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index 626d51891ee9..1a41cb268b72 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -26,8 +26,10 @@
 *          Jerome Glisse
 */
 #include <linux/seq_file.h>
+#include <linux/slab.h>
 #include <drm/drmP.h>
 #include "radeon.h"
+#include "radeon_asic.h"
 #include "rs400d.h"
 /* This files gather functions specifics to : rs400,rs480 */
@@ -202,9 +204,9 @@ void rs400_gart_disable(struct radeon_device *rdev)
 void rs400_gart_fini(struct radeon_device *rdev)
 {
+        radeon_gart_fini(rdev);
        rs400_gart_disable(rdev);
        radeon_gart_table_ram_free(rdev);
-        radeon_gart_fini(rdev);
 }
 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
@@ -264,6 +266,7 @@ void rs400_mc_init(struct radeon_device *rdev)
        base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
        radeon_vram_location(rdev, &rdev->mc, base);
        radeon_gtt_location(rdev, &rdev->mc);
+        radeon_update_bandwidth_info(rdev);
 }
 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
@@ -388,6 +391,8 @@ static int rs400_startup(struct radeon_device *rdev)
 {
        int r;
+        r100_set_common_regs(rdev);
        rs400_mc_program(rdev);
        /* Resume clock */
        r300_clock_startup(rdev);
@@ -453,6 +458,7 @@ int rs400_suspend(struct radeon_device *rdev)
 void rs400_fini(struct radeon_device *rdev)
 {
+        radeon_pm_fini(rdev);
        r100_cp_fini(rdev);
        r100_wb_fini(rdev);
        r100_ib_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 47f046b78c6b..a81bc7a21e14 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -37,6 +37,7 @@
 */
 #include "drmP.h"
 #include "radeon.h"
+#include "radeon_asic.h"
 #include "atom.h"
 #include "rs600d.h"
@@ -158,7 +159,7 @@ void rs600_gart_tlb_flush(struct radeon_device *rdev)
        WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
        tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
-        tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1);
+        tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
        WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
        tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
@@ -267,9 +268,9 @@ void rs600_gart_disable(struct radeon_device *rdev)
 void rs600_gart_fini(struct radeon_device *rdev)
 {
+        radeon_gart_fini(rdev);
        rs600_gart_disable(rdev);
        radeon_gart_table_vram_free(rdev);
-        radeon_gart_fini(rdev);
 }
 #define R600_PTE_VALID     (1 << 0)
@@ -392,10 +393,12 @@ int rs600_irq_process(struct radeon_device *rdev)
                /* Vertical blank interrupts */
                if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int)) {
                        drm_handle_vblank(rdev->ddev, 0);
+                        rdev->pm.vblank_sync = true;
                        wake_up(&rdev->irq.vblank_queue);
                }
                if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int)) {
                        drm_handle_vblank(rdev->ddev, 1);
+                        rdev->pm.vblank_sync = true;
                        wake_up(&rdev->irq.vblank_queue);
                }
                if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(r500_disp_int)) {
@@ -472,13 +475,38 @@ void rs600_mc_init(struct radeon_device *rdev)
        rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
        base = RREG32_MC(R_000004_MC_FB_LOCATION);
        base = G_000004_MC_FB_START(base) << 16;
+        rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
        radeon_vram_location(rdev, &rdev->mc, base);
        radeon_gtt_location(rdev, &rdev->mc);
+        radeon_update_bandwidth_info(rdev);
 }
 void rs600_bandwidth_update(struct radeon_device *rdev)
 {
-        /* FIXME: implement, should this be like rs690 ? */
+        struct drm_display_mode *mode0 = NULL;
+        struct drm_display_mode *mode1 = NULL;
+        u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
+        /* FIXME: implement full support */
+        radeon_update_display_priority(rdev);
+        if (rdev->mode_info.crtcs[0]->base.enabled)
+                mode0 = &rdev->mode_info.crtcs[0]->base.mode;
+        if (rdev->mode_info.crtcs[1]->base.enabled)
+                mode1 = &rdev->mode_info.crtcs[1]->base.mode;
+        rs690_line_buffer_adjust(rdev, mode0, mode1);
+        if (rdev->disp_priority == 2) {
+                d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
+                d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
+                d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
+                d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
+                WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
+                WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
+                WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
+                WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
+        }
 }
 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
@@ -598,6 +626,7 @@ int rs600_suspend(struct radeon_device *rdev)
 void rs600_fini(struct radeon_device *rdev)
 {
+        radeon_pm_fini(rdev);
        r100_cp_fini(rdev);
        r100_wb_fini(rdev);
        r100_ib_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/rs600d.h b/drivers/gpu/drm/radeon/rs600d.h
index c1c8f5885cbb..e52d2695510b 100644
--- a/drivers/gpu/drm/radeon/rs600d.h
+++ b/drivers/gpu/drm/radeon/rs600d.h
@@ -535,4 +535,57 @@
 #define   G_00016C_INVALIDATE_L1_TLB(x)                (((x) >> 20) & 0x1)
 #define   C_00016C_INVALIDATE_L1_TLB                   0xFFEFFFFF
+#define R_006548_D1MODE_PRIORITY_A_CNT               0x006548
+#define   S_006548_D1MODE_PRIORITY_MARK_A(x)           (((x) & 0x7FFF) << 0)
+#define   G_006548_D1MODE_PRIORITY_MARK_A(x)           (((x) >> 0) & 0x7FFF)
+#define   C_006548_D1MODE_PRIORITY_MARK_A              0xFFFF8000
+#define   S_006548_D1MODE_PRIORITY_A_OFF(x)            (((x) & 0x1) << 16)
+#define   G_006548_D1MODE_PRIORITY_A_OFF(x)            (((x) >> 16) & 0x1)
+#define   C_006548_D1MODE_PRIORITY_A_OFF               0xFFFEFFFF
+#define   S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x)      (((x) & 0x1) << 20)
+#define   G_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x)      (((x) >> 20) & 0x1)
+#define   C_006548_D1MODE_PRIORITY_A_ALWAYS_ON         0xFFEFFFFF
+#define   S_006548_D1MODE_PRIORITY_A_FORCE_MASK(x)     (((x) & 0x1) << 24)
+#define   G_006548_D1MODE_PRIORITY_A_FORCE_MASK(x)     (((x) >> 24) & 0x1)
+#define   C_006548_D1MODE_PRIORITY_A_FORCE_MASK        0xFEFFFFFF
+#define R_00654C_D1MODE_PRIORITY_B_CNT               0x00654C
+#define   S_00654C_D1MODE_PRIORITY_MARK_B(x)           (((x) & 0x7FFF) << 0)
+#define   G_00654C_D1MODE_PRIORITY_MARK_B(x)           (((x) >> 0) & 0x7FFF)
+#define   C_00654C_D1MODE_PRIORITY_MARK_B              0xFFFF8000
+#define   S_00654C_D1MODE_PRIORITY_B_OFF(x)            (((x) & 0x1) << 16)
+#define   G_00654C_D1MODE_PRIORITY_B_OFF(x)            (((x) >> 16) & 0x1)
+#define   C_00654C_D1MODE_PRIORITY_B_OFF               0xFFFEFFFF
+#define   S_00654C_D1MODE_PRIORITY_B_ALWAYS_ON(x)      (((x) & 0x1) << 20)
+#define   G_00654C_D1MODE_PRIORITY_B_ALWAYS_ON(x)      (((x) >> 20) & 0x1)
+#define   C_00654C_D1MODE_PRIORITY_B_ALWAYS_ON         0xFFEFFFFF
+#define   S_00654C_D1MODE_PRIORITY_B_FORCE_MASK(x)     (((x) & 0x1) << 24)
+#define   G_00654C_D1MODE_PRIORITY_B_FORCE_MASK(x)     (((x) >> 24) & 0x1)
+#define   C_00654C_D1MODE_PRIORITY_B_FORCE_MASK        0xFEFFFFFF
+#define R_006D48_D2MODE_PRIORITY_A_CNT               0x006D48
+#define   S_006D48_D2MODE_PRIORITY_MARK_A(x)           (((x) & 0x7FFF) << 0)
+#define   G_006D48_D2MODE_PRIORITY_MARK_A(x)           (((x) >> 0) & 0x7FFF)
+#define   C_006D48_D2MODE_PRIORITY_MARK_A              0xFFFF8000
+#define   S_006D48_D2MODE_PRIORITY_A_OFF(x)            (((x) & 0x1) << 16)
+#define   G_006D48_D2MODE_PRIORITY_A_OFF(x)            (((x) >> 16) & 0x1)
+#define   C_006D48_D2MODE_PRIORITY_A_OFF               0xFFFEFFFF
+#define   S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(x)      (((x) & 0x1) << 20)
+#define   G_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(x)      (((x) >> 20) & 0x1)
+#define   C_006D48_D2MODE_PRIORITY_A_ALWAYS_ON         0xFFEFFFFF
+#define   S_006D48_D2MODE_PRIORITY_A_FORCE_MASK(x)     (((x) & 0x1) << 24)
+#define   G_006D48_D2MODE_PRIORITY_A_FORCE_MASK(x)     (((x) >> 24) & 0x1)
+#define   C_006D48_D2MODE_PRIORITY_A_FORCE_MASK        0xFEFFFFFF
+#define R_006D4C_D2MODE_PRIORITY_B_CNT               0x006D4C
+#define   S_006D4C_D2MODE_PRIORITY_MARK_B(x)           (((x) & 0x7FFF) << 0)
+#define   G_006D4C_D2MODE_PRIORITY_MARK_B(x)           (((x) >> 0) & 0x7FFF)
+#define   C_006D4C_D2MODE_PRIORITY_MARK_B              0xFFFF8000
+#define   S_006D4C_D2MODE_PRIORITY_B_OFF(x)            (((x) & 0x1) << 16)
+#define   G_006D4C_D2MODE_PRIORITY_B_OFF(x)            (((x) >> 16) & 0x1)
+#define   C_006D4C_D2MODE_PRIORITY_B_OFF               0xFFFEFFFF
+#define   S_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON(x)      (((x) & 0x1) << 20)
+#define   G_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON(x)      (((x) >> 20) & 0x1)
+#define   C_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON         0xFFEFFFFF
+#define   S_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x)     (((x) & 0x1) << 24)
+#define   G_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x)     (((x) >> 24) & 0x1)
+#define   C_006D4C_D2MODE_PRIORITY_B_FORCE_MASK        0xFEFFFFFF
 #endif
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 83b9174f76f2..bbf3da790fd5 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -27,6 +27,7 @@
 */
 #include "drmP.h"
 #include "radeon.h"
+#include "radeon_asic.h"
 #include "atom.h"
 #include "rs690d.h"
@@ -57,42 +58,57 @@ static void rs690_gpu_init(struct radeon_device *rdev)
        }
 }
+union igp_info {
+        struct _ATOM_INTEGRATED_SYSTEM_INFO info;
+        struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2;
+};
 void rs690_pm_info(struct radeon_device *rdev)
 {
        int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
-        struct _ATOM_INTEGRATED_SYSTEM_INFO *info;
+        union igp_info *info;
-        struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *info_v2;
-        void *ptr;
        uint16_t data_offset;
        uint8_t frev, crev;
        fixed20_12 tmp;
-        atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
+        if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
-                               &frev, &crev, &data_offset);
+                                   &frev, &crev, &data_offset)) {
-        ptr = rdev->mode_info.atom_context->bios + data_offset;
+                info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
-        info = (struct _ATOM_INTEGRATED_SYSTEM_INFO *)ptr;
-        info_v2 = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *)ptr;
+                /* Get various system informations from bios */
-        /* Get various system informations from bios */
+                switch (crev) {
-        switch (crev) {
+                case 1:
-        case 1:
+                        tmp.full = rfixed_const(100);
-                tmp.full = rfixed_const(100);
+                        rdev->pm.igp_sideport_mclk.full = rfixed_const(info->info.ulBootUpMemoryClock);
-                rdev->pm.igp_sideport_mclk.full = rfixed_const(info->ulBootUpMemoryClock);
+                        rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
-                rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
+                        rdev->pm.igp_system_mclk.full = rfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
-                rdev->pm.igp_system_mclk.full = rfixed_const(le16_to_cpu(info->usK8MemoryClock));
+                        rdev->pm.igp_ht_link_clk.full = rfixed_const(le16_to_cpu(info->info.usFSBClock));
-                rdev->pm.igp_ht_link_clk.full = rfixed_const(le16_to_cpu(info->usFSBClock));
+                        rdev->pm.igp_ht_link_width.full = rfixed_const(info->info.ucHTLinkWidth);
-                rdev->pm.igp_ht_link_width.full = rfixed_const(info->ucHTLinkWidth);
+                        break;
-                break;
+                case 2:
-        case 2:
+                        tmp.full = rfixed_const(100);
-                tmp.full = rfixed_const(100);
+                        rdev->pm.igp_sideport_mclk.full = rfixed_const(info->info_v2.ulBootUpSidePortClock);
-                rdev->pm.igp_sideport_mclk.full = rfixed_const(info_v2->ulBootUpSidePortClock);
+                        rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
-                rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
+                        rdev->pm.igp_system_mclk.full = rfixed_const(info->info_v2.ulBootUpUMAClock);
-                rdev->pm.igp_system_mclk.full = rfixed_const(info_v2->ulBootUpUMAClock);
+                        rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
-                rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
+                        rdev->pm.igp_ht_link_clk.full = rfixed_const(info->info_v2.ulHTLinkFreq);
-                rdev->pm.igp_ht_link_clk.full = rfixed_const(info_v2->ulHTLinkFreq);
+                        rdev->pm.igp_ht_link_clk.full = rfixed_div(rdev->pm.igp_ht_link_clk, tmp);
-                rdev->pm.igp_ht_link_clk.full = rfixed_div(rdev->pm.igp_ht_link_clk, tmp);
+                        rdev->pm.igp_ht_link_width.full = rfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
-                rdev->pm.igp_ht_link_width.full = rfixed_const(le16_to_cpu(info_v2->usMinHTLinkWidth));
+                        break;
-                break;
+                default:
-        default:
+                        tmp.full = rfixed_const(100);
+                        /* We assume the slower possible clock ie worst case */
+                        /* DDR 333Mhz */
+                        rdev->pm.igp_sideport_mclk.full = rfixed_const(333);
+                        /* FIXME: system clock ? */
+                        rdev->pm.igp_system_mclk.full = rfixed_const(100);
+                        rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
+                        rdev->pm.igp_ht_link_clk.full = rfixed_const(200);
+                        rdev->pm.igp_ht_link_width.full = rfixed_const(8);
+                        DRM_ERROR("No integrated system info for your GPU, using safe default\n");
+                        break;
+                }
+        } else {
                tmp.full = rfixed_const(100);
                /* We assume the slower possible clock ie worst case */
                /* DDR 333Mhz */
@@ -103,7 +119,6 @@ void rs690_pm_info(struct radeon_device *rdev)
                rdev->pm.igp_ht_link_clk.full = rfixed_const(200);
                rdev->pm.igp_ht_link_width.full = rfixed_const(8);
                DRM_ERROR("No integrated system info for your GPU, using safe default\n");
-                break;
        }
        /* Compute various bandwidth */
        /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4  */
@@ -131,7 +146,6 @@ void rs690_pm_info(struct radeon_device *rdev)
 void rs690_mc_init(struct radeon_device *rdev)
 {
-        fixed20_12 a;
        u64 base;
        rs400_gart_adjust_size(rdev);
@@ -145,18 +159,10 @@ void rs690_mc_init(struct radeon_device *rdev)
        base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
        base = G_000100_MC_FB_START(base) << 16;
        rs690_pm_info(rdev);
-        /* FIXME: we should enforce default clock in case GPU is not in
-         * default setup
-         */
-        a.full = rfixed_const(100);
-        rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
-        rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
-        a.full = rfixed_const(16);
-        /* core_bandwidth = sclk(Mhz) * 16 */
-        rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a);
        rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
        radeon_vram_location(rdev, &rdev->mc, base);
        radeon_gtt_location(rdev, &rdev->mc);
+        radeon_update_bandwidth_info(rdev);
 }
 void rs690_line_buffer_adjust(struct radeon_device *rdev,
@@ -394,10 +400,12 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
        struct drm_display_mode *mode1 = NULL;
        struct rs690_watermark wm0;
        struct rs690_watermark wm1;
-        u32 tmp;
+        u32 tmp, d1mode_priority_a_cnt, d2mode_priority_a_cnt;
        fixed20_12 priority_mark02, priority_mark12, fill_rate;
        fixed20_12 a, b;
+        radeon_update_display_priority(rdev);
        if (rdev->mode_info.crtcs[0]->base.enabled)
                mode0 = &rdev->mode_info.crtcs[0]->base.mode;
        if (rdev->mode_info.crtcs[1]->base.enabled)
@@ -407,7 +415,8 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
         * modes if the user specifies HIGH for displaypriority
         * option.
         */
-        if (rdev->disp_priority == 2) {
+        if ((rdev->disp_priority == 2) &&
+            ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) {
                tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
                tmp &= C_000104_MC_DISP0R_INIT_LAT;
                tmp &= C_000104_MC_DISP1R_INIT_LAT;
@@ -482,10 +491,16 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
                        priority_mark12.full = 0;
                if (wm1.priority_mark_max.full > priority_mark12.full)
                        priority_mark12.full = wm1.priority_mark_max.full;
-                WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
+                d1mode_priority_a_cnt = rfixed_trunc(priority_mark02);
-                WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
+                d2mode_priority_a_cnt = rfixed_trunc(priority_mark12);
-                WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
+                if (rdev->disp_priority == 2) {
-                WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
+                        d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
+                        d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
+                }
+                WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
+                WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
+                WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
+                WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
        } else if (mode0) {
                if (rfixed_trunc(wm0.dbpp) > 64)
                        a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
@@ -512,8 +527,11 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
                        priority_mark02.full = 0;
                if (wm0.priority_mark_max.full > priority_mark02.full)
                        priority_mark02.full = wm0.priority_mark_max.full;
-                WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
+                d1mode_priority_a_cnt = rfixed_trunc(priority_mark02);
-                WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
+                if (rdev->disp_priority == 2)
+                        d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
+                WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
+                WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
                WREG32(R_006D48_D2MODE_PRIORITY_A_CNT,
                        S_006D48_D2MODE_PRIORITY_A_OFF(1));
                WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT,
@@ -544,12 +562,15 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
                        priority_mark12.full = 0;
                if (wm1.priority_mark_max.full > priority_mark12.full)
                        priority_mark12.full = wm1.priority_mark_max.full;
+                d2mode_priority_a_cnt = rfixed_trunc(priority_mark12);
+                if (rdev->disp_priority == 2)
+                        d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
                WREG32(R_006548_D1MODE_PRIORITY_A_CNT,
                        S_006548_D1MODE_PRIORITY_A_OFF(1));
                WREG32(R_00654C_D1MODE_PRIORITY_B_CNT,
                        S_00654C_D1MODE_PRIORITY_B_OFF(1));
-                WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
+                WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
-                WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
+                WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
        }
 }
@@ -657,6 +678,7 @@ int rs690_suspend(struct radeon_device *rdev)
 void rs690_fini(struct radeon_device *rdev)
 {
+        radeon_pm_fini(rdev);
        r100_cp_fini(rdev);
        r100_wb_fini(rdev);
        r100_ib_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/rs690d.h b/drivers/gpu/drm/radeon/rs690d.h
index 62d31e7a897f..36e6398a98ae 100644
--- a/drivers/gpu/drm/radeon/rs690d.h
+++ b/drivers/gpu/drm/radeon/rs690d.h
@@ -182,6 +182,9 @@
 #define   S_006548_D1MODE_PRIORITY_A_OFF(x)            (((x) & 0x1) << 16)
 #define   G_006548_D1MODE_PRIORITY_A_OFF(x)            (((x) >> 16) & 0x1)
 #define   C_006548_D1MODE_PRIORITY_A_OFF               0xFFFEFFFF
+#define   S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x)      (((x) & 0x1) << 20)
+#define   G_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x)      (((x) >> 20) & 0x1)
+#define   C_006548_D1MODE_PRIORITY_A_ALWAYS_ON         0xFFEFFFFF
 #define   S_006548_D1MODE_PRIORITY_A_FORCE_MASK(x)     (((x) & 0x1) << 24)
 #define   G_006548_D1MODE_PRIORITY_A_FORCE_MASK(x)     (((x) >> 24) & 0x1)
 #define   C_006548_D1MODE_PRIORITY_A_FORCE_MASK        0xFEFFFFFF
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index bea747da123f..9035121f4b58 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -26,9 +26,11 @@
 *          Jerome Glisse
 */
 #include <linux/seq_file.h>
+#include <linux/slab.h>
 #include "drmP.h"
 #include "rv515d.h"
 #include "radeon.h"
+#include "radeon_asic.h"
 #include "atom.h"
 #include "rv515_reg_safe.h"
@@ -279,19 +281,13 @@ static void rv515_vram_get_type(struct radeon_device *rdev)
 void rv515_mc_init(struct radeon_device *rdev)
 {
-        fixed20_12 a;
        rv515_vram_get_type(rdev);
        r100_vram_init_sizes(rdev);
        radeon_vram_location(rdev, &rdev->mc, 0);
        if (!(rdev->flags & RADEON_IS_AGP))
                radeon_gtt_location(rdev, &rdev->mc);
-        /* FIXME: we should enforce default clock in case GPU is not in
+        radeon_update_bandwidth_info(rdev);
-         * default setup
-         */
-        a.full = rfixed_const(100);
-        rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
-        rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
 }
 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
@@ -539,6 +535,7 @@ void rv515_set_safe_registers(struct radeon_device *rdev)
 void rv515_fini(struct radeon_device *rdev)
 {
+        radeon_pm_fini(rdev);
        r100_cp_fini(rdev);
        r100_wb_fini(rdev);
        r100_ib_fini(rdev);
@@ -1020,7 +1017,7 @@ void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
        struct drm_display_mode *mode1 = NULL;
        struct rv515_watermark wm0;
        struct rv515_watermark wm1;
-        u32 tmp;
+        u32 tmp, d1mode_priority_a_cnt, d2mode_priority_a_cnt;
        fixed20_12 priority_mark02, priority_mark12, fill_rate;
        fixed20_12 a, b;
@@ -1088,10 +1085,16 @@ void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
                        priority_mark12.full = 0;
                if (wm1.priority_mark_max.full > priority_mark12.full)
                        priority_mark12.full = wm1.priority_mark_max.full;
-                WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
+                d1mode_priority_a_cnt = rfixed_trunc(priority_mark02);
-                WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
+                d2mode_priority_a_cnt = rfixed_trunc(priority_mark12);
-                WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
+                if (rdev->disp_priority == 2) {
-                WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
+                        d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
+                        d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
+                }
+                WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
+                WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
+                WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
+                WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
        } else if (mode0) {
                if (rfixed_trunc(wm0.dbpp) > 64)
                        a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
@@ -1118,8 +1121,11 @@ void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
                        priority_mark02.full = 0;
                if (wm0.priority_mark_max.full > priority_mark02.full)
                        priority_mark02.full = wm0.priority_mark_max.full;
-                WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
+                d1mode_priority_a_cnt = rfixed_trunc(priority_mark02);
-                WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
+                if (rdev->disp_priority == 2)
+                        d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
+                WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
+                WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
                WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
                WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
        } else {
@@ -1148,10 +1154,13 @@ void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
                        priority_mark12.full = 0;
                if (wm1.priority_mark_max.full > priority_mark12.full)
                        priority_mark12.full = wm1.priority_mark_max.full;
+                d2mode_priority_a_cnt = rfixed_trunc(priority_mark12);
+                if (rdev->disp_priority == 2)
+                        d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
                WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
                WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
-                WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
+                WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
-                WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
+                WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
        }
 }
@@ -1161,6 +1170,8 @@ void rv515_bandwidth_update(struct radeon_device *rdev)
        struct drm_display_mode *mode0 = NULL;
        struct drm_display_mode *mode1 = NULL;
+        radeon_update_display_priority(rdev);
        if (rdev->mode_info.crtcs[0]->base.enabled)
                mode0 = &rdev->mode_info.crtcs[0]->base.mode;
        if (rdev->mode_info.crtcs[1]->base.enabled)
@@ -1170,7 +1181,8 @@ void rv515_bandwidth_update(struct radeon_device *rdev)
         * modes if the user specifies HIGH for displaypriority
         * option.
         */
-        if (rdev->disp_priority == 2) {
+        if ((rdev->disp_priority == 2) &&
+            (rdev->family == CHIP_RV515)) {
                tmp = RREG32_MC(MC_MISC_LAT_TIMER);
                tmp &= ~MC_DISP1R_INIT_LAT_MASK;
                tmp &= ~MC_DISP0R_INIT_LAT_MASK;
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 37887dee12af..97958a64df1a 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -27,8 +27,10 @@
 */
 #include <linux/firmware.h>
 #include <linux/platform_device.h>
+#include <linux/slab.h>
 #include "drmP.h"
 #include "radeon.h"
+#include "radeon_asic.h"
 #include "radeon_drm.h"
 #include "rv770d.h"
 #include "atom.h"
@@ -125,9 +127,9 @@ void rv770_pcie_gart_disable(struct radeon_device *rdev)
 void rv770_pcie_gart_fini(struct radeon_device *rdev)
 {
+        radeon_gart_fini(rdev);
        rv770_pcie_gart_disable(rdev);
        radeon_gart_table_vram_free(rdev);
-        radeon_gart_fini(rdev);
 }
@@ -647,10 +649,13 @@ static void rv770_gpu_init(struct radeon_device *rdev)
        WREG32(CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
        WREG32(CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
+        WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
        WREG32(CC_SYS_RB_BACKEND_DISABLE,  cc_rb_backend_disable);
        WREG32(CGTS_SYS_TCC_DISABLE, 0);
        WREG32(CGTS_TCC_DISABLE, 0);
+        WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
+        WREG32(CGTS_USER_TCC_DISABLE, 0);
        num_qd_pipes =
                R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
@@ -864,7 +869,6 @@ static void rv770_gpu_init(struct radeon_device *rdev)
 int rv770_mc_init(struct radeon_device *rdev)
 {
-        fixed20_12 a;
        u32 tmp;
        int chansize, numchan;
@@ -908,12 +912,8 @@ int rv770_mc_init(struct radeon_device *rdev)
                rdev->mc.real_vram_size = rdev->mc.aper_size;
        }
        r600_vram_gtt_location(rdev, &rdev->mc);
-        /* FIXME: we should enforce default clock in case GPU is not in
+        radeon_update_bandwidth_info(rdev);
-         * default setup
-         */
-        a.full = rfixed_const(100);
-        rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
-        rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
        return 0;
 }
@@ -1013,6 +1013,13 @@ int rv770_resume(struct radeon_device *rdev)
                DRM_ERROR("radeon: failled testing IB (%d).\n", r);
                return r;
        }
+        r = r600_audio_init(rdev);
+        if (r) {
+                dev_err(rdev->dev, "radeon: audio init failed\n");
+                return r;
+        }
        return r;
 }
@@ -1021,6 +1028,7 @@ int rv770_suspend(struct radeon_device *rdev)
 {
        int r;
+        r600_audio_fini(rdev);
        /* FIXME: we should wait for ring to be empty */
        r700_cp_stop(rdev);
        rdev->cp.ready = false;
@@ -1144,11 +1152,19 @@ int rv770_init(struct radeon_device *rdev)
                        }
                }
        }
+        r = r600_audio_init(rdev);
+        if (r) {
+                dev_err(rdev->dev, "radeon: audio init failed\n");
+                return r;
+        }
        return 0;
 }
 void rv770_fini(struct radeon_device *rdev)
 {
+        radeon_pm_fini(rdev);
        r600_blit_fini(rdev);
        r600_cp_fini(rdev);
        r600_wb_fini(rdev);
author	Jiri Kosina <jkosina@suse.cz>	2010-04-22 20:08:44 -0400
committer	Jiri Kosina <jkosina@suse.cz>	2010-04-22 20:08:44 -0400
commit	6c9468e9eb1252eaefd94ce7f06e1be9b0b641b1 (patch)
tree	797676a336b050bfa1ef879377c07e541b9075d6 /drivers/gpu/drm/radeon
parent	4cb3ca7cd7e2cae8d1daf5345ec99a1e8502cf3f (diff)
parent	c81eddb0e3728661d1585fbc564449c94165cc36 (diff)