diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/reg_srcs/r600')
-rw-r--r-- | drivers/gpu/drm/radeon/reg_srcs/r600 | 75 |
1 files changed, 0 insertions, 75 deletions
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r600 b/drivers/gpu/drm/radeon/reg_srcs/r600 index 8f414a5f520f..af0da4ae3f55 100644 --- a/drivers/gpu/drm/radeon/reg_srcs/r600 +++ b/drivers/gpu/drm/radeon/reg_srcs/r600 | |||
@@ -26,20 +26,16 @@ r600 0x9400 | |||
26 | 0x00028408 VGT_INDX_OFFSET | 26 | 0x00028408 VGT_INDX_OFFSET |
27 | 0x00028AA0 VGT_INSTANCE_STEP_RATE_0 | 27 | 0x00028AA0 VGT_INSTANCE_STEP_RATE_0 |
28 | 0x00028AA4 VGT_INSTANCE_STEP_RATE_1 | 28 | 0x00028AA4 VGT_INSTANCE_STEP_RATE_1 |
29 | 0x000088C0 VGT_LAST_COPY_STATE | ||
30 | 0x00028400 VGT_MAX_VTX_INDX | 29 | 0x00028400 VGT_MAX_VTX_INDX |
31 | 0x000088D8 VGT_MC_LAT_CNTL | ||
32 | 0x00028404 VGT_MIN_VTX_INDX | 30 | 0x00028404 VGT_MIN_VTX_INDX |
33 | 0x00028A94 VGT_MULTI_PRIM_IB_RESET_EN | 31 | 0x00028A94 VGT_MULTI_PRIM_IB_RESET_EN |
34 | 0x0002840C VGT_MULTI_PRIM_IB_RESET_INDX | 32 | 0x0002840C VGT_MULTI_PRIM_IB_RESET_INDX |
35 | 0x00008970 VGT_NUM_INDICES | 33 | 0x00008970 VGT_NUM_INDICES |
36 | 0x00008974 VGT_NUM_INSTANCES | 34 | 0x00008974 VGT_NUM_INSTANCES |
37 | 0x00028A10 VGT_OUTPUT_PATH_CNTL | 35 | 0x00028A10 VGT_OUTPUT_PATH_CNTL |
38 | 0x00028C5C VGT_OUT_DEALLOC_CNTL | ||
39 | 0x00028A84 VGT_PRIMITIVEID_EN | 36 | 0x00028A84 VGT_PRIMITIVEID_EN |
40 | 0x00008958 VGT_PRIMITIVE_TYPE | 37 | 0x00008958 VGT_PRIMITIVE_TYPE |
41 | 0x00028AB4 VGT_REUSE_OFF | 38 | 0x00028AB4 VGT_REUSE_OFF |
42 | 0x00028C58 VGT_VERTEX_REUSE_BLOCK_CNTL | ||
43 | 0x00028AB8 VGT_VTX_CNT_EN | 39 | 0x00028AB8 VGT_VTX_CNT_EN |
44 | 0x000088B0 VGT_VTX_VECT_EJECT_REG | 40 | 0x000088B0 VGT_VTX_VECT_EJECT_REG |
45 | 0x00028810 PA_CL_CLIP_CNTL | 41 | 0x00028810 PA_CL_CLIP_CNTL |
@@ -280,7 +276,6 @@ r600 0x9400 | |||
280 | 0x00028E00 PA_SU_POLY_OFFSET_FRONT_SCALE | 276 | 0x00028E00 PA_SU_POLY_OFFSET_FRONT_SCALE |
281 | 0x00028814 PA_SU_SC_MODE_CNTL | 277 | 0x00028814 PA_SU_SC_MODE_CNTL |
282 | 0x00028C08 PA_SU_VTX_CNTL | 278 | 0x00028C08 PA_SU_VTX_CNTL |
283 | 0x00008C00 SQ_CONFIG | ||
284 | 0x00008C04 SQ_GPR_RESOURCE_MGMT_1 | 279 | 0x00008C04 SQ_GPR_RESOURCE_MGMT_1 |
285 | 0x00008C08 SQ_GPR_RESOURCE_MGMT_2 | 280 | 0x00008C08 SQ_GPR_RESOURCE_MGMT_2 |
286 | 0x00008C10 SQ_STACK_RESOURCE_MGMT_1 | 281 | 0x00008C10 SQ_STACK_RESOURCE_MGMT_1 |
@@ -320,18 +315,6 @@ r600 0x9400 | |||
320 | 0x000283FC SQ_VTX_SEMANTIC_31 | 315 | 0x000283FC SQ_VTX_SEMANTIC_31 |
321 | 0x000288E0 SQ_VTX_SEMANTIC_CLEAR | 316 | 0x000288E0 SQ_VTX_SEMANTIC_CLEAR |
322 | 0x0003CFF4 SQ_VTX_START_INST_LOC | 317 | 0x0003CFF4 SQ_VTX_START_INST_LOC |
323 | 0x0003C000 SQ_TEX_SAMPLER_WORD0_0 | ||
324 | 0x0003C004 SQ_TEX_SAMPLER_WORD1_0 | ||
325 | 0x0003C008 SQ_TEX_SAMPLER_WORD2_0 | ||
326 | 0x00030000 SQ_ALU_CONSTANT0_0 | ||
327 | 0x00030004 SQ_ALU_CONSTANT1_0 | ||
328 | 0x00030008 SQ_ALU_CONSTANT2_0 | ||
329 | 0x0003000C SQ_ALU_CONSTANT3_0 | ||
330 | 0x0003E380 SQ_BOOL_CONST_0 | ||
331 | 0x0003E384 SQ_BOOL_CONST_1 | ||
332 | 0x0003E388 SQ_BOOL_CONST_2 | ||
333 | 0x0003E200 SQ_LOOP_CONST_0 | ||
334 | 0x0003E200 SQ_LOOP_CONST_DX10_0 | ||
335 | 0x000281C0 SQ_ALU_CONST_BUFFER_SIZE_GS_0 | 318 | 0x000281C0 SQ_ALU_CONST_BUFFER_SIZE_GS_0 |
336 | 0x000281C4 SQ_ALU_CONST_BUFFER_SIZE_GS_1 | 319 | 0x000281C4 SQ_ALU_CONST_BUFFER_SIZE_GS_1 |
337 | 0x000281C8 SQ_ALU_CONST_BUFFER_SIZE_GS_2 | 320 | 0x000281C8 SQ_ALU_CONST_BUFFER_SIZE_GS_2 |
@@ -380,54 +363,6 @@ r600 0x9400 | |||
380 | 0x000281B4 SQ_ALU_CONST_BUFFER_SIZE_VS_13 | 363 | 0x000281B4 SQ_ALU_CONST_BUFFER_SIZE_VS_13 |
381 | 0x000281B8 SQ_ALU_CONST_BUFFER_SIZE_VS_14 | 364 | 0x000281B8 SQ_ALU_CONST_BUFFER_SIZE_VS_14 |
382 | 0x000281BC SQ_ALU_CONST_BUFFER_SIZE_VS_15 | 365 | 0x000281BC SQ_ALU_CONST_BUFFER_SIZE_VS_15 |
383 | 0x000289C0 SQ_ALU_CONST_CACHE_GS_0 | ||
384 | 0x000289C4 SQ_ALU_CONST_CACHE_GS_1 | ||
385 | 0x000289C8 SQ_ALU_CONST_CACHE_GS_2 | ||
386 | 0x000289CC SQ_ALU_CONST_CACHE_GS_3 | ||
387 | 0x000289D0 SQ_ALU_CONST_CACHE_GS_4 | ||
388 | 0x000289D4 SQ_ALU_CONST_CACHE_GS_5 | ||
389 | 0x000289D8 SQ_ALU_CONST_CACHE_GS_6 | ||
390 | 0x000289DC SQ_ALU_CONST_CACHE_GS_7 | ||
391 | 0x000289E0 SQ_ALU_CONST_CACHE_GS_8 | ||
392 | 0x000289E4 SQ_ALU_CONST_CACHE_GS_9 | ||
393 | 0x000289E8 SQ_ALU_CONST_CACHE_GS_10 | ||
394 | 0x000289EC SQ_ALU_CONST_CACHE_GS_11 | ||
395 | 0x000289F0 SQ_ALU_CONST_CACHE_GS_12 | ||
396 | 0x000289F4 SQ_ALU_CONST_CACHE_GS_13 | ||
397 | 0x000289F8 SQ_ALU_CONST_CACHE_GS_14 | ||
398 | 0x000289FC SQ_ALU_CONST_CACHE_GS_15 | ||
399 | 0x00028940 SQ_ALU_CONST_CACHE_PS_0 | ||
400 | 0x00028944 SQ_ALU_CONST_CACHE_PS_1 | ||
401 | 0x00028948 SQ_ALU_CONST_CACHE_PS_2 | ||
402 | 0x0002894C SQ_ALU_CONST_CACHE_PS_3 | ||
403 | 0x00028950 SQ_ALU_CONST_CACHE_PS_4 | ||
404 | 0x00028954 SQ_ALU_CONST_CACHE_PS_5 | ||
405 | 0x00028958 SQ_ALU_CONST_CACHE_PS_6 | ||
406 | 0x0002895C SQ_ALU_CONST_CACHE_PS_7 | ||
407 | 0x00028960 SQ_ALU_CONST_CACHE_PS_8 | ||
408 | 0x00028964 SQ_ALU_CONST_CACHE_PS_9 | ||
409 | 0x00028968 SQ_ALU_CONST_CACHE_PS_10 | ||
410 | 0x0002896C SQ_ALU_CONST_CACHE_PS_11 | ||
411 | 0x00028970 SQ_ALU_CONST_CACHE_PS_12 | ||
412 | 0x00028974 SQ_ALU_CONST_CACHE_PS_13 | ||
413 | 0x00028978 SQ_ALU_CONST_CACHE_PS_14 | ||
414 | 0x0002897C SQ_ALU_CONST_CACHE_PS_15 | ||
415 | 0x00028980 SQ_ALU_CONST_CACHE_VS_0 | ||
416 | 0x00028984 SQ_ALU_CONST_CACHE_VS_1 | ||
417 | 0x00028988 SQ_ALU_CONST_CACHE_VS_2 | ||
418 | 0x0002898C SQ_ALU_CONST_CACHE_VS_3 | ||
419 | 0x00028990 SQ_ALU_CONST_CACHE_VS_4 | ||
420 | 0x00028994 SQ_ALU_CONST_CACHE_VS_5 | ||
421 | 0x00028998 SQ_ALU_CONST_CACHE_VS_6 | ||
422 | 0x0002899C SQ_ALU_CONST_CACHE_VS_7 | ||
423 | 0x000289A0 SQ_ALU_CONST_CACHE_VS_8 | ||
424 | 0x000289A4 SQ_ALU_CONST_CACHE_VS_9 | ||
425 | 0x000289A8 SQ_ALU_CONST_CACHE_VS_10 | ||
426 | 0x000289AC SQ_ALU_CONST_CACHE_VS_11 | ||
427 | 0x000289B0 SQ_ALU_CONST_CACHE_VS_12 | ||
428 | 0x000289B4 SQ_ALU_CONST_CACHE_VS_13 | ||
429 | 0x000289B8 SQ_ALU_CONST_CACHE_VS_14 | ||
430 | 0x000289BC SQ_ALU_CONST_CACHE_VS_15 | ||
431 | 0x000288D8 SQ_PGM_CF_OFFSET_ES | 366 | 0x000288D8 SQ_PGM_CF_OFFSET_ES |
432 | 0x000288DC SQ_PGM_CF_OFFSET_FS | 367 | 0x000288DC SQ_PGM_CF_OFFSET_FS |
433 | 0x000288D4 SQ_PGM_CF_OFFSET_GS | 368 | 0x000288D4 SQ_PGM_CF_OFFSET_GS |
@@ -494,12 +429,7 @@ r600 0x9400 | |||
494 | 0x00028438 SX_ALPHA_REF | 429 | 0x00028438 SX_ALPHA_REF |
495 | 0x00028410 SX_ALPHA_TEST_CONTROL | 430 | 0x00028410 SX_ALPHA_TEST_CONTROL |
496 | 0x00028350 SX_MISC | 431 | 0x00028350 SX_MISC |
497 | 0x0000A020 SMX_DC_CTL0 | ||
498 | 0x0000A024 SMX_DC_CTL1 | ||
499 | 0x0000A028 SMX_DC_CTL2 | ||
500 | 0x00009608 TC_CNTL | ||
501 | 0x00009604 TC_INVALIDATE | 432 | 0x00009604 TC_INVALIDATE |
502 | 0x00009490 TD_CNTL | ||
503 | 0x00009400 TD_FILTER4 | 433 | 0x00009400 TD_FILTER4 |
504 | 0x00009404 TD_FILTER4_1 | 434 | 0x00009404 TD_FILTER4_1 |
505 | 0x00009408 TD_FILTER4_2 | 435 | 0x00009408 TD_FILTER4_2 |
@@ -824,14 +754,9 @@ r600 0x9400 | |||
824 | 0x00028428 CB_FOG_GREEN | 754 | 0x00028428 CB_FOG_GREEN |
825 | 0x00028424 CB_FOG_RED | 755 | 0x00028424 CB_FOG_RED |
826 | 0x00008040 WAIT_UNTIL | 756 | 0x00008040 WAIT_UNTIL |
827 | 0x00008950 CC_GC_SHADER_PIPE_CONFIG | ||
828 | 0x00008954 GC_USER_SHADER_PIPE_CONFIG | ||
829 | 0x00009714 VC_ENHANCE | 757 | 0x00009714 VC_ENHANCE |
830 | 0x00009830 DB_DEBUG | 758 | 0x00009830 DB_DEBUG |
831 | 0x00009838 DB_WATERMARKS | 759 | 0x00009838 DB_WATERMARKS |
832 | 0x00028D28 DB_SRESULTS_COMPARE_STATE0 | 760 | 0x00028D28 DB_SRESULTS_COMPARE_STATE0 |
833 | 0x00028D44 DB_ALPHA_TO_MASK | 761 | 0x00028D44 DB_ALPHA_TO_MASK |
834 | 0x00009504 TA_CNTL | ||
835 | 0x00009700 VC_CNTL | 762 | 0x00009700 VC_CNTL |
836 | 0x00009718 VC_CONFIG | ||
837 | 0x0000A02C SMX_DC_MC_INTF_CTL | ||