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path: root/drivers/gpu/drm/radeon/rs600.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/rs600.c')
-rw-r--r--drivers/gpu/drm/radeon/rs600.c35
1 files changed, 32 insertions, 3 deletions
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 47f046b78c6b..a81bc7a21e14 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -37,6 +37,7 @@
37 */ 37 */
38#include "drmP.h" 38#include "drmP.h"
39#include "radeon.h" 39#include "radeon.h"
40#include "radeon_asic.h"
40#include "atom.h" 41#include "atom.h"
41#include "rs600d.h" 42#include "rs600d.h"
42 43
@@ -158,7 +159,7 @@ void rs600_gart_tlb_flush(struct radeon_device *rdev)
158 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 159 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
159 160
160 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 161 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
161 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1); 162 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
162 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 163 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
163 164
164 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 165 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
@@ -267,9 +268,9 @@ void rs600_gart_disable(struct radeon_device *rdev)
267 268
268void rs600_gart_fini(struct radeon_device *rdev) 269void rs600_gart_fini(struct radeon_device *rdev)
269{ 270{
271 radeon_gart_fini(rdev);
270 rs600_gart_disable(rdev); 272 rs600_gart_disable(rdev);
271 radeon_gart_table_vram_free(rdev); 273 radeon_gart_table_vram_free(rdev);
272 radeon_gart_fini(rdev);
273} 274}
274 275
275#define R600_PTE_VALID (1 << 0) 276#define R600_PTE_VALID (1 << 0)
@@ -392,10 +393,12 @@ int rs600_irq_process(struct radeon_device *rdev)
392 /* Vertical blank interrupts */ 393 /* Vertical blank interrupts */
393 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int)) { 394 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int)) {
394 drm_handle_vblank(rdev->ddev, 0); 395 drm_handle_vblank(rdev->ddev, 0);
396 rdev->pm.vblank_sync = true;
395 wake_up(&rdev->irq.vblank_queue); 397 wake_up(&rdev->irq.vblank_queue);
396 } 398 }
397 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int)) { 399 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int)) {
398 drm_handle_vblank(rdev->ddev, 1); 400 drm_handle_vblank(rdev->ddev, 1);
401 rdev->pm.vblank_sync = true;
399 wake_up(&rdev->irq.vblank_queue); 402 wake_up(&rdev->irq.vblank_queue);
400 } 403 }
401 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(r500_disp_int)) { 404 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(r500_disp_int)) {
@@ -472,13 +475,38 @@ void rs600_mc_init(struct radeon_device *rdev)
472 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 475 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
473 base = RREG32_MC(R_000004_MC_FB_LOCATION); 476 base = RREG32_MC(R_000004_MC_FB_LOCATION);
474 base = G_000004_MC_FB_START(base) << 16; 477 base = G_000004_MC_FB_START(base) << 16;
478 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
475 radeon_vram_location(rdev, &rdev->mc, base); 479 radeon_vram_location(rdev, &rdev->mc, base);
476 radeon_gtt_location(rdev, &rdev->mc); 480 radeon_gtt_location(rdev, &rdev->mc);
481 radeon_update_bandwidth_info(rdev);
477} 482}
478 483
479void rs600_bandwidth_update(struct radeon_device *rdev) 484void rs600_bandwidth_update(struct radeon_device *rdev)
480{ 485{
481 /* FIXME: implement, should this be like rs690 ? */ 486 struct drm_display_mode *mode0 = NULL;
487 struct drm_display_mode *mode1 = NULL;
488 u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
489 /* FIXME: implement full support */
490
491 radeon_update_display_priority(rdev);
492
493 if (rdev->mode_info.crtcs[0]->base.enabled)
494 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
495 if (rdev->mode_info.crtcs[1]->base.enabled)
496 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
497
498 rs690_line_buffer_adjust(rdev, mode0, mode1);
499
500 if (rdev->disp_priority == 2) {
501 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
502 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
503 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
504 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
505 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
506 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
507 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
508 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
509 }
482} 510}
483 511
484uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) 512uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
@@ -598,6 +626,7 @@ int rs600_suspend(struct radeon_device *rdev)
598 626
599void rs600_fini(struct radeon_device *rdev) 627void rs600_fini(struct radeon_device *rdev)
600{ 628{
629 radeon_pm_fini(rdev);
601 r100_cp_fini(rdev); 630 r100_cp_fini(rdev);
602 r100_wb_fini(rdev); 631 r100_wb_fini(rdev);
603 r100_ib_fini(rdev); 632 r100_ib_fini(rdev);