Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC device tree changes from Arnd Bergmann:
 "These changes from 30 individual branches for the most part update
  device tree files, but there are also a few source code changes that
  have crept in this time, usually in order to atomically move over a
  driver from using hardcoded data to DT probing.

  A number of platforms change their DT files to use the C preprocessor,
  which is causing a bit of churn, but that is hopefully only this once"

* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (372 commits)
  ARM: at91: dt: rm9200ek: add spi support
  ARM: at91: dt: rm9200: add spi support
  ARM: at91/DT: at91sam9n12: add SPI DMA client infos
  ARM: at91/DT: sama5d3: add SPI DMA client infos
  ARM: at91/DT: fix SPI compatibility string
  ARM: Kirkwood: Fix the internal register ranges translation
  ARM: dts: bcm281xx: change comment to C89 style
  ARM: mmc: bcm281xx SDHCI driver (dt mods)
  ARM: nomadik: add the new clocks to the device tree
  clk: nomadik: implement the Nomadik clocks properly
  ARM: dts: omap5-uevm: Provide USB Host PHY clock frequency
  ARM: dts: omap4-panda: Fix DVI EDID reads
  ARM: dts: omap4-panda: Add USB Host support
  arm: mvebu: enable mini-PCIe connectors on Armada 370 RD
  ARM: shmobile: irqpin: add a DT property to enable masking on parent
  ARM: dts: AM43x EPOS EVM support
  ARM: dts: OMAP5: Add bandgap DT entry
  ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM
  ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk
  ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone
  ...

261 files changed, 13440 insertions, 2610 deletions

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f9eae2f0ae5d..962c0eee3039 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -16,11 +16,13 @@ dtb-$(CONFIG_ARCH_AT91) += at91sam9263ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += tny_a9263.dtb
 dtb-$(CONFIG_ARCH_AT91) += usb_a9263.dtb
 # sam9g20
+dtb-$(CONFIG_ARCH_AT91) += at91-foxg20.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek_2mmc.dtb
 dtb-$(CONFIG_ARCH_AT91) += kizbox.dtb
 dtb-$(CONFIG_ARCH_AT91) += tny_a9g20.dtb
 dtb-$(CONFIG_ARCH_AT91) += usb_a9g20.dtb
+dtb-$(CONFIG_ARCH_AT91) += usb_a9g20_lpw.dtb
 # sam9g45
 dtb-$(CONFIG_ARCH_AT91) += at91sam9m10g45ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb
@@ -86,6 +88,8 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
         kirkwood-ns2max.dtb \
         kirkwood-ns2mini.dtb \
         kirkwood-nsa310.dtb \
+        kirkwood-sheevaplug.dtb \
+        kirkwood-sheevaplug-esata.dtb \
         kirkwood-topkick.dtb \
         kirkwood-ts219-6281.dtb \
         kirkwood-ts219-6282.dtb \
@@ -105,13 +109,15 @@ dtb-$(CONFIG_ARCH_MXC) += \
         imx27-apf27.dtb \
         imx27-apf27dev.dtb \
         imx27-pdk.dtb \
-        imx27-phytec-phycore.dtb \
+        imx27-phytec-phycore-som.dtb \
+        imx27-phytec-phycore-rdk.dtb \
         imx31-bug.dtb \
         imx51-apf51.dtb \
         imx51-apf51dev.dtb \
         imx51-babbage.dtb \
         imx53-ard.dtb \
         imx53-evk.dtb \
+        imx53-m53evk.dtb \
         imx53-mba53.dtb \
         imx53-qsb.dtb \
         imx53-smd.dtb \
@@ -119,10 +125,13 @@ dtb-$(CONFIG_ARCH_MXC) += \
         imx6dl-sabresd.dtb \
         imx6dl-wandboard.dtb \
         imx6q-arm2.dtb \
+        imx6q-phytec-pbab01.dtb \
         imx6q-sabreauto.dtb \
         imx6q-sabrelite.dtb \
         imx6q-sabresd.dtb \
-        imx6q-sbc6x.dtb
+        imx6q-sbc6x.dtb \
+        imx6sl-evk.dtb \
+        vf610-twr.dtb
 dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
         imx23-olinuxino.dtb \
         imx23-stmp378x_devb.dtb \
@@ -132,6 +141,8 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
         imx28-cfa10036.dtb \
         imx28-cfa10037.dtb \
         imx28-cfa10049.dtb \
+        imx28-cfa10055.dtb \
+        imx28-cfa10057.dtb \
         imx28-evk.dtb \
         imx28-m28evk.dtb \
         imx28-sps1.dtb \
@@ -151,19 +162,26 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
         omap4-panda-es.dtb \
         omap4-var-som.dtb \
         omap4-sdp.dtb \
-        omap5-evm.dtb \
+        omap4-sdp-es23plus.dtb \
+        omap5-uevm.dtb \
         am335x-evm.dtb \
         am335x-evmsk.dtb \
-        am335x-bone.dtb
+        am335x-bone.dtb \
+        am3517-evm.dtb \
+        am3517_mt_ventoux.dtb \
+        am43x-epos-evm.dtb
 dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
 dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
 dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
         hrefprev60.dtb \
         hrefv60plus.dtb \
+        ccu8540.dtb \
         ccu9540.dtb
+dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
 dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
         r8a7740-armadillo800eva.dtb \
         r8a7778-bockw.dtb \
+        r8a7740-armadillo800eva-reference.dtb \
         r8a7779-marzen-reference.dtb \
         r8a7790-lager.dtb \
         sh73a0-kzm9g.dtb \
@@ -183,6 +201,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
         sun4i-a10-cubieboard.dtb \
         sun4i-a10-mini-xplus.dtb \
         sun4i-a10-hackberry.dtb \
+        sun5i-a10s-olinuxino-micro.dtb \
         sun5i-a13-olinuxino.dtb
 dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
         tegra20-iris-512.dtb \
@@ -210,8 +229,11 @@ dtb-$(CONFIG_ARCH_VIRT) += xenvm-4.2.dtb
 dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
         wm8505-ref.dtb \
         wm8650-mid.dtb \
+        wm8750-apc8750.dtb \
         wm8850-w70v2.dtb
-dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb
+dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
+        zynq-zc706.dtb \
+        zynq-zed.dtb
 
 targets += dtbs
 targets += $(dtb-y)
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index 5302f79c05b7..04feaf8f1420 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "am33xx.dtsi"
+#include "am33xx.dtsi"
 
 / {
         model = "TI AM335x BeagleBone";
@@ -26,24 +26,104 @@
 
         am33xx_pinmux: pinmux@44e10800 {
                 pinctrl-names = "default";
-                pinctrl-0 = <&user_leds_s0>;
+                pinctrl-0 = <&clkout2_pin>;
 
                 user_leds_s0: user_leds_s0 {
                         pinctrl-single,pins = <
-                                0x54 0x7        /* gpmc_a5.gpio1_21, OUTPUT | MODE7 */
-                                0x58 0x17       /* gpmc_a6.gpio1_22, OUTPUT_PULLUP | MODE7 */
-                                0x5c 0x7        /* gpmc_a7.gpio1_23, OUTPUT | MODE7 */
-                                0x60 0x17       /* gpmc_a8.gpio1_24, OUTPUT_PULLUP | MODE7 */
+                                0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a5.gpio1_21 */
+                                0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7)    /* gpmc_a6.gpio1_22 */
+                                0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a7.gpio1_23 */
+                                0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7)    /* gpmc_a8.gpio1_24 */
+                        >;
+                };
+
+                i2c0_pins: pinmux_i2c0_pins {
+                        pinctrl-single,pins = <
+                                0x188 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
+                                0x18c (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
+                        >;
+                };
+
+                uart0_pins: pinmux_uart0_pins {
+                        pinctrl-single,pins = <
+                                0x170 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
+                                0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+                        >;
+                };
+
+                clkout2_pin: pinmux_clkout2_pin {
+                        pinctrl-single,pins = <
+                                0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
+                        >;
+                };
+
+                cpsw_default: cpsw_default {
+                        pinctrl-single,pins = <
+                                /* Slave 1 */
+                                0x110 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxerr.mii1_rxerr */
+                                0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
+                                0x118 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxdv.mii1_rxdv */
+                                0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
+                                0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
+                                0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
+                                0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
+                                0x12c (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_txclk.mii1_txclk */
+                                0x130 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxclk.mii1_rxclk */
+                                0x134 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd3.mii1_rxd3 */
+                                0x138 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd2.mii1_rxd2 */
+                                0x13c (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd1.mii1_rxd1 */
+                                0x140 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd0.mii1_rxd0 */
+                        >;
+                };
+
+                cpsw_sleep: cpsw_sleep {
+                        pinctrl-single,pins = <
+                                /* Slave 1 reset value */
+                                0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        >;
+                };
+
+                davinci_mdio_default: davinci_mdio_default {
+                        pinctrl-single,pins = <
+                                /* MDIO */
+                                0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
+                                0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
+                        >;
+                };
+
+                davinci_mdio_sleep: davinci_mdio_sleep {
+                        pinctrl-single,pins = <
+                                /* MDIO reset value */
+                                0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
                         >;
                 };
         };
 
         ocp {
-                uart1: serial@44e09000 {
+                uart0: serial@44e09000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins>;
+
                         status = "okay";
                 };
 
                 i2c0: i2c@44e0b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins>;
+
                         status = "okay";
                         clock-frequency = <400000>;
 
@@ -55,31 +135,34 @@
         };
 
         leds {
+                pinctrl-names = "default";
+                pinctrl-0 = <&user_leds_s0>;
+
                 compatible = "gpio-leds";
 
                 led@2 {
                         label = "beaglebone:green:heartbeat";
-                        gpios = <&gpio1 21 0>;
+                        gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
                         linux,default-trigger = "heartbeat";
                         default-state = "off";
                 };
 
                 led@3 {
                         label = "beaglebone:green:mmc0";
-                        gpios = <&gpio1 22 0>;
+                        gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
                         linux,default-trigger = "mmc0";
                         default-state = "off";
                 };
 
                 led@4 {
                         label = "beaglebone:green:usr2";
-                        gpios = <&gpio1 23 0>;
+                        gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
                         default-state = "off";
                 };
 
                 led@5 {
                         label = "beaglebone:green:usr3";
-                        gpios = <&gpio1 24 0>;
+                        gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
                         default-state = "off";
                 };
         };
@@ -136,3 +219,16 @@
 &cpsw_emac1 {
         phy_id = <&davinci_mdio>, <1>;
 };
+
+&mac {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&cpsw_default>;
+        pinctrl-1 = <&cpsw_sleep>;
+
+};
+
+&davinci_mdio {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&davinci_mdio_default>;
+        pinctrl-1 = <&davinci_mdio_sleep>;
+};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 0423298a26fe..a16bb9691cc6 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "am33xx.dtsi"
+#include "am33xx.dtsi"
 
 / {
         model = "TI AM335x EVM";
@@ -26,32 +26,143 @@
 
         am33xx_pinmux: pinmux@44e10800 {
                 pinctrl-names = "default";
-                pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0>;
+                pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
 
                 matrix_keypad_s0: matrix_keypad_s0 {
                         pinctrl-single,pins = <
-                                0x54 0x7        /* gpmc_a5.gpio1_21, OUTPUT | MODE7 */
-                                0x58 0x7        /* gpmc_a6.gpio1_22, OUTPUT | MODE7 */
-                                0x64 0x27       /* gpmc_a9.gpio1_25, INPUT | MODE7 */
-                                0x68 0x27       /* gpmc_a10.gpio1_26, INPUT | MODE7 */
-                                0x6c 0x27       /* gpmc_a11.gpio1_27, INPUT | MODE7 */
+                                0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a5.gpio1_21 */
+                                0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a6.gpio1_22 */
+                                0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a9.gpio1_25 */
+                                0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a10.gpio1_26 */
+                                0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a11.gpio1_27 */
                         >;
                 };
 
                 volume_keys_s0: volume_keys_s0 {
                         pinctrl-single,pins = <
-                                0x150 0x27      /* spi0_sclk.gpio0_2, INPUT | MODE7 */
-                                0x154 0x27      /* spi0_d0.gpio0_3, INPUT | MODE7 */
+                                0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* spi0_sclk.gpio0_2 */
+                                0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* spi0_d0.gpio0_3 */
+                        >;
+                };
+
+                i2c0_pins: pinmux_i2c0_pins {
+                        pinctrl-single,pins = <
+                                0x188 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
+                                0x18c (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
+                        >;
+                };
+
+                i2c1_pins: pinmux_i2c1_pins {
+                        pinctrl-single,pins = <
+                                0x158 (PIN_INPUT_PULLUP | MUX_MODE2)    /* spi0_d1.i2c1_sda */
+                                0x15c (PIN_INPUT_PULLUP | MUX_MODE2)    /* spi0_cs0.i2c1_scl */
+                        >;
+                };
+
+                uart0_pins: pinmux_uart0_pins {
+                        pinctrl-single,pins = <
+                                0x170 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
+                                0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+                        >;
+                };
+
+                clkout2_pin: pinmux_clkout2_pin {
+                        pinctrl-single,pins = <
+                                0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
+                        >;
+                };
+
+                nandflash_pins_s0: nandflash_pins_s0 {
+                        pinctrl-single,pins = <
+                                0x0 (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad0.gpmc_ad0 */
+                                0x4 (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad1.gpmc_ad1 */
+                                0x8 (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad2.gpmc_ad2 */
+                                0xc (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad3.gpmc_ad3 */
+                                0x10 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad4.gpmc_ad4 */
+                                0x14 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad5.gpmc_ad5 */
+                                0x18 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad6.gpmc_ad6 */
+                                0x1c (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad7.gpmc_ad7 */
+                                0x70 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_wait0.gpmc_wait0 */
+                                0x74 (PIN_INPUT_PULLUP | MUX_MODE7)     /* gpmc_wpn.gpio0_30 */
+                                0x7c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_csn0.gpmc_csn0  */
+                                0x90 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_advn_ale.gpmc_advn_ale */
+                                0x94 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_oen_ren.gpmc_oen_ren */
+                                0x98 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_wen.gpmc_wen */
+                                0x9c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_be0n_cle.gpmc_be0n_cle */
+                        >;
+                };
+
+                ecap0_pins: backlight_pins {
+                        pinctrl-single,pins = <
+                                0x164 0x0       /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
+                        >;
+                };
+
+                cpsw_default: cpsw_default {
+                        pinctrl-single,pins = <
+                                /* Slave 1 */
+                                0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
+                                0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxdv.rgmii1_rctl */
+                                0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
+                                0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
+                                0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
+                                0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
+                                0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
+                                0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxclk.rgmii1_rclk */
+                                0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd3.rgmii1_rd3 */
+                                0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd2.rgmii1_rd2 */
+                                0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rd1 */
+                                0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rd0 */
+                        >;
+                };
+
+                cpsw_sleep: cpsw_sleep {
+                        pinctrl-single,pins = <
+                                /* Slave 1 reset value */
+                                0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        >;
+                };
+
+                davinci_mdio_default: davinci_mdio_default {
+                        pinctrl-single,pins = <
+                                /* MDIO */
+                                0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
+                                0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
+                        >;
+                };
+
+                davinci_mdio_sleep: davinci_mdio_sleep {
+                        pinctrl-single,pins = <
+                                /* MDIO reset value */
+                                0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
                         >;
                 };
         };
 
         ocp {
-                uart1: serial@44e09000 {
+                uart0: serial@44e09000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins>;
+
                         status = "okay";
                 };
 
                 i2c0: i2c@44e0b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins>;
+
                         status = "okay";
                         clock-frequency = <400000>;
 
@@ -61,6 +172,9 @@
                 };
 
                 i2c1: i2c@4802a000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c1_pins>;
+
                         status = "okay";
                         clock-frequency = <100000>;
 
@@ -102,6 +216,101 @@
                                 reg = <0x48>;
                         };
                 };
+
+                elm: elm@48080000 {
+                        status = "okay";
+                };
+
+                epwmss0: epwmss@48300000 {
+                        status = "okay";
+
+                        ecap0: ecap@48300100 {
+                                status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&ecap0_pins>;
+                        };
+                };
+
+                gpmc: gpmc@50000000 {
+                        status = "okay";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&nandflash_pins_s0>;
+                        ranges = <0 0 0x08000000 0x10000000>;   /* CS0: NAND */
+                        nand@0,0 {
+                                reg = <0 0 0>; /* CS0, offset 0 */
+                                nand-bus-width = <8>;
+                                ti,nand-ecc-opt = "bch8";
+                                gpmc,device-nand = "true";
+                                gpmc,device-width = <1>;
+                                gpmc,sync-clk-ps = <0>;
+                                gpmc,cs-on-ns = <0>;
+                                gpmc,cs-rd-off-ns = <44>;
+                                gpmc,cs-wr-off-ns = <44>;
+                                gpmc,adv-on-ns = <6>;
+                                gpmc,adv-rd-off-ns = <34>;
+                                gpmc,adv-wr-off-ns = <44>;
+                                gpmc,we-on-ns = <0>;
+                                gpmc,we-off-ns = <40>;
+                                gpmc,oe-on-ns = <0>;
+                                gpmc,oe-off-ns = <54>;
+                                gpmc,access-ns = <64>;
+                                gpmc,rd-cycle-ns = <82>;
+                                gpmc,wr-cycle-ns = <82>;
+                                gpmc,wait-on-read = "true";
+                                gpmc,wait-on-write = "true";
+                                gpmc,bus-turnaround-ns = <0>;
+                                gpmc,cycle2cycle-delay-ns = <0>;
+                                gpmc,clk-activation-ns = <0>;
+                                gpmc,wait-monitoring-ns = <0>;
+                                gpmc,wr-access-ns = <40>;
+                                gpmc,wr-data-mux-bus-ns = <0>;
+
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                elm_id = <&elm>;
+
+                                /* MTD partition table */
+                                partition@0 {
+                                        label = "SPL1";
+                                        reg = <0x00000000 0x000020000>;
+                                };
+
+                                partition@1 {
+                                        label = "SPL2";
+                                        reg = <0x00020000 0x00020000>;
+                                };
+
+                                partition@2 {
+                                        label = "SPL3";
+                                        reg = <0x00040000 0x00020000>;
+                                };
+
+                                partition@3 {
+                                        label = "SPL4";
+                                        reg = <0x00060000 0x00020000>;
+                                };
+
+                                partition@4 {
+                                        label = "U-boot";
+                                        reg = <0x00080000 0x001e0000>;
+                                };
+
+                                partition@5 {
+                                        label = "environment";
+                                        reg = <0x00260000 0x00020000>;
+                                };
+
+                                partition@6 {
+                                        label = "Kernel";
+                                        reg = <0x00280000 0x00500000>;
+                                };
+
+                                partition@7 {
+                                        label = "File-System";
+                                        reg = <0x00780000 0x0F880000>;
+                                };
+                        };
+                };
         };
 
         vbat: fixedregulator@0 {
@@ -123,12 +332,12 @@
                 debounce-delay-ms = <5>;
                 col-scan-delay-us = <2>;
 
-                row-gpios = <&gpio1 25 0        /* Bank1, pin25 */
-                             &gpio1 26 0        /* Bank1, pin26 */
-                             &gpio1 27 0>;      /* Bank1, pin27 */
+                row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH         /* Bank1, pin25 */
+                             &gpio1 26 GPIO_ACTIVE_HIGH         /* Bank1, pin26 */
+                             &gpio1 27 GPIO_ACTIVE_HIGH>;       /* Bank1, pin27 */
 
-                col-gpios = <&gpio1 21 0        /* Bank1, pin21 */
-                             &gpio1 22 0>;      /* Bank1, pin22 */
+                col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH         /* Bank1, pin21 */
+                             &gpio1 22 GPIO_ACTIVE_HIGH>;       /* Bank1, pin22 */
 
                 linux,keymap = <0x0000008b      /* MENU */
                                 0x0100009e      /* BACK */
@@ -147,20 +356,27 @@
                 switch@9 {
                         label = "volume-up";
                         linux,code = <115>;
-                        gpios = <&gpio0 2 1>;
+                        gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
                         gpio-key,wakeup;
                 };
 
                 switch@10 {
                         label = "volume-down";
                         linux,code = <114>;
-                        gpios = <&gpio0 3 1>;
+                        gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
                         gpio-key,wakeup;
                 };
         };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&ecap0 0 50000 0>;
+                brightness-levels = <0 51 53 56 62 75 101 152 255>;
+                default-brightness-level = <8>;
+        };
 };
 
-/include/ "tps65910.dtsi"
+#include "tps65910.dtsi"
 
 &tps {
         vcc1-supply = <&vbat>;
@@ -237,6 +453,18 @@
         };
 };
 
+&mac {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&cpsw_default>;
+        pinctrl-1 = <&cpsw_sleep>;
+};
+
+&davinci_mdio {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&davinci_mdio_default>;
+        pinctrl-1 = <&davinci_mdio_sleep>;
+};
+
 &cpsw_emac0 {
         phy_id = <&davinci_mdio>, <0>;
 };
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index f67c360844f4..9e00eef9b74b 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -13,7 +13,7 @@
 
 /dts-v1/;
 
-/include/ "am33xx.dtsi"
+#include "am33xx.dtsi"
 
 / {
         model = "TI AM335x EVM-SK";
@@ -32,33 +32,145 @@
 
         am33xx_pinmux: pinmux@44e10800 {
                 pinctrl-names = "default";
-                pinctrl-0 = <&user_leds_s0 &gpio_keys_s0>;
+                pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
 
                 user_leds_s0: user_leds_s0 {
                         pinctrl-single,pins = <
-                                0x10 0x7        /* gpmc_ad4.gpio1_4, OUTPUT | MODE7 */
-                                0x14 0x7        /* gpmc_ad5.gpio1_5, OUTPUT | MODE7 */
-                                0x18 0x7        /* gpmc_ad6.gpio1_6, OUTPUT | MODE7 */
-                                0x1c 0x7        /* gpmc_ad7.gpio1_7, OUTPUT | MODE7 */
+                                0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_ad4.gpio1_4 */
+                                0x14 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_ad5.gpio1_5 */
+                                0x18 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_ad6.gpio1_6 */
+                                0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_ad7.gpio1_7 */
                         >;
                 };
 
                 gpio_keys_s0: gpio_keys_s0 {
                         pinctrl-single,pins = <
-                                0x94 0x27       /* gpmc_oen_ren.gpio2_3, INPUT | MODE7 */
-                                0x90 0x27       /* gpmc_advn_ale.gpio2_2, INPUT | MODE7 */
-                                0x70 0x27       /* gpmc_wait0.gpio0_30, INPUT | MODE7 */
-                                0x9c 0x27       /* gpmc_ben0_cle.gpio2_5, INPUT | MODE7 */
+                                0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_oen_ren.gpio2_3 */
+                                0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_advn_ale.gpio2_2 */
+                                0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_wait0.gpio0_30 */
+                                0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_ben0_cle.gpio2_5 */
+                        >;
+                };
+
+                i2c0_pins: pinmux_i2c0_pins {
+                        pinctrl-single,pins = <
+                                0x188 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
+                                0x18c (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
+                        >;
+                };
+
+                uart0_pins: pinmux_uart0_pins {
+                        pinctrl-single,pins = <
+                                0x170 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
+                                0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)         /* uart0_txd.uart0_txd */
+                        >;
+                };
+
+                clkout2_pin: pinmux_clkout2_pin {
+                        pinctrl-single,pins = <
+                                0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)         /* xdma_event_intr1.clkout2 */
+                        >;
+                };
+
+                ecap2_pins: backlight_pins {
+                        pinctrl-single,pins = <
+                                0x19c 0x4       /* mcasp0_ahclkr.ecap2_in_pwm2_out MODE4 */
+                        >;
+                };
+
+                cpsw_default: cpsw_default {
+                        pinctrl-single,pins = <
+                                /* Slave 1 */
+                                0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
+                                0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxdv.rgmii1_rctl */
+                                0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
+                                0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
+                                0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
+                                0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
+                                0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
+                                0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxclk.rgmii1_rclk */
+                                0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd3.rgmii1_rd3 */
+                                0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd2.rgmii1_rd2 */
+                                0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rd1 */
+                                0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rd0 */
+
+                                /* Slave 2 */
+                                0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)  /* gpmc_a0.rgmii2_tctl */
+                                0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2)   /* gpmc_a1.rgmii2_rctl */
+                                0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)  /* gpmc_a2.rgmii2_td3 */
+                                0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2)  /* gpmc_a3.rgmii2_td2 */
+                                0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)  /* gpmc_a4.rgmii2_td1 */
+                                0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)  /* gpmc_a5.rgmii2_td0 */
+                                0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)  /* gpmc_a6.rgmii2_tclk */
+                                0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2)   /* gpmc_a7.rgmii2_rclk */
+                                0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2)   /* gpmc_a8.rgmii2_rd3 */
+                                0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2)   /* gpmc_a9.rgmii2_rd2 */
+                                0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2)   /* gpmc_a10.rgmii2_rd1 */
+                                0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2)   /* gpmc_a11.rgmii2_rd0 */
+                        >;
+                };
+
+                cpsw_sleep: cpsw_sleep {
+                        pinctrl-single,pins = <
+                                /* Slave 1 reset value */
+                                0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+
+                                /* Slave 2 reset value*/
+                                0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        >;
+                };
+
+                davinci_mdio_default: davinci_mdio_default {
+                        pinctrl-single,pins = <
+                                /* MDIO */
+                                0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
+                                0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
+                        >;
+                };
+
+                davinci_mdio_sleep: davinci_mdio_sleep {
+                        pinctrl-single,pins = <
+                                /* MDIO reset value */
+                                0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
                         >;
                 };
         };
 
         ocp {
-                uart1: serial@44e09000 {
+                uart0: serial@44e09000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins>;
+
                         status = "okay";
                 };
 
                 i2c0: i2c@44e0b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins>;
+
                         status = "okay";
                         clock-frequency = <400000>;
 
@@ -94,6 +206,16 @@
                                 st,max-limit-z = <750>;
                         };
                 };
+
+                epwmss2: epwmss@48304000 {
+                        status = "okay";
+
+                        ecap2: ecap@48304100 {
+                                status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&ecap2_pins>;
+                        };
+                };
         };
 
         vbat: fixedregulator@0 {
@@ -111,30 +233,33 @@
         };
 
         leds {
+                pinctrl-names = "default";
+                pinctrl-0 = <&user_leds_s0>;
+
                 compatible = "gpio-leds";
 
                 led@1 {
                         label = "evmsk:green:usr0";
-                        gpios = <&gpio1 4 0>;
+                        gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
                         default-state = "off";
                 };
 
                 led@2 {
                         label = "evmsk:green:usr1";
-                        gpios = <&gpio1 5 0>;
+                        gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
                         default-state = "off";
                 };
 
                 led@3 {
                         label = "evmsk:green:mmc0";
-                        gpios = <&gpio1 6 0>;
+                        gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
                         linux,default-trigger = "mmc0";
                         default-state = "off";
                 };
 
                 led@4 {
                         label = "evmsk:green:heartbeat";
-                        gpios = <&gpio1 7 0>;
+                        gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
                         linux,default-trigger = "heartbeat";
                         default-state = "off";
                 };
@@ -148,31 +273,38 @@
                 switch@1 {
                         label = "button0";
                         linux,code = <0x100>;
-                        gpios = <&gpio2 3 0>;
+                        gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
                 };
 
                 switch@2 {
                         label = "button1";
                         linux,code = <0x101>;
-                        gpios = <&gpio2 2 0>;
+                        gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
                 };
 
                 switch@3 {
                         label = "button2";
                         linux,code = <0x102>;
-                        gpios = <&gpio0 30 0>;
+                        gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>;
                         gpio-key,wakeup;
                 };
 
                 switch@4 {
                         label = "button3";
                         linux,code = <0x103>;
-                        gpios = <&gpio2 5 0>;
+                        gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
                 };
         };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&ecap2 0 50000 1>;
+                brightness-levels = <0 58 61 66 75 90 125 170 255>;
+                default-brightness-level = <8>;
+        };
 };
 
-/include/ "tps65910.dtsi"
+#include "tps65910.dtsi"
 
 &tps {
         vcc1-supply = <&vbat>;
@@ -248,3 +380,15 @@
                 };
         };
 };
+
+&mac {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&cpsw_default>;
+        pinctrl-1 = <&cpsw_sleep>;
+};
+
+&davinci_mdio {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&davinci_mdio_default>;
+        pinctrl-1 = <&davinci_mdio_sleep>;
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 77aa1b0cf6a7..0d4df90477f7 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -8,26 +8,33 @@
  * kind, whether express or implied.
  */
 
-/include/ "skeleton.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/am33xx.h>
+
+#include "skeleton.dtsi"
 
 / {
         compatible = "ti,am33xx";
         interrupt-parent = <&intc>;
 
         aliases {
-                serial0 = &uart1;
-                serial1 = &uart2;
-                serial2 = &uart3;
-                serial3 = &uart4;
-                serial4 = &uart5;
-                serial5 = &uart6;
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+                serial4 = &uart4;
+                serial5 = &uart5;
                 d_can0 = &dcan0;
                 d_can1 = &dcan1;
         };
 
         cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
                 cpu@0 {
                         compatible = "arm,cortex-a8";
+                        device_type = "cpu";
+                        reg = <0>;
 
                         /*
                          * To consider voltage drop between PMIC and SoC,
@@ -133,7 +140,7 @@
                         interrupts = <62>;
                 };
 
-                uart1: serial@44e09000 {
+                uart0: serial@44e09000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart1";
                         clock-frequency = <48000000>;
@@ -142,7 +149,7 @@
                         status = "disabled";
                 };
 
-                uart2: serial@48022000 {
+                uart1: serial@48022000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart2";
                         clock-frequency = <48000000>;
@@ -151,7 +158,7 @@
                         status = "disabled";
                 };
 
-                uart3: serial@48024000 {
+                uart2: serial@48024000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart3";
                         clock-frequency = <48000000>;
@@ -160,7 +167,7 @@
                         status = "disabled";
                 };
 
-                uart4: serial@481a6000 {
+                uart3: serial@481a6000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart4";
                         clock-frequency = <48000000>;
@@ -169,7 +176,7 @@
                         status = "disabled";
                 };
 
-                uart5: serial@481a8000 {
+                uart4: serial@481a8000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart5";
                         clock-frequency = <48000000>;
@@ -178,7 +185,7 @@
                         status = "disabled";
                 };
 
-                uart6: serial@481aa000 {
+                uart5: serial@481aa000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart6";
                         clock-frequency = <48000000>;
@@ -343,6 +350,90 @@
                         ti,hwmods = "usb_otg_hs";
                 };
 
+                epwmss0: epwmss@48300000 {
+                        compatible = "ti,am33xx-pwmss";
+                        reg = <0x48300000 0x10>;
+                        ti,hwmods = "epwmss0";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        status = "disabled";
+                        ranges = <0x48300100 0x48300100 0x80   /* ECAP */
+                                  0x48300180 0x48300180 0x80   /* EQEP */
+                                  0x48300200 0x48300200 0x80>; /* EHRPWM */
+
+                        ecap0: ecap@48300100 {
+                                compatible = "ti,am33xx-ecap";
+                                #pwm-cells = <3>;
+                                reg = <0x48300100 0x80>;
+                                ti,hwmods = "ecap0";
+                                status = "disabled";
+                        };
+
+                        ehrpwm0: ehrpwm@48300200 {
+                                compatible = "ti,am33xx-ehrpwm";
+                                #pwm-cells = <3>;
+                                reg = <0x48300200 0x80>;
+                                ti,hwmods = "ehrpwm0";
+                                status = "disabled";
+                        };
+                };
+
+                epwmss1: epwmss@48302000 {
+                        compatible = "ti,am33xx-pwmss";
+                        reg = <0x48302000 0x10>;
+                        ti,hwmods = "epwmss1";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        status = "disabled";
+                        ranges = <0x48302100 0x48302100 0x80   /* ECAP */
+                                  0x48302180 0x48302180 0x80   /* EQEP */
+                                  0x48302200 0x48302200 0x80>; /* EHRPWM */
+
+                        ecap1: ecap@48302100 {
+                                compatible = "ti,am33xx-ecap";
+                                #pwm-cells = <3>;
+                                reg = <0x48302100 0x80>;
+                                ti,hwmods = "ecap1";
+                                status = "disabled";
+                        };
+
+                        ehrpwm1: ehrpwm@48302200 {
+                                compatible = "ti,am33xx-ehrpwm";
+                                #pwm-cells = <3>;
+                                reg = <0x48302200 0x80>;
+                                ti,hwmods = "ehrpwm1";
+                                status = "disabled";
+                        };
+                };
+
+                epwmss2: epwmss@48304000 {
+                        compatible = "ti,am33xx-pwmss";
+                        reg = <0x48304000 0x10>;
+                        ti,hwmods = "epwmss2";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        status = "disabled";
+                        ranges = <0x48304100 0x48304100 0x80   /* ECAP */
+                                  0x48304180 0x48304180 0x80   /* EQEP */
+                                  0x48304200 0x48304200 0x80>; /* EHRPWM */
+
+                        ecap2: ecap@48304100 {
+                                compatible = "ti,am33xx-ecap";
+                                #pwm-cells = <3>;
+                                reg = <0x48304100 0x80>;
+                                ti,hwmods = "ecap2";
+                                status = "disabled";
+                        };
+
+                        ehrpwm2: ehrpwm@48304200 {
+                                compatible = "ti,am33xx-ehrpwm";
+                                #pwm-cells = <3>;
+                                reg = <0x48304200 0x80>;
+                                ti,hwmods = "ehrpwm2";
+                                status = "disabled";
+                        };
+                };
+
                 mac: ethernet@4a100000 {
                         compatible = "ti,cpsw";
                         ti,hwmods = "cpgmac0";
@@ -403,6 +494,14 @@
                         ti,hwmods = "wkup_m3";
                 };
 
+                elm: elm@48080000 {
+                        compatible = "ti,am3352-elm";
+                        reg = <0x48080000 0x2000>;
+                        interrupts = <4>;
+                        ti,hwmods = "elm";
+                        status = "disabled";
+                };
+
                 gpmc: gpmc@50000000 {
                         compatible = "ti,am3352-gpmc";
                         ti,hwmods = "gpmc";
diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts
index e9b5bdae4908..e99dfaf70052 100644
--- a/arch/arm/boot/dts/am3517-evm.dts
+++ b/arch/arm/boot/dts/am3517-evm.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
         model = "TI AM3517 EVM (AM3517/05)";
diff --git a/arch/arm/boot/dts/am3517_mt_ventoux.dts b/arch/arm/boot/dts/am3517_mt_ventoux.dts
index 556868388a23..fdf5ce63c8e6 100644
--- a/arch/arm/boot/dts/am3517_mt_ventoux.dts
+++ b/arch/arm/boot/dts/am3517_mt_ventoux.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
         model = "TeeJet Mt.Ventoux";
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
new file mode 100644
index 000000000000..ddc1df77ac52
--- /dev/null
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -0,0 +1,68 @@
+/*
+ * Device Tree Source for AM4372 SoC
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "skeleton.dtsi"
+
+/ {
+        compatible = "ti,am4372", "ti,am43";
+        interrupt-parent = <&gic>;
+
+
+        aliases {
+                serial0 = &uart0;
+        };
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,cortex-a9";
+                };
+        };
+
+        gic: interrupt-controller@48241000 {
+                compatible = "arm,cortex-a9-gic";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = <0x48241000 0x1000>,
+                      <0x48240100 0x0100>;
+        };
+
+        ocp {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                uart0: serial@44e09000 {
+                        compatible = "ti,am4372-uart","ti,omap2-uart";
+                        reg = <0x44e09000 0x2000>;
+                        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+                };
+
+                timer1: timer@44e31000 {
+                        compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
+                        reg = <0x44e31000 0x400>;
+                        interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+                        ti,timer-alwon;
+                };
+
+                timer2: timer@48040000  {
+                        compatible = "ti,am4372-timer","ti,am335x-timer";
+                        reg = <0x48040000  0x400>;
+                        interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+                };
+
+                counter32k: counter@44e86000 {
+                        compatible = "ti,am4372-counter32k","ti,omap-counter32k";
+                        reg = <0x44e86000 0x40>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
new file mode 100644
index 000000000000..74174d48f476
--- /dev/null
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* AM43x EPOS EVM */
+
+/dts-v1/;
+
+#include "am4372.dtsi"
+
+/ {
+        model = "TI AM43x EPOS EVM";
+        compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43";
+};
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index 2353b1f13704..beee1699d49e 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -74,6 +74,7 @@
                                  */
                                 status = "disabled";
                                 /* No CD or WP GPIOs */
+                                broken-cd;
                         };
 
                         usb@50000 {
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 14e36e19d515..45b107763e3b 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -99,6 +99,7 @@
                                  * No CD or WP GPIOs: SDIO interface used for
                                  * Wifi/Bluetooth chip
                                  */
+                                 broken-cd;
                         };
 
                         usb@50000 {
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 130f8390a7e4..a3a2fedb8726 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -64,6 +64,7 @@
                                 pinctrl-names = "default";
                                 status = "okay";
                                 /* No CD or WP GPIOs */
+                                broken-cd;
                         };
 
                         usb@50000 {
@@ -84,6 +85,22 @@
                                         gpios = <&gpio0 6 1>;
                                 };
                         };
+
+                        pcie-controller {
+                                status = "okay";
+
+                                /* Internal mini-PCIe connector */
+                                pcie@1,0 {
+                                        /* Port 0, Lane 0 */
+                                        status = "okay";
+                                };
+
+                                /* Internal mini-PCIe connector */
+                                pcie@2,0 {
+                                        /* Port 1, Lane 0 */
+                                        status = "okay";
+                                };
+                        };
                 };
         };
  };
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 52a1f5efc086..90b117624abb 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -22,9 +22,18 @@
         model = "Marvell Armada 370 and XP SoC";
         compatible = "marvell,armada-370-xp";
 
+        aliases {
+                eth0 = &eth0;
+                eth1 = &eth1;
+        };
+
         cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
                 cpu@0 {
                         compatible = "marvell,sheeva-v7";
+                        device_type = "cpu";
+                        reg = <0>;
                 };
         };
 
@@ -94,7 +103,7 @@
                                 reg = <0x72004 0x4>;
                         };
 
-                        ethernet@70000 {
+                        eth0: ethernet@70000 {
                                 compatible = "marvell,armada-370-neta";
                                 reg = <0x70000 0x4000>;
                                 interrupts = <8>;
@@ -102,7 +111,7 @@
                                 status = "disabled";
                         };
 
-                        ethernet@74000 {
+                        eth1: ethernet@74000 {
                                 compatible = "marvell,armada-370-neta";
                                 reg = <0x74000 0x4000>;
                                 interrupts = <10>;
@@ -143,6 +152,10 @@
                                 reg = <0xd4000 0x200>;
                                 interrupts = <54>;
                                 clocks = <&gateclk 17>;
+                                bus-width = <4>;
+                                cap-sdio-irq;
+                                cap-sd-highspeed;
+                                cap-mmc-highspeed;
                                 status = "disabled";
                         };
 
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index aee2b1866ce2..fa3dfc6b4c6a 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -180,10 +180,6 @@
 
                                 bus-range = <0x00 0xff>;
 
-                                reg = <0x40000 0x2000>, <0x80000 0x2000>;
-
-                                reg-names = "pcie0.0", "pcie1.0";
-
                                 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000   /* Port 0.0 registers */
                                         0x82000000 0 0x80000 0x80000 0 0x00002000   /* Port 1.0 registers */
                                         0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index d6cc8bf8272e..e28e68ff864d 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -30,6 +30,10 @@
         };
 
         soc {
+                ranges = <0          0 0xd0000000 0x100000      /* Internal registers 1MiB */
+                          0xe0000000 0 0xe0000000 0x8100000     /* PCIe */
+                          0xf0000000 0 0xf0000000 0x1000000>;   /* Device Bus, NOR 16MiB   */
+
                 internal-regs {
                         serial@12000 {
                                 clock-frequency = <250000000>;
@@ -97,6 +101,7 @@
                                 pinctrl-names = "default";
                                 status = "okay";
                                 /* No CD or WP GPIOs */
+                                broken-cd;
                         };
 
                         usb@50000 {
@@ -155,6 +160,35 @@
                                         status = "okay";
                                 };
                         };
+
+                        devbus-bootcs@10400 {
+                                status = "okay";
+                                ranges = <0 0xf0000000 0x1000000>;
+
+                                /* Device Bus parameters are required */
+
+                                /* Read parameters */
+                                devbus,bus-width    = <8>;
+                                devbus,turn-off-ps  = <60000>;
+                                devbus,badr-skew-ps = <0>;
+                                devbus,acc-first-ps = <124000>;
+                                devbus,acc-next-ps  = <248000>;
+                                devbus,rd-setup-ps  = <0>;
+                                devbus,rd-hold-ps   = <0>;
+
+                                /* Write parameters */
+                                devbus,sync-enable = <0>;
+                                devbus,wr-high-ps  = <60000>;
+                                devbus,wr-low-ps   = <60000>;
+                                devbus,ale-wr-ps   = <60000>;
+
+                                /* NOR 16 MiB */
+                                nor@0 {
+                                        compatible = "cfi-flash";
+                                        reg = <0 0x1000000>;
+                                        bank-width = <2>;
+                                };
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 76db557adbe7..c87b2de29c30 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -105,6 +105,16 @@
                                 phy-mode = "rgmii-id";
                         };
 
+                        /* Front-side USB slot */
+                        usb@50000 {
+                                status = "okay";
+                        };
+
+                        /* Back-side USB slot */
+                        usb@51000 {
+                                status = "okay";
+                        };
+
                         spi0: spi@10600 {
                                 status = "okay";
 
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 488ca5eb9a55..c7b1f4d5c1c7 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -23,6 +23,7 @@
                 gpio0 = &gpio0;
                 gpio1 = &gpio1;
                 gpio2 = &gpio2;
+                eth3 = &eth3;
         };
 
 
@@ -105,7 +106,7 @@
                                 interrupts = <91>;
                         };
 
-                        ethernet@34000 {
+                        eth3: ethernet@34000 {
                                 compatible = "marvell,armada-370-neta";
                                 reg = <0x34000 0x4000>;
                                 interrupts = <14>;
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index fdea75c73411..8f510458ea86 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -138,13 +138,22 @@
                                 nr-ports = <2>;
                                 status = "okay";
                         };
+
+                        /* Front side USB 0 */
                         usb@50000 {
                                 status = "okay";
                         };
+
+                        /* Front side USB 1 */
                         usb@51000 {
                                 status = "okay";
                         };
 
+                        /* USB interface in the mini-PCIe connector */
+                        usb@52000 {
+                                status = "okay";
+                        };
+
                         devbus-bootcs@10400 {
                                 status = "okay";
                                 ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 1ee8540b0eba..416eb9481844 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -22,6 +22,10 @@
         model = "Marvell Armada XP family SoC";
         compatible = "marvell,armadaxp", "marvell,armada-370-xp";
 
+        aliases {
+                eth2 = &eth2;
+        };
+
         soc {
                 internal-regs {
                         L2: l2-cache {
@@ -86,7 +90,7 @@
                                 reg = <0x18200 0x500>;
                         };
 
-                        ethernet@30000 {
+                        eth2: ethernet@30000 {
                                 compatible = "marvell,armada-370-neta";
                                 reg = <0x30000 0x4000>;
                                 interrupts = <12>;
diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts
index 5ede7678f298..cce45f5177f9 100644
--- a/arch/arm/boot/dts/at91-ariag25.dts
+++ b/arch/arm/boot/dts/at91-ariag25.dts
@@ -21,6 +21,7 @@
                 serial3 = &usart2;
                 serial4 = &usart3;
                 serial5 = &uart0;
+                serial6 = &uart1;
         };
 
         chosen {
@@ -112,13 +113,17 @@
                                 status = "okay";
                         };
 
+                        /*
+                         * UART0/1 pins are marked as GPIO on
+                         * Aria documentation.
+                         * Change to "okay" if you need additional serial ports
+                         */
                         uart0: serial@f8040000 {
-                                compatible = "atmel,at91sam9260-usart";
-                                reg = <0xf8040000 0x200>;
-                                interrupts = <15 4 5>;
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_uart0>;
-                                status = "okay";
+                                status = "disabled";
+                        };
+
+                        uart1: serial@f8044000 {
+                                status = "disabled";
                         };
 
                         adc0: adc@f804c000 {
@@ -138,6 +143,10 @@
                                         };
                                 };
                         };
+
+                        rtc@fffffeb0 {
+                                status = "okay";
+                        };
                 };
 
                 usb0: ohci@00600000 {
diff --git a/arch/arm/boot/dts/at91-foxg20.dts b/arch/arm/boot/dts/at91-foxg20.dts
new file mode 100644
index 000000000000..cbe967343997
--- /dev/null
+++ b/arch/arm/boot/dts/at91-foxg20.dts
@@ -0,0 +1,157 @@
+/*
+ * at91-foxg20.dts - Device Tree file for Acme Systems FoxG20 board
+ *
+ * Based on DT files for at91sam9g20ek evaluation board (AT91SAM9G20 SoC)
+ *
+ * Copyright (C) 2013 Douglas Gilbert <dgilbert@interlog.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+#include "at91sam9g20.dtsi"
+
+/ {
+        model = "Acme Systems FoxG20";
+        compatible = "acme,foxg20", "atmel,at91sam9g20", "atmel,at91sam9";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait";
+        };
+
+        memory {
+                reg = <0x20000000 0x4000000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <18432000>;
+                };
+        };
+
+        ahb {
+                apb {
+                        usb1: gadget@fffa4000 {
+                                atmel,vbus-gpio = <&pioC 6 GPIO_ACTIVE_HIGH>;
+                                status = "okay";
+                        };
+
+                        mmc0: mmc@fffa8000 {
+                                pinctrl-0 = <
+                                        &pinctrl_mmc0_clk
+                                        &pinctrl_mmc0_slot1_cmd_dat0
+                                        &pinctrl_mmc0_slot1_dat1_3>;
+                                status = "okay";
+
+                                slot@1 {
+                                        reg = <1>;
+                                        bus-width = <4>;
+                                };
+                        };
+
+                        usart0: serial@fffb0000 {
+                                pinctrl-0 =
+                                        <&pinctrl_usart0
+                                         &pinctrl_usart0_rts
+                                         &pinctrl_usart0_cts
+                                        >;
+                                status = "okay";
+                        };
+
+                        usart1: serial@fffb4000 {
+                                status = "okay";
+                        };
+
+                        usart2: serial@fffb8000 {
+                                status = "okay";
+                        };
+
+                        macb0: ethernet@fffc4000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+
+                        usart3: serial@fffd0000 {
+                                status = "okay";
+                        };
+
+                        uart0: serial@fffd4000 {
+                                status = "okay";
+                        };
+
+                        uart1: serial@fffd8000 {
+                                status = "okay";
+                        };
+
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+
+                        pinctrl@fffff400 {
+                                board {
+                                        pinctrl_pck0_as_mck: pck0_as_mck {
+                                                atmel,pins =
+                                                        <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                };
+
+                                mmc0_slot1 {
+                                        pinctrl_board_mmc0_slot1: mmc0_slot1-board {
+                                                atmel,pins =
+                                                        <AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;   /* CD pin */
+                                        };
+                                };
+
+                                i2c0 {
+                                        pinctrl_i2c0: i2c0-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE    /* TWD (SDA), open drain */
+                                                         AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE>;  /* TWCK (SCL), open drain */
+                                        };
+                                };
+                        };
+
+                        watchdog@fffffd40 {
+                                status = "okay";
+                        };
+                };
+
+                usb0: ohci@00500000 {
+                        num-ports = <2>;
+                        status = "okay";
+                };
+        };
+
+        i2c@0 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_i2c0>;
+                i2c-gpio,delay-us = <5>;        /* ~85 kHz */
+                status = "okay";
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                /* red LED marked "PC7" near mini USB (device) receptacle */
+                user_led {
+                        label = "user_led";
+                        gpios = <&pioC 7 GPIO_ACTIVE_HIGH>;     /* PC7 */
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+
+                btn {
+                        label = "Button";
+                        gpios = <&pioC 4 GPIO_ACTIVE_LOW>;
+                        linux,code = <0x103>;
+                        gpio-key,wakeup;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 4aad0d9f5462..92b9e21389db 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -38,8 +38,12 @@
                 ssc2 = &ssc2;
         };
         cpus {
-                cpu@0 {
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
                         compatible = "arm,arm920t";
+                        device_type = "cpu";
                 };
         };
 
@@ -398,6 +402,91 @@
                                         };
                                 };
 
+                                tcb0 {
+                                        pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+                                                atmel,pins = <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+                                                atmel,pins = <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+                                                atmel,pins = <AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+                                                atmel,pins = <AT91_PIOA 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+                                                atmel,pins = <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+                                                atmel,pins = <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+                                                atmel,pins = <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+                                                atmel,pins = <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+                                                atmel,pins = <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                };
+
+                                tcb1 {
+                                        pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+                                                atmel,pins = <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+                                                atmel,pins = <AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+                                                atmel,pins = <AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+                                                atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+                                                atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+                                                atmel,pins = <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+                                                atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+                                                atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+                                                atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                };
+
+                                spi0 {
+                                        pinctrl_spi0: spi0-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA0 periph A SPI0_MISO pin */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA1 periph A SPI0_MOSI pin */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA2 periph A SPI0_SPCK pin */
+                                        };
+                                };
+
                                 pioA: gpio@fffff400 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffff400 0x200>;
@@ -498,6 +587,17 @@
                                 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>;
                                 status = "disabled";
                         };
+
+                        spi0: spi@fffe0000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91rm9200-spi";
+                                reg = <0xfffe0000 0x200>;
+                                interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_spi0>;
+                                status = "disabled";
+                        };
                 };
 
                 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts
index 14058125d123..d2d72c3b44c4 100644
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -53,6 +53,16 @@
                                 atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>;
                                 status = "okay";
                         };
+
+                        spi0: spi@fffe0000 {
+                                status = "okay";
+                                cs-gpios = <&pioA 3 0>, <0>, <0>, <0>;
+                                mtd_dataflash@0 {
+                                        compatible = "atmel,at45", "atmel,dataflash";
+                                        spi-max-frequency = <15000000>;
+                                        reg = <0>;
+                                };
+                        };
                 };
 
                 usb0: ohci@00300000 {
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 44851b977069..c7ccbcbffb3e 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -35,8 +35,12 @@
                 ssc0 = &ssc0;
         };
         cpus {
-                cpu@0 {
-                        compatible = "arm,arm926ejs";
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                 };
         };
 
@@ -347,6 +351,90 @@
                                         };
                                 };
 
+                                i2c_gpio0 {
+                                        pinctrl_i2c_gpio0: i2c_gpio0-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 23 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE
+                                                         AT91_PIOA 24 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
+                                        };
+                                };
+
+                                tcb0 {
+                                        pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+                                                atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+                                                atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+                                                atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+                                                atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+                                                atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+                                                atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+                                                atmel,pins = <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+                                                atmel,pins = <AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+                                                atmel,pins = <AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                };
+
+                                tcb1 {
+                                        pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+                                                atmel,pins = <AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+                                                atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+                                                atmel,pins = <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+                                                atmel,pins = <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+                                                atmel,pins = <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+                                                atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+                                                atmel,pins = <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+                                                atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+                                                atmel,pins = <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                };
+
                                 pioA: gpio@fffff400 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffff400 0x200>;
@@ -599,6 +687,8 @@
                 i2c-gpio,delay-us = <2>;        /* ~100 kHz */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_i2c_gpio0>;
                 status = "disabled";
         };
 };
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index d9cf51a01b60..d5bd65f74602 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -32,8 +32,12 @@
                 ssc1 = &ssc1;
         };
         cpus {
-                cpu@0 {
-                        compatible = "arm,arm926ejs";
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                 };
         };
 
@@ -324,6 +328,44 @@
                                         };
                                 };
 
+                                tcb0 {
+                                        pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+                                                atmel,pins = <AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+                                                atmel,pins = <AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+                                                atmel,pins = <AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+                                                atmel,pins = <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+                                                atmel,pins = <AT91_PIOE 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+                                                atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+                                                atmel,pins = <AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+                                                atmel,pins = <AT91_PIOE 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+                                                atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                };
+
                                 pioA: gpio@fffff200 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffff200 0x200>;
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index eff1afb81304..70f835b55c0b 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -89,6 +89,10 @@
                                         reg = <0>;
                                 };
                         };
+
+                        watchdog@fffffd40 {
+                                status = "okay";
+                        };
                 };
 
                 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index c7ffc32918f9..137354689ad0 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -104,6 +104,10 @@
                                         reg = <1>;
                                 };
                         };
+
+                        watchdog@fffffd40 {
+                                status = "okay";
+                        };
                 };
 
                 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index f0091af6c285..c3e514837074 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -10,6 +10,7 @@
  */
 
 #include "skeleton.dtsi"
+#include <dt-bindings/dma/at91.h>
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
@@ -38,8 +39,12 @@
                 ssc1 = &ssc1;
         };
         cpus {
-                cpu@0 {
-                        compatible = "arm,arm926ejs";
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                 };
         };
 
@@ -344,6 +349,82 @@
                                         };
                                 };
 
+                                tcb0 {
+                                        pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+                                                atmel,pins = <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+                                                atmel,pins = <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+                                                atmel,pins = <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+                                                atmel,pins = <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+                                                atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+                                                atmel,pins = <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+                                                atmel,pins = <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+                                                atmel,pins = <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+                                                atmel,pins = <AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                };
+
+                                tcb1 {
+                                        pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+                                                atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+                                                atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+                                                atmel,pins = <AT91_PIOD 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+                                                atmel,pins = <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+                                                atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+                                                atmel,pins = <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+                                                atmel,pins = <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+                                                atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+                                                atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                };
+
                                 pioA: gpio@fffff200 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffff200 0x200>;
@@ -537,7 +618,7 @@
                                 compatible = "atmel,hsmci";
                                 reg = <0xfff80000 0x600>;
                                 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
-                                dmas = <&dma 1 0>;
+                                dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
                                 dma-names = "rxtx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -548,7 +629,7 @@
                                 compatible = "atmel,hsmci";
                                 reg = <0xfffd0000 0x600>;
                                 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
-                                dmas = <&dma 1 13>;
+                                dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>;
                                 dma-names = "rxtx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -582,6 +663,68 @@
                                 pinctrl-0 = <&pinctrl_spi1>;
                                 status = "disabled";
                         };
+
+                        usb2: gadget@fff78000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91sam9rl-udc";
+                                reg = <0x00600000 0x80000
+                                       0xfff78000 0x400>;
+                                interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
+                                status = "disabled";
+
+                                ep0 {
+                                        reg = <0>;
+                                        atmel,fifo-size = <64>;
+                                        atmel,nb-banks = <1>;
+                                };
+
+                                ep1 {
+                                        reg = <1>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <2>;
+                                        atmel,can-dma;
+                                        atmel,can-isoc;
+                                };
+
+                                ep2 {
+                                        reg = <2>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <2>;
+                                        atmel,can-dma;
+                                        atmel,can-isoc;
+                                };
+
+                                ep3 {
+                                        reg = <3>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <3>;
+                                        atmel,can-dma;
+                                };
+
+                                ep4 {
+                                        reg = <4>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <3>;
+                                        atmel,can-dma;
+                                };
+
+                                ep5 {
+                                        reg = <5>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <3>;
+                                        atmel,can-dma;
+                                        atmel,can-isoc;
+                                };
+
+                                ep6 {
+                                        reg = <6>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <3>;
+                                        atmel,can-dma;
+                                        atmel,can-isoc;
+                                };
+                        };
                 };
 
                 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 89c50d108d44..a4b00e5c61c0 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -59,6 +59,10 @@
                                 status = "okay";
                         };
 
+                        watchdog@fffffd40 {
+                                status = "okay";
+                        };
+
                         mmc0: mmc@fff80000 {
                                 pinctrl-0 = <
                                         &pinctrl_board_mmc0
@@ -112,6 +116,11 @@
                                         reg = <0>;
                                 };
                         };
+
+                        usb2: gadget@fff78000 {
+                                atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>;
+                                status = "okay";
+                        };
                 };
 
                 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index d864f7a9d2e0..bb7f564b3a55 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -8,6 +8,7 @@
  */
 
 #include "skeleton.dtsi"
+#include <dt-bindings/dma/at91.h>
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
@@ -34,8 +35,12 @@
                 ssc0 = &ssc0;
         };
         cpus {
-                cpu@0 {
-                        compatible = "arm,arm926ejs";
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                 };
         };
 
@@ -93,7 +98,7 @@
                                 compatible = "atmel,hsmci";
                                 reg = <0xf0008000 0x600>;
                                 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
-                                dmas = <&dma 1 0>;
+                                dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
                                 dma-names = "rxtx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -286,6 +291,82 @@
                                         };
                                 };
 
+                                tcb0 {
+                                        pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+                                                atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+                                                atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+                                                atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+                                                atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+                                                atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+                                                atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+                                                atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+                                                atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+                                                atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                };
+
+                                tcb1 {
+                                        pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+                                                atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+                                                atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+                                                atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+                                                atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+                                                atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+                                                atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+                                                atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+                                                atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+                                                atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+                                };
+
                                 pioA: gpio@fffff400 {
                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                         reg = <0xfffff400 0x200>;
@@ -385,8 +466,8 @@
                                 compatible = "atmel,at91sam9x5-i2c";
                                 reg = <0xf8010000 0x100>;
                                 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
-                                dmas = <&dma 1 13>,
-                                       <&dma 1 14>;
+                                dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>,
+                                       <&dma 1 AT91_DMA_CFG_PER_ID(14)>;
                                 dma-names = "tx", "rx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -397,8 +478,8 @@
                                 compatible = "atmel,at91sam9x5-i2c";
                                 reg = <0xf8014000 0x100>;
                                 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
-                                dmas = <&dma 1 15>,
-                                       <&dma 1 16>;
+                                dmas = <&dma 1 AT91_DMA_CFG_PER_ID(15)>,
+                                       <&dma 1 AT91_DMA_CFG_PER_ID(16)>;
                                 dma-names = "tx", "rx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -411,6 +492,9 @@
                                 compatible = "atmel,at91rm9200-spi";
                                 reg = <0xf0000000 0x100>;
                                 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
+                                dmas = <&dma 1 AT91_DMA_CFG_PER_ID(1)>,
+                                       <&dma 1 AT91_DMA_CFG_PER_ID(2)>;
+                                dma-names = "tx", "rx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_spi0>;
                                 status = "disabled";
@@ -422,10 +506,19 @@
                                 compatible = "atmel,at91rm9200-spi";
                                 reg = <0xf0004000 0x100>;
                                 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
+                                dmas = <&dma 1 AT91_DMA_CFG_PER_ID(3)>,
+                                       <&dma 1 AT91_DMA_CFG_PER_ID(4)>;
+                                dma-names = "tx", "rx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_spi1>;
                                 status = "disabled";
                         };
+
+                        watchdog@fffffe40 {
+                                compatible = "atmel,at91sam9260-wdt";
+                                reg = <0xfffffe40 0x10>;
+                                status = "disabled";
+                        };
                 };
 
                 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index 2e67cd5e47eb..d59b70c6a6a0 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -77,6 +77,10 @@
                                         reg = <0>;
                                 };
                         };
+
+                        watchdog@fffffe40 {
+                                status = "okay";
+                        };
                 };
 
                 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index af91599488e9..57d45f5bea09 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -10,6 +10,7 @@
  */
 
 #include "skeleton.dtsi"
+#include <dt-bindings/dma/at91.h>
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
@@ -36,8 +37,12 @@
                 ssc0 = &ssc0;
         };
         cpus {
-                cpu@0 {
-                        compatible = "arm,arm926ejs";
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                 };
         };
 
@@ -414,6 +419,82 @@
                                         };
                                 };
 
+                                tcb0 {
+                                        pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+                                                atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+                                                atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+                                                atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+                                                atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+                                                atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+                                                atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+                                                atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+                                                atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+                                                atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                };
+
+                                tcb1 {
+                                        pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+                                                atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+                                                atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+                                                atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+                                                atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+                                                atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+                                                atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+                                                atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+                                                atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+                                                atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+                                };
+
                                 pioA: gpio@fffff400 {
                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                         reg = <0xfffff400 0x200>;
@@ -470,7 +551,7 @@
                                 compatible = "atmel,hsmci";
                                 reg = <0xf0008000 0x600>;
                                 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
-                                dmas = <&dma0 1 0>;
+                                dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>;
                                 dma-names = "rxtx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -481,7 +562,7 @@
                                 compatible = "atmel,hsmci";
                                 reg = <0xf000c000 0x600>;
                                 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
-                                dmas = <&dma1 1 0>;
+                                dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>;
                                 dma-names = "rxtx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -544,8 +625,8 @@
                                 compatible = "atmel,at91sam9x5-i2c";
                                 reg = <0xf8010000 0x100>;
                                 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
-                                dmas = <&dma0 1 7>,
-                                       <&dma0 1 8>;
+                                dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(7)>,
+                                       <&dma0 1 AT91_DMA_CFG_PER_ID(8)>;
                                 dma-names = "tx", "rx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -558,8 +639,8 @@
                                 compatible = "atmel,at91sam9x5-i2c";
                                 reg = <0xf8014000 0x100>;
                                 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
-                                dmas = <&dma1 1 5>,
-                                       <&dma1 1 6>;
+                                dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(5)>,
+                                       <&dma1 1 AT91_DMA_CFG_PER_ID(6)>;
                                 dma-names = "tx", "rx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -572,8 +653,8 @@
                                 compatible = "atmel,at91sam9x5-i2c";
                                 reg = <0xf8018000 0x100>;
                                 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
-                                dmas = <&dma0 1 9>,
-                                       <&dma0 1 10>;
+                                dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(9)>,
+                                       <&dma0 1 AT91_DMA_CFG_PER_ID(10)>;
                                 dma-names = "tx", "rx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -582,6 +663,24 @@
                                 status = "disabled";
                         };
 
+                        uart0: serial@f8040000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf8040000 0x200>;
+                                interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart0>;
+                                status = "disabled";
+                        };
+
+                        uart1: serial@f8044000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf8044000 0x200>;
+                                interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart1>;
+                                status = "disabled";
+                        };
+
                         adc0: adc@f804c000 {
                                 compatible = "atmel,at91sam9260-adc";
                                 reg = <0xf804c000 0x100>;
@@ -629,6 +728,9 @@
                                 compatible = "atmel,at91rm9200-spi";
                                 reg = <0xf0000000 0x100>;
                                 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
+                                dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(1)>,
+                                       <&dma0 1 AT91_DMA_CFG_PER_ID(2)>;
+                                dma-names = "tx", "rx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_spi0>;
                                 status = "disabled";
@@ -640,13 +742,84 @@
                                 compatible = "atmel,at91rm9200-spi";
                                 reg = <0xf0004000 0x100>;
                                 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
+                                dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(1)>,
+                                       <&dma1 1 AT91_DMA_CFG_PER_ID(2)>;
+                                dma-names = "tx", "rx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_spi1>;
                                 status = "disabled";
                         };
 
+                        usb2: gadget@f803c000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91sam9rl-udc";
+                                reg = <0x00500000 0x80000
+                                       0xf803c000 0x400>;
+                                interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
+                                status = "disabled";
+
+                                ep0 {
+                                        reg = <0>;
+                                        atmel,fifo-size = <64>;
+                                        atmel,nb-banks = <1>;
+                                };
+
+                                ep1 {
+                                        reg = <1>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <2>;
+                                        atmel,can-dma;
+                                        atmel,can-isoc;
+                                };
+
+                                ep2 {
+                                        reg = <2>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <2>;
+                                        atmel,can-dma;
+                                        atmel,can-isoc;
+                                };
+
+                                ep3 {
+                                        reg = <3>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <3>;
+                                        atmel,can-dma;
+                                };
+
+                                ep4 {
+                                        reg = <4>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <3>;
+                                        atmel,can-dma;
+                                };
+
+                                ep5 {
+                                        reg = <5>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <3>;
+                                        atmel,can-dma;
+                                        atmel,can-isoc;
+                                };
+
+                                ep6 {
+                                        reg = <6>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <3>;
+                                        atmel,can-dma;
+                                        atmel,can-isoc;
+                                };
+                        };
+
+                        watchdog@fffffe40 {
+                                compatible = "atmel,at91sam9260-wdt";
+                                reg = <0xfffffe40 0x10>;
+                                status = "disabled";
+                        };
+
                         rtc@fffffeb0 {
-                                compatible = "atmel,at91rm9200-rtc";
+                                compatible = "atmel,at91sam9x5-rtc";
                                 reg = <0xfffffeb0 0x40>;
                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                 status = "disabled";
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
index 19c8ebb303f4..b753855b2058 100644
--- a/arch/arm/boot/dts/at91sam9x5ek.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -52,6 +52,11 @@
                                 status = "okay";
                         };
 
+                        usb2: gadget@f803c000 {
+                                atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>;
+                                status = "okay";
+                        };
+
                         i2c0: i2c@f8010000 {
                                 status = "okay";
                         };
@@ -81,6 +86,10 @@
                                         reg = <0>;
                                 };
                         };
+
+                        watchdog@fffffe40 {
+                                status = "okay";
+                        };
                 };
 
                 usb0: ohci@00600000 {
diff --git a/arch/arm/boot/dts/bcm11351-brt.dts b/arch/arm/boot/dts/bcm11351-brt.dts
index 248067cf7069..67ec524098b5 100644
--- a/arch/arm/boot/dts/bcm11351-brt.dts
+++ b/arch/arm/boot/dts/bcm11351-brt.dts
@@ -13,7 +13,7 @@
 
 /dts-v1/;
 
-/include/ "bcm11351.dtsi"
+#include "bcm11351.dtsi"
 
 / {
         model = "BCM11351 BRT board";
@@ -27,4 +27,21 @@
                 status = "okay";
         };
 
+        sdio0: sdio@0x3f180000 {
+                max-frequency = <48000000>;
+                status = "okay";
+        };
+
+        sdio1: sdio@0x3f190000 {
+                non-removable;
+                max-frequency = <48000000>;
+                status = "okay";
+        };
+
+        sdio3: sdio@0x3f1b0000 {
+                max-frequency = <48000000>;
+                status = "okay";
+        };
+
+
 };
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index 41b2c6c33f09..17979d5f23b4 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -11,7 +11,10 @@
  * GNU General Public License for more details.
  */
 
-/include/ "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "skeleton.dtsi"
 
 / {
         model = "BCM11351 SoC";
@@ -33,7 +36,7 @@
 
         smc@0x3404c000 {
                 compatible = "bcm,bcm11351-smc", "bcm,kona-smc";
-                reg = <0x3404c000 0x400>; //1 KiB in SRAM
+                reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */
         };
 
         uart@3e000000 {
@@ -41,7 +44,7 @@
                 status = "disabled";
                 reg = <0x3e000000 0x1000>;
                 clock-frequency = <13000000>;
-                interrupts = <0x0 67 0x4>;
+                interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
                 reg-shift = <2>;
                 reg-io-width = <4>;
         };
@@ -56,8 +59,36 @@
         timer@35006000 {
                 compatible = "bcm,kona-timer";
                 reg = <0x35006000 0x1000>;
-                interrupts = <0x0 7 0x4>;
+                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
                 clock-frequency = <32768>;
         };
 
+        sdio0: sdio@0x3f180000 {
+                compatible = "bcm,kona-sdhci";
+                reg = <0x3f180000 0x10000>;
+                interrupts = <0x0 77 0x4>;
+                status = "disabled";
+        };
+
+        sdio1: sdio@0x3f190000 {
+                compatible = "bcm,kona-sdhci";
+                reg = <0x3f190000 0x10000>;
+                interrupts = <0x0 76 0x4>;
+                status = "disabled";
+        };
+
+        sdio2: sdio@0x3f1a0000 {
+                compatible = "bcm,kona-sdhci";
+                reg = <0x3f1a0000 0x10000>;
+                interrupts = <0x0 74 0x4>;
+                status = "disabled";
+        };
+
+        sdio3: sdio@0x3f1b0000 {
+                compatible = "bcm,kona-sdhci";
+                reg = <0x3f1b0000 0x10000>;
+                interrupts = <0x0 73 0x4>;
+                status = "disabled";
+        };
+
 };
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
index aafda174a605..6e9deb786a7d 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -8,6 +8,17 @@
         memory {
                 reg = <0 0x10000000>;
         };
+
+        leds {
+                compatible = "gpio-leds";
+
+                act {
+                        label = "ACT";
+                        gpios = <&gpio 16 1>;
+                        default-state = "keep";
+                        linux,default-trigger = "heartbeat";
+                };
+        };
 };
 
 &gpio {
diff --git a/arch/arm/boot/dts/ccu8540.dts b/arch/arm/boot/dts/ccu8540.dts
new file mode 100644
index 000000000000..48ff03441f5a
--- /dev/null
+++ b/arch/arm/boot/dts/ccu8540.dts
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2013 ST-Ericsson AB
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "dbx5x0.dtsi"
+
+/ {
+        model = "ST-Ericsson U8540 platform with Device Tree";
+        compatible = "st-ericsson,ccu8540", "st-ericsson,u8540";
+
+        memory@0 {
+                reg = <0x20000000 0x1f000000>, <0xc0000000 0x3f000000>;
+        };
+
+        soc {
+                prcmu@80157000 {
+                        reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x3000>;
+                        reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
+                };
+
+                uart@80120000 {
+                        status = "okay";
+                };
+
+                uart@80121000 {
+                        status = "okay";
+                };
+
+                uart@80007000 {
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/ccu9540.dts b/arch/arm/boot/dts/ccu9540.dts
index 04305463f00d..ed29ec7288e4 100644
--- a/arch/arm/boot/dts/ccu9540.dts
+++ b/arch/arm/boot/dts/ccu9540.dts
@@ -10,7 +10,7 @@
  */
 
 /dts-v1/;
-/include/ "dbx5x0.dtsi"
+#include "dbx5x0.dtsi"
 
 / {
         model = "ST-Ericsson CCU9540 platform with Device Tree";
@@ -20,7 +20,7 @@
                 reg = <0x00000000 0x20000000>;
         };
 
-        soc-u9500 {
+        soc {
                 uart@80120000 {
                         status = "okay";
                 };
@@ -52,7 +52,7 @@
                 // WLAN SDIO channel
                 sdi1_per2@80118000 {
                         arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                         bus-width = <4>;
 
                         status = "okay";
diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index b6bc4ff17f26..a082f0ba1ddb 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -9,10 +9,11 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-/include/ "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "skeleton.dtsi"
 
 / {
-        soc-u9500 {
+        soc {
                 #address-cells = <1>;
                 #size-cells = <1>;
                 compatible = "stericsson,db8500";
@@ -31,33 +32,33 @@
                 L2: l2-cache {
                         compatible = "arm,pl310-cache";
                         reg = <0xa0412000 0x1000>;
-                        interrupts = <0 13 4>;
+                        interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
                         cache-unified;
                         cache-level = <2>;
                 };
 
                 pmu {
                         compatible = "arm,cortex-a9-pmu";
-                        interrupts = <0 7 0x4>;
+                        interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
                 };
 
                 timer@a0410600 {
                         compatible = "arm,cortex-a9-twd-timer";
                         reg = <0xa0410600 0x20>;
-                        interrupts = <1 13 0x304>;
+                        interrupts = <1 13 0x304>; /* IRQ level high per-CPU */
                 };
 
                 rtc@80154000 {
                         compatible = "arm,rtc-pl031", "arm,primecell";
                         reg = <0x80154000 0x1000>;
-                        interrupts = <0 18 0x4>;
+                        interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
                 };
 
                 gpio0: gpio@8012e000 {
                         compatible = "stericsson,db8500-gpio",
                                 "st,nomadik-gpio";
                         reg =  <0x8012e000 0x80>;
-                        interrupts = <0 119 0x4>;
+                        interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
                         st,supports-sleepmode;
@@ -70,7 +71,7 @@
                         compatible = "stericsson,db8500-gpio",
                                 "st,nomadik-gpio";
                         reg =  <0x8012e080 0x80>;
-                        interrupts = <0 120 0x4>;
+                        interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
                         st,supports-sleepmode;
@@ -83,7 +84,7 @@
                         compatible = "stericsson,db8500-gpio",
                                 "st,nomadik-gpio";
                         reg =  <0x8000e000 0x80>;
-                        interrupts = <0 121 0x4>;
+                        interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
                         st,supports-sleepmode;
@@ -96,7 +97,7 @@
                         compatible = "stericsson,db8500-gpio",
                                 "st,nomadik-gpio";
                         reg =  <0x8000e080 0x80>;
-                        interrupts = <0 122 0x4>;
+                        interrupts = <0 122 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
                         st,supports-sleepmode;
@@ -109,7 +110,7 @@
                         compatible = "stericsson,db8500-gpio",
                                 "st,nomadik-gpio";
                         reg =  <0x8000e100 0x80>;
-                        interrupts = <0 123 0x4>;
+                        interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
                         st,supports-sleepmode;
@@ -122,7 +123,7 @@
                         compatible = "stericsson,db8500-gpio",
                                 "st,nomadik-gpio";
                         reg =  <0x8000e180 0x80>;
-                        interrupts = <0 124 0x4>;
+                        interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
                         st,supports-sleepmode;
@@ -135,7 +136,7 @@
                         compatible = "stericsson,db8500-gpio",
                                 "st,nomadik-gpio";
                         reg =  <0x8011e000 0x80>;
-                        interrupts = <0 125 0x4>;
+                        interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
                         st,supports-sleepmode;
@@ -148,7 +149,7 @@
                         compatible = "stericsson,db8500-gpio",
                                 "st,nomadik-gpio";
                         reg =  <0x8011e080 0x80>;
-                        interrupts = <0 126 0x4>;
+                        interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
                         st,supports-sleepmode;
@@ -161,7 +162,7 @@
                         compatible = "stericsson,db8500-gpio",
                                 "st,nomadik-gpio";
                         reg =  <0xa03fe000 0x80>;
-                        interrupts = <0 127 0x4>;
+                        interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
                         st,supports-sleepmode;
@@ -171,29 +172,61 @@
                 };
 
                 pinctrl {
-                        compatible = "stericsson,nmk-pinctrl";
+                        compatible = "stericsson,db8500-pinctrl";
                         prcm = <&prcmu>;
                 };
 
-                usb@a03e0000 {
+                usb_per5@a03e0000 {
                         compatible = "stericsson,db8500-musb",
                                 "mentor,musb";
                         reg = <0xa03e0000 0x10000>;
-                        interrupts = <0 23 0x4>;
-                };
-
-                dma-controller@801C0000 {
-                        compatible = "stericsson,db8500-dma40",
-                                        "stericsson,dma40";
+                        interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "mc";
+
+                        dr_mode = "otg";
+
+                        dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
+                               <&dma 38 0 0x0>, /* Logical - MemToDev */
+                               <&dma 37 0 0x2>, /* Logical - DevToMem */
+                               <&dma 37 0 0x0>, /* Logical - MemToDev */
+                               <&dma 36 0 0x2>, /* Logical - DevToMem */
+                               <&dma 36 0 0x0>, /* Logical - MemToDev */
+                               <&dma 19 0 0x2>, /* Logical - DevToMem */
+                               <&dma 19 0 0x0>, /* Logical - MemToDev */
+                               <&dma 18 0 0x2>, /* Logical - DevToMem */
+                               <&dma 18 0 0x0>, /* Logical - MemToDev */
+                               <&dma 17 0 0x2>, /* Logical - DevToMem */
+                               <&dma 17 0 0x0>, /* Logical - MemToDev */
+                               <&dma 16 0 0x2>, /* Logical - DevToMem */
+                               <&dma 16 0 0x0>, /* Logical - MemToDev */
+                               <&dma 39 0 0x2>, /* Logical - DevToMem */
+                               <&dma 39 0 0x0>; /* Logical - MemToDev */
+
+                        dma-names = "iep_1_9",  "oep_1_9",
+                                    "iep_2_10", "oep_2_10",
+                                    "iep_3_11", "oep_3_11",
+                                    "iep_4_12", "oep_4_12",
+                                    "iep_5_13", "oep_5_13",
+                                    "iep_6_14", "oep_6_14",
+                                    "iep_7_15", "oep_7_15",
+                                    "iep_8",    "oep_8";
+                };
+
+                dma: dma-controller@801C0000 {
+                        compatible = "stericsson,db8500-dma40", "stericsson,dma40";
                         reg = <0x801C0000 0x1000 0x40010000 0x800>;
-                        interrupts = <0 25 0x4>;
+                        reg-names = "base", "lcpa";
+                        interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
+
+                        #dma-cells = <3>;
+                        memcpy-channels = <56 57 58 59 60>;
                 };
 
                 prcmu: prcmu@80157000 {
                         compatible = "stericsson,db8500-prcmu";
                         reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
                         reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
-                        interrupts = <0 47 0x4>;
+                        interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <1>;
                         interrupt-controller;
@@ -208,7 +241,8 @@
                         thermal@801573c0 {
                                 compatible = "stericsson,db8500-thermal";
                                 reg = <0x801573c0 0x40>;
-                                interrupts = <21 0x4>, <22 0x4>;
+                                interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
+                                             <22 IRQ_TYPE_LEVEL_HIGH>;
                                 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
                                 status = "disabled";
                          };
@@ -322,21 +356,21 @@
                         ab8500 {
                                 compatible = "stericsson,ab8500";
                                 interrupt-parent = <&intc>;
-                                interrupts = <0 40 0x4>;
+                                interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
                                 interrupt-controller;
                                 #interrupt-cells = <2>;
 
                                 ab8500-rtc {
                                         compatible = "stericsson,ab8500-rtc";
-                                        interrupts = <17 0x4
-                                                      18 0x4>;
+                                        interrupts = <17 IRQ_TYPE_LEVEL_HIGH
+                                                      18 IRQ_TYPE_LEVEL_HIGH>;
                                         interrupt-names = "60S", "ALARM";
                                 };
 
                                 ab8500-gpadc {
                                         compatible = "stericsson,ab8500-gpadc";
-                                        interrupts = <32 0x4
-                                                      39 0x4>;
+                                        interrupts = <32 IRQ_TYPE_LEVEL_HIGH
+                                                      39 IRQ_TYPE_LEVEL_HIGH>;
                                         interrupt-names = "HW_CONV_END", "SW_CONV_END";
                                         vddadc-supply = <&ab8500_ldo_tvout_reg>;
                                 };
@@ -369,13 +403,13 @@
 
                                 ab8500_usb {
                                         compatible = "stericsson,ab8500-usb";
-                                        interrupts = < 90 0x4
-                                                       96 0x4
-                                                       14 0x4
-                                                       15 0x4
-                                                       79 0x4
-                                                       74 0x4
-                                                       75 0x4>;
+                                        interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
+                                                       96 IRQ_TYPE_LEVEL_HIGH
+                                                       14 IRQ_TYPE_LEVEL_HIGH
+                                                       15 IRQ_TYPE_LEVEL_HIGH
+                                                       79 IRQ_TYPE_LEVEL_HIGH
+                                                       74 IRQ_TYPE_LEVEL_HIGH
+                                                       75 IRQ_TYPE_LEVEL_HIGH>;
                                         interrupt-names = "ID_WAKEUP_R",
                                                           "ID_WAKEUP_F",
                                                           "VBUS_DET_F",
@@ -383,15 +417,15 @@
                                                           "USB_LINK_STATUS",
                                                           "USB_ADP_PROBE_PLUG",
                                                           "USB_ADP_PROBE_UNPLUG";
-                                        vddulpivio18-supply = <&ab8500_ldo_initcore_reg>;
+                                        vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
                                         v-ape-supply = <&db8500_vape_reg>;
                                         musb_1v8-supply = <&db8500_vsmps2_reg>;
                                 };
 
                                 ab8500-ponkey {
                                         compatible = "stericsson,ab8500-poweron-key";
-                                        interrupts = <6 0x4
-                                                      7 0x4>;
+                                        interrupts = <6 IRQ_TYPE_LEVEL_HIGH
+                                                      7 IRQ_TYPE_LEVEL_HIGH>;
                                         interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
                                 };
 
@@ -410,6 +444,11 @@
                                 codec: ab8500-codec {
                                         compatible = "stericsson,ab8500-codec";
 
+                                        V-AUD-supply = <&ab8500_ldo_audio_reg>;
+                                        V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>;
+                                        V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;
+                                        V-DMIC-supply = <&ab8500_ldo_dmic_reg>;
+
                                         stericsson,earpeice-cmv = <950>; /* Units in mV. */
                                 };
 
@@ -441,8 +480,8 @@
                                         };
 
                                         // supply for v-intcore12; VINTCORE12 LDO
-                                        ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
-                                                regulator-compatible = "ab8500_ldo_initcore";
+                                        ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
+                                                regulator-compatible = "ab8500_ldo_intcore";
                                         };
 
                                         // supply for tvout; gpadc; TVOUT LDO
@@ -460,14 +499,14 @@
                                                 regulator-compatible = "ab8500_ldo_audio";
                                         };
 
-                                        // supply for v-anamic1 VAMic1-LDO
+                                        // supply for v-anamic1 VAMIC1 LDO
                                         ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
                                                 regulator-compatible = "ab8500_ldo_anamic1";
                                         };
 
                                         // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
-                                        ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
-                                                regulator-compatible = "ab8500_ldo_amamic2";
+                                        ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
+                                                regulator-compatible = "ab8500_ldo_anamic2";
                                         };
 
                                         // supply for v-dmic; VDMIC LDO
@@ -486,7 +525,7 @@
                 i2c@80004000 {
                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                         reg = <0x80004000 0x1000>;
-                        interrupts = <0 21 0x4>;
+                        interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
                         arm,primecell-periphid = <0x180024>;
 
                         #address-cells = <1>;
@@ -499,7 +538,7 @@
                 i2c@80122000 {
                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                         reg = <0x80122000 0x1000>;
-                        interrupts = <0 22 0x4>;
+                        interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
                         arm,primecell-periphid = <0x180024>;
 
                         #address-cells = <1>;
@@ -512,7 +551,7 @@
                 i2c@80128000 {
                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                         reg = <0x80128000 0x1000>;
-                        interrupts = <0 55 0x4>;
+                        interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
                         arm,primecell-periphid = <0x180024>;
 
                         #address-cells = <1>;
@@ -525,7 +564,7 @@
                 i2c@80110000 {
                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                         reg = <0x80110000 0x1000>;
-                        interrupts = <0 12 0x4>;
+                        interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
                         arm,primecell-periphid = <0x180024>;
 
                         #address-cells = <1>;
@@ -538,7 +577,7 @@
                 i2c@8012a000 {
                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                         reg = <0x8012a000 0x1000>;
-                        interrupts = <0 51 0x4>;
+                        interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
                         arm,primecell-periphid = <0x180024>;
 
                         #address-cells = <1>;
@@ -551,82 +590,114 @@
                 ssp@80002000 {
                         compatible = "arm,pl022", "arm,primecell";
                         reg = <0x80002000 0x1000>;
-                        interrupts = <0 14 0x4>;
+                        interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         status = "disabled";
-
-                        // Add one of these for each child device
-                        cs-gpios = <&gpio0 31 0x4 &gpio4 14 0x4 &gpio4 16 0x4
-                                    &gpio6 22 0x4 &gpio7 0 0x4>;
-
                 };
 
                 uart@80120000 {
                         compatible = "arm,pl011", "arm,primecell";
                         reg = <0x80120000 0x1000>;
-                        interrupts = <0 11 0x4>;
+                        interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
+
+                        dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
+                               <&dma 13 0 0x0>; /* Logical - MemToDev */
+                        dma-names = "rx", "tx";
+
                         status = "disabled";
                 };
+
                 uart@80121000 {
                         compatible = "arm,pl011", "arm,primecell";
                         reg = <0x80121000 0x1000>;
-                        interrupts = <0 19 0x4>;
+                        interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
+
+                        dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
+                               <&dma 12 0 0x0>; /* Logical - MemToDev */
+                        dma-names = "rx", "tx";
+
                         status = "disabled";
                 };
+
                 uart@80007000 {
                         compatible = "arm,pl011", "arm,primecell";
                         reg = <0x80007000 0x1000>;
-                        interrupts = <0 26 0x4>;
+                        interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
+
+                        dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
+                               <&dma 11 0 0x0>; /* Logical - MemToDev */
+                        dma-names = "rx", "tx";
+
                         status = "disabled";
                 };
 
                 sdi0_per1@80126000 {
                         compatible = "arm,pl18x", "arm,primecell";
                         reg = <0x80126000 0x1000>;
-                        interrupts = <0 60 0x4>;
+                        interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
+
+                        dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
+                               <&dma 29 0 0x0>; /* Logical - MemToDev */
+                        dma-names = "rx", "tx";
+
                         status = "disabled";
                 };
 
                 sdi1_per2@80118000 {
                         compatible = "arm,pl18x", "arm,primecell";
                         reg = <0x80118000 0x1000>;
-                        interrupts = <0 50 0x4>;
+                        interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
+
+                        dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
+                               <&dma 32 0 0x0>; /* Logical - MemToDev */
+                        dma-names = "rx", "tx";
+
                         status = "disabled";
                 };
 
                 sdi2_per3@80005000 {
                         compatible = "arm,pl18x", "arm,primecell";
                         reg = <0x80005000 0x1000>;
-                        interrupts = <0 41 0x4>;
+                        interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
+
+                        dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
+                               <&dma 28 0 0x0>; /* Logical - MemToDev */
+                        dma-names = "rx", "tx";
+
                         status = "disabled";
                 };
 
                 sdi3_per2@80119000 {
                         compatible = "arm,pl18x", "arm,primecell";
                         reg = <0x80119000 0x1000>;
-                        interrupts = <0 59 0x4>;
+                        interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
                         status = "disabled";
                 };
 
                 sdi4_per2@80114000 {
                         compatible = "arm,pl18x", "arm,primecell";
                         reg = <0x80114000 0x1000>;
-                        interrupts = <0 99 0x4>;
+                        interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
+
+                        dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
+                               <&dma 42 0 0x0>; /* Logical - MemToDev */
+                        dma-names = "rx", "tx";
+
                         status = "disabled";
                 };
 
                 sdi5_per3@80008000 {
                         compatible = "arm,pl18x", "arm,primecell";
                         reg = <0x80008000 0x1000>;
-                        interrupts = <0 100 0x4>;
+                        interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
                         status = "disabled";
                 };
 
                 msp0: msp@80123000 {
                         compatible = "stericsson,ux500-msp-i2s";
                         reg = <0x80123000 0x1000>;
-                        interrupts = <0 31 0x4>;
+                        interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
                         v-ape-supply = <&db8500_vape_reg>;
                         status = "disabled";
                 };
@@ -634,7 +705,7 @@
                 msp1: msp@80124000 {
                         compatible = "stericsson,ux500-msp-i2s";
                         reg = <0x80124000 0x1000>;
-                        interrupts = <0 62 0x4>;
+                        interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
                         v-ape-supply = <&db8500_vape_reg>;
                         status = "disabled";
                 };
@@ -643,7 +714,7 @@
                 msp2: msp@80117000 {
                         compatible = "stericsson,ux500-msp-i2s";
                         reg = <0x80117000 0x1000>;
-                        interrupts = <0 98 0x4>;
+                        interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
                         v-ape-supply = <&db8500_vape_reg>;
                         status = "disabled";
                 };
@@ -651,7 +722,7 @@
                 msp3: msp@80125000 {
                         compatible = "stericsson,ux500-msp-i2s";
                         reg = <0x80125000 0x1000>;
-                        interrupts = <0 62 0x4>;
+                        interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
                         v-ape-supply = <&db8500_vape_reg>;
                         status = "disabled";
                 };
@@ -686,5 +757,20 @@
 
                         status = "disabled";
                 };
+
+                cryp@a03cb000 {
+                        compatible = "stericsson,ux500-cryp";
+                        reg = <0xa03cb000 0x1000>;
+                        interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
+
+                        v-ape-supply = <&db8500_vape_reg>;
+                };
+
+                hash@a03c2000 {
+                        compatible = "stericsson,ux500-hash";
+                        reg = <0xa03c2000 0x1000>;
+
+                        v-ape-supply = <&db8500_vape_reg>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
index 7e3065abd751..5cae2ab69762 100644
--- a/arch/arm/boot/dts/dove-cubox.dts
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -44,11 +44,60 @@
                         gpio = <&gpio0 1 0>;
                 };
         };
+
+        clocks {
+                /* 25MHz reference crystal */
+                ref25: oscillator {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <25000000>;
+                };
+        };
 };
 
 &uart0 { status = "okay"; };
 &sata0 { status = "okay"; };
-&i2c0 { status = "okay"; };
+
+&i2c0 {
+        status = "okay";
+        clock-frequency = <100000>;
+
+        si5351: clock-generator {
+                compatible = "silabs,si5351a-msop";
+                reg = <0x60>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                #clock-cells = <1>;
+
+                /* connect xtal input to 25MHz reference */
+                clocks = <&ref25>;
+
+                /* connect xtal input as source of pll0 and pll1 */
+                silabs,pll-source = <0 0>, <1 0>;
+
+                clkout0 {
+                        reg = <0>;
+                        silabs,drive-strength = <8>;
+                        silabs,multisynth-source = <0>;
+                        silabs,clock-source = <0>;
+                        silabs,pll-master;
+                };
+
+                clkout1 {
+                        reg = <1>;
+                        silabs,drive-strength = <8>;
+                        silabs,multisynth-source = <1>;
+                        silabs,clock-source = <0>;
+                        silabs,pll-master;
+                };
+
+                clkout2 {
+                        reg = <2>;
+                        silabs,multisynth-source = <1>;
+                        silabs,clock-source = <0>;
+                };
+        };
+};
 
 &sdio0 {
         status = "okay";
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 359694c78918..bed40ee2e4f6 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -160,6 +160,8 @@
                 reg = <0x13400000 0x10000>;
                 interrupts = <0 94 0>;
                 samsung,power-domain = <&pd_mfc>;
+                clocks = <&clock 170>, <&clock 273>;
+                clock-names = "sclk_mfc", "mfc";
                 status = "disabled";
         };
 
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index 524b90846df5..08609b8bdaf1 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -41,6 +41,10 @@
                 enable-active-high;
         };
 
+        tmu@100C0000 {
+                status = "okay";
+        };
+
         sdhci@12530000 {
                 bus-width = <4>;
                 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
@@ -83,6 +87,150 @@
                 status = "okay";
         };
 
+        i2c@13860000 {
+                status = "okay";
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <20000>;
+                pinctrl-0 = <&i2c0_bus>;
+                pinctrl-names = "default";
+
+                max8997_pmic@66 {
+                        compatible = "maxim,max8997-pmic";
+                        reg = <0x66>;
+                        interrupt-parent = <&gpx0>;
+                        interrupts = <4 0>, <3 0>;
+
+                        max8997,pmic-buck1-dvs-voltage = <1350000>;
+                        max8997,pmic-buck2-dvs-voltage = <1100000>;
+                        max8997,pmic-buck5-dvs-voltage = <1200000>;
+
+                        regulators {
+                                ldo1_reg: LDO1 {
+                                        regulator-name = "VDD_ABB_3.3V";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                ldo2_reg: LDO2 {
+                                        regulator-name = "VDD_ALIVE_1.1V";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo3_reg: LDO3 {
+                                        regulator-name = "VMIPI_1.1V";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                };
+
+                                ldo4_reg: LDO4 {
+                                        regulator-name = "VDD_RTC_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo6_reg: LDO6 {
+                                        regulator-name = "VMIPI_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo7_reg: LDO7 {
+                                        regulator-name = "VDD_AUD_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                ldo8_reg: LDO8 {
+                                        regulator-name = "VADC_3.3V";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                ldo9_reg: LDO9 {
+                                        regulator-name = "DVDD_SWB_2.8V";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo10_reg: LDO10 {
+                                        regulator-name = "VDD_PLL_1.1V";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo11_reg: LDO11 {
+                                        regulator-name = "VDD_AUD_3V";
+                                        regulator-min-microvolt = <3000000>;
+                                        regulator-max-microvolt = <3000000>;
+                                };
+
+                                ldo14_reg: LDO14 {
+                                        regulator-name = "AVDD18_SWB_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo17_reg: LDO17 {
+                                        regulator-name = "VDD_SWB_3.3V";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo21_reg: LDO21 {
+                                        regulator-name = "VDD_MIF_1.2V";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+
+                                buck1_reg: BUCK1 {
+                                        regulator-name = "VDD_ARM_1.2V";
+                                        regulator-min-microvolt = <950000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck2_reg: BUCK2 {
+                                        regulator-name = "VDD_INT_1.1V";
+                                        regulator-min-microvolt = <900000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck3_reg: BUCK3 {
+                                        regulator-name = "VDD_G3D_1.1V";
+                                        regulator-min-microvolt = <900000>;
+                                        regulator-max-microvolt = <1100000>;
+                                };
+
+                                buck5_reg: BUCK5 {
+                                        regulator-name = "VDDQ_M1M2_1.2V";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+
+                                buck7_reg: BUCK7 {
+                                        regulator-name = "VDD_LCD_3.3V";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+                        };
+                };
+        };
+
         gpio_keys {
                 compatible = "gpio-keys";
                 #address-cells = <1>;
@@ -143,4 +291,25 @@
                         clock-frequency = <24000000>;
                 };
         };
+
+        fimd@11c00000 {
+                pinctrl-0 = <&lcd_en &lcd_clk &lcd_data24 &pwm0_out>;
+                pinctrl-names = "default";
+                status = "okay";
+        };
+
+        display-timings {
+                native-mode = <&timing0>;
+                timing0: timing {
+                        clock-frequency = <50000>;
+                        hactive = <1024>;
+                        vactive = <600>;
+                        hfront-porch = <64>;
+                        hback-porch = <16>;
+                        hsync-len = <48>;
+                        vback-porch = <64>;
+                        vfront-porch = <16>;
+                        vsync-len = <3>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
index 55a2efb763d1..553bceae8967 100644
--- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
@@ -330,6 +330,95 @@
                         samsung,pin-pud = <3>;
                         samsung,pin-drv = <0>;
                 };
+
+                pwm0_out: pwm0-out {
+                        samsung,pins = "gpd0-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                pwm1_out: pwm1-out {
+                        samsung,pins = "gpd0-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                pwm2_out: pwm2-out {
+                        samsung,pins = "gpd0-2";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                pwm3_out: pwm3-out {
+                        samsung,pins = "gpd0-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                lcd_ctrl: lcd-ctrl {
+                        samsung,pins = "gpd0-0", "gpd0-1";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                lcd_sync: lcd-sync {
+                        samsung,pins = "gpf0-0", "gpf0-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                lcd_en: lcd-en {
+                        samsung,pins = "gpe3-4";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                lcd_clk: lcd-clk {
+                        samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                lcd_data16: lcd-data-width16 {
+                        samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2",
+                                        "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0",
+                                        "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7",
+                                        "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                lcd_data18: lcd-data-width18 {
+                        samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1",
+                                        "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7",
+                                        "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
+                                        "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1",
+                                        "gpf3-2", "gpf3-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                lcd_data24: lcd-data-width24 {
+                        samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7",
+                                        "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3",
+                                        "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7",
+                                        "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
+                                        "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7",
+                                        "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
         };
 
         pinctrl@11000000 {
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 54710de82908..d4f8067e89ba 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -112,12 +112,17 @@
                 interrupt-parent = <&combiner>;
                 reg = <0x100C0000 0x100>;
                 interrupts = <2 4>;
+                clocks = <&clock 383>;
+                clock-names = "tmu_apbif";
+                status = "disabled";
         };
 
         g2d@12800000 {
                 compatible = "samsung,s5pv210-g2d";
                 reg = <0x12800000 0x1000>;
                 interrupts = <0 89 0>;
+                clocks = <&clock 177>, <&clock 277>;
+                clock-names = "sclk_fimg2d", "fimg2d";
                 status = "disabled";
         };
 };
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 53bc8bf77984..867d9452619b 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -43,6 +43,7 @@
                 #size-cells = <0>;
                 pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
                 pinctrl-names = "default";
+                vmmc-supply = <&ldo20_reg &buck8_reg>;
                 status = "okay";
 
                 num-slots = <1>;
@@ -78,6 +79,7 @@
                 bus-width = <4>;
                 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
                 pinctrl-names = "default";
+                vmmc-supply = <&ldo4_reg &ldo21_reg>;
                 status = "okay";
         };
 
@@ -108,4 +110,199 @@
                         clock-frequency = <24000000>;
                 };
         };
+
+        i2c@13860000 {
+                pinctrl-0 = <&i2c0_bus>;
+                pinctrl-names = "default";
+                status = "okay";
+
+                max77686: pmic@09 {
+                        compatible = "maxim,max77686";
+                        reg = <0x09>;
+
+                        voltage-regulators {
+                                ldo1_reg: LDO1 {
+                                        regulator-name = "VDD_ALIVE_1.0V";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo2_reg: LDO2 {
+                                        regulator-name = "VDDQ_M1_2_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo3_reg: LDO3 {
+                                        regulator-name = "VDDQ_EXT_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo4_reg: LDO4 {
+                                        regulator-name = "VDDQ_MMC2_2.8V";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo5_reg: LDO5 {
+                                        regulator-name = "VDDQ_MMC1_3_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo6_reg: LDO6 {
+                                        regulator-name = "VDD10_MPLL_1.0V";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo7_reg: LDO7 {
+                                        regulator-name = "VDD10_XPLL_1.0V";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo11_reg: LDO11 {
+                                        regulator-name = "VDD18_ABB1_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo12_reg: LDO12 {
+                                        regulator-name = "VDD33_USB_3.3V";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo13_reg: LDO13 {
+                                        regulator-name = "VDDQ_C2C_W_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo14_reg: LDO14 {
+                                        regulator-name = "VDD18_ABB0_2_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo15_reg: LDO15 {
+                                        regulator-name = "VDD10_HSIC_1.0V";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo16_reg: LDO16 {
+                                        regulator-name = "VDD18_HSIC_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo20_reg: LDO20 {
+                                        regulator-name = "LDO20_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-boot-on;
+                                };
+
+                                ldo21_reg: LDO21 {
+                                        regulator-name = "LDO21_3.3V";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo25_reg: LDO25 {
+                                        regulator-name = "VDDQ_LCD_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck1_reg: BUCK1 {
+                                        regulator-name = "vdd_mif";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck2_reg: BUCK2 {
+                                        regulator-name = "vdd_arm";
+                                        regulator-min-microvolt = <900000>;
+                                        regulator-max-microvolt = <1300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck3_reg: BUCK3 {
+                                        regulator-name = "vdd_int";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck4_reg: BUCK4 {
+                                        regulator-name = "vdd_g3d";
+                                        regulator-min-microvolt = <900000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-microvolt-offset = <50000>;
+                                };
+
+                                buck5_reg: BUCK5 {
+                                        regulator-name = "VDDQ_CKEM1_2_1.2V";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck6_reg: BUCK6 {
+                                        regulator-name = "BUCK6_1.35V";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck7_reg: BUCK7 {
+                                        regulator-name = "BUCK7_2.0V";
+                                        regulator-min-microvolt = <2000000>;
+                                        regulator-max-microvolt = <2000000>;
+                                        regulator-always-on;
+                                };
+
+                                buck8_reg: BUCK8 {
+                                        regulator-name = "BUCK8_2.8V";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index 1c21bad32ca9..ca73c42f77e1 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -36,6 +36,72 @@
                 enable-active-high;
         };
 
+        pinctrl@11000000 {
+                keypad_rows: keypad-rows {
+                        samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                keypad_cols: keypad-cols {
+                        samsung,pins = "gpx1-0", "gpx1-1";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+        };
+
+        keypad@100A0000 {
+                samsung,keypad-num-rows = <3>;
+                samsung,keypad-num-columns = <2>;
+                linux,keypad-no-autorepeat;
+                linux,keypad-wakeup;
+                pinctrl-0 = <&keypad_rows &keypad_cols>;
+                pinctrl-names = "default";
+                status = "okay";
+
+                key_home {
+                        keypad,row = <0>;
+                        keypad,column = <0>;
+                        linux,code = <102>;
+                };
+
+                key_down {
+                        keypad,row = <0>;
+                        keypad,column = <1>;
+                        linux,code = <108>;
+                };
+
+                key_up {
+                        keypad,row = <1>;
+                        keypad,column = <0>;
+                        linux,code = <103>;
+                };
+
+                key_menu {
+                        keypad,row = <1>;
+                        keypad,column = <1>;
+                        linux,code = <139>;
+                };
+
+                key_back {
+                        keypad,row = <2>;
+                        keypad,column = <0>;
+                        linux,code = <158>;
+                };
+
+                key_enter {
+                        keypad,row = <2>;
+                        keypad,column = <1>;
+                        linux,code = <28>;
+                };
+        };
+
+        g2d@10800000 {
+                status = "okay";
+        };
+
         sdhci@12530000 {
                 bus-width = <4>;
                 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index dd564310d4a5..a8ba195c41ac 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -31,8 +31,91 @@
                 status = "okay";
         };
 
-        g2d@10800000 {
+        pinctrl@11000000 {
+                keypad_rows: keypad-rows {
+                        samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                keypad_cols: keypad-cols {
+                        samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3",
+                                       "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+        };
+
+        keypad@100A0000 {
+                samsung,keypad-num-rows = <3>;
+                samsung,keypad-num-columns = <8>;
+                linux,keypad-no-autorepeat;
+                linux,keypad-wakeup;
+                pinctrl-0 = <&keypad_rows &keypad_cols>;
+                pinctrl-names = "default";
                 status = "okay";
+
+                key_1 {
+                        keypad,row = <1>;
+                        keypad,column = <3>;
+                        linux,code = <2>;
+                };
+
+                key_2 {
+                        keypad,row = <1>;
+                        keypad,column = <4>;
+                        linux,code = <3>;
+                };
+
+                key_3 {
+                        keypad,row = <1>;
+                        keypad,column = <5>;
+                        linux,code = <4>;
+                };
+
+                key_4 {
+                        keypad,row = <1>;
+                        keypad,column = <6>;
+                        linux,code = <5>;
+                };
+
+                key_5 {
+                        keypad,row = <1>;
+                        keypad,column = <7>;
+                        linux,code = <6>;
+                };
+
+                key_A {
+                        keypad,row = <2>;
+                        keypad,column = <6>;
+                        linux,code = <30>;
+                };
+
+                key_B {
+                        keypad,row = <2>;
+                        keypad,column = <7>;
+                        linux,code = <48>;
+                };
+
+                key_C {
+                        keypad,row = <0>;
+                        keypad,column = <5>;
+                        linux,code = <46>;
+                };
+
+                key_D {
+                        keypad,row = <2>;
+                        keypad,column = <5>;
+                        linux,code = <32>;
+                };
+
+                key_E {
+                        keypad,row = <0>;
+                        keypad,column = <7>;
+                        linux,code = <18>;
+                };
         };
 
         sdhci@12530000 {
diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
index 099cec79e2ae..704290f7c5c0 100644
--- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
@@ -778,62 +778,6 @@
                         samsung,pin-drv = <3>;
                 };
 
-                keypad_col0: keypad-col0 {
-                        samsung,pins = "gpl2-0";
-                        samsung,pin-function = <3>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-
-                keypad_col1: keypad-col1 {
-                        samsung,pins = "gpl2-1";
-                        samsung,pin-function = <3>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-
-                keypad_col2: keypad-col2 {
-                        samsung,pins = "gpl2-2";
-                        samsung,pin-function = <3>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-
-                keypad_col3: keypad-col3 {
-                        samsung,pins = "gpl2-3";
-                        samsung,pin-function = <3>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-
-                keypad_col4: keypad-col4 {
-                        samsung,pins = "gpl2-4";
-                        samsung,pin-function = <3>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-
-                keypad_col5: keypad-col5 {
-                        samsung,pins = "gpl2-5";
-                        samsung,pin-function = <3>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-
-                keypad_col6: keypad-col6 {
-                        samsung,pins = "gpl2-6";
-                        samsung,pin-function = <3>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-
-                keypad_col7: keypad-col7 {
-                        samsung,pins = "gpl2-7";
-                        samsung,pin-function = <3>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-
                 cam_port_b: cam-port-b {
                         samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
                                         "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index e3380a7a285c..35cb2099d55e 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -28,14 +28,6 @@
                 pinctrl3 = &pinctrl_3;
         };
 
-        combiner:interrupt-controller@10440000 {
-                interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
-                             <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
-                             <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
-                             <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
-                             <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
-        };
-
         clock: clock-controller@0x10030000 {
                 compatible = "samsung,exynos4412-clock";
                 reg = <0x10030000 0x20000>;
@@ -77,6 +69,8 @@
                 compatible = "samsung,exynos4212-g2d";
                 reg = <0x10800000 0x1000>;
                 interrupts = <0 89 0>;
+                clocks = <&clock 177>, <&clock 277>;
+                clock-names = "sclk_fimg2d", "fimg2d";
                 status = "disabled";
         };
 };
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 02cfc76d002f..c6db281a3430 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -449,4 +449,35 @@
                         clock-frequency = <24000000>;
                 };
         };
+
+        dp-controller {
+                samsung,color-space = <0>;
+                samsung,dynamic-range = <0>;
+                samsung,ycbcr-coeff = <0>;
+                samsung,color-depth = <1>;
+                samsung,link-rate = <0x0a>;
+                samsung,lane-count = <4>;
+        };
+
+        fimd: fimd@14400000 {
+                display-timings {
+                        native-mode = <&timing0>;
+                        timing0: timing@0 {
+                                /* 2560x1600 DP panel */
+                                clock-frequency = <50000>;
+                                hactive = <2560>;
+                                vactive = <1600>;
+                                hfront-porch = <48>;
+                                hback-porch = <80>;
+                                hsync-len = <32>;
+                                vback-porch = <16>;
+                                vfront-porch = <8>;
+                                vsync-len = <6>;
+                        };
+                };
+        };
+
+        rtc {
+                status = "okay";
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
index ded558bb0f3b..724a22f9b1c8 100644
--- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
@@ -553,6 +553,13 @@
                         samsung,pin-pud = <0>;
                         samaung,pin-drv = <0>;
                 };
+
+                dp_hpd: dp_hpd {
+                        samsung,pins = "gpx0-7";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samaung,pin-drv = <0>;
+                };
         };
 
         pinctrl@13400000 {
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 3e0c792e2767..1e21200b6d85 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -37,6 +37,30 @@
                 };
         };
 
+        vdd:fixed-regulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "vdd-supply";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                regulator-always-on;
+        };
+
+        dbvdd:fixed-regulator@1 {
+                compatible = "regulator-fixed";
+                regulator-name = "dbvdd-supply";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
+
+        spkvdd:fixed-regulator@2 {
+                compatible = "regulator-fixed";
+                regulator-name = "spkvdd-supply";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-always-on;
+        };
+
         i2c@12C70000 {
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <20000>;
@@ -47,8 +71,17 @@
                 };
 
                 wm8994: wm8994@1a {
-                         compatible = "wlf,wm8994";
-                         reg = <0x1a>;
+                        compatible = "wlf,wm8994";
+                        reg = <0x1a>;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        AVDD2-supply = <&vdd>;
+                        CPVDD-supply = <&vdd>;
+                        DBVDD-supply = <&dbvdd>;
+                        SPKVDD1-supply = <&spkvdd>;
+                        SPKVDD2-supply = <&spkvdd>;
                 };
         };
 
@@ -224,6 +257,9 @@
                 samsung,color-depth = <1>;
                 samsung,link-rate = <0x0a>;
                 samsung,lane-count = <4>;
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&dp_hpd>;
         };
 
         display-timings {
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index d449feb7e143..05244f150dd9 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -171,6 +171,10 @@
                 };
         };
 
+        rtc {
+                status = "okay";
+        };
+
         /*
          * On Snow we've got SIP WiFi and so can keep drive strengths low to
          * reduce EMI.
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index fc9fb3d526e2..54a35e64c781 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -479,6 +479,36 @@
                 pinctrl-0 = <&i2s2_bus>;
         };
 
+        usb@12000000 {
+                compatible = "samsung,exynos5250-dwusb3";
+                clocks = <&clock 286>;
+                clock-names = "usbdrd30";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                dwc3 {
+                        compatible = "synopsys,dwc3";
+                        reg = <0x12000000 0x10000>;
+                        interrupts = <0 72 0>;
+                        usb-phy = <&usb2_phy &usb3_phy>;
+                };
+        };
+
+        usb3_phy: usbphy@12100000 {
+                compatible = "samsung,exynos5250-usb3phy";
+                reg = <0x12100000 0x100>;
+                clocks = <&clock 1>, <&clock 286>;
+                clock-names = "ext_xtal", "usbdrd30";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                usbphy-sys {
+                        reg = <0x10040704 0x8>;
+                };
+        };
+
         usb@12110000 {
                 compatible = "samsung,exynos4210-ehci";
                 reg = <0x12110000 0x100>;
@@ -497,7 +527,7 @@
                 clock-names = "usbhost";
         };
 
-        usbphy@12130000 {
+        usb2_phy: usbphy@12130000 {
                 compatible = "samsung,exynos5250-usb2phy";
                 reg = <0x12130000 0x100>;
                 clocks = <&clock 1>, <&clock 285>;
@@ -621,6 +651,8 @@
                 reg = <0x145b0000 0x1000>;
                 interrupts = <10 3>;
                 interrupt-parent = <&combiner>;
+                clocks = <&clock 342>;
+                clock-names = "dp";
                 #address-cells = <1>;
                 #size-cells = <0>;
 
diff --git a/arch/arm/boot/dts/exynos5440-sd5v1.dts b/arch/arm/boot/dts/exynos5440-sd5v1.dts
index ef747b52b674..f722a0263ac8 100644
--- a/arch/arm/boot/dts/exynos5440-sd5v1.dts
+++ b/arch/arm/boot/dts/exynos5440-sd5v1.dts
@@ -17,7 +17,7 @@
         compatible = "samsung,sd5v1", "samsung,exynos5440";
 
         chosen {
-                bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 console=ttySAC0,115200";
+                bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200";
         };
 
         fixed-rate-clocks {
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index f96de398c965..ba88cfd2486f 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -17,11 +17,46 @@
         compatible = "samsung,ssdk5440", "samsung,exynos5440";
 
         chosen {
-                bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 console=ttySAC0,115200";
+                bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200";
         };
 
-        spi {
-                status = "disabled";
+        spi_0: spi@D0000 {
+
+                flash: w25q128@0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "winbond,w25q128";
+                        spi-max-frequency = <15625000>;
+                        reg = <0>;
+                        controller-data {
+                                samsung,spi-feedback-delay = <0>;
+                        };
+
+                        partition@00000 {
+                                label = "BootLoader";
+                                reg = <0x60000 0x80000>;
+                                read-only;
+                        };
+
+                        partition@e0000 {
+                                label = "Recovery-Kernel";
+                                reg = <0xe0000 0x300000>;
+                                read-only;
+                        };
+
+                        partition@3e0000 {
+                                label = "CRAM-FS";
+                                reg = <0x3e0000 0x700000>;
+                                read-only;
+                        };
+
+                        partition@ae0000 {
+                                label = "User-Data";
+                                reg = <0xae0000 0x520000>;
+                        };
+
+                };
+
         };
 
         fixed-rate-clocks {
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index b7ffc4dfe219..bfcb907b7e33 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -16,6 +16,10 @@
 
         interrupt-parent = <&gic>;
 
+        aliases {
+                spi0 = &spi_0;
+        };
+
         clock: clock-controller@0x160000 {
                 compatible = "samsung,exynos5440-clock";
                 reg = <0x160000 0x1000>;
@@ -38,18 +42,22 @@
                 #size-cells = <0>;
 
                 cpu@0 {
+                        device_type = "cpu";
                         compatible = "arm,cortex-a15";
                         reg = <0>;
                 };
                 cpu@1 {
+                        device_type = "cpu";
                         compatible = "arm,cortex-a15";
                         reg = <1>;
                 };
                 cpu@2 {
+                        device_type = "cpu";
                         compatible = "arm,cortex-a15";
                         reg = <2>;
                 };
                 cpu@3 {
+                        device_type = "cpu";
                         compatible = "arm,cortex-a15";
                         reg = <3>;
                 };
@@ -79,8 +87,13 @@
                 interrupts = <0 57 0>;
                 operating-points = <
                                 /* KHz    uV */
+                                1500000 1100000
+                                1400000 1075000
+                                1300000 1050000
                                 1200000 1025000
+                                1100000 1000000
                                 1000000 975000
+                                900000  950000
                                 800000  925000
                 >;
         };
@@ -101,14 +114,14 @@
                 clock-names = "uart", "clk_uart_baud0";
         };
 
-        spi {
-                compatible = "samsung,exynos4210-spi";
-                reg = <0xD0000 0x1000>;
+        spi_0: spi@D0000 {
+                compatible = "samsung,exynos5440-spi";
+                reg = <0xD0000 0x100>;
                 interrupts = <0 4 0>;
-                tx-dma-channel = <&pdma0 5>; /* preliminary */
-                rx-dma-channel = <&pdma0 4>; /* preliminary */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                samsung,spi-src-clk = <0>;
+                num-cs = <1>;
                 clocks = <&clock 21>, <&clock 16>;
                 clock-names = "spi", "spi_busclk0";
         };
@@ -184,28 +197,6 @@
                 compatible = "arm,amba-bus";
                 interrupt-parent = <&gic>;
                 ranges;
-
-                pdma0: pdma@00121000 {
-                        compatible = "arm,pl330", "arm,primecell";
-                        reg = <0x121000 0x1000>;
-                        interrupts = <0 46 0>;
-                        clocks = <&clock 8>;
-                        clock-names = "apb_pclk";
-                        #dma-cells = <1>;
-                        #dma-channels = <8>;
-                        #dma-requests = <32>;
-                };
-
-                pdma1: pdma@00120000 {
-                        compatible = "arm,pl330", "arm,primecell";
-                        reg = <0x120000 0x1000>;
-                        interrupts = <0 47 0>;
-                        clocks = <&clock 8>;
-                        clock-names = "apb_pclk";
-                        #dma-cells = <1>;
-                        #dma-channels = <8>;
-                        #dma-requests = <32>;
-                };
         };
 
         rtc {
@@ -214,7 +205,30 @@
                 interrupts = <0 17 0>, <0 16 0>;
                 clocks = <&clock 21>;
                 clock-names = "rtc";
-                status = "disabled";
+        };
+
+        sata@210000 {
+                compatible = "snps,exynos5440-ahci";
+                reg = <0x210000 0x10000>;
+                interrupts = <0 30 0>;
+                clocks = <&clock 23>;
+                clock-names = "sata";
+        };
+
+        ohci@220000 {
+                compatible = "samsung,exynos5440-ohci";
+                reg = <0x220000 0x1000>;
+                interrupts = <0 29 0>;
+                clocks = <&clock 24>;
+                clock-names = "usbhost";
+        };
+
+        ehci@221000 {
+                compatible = "samsung,exynos5440-ehci";
+                reg = <0x221000 0x1000>;
+                interrupts = <0 29 0>;
+                clocks = <&clock 24>;
+                clock-names = "usbhost";
         };
 
         pcie@290000 {
diff --git a/arch/arm/boot/dts/href.dtsi b/arch/arm/boot/dts/href.dtsi
index c0bc426952ea..9db41b9d8358 100644
--- a/arch/arm/boot/dts/href.dtsi
+++ b/arch/arm/boot/dts/href.dtsi
@@ -9,7 +9,8 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-/include/ "dbx5x0.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "dbx5x0.dtsi"
 
 / {
         memory {
@@ -27,7 +28,7 @@
                 };
         };
 
-        soc-u9500 {
+        soc {
                 uart@80120000 {
                         status = "okay";
                 };
@@ -45,14 +46,14 @@
                                 compatible = "tc3589x";
                                 reg = <0x42>;
                                 interrupt-parent = <&gpio6>;
-                                interrupts = <25 0x1>;
+                                interrupts = <25 IRQ_TYPE_EDGE_RISING>;
 
                                 interrupt-controller;
                                 #interrupt-cells = <2>;
 
                                 tc3589x_gpio: tc3589x_gpio {
                                         compatible = "tc3589x-gpio";
-                                        interrupts = <0 0x1>;
+                                        interrupts = <0 IRQ_TYPE_EDGE_RISING>;
 
                                         interrupt-controller;
                                         #interrupt-cells = <2>;
@@ -63,17 +64,43 @@
                 };
 
                 i2c@80128000 {
-                        lp5521@0x33 {
-                                compatible = "lp5521";
+                        lp5521@33 {
+                                compatible = "national,lp5521";
                                 reg = <0x33>;
+                                label = "lp5521_pri";
+                                clock-mode = /bits/ 8 <2>;
+                                chan0 {
+                                        led-cur = /bits/ 8 <0x2f>;
+                                        max-cur = /bits/ 8 <0x5f>;
+                                };
+                                chan1 {
+                                        led-cur = /bits/ 8 <0x2f>;
+                                        max-cur = /bits/ 8 <0x5f>;
+                                };
+                                chan2 {
+                                        led-cur = /bits/ 8 <0x2f>;
+                                        max-cur = /bits/ 8 <0x5f>;
+                                };
                         };
-
-                        lp5521@0x34 {
-                                compatible = "lp5521";
+                        lp5521@34 {
+                                compatible = "national,lp5521";
                                 reg = <0x34>;
+                                label = "lp5521_sec";
+                                clock-mode = /bits/ 8 <2>;
+                                chan0 {
+                                        led-cur = /bits/ 8 <0x2f>;
+                                        max-cur = /bits/ 8 <0x5f>;
+                                };
+                                chan1 {
+                                        led-cur = /bits/ 8 <0x2f>;
+                                        max-cur = /bits/ 8 <0x5f>;
+                                };
+                                chan2 {
+                                        led-cur = /bits/ 8 <0x2f>;
+                                        max-cur = /bits/ 8 <0x5f>;
+                                };
                         };
-
-                        bh1780@0x29 {
+                        bh1780@29 {
                                 compatible = "rohm,bh1780gli";
                                 reg = <0x33>;
                         };
@@ -82,7 +109,7 @@
                 // External Micro SD slot
                 sdi0_per1@80126000 {
                         arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                         bus-width = <4>;
                         mmc-cap-sd-highspeed;
                         mmc-cap-mmc-highspeed;
@@ -97,7 +124,7 @@
                 // WLAN SDIO channel
                 sdi1_per2@80118000 {
                         arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                         bus-width = <4>;
 
                         status = "okay";
@@ -106,7 +133,7 @@
                 // PoP:ed eMMC
                 sdi2_per3@80005000 {
                         arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                         bus-width = <8>;
                         mmc-cap-mmc-highspeed;
 
@@ -116,7 +143,7 @@
                 // On-board eMMC
                 sdi4_per2@80114000 {
                         arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                         bus-width = <8>;
                         mmc-cap-mmc-highspeed;
                         vmmc-supply = <&ab8500_ldo_aux2_reg>;
@@ -236,7 +263,7 @@
                                                 regulator-name = "V-MMC-SD";
                                         };
 
-                                        ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
+                                        ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
                                                 regulator-name = "V-INTCORE";
                                         };
 
@@ -256,7 +283,7 @@
                                                 regulator-name = "V-AMIC1";
                                         };
 
-                                        ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
+                                        ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
                                                 regulator-name = "V-AMIC2";
                                         };
 
diff --git a/arch/arm/boot/dts/hrefprev60.dts b/arch/arm/boot/dts/hrefprev60.dts
index c2d274815923..c6bb07df2d1d 100644
--- a/arch/arm/boot/dts/hrefprev60.dts
+++ b/arch/arm/boot/dts/hrefprev60.dts
@@ -10,9 +10,9 @@
  */
 
 /dts-v1/;
-/include/ "dbx5x0.dtsi"
-/include/ "href.dtsi"
-/include/ "stuib.dtsi"
+#include "dbx5x0.dtsi"
+#include "href.dtsi"
+#include "stuib.dtsi"
 
 / {
         model = "ST-Ericsson HREF (pre-v60) platform with Device Tree";
@@ -24,7 +24,7 @@
                 };
         };
 
-        soc-u9500 {
+        soc {
                 prcmu@80157000 {
                         ab8500@5 {
                                 ab8500-gpio {
@@ -41,7 +41,7 @@
                 };
 
                 i2c@80110000 {
-                        bu21013_tp@0x5c {
+                        bu21013_tp@5c {
                                 reset-gpio = <&tc3589x_gpio 13 0x4>;
                         };
                 };
diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts
index 2b587a74b813..3d580d6447f9 100644
--- a/arch/arm/boot/dts/hrefv60plus.dts
+++ b/arch/arm/boot/dts/hrefv60plus.dts
@@ -10,9 +10,9 @@
  */
 
 /dts-v1/;
-/include/ "dbx5x0.dtsi"
-/include/ "href.dtsi"
-/include/ "stuib.dtsi"
+#include "dbx5x0.dtsi"
+#include "href.dtsi"
+#include "stuib.dtsi"
 
 / {
         model = "ST-Ericsson HREF (v60+) platform with Device Tree";
@@ -24,7 +24,7 @@
                 };
         };
 
-        soc-u9500 {
+        soc {
                 i2c@80110000 {
                         bu21013_tp@0x5c {
                                 reset-gpio = <&gpio4 15 0x4>;
@@ -34,7 +34,7 @@
                 // External Micro SD slot
                 sdi0_per1@80126000 {
                         arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                         bus-width = <4>;
                         mmc-cap-sd-highspeed;
                         mmc-cap-mmc-highspeed;
@@ -48,7 +48,7 @@
                 // WLAN SDIO channel
                 sdi1_per2@80118000 {
                         arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                         bus-width = <4>;
 
                         status = "okay";
@@ -57,7 +57,7 @@
                 // PoP:ed eMMC
                 sdi2_per3@80005000 {
                         arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                         bus-width = <8>;
                         mmc-cap-mmc-highspeed;
 
@@ -67,7 +67,7 @@
                 // On-board eMMC
                 sdi4_per2@80114000 {
                         arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                         bus-width = <8>;
                         mmc-cap-mmc-highspeed;
                         vmmc-supply = <&ab8500_ldo_aux2_reg>;
@@ -172,7 +172,7 @@
                                                 regulator-name = "V-MMC-SD";
                                         };
 
-                                        ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
+                                        ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
                                                 regulator-name = "V-INTCORE";
                                         };
 
@@ -192,7 +192,7 @@
                                                 regulator-name = "V-AMIC1";
                                         };
 
-                                        ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
+                                        ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
                                                 regulator-name = "V-AMIC2";
                                         };
 
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 73fd7d0887b5..587ceef81e45 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -23,8 +23,12 @@
         };
 
         cpus {
-                cpu@0 {
-                        compatible = "arm,arm926ejs";
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                 };
         };
 
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
new file mode 100644
index 000000000000..e7ed9786920a
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
@@ -0,0 +1,37 @@
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "imx27-phytec-phycore-som.dts"
+
+/ {
+        model = "Phytec pcm970";
+        compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27";
+};
+
+&cspi1 {
+        fsl,spi-num-chipselects = <2>;
+        cs-gpios = <&gpio4 28 0>, <&gpio4 27 0>;
+};
+
+&sdhci2 {
+        bus-width = <4>;
+        cd-gpios = <&gpio3 29 0>;
+        wp-gpios = <&gpio3 28 0>;
+        vmmc-supply = <&vmmc1_reg>;
+        status = "okay";
+};
+
+&uart1 {
+        fsl,uart-has-rtscts;
+};
+
+&uart2 {
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
new file mode 100644
index 000000000000..f0105651869d
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
@@ -0,0 +1,179 @@
+/*
+ * Copyright 2012 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx27.dtsi"
+
+/ {
+        model = "Phytec pcm038";
+        compatible = "phytec,imx27-pcm038", "fsl,imx27";
+
+        memory {
+                reg = <0x0 0x0>;
+        };
+
+        soc {
+                aipi@10000000 { /* aipi1 */
+                        serial@1000a000 {
+                                status = "okay";
+                        };
+
+                        i2c@1001d000 {
+                                clock-frequency = <400000>;
+                                status = "okay";
+                                at24@52 {
+                                        compatible = "at,24c32";
+                                        pagesize = <32>;
+                                        reg = <0x52>;
+                                };
+                                pcf8563@51 {
+                                        compatible = "nxp,pcf8563";
+                                        reg = <0x51>;
+                                };
+                                lm75@4a {
+                                        compatible = "national,lm75";
+                                        reg = <0x4a>;
+                                };
+                        };
+                };
+
+                aipi@10020000 { /* aipi2 */
+                        ethernet@1002b000 {
+                                phy-reset-gpios = <&gpio3 30 0>;
+                                status = "okay";
+                        };
+                };
+        };
+
+        nor_flash@c0000000 {
+                compatible = "cfi-flash";
+                bank-width = <2>;
+                reg = <0xc0000000 0x02000000>;
+                linux,mtd-name = "physmap-flash.0";
+                #address-cells = <1>;
+                #size-cells = <1>;
+        };
+};
+
+&cspi1 {
+        fsl,spi-num-chipselects = <1>;
+        cs-gpios = <&gpio4 28 0>;
+        status = "okay";
+
+        pmic: mc13783@0 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "fsl,mc13783";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+                interrupt-parent = <&gpio2>;
+                interrupts = <23 0x4>;
+                fsl,mc13xxx-uses-adc;
+                fsl,mc13xxx-uses-rtc;
+
+                regulators {
+                        sw1a_reg: sw1a {
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        sw1b_reg: sw1b {
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        sw2a_reg: sw2a {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        sw2b_reg: sw2b {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        sw3_reg: sw3 {
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5000000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        vaudio_reg: vaudio {
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        violo_reg: violo {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        viohi_reg: viohi {
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        vgen_reg: vgen {
+                                regulator-min-microvolt = <1500000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        vcam_reg: vcam {
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                        };
+
+                        vrf1_reg: vrf1 {
+                                regulator-min-microvolt = <2775000>;
+                                regulator-max-microvolt = <2775000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        vrf2_reg: vrf2 {
+                                regulator-min-microvolt = <2775000>;
+                                regulator-max-microvolt = <2775000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        vmmc1_reg: vmmc1 {
+                                regulator-min-microvolt = <1600000>;
+                                regulator-max-microvolt = <3000000>;
+                        };
+
+                        gpo1_reg: gpo1 { };
+
+                        pwgt1spi_reg: pwgt1spi {
+                                regulator-always-on;
+                        };
+                };
+        };
+};
+
+&nfc {
+        nand-bus-width = <8>;
+        nand-ecc-mode = "hw";
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
deleted file mode 100644
index fe64e3a91df0..000000000000
--- a/arch/arm/boot/dts/imx27-phytec-phycore.dts
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright 2012 Sascha Hauer, Pengutronix
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/dts-v1/;
-#include "imx27.dtsi"
-
-/ {
-        model = "Phytec pcm038";
-        compatible = "phytec,imx27-pcm038", "fsl,imx27";
-
-        memory {
-                reg = <0x0 0x0>;
-        };
-
-        soc {
-                aipi@10000000 { /* aipi1 */
-                        serial@1000a000 {
-                                fsl,uart-has-rtscts;
-                                status = "okay";
-                        };
-
-                        serial@1000b000 {
-                                fsl,uart-has-rtscts;
-                                status = "okay";
-                        };
-
-                        serial@1000c000 {
-                                fsl,uart-has-rtscts;
-                                status = "okay";
-                        };
-
-                        i2c@1001d000 {
-                                clock-frequency = <400000>;
-                                status = "okay";
-                                at24@52 {
-                                        compatible = "at,24c32";
-                                        pagesize = <32>;
-                                        reg = <0x52>;
-                                };
-                                pcf8563@51 {
-                                        compatible = "nxp,pcf8563";
-                                        reg = <0x51>;
-                                };
-                                lm75@4a {
-                                        compatible = "national,lm75";
-                                        reg = <0x4a>;
-                                };
-                        };
-                };
-
-                aipi@10020000 { /* aipi2 */
-                        ethernet@1002b000 {
-                                status = "okay";
-                        };
-                };
-        };
-
-        nor_flash@c0000000 {
-                compatible = "cfi-flash";
-                bank-width = <2>;
-                reg = <0xc0000000 0x02000000>;
-                #address-cells = <1>;
-                #size-cells = <1>;
-        };
-};
-
-&nfc {
-        nand-bus-width = <8>;
-        nand-ecc-mode = "hw";
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 75bd11386516..0695264ddf1b 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -25,6 +25,9 @@
                 gpio3 = &gpio4;
                 gpio4 = &gpio5;
                 gpio5 = &gpio6;
+                spi0 = &cspi1;
+                spi1 = &cspi2;
+                spi2 = &cspi3;
         };
 
         avic: avic-interrupt-controller@e0000000 {
@@ -58,6 +61,16 @@
                         reg = <0x10000000 0x20000>;
                         ranges;
 
+                        dma: dma@10001000 {
+                                compatible = "fsl,imx27-dma";
+                                reg = <0x10001000 0x1000>;
+                                interrupts = <32>;
+                                clocks = <&clks 50>, <&clks 70>;
+                                clock-names = "ipg", "ahb";
+                                #dma-cells = <1>;
+                                #dma-channels = <16>;
+                        };
+
                         wdog: wdog@10002000 {
                                 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
                                 reg = <0x10002000 0x1000>;
@@ -89,6 +102,14 @@
                                 clock-names = "ipg", "per";
                         };
 
+                        pwm0: pwm@10006000 {
+                                compatible = "fsl,imx27-pwm";
+                                reg = <0x10006000 0x1000>;
+                                interrupts = <23>;
+                                clocks = <&clks 34>, <&clks 61>;
+                                clock-names = "ipg", "per";
+                        };
+
                         uart1: serial@1000a000 {
                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
                                 reg = <0x1000a000 0x1000>;
@@ -157,6 +178,28 @@
                                 status = "disabled";
                         };
 
+                        sdhci1: sdhci@10013000 {
+                                compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
+                                reg = <0x10013000 0x1000>;
+                                interrupts = <11>;
+                                clocks = <&clks 30>, <&clks 60>;
+                                clock-names = "ipg", "per";
+                                dmas = <&dma 7>;
+                                dma-names = "rx-tx";
+                                status = "disabled";
+                        };
+
+                        sdhci2: sdhci@10014000 {
+                                compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
+                                reg = <0x10014000 0x1000>;
+                                interrupts = <10>;
+                                clocks = <&clks 29>, <&clks 60>;
+                                clock-names = "ipg", "per";
+                                dmas = <&dma 6>;
+                                dma-names = "rx-tx";
+                                status = "disabled";
+                        };
+
                         gpio1: gpio@10015000 {
                                 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
                                 reg = <0x10015000 0x100>;
@@ -272,6 +315,17 @@
                                 status = "disabled";
                         };
 
+                        sdhci3: sdhci@1001e000 {
+                                compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
+                                reg = <0x1001e000 0x1000>;
+                                interrupts = <9>;
+                                clocks = <&clks 28>, <&clks 60>;
+                                clock-names = "ipg", "per";
+                                dmas = <&dma 36>;
+                                dma-names = "rx-tx";
+                                status = "disabled";
+                        };
+
                         gpt6: timer@1001f000 {
                                 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
                                 reg = <0x1001f000 0x1000>;
@@ -288,6 +342,21 @@
                         reg = <0x10020000 0x20000>;
                         ranges;
 
+                        coda: coda@10023000 {
+                                compatible = "fsl,imx27-vpu";
+                                reg = <0x10023000 0x0200>;
+                                interrupts = <53>;
+                                clocks = <&clks 57>, <&clks 66>;
+                                clock-names = "per", "ahb";
+                                iram = <&iram>;
+                        };
+
+                        clks: ccm@10027000{
+                                compatible = "fsl,imx27-ccm";
+                                reg = <0x10027000 0x1000>;
+                                #clock-cells = <1>;
+                        };
+
                         fec: ethernet@1002b000 {
                                 compatible = "fsl,imx27-fec";
                                 reg = <0x1002b000 0x4000>;
@@ -296,19 +365,16 @@
                                 clock-names = "ipg", "ahb", "ptp";
                                 status = "disabled";
                         };
-
-                        clks: ccm@10027000{
-                                compatible = "fsl,imx27-ccm";
-                                reg = <0x10027000 0x1000>;
-                                #clock-cells = <1>;
-                        };
                 };
 
+                iram: iram@ffff4c00 {
+                        compatible = "mmio-sram";
+                        reg = <0xffff4c00 0xb400>;
+                };
 
                 nfc: nand@d8000000 {
                         #address-cells = <1>;
                         #size-cells = <1>;
-
                         compatible = "fsl,imx27-nand";
                         reg = <0xd8000000 0x1000>;
                         interrupts = <29>;
diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts
index 3d905d16cbec..b602494c152b 100644
--- a/arch/arm/boot/dts/imx28-apf28dev.dts
+++ b/arch/arm/boot/dts/imx28-apf28dev.dts
@@ -103,6 +103,7 @@
 
                 apbx@80040000 {
                         lradc@80050000 {
+                                fsl,lradc-touchscreen-wires = <4>;
                                 status = "okay";
                         };
 
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts
index 1594694532b9..94c4476972c3 100644
--- a/arch/arm/boot/dts/imx28-cfa10036.dts
+++ b/arch/arm/boot/dts/imx28-cfa10036.dts
@@ -45,6 +45,17 @@
                                         fsl,voltage = <1>;
                                         fsl,pull-up = <0>;
                                 };
+
+                                usb0_otg_cfa10036: otg-10036@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x0142 /* MX28_PAD_GPMI_READY0__USB0_ID */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
                         };
 
                         ssp0: ssp@80010000 {
@@ -58,12 +69,6 @@
                 };
 
                 apbx@80040000 {
-                        pwm: pwm@80064000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pwm4_pins_a>;
-                                status = "okay";
-                        };
-
                         duart: serial@80074000 {
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&duart_pins_b>;
@@ -73,15 +78,30 @@
                         i2c0: i2c@80058000 {
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&i2c0_pins_b>;
+                                clock-frequency = <400000>;
                                 status = "okay";
 
-                                ssd1307: oled@3c {
-                                        compatible = "solomon,ssd1307fb-i2c";
+                                ssd1306: oled@3c {
+                                        compatible = "solomon,ssd1306fb-i2c";
                                         reg = <0x3c>;
-                                        pwms = <&pwm 4 3000>;
                                         reset-gpios = <&gpio2 7 0>;
+                                        solomon,height = <32>;
+                                        solomon,width = <128>;
+                                        solomon,page-offset = <0>;
                                 };
                         };
+
+                        usbphy0: usbphy@8007c000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        ahb@80080000 {
+                usb0: usb@80080000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&usb0_otg_cfa10036>;
+                        status = "okay";
                 };
         };
 
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
index 063e62059890..04b2f769ffbd 100644
--- a/arch/arm/boot/dts/imx28-cfa10049.dts
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -33,7 +33,7 @@
                                                 0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */
                                                 0x1173 /* MX28_PAD_LCD_D22__GPIO_1_23 */
                                                 0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */
-                                                0x3173 /* MX28_PAD_LCD_RESET__GPIO_3_23 */
+                                                0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
                                         >;
                                         fsl,drive-strength = <0>;
                                         fsl,voltage = <1>;
@@ -166,8 +166,8 @@
 
                 apbx@80040000 {
                         pwm: pwm@80064000 {
-                                pinctrl-names = "default", "default";
-                                pinctrl-1 = <&pwm3_pins_b>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pwm3_pins_b>;
                                 status = "okay";
                         };
 
@@ -265,7 +265,7 @@
                 gpio-sck = <&gpio2 16 0>;
                 gpio-mosi = <&gpio2 17 0>;
                 gpio-miso = <&gpio2 18 0>;
-                cs-gpios = <&gpio3 23 0>;
+                cs-gpios = <&gpio3 5 0>;
                 num-chipselects = <1>;
                 #address-cells = <1>;
                 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/imx28-cfa10055.dts b/arch/arm/boot/dts/imx28-cfa10055.dts
new file mode 100644
index 000000000000..158111244122
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-cfa10055.dts
@@ -0,0 +1,179 @@
+/*
+ * Copyright 2013 Crystalfontz America, Inc.
+ *                                Free Electrons
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * The CFA-10055 is an expansion board for the CFA-10036 module and
+ * CFA-10037, thus we need to include the CFA-10037 DTS.
+ */
+/include/ "imx28-cfa10037.dts"
+
+/ {
+        model = "Crystalfontz CFA-10055 Board";
+        compatible = "crystalfontz,cfa10055", "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28";
+
+        apb@80000000 {
+                apbh@80000000 {
+                        pinctrl@80018000 {
+                                pinctrl-names = "default", "default";
+                                pinctrl-1 = <&hog_pins_cfa10055
+                                        &hog_pins_cfa10055_pullup>;
+
+                                hog_pins_cfa10055: hog-10055@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                hog_pins_cfa10055_pullup: hog-10055-pullup@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
+
+                                spi2_pins_cfa10055: spi2-cfa10055@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2103 /* MX28_PAD_SSP2_SCK__GPIO_2_16 */
+                                                0x2113 /* MX28_PAD_SSP2_CMD__GPIO_2_17 */
+                                                0x2123 /* MX28_PAD_SSP2_D0__GPIO_2_18 */
+                                        >;
+                                        fsl,drive-strength = <1>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
+
+                                lcdif_18bit_pins_cfa10055: lcdif-18bit@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
+                                                0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
+                                                0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
+                                                0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
+                                                0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
+                                                0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
+                                                0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
+                                                0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
+                                                0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
+                                                0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
+                                                0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
+                                                0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
+                                                0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
+                                                0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
+                                                0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
+                                                0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
+                                                0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
+                                                0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                lcdif_pins_cfa10055: lcdif-evk@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
+                                                0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
+                                                0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
+                                                0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                        };
+
+                        lcdif@80030000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&lcdif_18bit_pins_cfa10055
+                                             &lcdif_pins_cfa10055>;
+                                display = <&display>;
+                                status = "okay";
+
+                                display: display {
+                                        bits-per-pixel = <32>;
+                                        bus-width = <18>;
+
+                                        display-timings {
+                                                native-mode = <&timing0>;
+                                                timing0: timing0 {
+                                                        clock-frequency = <9216000>;
+                                                        hactive = <320>;
+                                                        vactive = <480>;
+                                                        hback-porch = <2>;
+                                                        hfront-porch = <2>;
+                                                        vback-porch = <2>;
+                                                        vfront-porch = <2>;
+                                                        hsync-len = <15>;
+                                                        vsync-len = <15>;
+                                                        hsync-active = <0>;
+                                                        vsync-active = <0>;
+                                                        de-active = <1>;
+                                                        pixelclk-active = <1>;
+                                                };
+                                        };
+                                };
+                        };
+                };
+
+                apbx@80040000 {
+                        lradc@80050000 {
+                                fsl,lradc-touchscreen-wires = <4>;
+                                status = "okay";
+                        };
+
+                        pwm: pwm@80064000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pwm3_pins_b>;
+                                status = "okay";
+                        };
+                };
+        };
+
+        spi2 {
+                compatible = "spi-gpio";
+                pinctrl-names = "default";
+                pinctrl-0 = <&spi2_pins_cfa10055>;
+                status = "okay";
+                gpio-sck = <&gpio2 16 0>;
+                gpio-mosi = <&gpio2 17 0>;
+                gpio-miso = <&gpio2 18 0>;
+                cs-gpios = <&gpio3 5 0>;
+                num-chipselects = <1>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                hx8357: hx8357@0 {
+                        compatible = "himax,hx8357b", "himax,hx8357";
+                        reg = <0>;
+                        spi-max-frequency = <100000>;
+                        spi-cpol;
+                        spi-cpha;
+                        gpios-reset = <&gpio3 30 0>;
+                };
+        };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 3 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx28-cfa10057.dts b/arch/arm/boot/dts/imx28-cfa10057.dts
new file mode 100644
index 000000000000..2da713cdb42a
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-cfa10057.dts
@@ -0,0 +1,191 @@
+/*
+ * Copyright 2013 Crystalfontz America, Inc.
+ * Copyright 2012 Free Electrons
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * The CFA-10057 is an expansion board for the CFA-10036 module, thus we
+ * need to include the CFA-10036 DTS.
+ */
+/include/ "imx28-cfa10036.dts"
+
+/ {
+        model = "Crystalfontz CFA-10057 Board";
+        compatible = "crystalfontz,cfa10057", "crystalfontz,cfa10036", "fsl,imx28";
+
+        apb@80000000 {
+                apbh@80000000 {
+                        pinctrl@80018000 {
+                                pinctrl-names = "default", "default";
+                                pinctrl-1 = <&hog_pins_cfa10057
+                                        &hog_pins_cfa10057_pullup>;
+
+                                hog_pins_cfa10057: hog-10057@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */
+                                                0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                hog_pins_cfa10057_pullup: hog-10057-pullup@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2133 /* MX28_PAD_SSP2_D3__GPIO_2_19 */
+                                                0x3183 /* MX28_PAD_I2C0_SCL__GPIO_3_24 */
+                                                0x3193 /* MX28_PAD_I2C0_SDA__GPIO_3_25 */
+                                                0x31a3 /* MX28_PAD_SAIF_SDATA0__GPIO_3_26 */
+                                                0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
+
+                                lcdif_18bit_pins_cfa10057: lcdif-18bit@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
+                                                0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
+                                                0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
+                                                0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
+                                                0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
+                                                0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
+                                                0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
+                                                0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
+                                                0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
+                                                0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
+                                                0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
+                                                0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
+                                                0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
+                                                0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
+                                                0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
+                                                0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
+                                                0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
+                                                0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                lcdif_pins_cfa10057: lcdif-evk@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
+                                                0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
+                                                0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
+                                                0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                        };
+
+                        lcdif@80030000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&lcdif_18bit_pins_cfa10057
+                                             &lcdif_pins_cfa10057>;
+                                display = <&display>;
+                                status = "okay";
+
+                                display: display {
+                                        bits-per-pixel = <32>;
+                                        bus-width = <18>;
+
+                                        display-timings {
+                                                native-mode = <&timing0>;
+                                                timing0: timing0 {
+                                                        clock-frequency = <30000000>;
+                                                        hactive = <480>;
+                                                        vactive = <800>;
+                                                        hfront-porch = <12>;
+                                                        hback-porch = <2>;
+                                                        vfront-porch = <5>;
+                                                        vback-porch = <3>;
+                                                        hsync-len = <2>;
+                                                        vsync-len = <2>;
+                                                        hsync-active = <0>;
+                                                        vsync-active = <0>;
+                                                        de-active = <1>;
+                                                        pixelclk-active = <1>;
+                                                };
+                                        };
+                                };
+                        };
+                };
+
+                apbx@80040000 {
+                        lradc@80050000 {
+                                fsl,lradc-touchscreen-wires = <4>;
+                                status = "okay";
+                        };
+
+                        pwm: pwm@80064000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pwm3_pins_b>;
+                                status = "okay";
+                        };
+
+                        i2c1: i2c@8005a000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&i2c1_pins_a>;
+                                status = "okay";
+                        };
+
+                        usbphy1: usbphy@8007e000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        ahb@80080000 {
+                usb1: usb@80090000 {
+                        vbus-supply = <&reg_usb1_vbus>;
+                        pinctrl-0 = <&usbphy1_pins_a>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+
+                reg_usb1_vbus: usb1_vbus {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio0 7 1>;
+                };
+        };
+
+        ahb@80080000 {
+                mac0: ethernet@800f0000 {
+                        phy-mode = "rmii";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mac0_pins_a>;
+                        phy-reset-gpios = <&gpio2 21 0>;
+                        phy-reset-duration = <100>;
+                        status = "okay";
+                };
+        };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 3 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <7>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index 5aa44e05c9f5..880df2f13be8 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -220,7 +220,19 @@
 
                         auart0: serial@8006a000 {
                                 pinctrl-names = "default";
-                                pinctrl-0 = <&auart0_2pins_a>;
+                                pinctrl-0 = <&auart0_pins_a>;
+                                status = "okay";
+                        };
+
+                        auart1: serial@8006c000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart1_pins_a>;
+                                status = "okay";
+                        };
+
+                        auart2: serial@8006e000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart2_2pins_b>;
                                 status = "okay";
                         };
                 };
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 600f7cb51f3e..195451bf7706 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -32,8 +32,12 @@
         };
 
         cpus {
-                cpu@0 {
-                        compatible = "arm,arm926ejs";
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                 };
         };
 
@@ -330,6 +334,17 @@
                                         fsl,pull-up = <0>;
                                 };
 
+                                auart2_2pins_b: auart2-2pins@1 {
+                                        reg = <1>;
+                                        fsl,pinmux-ids = <
+                                                0x3080 /* MX28_PAD_AUART2_RX__AUART2_RX */
+                                                0x3090 /* MX28_PAD_AUART2_TX__AUART2_TX */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
                                 auart3_pins_a: auart3@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
@@ -354,6 +369,28 @@
                                         fsl,pull-up = <0>;
                                 };
 
+                                auart3_2pins_b: auart3-2pins@1 {
+                                        reg = <1>;
+                                        fsl,pinmux-ids = <
+                                                0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
+                                                0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                auart4_2pins_a: auart4@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2181 /* MX28_PAD_SSP3_SCK__AUART4_TX */
+                                                0x2191 /* MX28_PAD_SSP3_MOSI__AUART4_RX */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
                                 mac0_pins_a: mac0@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
@@ -669,7 +706,7 @@
                         };
 
                         digctl@8001c000 {
-                                compatible = "fsl,imx28-digctl";
+                                compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
                                 reg = <0x8001c000 0x2000>;
                                 interrupts = <89>;
                                 status = "disabled";
diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts
index 2bcf6981d490..8f7f9ac0b989 100644
--- a/arch/arm/boot/dts/imx51-apf51.dts
+++ b/arch/arm/boot/dts/imx51-apf51.dts
@@ -45,6 +45,13 @@
         status = "okay";
 };
 
+&nfc {
+        nand-bus-width = <8>;
+        nand-ecc-mode = "hw";
+        nand-on-flash-bbt;
+        status = "okay";
+};
+
 &uart3 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart3_2>;
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 53fdde69bbf4..25764b505a61 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -175,10 +175,20 @@
                                 };
                         };
 
+                        usbphy0: usbphy@0 {
+                                compatible = "usb-nop-xceiv";
+                                clocks = <&clks 124>;
+                                clock-names = "main_clk";
+                                status = "okay";
+                        };
+
                         usbotg: usb@73f80000 {
                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
                                 reg = <0x73f80000 0x0200>;
                                 interrupts = <18>;
+                                clocks = <&clks 108>;
+                                fsl,usbmisc = <&usbmisc 0>;
+                                fsl,usbphy = <&usbphy0>;
                                 status = "disabled";
                         };
 
@@ -186,6 +196,8 @@
                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
                                 reg = <0x73f80200 0x0200>;
                                 interrupts = <14>;
+                                clocks = <&clks 108>;
+                                fsl,usbmisc = <&usbmisc 1>;
                                 status = "disabled";
                         };
 
@@ -193,6 +205,8 @@
                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
                                 reg = <0x73f80400 0x0200>;
                                 interrupts = <16>;
+                                clocks = <&clks 108>;
+                                fsl,usbmisc = <&usbmisc 2>;
                                 status = "disabled";
                         };
 
@@ -200,9 +214,18 @@
                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
                                 reg = <0x73f80600 0x0200>;
                                 interrupts = <17>;
+                                clocks = <&clks 108>;
+                                fsl,usbmisc = <&usbmisc 3>;
                                 status = "disabled";
                         };
 
+                        usbmisc: usbmisc@73f80800 {
+                                #index-cells = <1>;
+                                compatible = "fsl,imx51-usbmisc";
+                                reg = <0x73f80800 0x200>;
+                                clocks = <&clks 108>;
+                        };
+
                         gpio1: gpio@73f84000 {
                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
                                 reg = <0x73f84000 0x4000>;
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts
new file mode 100644
index 000000000000..7d304d02ed38
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-m53evk.dts
@@ -0,0 +1,259 @@
+/*
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx53.dtsi"
+
+/ {
+        model = "DENX M53EVK";
+        compatible = "denx,imx53-m53evk", "fsl,imx53";
+
+        memory {
+                reg = <0x70000000 0x20000000>;
+        };
+
+        soc {
+                display@di1 {
+                        compatible = "fsl,imx-parallel-display";
+                        crtcs = <&ipu 1>;
+                        interface-pix-fmt = "bgr666";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_ipu_disp2_1>;
+
+                        display-timings {
+                                800x480p60 {
+                                        native-mode;
+                                        clock-frequency = <31500000>;
+                                        hactive = <800>;
+                                        vactive = <480>;
+                                        hfront-porch = <40>;
+                                        hback-porch = <88>;
+                                        hsync-len = <128>;
+                                        vback-porch = <33>;
+                                        vfront-porch = <9>;
+                                        vsync-len = <3>;
+                                        vsync-active = <1>;
+                                };
+                        };
+                };
+        };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm1 0 3000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pin_gpio>;
+
+                user1 {
+                        label = "user1";
+                        gpios = <&gpio2 8 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+
+                user2 {
+                        label = "user2";
+                        gpios = <&gpio2 9 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+
+                reg_3p2v: 3p2v {
+                        compatible = "regulator-fixed";
+                        regulator-name = "3P2V";
+                        regulator-min-microvolt = <3200000>;
+                        regulator-max-microvolt = <3200000>;
+                        regulator-always-on;
+                };
+        };
+
+        sound {
+                compatible = "fsl,imx53-m53evk-sgtl5000",
+                             "fsl,imx-audio-sgtl5000";
+                model = "imx53-m53evk-sgtl5000";
+                ssi-controller = <&ssi2>;
+                audio-codec = <&sgtl5000>;
+                audio-routing =
+                        "MIC_IN", "Mic Jack",
+                        "Mic Jack", "Mic Bias",
+                        "LINE_IN", "Line In Jack",
+                        "Headphone Jack", "HP_OUT",
+                        "Ext Spk", "LINE_OUT";
+                mux-int-port = <2>;
+                mux-ext-port = <4>;
+        };
+};
+
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux_2>;
+        status = "okay";
+};
+
+&can1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_can1_3>;
+        status = "okay";
+};
+
+&can2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_can2_1>;
+        status = "okay";
+};
+
+&esdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc1_1>;
+        cd-gpios = <&gpio1 1 0>;
+        wp-gpios = <&gpio1 9 0>;
+        status = "okay";
+};
+
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec_1>;
+        phy-mode = "rmii";
+        status = "okay";
+};
+
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1_2>;
+        status = "okay";
+
+        sgtl5000: codec@0a {
+                compatible = "fsl,sgtl5000";
+                reg = <0x0a>;
+                VDDA-supply = <&reg_3p2v>;
+                VDDIO-supply = <&reg_3p2v>;
+                clocks = <&clks 150>;
+        };
+};
+
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2_2>;
+        clock-frequency = <400000>;
+        status = "okay";
+
+        stmpe610@41 {
+                compatible = "st,stmpe610";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x41>;
+                id = <0>;
+                blocks = <0x5>;
+                interrupts = <6 0x0>;
+                interrupt-parent = <&gpio7>;
+                irq-trigger = <0x1>;
+
+                stmpe_touchscreen {
+                        compatible = "stmpe,ts";
+                        reg = <0>;
+                        ts,sample-time = <4>;
+                        ts,mod-12b = <1>;
+                        ts,ref-sel = <0>;
+                        ts,adc-freq = <1>;
+                        ts,ave-ctrl = <3>;
+                        ts,touch-det-delay = <3>;
+                        ts,settling = <4>;
+                        ts,fraction-z = <7>;
+                        ts,i-drive = <1>;
+                };
+        };
+
+        eeprom: eeprom@50 {
+                compatible = "atmel,24c128";
+                reg = <0x50>;
+                pagesize = <32>;
+        };
+
+        rtc: rtc@68 {
+                compatible = "stm,m41t62";
+                reg = <0x68>;
+        };
+};
+
+&i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3_1>;
+        status = "okay";
+};
+
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+
+        hog {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK       0x80000000
+                                MX53_PAD_EIM_EB3__GPIO2_31              0x80000000
+                                MX53_PAD_PATA_DA_0__GPIO7_6             0x80000000
+                                MX53_PAD_DISP0_DAT8__PWM1_PWMO          0x5
+
+                        >;
+                };
+
+                led_pin_gpio: led_gpio@0 {
+                        fsl,pins = <
+                                MX53_PAD_PATA_DATA8__GPIO2_8            0x80000000
+                                MX53_PAD_PATA_DATA9__GPIO2_9            0x80000000
+                        >;
+                };
+        };
+};
+
+&nfc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_nand_1>;
+        nand-bus-width = <8>;
+        nand-ecc-mode = "hw";
+        status = "okay";
+};
+
+&pwm1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm1_1>;
+        status = "okay";
+};
+
+&ssi2 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1_2>;
+        status = "okay";
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2_1>;
+        status = "okay";
+};
+
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3_1>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts
index 445a01119cc5..aaa33bc99f78 100644
--- a/arch/arm/boot/dts/imx53-mba53.dts
+++ b/arch/arm/boot/dts/imx53-mba53.dts
@@ -16,27 +16,81 @@
 / {
         model = "TQ MBa53 starter kit";
         compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
+
+        reg_backlight: fixed@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "lcd-supply";
+                gpio = <&gpio2 5 0>;
+                startup-delay-us = <5000>;
+                enable-active-low;
+        };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm2 0 50000 0 0>;
+                brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>;
+                default-brightness-level = <10>;
+                enable-gpios = <&gpio7 7 0>;
+                power-supply = <&reg_backlight>;
+        };
+
+        disp1: display@disp1 {
+                compatible = "fsl,imx-parallel-display";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_disp1_1>;
+                crtcs = <&ipu 1>;
+                interface-pix-fmt = "rgb24";
+                status = "disabled";
+        };
+
+        reg_3p2v: 3p2v {
+                compatible = "regulator-fixed";
+                regulator-name = "3P2V";
+                regulator-min-microvolt = <3200000>;
+                regulator-max-microvolt = <3200000>;
+                regulator-always-on;
+        };
+
+        sound {
+                compatible = "tq,imx53-mba53-sgtl5000",
+                             "fsl,imx-audio-sgtl5000";
+                model = "imx53-mba53-sgtl5000";
+                ssi-controller = <&ssi2>;
+                audio-codec = <&codec>;
+                audio-routing =
+                        "MIC_IN", "Mic Jack",
+                        "Mic Jack", "Mic Bias",
+                        "Headphone Jack", "HP_OUT";
+                mux-int-port = <2>;
+                mux-ext-port = <5>;
+        };
+};
+
+&ldb {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_lvds1_1>;
+        status = "disabled";
 };
 
 &iomuxc {
         lvds1 {
                 pinctrl_lvds1_1: lvds1-grp1 {
                         fsl,pins = <
-                                MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x10000
-                                MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x10000
-                                MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x10000
-                                MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x10000
-                                MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x10000
+                                MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
+                                MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
+                                MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
+                                MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
+                                MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
                         >;
                 };
 
                 pinctrl_lvds1_2: lvds1-grp2 {
                         fsl,pins = <
-                                MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x10000
-                                MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x10000
-                                MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x10000
-                                MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x10000
-                                MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x10000
+                                MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
+                                MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
+                                MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
+                                MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
+                                MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
                         >;
                 };
         };
@@ -44,33 +98,44 @@
         disp1 {
                 pinctrl_disp1_1: disp1-grp1 {
                         fsl,pins = <
-                                MX53_PAD_EIM_DA10__IPU_DI1_PIN15   0x10000 /* DISP1_DRDY */
-                                MX53_PAD_EIM_D23__IPU_DI1_PIN2     0x10000 /* DISP1_HSYNC */
-                                MX53_PAD_EIM_EB3__IPU_DI1_PIN3     0x10000 /* DISP1_VSYNC */
-                                MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x10000
-                                MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x10000
-                                MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x10000
-                                MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x10000
-                                MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x10000
-                                MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x10000
-                                MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x10000
-                                MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x10000
-                                MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x10000
-                                MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x10000
-                                MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x10000
-                                MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x10000
-                                MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x10000
-                                MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x10000
-                                MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9  0x10000
-                                MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8  0x10000
-                                MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7  0x10000
-                                MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6  0x10000
-                                MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5  0x10000
-                                MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4  0x10000
-                                MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3  0x10000
-                                MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2  0x10000
-                                MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1  0x10000
-                                MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0  0x10000
+                                MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */
+                                MX53_PAD_EIM_DA10__IPU_DI1_PIN15   0x80000000 /* DISP1_DRDY */
+                                MX53_PAD_EIM_D23__IPU_DI1_PIN2     0x80000000 /* DISP1_HSYNC */
+                                MX53_PAD_EIM_EB3__IPU_DI1_PIN3     0x80000000 /* DISP1_VSYNC */
+                                MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000
+                                MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000
+                                MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000
+                                MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000
+                                MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000
+                                MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000
+                                MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000
+                                MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000
+                                MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000
+                                MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000
+                                MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000
+                                MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000
+                                MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000
+                                MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000
+                                MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9  0x80000000
+                                MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8  0x80000000
+                                MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7  0x80000000
+                                MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6  0x80000000
+                                MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5  0x80000000
+                                MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4  0x80000000
+                                MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3  0x80000000
+                                MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2  0x80000000
+                                MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1  0x80000000
+                                MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0  0x80000000
+                        >;
+                };
+        };
+
+        tve {
+                pinctrl_vga_sync_1: vgasync-grp1 {
+                        fsl,pins = <
+                                /* VGA_VSYNC, HSYNC with max drive strength */
+                                MX53_PAD_EIM_CS1__IPU_DI1_PIN6     0xe6
+                                MX53_PAD_EIM_DA15__IPU_DI1_PIN4    0xe6
                         >;
                 };
         };
@@ -80,16 +145,27 @@
         status = "okay";
 };
 
+&audmux {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux_1>;
+};
+
 &i2c2 {
         codec: sgtl5000@a {
                 compatible = "fsl,sgtl5000";
                 reg = <0x0a>;
+                clocks = <&clks 150>;
+                VDDA-supply = <&reg_3p2v>;
+                VDDIO-supply = <&reg_3p2v>;
         };
 
         expander: pca9554@20 {
                 compatible = "pca9554";
                 reg = <0x20>;
                 interrupts = <109>;
+                #gpio-cells = <2>;
+                gpio-controller;
         };
 
         sensor2: lm75@49 {
@@ -99,6 +175,7 @@
 };
 
 &fec {
+        phy-reset-gpios = <&gpio7 6 0>;
         status = "okay";
 };
 
@@ -114,10 +191,24 @@
         status = "okay";
 };
 
+&usbotg {
+        dr_mode = "host";
+        status = "okay";
+};
+
+&usbh1 {
+        status = "okay";
+};
+
 &uart1 {
         status = "okay";
 };
 
+&ssi2 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+
 &uart2 {
         status = "okay";
 };
@@ -133,3 +224,13 @@
 &i2c3 {
         status = "okay";
 };
+
+&tve {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_vga_sync_1>;
+        ddc = <&i2c3>;
+        fsl,tve-mode = "vga";
+        fsl,hsync-pin = <4>;
+        fsl,vsync-pin = <6>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index 8f0e9ae0e3e6..512a1f608253 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -21,6 +21,33 @@
                 reg = <0x70000000 0x40000000>;
         };
 
+        display@di0 {
+                compatible = "fsl,imx-parallel-display";
+                crtcs = <&ipu 0>;
+                interface-pix-fmt = "rgb565";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_ipu_disp0_1>;
+                status = "disabled";
+                display-timings {
+                        claawvga {
+                                native-mode;
+                                clock-frequency = <27000000>;
+                                hactive = <800>;
+                                vactive = <480>;
+                                hback-porch = <40>;
+                                hfront-porch = <60>;
+                                vback-porch = <10>;
+                                vfront-porch = <10>;
+                                hsync-len = <20>;
+                                vsync-len = <10>;
+                                hsync-active = <0>;
+                                vsync-active = <0>;
+                                de-active = <1>;
+                                pixelclk-active = <0>;
+                        };
+                };
+        };
+
         gpio-keys {
                 compatible = "gpio-keys";
 
@@ -147,6 +174,7 @@
                 reg = <0x0a>;
                 VDDA-supply = <&reg_3p2v>;
                 VDDIO-supply = <&reg_3p2v>;
+                clocks = <&clks 150>;
         };
 };
 
@@ -268,3 +296,11 @@
         phy-reset-gpios = <&gpio7 6 0>;
         status = "okay";
 };
+
+&usbh1 {
+       status = "okay";
+};
+
+&usbotg {
+       status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi
index 38bed3ed7c1a..abd72af545bf 100644
--- a/arch/arm/boot/dts/imx53-tqma53.dtsi
+++ b/arch/arm/boot/dts/imx53-tqma53.dtsi
@@ -35,7 +35,9 @@
 
 &esdhc2 {
         pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_esdhc2_1>;
+        pinctrl-0 = <&pinctrl_esdhc2_1>,
+                    <&pinctrl_tqma53_esdhc2_2>;
+        vmmc-supply = <&reg_3p3v>;
         wp-gpios = <&gpio1 2 0>;
         cd-gpios = <&gpio1 4 0>;
         status = "disabled";
@@ -69,14 +71,22 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_hog>;
 
+        esdhc2_2 {
+                pinctrl_tqma53_esdhc2_2: esdhc2-tqma53-grp2 {
+                        fsl,pins = <
+                                MX53_PAD_GPIO_4__GPIO1_4        0x80000000 /* SD2_CD */
+                                MX53_PAD_GPIO_2__GPIO1_2        0x80000000 /* SD2_WP */
+                        >;
+                };
+        };
+
         i2s {
                 pinctrl_i2s_1: i2s-grp1 {
                         fsl,pins = <
-                                 MX53_PAD_GPIO_19__GPIO4_5           0x10000 /* I2S_MCLK */
-                                 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC  0x10000 /* I2S_SCLK */
-                                 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD  0x10000 /* I2S_DOUT */
-                                 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x10000 /* I2S_LRCLK */
-                                 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD  0x10000 /* I2S_DIN */
+                                 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC  0x80000000 /* I2S_SCLK */
+                                 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD  0x80000000 /* I2S_DOUT */
+                                 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 /* I2S_LRCLK */
+                                 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD  0x80000000 /* I2S_DIN */
                         >;
                 };
         };
@@ -84,16 +94,17 @@
         hog {
                 pinctrl_hog: hoggrp {
                         fsl,pins = <
-                                 MX53_PAD_EIM_CS1__IPU_DI1_PIN6  0x10000 /* VSYNC */
-                                 MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0x10000 /* HSYNC */
-                                 MX53_PAD_PATA_DA_1__GPIO7_7     0x10000 /* LCD_BLT_EN */
-                                 MX53_PAD_PATA_DA_2__GPIO7_8     0x10000 /* LCD_RESET */
-                                 MX53_PAD_PATA_DATA5__GPIO2_5    0x10000 /* LCD_POWER */
-                                 MX53_PAD_PATA_DATA6__GPIO2_6    0x10000 /* PMIC_INT */
-                                 MX53_PAD_PATA_DATA14__GPIO2_14  0x10000 /* CSI_RST */
-                                 MX53_PAD_PATA_DATA15__GPIO2_15  0x10000 /* CSI_PWDN */
-                                 MX53_PAD_GPIO_0__GPIO1_0        0x10000 /* SYSTEM_DOWN */
-                                 MX53_PAD_GPIO_3__GPIO1_3        0x10000
+                                 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */
+                                 MX53_PAD_PATA_DA_1__GPIO7_7     0x80000000 /* LCD_BLT_EN */
+                                 MX53_PAD_PATA_DA_2__GPIO7_8     0x80000000 /* LCD_RESET */
+                                 MX53_PAD_PATA_DATA5__GPIO2_5    0x80000000 /* LCD_POWER */
+                                 MX53_PAD_PATA_DATA6__GPIO2_6    0x80000000 /* PMIC_INT */
+                                 MX53_PAD_PATA_DATA14__GPIO2_14  0x80000000 /* CSI_RST */
+                                 MX53_PAD_PATA_DATA15__GPIO2_15  0x80000000 /* CSI_PWDN */
+                                 MX53_PAD_GPIO_19__GPIO4_5       0x80000000 /* #SYSTEM_DOWN */
+                                 MX53_PAD_GPIO_3__GPIO1_3        0x80000000
+                                 MX53_PAD_PATA_DA_0__GPIO7_6     0x80000000 /* #PHY_RESET */
+                                 MX53_PAD_GPIO_1__PWM2_PWMO      0x80000000 /* LCD_CONTRAST */
                         >;
                 };
         };
@@ -149,7 +160,7 @@
                 reg = <0x8>;
                 fsl,mc13xxx-uses-rtc;
                 interrupt-parent = <&gpio2>;
-                interrupts = <6 8>; /* PDATA_DATA6, low active */
+                interrupts = <6 4>; /* PATA_DATA6, active high */
         };
 
         sensor1: lm75@48 {
diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi
new file mode 100644
index 000000000000..f494766700a3
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-tx53.dtsi
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "imx53.dtsi"
+
+/ {
+        model = "Ka-Ro TX53";
+        compatible = "karo,tx53", "fsl,imx53";
+
+        memory {
+                reg = <0x70000000 0x40000000>; /* Up to 1GiB */
+        };
+
+        regulators {
+                compatible = "simple-bus";
+
+                reg_3p3v: 3p3v {
+                        compatible = "regulator-fixed";
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+        };
+};
+
+&can1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_can1_2>;
+        status = "disabled";
+};
+
+&can2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_can2_1>;
+        status = "disabled";
+};
+
+&ecspi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi1_2>;
+        status = "disabled";
+};
+
+&esdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc1_2>;
+        status = "disabled";
+};
+
+&esdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc2_1>;
+        status = "disabled";
+};
+
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec_1>;
+        phy-mode = "rmii";
+        status = "disabled";
+};
+
+&i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3_2>;
+        status = "disabled";
+};
+
+&owire {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_owire_1>;
+        status = "disabled";
+};
+
+&pwm2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm2_1>;
+        status = "disabled";
+};
+
+&ssi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux_1>;
+        status = "disabled";
+};
+
+&ssi2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux_2>;
+        status = "disabled";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1_2>,
+                    <&pinctrl_uart1_3>;
+        fsl,uart-has-rtscts;
+        status = "disabled";
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2_2>;
+        fsl,uart-has-rtscts;
+        status = "disabled";
+};
+
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3_1>;
+        fsl,uart-has-rtscts;
+        status = "disabled";
+};
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index eb83aa039b8b..3895fbba8fce 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -27,6 +27,9 @@
                 gpio4 = &gpio5;
                 gpio5 = &gpio6;
                 gpio6 = &gpio7;
+                i2c0 = &i2c1;
+                i2c1 = &i2c2;
+                i2c2 = &i2c3;
         };
 
         tzic: tz-interrupt-controller@0fffc000 {
@@ -163,10 +166,27 @@
                                 };
                         };
 
+                        usbphy0: usbphy@0 {
+                                compatible = "usb-nop-xceiv";
+                                clocks = <&clks 124>;
+                                clock-names = "main_clk";
+                                status = "okay";
+                        };
+
+                        usbphy1: usbphy@1 {
+                                compatible = "usb-nop-xceiv";
+                                clocks = <&clks 125>;
+                                clock-names = "main_clk";
+                                status = "okay";
+                        };
+
                         usbotg: usb@53f80000 {
                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
                                 reg = <0x53f80000 0x0200>;
                                 interrupts = <18>;
+                                clocks = <&clks 108>;
+                                fsl,usbmisc = <&usbmisc 0>;
+                                fsl,usbphy = <&usbphy0>;
                                 status = "disabled";
                         };
 
@@ -174,6 +194,9 @@
                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
                                 reg = <0x53f80200 0x0200>;
                                 interrupts = <14>;
+                                clocks = <&clks 108>;
+                                fsl,usbmisc = <&usbmisc 1>;
+                                fsl,usbphy = <&usbphy1>;
                                 status = "disabled";
                         };
 
@@ -181,6 +204,8 @@
                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
                                 reg = <0x53f80400 0x0200>;
                                 interrupts = <16>;
+                                clocks = <&clks 108>;
+                                fsl,usbmisc = <&usbmisc 2>;
                                 status = "disabled";
                         };
 
@@ -188,9 +213,18 @@
                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
                                 reg = <0x53f80600 0x0200>;
                                 interrupts = <17>;
+                                clocks = <&clks 108>;
+                                fsl,usbmisc = <&usbmisc 3>;
                                 status = "disabled";
                         };
 
+                        usbmisc: usbmisc@53f80800 {
+                                #index-cells = <1>;
+                                compatible = "fsl,imx53-usbmisc";
+                                reg = <0x53f80800 0x200>;
+                                clocks = <&clks 108>;
+                        };
+
                         gpio1: gpio@53f84000 {
                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
                                 reg = <0x53f84000 0x4000>;
@@ -267,6 +301,24 @@
                                                         MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD  0x80000000
                                                 >;
                                         };
+
+                                        pinctrl_audmux_2: audmuxgrp-2 {
+                                                fsl,pins = <
+                                                        MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC     0x80000000
+                                                        MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD     0x80000000
+                                                        MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS    0x80000000
+                                                        MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD     0x80000000
+                                                >;
+                                        };
+
+                                        pinctrl_audmux_3: audmuxgrp-3 {
+                                                fsl,pins = <
+                                                        MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC     0x80000000
+                                                        MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD     0x80000000
+                                                        MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS    0x80000000
+                                                        MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD     0x80000000
+                                                >;
+                                        };
                                 };
 
                                 fec {
@@ -284,6 +336,29 @@
                                                         MX53_PAD_FEC_TXD0__FEC_TDATA_0   0x80000000
                                                 >;
                                         };
+
+                                        pinctrl_fec_2: fecgrp-2 {
+                                                fsl,pins = <
+                                                        MX53_PAD_FEC_MDC__FEC_MDC        0x80000000
+                                                        MX53_PAD_FEC_MDIO__FEC_MDIO      0x80000000
+                                                        MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
+                                                        MX53_PAD_FEC_RX_ER__FEC_RX_ER    0x80000000
+                                                        MX53_PAD_FEC_CRS_DV__FEC_RX_DV   0x80000000
+                                                        MX53_PAD_FEC_RXD1__FEC_RDATA_1   0x80000000
+                                                        MX53_PAD_FEC_RXD0__FEC_RDATA_0   0x80000000
+                                                        MX53_PAD_FEC_TX_EN__FEC_TX_EN    0x80000000
+                                                        MX53_PAD_FEC_TXD1__FEC_TDATA_1   0x80000000
+                                                        MX53_PAD_FEC_TXD0__FEC_TDATA_0   0x80000000
+                                                        MX53_PAD_KEY_ROW1__FEC_COL       0x80000000
+                                                        MX53_PAD_KEY_COL3__FEC_CRS       0x80000000
+                                                        MX53_PAD_KEY_COL2__FEC_RDATA_2   0x80000000
+                                                        MX53_PAD_KEY_COL0__FEC_RDATA_3   0x80000000
+                                                        MX53_PAD_KEY_COL1__FEC_RX_CLK    0x80000000
+                                                        MX53_PAD_KEY_ROW2__FEC_TDATA_2   0x80000000
+                                                        MX53_PAD_GPIO_19__FEC_TDATA_3    0x80000000
+                                                        MX53_PAD_KEY_ROW0__FEC_TX_ER     0x80000000
+                                                >;
+                                        };
                                 };
 
                                 csi {
@@ -312,6 +387,22 @@
                                                         MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK   0x1d5
                                                 >;
                                         };
+
+                                        pinctrl_csi_2: csigrp-2 {
+                                                fsl,pins = <
+                                                        MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC     0x1d5
+                                                        MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC      0x1d5
+                                                        MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK   0x1d5
+                                                        MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19      0x1d5
+                                                        MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18      0x1d5
+                                                        MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17      0x1d5
+                                                        MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16      0x1d5
+                                                        MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15      0x1d5
+                                                        MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14      0x1d5
+                                                        MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13      0x1d5
+                                                        MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12      0x1d5
+                                                >;
+                                        };
                                 };
 
                                 cspi {
@@ -322,6 +413,14 @@
                                                         MX53_PAD_SD1_CLK__CSPI_SCLK   0x1d5
                                                 >;
                                         };
+
+                                        pinctrl_cspi_2: cspigrp-2 {
+                                                fsl,pins = <
+                                                        MX53_PAD_EIM_D22__CSPI_MISO 0x1d5
+                                                        MX53_PAD_EIM_D28__CSPI_MOSI 0x1d5
+                                                        MX53_PAD_EIM_D21__CSPI_SCLK 0x1d5
+                                                >;
+                                        };
                                 };
 
                                 ecspi1 {
@@ -332,6 +431,27 @@
                                                         MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
                                                 >;
                                         };
+
+                                        pinctrl_ecspi1_2: ecspi1grp-2 {
+                                                fsl,pins = <
+                                                        MX53_PAD_GPIO_19__ECSPI1_RDY    0x80000000
+                                                        MX53_PAD_EIM_EB2__ECSPI1_SS0    0x80000000
+                                                        MX53_PAD_EIM_D16__ECSPI1_SCLK   0x80000000
+                                                        MX53_PAD_EIM_D17__ECSPI1_MISO   0x80000000
+                                                        MX53_PAD_EIM_D18__ECSPI1_MOSI   0x80000000
+                                                        MX53_PAD_EIM_D19__ECSPI1_SS1    0x80000000
+                                                >;
+                                        };
+                                };
+
+                                ecspi2 {
+                                        pinctrl_ecspi2_1: ecspi2grp-1 {
+                                                fsl,pins = <
+                                                        MX53_PAD_EIM_OE__ECSPI2_MISO  0x80000000
+                                                        MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x80000000
+                                                        MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x80000000
+                                                >;
+                                        };
                                 };
 
                                 esdhc1 {
@@ -406,6 +526,13 @@
                                                         MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
                                                 >;
                                         };
+
+                                        pinctrl_can1_3: can1grp-3 {
+                                                fsl,pins = <
+                                                        MX53_PAD_GPIO_7__CAN1_TXCAN     0x80000000
+                                                        MX53_PAD_GPIO_8__CAN1_RXCAN     0x80000000
+                                                >;
+                                        };
                                 };
 
                                 can2 {
@@ -424,6 +551,13 @@
                                                         MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
                                                 >;
                                         };
+
+                                        pinctrl_i2c1_2: i2c1grp-2 {
+                                                fsl,pins = <
+                                                        MX53_PAD_EIM_D21__I2C1_SCL      0xc0000000
+                                                        MX53_PAD_EIM_D28__I2C1_SDA      0xc0000000
+                                                >;
+                                        };
                                 };
 
                                 i2c2 {
@@ -433,6 +567,13 @@
                                                         MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
                                                 >;
                                         };
+
+                                        pinctrl_i2c2_2: i2c2grp-2 {
+                                                fsl,pins = <
+                                                        MX53_PAD_EIM_D16__I2C2_SDA      0xc0000000
+                                                        MX53_PAD_EIM_EB2__I2C2_SCL      0xc0000000
+                                                >;
+                                        };
                                 };
 
                                 i2c3 {
@@ -444,6 +585,119 @@
                                         };
                                 };
 
+                                ipu_disp0 {
+                                        pinctrl_ipu_disp0_1: ipudisp0grp-1 {
+                                                fsl,pins = <
+                                                MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
+                                                MX53_PAD_DI0_PIN15__IPU_DI0_PIN15               0x5
+                                                MX53_PAD_DI0_PIN2__IPU_DI0_PIN2         0x5
+                                                MX53_PAD_DI0_PIN3__IPU_DI0_PIN3                 0x5
+                                                MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0            0x5
+                                                MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1            0x5
+                                                MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2            0x5
+                                                MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3            0x5
+                                                MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4            0x5
+                                                MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5            0x5
+                                                MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6            0x5
+                                                MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7            0x5
+                                                MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8            0x5
+                                                MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9            0x5
+                                                MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10          0x5
+                                                MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11          0x5
+                                                MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12          0x5
+                                                MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13          0x5
+                                                MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14          0x5
+                                                MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15          0x5
+                                                MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16          0x5
+                                                MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17          0x5
+                                                MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18          0x5
+                                                MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19          0x5
+                                                MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20          0x5
+                                                MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21          0x5
+                                                MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22          0x5
+                                                MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23          0x5
+                                                >;
+                                        };
+                                };
+
+                                ipu_disp1 {
+                                        pinctrl_ipu_disp1_1: ipudisp1grp-1 {
+                                                fsl,pins = <
+                                                        MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0       0x5
+                                                        MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1       0x5
+                                                        MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2       0x5
+                                                        MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3       0x5
+                                                        MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4       0x5
+                                                        MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5       0x5
+                                                        MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6       0x5
+                                                        MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7       0x5
+                                                        MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8       0x5
+                                                        MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9       0x5
+                                                        MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10      0x5
+                                                        MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11      0x5
+                                                        MX53_PAD_EIM_A17__IPU_DISP1_DAT_12      0x5
+                                                        MX53_PAD_EIM_A18__IPU_DISP1_DAT_13      0x5
+                                                        MX53_PAD_EIM_A19__IPU_DISP1_DAT_14      0x5
+                                                        MX53_PAD_EIM_A20__IPU_DISP1_DAT_15      0x5
+                                                        MX53_PAD_EIM_A21__IPU_DISP1_DAT_16      0x5
+                                                        MX53_PAD_EIM_A22__IPU_DISP1_DAT_17      0x5
+                                                        MX53_PAD_EIM_A23__IPU_DISP1_DAT_18      0x5
+                                                        MX53_PAD_EIM_A24__IPU_DISP1_DAT_19      0x5
+                                                        MX53_PAD_EIM_D31__IPU_DISP1_DAT_20      0x5
+                                                        MX53_PAD_EIM_D30__IPU_DISP1_DAT_21      0x5
+                                                        MX53_PAD_EIM_D26__IPU_DISP1_DAT_22      0x5
+                                                        MX53_PAD_EIM_D27__IPU_DISP1_DAT_23      0x5
+                                                        MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK      0x5
+                                                        MX53_PAD_EIM_DA13__IPU_DI1_D0_CS        0x5
+                                                        MX53_PAD_EIM_DA14__IPU_DI1_D1_CS        0x5
+                                                        MX53_PAD_EIM_DA15__IPU_DI1_PIN1         0x5
+                                                        MX53_PAD_EIM_DA11__IPU_DI1_PIN2         0x5
+                                                        MX53_PAD_EIM_DA12__IPU_DI1_PIN3         0x5
+                                                        MX53_PAD_EIM_A25__IPU_DI1_PIN12         0x5
+                                                        MX53_PAD_EIM_DA10__IPU_DI1_PIN15        0x5
+                                                >;
+                                        };
+                                };
+
+                                ipu_disp2 {
+                                        pinctrl_ipu_disp2_1: ipudisp2grp-1 {
+                                                fsl,pins = <
+                                                        MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0     0x80000000
+                                                        MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1     0x80000000
+                                                        MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2     0x80000000
+                                                        MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3     0x80000000
+                                                        MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK     0x80000000
+                                                        MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0     0x80000000
+                                                        MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1     0x80000000
+                                                        MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2     0x80000000
+                                                        MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3     0x80000000
+                                                        MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK     0x80000000
+                                                >;
+                                        };
+                                };
+
+                                nand {
+                                        pinctrl_nand_1: nandgrp-1 {
+                                                fsl,pins = <
+                                                        MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B     0x4
+                                                        MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B     0x4
+                                                        MX53_PAD_NANDF_CLE__EMI_NANDF_CLE       0x4
+                                                        MX53_PAD_NANDF_ALE__EMI_NANDF_ALE       0x4
+                                                        MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B     0xe0
+                                                        MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0      0xe0
+                                                        MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0      0x4
+                                                        MX53_PAD_PATA_DATA0__EMI_NANDF_D_0      0xa4
+                                                        MX53_PAD_PATA_DATA1__EMI_NANDF_D_1      0xa4
+                                                        MX53_PAD_PATA_DATA2__EMI_NANDF_D_2      0xa4
+                                                        MX53_PAD_PATA_DATA3__EMI_NANDF_D_3      0xa4
+                                                        MX53_PAD_PATA_DATA4__EMI_NANDF_D_4      0xa4
+                                                        MX53_PAD_PATA_DATA5__EMI_NANDF_D_5      0xa4
+                                                        MX53_PAD_PATA_DATA6__EMI_NANDF_D_6      0xa4
+                                                        MX53_PAD_PATA_DATA7__EMI_NANDF_D_7      0xa4
+                                                >;
+                                        };
+                                };
+
                                 owire {
                                         pinctrl_owire_1: owiregrp-1 {
                                                 fsl,pins = <
@@ -452,6 +706,22 @@
                                         };
                                 };
 
+                                pwm1 {
+                                        pinctrl_pwm1_1: pwm1grp-1 {
+                                                fsl,pins = <
+                                                        MX53_PAD_DISP0_DAT8__PWM1_PWMO  0x5
+                                                >;
+                                        };
+                                };
+
+                                pwm2 {
+                                        pinctrl_pwm2_1: pwm2grp-1 {
+                                                fsl,pins = <
+                                                        MX53_PAD_GPIO_1__PWM2_PWMO      0x80000000
+                                                >;
+                                        };
+                                };
+
                                 uart1 {
                                         pinctrl_uart1_1: uart1grp-1 {
                                                 fsl,pins = <
@@ -466,6 +736,13 @@
                                                         MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5
                                                 >;
                                         };
+
+                                        pinctrl_uart1_3: uart1grp-3 {
+                                                fsl,pins = <
+                                                        MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5
+                                                        MX53_PAD_PATA_IORDY__UART1_RTS   0x1c5
+                                                >;
+                                        };
                                 };
 
                                 uart2 {
@@ -475,6 +752,15 @@
                                                         MX53_PAD_PATA_DMARQ__UART2_TXD_MUX     0x1c5
                                                 >;
                                         };
+
+                                        pinctrl_uart2_2: uart2grp-2 {
+                                                fsl,pins = <
+                                                        MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX  0x1c5
+                                                        MX53_PAD_PATA_DMARQ__UART2_TXD_MUX      0x1c5
+                                                        MX53_PAD_PATA_DIOR__UART2_RTS           0x1c5
+                                                        MX53_PAD_PATA_INTRQ__UART2_CTS          0x1c5
+                                                >;
+                                        };
                                 };
 
                                 uart3 {
@@ -513,7 +799,6 @@
                                                 >;
                                         };
                                 };
-
                         };
 
                         gpr: iomuxc-gpr@53fa8000 {
@@ -781,6 +1066,16 @@
                                 clock-names = "ipg", "ahb", "ptp";
                                 status = "disabled";
                         };
+
+                        tve: tve@63ff0000 {
+                                compatible = "fsl,imx53-tve";
+                                reg = <0x63ff0000 0x1000>;
+                                interrupts = <92>;
+                                clocks = <&clks 69>, <&clks 116>;
+                                clock-names = "tve", "di_sel";
+                                crtcs = <&ipu 1>;
+                                status = "disabled";
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/imx6dl-sabreauto.dts
index 7adcec360213..95da71185a4a 100644
--- a/arch/arm/boot/dts/imx6dl-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6dl-sabreauto.dts
@@ -28,4 +28,12 @@
                         >;
                 };
         };
+
+        ecspi1 {
+                pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
+                        fsl,pins = <
+                                MX6DL_PAD_EIM_D19__GPIO3_IO19  0x80000000
+                        >;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/imx6dl-sabresd.dts
index 7efb05db4783..8989df2b89e5 100644
--- a/arch/arm/boot/dts/imx6dl-sabresd.dts
+++ b/arch/arm/boot/dts/imx6dl-sabresd.dts
@@ -29,6 +29,7 @@
                                 MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
                                 MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
                                 MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
+                                MX6DL_PAD_GPIO_0__CCM_CLKO1    0x130b0
                         >;
                 };
         };
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 5bcdf3a90bb3..2b3ecd679350 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -18,12 +18,14 @@
 
                 cpu@0 {
                         compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                         reg = <0>;
                         next-level-cache = <&L2>;
                 };
 
                 cpu@1 {
                         compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                         reg = <1>;
                         next-level-cache = <&L2>;
                 };
@@ -35,6 +37,27 @@
                                 compatible = "fsl,imx6dl-iomuxc";
                                 reg = <0x020e0000 0x4000>;
 
+                                audmux {
+                                        pinctrl_audmux_2: audmux-2 {
+                                                fsl,pins = <
+                                                        MX6DL_PAD_CSI0_DAT7__AUD3_RXD  0x80000000
+                                                        MX6DL_PAD_CSI0_DAT4__AUD3_TXC  0x80000000
+                                                        MX6DL_PAD_CSI0_DAT5__AUD3_TXD  0x80000000
+                                                        MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
+                                                >;
+                                        };
+                                };
+
+                                ecspi1 {
+                                        pinctrl_ecspi1_1: ecspi1grp-1 {
+                                                fsl,pins = <
+                                                        MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+                                                        MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+                                                        MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+                                                >;
+                                        };
+                                };
+
                                 enet {
                                         pinctrl_enet_1: enetgrp-1 {
                                                 fsl,pins = <
@@ -78,6 +101,39 @@
                                         };
                                 };
 
+                                gpmi-nand {
+                                        pinctrl_gpmi_nand_1: gpmi-nand-1 {
+                                                fsl,pins = <
+                                                        MX6DL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
+                                                        MX6DL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
+                                                        MX6DL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
+                                                        MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+                                                        MX6DL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
+                                                        MX6DL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
+                                                        MX6DL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
+                                                        MX6DL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
+                                                        MX6DL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
+                                                        MX6DL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
+                                                        MX6DL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
+                                                        MX6DL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
+                                                        MX6DL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
+                                                        MX6DL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
+                                                        MX6DL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
+                                                        MX6DL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
+                                                        MX6DL_PAD_SD4_DAT0__NAND_DQS      0x00b1
+                                                >;
+                                        };
+                                };
+
+                                i2c1 {
+                                        pinctrl_i2c1_2: i2c1grp-2 {
+                                                fsl,pins = <
+                                                        MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+                                                        MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+                                                >;
+                                        };
+                                };
+
                                 uart1 {
                                         pinctrl_uart1_1: uart1grp-1 {
                                                 fsl,pins = <
@@ -149,6 +205,64 @@
                                         };
                                 };
 
+                                weim {
+                                        pinctrl_weim_cs0_1: weim_cs0grp-1 {
+                                                fsl,pins = <
+                                                        MX6DL_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
+                                                >;
+                                        };
+
+                                        pinctrl_weim_nor_1: weim_norgrp-1 {
+                                                fsl,pins = <
+                                                        MX6DL_PAD_EIM_OE__EIM_OE_B     0xb0b1
+                                                        MX6DL_PAD_EIM_RW__EIM_RW       0xb0b1
+                                                        MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
+                                                        /* data */
+                                                        MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
+                                                        MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
+                                                        MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
+                                                        MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
+                                                        MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
+                                                        MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
+                                                        MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
+                                                        MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
+                                                        MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
+                                                        MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
+                                                        MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
+                                                        MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
+                                                        MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
+                                                        MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
+                                                        MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
+                                                        MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
+                                                        /* address */
+                                                        MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
+                                                        MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
+                                                        MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
+                                                        MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
+                                                        MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
+                                                        MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
+                                                        MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
+                                                        MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
+                                                        MX6DL_PAD_EIM_DA15__EIM_AD15  0xb0b1
+                                                        MX6DL_PAD_EIM_DA14__EIM_AD14  0xb0b1
+                                                        MX6DL_PAD_EIM_DA13__EIM_AD13  0xb0b1
+                                                        MX6DL_PAD_EIM_DA12__EIM_AD12  0xb0b1
+                                                        MX6DL_PAD_EIM_DA11__EIM_AD11  0xb0b1
+                                                        MX6DL_PAD_EIM_DA10__EIM_AD10  0xb0b1
+                                                        MX6DL_PAD_EIM_DA9__EIM_AD09   0xb0b1
+                                                        MX6DL_PAD_EIM_DA8__EIM_AD08   0xb0b1
+                                                        MX6DL_PAD_EIM_DA7__EIM_AD07   0xb0b1
+                                                        MX6DL_PAD_EIM_DA6__EIM_AD06   0xb0b1
+                                                        MX6DL_PAD_EIM_DA5__EIM_AD05   0xb0b1
+                                                        MX6DL_PAD_EIM_DA4__EIM_AD04   0xb0b1
+                                                        MX6DL_PAD_EIM_DA3__EIM_AD03   0xb0b1
+                                                        MX6DL_PAD_EIM_DA2__EIM_AD02   0xb0b1
+                                                        MX6DL_PAD_EIM_DA1__EIM_AD01   0xb0b1
+                                                        MX6DL_PAD_EIM_DA0__EIM_AD00   0xb0b1
+                                                >;
+                                        };
+
+                                };
 
                         };
 
diff --git a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts
new file mode 100644
index 000000000000..7d37ec60d58d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx6q-phytec-pfla02.dtsi"
+
+/ {
+        model = "Phytec phyFLEX-i.MX6 Quad Carrier-Board";
+        compatible = "phytec,imx6q-pbab01", "phytec,imx6q-pfla02", "fsl,imx6q";
+};
+
+&fec {
+        status = "okay";
+};
+
+&uart4 {
+        status = "okay";
+};
+
+&usdhc2 {
+        status = "okay";
+};
+
+&usdhc3 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
new file mode 100644
index 000000000000..f5e1981025ed
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "imx6q.dtsi"
+
+/ {
+        model = "Phytec phyFLEX-i.MX6 Ouad";
+        compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
+
+        memory {
+                reg = <0x10000000 0x80000000>;
+        };
+};
+
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+
+        hog {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                MX6Q_PAD_EIM_D23__GPIO3_IO23    0x80000000
+                        >;
+                };
+        };
+
+        pfla02 {
+                pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 {
+                        fsl,pins = <
+                                MX6Q_PAD_ENET_RXD0__GPIO1_IO27  0x80000000
+                                MX6Q_PAD_ENET_TXD1__GPIO1_IO29  0x80000000
+                        >;
+                };
+        };
+};
+
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet_3>;
+        phy-mode = "rgmii";
+        phy-reset-gpios = <&gpio3 23 0>;
+        status = "disabled";
+};
+
+&uart4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart4_1>;
+        status = "disabled";
+};
+
+&usdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc2_2>;
+        cd-gpios = <&gpio1 4 0>;
+        wp-gpios = <&gpio1 2 0>;
+        status = "disabled";
+};
+
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3_2
+                     &pinctrl_usdhc3_pfla02>;
+        cd-gpios = <&gpio1 27 0>;
+        wp-gpios = <&gpio1 29 0>;
+        status = "disabled";
+};
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
index 49d6f2831ec9..09a75807bc6d 100644
--- a/arch/arm/boot/dts/imx6q-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
@@ -32,4 +32,12 @@
                         >;
                 };
         };
+
+        ecspi1 {
+                pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
+                        fsl,pins = <
+                                MX6Q_PAD_EIM_D19__GPIO3_IO19  0x80000000
+                        >;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index 442051350225..0038228c508c 100644
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -33,6 +33,7 @@
                                 MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x80000000
                                 MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x80000000
                                 MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x80000000
+                                MX6Q_PAD_GPIO_0__CCM_CLKO1    0x130b0
                         >;
                 };
         };
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 21e675848bd1..ba09dc32324e 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -18,6 +18,7 @@
 
                 cpu@0 {
                         compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                         reg = <0>;
                         next-level-cache = <&L2>;
                         operating-points = <
@@ -39,18 +40,21 @@
 
                 cpu@1 {
                         compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                         reg = <1>;
                         next-level-cache = <&L2>;
                 };
 
                 cpu@2 {
                         compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                         reg = <2>;
                         next-level-cache = <&L2>;
                 };
 
                 cpu@3 {
                         compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                         reg = <3>;
                         next-level-cache = <&L2>;
                 };
@@ -157,6 +161,27 @@
                                                         MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
                                                 >;
                                         };
+
+                                        pinctrl_enet_3: enetgrp-3 {
+                                                fsl,pins = <
+                                                        MX6Q_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
+                                                        MX6Q_PAD_ENET_MDC__ENET_MDC         0x1b0b0
+                                                        MX6Q_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
+                                                        MX6Q_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
+                                                        MX6Q_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
+                                                        MX6Q_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
+                                                        MX6Q_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
+                                                        MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+                                                        MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+                                                        MX6Q_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
+                                                        MX6Q_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
+                                                        MX6Q_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
+                                                        MX6Q_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
+                                                        MX6Q_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
+                                                        MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+                                                        MX6Q_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
+                                                >;
+                                        };
                                 };
 
                                 gpmi-nand {
@@ -168,8 +193,6 @@
                                                         MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
                                                         MX6Q_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
                                                         MX6Q_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
-                                                        MX6Q_PAD_NANDF_CS2__NAND_CE2_B   0xb0b1
-                                                        MX6Q_PAD_NANDF_CS3__NAND_CE3_B   0xb0b1
                                                         MX6Q_PAD_SD4_CMD__NAND_RE_B      0xb0b1
                                                         MX6Q_PAD_SD4_CLK__NAND_WE_B      0xb0b1
                                                         MX6Q_PAD_NANDF_D0__NAND_DATA00   0xb0b1
@@ -192,6 +215,13 @@
                                                         MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
                                                 >;
                                         };
+
+                                        pinctrl_i2c1_2: i2c1grp-2 {
+                                                fsl,pins = <
+                                                        MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+                                                        MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+                                                >;
+                                        };
                                 };
 
                                 i2c2 {
@@ -268,6 +298,17 @@
                                                         MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059
                                                 >;
                                         };
+
+                                        pinctrl_usdhc2_2: usdhc2grp-2 {
+                                                fsl,pins = <
+                                                        MX6Q_PAD_SD2_CMD__SD2_CMD    0x17059
+                                                        MX6Q_PAD_SD2_CLK__SD2_CLK    0x10059
+                                                        MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
+                                                        MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
+                                                        MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
+                                                        MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
+                                                >;
+                                        };
                                 };
 
                                 usdhc3 {
@@ -325,6 +366,65 @@
                                                 >;
                                         };
                                 };
+
+                                weim {
+                                        pinctrl_weim_cs0_1: weim_cs0grp-1 {
+                                                fsl,pins = <
+                                                        MX6Q_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
+                                                >;
+                                        };
+
+                                        pinctrl_weim_nor_1: weimnorgrp-1 {
+                                                fsl,pins = <
+                                                        MX6Q_PAD_EIM_OE__EIM_OE_B     0xb0b1
+                                                        MX6Q_PAD_EIM_RW__EIM_RW       0xb0b1
+                                                        MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
+                                                        /* data */
+                                                        MX6Q_PAD_EIM_D16__EIM_DATA16 0x1b0b0
+                                                        MX6Q_PAD_EIM_D17__EIM_DATA17 0x1b0b0
+                                                        MX6Q_PAD_EIM_D18__EIM_DATA18 0x1b0b0
+                                                        MX6Q_PAD_EIM_D19__EIM_DATA19 0x1b0b0
+                                                        MX6Q_PAD_EIM_D20__EIM_DATA20 0x1b0b0
+                                                        MX6Q_PAD_EIM_D21__EIM_DATA21 0x1b0b0
+                                                        MX6Q_PAD_EIM_D22__EIM_DATA22 0x1b0b0
+                                                        MX6Q_PAD_EIM_D23__EIM_DATA23 0x1b0b0
+                                                        MX6Q_PAD_EIM_D24__EIM_DATA24 0x1b0b0
+                                                        MX6Q_PAD_EIM_D25__EIM_DATA25 0x1b0b0
+                                                        MX6Q_PAD_EIM_D26__EIM_DATA26 0x1b0b0
+                                                        MX6Q_PAD_EIM_D27__EIM_DATA27 0x1b0b0
+                                                        MX6Q_PAD_EIM_D28__EIM_DATA28 0x1b0b0
+                                                        MX6Q_PAD_EIM_D29__EIM_DATA29 0x1b0b0
+                                                        MX6Q_PAD_EIM_D30__EIM_DATA30 0x1b0b0
+                                                        MX6Q_PAD_EIM_D31__EIM_DATA31 0x1b0b0
+                                                        /* address */
+                                                        MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1
+                                                        MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1
+                                                        MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1
+                                                        MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1
+                                                        MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1
+                                                        MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1
+                                                        MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1
+                                                        MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1
+                                                        MX6Q_PAD_EIM_DA15__EIM_AD15  0xb0b1
+                                                        MX6Q_PAD_EIM_DA14__EIM_AD14  0xb0b1
+                                                        MX6Q_PAD_EIM_DA13__EIM_AD13  0xb0b1
+                                                        MX6Q_PAD_EIM_DA12__EIM_AD12  0xb0b1
+                                                        MX6Q_PAD_EIM_DA11__EIM_AD11  0xb0b1
+                                                        MX6Q_PAD_EIM_DA10__EIM_AD10  0xb0b1
+                                                        MX6Q_PAD_EIM_DA9__EIM_AD09   0xb0b1
+                                                        MX6Q_PAD_EIM_DA8__EIM_AD08   0xb0b1
+                                                        MX6Q_PAD_EIM_DA7__EIM_AD07   0xb0b1
+                                                        MX6Q_PAD_EIM_DA6__EIM_AD06   0xb0b1
+                                                        MX6Q_PAD_EIM_DA5__EIM_AD05   0xb0b1
+                                                        MX6Q_PAD_EIM_DA4__EIM_AD04   0xb0b1
+                                                        MX6Q_PAD_EIM_DA3__EIM_AD03   0xb0b1
+                                                        MX6Q_PAD_EIM_DA2__EIM_AD02   0xb0b1
+                                                        MX6Q_PAD_EIM_DA1__EIM_AD01   0xb0b1
+                                                        MX6Q_PAD_EIM_DA0__EIM_AD00   0xb0b1
+                                                >;
+                                        };
+
+                                };
                         };
                 };
 
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 4d237cffcc41..e994011220e7 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -16,6 +16,22 @@
         };
 };
 
+&ecspi1 {
+        fsl,spi-num-chipselects = <1>;
+        cs-gpios = <&gpio3 19 0>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_sabreauto>;
+        status = "disabled"; /* pin conflict with WEIM NOR */
+
+        flash: m25p80@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "st,m25p32";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+        };
+};
+
 &fec {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_enet_2>;
@@ -23,6 +39,12 @@
         status = "okay";
 };
 
+&gpmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+        status = "okay";
+};
+
 &uart4 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart4_1>;
@@ -36,3 +58,22 @@
         wp-gpios = <&gpio1 13 0>;
         status = "okay";
 };
+
+&weim {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>;
+        #address-cells = <2>;
+        #size-cells = <1>;
+        ranges = <0 0 0x08000000 0x08000000>;
+        status = "disabled"; /* pin conflict with SPI NOR */
+
+        nor@0,0 {
+                compatible = "cfi-flash";
+                reg = <0 0 0x02000000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                bank-width = <2>;
+                fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
+                                0x0000c000 0x1404a38e 0x00000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index e21f6a89cf0f..6e5dfdb32416 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -26,6 +26,13 @@
                         gpio = <&gpio3 22 0>;
                         enable-active-high;
                 };
+
+                reg_audio: wm8962_supply {
+                        compatible = "regulator-fixed";
+                        regulator-name = "wm8962-supply";
+                        gpio = <&gpio4 10 0>;
+                        enable-active-high;
+                };
         };
 
         gpio-keys {
@@ -43,6 +50,31 @@
                         linux,code = <114>; /* KEY_VOLUMEDOWN */
                 };
         };
+
+        sound {
+                compatible = "fsl,imx6q-sabresd-wm8962",
+                           "fsl,imx-audio-wm8962";
+                model = "wm8962-audio";
+                ssi-controller = <&ssi2>;
+                audio-codec = <&codec>;
+                audio-routing =
+                        "Headphone Jack", "HPOUTL",
+                        "Headphone Jack", "HPOUTR",
+                        "Ext Spk", "SPKOUTL",
+                        "Ext Spk", "SPKOUTR",
+                        "MICBIAS", "AMIC",
+                        "IN3R", "MICBIAS",
+                        "DMIC", "MICBIAS",
+                        "DMICDAT", "DMIC";
+                mux-int-port = <2>;
+                mux-ext-port = <3>;
+        };
+};
+
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux_2>;
+        status = "okay";
 };
 
 &fec {
@@ -52,6 +84,40 @@
         status = "okay";
 };
 
+&i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1_2>;
+        status = "okay";
+
+        codec: wm8962@1a {
+                compatible = "wlf,wm8962";
+                reg = <0x1a>;
+                clocks = <&clks 169>;
+                DCVDD-supply = <&reg_audio>;
+                DBVDD-supply = <&reg_audio>;
+                AVDD-supply = <&reg_audio>;
+                CPVDD-supply = <&reg_audio>;
+                MICVDD-supply = <&reg_audio>;
+                PLLVDD-supply = <&reg_audio>;
+                SPKVDD1-supply = <&reg_audio>;
+                SPKVDD2-supply = <&reg_audio>;
+                gpio-cfg = <
+                        0x0000 /* 0:Default */
+                        0x0000 /* 1:Default */
+                        0x0013 /* 2:FN_DMICCLK */
+                        0x0000 /* 3:Default */
+                        0x8014 /* 4:FN_DMICCDAT */
+                        0x0000 /* 5:Default */
+                >;
+       };
+};
+
+&ssi2 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+
 &uart1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart1_1>;
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 9e8296e4c343..f21d259080fd 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -106,6 +106,8 @@
                         interrupts = <0 92 0x04>;
                         cache-unified;
                         cache-level = <2>;
+                        arm,tag-latency = <4 2 3>;
+                        arm,data-latency = <4 2 3>;
                 };
 
                 pmu {
@@ -638,7 +640,7 @@
                                 status = "disabled";
                         };
 
-                        usbmisc: usbmisc: usbmisc@02184800 {
+                        usbmisc: usbmisc@02184800 {
                                 #index-cells = <1>;
                                 compatible = "fsl,imx6q-usbmisc";
                                 reg = <0x02184800 0x200>;
@@ -742,9 +744,11 @@
                                 reg = <0x021b4000 0x4000>;
                         };
 
-                        weim@021b8000 {
+                        weim: weim@021b8000 {
+                                compatible = "fsl,imx6q-weim";
                                 reg = <0x021b8000 0x4000>;
                                 interrupts = <0 14 0x04>;
+                                clocks = <&clks 196>;
                         };
 
                         ocotp@021bc000 {
@@ -752,11 +756,6 @@
                                 reg = <0x021bc000 0x4000>;
                         };
 
-                        ocotp@021c0000 {
-                                reg = <0x021c0000 0x4000>;
-                                interrupts = <0 21 0x04>;
-                        };
-
                         tzasc@021d0000 { /* TZASC1 */
                                 reg = <0x021d0000 0x4000>;
                                 interrupts = <0 108 0x04>;
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
new file mode 100644
index 000000000000..2886a590823d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "imx6sl.dtsi"
+
+/ {
+        model = "Freescale i.MX6 SoloLite EVK Board";
+        compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
+
+        memory {
+                reg = <0x80000000 0x40000000>;
+        };
+};
+
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec_1>;
+        phy-mode = "rmii";
+        status = "okay";
+};
+
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+
+        hog {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                MX6SL_PAD_KEY_ROW7__GPIO4_IO07    0x17059
+                                MX6SL_PAD_KEY_COL7__GPIO4_IO06    0x17059
+                                MX6SL_PAD_SD2_DAT7__GPIO5_IO00    0x17059
+                                MX6SL_PAD_SD2_DAT6__GPIO4_IO29    0x17059
+                                MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
+                        >;
+                };
+        };
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1_1>;
+        status = "okay";
+};
+
+&usdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc1_1>;
+        bus-width = <8>;
+        cd-gpios = <&gpio4 7 0>;
+        wp-gpios = <&gpio4 6 0>;
+        status = "okay";
+};
+
+&usdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc2_1>;
+        cd-gpios = <&gpio5 0 0>;
+        wp-gpios = <&gpio4 29 0>;
+        status = "okay";
+};
+
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3_1>;
+        cd-gpios = <&gpio3 22 0>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
new file mode 100644
index 000000000000..c5e5da02d7e3
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -0,0 +1,779 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include "skeleton.dtsi"
+#include "imx6sl-pinfunc.h"
+#include <dt-bindings/clock/imx6sl-clock.h>
+
+/ {
+        aliases {
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+                serial4 = &uart5;
+                gpio0 = &gpio1;
+                gpio1 = &gpio2;
+                gpio2 = &gpio3;
+                gpio3 = &gpio4;
+                gpio4 = &gpio5;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        next-level-cache = <&L2>;
+                };
+        };
+
+        intc: interrupt-controller@00a01000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                interrupt-controller;
+                reg = <0x00a01000 0x1000>,
+                      <0x00a00100 0x100>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ckil {
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+
+                osc {
+                        compatible = "fixed-clock";
+                        clock-frequency = <24000000>;
+                };
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&intc>;
+                ranges;
+
+                L2: l2-cache@00a02000 {
+                        compatible = "arm,pl310-cache";
+                        reg = <0x00a02000 0x1000>;
+                        interrupts = <0 92 0x04>;
+                        cache-unified;
+                        cache-level = <2>;
+                        arm,tag-latency = <4 2 3>;
+                        arm,data-latency = <4 2 3>;
+                };
+
+                pmu {
+                        compatible = "arm,cortex-a9-pmu";
+                        interrupts = <0 94 0x04>;
+                };
+
+                aips1: aips-bus@02000000 {
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x02000000 0x100000>;
+                        ranges;
+
+                        spba: spba-bus@02000000 {
+                                compatible = "fsl,spba-bus", "simple-bus";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0x02000000 0x40000>;
+                                ranges;
+
+                                spdif: spdif@02004000 {
+                                        reg = <0x02004000 0x4000>;
+                                        interrupts = <0 52 0x04>;
+                                };
+
+                                ecspi1: ecspi@02008000 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x02008000 0x4000>;
+                                        interrupts = <0 31 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_ECSPI1>,
+                                                 <&clks IMX6SL_CLK_ECSPI1>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+
+                                ecspi2: ecspi@0200c000 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x0200c000 0x4000>;
+                                        interrupts = <0 32 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_ECSPI2>,
+                                                 <&clks IMX6SL_CLK_ECSPI2>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+
+                                ecspi3: ecspi@02010000 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x02010000 0x4000>;
+                                        interrupts = <0 33 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_ECSPI3>,
+                                                 <&clks IMX6SL_CLK_ECSPI3>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+
+                                ecspi4: ecspi@02014000 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x02014000 0x4000>;
+                                        interrupts = <0 34 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_ECSPI4>,
+                                                 <&clks IMX6SL_CLK_ECSPI4>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+
+                                uart5: serial@02018000 {
+                                        compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+                                        reg = <0x02018000 0x4000>;
+                                        interrupts = <0 30 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_UART>,
+                                                 <&clks IMX6SL_CLK_UART_SERIAL>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+
+                                uart1: serial@02020000 {
+                                        compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+                                        reg = <0x02020000 0x4000>;
+                                        interrupts = <0 26 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_UART>,
+                                                 <&clks IMX6SL_CLK_UART_SERIAL>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+
+                                uart2: serial@02024000 {
+                                        compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+                                        reg = <0x02024000 0x4000>;
+                                        interrupts = <0 27 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_UART>,
+                                                 <&clks IMX6SL_CLK_UART_SERIAL>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+
+                                ssi1: ssi@02028000 {
+                                        compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
+                                        reg = <0x02028000 0x4000>;
+                                        interrupts = <0 46 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_SSI1>;
+                                        fsl,fifo-depth = <15>;
+                                        status = "disabled";
+                                };
+
+                                ssi2: ssi@0202c000 {
+                                        compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
+                                        reg = <0x0202c000 0x4000>;
+                                        interrupts = <0 47 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_SSI2>;
+                                        fsl,fifo-depth = <15>;
+                                        status = "disabled";
+                                };
+
+                                ssi3: ssi@02030000 {
+                                        compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
+                                        reg = <0x02030000 0x4000>;
+                                        interrupts = <0 48 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_SSI3>;
+                                        fsl,fifo-depth = <15>;
+                                        status = "disabled";
+                                };
+
+                                uart3: serial@02034000 {
+                                        compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+                                        reg = <0x02034000 0x4000>;
+                                        interrupts = <0 28 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_UART>,
+                                                 <&clks IMX6SL_CLK_UART_SERIAL>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+
+                                uart4: serial@02038000 {
+                                        compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+                                        reg = <0x02038000 0x4000>;
+                                        interrupts = <0 29 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_UART>,
+                                                 <&clks IMX6SL_CLK_UART_SERIAL>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+                        };
+
+                        pwm1: pwm@02080000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
+                                reg = <0x02080000 0x4000>;
+                                interrupts = <0 83 0x04>;
+                                clocks = <&clks IMX6SL_CLK_PWM1>,
+                                         <&clks IMX6SL_CLK_PWM1>;
+                                clock-names = "ipg", "per";
+                        };
+
+                        pwm2: pwm@02084000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
+                                reg = <0x02084000 0x4000>;
+                                interrupts = <0 84 0x04>;
+                                clocks = <&clks IMX6SL_CLK_PWM2>,
+                                         <&clks IMX6SL_CLK_PWM2>;
+                                clock-names = "ipg", "per";
+                        };
+
+                        pwm3: pwm@02088000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
+                                reg = <0x02088000 0x4000>;
+                                interrupts = <0 85 0x04>;
+                                clocks = <&clks IMX6SL_CLK_PWM3>,
+                                         <&clks IMX6SL_CLK_PWM3>;
+                                clock-names = "ipg", "per";
+                        };
+
+                        pwm4: pwm@0208c000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
+                                reg = <0x0208c000 0x4000>;
+                                interrupts = <0 86 0x04>;
+                                clocks = <&clks IMX6SL_CLK_PWM4>,
+                                         <&clks IMX6SL_CLK_PWM4>;
+                                clock-names = "ipg", "per";
+                        };
+
+                        gpt: gpt@02098000 {
+                                compatible = "fsl,imx6sl-gpt";
+                                reg = <0x02098000 0x4000>;
+                                interrupts = <0 55 0x04>;
+                                clocks = <&clks IMX6SL_CLK_GPT>,
+                                         <&clks IMX6SL_CLK_GPT_SERIAL>;
+                                clock-names = "ipg", "per";
+                        };
+
+                        gpio1: gpio@0209c000 {
+                                compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
+                                reg = <0x0209c000 0x4000>;
+                                interrupts = <0 66 0x04 0 67 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+
+                        gpio2: gpio@020a0000 {
+                                compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
+                                reg = <0x020a0000 0x4000>;
+                                interrupts = <0 68 0x04 0 69 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+
+                        gpio3: gpio@020a4000 {
+                                compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
+                                reg = <0x020a4000 0x4000>;
+                                interrupts = <0 70 0x04 0 71 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+
+                        gpio4: gpio@020a8000 {
+                                compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
+                                reg = <0x020a8000 0x4000>;
+                                interrupts = <0 72 0x04 0 73 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+
+                        gpio5: gpio@020ac000 {
+                                compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
+                                reg = <0x020ac000 0x4000>;
+                                interrupts = <0 74 0x04 0 75 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+
+                        kpp: kpp@020b8000 {
+                                reg = <0x020b8000 0x4000>;
+                                interrupts = <0 82 0x04>;
+                        };
+
+                        wdog1: wdog@020bc000 {
+                                compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
+                                reg = <0x020bc000 0x4000>;
+                                interrupts = <0 80 0x04>;
+                                clocks = <&clks IMX6SL_CLK_DUMMY>;
+                        };
+
+                        wdog2: wdog@020c0000 {
+                                compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
+                                reg = <0x020c0000 0x4000>;
+                                interrupts = <0 81 0x04>;
+                                clocks = <&clks IMX6SL_CLK_DUMMY>;
+                                status = "disabled";
+                        };
+
+                        clks: ccm@020c4000 {
+                                compatible = "fsl,imx6sl-ccm";
+                                reg = <0x020c4000 0x4000>;
+                                interrupts = <0 87 0x04 0 88 0x04>;
+                                #clock-cells = <1>;
+                        };
+
+                        anatop: anatop@020c8000 {
+                                compatible = "fsl,imx6sl-anatop", "syscon", "simple-bus";
+                                reg = <0x020c8000 0x1000>;
+                                interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
+
+                                regulator-1p1@110 {
+                                        compatible = "fsl,anatop-regulator";
+                                        regulator-name = "vdd1p1";
+                                        regulator-min-microvolt = <800000>;
+                                        regulator-max-microvolt = <1375000>;
+                                        regulator-always-on;
+                                        anatop-reg-offset = <0x110>;
+                                        anatop-vol-bit-shift = <8>;
+                                        anatop-vol-bit-width = <5>;
+                                        anatop-min-bit-val = <4>;
+                                        anatop-min-voltage = <800000>;
+                                        anatop-max-voltage = <1375000>;
+                                };
+
+                                regulator-3p0@120 {
+                                        compatible = "fsl,anatop-regulator";
+                                        regulator-name = "vdd3p0";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <3150000>;
+                                        regulator-always-on;
+                                        anatop-reg-offset = <0x120>;
+                                        anatop-vol-bit-shift = <8>;
+                                        anatop-vol-bit-width = <5>;
+                                        anatop-min-bit-val = <0>;
+                                        anatop-min-voltage = <2625000>;
+                                        anatop-max-voltage = <3400000>;
+                                };
+
+                                regulator-2p5@130 {
+                                        compatible = "fsl,anatop-regulator";
+                                        regulator-name = "vdd2p5";
+                                        regulator-min-microvolt = <2100000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                        anatop-reg-offset = <0x130>;
+                                        anatop-vol-bit-shift = <8>;
+                                        anatop-vol-bit-width = <5>;
+                                        anatop-min-bit-val = <0>;
+                                        anatop-min-voltage = <2100000>;
+                                        anatop-max-voltage = <2850000>;
+                                };
+
+                                reg_arm: regulator-vddcore@140 {
+                                        compatible = "fsl,anatop-regulator";
+                                        regulator-name = "cpu";
+                                        regulator-min-microvolt = <725000>;
+                                        regulator-max-microvolt = <1450000>;
+                                        regulator-always-on;
+                                        anatop-reg-offset = <0x140>;
+                                        anatop-vol-bit-shift = <0>;
+                                        anatop-vol-bit-width = <5>;
+                                        anatop-delay-reg-offset = <0x170>;
+                                        anatop-delay-bit-shift = <24>;
+                                        anatop-delay-bit-width = <2>;
+                                        anatop-min-bit-val = <1>;
+                                        anatop-min-voltage = <725000>;
+                                        anatop-max-voltage = <1450000>;
+                                };
+
+                                reg_pu: regulator-vddpu@140 {
+                                        compatible = "fsl,anatop-regulator";
+                                        regulator-name = "vddpu";
+                                        regulator-min-microvolt = <725000>;
+                                        regulator-max-microvolt = <1450000>;
+                                        regulator-always-on;
+                                        anatop-reg-offset = <0x140>;
+                                        anatop-vol-bit-shift = <9>;
+                                        anatop-vol-bit-width = <5>;
+                                        anatop-delay-reg-offset = <0x170>;
+                                        anatop-delay-bit-shift = <26>;
+                                        anatop-delay-bit-width = <2>;
+                                        anatop-min-bit-val = <1>;
+                                        anatop-min-voltage = <725000>;
+                                        anatop-max-voltage = <1450000>;
+                                };
+
+                                reg_soc: regulator-vddsoc@140 {
+                                        compatible = "fsl,anatop-regulator";
+                                        regulator-name = "vddsoc";
+                                        regulator-min-microvolt = <725000>;
+                                        regulator-max-microvolt = <1450000>;
+                                        regulator-always-on;
+                                        anatop-reg-offset = <0x140>;
+                                        anatop-vol-bit-shift = <18>;
+                                        anatop-vol-bit-width = <5>;
+                                        anatop-delay-reg-offset = <0x170>;
+                                        anatop-delay-bit-shift = <28>;
+                                        anatop-delay-bit-width = <2>;
+                                        anatop-min-bit-val = <1>;
+                                        anatop-min-voltage = <725000>;
+                                        anatop-max-voltage = <1450000>;
+                                };
+                        };
+
+                        usbphy1: usbphy@020c9000 {
+                                compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
+                                reg = <0x020c9000 0x1000>;
+                                interrupts = <0 44 0x04>;
+                                clocks = <&clks IMX6SL_CLK_USBPHY1>;
+                        };
+
+                        usbphy2: usbphy@020ca000 {
+                                compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
+                                reg = <0x020ca000 0x1000>;
+                                interrupts = <0 45 0x04>;
+                                clocks = <&clks IMX6SL_CLK_USBPHY2>;
+                        };
+
+                        snvs@020cc000 {
+                                compatible = "fsl,sec-v4.0-mon", "simple-bus";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0 0x020cc000 0x4000>;
+
+                                snvs-rtc-lp@34 {
+                                        compatible = "fsl,sec-v4.0-mon-rtc-lp";
+                                        reg = <0x34 0x58>;
+                                        interrupts = <0 19 0x04 0 20 0x04>;
+                                };
+                        };
+
+                        epit1: epit@020d0000 {
+                                reg = <0x020d0000 0x4000>;
+                                interrupts = <0 56 0x04>;
+                        };
+
+                        epit2: epit@020d4000 {
+                                reg = <0x020d4000 0x4000>;
+                                interrupts = <0 57 0x04>;
+                        };
+
+                        src: src@020d8000 {
+                                compatible = "fsl,imx6sl-src", "fsl,imx51-src";
+                                reg = <0x020d8000 0x4000>;
+                                interrupts = <0 91 0x04 0 96 0x04>;
+                                #reset-cells = <1>;
+                        };
+
+                        gpc: gpc@020dc000 {
+                                compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
+                                reg = <0x020dc000 0x4000>;
+                                interrupts = <0 89 0x04>;
+                        };
+
+                        iomuxc: iomuxc@020e0000 {
+                                compatible = "fsl,imx6sl-iomuxc";
+                                reg = <0x020e0000 0x4000>;
+
+                                fec {
+                                        pinctrl_fec_1: fecgrp-1 {
+                                                fsl,pins = <
+                                                        MX6SL_PAD_FEC_MDC__FEC_MDC         0x1b0b0
+                                                        MX6SL_PAD_FEC_MDIO__FEC_MDIO       0x1b0b0
+                                                        MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV    0x1b0b0
+                                                        MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0   0x1b0b0
+                                                        MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1   0x1b0b0
+                                                        MX6SL_PAD_FEC_TX_EN__FEC_TX_EN     0x1b0b0
+                                                        MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0   0x1b0b0
+                                                        MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1   0x1b0b0
+                                                        MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
+                                                >;
+                                        };
+                                };
+
+                                uart1 {
+                                        pinctrl_uart1_1: uart1grp-1 {
+                                                fsl,pins = <
+                                                        MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
+                                                        MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
+                                                >;
+                                        };
+                                };
+
+                                usdhc1 {
+                                        pinctrl_usdhc1_1: usdhc1grp-1 {
+                                                fsl,pins = <
+                                                        MX6SL_PAD_SD1_CMD__SD1_CMD    0x17059
+                                                        MX6SL_PAD_SD1_CLK__SD1_CLK    0x10059
+                                                        MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
+                                                        MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+                                                        MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+                                                        MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
+                                                        MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
+                                                        MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
+                                                        MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
+                                                        MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
+                                                >;
+                                        };
+                                };
+
+                                usdhc2 {
+                                        pinctrl_usdhc2_1: usdhc2grp-1 {
+                                                fsl,pins = <
+                                                        MX6SL_PAD_SD2_CMD__SD2_CMD    0x17059
+                                                        MX6SL_PAD_SD2_CLK__SD2_CLK    0x10059
+                                                        MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+                                                        MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+                                                        MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+                                                        MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+                                                >;
+                                        };
+                                };
+
+                                usdhc3 {
+                                        pinctrl_usdhc3_1: usdhc3grp-1 {
+                                                fsl,pins = <
+                                                        MX6SL_PAD_SD3_CMD__SD3_CMD    0x17059
+                                                        MX6SL_PAD_SD3_CLK__SD3_CLK    0x10059
+                                                        MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+                                                        MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+                                                        MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+                                                        MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+                                                >;
+                                        };
+                                };
+                        };
+
+                        csi: csi@020e4000 {
+                                reg = <0x020e4000 0x4000>;
+                                interrupts = <0 7 0x04>;
+                        };
+
+                        spdc: spdc@020e8000 {
+                                reg = <0x020e8000 0x4000>;
+                                interrupts = <0 6 0x04>;
+                        };
+
+                        sdma: sdma@020ec000 {
+                                compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma";
+                                reg = <0x020ec000 0x4000>;
+                                interrupts = <0 2 0x04>;
+                                clocks = <&clks IMX6SL_CLK_SDMA>,
+                                         <&clks IMX6SL_CLK_SDMA>;
+                                clock-names = "ipg", "ahb";
+                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6sl.bin";
+                        };
+
+                        pxp: pxp@020f0000 {
+                                reg = <0x020f0000 0x4000>;
+                                interrupts = <0 98 0x04>;
+                        };
+
+                        epdc: epdc@020f4000 {
+                                reg = <0x020f4000 0x4000>;
+                                interrupts = <0 97 0x04>;
+                        };
+
+                        lcdif: lcdif@020f8000 {
+                                reg = <0x020f8000 0x4000>;
+                                interrupts = <0 39 0x04>;
+                        };
+
+                        dcp: dcp@020fc000 {
+                                reg = <0x020fc000 0x4000>;
+                                interrupts = <0 99 0x04>;
+                        };
+                };
+
+                aips2: aips-bus@02100000 {
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x02100000 0x100000>;
+                        ranges;
+
+                        usbotg1: usb@02184000 {
+                                compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
+                                reg = <0x02184000 0x200>;
+                                interrupts = <0 43 0x04>;
+                                clocks = <&clks IMX6SL_CLK_USBOH3>;
+                                fsl,usbphy = <&usbphy1>;
+                                fsl,usbmisc = <&usbmisc 0>;
+                                status = "disabled";
+                        };
+
+                        usbotg2: usb@02184200 {
+                                compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
+                                reg = <0x02184200 0x200>;
+                                interrupts = <0 40 0x04>;
+                                clocks = <&clks IMX6SL_CLK_USBOH3>;
+                                fsl,usbphy = <&usbphy2>;
+                                fsl,usbmisc = <&usbmisc 1>;
+                                status = "disabled";
+                        };
+
+                        usbh: usb@02184400 {
+                                compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
+                                reg = <0x02184400 0x200>;
+                                interrupts = <0 42 0x04>;
+                                clocks = <&clks IMX6SL_CLK_USBOH3>;
+                                fsl,usbmisc = <&usbmisc 2>;
+                                status = "disabled";
+                        };
+
+                        usbmisc: usbmisc@02184800 {
+                                #index-cells = <1>;
+                                compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
+                                reg = <0x02184800 0x200>;
+                                clocks = <&clks IMX6SL_CLK_USBOH3>;
+                        };
+
+                        fec: ethernet@02188000 {
+                                compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
+                                reg = <0x02188000 0x4000>;
+                                interrupts = <0 114 0x04>;
+                                clocks = <&clks IMX6SL_CLK_ENET_REF>,
+                                         <&clks IMX6SL_CLK_ENET_REF>;
+                                clock-names = "ipg", "ahb";
+                                status = "disabled";
+                        };
+
+                        usdhc1: usdhc@02190000 {
+                                compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
+                                reg = <0x02190000 0x4000>;
+                                interrupts = <0 22 0x04>;
+                                clocks = <&clks IMX6SL_CLK_USDHC1>,
+                                         <&clks IMX6SL_CLK_USDHC1>,
+                                         <&clks IMX6SL_CLK_USDHC1>;
+                                clock-names = "ipg", "ahb", "per";
+                                bus-width = <4>;
+                                status = "disabled";
+                        };
+
+                        usdhc2: usdhc@02194000 {
+                                compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
+                                reg = <0x02194000 0x4000>;
+                                interrupts = <0 23 0x04>;
+                                clocks = <&clks IMX6SL_CLK_USDHC2>,
+                                         <&clks IMX6SL_CLK_USDHC2>,
+                                         <&clks IMX6SL_CLK_USDHC2>;
+                                clock-names = "ipg", "ahb", "per";
+                                bus-width = <4>;
+                                status = "disabled";
+                        };
+
+                        usdhc3: usdhc@02198000 {
+                                compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
+                                reg = <0x02198000 0x4000>;
+                                interrupts = <0 24 0x04>;
+                                clocks = <&clks IMX6SL_CLK_USDHC3>,
+                                         <&clks IMX6SL_CLK_USDHC3>,
+                                         <&clks IMX6SL_CLK_USDHC3>;
+                                clock-names = "ipg", "ahb", "per";
+                                bus-width = <4>;
+                                status = "disabled";
+                        };
+
+                        usdhc4: usdhc@0219c000 {
+                                compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
+                                reg = <0x0219c000 0x4000>;
+                                interrupts = <0 25 0x04>;
+                                clocks = <&clks IMX6SL_CLK_USDHC4>,
+                                         <&clks IMX6SL_CLK_USDHC4>,
+                                         <&clks IMX6SL_CLK_USDHC4>;
+                                clock-names = "ipg", "ahb", "per";
+                                bus-width = <4>;
+                                status = "disabled";
+                        };
+
+                        i2c1: i2c@021a0000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
+                                reg = <0x021a0000 0x4000>;
+                                interrupts = <0 36 0x04>;
+                                clocks = <&clks IMX6SL_CLK_I2C1>;
+                                status = "disabled";
+                        };
+
+                        i2c2: i2c@021a4000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
+                                reg = <0x021a4000 0x4000>;
+                                interrupts = <0 37 0x04>;
+                                clocks = <&clks IMX6SL_CLK_I2C2>;
+                                status = "disabled";
+                        };
+
+                        i2c3: i2c@021a8000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
+                                reg = <0x021a8000 0x4000>;
+                                interrupts = <0 38 0x04>;
+                                clocks = <&clks IMX6SL_CLK_I2C3>;
+                                status = "disabled";
+                        };
+
+                        mmdc: mmdc@021b0000 {
+                                compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
+                                reg = <0x021b0000 0x4000>;
+                        };
+
+                        rngb: rngb@021b4000 {
+                                reg = <0x021b4000 0x4000>;
+                                interrupts = <0 5 0x04>;
+                        };
+
+                        weim: weim@021b8000 {
+                                reg = <0x021b8000 0x4000>;
+                                interrupts = <0 14 0x04>;
+                        };
+
+                        ocotp: ocotp@021bc000 {
+                                compatible = "fsl,imx6sl-ocotp";
+                                reg = <0x021bc000 0x4000>;
+                        };
+
+                        audmux: audmux@021d8000 {
+                                compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
+                                reg = <0x021d8000 0x4000>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi
index 51376683dbcd..1e5bef0bead7 100644
--- a/arch/arm/boot/dts/kirkwood-6281.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6281.dtsi
@@ -71,5 +71,33 @@
                                 status = "disabled";
                         };
                 };
+
+                rtc@10300 {
+                        compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
+                        reg = <0x10300 0x20>;
+                        interrupts = <53>;
+                        clocks = <&gate_clk 7>;
+                };
+
+                sata@80000 {
+                        compatible = "marvell,orion-sata";
+                        reg = <0x80000 0x5000>;
+                        interrupts = <21>;
+                        clocks = <&gate_clk 14>, <&gate_clk 15>;
+                        clock-names = "0", "1";
+                        status = "disabled";
+                };
+
+                mvsdio@90000 {
+                        compatible = "marvell,orion-sdio";
+                        reg = <0x90000 0x200>;
+                        interrupts = <28>;
+                        clocks = <&gate_clk 4>;
+                        bus-width = <4>;
+                        cap-sdio-irq;
+                        cap-sd-highspeed;
+                        cap-mmc-highspeed;
+                        status = "disabled";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
index 66a751ab5516..a63a11137262 100644
--- a/arch/arm/boot/dts/kirkwood-6282.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -49,6 +49,34 @@
                         };
                 };
 
+                rtc@10300 {
+                        compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
+                        reg = <0x10300 0x20>;
+                        interrupts = <53>;
+                        clocks = <&gate_clk 7>;
+                };
+
+                sata@80000 {
+                        compatible = "marvell,orion-sata";
+                        reg = <0x80000 0x5000>;
+                        interrupts = <21>;
+                        clocks = <&gate_clk 14>, <&gate_clk 15>;
+                        clock-names = "0", "1";
+                        status = "disabled";
+                };
+
+                mvsdio@90000 {
+                        compatible = "marvell,orion-sdio";
+                        reg = <0x90000 0x200>;
+                        interrupts = <28>;
+                        clocks = <&gate_clk 4>;
+                        bus-width = <4>;
+                        cap-sdio-irq;
+                        cap-sd-highspeed;
+                        cap-mmc-highspeed;
+                        status = "disabled";
+                };
+
                 thermal@10078 {
                         compatible = "marvell,kirkwood-thermal";
                         reg = <0x10078 0x4>;
diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts
index 5f21d4e427b0..00c48d26de68 100644
--- a/arch/arm/boot/dts/kirkwood-cloudbox.dts
+++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts
@@ -18,10 +18,6 @@
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
-                        pinctrl-0 = < &pmx_spi &pmx_uart0
-                                        &pmx_cloudbox_sata0 >;
-                        pinctrl-names = "default";
-
                         pmx_cloudbox_sata0: pmx-cloudbox-sata0 {
                                 marvell,pins = "mpp15";
                                 marvell,function = "sata0";
@@ -29,16 +25,22 @@
                 };
 
                 serial@12000 {
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
                         clock-frequency = <166666667>;
                         status = "okay";
                 };
 
                 sata@80000 {
+                        pinctrl-0 = <&pmx_cloudbox_sata0>;
+                        pinctrl-names = "default";
                         status = "okay";
                         nr-ports = <1>;
                 };
 
                 spi@10600 {
+                        pinctrl-0 = <&pmx_spi>;
+                        pinctrl-names = "default";
                         status = "okay";
 
                         flash@0 {
diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
index c9c44b2f62d7..14d4ceea3057 100644
--- a/arch/arm/boot/dts/kirkwood-dns320.dts
+++ b/arch/arm/boot/dts/kirkwood-dns320.dts
@@ -17,6 +17,11 @@
 
         gpio-leds {
                 compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_320
+                             &pmx_led_red_left_hdd &pmx_led_red_right_hdd
+                             &pmx_led_white_usb>;
+                pinctrl-names = "default";
+
                 blue-power {
                         label = "dns320:blue:power";
                         gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */
@@ -46,6 +51,8 @@
                 };
 
                 serial@12100 {
+                        pinctrl-0 = <&pmx_uart1>;
+                        pinctrl-names = "default";
                         status = "okay";
                 };
         };
diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts
index e4e4930dc5cf..63872570e6ce 100644
--- a/arch/arm/boot/dts/kirkwood-dns325.dts
+++ b/arch/arm/boot/dts/kirkwood-dns325.dts
@@ -17,6 +17,11 @@
 
         gpio-leds {
                 compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_325
+                             &pmx_led_red_left_hdd &pmx_led_red_right_hdd
+                             &pmx_led_white_usb>;
+                pinctrl-names = "default";
+
                 white-power {
                         label = "dns325:white:power";
                         gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
index 6875ac00c174..0afe1d07c803 100644
--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
@@ -9,6 +9,10 @@
                 compatible = "gpio-keys";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = <&pmx_button_power &pmx_button_unmount
+                             &pmx_button_reset>;
+                pinctrl-names = "default";
+
                 button@1 {
                         label = "Power button";
                         linux,code = <116>;
@@ -29,6 +33,8 @@
         gpio_fan {
                 /* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */
                 compatible = "gpio-fan";
+                pinctrl-0 = <&pmx_fan_high_speed &pmx_fan_low_speed>;
+                pinctrl-names = "default";
                 gpios = <&gpio1 14 1
                          &gpio1 13 1>;
                 gpio-fan,speed-map = <0    0
@@ -38,27 +44,17 @@
 
         gpio_poweroff {
                 compatible = "gpio-poweroff";
+                pinctrl-0 = <&pmx_power_off>;
+                pinctrl-names = "default";
                 gpios = <&gpio1 4 0>;
         };
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
 
-                        pinctrl-0 = < &pmx_nand &pmx_uart1
-                                      &pmx_sata0 &pmx_sata1
-                                      &pmx_led_power
-                                      &pmx_led_red_right_hdd
-                                      &pmx_led_red_left_hdd
-                                      &pmx_led_red_usb_325
-                                      &pmx_button_power
-                                      &pmx_led_red_usb_320
-                                      &pmx_power_off &pmx_power_back_on
-                                      &pmx_power_sata0 &pmx_power_sata1
-                                      &pmx_present_sata0 &pmx_present_sata1
-                                      &pmx_led_white_usb &pmx_fan_tacho
-                                      &pmx_fan_high_speed &pmx_fan_low_speed
-                                      &pmx_button_unmount &pmx_button_reset
-                                      &pmx_temp_alarm >;
+                        pinctrl-0 = <&pmx_power_back_on &pmx_present_sata0
+                                     &pmx_present_sata1 &pmx_fan_tacho
+                                     &pmx_temp_alarm>;
                         pinctrl-names = "default";
 
                         pmx_sata0: pmx-sata0 {
@@ -147,11 +143,15 @@
                         };
                 };
                 sata@80000 {
+                        pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
+                        pinctrl-names = "default";
                         status = "okay";
                         nr-ports = <2>;
                 };
 
                 nand@3000000 {
+                        pinctrl-0 = <&pmx_nand>;
+                        pinctrl-names = "default";
                         status = "okay";
                         chip-delay = <35>;
 
@@ -192,6 +192,8 @@
                 compatible = "simple-bus";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>;
+                pinctrl-names = "default";
 
                 sata0_power: regulator@1 {
                         compatible = "regulator-fixed";
diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts
index 0196cf6b0ef2..7714742bb8d8 100644
--- a/arch/arm/boot/dts/kirkwood-dockstar.dts
+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts
@@ -18,11 +18,6 @@
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
-
-                        pinctrl-0 = < &pmx_usb_power_enable
-                                      &pmx_led_green &pmx_led_orange >;
-                        pinctrl-names = "default";
-
                         pmx_usb_power_enable: pmx-usb-power-enable {
                                 marvell,pins = "mpp29";
                                 marvell,function = "gpio";
@@ -62,6 +57,8 @@
         };
         gpio-leds {
                 compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_green &pmx_led_orange>;
+                pinctrl-names = "default";
 
                 health {
                         label = "status:green:health";
@@ -77,6 +74,8 @@
                 compatible = "simple-bus";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = <&pmx_usb_power_enable>;
+                pinctrl-names = "default";
 
                 usb_power: regulator@1 {
                         compatible = "regulator-fixed";
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index 289e51d86372..36c7ba38d500 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -18,12 +18,6 @@
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
-
-                        pinctrl-0 = < &pmx_spi
-                                      &pmx_led_bluetooth &pmx_led_wifi
-                                      &pmx_led_wifi_ap >;
-                        pinctrl-names = "default";
-
                         pmx_led_bluetooth: pmx-led-bluetooth {
                                 marvell,pins = "mpp47";
                                 marvell,function = "gpio";
@@ -43,6 +37,8 @@
 
                 spi@10600 {
                         status = "okay";
+                        pinctrl-0 = <&pmx_spi>;
+                        pinctrl-names = "default";
 
                         m25p40@0 {
                                 #address-cells = <1>;
@@ -79,11 +75,15 @@
                         pinctrl-names = "default";
                         status = "okay";
                         /* No CD or WP GPIOs */
+                        broken-cd;
                 };
         };
 
         gpio-leds {
                 compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_bluetooth &pmx_led_wifi
+                             &pmx_led_wifi_ap >;
+                pinctrl-names = "default";
 
                 bluetooth {
                         label = "dreamplug:blue:bluetooth";
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
index c3573be7b92c..31caa6405065 100644
--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
@@ -18,15 +18,6 @@
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
-
-                        pinctrl-0 = < &pmx_usb_power_enable &pmx_led_orange
-                                      &pmx_led_left_cap_0 &pmx_led_left_cap_1
-                                      &pmx_led_left_cap_2 &pmx_led_left_cap_3
-                                      &pmx_led_right_cap_0 &pmx_led_right_cap_1
-                                      &pmx_led_right_cap_2 &pmx_led_right_cap_3
-                                    >;
-                        pinctrl-names = "default";
-
                         pmx_usb_power_enable: pmx-usb-power-enable {
                                 marvell,pins = "mpp29";
                                 marvell,function = "gpio";
@@ -109,6 +100,13 @@
         };
         gpio-leds {
                 compatible = "gpio-leds";
+                pinctrl-0 = < &pmx_led_orange
+                              &pmx_led_left_cap_0 &pmx_led_left_cap_1
+                              &pmx_led_left_cap_2 &pmx_led_left_cap_3
+                              &pmx_led_right_cap_0 &pmx_led_right_cap_1
+                              &pmx_led_right_cap_2 &pmx_led_right_cap_3
+                            >;
+                pinctrl-names = "default";
 
                 health {
                         label = "status:green:health";
@@ -156,6 +154,8 @@
                 compatible = "simple-bus";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = <&pmx_usb_power_enable>;
+                pinctrl-names = "default";
 
                 usb_power: regulator@1 {
                         compatible = "regulator-fixed";
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
index 44fd97dfc1f3..1e642f39b154 100644
--- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
+++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
@@ -18,11 +18,6 @@
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
-
-                        pinctrl-0 = < &pmx_led_health_r &pmx_led_health_g
-                                      &pmx_led_wmode_r &pmx_led_wmode_g >;
-                        pinctrl-names = "default";
-
                         pmx_led_health_r: pmx-led-health-r {
                                 marvell,pins = "mpp46";
                                 marvell,function = "gpio";
@@ -72,11 +67,16 @@
 
                 mvsdio@90000 {
                         status = "okay";
+                        /* No CD or WP GPIOs */
+                        broken-cd;
                 };
         };
 
         gpio-leds {
                 compatible = "gpio-leds";
+                pinctrl-0 = < &pmx_led_health_r &pmx_led_health_g
+                              &pmx_led_wmode_r &pmx_led_wmode_g >;
+                pinctrl-names = "default";
 
                 health-r {
                         label = "guruplug:red:health";
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts
index 5335b1aa8601..20c4b081f420 100644
--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts
+++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts
@@ -18,13 +18,6 @@
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
-
-                        pinctrl-0 = < &pmx_nand
-                                      &pmx_led_os_red &pmx_power_off
-                                      &pmx_led_os_green &pmx_led_usb_transfer
-                                      &pmx_button_reset &pmx_button_usb_copy >;
-                        pinctrl-names = "default";
-
                         pmx_led_os_red: pmx-led-os-red {
                                 marvell,pins = "mpp22";
                                 marvell,function = "gpio";
@@ -61,6 +54,8 @@
 
                 nand@3000000 {
                         status = "okay";
+                        pinctrl-0 = <&pmx_nand>;
+                        pinctrl-names = "default";
 
                         partition@0 {
                                 label = "u-boot";
@@ -84,6 +79,9 @@
                 compatible = "gpio-keys";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = <&pmx_button_reset &pmx_button_usb_copy>;
+                pinctrl-names = "default";
+
                 button@1 {
                         label = "USB Copy";
                         linux,code = <133>;
@@ -97,6 +95,9 @@
         };
         gpio-leds {
                 compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_os_red &pmx_led_os_green
+                             &pmx_led_usb_transfer>;
+                pinctrl-names = "default";
 
                 green-os {
                         label = "ib62x0:green:os";
@@ -114,6 +115,8 @@
         };
         gpio_poweroff {
                 compatible = "gpio-poweroff";
+                pinctrl-0 = <&pmx_power_off>;
+                pinctrl-names = "default";
                 gpios = <&gpio0 24 0>;
         };
 
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index e591d5df769f..441204e8abc6 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -20,51 +20,43 @@
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
-
-                        pinctrl-0 = < &pmx_gpio_12 &pmx_gpio_35
-                                      &pmx_gpio_41 &pmx_gpio_42
-                                      &pmx_gpio_43 &pmx_gpio_44
-                                      &pmx_gpio_45 &pmx_gpio_46
-                                      &pmx_gpio_47 &pmx_gpio_48 >;
-                        pinctrl-names = "default";
-
-                        pmx_gpio_12: pmx-gpio-12 {
+                        pmx_button_reset: pmx-button-reset {
                                 marvell,pins = "mpp12";
                                 marvell,function = "gpio";
                         };
-                        pmx_gpio_35: pmx-gpio-35 {
+                        pmx_button_otb: pmx-button-otb {
                                 marvell,pins = "mpp35";
                                 marvell,function = "gpio";
                         };
-                        pmx_gpio_41: pmx-gpio-41 {
+                        pmx_led_level: pmx-led-level {
                                 marvell,pins = "mpp41";
                                 marvell,function = "gpio";
                         };
-                        pmx_gpio_42: pmx-gpio-42 {
+                        pmx_led_power_blue: pmx-led-power-blue {
                                 marvell,pins = "mpp42";
                                 marvell,function = "gpio";
                         };
-                        pmx_gpio_43: pmx-gpio-43 {
+                        pmx_led_power_red: pmx-power-red {
                                 marvell,pins = "mpp43";
                                 marvell,function = "gpio";
                         };
-                        pmx_gpio_44: pmx-gpio-44 {
+                        pmx_led_usb1: pmx-led-usb1 {
                                 marvell,pins = "mpp44";
                                 marvell,function = "gpio";
                         };
-                        pmx_gpio_45: pmx-gpio-45 {
+                        pmx_led_usb2: pmx-led-usb2 {
                                 marvell,pins = "mpp45";
                                 marvell,function = "gpio";
                         };
-                        pmx_gpio_46: pmx-gpio-46 {
+                        pmx_led_usb3: pmx-led-usb3 {
                                 marvell,pins = "mpp46";
                                 marvell,function = "gpio";
                         };
-                        pmx_gpio_47: pmx-gpio-47 {
+                        pmx_led_usb4: pmx-led-usb4 {
                                 marvell,pins = "mpp47";
                                 marvell,function = "gpio";
                         };
-                        pmx_gpio_48: pmx-gpio-48 {
+                        pmx_led_otb: pmx-led-otb {
                                 marvell,pins = "mpp48";
                                 marvell,function = "gpio";
                         };
@@ -121,6 +113,11 @@
 
         gpio-leds {
                 compatible = "gpio-leds";
+                pinctrl-0 = < &pmx_led_level &pmx_led_power_blue
+                              &pmx_led_power_red &pmx_led_usb1
+                              &pmx_led_usb2 &pmx_led_usb3
+                              &pmx_led_usb4 &pmx_led_otb >;
+                pinctrl-names = "default";
 
                 led-level {
                         label = "led_level";
@@ -162,6 +159,9 @@
                 compatible = "gpio-keys";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = < &pmx_button_reset &pmx_button_otb >;
+                pinctrl-names = "default";
+
                 button@1 {
                         label = "OTB Button";
                         linux,code = <133>;
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
index 3694e94f6e99..00a7bfe5e83b 100644
--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -18,12 +18,7 @@
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
-
-                        pinctrl-0 = < &pmx_button_reset &pmx_button_power
-                                      &pmx_led_backup &pmx_led_power
-                                      &pmx_button_otb &pmx_led_rebuild
-                                      &pmx_led_health
-                                      &pmx_led_sata_brt_ctrl_1
+                        pinctrl-0 = < &pmx_led_sata_brt_ctrl_1
                                       &pmx_led_sata_brt_ctrl_2
                                       &pmx_led_backup_brt_ctrl_1
                                       &pmx_led_backup_brt_ctrl_2
@@ -151,6 +146,9 @@
         };
         gpio-leds {
                 compatible = "gpio-leds";
+                pinctrl-0 = < &pmx_led_backup &pmx_led_power
+                              &pmx_led_rebuild &pmx_led_health >;
+                pinctrl-names = "default";
 
                 power_led {
                         label = "status:white:power_led";
@@ -174,6 +172,11 @@
                 compatible = "gpio-keys";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = <&pmx_button_reset &pmx_button_power
+                             &pmx_button_otb>;
+                pinctrl-names = "default";
+
+
                 Power {
                         label = "Power Button";
                         linux,code = <116>;
diff --git a/arch/arm/boot/dts/kirkwood-is2.dts b/arch/arm/boot/dts/kirkwood-is2.dts
index 0bdce0ad7277..c3f036b86cca 100644
--- a/arch/arm/boot/dts/kirkwood-is2.dts
+++ b/arch/arm/boot/dts/kirkwood-is2.dts
@@ -13,6 +13,8 @@
 
         ocp@f1000000 {
                 sata@80000 {
+                        pinctrl-0 = <&pmx_ns2_sata0>;
+                        pinctrl-names = "default";
                         status = "okay";
                         nr-ports = <1>;
                 };
diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
index 5bbd0542cdd3..5d9f5ea78700 100644
--- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
+++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
@@ -18,9 +18,7 @@
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
-
-                        pinctrl-0 = < &pmx_nand &pmx_i2c_gpio_sda
-                                &pmx_i2c_gpio_scl >;
+                        pinctrl-0 = < &pmx_i2c_gpio_sda &pmx_i2c_gpio_scl >;
                         pinctrl-names = "default";
 
                         pmx_i2c_gpio_sda: pmx-gpio-sda {
@@ -38,8 +36,17 @@
                 };
 
                 nand@3000000 {
+                        pinctrl-0 = <&pmx_nand>;
+                        pinctrl-names = "default";
                         status = "ok";
                         chip-delay = <25>;
                 };
         };
+
+        i2c@0 {
+                compatible = "i2c-gpio";
+                gpios = < &gpio0 8 0            /* sda */
+                        &gpio0 9 0 >;           /* scl */
+                i2c-gpio,delay-us = <2>;        /* ~100 kHz */
+        };
 };
diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
index 996c7fefd253..31b17f5b9d28 100644
--- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi
+++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
@@ -8,16 +8,6 @@
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
-
-                        pinctrl-0 = < &pmx_power_hdd &pmx_usb_vbus
-                                      &pmx_fan_low &pmx_fan_high
-                                      &pmx_led_function_red &pmx_led_alarm
-                                      &pmx_led_info &pmx_led_power
-                                      &pmx_fan_lock &pmx_button_function
-                                      &pmx_power_switch &pmx_power_auto_switch
-                                      &pmx_led_function_blue >;
-                        pinctrl-names = "default";
-
                         pmx_power_hdd: pmx-power-hdd {
                                 marvell,pins = "mpp10";
                                 marvell,function = "gpo";
@@ -112,6 +102,10 @@
                 compatible = "gpio-keys";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = <&pmx_button_function &pmx_power_switch
+                             &pmx_power_auto_switch>;
+                pinctrl-names = "default";
+
                 button@1 {
                         label = "Function Button";
                         linux,code = <357>;
@@ -133,6 +127,10 @@
 
         gpio_leds {
                 compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm
+                             &pmx_led_info &pmx_led_power
+                             &pmx_led_function_blue>;
+                pinctrl-names = "default";
 
                 led@1 {
                         label = "lsxl:blue:func";
@@ -163,6 +161,8 @@
 
         gpio_fan {
                 compatible = "gpio-fan";
+                pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>;
+                pinctrl-names = "default";
                 gpios = <&gpio0 19 1
                          &gpio0 18 1>;
                 gpio-fan,speed-map = <0    3
@@ -180,6 +180,8 @@
                 compatible = "simple-bus";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = <&pmx_power_hdd &pmx_usb_vbus>;
+                pinctrl-names = "default";
 
                 usb_power: regulator@1 {
                         compatible = "regulator-fixed";
diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
index 90501cf129bb..6179333fd71f 100644
--- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
+++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
@@ -18,16 +18,6 @@
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
-
-                        pinctrl-0 = < &pmx_nand &pmx_uart0
-                                      &pmx_led_health
-                                      &pmx_sata0 &pmx_sata1
-                                      &pmx_led_user1o
-                                      &pmx_led_user1g &pmx_led_user0o
-                                      &pmx_led_user0g &pmx_led_misc
-                                    >;
-                        pinctrl-names = "default";
-
                         pmx_led_health: pmx-led-health {
                                 marvell,pins = "mpp7";
                                 marvell,function = "gpo";
@@ -91,9 +81,13 @@
 
                 serial@12000 {
                         status = "ok";
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
                 };
 
                 nand@3000000 {
+                        pinctrl-0 = <&pmx_nand>;
+                        pinctrl-names = "default";
                         status = "okay";
 
                         partition@0 {
@@ -127,16 +121,17 @@
                 };
 
                 sata@80000 {
+                        pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
+                        pinctrl-names = "default";
                         nr-ports = <2>;
                         status = "okay";
-
                 };
 
                 mvsdio@90000 {
                         pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>;
                         pinctrl-names = "default";
                         status = "okay";
-                        cd-gpios = <&gpio1 15 0>;
+                        cd-gpios = <&gpio1 15 1>;
                         /* No WP GPIO */
                 };
 
@@ -151,6 +146,12 @@
 
         gpio-leds {
                 compatible = "gpio-leds";
+                pinctrl-0 = < &pmx_led_health
+                              &pmx_led_user1o
+                              &pmx_led_user1g &pmx_led_user0o
+                              &pmx_led_user0g &pmx_led_misc
+                            >;
+                pinctrl-names = "default";
 
                 health {
                         label = "status:green:health";
diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
index 0f852b40f5c1..ad6ade7d9191 100644
--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
@@ -18,18 +18,6 @@
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
-
-                        pinctrl-0 = < &pmx_uart0
-                                      &pmx_button_power
-                                      &pmx_button_backup
-                                      &pmx_button_reset
-                                      &pmx_led_blue_power
-                                      &pmx_led_blue_activity
-                                      &pmx_led_blue_disk1
-                                      &pmx_led_blue_disk2
-                                      &pmx_led_blue_backup >;
-                        pinctrl-names = "default";
-
                         pmx_button_power: pmx-button-power {
                                 marvell,pins = "mpp47";
                                 marvell,function = "gpio";
@@ -74,6 +62,8 @@
                 };
 
                 serial@12000 {
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
                         status = "okay";
                 };
 
@@ -123,6 +113,10 @@
 
         gpio-leds {
                 compatible = "gpio-leds";
+                pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_activity
+                              &pmx_led_blue_disk1 &pmx_led_blue_disk2
+                              &pmx_led_blue_backup >;
+                pinctrl-names = "default";
 
                 power_led {
                         label = "status:blue:power_led";
@@ -151,6 +145,10 @@
                 compatible = "gpio-keys";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = <&pmx_button_power &pmx_button_backup
+                             &pmx_button_reset>;
+                pinctrl-names = "default";
+
                 button@1 {
                         label = "Power Button";
                         linux,code = <116>;     /* KEY_POWER */
diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
index 6affd924fe11..2afac0405816 100644
--- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
@@ -8,10 +8,6 @@
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
-                        pinctrl-0 = < &pmx_spi &pmx_twsi0 &pmx_uart0
-                                        &pmx_ns2_sata0 &pmx_ns2_sata1>;
-                        pinctrl-names = "default";
-
                         pmx_ns2_sata0: pmx-ns2-sata0 {
                                 marvell,pins = "mpp21";
                                 marvell,function = "sata0";
@@ -23,10 +19,14 @@
                 };
 
                 serial@12000 {
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
                         status = "okay";
                 };
 
                 spi@10600 {
+                        pinctrl-0 = <&pmx_spi>;
+                        pinctrl-names = "default";
                         status = "okay";
 
                         flash@0 {
@@ -45,6 +45,8 @@
                 };
 
                 i2c@11000 {
+                        pinctrl-0 = <&pmx_twsi0>;
+                        pinctrl-names = "default";
                         status = "okay";
 
                         eeprom@50 {
diff --git a/arch/arm/boot/dts/kirkwood-ns2.dts b/arch/arm/boot/dts/kirkwood-ns2.dts
index f2d36ecf36d8..b50e93d7796c 100644
--- a/arch/arm/boot/dts/kirkwood-ns2.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2.dts
@@ -13,6 +13,8 @@
 
         ocp@f1000000 {
                 sata@80000 {
+                        pinctrl-0 = <&pmx_ns2_sata0>;
+                        pinctrl-names = "default";
                         status = "okay";
                         nr-ports = <1>;
                 };
diff --git a/arch/arm/boot/dts/kirkwood-ns2lite.dts b/arch/arm/boot/dts/kirkwood-ns2lite.dts
index b02eb4ea1bb4..af8259fe8955 100644
--- a/arch/arm/boot/dts/kirkwood-ns2lite.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2lite.dts
@@ -13,6 +13,8 @@
 
         ocp@f1000000 {
                 sata@80000 {
+                        pinctrl-0 = <&pmx_ns2_sata0>;
+                        pinctrl-names = "default";
                         status = "okay";
                         nr-ports = <1>;
                 };
diff --git a/arch/arm/boot/dts/kirkwood-ns2max.dts b/arch/arm/boot/dts/kirkwood-ns2max.dts
index bcec4d6cada7..85f24d227e17 100644
--- a/arch/arm/boot/dts/kirkwood-ns2max.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2max.dts
@@ -13,6 +13,8 @@
 
         ocp@f1000000 {
                 sata@80000 {
+                        pinctrl-0 = <&pmx_ns2_sata0 &pmx_ns2_sata1>;
+                        pinctrl-names = "default";
                         status = "okay";
                         nr-ports = <2>;
                 };
diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/kirkwood-ns2mini.dts
index adab1ab25733..329e530bffe7 100644
--- a/arch/arm/boot/dts/kirkwood-ns2mini.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2mini.dts
@@ -14,6 +14,8 @@
 
         ocp@f1000000 {
                 sata@80000 {
+                        pinctrl-0 = <&pmx_ns2_sata0>;
+                        pinctrl-names = "default";
                         status = "okay";
                         nr-ports = <1>;
                 };
diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts
index 9ddf218f2cbd..69003598f5fa 100644
--- a/arch/arm/boot/dts/kirkwood-nsa310.dts
+++ b/arch/arm/boot/dts/kirkwood-nsa310.dts
@@ -1,6 +1,7 @@
 /dts-v1/;
 
 /include/ "kirkwood.dtsi"
+/include/ "kirkwood-6281.dtsi"
 
 / {
         model = "ZyXEL NSA310";
@@ -17,22 +18,7 @@
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
-                        pinctrl-0 = < &pmx_led_esata_green
-                                      &pmx_led_esata_red
-                                      &pmx_led_usb_green
-                                      &pmx_led_usb_red
-                                      &pmx_usb_power_off
-                                      &pmx_led_sys_green
-                                      &pmx_led_sys_red
-                                      &pmx_btn_reset
-                                      &pmx_btn_copy
-                                      &pmx_led_copy_green
-                                      &pmx_led_copy_red
-                                      &pmx_led_hdd_green
-                                      &pmx_led_hdd_red
-                                      &pmx_unknown
-                                      &pmx_btn_power
-                                      &pmx_pwr_off >;
+                        pinctrl-0 = <&pmx_unknown>;
                         pinctrl-names = "default";
 
                         pmx_led_esata_green: pmx-led-esata-green {
@@ -190,6 +176,8 @@
                 compatible = "gpio-keys";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>;
+                pinctrl-names = "default";
 
                 button@1 {
                         label = "Power Button";
@@ -210,6 +198,12 @@
 
         gpio-leds {
                 compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_esata_green &pmx_led_esata_red
+                             &pmx_led_usb_green &pmx_led_usb_red
+                             &pmx_led_sys_green &pmx_led_sys_red
+                             &pmx_led_copy_green &pmx_led_copy_red
+                             &pmx_led_hdd_green &pmx_led_hdd_red>;
+                pinctrl-names = "default";
 
                 green-sys {
                         label = "nsa310:green:sys";
@@ -255,6 +249,8 @@
 
         gpio_poweroff {
                 compatible = "gpio-poweroff";
+                pinctrl-0 = <&pmx_pwr_off>;
+                pinctrl-names = "default";
                 gpios = <&gpio1 16 0>;
         };
 
@@ -262,6 +258,8 @@
                 compatible = "simple-bus";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = <&pmx_usb_power_off>;
+                pinctrl-names = "default";
 
                 usb0_power_off: regulator@1 {
                         compatible = "regulator-fixed";
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
index d27f7245f8e7..38dc8517d777 100644
--- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
@@ -19,15 +19,21 @@
         ocp@f1000000 {
                 serial@12000 {
                         status = "ok";
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
                 };
 
                 serial@12100 {
                         status = "ok";
+                        pinctrl-0 = <&pmx_uart1>;
+                        pinctrl-names = "default";
                 };
 
                 nand@3000000 {
                         chip-delay = <25>;
                         status = "okay";
+                        pinctrl-0 = <&pmx_nand>;
+                        pinctrl-names = "default";
 
                         partition@0 {
                                 label = "uboot";
@@ -67,6 +73,8 @@
 
                 i2c@11100 {
                         status = "okay";
+                        pinctrl-0 = <&pmx_twsi1>;
+                        pinctrl-names = "default";
 
                         s35390a: s35390a@30 {
                                 compatible = "s35390a";
@@ -75,16 +83,7 @@
                 };
 
                 pinctrl: pinctrl@10000 {
-                        pinctrl-0 = < &pmx_nand &pmx_uart0
-                                &pmx_uart1 &pmx_twsi1
-                                &pmx_dip_sw0 &pmx_dip_sw1
-                                &pmx_dip_sw2 &pmx_dip_sw3
-                                &pmx_gpio_0 &pmx_gpio_1
-                                &pmx_gpio_2 &pmx_gpio_3
-                                &pmx_gpio_4 &pmx_gpio_5
-                                &pmx_gpio_6 &pmx_gpio_7
-                                &pmx_led_red &pmx_led_green
-                                &pmx_led_yellow >;
+                        pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>;
                         pinctrl-names = "default";
 
                         pmx_uart0: pmx-uart0 {
@@ -104,63 +103,14 @@
                                 marvell,function = "sysrst";
                         };
 
-                        pmx_dip_sw0: pmx-dip-sw0 {
-                                marvell,pins = "mpp20";
-                                marvell,function = "gpio";
-                        };
-
-                        pmx_dip_sw1: pmx-dip-sw1 {
-                                marvell,pins = "mpp21";
-                                marvell,function = "gpio";
-                        };
-
-                        pmx_dip_sw2: pmx-dip-sw2 {
-                                marvell,pins = "mpp22";
-                                marvell,function = "gpio";
-                        };
-
-                        pmx_dip_sw3: pmx-dip-sw3 {
-                                marvell,pins = "mpp23";
-                                marvell,function = "gpio";
-                        };
-
-                        pmx_gpio_0: pmx-gpio-0 {
-                                marvell,pins = "mpp24";
-                                marvell,function = "gpio";
-                        };
-
-                        pmx_gpio_1: pmx-gpio-1 {
-                                marvell,pins = "mpp25";
-                                marvell,function = "gpio";
-                        };
-
-                        pmx_gpio_2: pmx-gpio-2 {
-                                marvell,pins = "mpp26";
+                        pmx_dip_switches: pmx-dip-switches {
+                                marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23";
                                 marvell,function = "gpio";
                         };
 
-                        pmx_gpio_3: pmx-gpio-3 {
-                                marvell,pins = "mpp27";
-                                marvell,function = "gpio";
-                        };
-
-                        pmx_gpio_4: pmx-gpio-4 {
-                                marvell,pins = "mpp28";
-                                marvell,function = "gpio";
-                        };
-
-                        pmx_gpio_5: pmx-gpio-5 {
-                                marvell,pins = "mpp29";
-                                marvell,function = "gpio";
-                        };
-
-                        pmx_gpio_6: pmx-gpio-6 {
-                                marvell,pins = "mpp30";
-                                marvell,function = "gpio";
-                        };
-
-                        pmx_gpio_7: pmx-gpio-7 {
-                                marvell,pins = "mpp31";
+                        pmx_gpio_header: pmx-gpio-header {
+                                marvell,pins = "mpp24", "mpp25", "mpp26", "mpp27",
+                                               "mpp28", "mpp29", "mpp30", "mpp31";
                                 marvell,function = "gpio";
                         };
 
@@ -174,18 +124,8 @@
                                 marvell,function = "gpio";
                         };
 
-                        pmx_led_red: pmx-led-red {
-                                marvell,pins = "mpp41";
-                                marvell,function = "gpio";
-                        };
-
-                        pmx_led_green: pmx-led-green {
-                                marvell,pins = "mpp42";
-                                marvell,function = "gpio";
-                        };
-
-                        pmx_led_yellow: pmx-led-yellow {
-                                marvell,pins = "mpp43";
+                        pmx_leds: pmx-leds {
+                                marvell,pins = "mpp41", "mpp42", "mpp43";
                                 marvell,function = "gpio";
                         };
                 };
@@ -193,6 +133,8 @@
 
         gpio-leds {
                 compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_leds>;
+                pinctrl-names = "default";
 
                 led-red {
                         label = "obsa6:red:stat";
@@ -209,4 +151,18 @@
                         gpios = <&gpio1 11 1>;
                 };
         };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                pinctrl-0 = <&pmx_gpio_init>;
+                pinctrl-names = "default";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                button@1 {
+                        label = "Init Button";
+                        linux,code = <116>;
+                        gpios = <&gpio1 6 0>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
new file mode 100644
index 000000000000..f7143f128504
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
@@ -0,0 +1,93 @@
+/*
+ * kirkwood-sheevaplug-common.dts - Common parts for Sheevaplugs
+ *
+ * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com>
+ *
+ * Licensed under GPLv2
+ */
+
+/include/ "kirkwood.dtsi"
+/include/ "kirkwood-6281.dtsi"
+
+/ {
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+
+        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+
+                        pmx_usb_power_enable: pmx-usb-power-enable {
+                                marvell,pins = "mpp29";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_red: pmx-led-red {
+                                marvell,pins = "mpp46";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_blue: pmx-led-blue {
+                                marvell,pins = "mpp49";
+                                marvell,function = "gpio";
+                        };
+                        pmx_sdio_cd: pmx-sdio-cd {
+                                marvell,pins = "mpp44";
+                                marvell,function = "gpio";
+                        };
+                        pmx_sdio_wp: pmx-sdio-wp {
+                                marvell,pins = "mpp47";
+                                marvell,function = "gpio";
+                        };
+                };
+                serial@12000 {
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                };
+
+                nand@3000000 {
+                        pinctrl-0 = <&pmx_nand>;
+                        pinctrl-names = "default";
+                        status = "okay";
+
+                        partition@0 {
+                                label = "u-boot";
+                                reg = <0x0000000 0x100000>;
+                        };
+
+                        partition@100000 {
+                                label = "uImage";
+                                reg = <0x0100000 0x400000>;
+                        };
+
+                        partition@500000 {
+                                label = "root";
+                                reg = <0x0500000 0x1fb00000>;
+                        };
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&pmx_usb_power_enable>;
+                pinctrl-names = "default";
+
+                usb_power: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "USB Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio0 29 0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
new file mode 100644
index 000000000000..f620ce48de97
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
@@ -0,0 +1,43 @@
+/*
+ * kirkwood-sheevaplug-esata.dts - Device tree file for eSATA Sheevaplug
+ *
+ * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com>
+ *
+ * Licensed under GPLv2
+ */
+
+/dts-v1/;
+
+/include/ "kirkwood-sheevaplug-common.dtsi"
+
+/ {
+        model = "Globalscale Technologies eSATA SheevaPlug";
+        compatible = "globalscale,sheevaplug-esata-rev13", "globalscale,sheevaplug-esata", "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+        ocp@f1000000 {
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <2>;
+                };
+
+                mvsdio@90000 {
+                        pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                        cd-gpios = <&gpio1 12 1>;
+                        wp-gpios = <&gpio1 15 0>;
+                };
+        };
+
+        gpio-leds {
+                compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_blue>;
+                pinctrl-names = "default";
+
+                health {
+                        label = "sheevaplug:blue:health";
+                        gpios = <&gpio1 17 1>;
+                        linux,default-trigger = "default-on";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug.dts b/arch/arm/boot/dts/kirkwood-sheevaplug.dts
new file mode 100644
index 000000000000..bf1dff251432
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug.dts
@@ -0,0 +1,43 @@
+/*
+ * kirkwood-sheevaplug-esata.dts - Device tree file for Sheevaplug
+ *
+ * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com>
+ *
+ * Licensed under GPLv2
+ */
+
+/dts-v1/;
+
+/include/ "kirkwood-sheevaplug-common.dtsi"
+
+/ {
+        model = "Globalscale Technologies SheevaPlug";
+        compatible = "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+        ocp@f1000000 {
+                mvsdio@90000 {
+                        pinctrl-0 = <&pmx_sdio>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                        /* No CD or WP GPIOs */
+                        broken-cd;
+                };
+        };
+
+        gpio-leds {
+                compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_blue &pmx_led_red>;
+                pinctrl-names = "default";
+
+                health {
+                        label = "sheevaplug:blue:health";
+                        gpios = <&gpio1 17 1>;
+                        linux,default-trigger = "default-on";
+                };
+
+                misc {
+                        label = "sheevaplug:red:misc";
+                        gpios = <&gpio1 14 1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts
index 66eb45b00b25..f2052d7bc10f 100644
--- a/arch/arm/boot/dts/kirkwood-topkick.dts
+++ b/arch/arm/boot/dts/kirkwood-topkick.dts
@@ -19,18 +19,6 @@
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
                         /*
-                         * GPIO LED layout
-                         *
-                         *       /-SYS_LED(2)
-                         *       |
-                         *       |   /-DISK_LED
-                         *       |   |
-                         *       |   |   /-WLAN_LED(2)
-                         *       |   |   |
-                         * [SW] [*] [*] [*]
-                         */
-
-                        /*
                          * Switch positions
                          *
                          *     /-SW_LEFT(2)
@@ -41,19 +29,8 @@
                          *     |   |   |
                          * PS [L] [I] [R] LEDS
                          */
-                        pinctrl-0 = < &pmx_led_disk_yellow
-                                      &pmx_sata0_pwr_enable
-                                      &pmx_led_sys_red
-                                      &pmx_led_sys_blue
-                                      &pmx_led_wifi_green
-                                      &pmx_sw_left
-                                      &pmx_sw_right
-                                      &pmx_sw_idle
-                                      &pmx_sw_left2
-                                      &pmx_led_wifi_yellow
-                                      &pmx_uart0
-                                      &pmx_nand
-                                      &pmx_twsi0 >;
+                        pinctrl-0 = <&pmx_sw_left &pmx_sw_right
+                                     &pmx_sw_idle &pmx_sw_left2>;
                         pinctrl-names = "default";
 
                         pmx_led_disk_yellow: pmx-led-disk-yellow {
@@ -109,10 +86,14 @@
 
                 serial@12000 {
                         status = "ok";
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
                 };
 
                 nand@3000000 {
                         status = "okay";
+                        pinctrl-0 = <&pmx_nand>;
+                        pinctrl-names = "default";
 
                         partition@0 {
                                 label = "u-boot";
@@ -147,6 +128,8 @@
 
                 i2c@11000 {
                         status = "ok";
+                        pinctrl-0 = <&pmx_twsi0>;
+                        pinctrl-names = "default";
                 };
 
                 mvsdio@90000 {
@@ -154,11 +137,28 @@
                         pinctrl-names = "default";
                         status = "okay";
                         /* No CD or WP GPIOs */
+                        broken-cd;
                 };
         };
 
         gpio-leds {
+                /*
+                 * GPIO LED layout
+                 *
+                 *       /-SYS_LED(2)
+                 *       |
+                 *       |   /-DISK_LED
+                 *       |   |
+                 *       |   |   /-WLAN_LED(2)
+                 *       |   |   |
+                 * [SW] [*] [*] [*]
+                 */
+
                 compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_disk_yellow &pmx_led_sys_red
+                             &pmx_led_sys_blue &pmx_led_wifi_green
+                             &pmx_led_wifi_yellow>;
+                pinctrl-names = "default";
 
                 disk {
                         label = "topkick:yellow:disk";
@@ -187,6 +187,8 @@
                 compatible = "simple-bus";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = <&pmx_sata0_pwr_enable>;
+                pinctrl-names = "default";
 
                 sata0_power: regulator@1 {
                         compatible = "regulator-fixed";
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
index 42648ab77c61..6dd1038e4de4 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
@@ -8,10 +8,7 @@
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
 
-                        pinctrl-0 = < &pmx_uart0 &pmx_uart1 &pmx_spi
-                                      &pmx_twsi0 &pmx_sata0 &pmx_sata1
-                                      &pmx_ram_size &pmx_reset_button
-                                      &pmx_USB_copy_button &pmx_board_id>;
+                        pinctrl-0 = <&pmx_ram_size &pmx_board_id>;
                         pinctrl-names = "default";
 
                         pmx_ram_size: pmx-ram-size {
@@ -39,6 +36,9 @@
                 compatible = "gpio-keys";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>;
+                pinctrl-names = "default";
+
                 button@1 {
                         label = "USB Copy";
                         linux,code = <133>;
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
index 95ceeb93ba5a..6fdc5ffcaae5 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
@@ -8,10 +8,7 @@
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
 
-                        pinctrl-0 = < &pmx_uart0 &pmx_uart1 &pmx_spi
-                                      &pmx_twsi0 &pmx_sata0 &pmx_sata1
-                                      &pmx_ram_size &pmx_reset_button
-                                      &pmx_USB_copy_button &pmx_board_id>;
+                        pinctrl-0 = <&pmx_ram_size &pmx_board_id>;
                         pinctrl-names = "default";
 
                         pmx_ram_size: pmx-ram-size {
@@ -33,12 +30,23 @@
                                 marvell,function = "gpio";
                         };
                 };
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@2,0 {
+                                status = "okay";
+                        };
+                };
+
         };
 
         gpio_keys {
                 compatible = "gpio-keys";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>;
+                pinctrl-names = "default";
+
                 button@1 {
                         label = "USB Copy";
                         linux,code = <133>;
diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi
index 09c820fc177f..0c9a94cd666c 100644
--- a/arch/arm/boot/dts/kirkwood-ts219.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi
@@ -15,6 +15,8 @@
                 i2c@11000 {
                         status = "okay";
                         clock-frequency = <400000>;
+                        pinctrl-0 = <&pmx_twsi0>;
+                        pinctrl-names = "default";
 
                         s35390a: s35390a@30 {
                                 compatible = "s35390a";
@@ -24,10 +26,14 @@
                 serial@12000 {
                         clock-frequency = <200000000>;
                         status = "okay";
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
                 };
                 serial@12100 {
                         clock-frequency = <200000000>;
                         status = "okay";
+                        pinctrl-0 = <&pmx_uart1>;
+                        pinctrl-names = "default";
                 };
                 poweroff@12100 {
                         compatible = "qnap,power-off";
@@ -36,6 +42,8 @@
                 };
                 spi@10600 {
                         status = "okay";
+                        pinctrl-0 = <&pmx_spi>;
+                        pinctrl-names = "default";
 
                         m25p128@0 {
                                 #address-cells = <1>;
@@ -74,6 +82,8 @@
                         };
                 };
                 sata@80000 {
+                        pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
+                        pinctrl-names = "default";
                         status = "okay";
                         nr-ports = <2>;
                 };
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 7eef88f00fea..9809fc1f105c 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -4,6 +4,18 @@
         compatible = "marvell,kirkwood";
         interrupt-parent = <&intc>;
 
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "marvell,feroceon";
+                        clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
+                        clock-names = "cpu_clk", "ddrclk", "powersave";
+                };
+        };
+
         aliases {
                gpio0 = &gpio0;
                gpio1 = &gpio1;
@@ -18,8 +30,9 @@
 
         ocp@f1000000 {
                 compatible = "simple-bus";
-                ranges = <0x00000000 0xf1000000 0x4000000
+                ranges = <0x00000000 0xf1000000 0x0100000
                           0xe0000000 0xe0000000 0x8100000 /* PCIE */
+                          0xf4000000 0xf4000000 0x0000400
                           0xf5000000 0xf5000000 0x0000400>;
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -72,13 +85,6 @@
                         status = "disabled";
                 };
 
-                rtc@10300 {
-                        compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
-                        reg = <0x10300 0x20>;
-                        interrupts = <53>;
-                        clocks = <&gate_clk 7>;
-                };
-
                 spi@10600 {
                         compatible = "marvell,orion-spi";
                         #address-cells = <1>;
@@ -152,15 +158,6 @@
                         status = "okay";
                 };
 
-                sata@80000 {
-                        compatible = "marvell,orion-sata";
-                        reg = <0x80000 0x5000>;
-                        interrupts = <21>;
-                        clocks = <&gate_clk 14>, <&gate_clk 15>;
-                        clock-names = "0", "1";
-                        status = "disabled";
-                };
-
                 nand@3000000 {
                         #address-cells = <1>;
                         #size-cells = <1>;
@@ -168,7 +165,7 @@
                         ale = <1>;
                         bank-width = <1>;
                         compatible = "marvell,orion-nand";
-                        reg = <0x3000000 0x400>;
+                        reg = <0xf4000000 0x400>;
                         chip-delay = <25>;
                         /* set partition map and/or chip-delay in board dts */
                         clocks = <&gate_clk 7>;
@@ -195,13 +192,5 @@
                         clocks = <&gate_clk 17>;
                         status = "okay";
                 };
-
-                mvsdio@90000 {
-                        compatible = "marvell,orion-sdio";
-                        reg = <0x90000 0x200>;
-                        interrupts = <28>;
-                        clocks = <&gate_clk 4>;
-                        status = "disabled";
-                };
         };
 };
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 1582f484a867..3abebb75fc57 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -18,8 +18,12 @@
         interrupt-parent = <&mic>;
 
         cpus {
-                cpu@0 {
-                        compatible = "arm,arm926ejs";
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                 };
         };
 
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 37aa7487d4d8..a2bfcde858a6 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -8,7 +8,10 @@
  * kind, whether express or implied.
  */
 
-/include/ "skeleton.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/omap.h>
+
+#include "skeleton.dtsi"
 
 / {
         compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
@@ -21,8 +24,12 @@
         };
 
         cpus {
-                cpu@0 {
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
                         compatible = "arm,arm1136jf-s";
+                        device_type = "cpu";
                 };
         };
 
diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts
index 68282ee13e26..224c08f472f4 100644
--- a/arch/arm/boot/dts/omap2420-h4.dts
+++ b/arch/arm/boot/dts/omap2420-h4.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap2420.dtsi"
+#include "omap2420.dtsi"
 
 / {
         model = "TI OMAP2420 H4 board";
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index da5b285b73be..c8f9c55169ea 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap2.dtsi"
+#include "omap2.dtsi"
 
 / {
         compatible = "ti,omap2420", "ti,omap2";
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 054bc4439568..c535a5a2b27f 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap2.dtsi"
+#include "omap2.dtsi"
 
 / {
         compatible = "ti,omap2430", "ti,omap2";
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 3046d1f81be0..afdb16417d4e 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap36xx.dtsi"
+#include "omap36xx.dtsi"
 
 / {
         model = "TI OMAP3 BeagleBoard xM";
@@ -29,13 +29,13 @@
 
                 heartbeat {
                         label = "beagleboard::usr0";
-                        gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
+                        gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
                         linux,default-trigger = "heartbeat";
                 };
 
                 mmc {
                         label = "beagleboard::usr1";
-                        gpios = <&gpio5 21 0>; /* 149 -> D7 LED */
+                        gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
                         linux,default-trigger = "mmc0";
                 };
         };
@@ -57,6 +57,26 @@
                 ti,mcbsp = <&mcbsp2>;
                 ti,codec = <&twl_audio>;
         };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+
+                user {
+                        label = "user";
+                        gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+                        linux,code = <0x114>;
+                        gpio-key,wakeup;
+                };
+
+        };
+};
+
+&omap3_pmx_wkup {
+        gpio1_pins: pinmux_gpio1_pins {
+                pinctrl-single,pins = <
+                        0x0e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot2.gpio_4 */
+                >;
+        };
 };
 
 &i2c1 {
@@ -75,7 +95,8 @@
         };
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
 
 &i2c2 {
         clock-frequency = <400000>;
@@ -126,3 +147,22 @@
         mode = <3>;
         power = <50>;
 };
+
+&omap3_pmx_core {
+        uart3_pins: pinmux_uart3_pins {
+                pinctrl-single,pins = <
+                        0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+                        0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
+                >;
+        };
+};
+
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins>;
+};
+
+&gpio1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&gpio1_pins>;
+};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 6eec69997607..dfd83103657a 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
         model = "TI OMAP3 BeagleBoard";
@@ -28,18 +28,18 @@
                 compatible = "gpio-leds";
                 pmu_stat {
                         label = "beagleboard::pmu_stat";
-                        gpios = <&twl_gpio 19 0>; /* LEDB */
+                        gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */
                 };
 
                 heartbeat {
                         label = "beagleboard::usr0";
-                        gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
+                        gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
                         linux,default-trigger = "heartbeat";
                 };
 
                 mmc {
                         label = "beagleboard::usr1";
-                        gpios = <&gpio5 21 0>; /* 149 -> D7 LED */
+                        gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
                         linux,default-trigger = "mmc0";
                 };
         };
@@ -71,6 +71,26 @@
                 reset-supply = <&hsusb2_reset>;
                 vcc-supply = <&hsusb2_power>;
         };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+
+                user {
+                        label = "user";
+                        gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+                        linux,code = <0x114>;
+                        gpio-key,wakeup;
+                };
+
+        };
+};
+
+&omap3_pmx_wkup {
+        gpio1_pins: pinmux_gpio1_pins {
+                pinctrl-single,pins = <
+                        0x14 (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */
+                >;
+        };
 };
 
 &omap3_pmx_core {
@@ -81,18 +101,25 @@
 
         hsusbb2_pins: pinmux_hsusbb2_pins {
                 pinctrl-single,pins = <
-                        0x5c0 0x3  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk OUTPUT */
-                        0x5c2 0x3  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_stp OUTPUT */
-                        0x5c4 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dir INPUT | PULLDOWN */
-                        0x5c6 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_nxt INPUT | PULLDOWN */
-                        0x5c8 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat0 INPUT | PULLDOWN */
-                        0x5cA 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat1 INPUT | PULLDOWN */
-                        0x1a4 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat2 INPUT | PULLDOWN */
-                        0x1a6 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat3 INPUT | PULLDOWN */
-                        0x1a8 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat4 INPUT | PULLDOWN */
-                        0x1aa 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat5 INPUT | PULLDOWN */
-                        0x1ac 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat6 INPUT | PULLDOWN */
-                        0x1ae 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 INPUT | PULLDOWN */
+                        0x5c0 (PIN_OUTPUT | MUX_MODE3)          /* usbb2_ulpitll_clk.usbb1_ulpiphy_clk */
+                        0x5c2 (PIN_OUTPUT | MUX_MODE3)          /* usbb2_ulpitll_clk.usbb1_ulpiphy_stp */
+                        0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_dir */
+                        0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_nxt */
+                        0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat0 */
+                        0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat1 */
+                        0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat2 */
+                        0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat3 */
+                        0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat4 */
+                        0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat5 */
+                        0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat6 */
+                        0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat7 */
+                >;
+        };
+
+        uart3_pins: pinmux_uart3_pins {
+                pinctrl-single,pins = <
+                        0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+                        0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
                 >;
         };
 };
@@ -107,7 +134,8 @@
         };
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
 
 &mmc1 {
         vmmc-supply = <&vmmc1>;
@@ -142,3 +170,13 @@
          */
         ti,pulldowns = <0x03a1c4>;
 };
+
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins>;
+};
+
+&gpio1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&gpio1_pins>;
+};
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts
index 8a5cdcc6debd..af32eff9f4b7 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 / {
         model = "TimLL OMAP3 Devkit8000";
         compatible = "timll,omap3-devkit8000", "ti,omap3";
@@ -22,21 +22,21 @@
 
                 heartbeat {
                         label = "devkit8000::led1";
-                        gpios = <&gpio6 26 0>;  /* 186 -> LED1 */
+                        gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>;   /* 186 -> LED1 */
                         default-state = "on";
                         linux,default-trigger = "heartbeat";
                 };
 
                 mmc {
                         label = "devkit8000::led2";
-                        gpios = <&gpio6 3 0>;   /* 163 -> LED2 */
+                        gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>;    /* 163 -> LED2 */
                         default-state = "on";
                         linux,default-trigger = "none";
                 };
 
                 usr {
                         label = "devkit8000::led3";
-                        gpios = <&gpio6 4 0>;   /* 164 -> LED3 */
+                        gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>;    /* 164 -> LED3 */
                         default-state = "on";
                         linux,default-trigger = "usr";
                 };
@@ -80,7 +80,8 @@
         status = "disabled";
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
 
 &mmc1 {
         vmmc-supply = <&vmmc1>;
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index 96d1c206a57b..7d4329d179c4 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
         model = "TI OMAP3 EVM (OMAP3530, AM/DM37x)";
@@ -28,7 +28,7 @@
                 compatible = "gpio-leds";
                 ledb {
                         label = "omap3evm::ledb";
-                        gpios = <&twl_gpio 19 0>; /* LEDB */
+                        gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */
                         linux,default-trigger = "default-on";
                 };
         };
@@ -44,7 +44,8 @@
         };
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
 
 &i2c2 {
         clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index f8fe3b748c3e..bc48b114eae6 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -10,7 +10,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
         memory {
@@ -29,37 +29,43 @@
 &omap3_pmx_core {
         uart1_pins: pinmux_uart1_pins {
                 pinctrl-single,pins = <
-                        0x152 0x100     /* uart1_rx.uart1_rx INPUT | MODE0 */
-                        0x14c 0         /* uart1_tx.uart1_tx OUTPUT | MODE0 */
+                        0x152 (PIN_INPUT | MUX_MODE0)           /* uart1_rx.uart1_rx */
+                        0x14c (PIN_OUTPUT |MUX_MODE0)           /* uart1_tx.uart1_tx */
                 >;
         };
 
         uart2_pins: pinmux_uart2_pins {
                 pinctrl-single,pins = <
-                        0x14a 0x100     /* uart2_rx.uart2_rx INPUT | MODE0 */
-                        0x148 0         /* uart2_tx.uart2_tx OUTPUT | MODE0 */
+                        0x14a (PIN_INPUT | MUX_MODE0)           /* uart2_rx.uart2_rx */
+                        0x148 (PIN_OUTPUT | MUX_MODE0)          /* uart2_tx.uart2_tx */
                 >;
         };
 
         uart3_pins: pinmux_uart3_pins {
                 pinctrl-single,pins = <
-                        0x16e 0x100     /* uart3_rx.uart3_rx INPUT | MODE0 */
-                        0x170 0         /* uart3_tx.uart3_tx OUTPUT | MODE0 */
+                        0x16e (PIN_INPUT | MUX_MODE0)           /* uart3_rx.uart3_rx */
+                        0x170 (PIN_OUTPUT | MUX_MODE0)          /* uart3_tx.uart3_tx */
                 >;
         };
 
         mmc1_pins: pinmux_mmc1_pins {
                 pinctrl-single,pins = <
-                        0x114 0x0118    /* sdmmc1_clk.sdmmc1_clk INPUT PULLUP | MODE 0 */
-                        0x116 0x0118    /* sdmmc1_cmd.sdmmc1_cmd INPUT PULLUP | MODE 0 */
-                        0x118 0x0118    /* sdmmc1_dat0.sdmmc1_dat0 INPUT PULLUP | MODE 0 */
-                        0x11a 0x0118    /* sdmmc1_dat1.sdmmc1_dat1 INPUT PULLUP | MODE 0 */
-                        0x11c 0x0118    /* sdmmc1_dat2.sdmmc1_dat2 INPUT PULLUP | MODE 0 */
-                        0x11e 0x0118    /* sdmmc1_dat3.sdmmc1_dat3 INPUT PULLUP | MODE 0 */
-                        0x120 0x0100    /* sdmmc1_dat4.sdmmc1_dat4 INPUT | MODE 0 */
-                        0x122 0x0100    /* sdmmc1_dat5.sdmmc1_dat5 INPUT | MODE 0 */
-                        0x124 0x0100    /* sdmmc1_dat6.sdmmc1_dat6 INPUT | MODE 0 */
-                        0x126 0x0100    /* sdmmc1_dat7.sdmmc1_dat7 INPUT | MODE 0 */
+                        0x114 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_clk.sdmmc1_clk */
+                        0x116 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_cmd.sdmmc1_cmd */
+                        0x118 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat0.sdmmc1_dat0 */
+                        0x11a (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat1.sdmmc1_dat1 */
+                        0x11c (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat2.sdmmc1_dat2 */
+                        0x11e (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat3.sdmmc1_dat3 */
+                        0x120 (PIN_INPUT | MUX_MODE0)           /* sdmmc1_dat4.sdmmc1_dat4 */
+                        0x122 (PIN_INPUT | MUX_MODE0)           /* sdmmc1_dat5.sdmmc1_dat5 */
+                        0x124 (PIN_INPUT | MUX_MODE0)           /* sdmmc1_dat6.sdmmc1_dat6 */
+                        0x126 (PIN_INPUT | MUX_MODE0)           /* sdmmc1_dat7.sdmmc1_dat7 */
+                >;
+        };
+
+        smsc911x_pins: pinmux_smsc911x_pins {
+                pinctrl-single,pins = <
+                        0x1a2 (PIN_INPUT | MUX_MODE4)           /* mcspi1_cs2.gpio_176 */
                 >;
         };
 };
@@ -80,7 +86,8 @@
         };
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
 
 &i2c2 {
         clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index e2b98490cc9a..e8c48284587c 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -9,7 +9,7 @@
  * published by the Free Software Foundation.
  */
 
-/include/ "omap3-igep.dtsi"
+#include "omap3-igep.dtsi"
 
 / {
         model = "IGEPv2";
@@ -19,27 +19,39 @@
                 compatible = "gpio-leds";
                 boot {
                          label = "omap3:green:boot";
-                         gpios = <&gpio1 26 0>;
+                         gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
                          default-state = "on";
                 };
 
                 user0 {
                          label = "omap3:red:user0";
-                         gpios = <&gpio1 27 0>;
+                         gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
                          default-state = "off";
                 };
 
                 user1 {
                          label = "omap3:red:user1";
-                         gpios = <&gpio1 28 0>;
+                         gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
                          default-state = "off";
                 };
 
                 user2 {
                         label = "omap3:green:user1";
-                        gpios = <&twl_gpio 19 1>;
+                        gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;
                 };
         };
+
+        vddvario: regulator-vddvario {
+                  compatible = "regulator-fixed";
+                  regulator-name = "vddvario";
+                  regulator-always-on;
+        };
+
+        vdd33a: regulator-vdd33a {
+                compatible = "regulator-fixed";
+                regulator-name = "vdd33a";
+                regulator-always-on;
+        };
 };
 
 &i2c3 {
@@ -54,3 +66,92 @@
                 reg = <0x50>;
         };
 };
+
+&gpmc {
+        ranges = <0 0 0x00000000 0x20000000>,
+                 <5 0 0x2c000000 0x01000000>;
+
+        nand@0,0 {
+                linux,mtd-name= "micron,mt29c4g96maz";
+                reg = <0 0 0>;
+                nand-bus-width = <16>;
+                ti,nand-ecc-opt = "bch8";
+
+                gpmc,sync-clk-ps = <0>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <44>;
+                gpmc,cs-wr-off-ns = <44>;
+                gpmc,adv-on-ns = <6>;
+                gpmc,adv-rd-off-ns = <34>;
+                gpmc,adv-wr-off-ns = <44>;
+                gpmc,we-off-ns = <40>;
+                gpmc,oe-off-ns = <54>;
+                gpmc,access-ns = <64>;
+                gpmc,rd-cycle-ns = <82>;
+                gpmc,wr-cycle-ns = <82>;
+                gpmc,wr-access-ns = <40>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                partition@0 {
+                        label = "SPL";
+                        reg = <0 0x100000>;
+                };
+                partition@0x80000 {
+                        label = "U-Boot";
+                        reg = <0x100000 0x180000>;
+                };
+                partition@0x1c0000 {
+                        label = "Environment";
+                        reg = <0x280000 0x100000>;
+                };
+                partition@0x280000 {
+                        label = "Kernel";
+                        reg = <0x380000 0x300000>;
+                };
+                partition@0x780000 {
+                        label = "Filesystem";
+                        reg = <0x680000 0x1f980000>;
+                };
+        };
+
+        ethernet@5,0 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&smsc911x_pins>;
+                compatible = "smsc,lan9221", "smsc,lan9115";
+                reg = <5 0 0xff>;
+                bank-width = <2>;
+
+                gpmc,mux-add-data;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <186>;
+                gpmc,cs-wr-off-ns = <186>;
+                gpmc,adv-on-ns = <12>;
+                gpmc,adv-rd-off-ns = <48>;
+                gpmc,adv-wr-off-ns = <48>;
+                gpmc,oe-on-ns = <54>;
+                gpmc,oe-off-ns = <168>;
+                gpmc,we-on-ns = <54>;
+                gpmc,we-off-ns = <168>;
+                gpmc,rd-cycle-ns = <186>;
+                gpmc,wr-cycle-ns = <186>;
+                gpmc,access-ns = <114>;
+                gpmc,page-burst-access-ns = <6>;
+                gpmc,bus-turnaround-ns = <12>;
+                gpmc,cycle2cycle-delay-ns = <18>;
+                gpmc,wr-data-mux-bus-ns = <90>;
+                gpmc,wr-access-ns = <186>;
+                gpmc,cycle2cycle-samecsen;
+                gpmc,cycle2cycle-diffcsen;
+
+                interrupt-parent = <&gpio6>;
+                interrupts = <16 8>;
+                vmmc-supply = <&vddvario>;
+                vmmc_aux-supply = <&vdd33a>;
+                reg-io-width = <4>;
+
+                smsc,save-mac-address;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts
index 9dc48d262ffb..644d05383836 100644
--- a/arch/arm/boot/dts/omap3-igep0030.dts
+++ b/arch/arm/boot/dts/omap3-igep0030.dts
@@ -9,7 +9,7 @@
  * published by the Free Software Foundation.
  */
 
-/include/ "omap3-igep.dtsi"
+#include "omap3-igep.dtsi"
 
 / {
         model = "IGEP COM Module";
@@ -19,26 +19,76 @@
                 compatible = "gpio-leds";
                 boot {
                          label = "omap3:green:boot";
-                         gpios = <&twl_gpio 13 1>;
+                         gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>;
                          default-state = "on";
                 };
 
                 user0 {
                          label = "omap3:red:user0";
-                         gpios = <&twl_gpio 18 1>; /* LEDA */
+                         gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */
                          default-state = "off";
                 };
 
                 user1 {
                          label = "omap3:green:user1";
-                         gpios = <&twl_gpio 19 1>; /* LEDB */
+                         gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */
                          default-state = "off";
                 };
 
                 user2 {
                          label = "omap3:red:user1";
-                         gpios = <&gpio1 16 1>;
+                         gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
                          default-state = "off";
                 };
         };
 };
+
+&gpmc {
+        ranges = <0 0 0x00000000 0x20000000>;
+
+        nand@0,0 {
+                linux,mtd-name= "micron,mt29c4g96maz";
+                reg = <0 0 0>;
+                nand-bus-width = <16>;
+                ti,nand-ecc-opt = "bch8";
+
+                gpmc,sync-clk-ps = <0>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <44>;
+                gpmc,cs-wr-off-ns = <44>;
+                gpmc,adv-on-ns = <6>;
+                gpmc,adv-rd-off-ns = <34>;
+                gpmc,adv-wr-off-ns = <44>;
+                gpmc,we-off-ns = <40>;
+                gpmc,oe-off-ns = <54>;
+                gpmc,access-ns = <64>;
+                gpmc,rd-cycle-ns = <82>;
+                gpmc,wr-cycle-ns = <82>;
+                gpmc,wr-access-ns = <40>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                partition@0 {
+                        label = "SPL";
+                        reg = <0 0x100000>;
+                };
+                partition@0x80000 {
+                        label = "U-Boot";
+                        reg = <0x100000 0x180000>;
+                };
+                partition@0x1c0000 {
+                        label = "Environment";
+                        reg = <0x280000 0x100000>;
+                };
+                partition@0x280000 {
+                        label = "Kernel";
+                        reg = <0x380000 0x300000>;
+                };
+                partition@0x780000 {
+                        label = "Filesystem";
+                        reg = <0x680000 0x1f980000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi
index a626c50041f6..8f1abec78275 100644
--- a/arch/arm/boot/dts/omap3-overo.dtsi
+++ b/arch/arm/boot/dts/omap3-overo.dtsi
@@ -11,7 +11,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
         pwmleds {
@@ -21,6 +21,7 @@
                         label = "overo:blue:COM";
                         pwms = <&twl_pwmled 1 7812500>;
                         max-brightness = <127>;
+                        linux,default-trigger = "mmc0";
                 };
         };
 
@@ -49,7 +50,8 @@
         };
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
 
 /* i2c2 pins are used for gpio */
 &i2c2 {
@@ -77,3 +79,17 @@
         mode = <3>;
         power = <50>;
 };
+
+&omap3_pmx_core {
+        uart3_pins: pinmux_uart3_pins {
+                pinctrl-single,pins = <
+                        0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+                        0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
+                >;
+        };
+};
+
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins>;
+};
diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-tobi.dts
index a13d12de77ff..7e4ad2aec37a 100644
--- a/arch/arm/boot/dts/omap3-tobi.dts
+++ b/arch/arm/boot/dts/omap3-tobi.dts
@@ -10,7 +10,7 @@
  * Tobi expansion board is manufactured by Gumstix Inc.
  */
 
-/include/ "omap3-overo.dtsi"
+#include "omap3-overo.dtsi"
 
 / {
         model = "TI OMAP3 Gumstix Overo on Tobi";
@@ -20,10 +20,58 @@
                 compatible = "gpio-leds";
                 heartbeat {
                         label = "overo:red:gpio21";
-                        gpios = <&gpio1 21 0>;
+                        gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
                         linux,default-trigger = "heartbeat";
                 };
         };
+
+        vddvario: regulator-vddvario {
+                  compatible = "regulator-fixed";
+                  regulator-name = "vddvario";
+                  regulator-always-on;
+        };
+
+        vdd33a: regulator-vdd33a {
+                compatible = "regulator-fixed";
+                regulator-name = "vdd33a";
+                regulator-always-on;
+        };
+};
+
+&gpmc {
+        ranges = <5 0 0x2c000000 0x1000000>;    /* CS5 */
+
+        ethernet@5,0 {
+                compatible = "smsc,lan9221", "smsc,lan9115";
+                reg = <5 0 0xff>;
+                bank-width = <2>;
+
+                gpmc,mux-add-data;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <42>;
+                gpmc,cs-wr-off-ns = <36>;
+                gpmc,adv-on-ns = <6>;
+                gpmc,adv-rd-off-ns = <12>;
+                gpmc,adv-wr-off-ns = <12>;
+                gpmc,oe-on-ns = <0>;
+                gpmc,oe-off-ns = <42>;
+                gpmc,we-on-ns = <0>;
+                gpmc,we-off-ns = <36>;
+                gpmc,rd-cycle-ns = <60>;
+                gpmc,wr-cycle-ns = <54>;
+                gpmc,access-ns = <36>;
+                gpmc,page-burst-access-ns = <0>;
+                gpmc,bus-turnaround-ns = <0>;
+                gpmc,cycle2cycle-delay-ns = <0>;
+                gpmc,wr-data-mux-bus-ns = <18>;
+                gpmc,wr-access-ns = <42>;
+                gpmc,cycle2cycle-samecsen;
+                gpmc,cycle2cycle-diffcsen;
+
+                interrupt-parent = <&gpio6>;
+                interrupts = <16 IRQ_TYPE_LEVEL_LOW>;   /* GPIO 176 */
+                reg-io-width = <4>;
+        };
 };
 
 &i2c3 {
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 99ba6e14ebf3..7d95cda1fae4 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -8,7 +8,11 @@
  * kind, whether express or implied.
  */
 
-/include/ "skeleton.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/omap.h>
+
+#include "skeleton.dtsi"
 
 / {
         compatible = "ti,omap3430", "ti,omap3";
@@ -21,8 +25,13 @@
         };
 
         cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
                 cpu@0 {
                         compatible = "arm,cortex-a8";
+                        device_type = "cpu";
+                        reg = <0x0>;
                 };
         };
 
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts
index 144ae43453c4..c4a1c0a97728 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
         model = "TI OMAP3430 SDP";
@@ -28,7 +28,8 @@
         };
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
 
 &mmc1 {
         vmmc-supply = <&vmmc1>;
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 75ed4ae2e631..5355d6173748 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap3.dtsi"
+#include "omap3.dtsi"
 
 / {
         cpus {
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index f3447bc1b032..f8b3765eb9be 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap3.dtsi"
+#include "omap3.dtsi"
 
 / {
         aliases {
diff --git a/arch/arm/boot/dts/omap4-panda-a4.dts b/arch/arm/boot/dts/omap4-panda-a4.dts
index e30cdf0f5ac1..133f1b74e8ae 100644
--- a/arch/arm/boot/dts/omap4-panda-a4.dts
+++ b/arch/arm/boot/dts/omap4-panda-a4.dts
@@ -7,14 +7,14 @@
  */
 /dts-v1/;
 
-/include/ "omap443x.dtsi"
-/include/ "omap4-panda-common.dtsi"
+#include "omap443x.dtsi"
+#include "omap4-panda-common.dtsi"
 
 /* Pandaboard Rev A4+ have external pullups on SCL & SDA */
 &dss_hdmi_pins {
         pinctrl-single,pins = <
-                0x5a 0x118      /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
-                0x5c 0x100      /* hdmi_scl.hdmi_scl INPUT | MODE 0 */
-                0x5e 0x100      /* hdmi_sda.hdmi_sda INPUT | MODE 0 */
+                0x5a (PIN_INPUT_PULLUP | MUX_MODE0)     /* hdmi_cec.hdmi_cec */
+                0x5c (PIN_INPUT | MUX_MODE0)            /* hdmi_scl.hdmi_scl */
+                0x5e (PIN_INPUT | MUX_MODE0)            /* hdmi_sda.hdmi_sda */
                 >;
 };
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index eeb734e25709..faa95b5b242e 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -5,7 +5,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-/include/ "elpida_ecb240abacn.dtsi"
+#include "elpida_ecb240abacn.dtsi"
 
 / {
         model = "TI OMAP4 PandaBoard";
@@ -16,17 +16,22 @@
                 reg = <0x80000000 0x40000000>; /* 1 GB */
         };
 
-        leds {
+        leds: leds {
                 compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <
+                        &led_wkgpio_pins
+                >;
+
                 heartbeat {
                         label = "pandaboard::status1";
-                        gpios = <&gpio1 7 0>;
+                        gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
                         linux,default-trigger = "heartbeat";
                 };
 
                 mmc {
                         label = "pandaboard::status2";
-                        gpios = <&gpio1 8 0>;
+                        gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
                         linux,default-trigger = "mmc0";
                 };
         };
@@ -54,6 +59,54 @@
                         "AFML", "Line In",
                         "AFMR", "Line In";
         };
+
+        /*
+         * Temp hack: Need to be replaced with the proper gpio-controlled
+         * reset driver as soon it will be merged.
+         * http://thread.gmane.org/gmane.linux.drivers.devicetree/36830
+         */
+        /* HS USB Port 1 RESET */
+        hsusb1_reset: hsusb1_reset_reg {
+                compatible = "regulator-fixed";
+                regulator-name = "hsusb1_reset";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio2 30 0>;   /* gpio_62 */
+                startup-delay-us = <70000>;
+                enable-active-high;
+        };
+
+        /* HS USB Port 1 Power */
+        hsusb1_power: hsusb1_power_reg {
+                compatible = "regulator-fixed";
+                regulator-name = "hsusb1_vbus";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio1 1 0>;    /* gpio_1 */
+                startup-delay-us = <70000>;
+                enable-active-high;
+                /*
+                 * boot-on is required along with always-on as the
+                 * regulator framework doesn't enable the regulator
+                 * if boot-on is not there.
+                 */
+                regulator-always-on;
+                regulator-boot-on;
+        };
+
+        /* HS USB Host PHY on PORT 1 */
+        hsusb1_phy: hsusb1_phy {
+                compatible = "usb-nop-xceiv";
+                reset-supply = <&hsusb1_reset>;
+                vcc-supply = <&hsusb1_power>;
+        /**
+         * FIXME:
+         * put the right clock phandle here when available
+         *      clocks = <&auxclk3>;
+         *      clock-names = "main_clk";
+         */
+                clock-frequency = <19200000>;
+        };
 };
 
 &omap4_pmx_wkup {
@@ -64,7 +117,7 @@
 
         twl6030_wkup_pins: pinmux_twl6030_wkup_pins {
                 pinctrl-single,pins = <
-                        0x14 0x2        /* fref_clk0_out.sys_drm_msecure OUTPUT | MODE2 */
+                        0x14 (PIN_OUTPUT | MUX_MODE2)           /* fref_clk0_out.sys_drm_msecure */
                 >;
         };
 };
@@ -78,81 +131,108 @@
                         &mcbsp1_pins
                         &dss_hdmi_pins
                         &tpd12s015_pins
+                        &hsusbb1_pins
         >;
 
         twl6030_pins: pinmux_twl6030_pins {
                 pinctrl-single,pins = <
-                        0x15e 0x4118    /* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */
+                        0x15e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0)        /* sys_nirq1.sys_nirq1 */
                 >;
         };
 
         twl6040_pins: pinmux_twl6040_pins {
                 pinctrl-single,pins = <
-                        0xe0 0x3        /* hdq_sio.gpio_127 OUTPUT | MODE3 */
-                        0x160 0x100     /* sys_nirq2.sys_nirq2 INPUT | MODE0 */
+                        0xe0 (PIN_OUTPUT | MUX_MODE3)   /* hdq_sio.gpio_127 */
+                        0x160 (PIN_INPUT | MUX_MODE0)   /* sys_nirq2.sys_nirq2 */
                 >;
         };
 
         mcpdm_pins: pinmux_mcpdm_pins {
                 pinctrl-single,pins = <
-                        0xc6 0x108      /* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */
-                        0xc8 0x108      /* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */
-                        0xca 0x118      /* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */
-                        0xcc 0x108      /* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */
-                        0xce 0x108      /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
+                        0xc6 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_pdm_ul_data.abe_pdm_ul_data */
+                        0xc8 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_pdm_dl_data.abe_pdm_dl_data */
+                        0xca (PIN_INPUT_PULLUP   | MUX_MODE0)   /* abe_pdm_frame.abe_pdm_frame */
+                        0xcc (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_pdm_lb_clk.abe_pdm_lb_clk */
+                        0xce (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_clks.abe_clks */
                 >;
         };
 
         mcbsp1_pins: pinmux_mcbsp1_pins {
                 pinctrl-single,pins = <
-                        0xbe 0x100      /* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */
-                        0xc0 0x108      /* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */
-                        0xc2 0x8                /* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */
-                        0xc4 0x100      /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */
+                        0xbe (PIN_INPUT | MUX_MODE0)            /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */
+                        0xc0 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_mcbsp1_dr.abe_mcbsp1_dr */
+                        0xc2 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)  /* abe_mcbsp1_dx.abe_mcbsp1_dx */
+                        0xc4 (PIN_INPUT | MUX_MODE0)            /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */
                 >;
         };
 
         dss_hdmi_pins: pinmux_dss_hdmi_pins {
                 pinctrl-single,pins = <
-                        0x5a 0x118      /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
-                        0x5c 0x118      /* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */
-                        0x5e 0x118      /* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */
+                        0x5a (PIN_INPUT_PULLUP | MUX_MODE0)     /* hdmi_cec.hdmi_cec */
+                        0x5c (PIN_INPUT_PULLUP | MUX_MODE0)     /* hdmi_scl.hdmi_scl */
+                        0x5e (PIN_INPUT_PULLUP | MUX_MODE0)     /* hdmi_sda.hdmi_sda */
                 >;
         };
 
         tpd12s015_pins: pinmux_tpd12s015_pins {
                 pinctrl-single,pins = <
-                        0x22 0x3        /* gpmc_a17.gpio_41 OUTPUT | MODE3 */
-                        0x48 0x3        /* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */
-                        0x58 0x10b      /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */
+                        0x22 (PIN_OUTPUT | MUX_MODE3)           /* gpmc_a17.gpio_41 */
+                        0x48 (PIN_OUTPUT | MUX_MODE3)           /* gpmc_nbe1.gpio_60 */
+                        0x58 (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* hdmi_hpd.gpio_63 */
+                >;
+        };
+
+        hsusbb1_pins: pinmux_hsusbb1_pins {
+                pinctrl-single,pins = <
+                        0x82 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */
+                        0x84 (PIN_OUTPUT | MUX_MODE4)           /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */
+                        0x86 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */
+                        0x88 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */
+                        0x8a (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */
+                        0x8c (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */
+                        0x8e (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */
+                        0x90 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */
+                        0x92 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */
+                        0x94 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */
+                        0x96 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */
+                        0x98 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */
                 >;
         };
 
         i2c1_pins: pinmux_i2c1_pins {
                 pinctrl-single,pins = <
-                        0xe2 0x118        /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */
-                        0xe4 0x118        /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */
+                        0xe2 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c1_scl */
+                        0xe4 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c1_sda */
                 >;
         };
 
         i2c2_pins: pinmux_i2c2_pins {
                 pinctrl-single,pins = <
-                        0xe6 0x118        /* i2c2_scl PULLUP | INPUTENABLE | MODE0 */
-                        0xe8 0x118        /* i2c2_sda PULLUP | INPUTENABLE | MODE0 */
+                        0xe6 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c2_scl */
+                        0xe8 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c2_sda */
                 >;
         };
 
         i2c3_pins: pinmux_i2c3_pins {
                 pinctrl-single,pins = <
-                        0xea 0x118        /* i2c3_scl PULLUP | INPUTENABLE | MODE0 */
-                        0xec 0x118     /* i2c3_sda PULLUP | INPUTENABLE | MODE0 */
+                        0xea (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c3_scl */
+                        0xec (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c3_sda */
                 >;
         };
 
         i2c4_pins: pinmux_i2c4_pins {
                 pinctrl-single,pins = <
-                        0xee 0x118        /* i2c4_scl PULLUP | INPUTENABLE | MODE0 */
-                        0xf0 0x118     /* i2c4_sda PULLUP | INPUTENABLE | MODE0 */
+                        0xee (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c4_scl */
+                        0xf0 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c4_sda */
+                >;
+        };
+};
+
+&omap4_pmx_wkup {
+        led_wkgpio_pins: pinmux_leds_wkpins {
+                pinctrl-single,pins = <
+                        0x1a (PIN_OUTPUT | MUX_MODE3)   /* gpio_wk7 */
+                        0x1c (PIN_OUTPUT | MUX_MODE3)   /* gpio_wk8 */
                 >;
         };
 };
@@ -165,18 +245,18 @@
 
         twl: twl@48 {
                 reg = <0x48>;
-                /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
-                interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
+                /* IRQ# = 7 */
+                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
                 interrupt-parent = <&gic>;
         };
 
         twl6040: twl@4b {
                 compatible = "ti,twl6040";
                 reg = <0x4b>;
-                /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
-                interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
+                /* IRQ# = 119 */
+                interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
                 interrupt-parent = <&gic>;
-                ti,audpwron-gpio = <&gpio4 31 0>;  /* gpio line 127 */
+                ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>;  /* gpio line 127 */
 
                 vio-supply = <&v1v8>;
                 v2v1-supply = <&v2v1>;
@@ -184,7 +264,7 @@
         };
 };
 
-/include/ "twl6030.dtsi"
+#include "twl6030.dtsi"
 
 &i2c2 {
         pinctrl-names = "default";
@@ -269,3 +349,11 @@
         mode = <3>;
         power = <50>;
 };
+
+&usbhshost {
+        port1-mode = "ehci-phy";
+};
+
+&usbhsehci {
+        phys = <&hsusb1_phy>;
+};
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
index f1d8c217ce12..56c435468e94 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -7,8 +7,8 @@
  */
 /dts-v1/;
 
-/include/ "omap4460.dtsi"
-/include/ "omap4-panda-common.dtsi"
+#include "omap4460.dtsi"
+#include "omap4-panda-common.dtsi"
 
 /* Audio routing is differnet between PandaBoard4430 and PandaBoardES */
 &sound {
@@ -29,8 +29,36 @@
 /* PandaboardES has external pullups on SCL & SDA */
 &dss_hdmi_pins {
         pinctrl-single,pins = <
-                0x5a 0x118      /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
-                0x5c 0x100      /* hdmi_scl.hdmi_scl INPUT | MODE 0 */
-                0x5e 0x100      /* hdmi_sda.hdmi_sda INPUT | MODE 0 */
+                0x5a (PIN_INPUT_PULLUP | MUX_MODE0)     /* hdmi_cec.hdmi_cec */
+                0x5c (PIN_INPUT | MUX_MODE0)            /* hdmi_scl.hdmi_scl */
+                0x5e (PIN_INPUT | MUX_MODE0)            /* hdmi_sda.hdmi_sda */
                 >;
 };
+
+&omap4_pmx_core {
+        led_gpio_pins: gpio_led_pmx {
+                pinctrl-single,pins = <
+                        0xb6 (PIN_OUTPUT | MUX_MODE3)   /* gpio_110 */
+                >;
+        };
+};
+
+&led_wkgpio_pins {
+        pinctrl-single,pins = <
+                0x1c (PIN_OUTPUT | MUX_MODE3)   /* gpio_wk8 */
+        >;
+};
+
+&leds {
+        pinctrl-0 = <
+                &led_gpio_pins
+                &led_wkgpio_pins
+        >;
+
+        heartbeat {
+                gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>;
+        };
+        mmc {
+                gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index f8b221f0168e..6189a8b77d7f 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -7,5 +7,5 @@
  */
 /dts-v1/;
 
-/include/ "omap443x.dtsi"
-/include/ "omap4-panda-common.dtsi"
+#include "omap443x.dtsi"
+#include "omap4-panda-common.dtsi"
diff --git a/arch/arm/boot/dts/omap4-sdp-es23plus.dts b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
index b4a40ffbce31..aad5dda0f469 100644
--- a/arch/arm/boot/dts/omap4-sdp-es23plus.dts
+++ b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
@@ -5,13 +5,13 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-/include/ "omap4-sdp.dts"
+#include "omap4-sdp.dts"
 
 /* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */
 &dss_hdmi_pins {
         pinctrl-single,pins = <
-                0x5a 0x118      /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
-                0x5c 0x100      /* hdmi_scl.hdmi_scl INPUT | MODE 0 */
-                0x5e 0x100      /* hdmi_sda.hdmi_sda INPUT | MODE 0 */
+                0x5a (PIN_INPUT_PULLUP | MUX_MODE0)     /* hdmi_cec.hdmi_cec */
+                0x5c (PIN_INPUT | MUX_MODE0)            /* hdmi_scl.hdmi_scl */
+                0x5e (PIN_INPUT | MUX_MODE0)            /* hdmi_sda.hdmi_sda */
                 >;
 };
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 98505a2ef162..7951b4ea500a 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -7,8 +7,8 @@
  */
 /dts-v1/;
 
-/include/ "omap443x.dtsi"
-/include/ "elpida_ecb240abacn.dtsi"
+#include "omap443x.dtsi"
+#include "elpida_ecb240abacn.dtsi"
 
 / {
         model = "TI OMAP4 SDP board";
@@ -41,42 +41,42 @@
                 compatible = "gpio-leds";
                 debug0 {
                         label = "omap4:green:debug0";
-                        gpios = <&gpio2 29 0>; /* 61 */
+                        gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; /* 61 */
                 };
 
                 debug1 {
                         label = "omap4:green:debug1";
-                        gpios = <&gpio1 30 0>; /* 30 */
+                        gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; /* 30 */
                 };
 
                 debug2 {
                         label = "omap4:green:debug2";
-                        gpios = <&gpio1 7 0>; /* 7 */
+                        gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; /* 7 */
                 };
 
                 debug3 {
                         label = "omap4:green:debug3";
-                        gpios = <&gpio1 8 0>; /* 8 */
+                        gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* 8 */
                 };
 
                 debug4 {
                         label = "omap4:green:debug4";
-                        gpios = <&gpio2 18 0>; /* 50 */
+                        gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; /* 50 */
                 };
 
                 user1 {
                         label = "omap4:blue:user";
-                        gpios = <&gpio6 9 0>; /* 169 */
+                        gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* 169 */
                 };
 
                 user2 {
                         label = "omap4:red:user";
-                        gpios = <&gpio6 10 0>; /* 170 */
+                        gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* 170 */
                 };
 
                 user3 {
                         label = "omap4:green:user";
-                        gpios = <&gpio5 11 0>; /* 139 */
+                        gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* 139 */
                 };
         };
 
@@ -150,7 +150,7 @@
 
         twl6030_wkup_pins: pinmux_twl6030_wkup_pins {
                 pinctrl-single,pins = <
-                        0x14 0x2        /* fref_clk0_out.sys_drm_msecure OUTPUT | MODE2 */
+                        0x14 (PIN_OUTPUT | MUX_MODE2)           /* fref_clk0_out.sys_drm_msecure */
                 >;
         };
 };
@@ -170,129 +170,129 @@
 
         uart2_pins: pinmux_uart2_pins {
                 pinctrl-single,pins = <
-                        0xd8 0x118      /* uart2_cts.uart2_cts INPUT_PULLUP | MODE0 */
-                        0xda 0          /* uart2_rts.uart2_rts OUTPUT | MODE0 */
-                        0xdc 0x118      /* uart2_rx.uart2_rx INPUT_PULLUP | MODE0 */
-                        0xde 0          /* uart2_tx.uart2_tx OUTPUT | MODE0 */
+                        0xd8 (PIN_INPUT_PULLUP | MUX_MODE0)     /* uart2_cts.uart2_cts */
+                        0xda (PIN_OUTPUT | MUX_MODE0)           /* uart2_rts.uart2_rts */
+                        0xdc (PIN_INPUT_PULLUP | MUX_MODE0)     /* uart2_rx.uart2_rx */
+                        0xde (PIN_OUTPUT | MUX_MODE0)           /* uart2_tx.uart2_tx */
                 >;
         };
 
         uart3_pins: pinmux_uart3_pins {
                 pinctrl-single,pins = <
-                        0x100 0x118     /* uart3_cts_rctx.uart3_cts_rctx INPUT_PULLUP | MODE0 */
-                        0x102 0         /* uart3_rts_sd.uart3_rts_sd OUTPUT | MODE0 */
-                        0x104 0x100     /* uart3_rx_irrx.uart3_rx_irrx INPUT | MODE0 */
-                        0x106 0         /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
+                        0x100 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart3_cts_rctx.uart3_cts_rctx */
+                        0x102 (PIN_OUTPUT | MUX_MODE0)          /* uart3_rts_sd.uart3_rts_sd */
+                        0x104 (PIN_INPUT | MUX_MODE0)           /* uart3_rx_irrx.uart3_rx_irrx */
+                        0x106 (PIN_OUTPUT | MUX_MODE0)          /* uart3_tx_irtx.uart3_tx_irtx */
                 >;
         };
 
         uart4_pins: pinmux_uart4_pins {
                 pinctrl-single,pins = <
-                        0x11c 0x100     /* uart4_rx.uart4_rx INPUT | MODE0 */
-                        0x11e 0         /* uart4_tx.uart4_tx OUTPUT | MODE0 */
+                        0x11c (PIN_INPUT | MUX_MODE0)           /* uart4_rx.uart4_rx */
+                        0x11e (PIN_OUTPUT | MUX_MODE0)          /* uart4_tx.uart4_tx */
                 >;
         };
 
         twl6030_pins: pinmux_twl6030_pins {
                 pinctrl-single,pins = <
-                        0x15e 0x4118    /* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */
+                        0x15e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0)        /* sys_nirq1.sys_nirq1 */
                 >;
         };
 
         twl6040_pins: pinmux_twl6040_pins {
                 pinctrl-single,pins = <
-                        0xe0 0x3        /* hdq_sio.gpio_127 OUTPUT | MODE3 */
-                        0x160 0x100     /* sys_nirq2.sys_nirq2 INPUT | MODE0 */
+                        0xe0 (PIN_OUTPUT | MUX_MODE3)           /* hdq_sio.gpio_127 */
+                        0x160 (PIN_INPUT | MUX_MODE0)           /* sys_nirq2.sys_nirq2 */
                 >;
         };
 
         mcpdm_pins: pinmux_mcpdm_pins {
                 pinctrl-single,pins = <
-                        0xc6 0x108      /* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */
-                        0xc8 0x108      /* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */
-                        0xca 0x118      /* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */
-                        0xcc 0x108      /* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */
-                        0xce 0x108      /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
+                        0xc6 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_pdm_ul_data.abe_pdm_ul_data */
+                        0xc8 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_pdm_dl_data.abe_pdm_dl_data */
+                        0xca (PIN_INPUT_PULLUP | MUX_MODE0)     /* abe_pdm_frame.abe_pdm_frame */
+                        0xcc (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_pdm_lb_clk.abe_pdm_lb_clk */
+                        0xce (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_clks.abe_clks */
                 >;
         };
 
         dmic_pins: pinmux_dmic_pins {
                 pinctrl-single,pins = <
-                        0xd0 0          /* abe_dmic_clk1.abe_dmic_clk1 OUTPUT | MODE0 */
-                        0xd2 0x100      /* abe_dmic_din1.abe_dmic_din1 INPUT | MODE0 */
-                        0xd4 0x100      /* abe_dmic_din2.abe_dmic_din2 INPUT | MODE0 */
-                        0xd6 0x100      /* abe_dmic_din3.abe_dmic_din3 INPUT | MODE0 */
+                        0xd0 (PIN_OUTPUT | MUX_MODE0)           /* abe_dmic_clk1.abe_dmic_clk1 */
+                        0xd2 (PIN_INPUT | MUX_MODE0)            /* abe_dmic_din1.abe_dmic_din1 */
+                        0xd4 (PIN_INPUT | MUX_MODE0)            /* abe_dmic_din2.abe_dmic_din2 */
+                        0xd6 (PIN_INPUT | MUX_MODE0)            /* abe_dmic_din3.abe_dmic_din3 */
                 >;
         };
 
         mcbsp1_pins: pinmux_mcbsp1_pins {
                 pinctrl-single,pins = <
-                        0xbe 0x100      /* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */
-                        0xc0 0x108      /* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */
-                        0xc2 0x8        /* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */
-                        0xc4 0x100      /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */
+                        0xbe (PIN_INPUT | MUX_MODE0)            /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */
+                        0xc0 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_mcbsp1_dr.abe_mcbsp1_dr */
+                        0xc2 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)  /* abe_mcbsp1_dx.abe_mcbsp1_dx */
+                        0xc4 (PIN_INPUT | MUX_MODE0)            /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */
                 >;
         };
 
         mcbsp2_pins: pinmux_mcbsp2_pins {
                 pinctrl-single,pins = <
-                        0xb6 0x100      /* abe_mcbsp2_clkx.abe_mcbsp2_clkx INPUT | MODE0 */
-                        0xb8 0x108      /* abe_mcbsp2_dr.abe_mcbsp2_dr INPUT PULLDOWN | MODE0 */
-                        0xba 0x8        /* abe_mcbsp2_dx.abe_mcbsp2_dx OUTPUT PULLDOWN | MODE0 */
-                        0xbc 0x100      /* abe_mcbsp2_fsx.abe_mcbsp2_fsx INPUT | MODE0 */
+                        0xb6 (PIN_INPUT | MUX_MODE0)            /* abe_mcbsp2_clkx.abe_mcbsp2_clkx */
+                        0xb8 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_mcbsp2_dr.abe_mcbsp2_dr */
+                        0xba (PIN_OUTPUT_PULLDOWN | MUX_MODE0)  /* abe_mcbsp2_dx.abe_mcbsp2_dx */
+                        0xbc (PIN_INPUT | MUX_MODE0)            /* abe_mcbsp2_fsx.abe_mcbsp2_fsx */
                 >;
         };
 
         mcspi1_pins: pinmux_mcspi1_pins {
                 pinctrl-single,pins = <
-                        0xf2 0x100      /*  mcspi1_clk.mcspi1_clk INPUT | MODE0 */
-                        0xf4 0x100      /*  mcspi1_somi.mcspi1_somi INPUT | MODE0 */
-                        0xf6 0x100      /*  mcspi1_simo.mcspi1_simo INPUT | MODE0 */
-                        0xf8 0x100      /*  mcspi1_cs0.mcspi1_cs0 INPUT | MODE0*/
+                        0xf2 (PIN_INPUT | MUX_MODE0)            /*  mcspi1_clk.mcspi1_clk */
+                        0xf4 (PIN_INPUT | MUX_MODE0)            /*  mcspi1_somi.mcspi1_somi */
+                        0xf6 (PIN_INPUT | MUX_MODE0)            /*  mcspi1_simo.mcspi1_simo */
+                        0xf8 (PIN_INPUT | MUX_MODE0)            /*  mcspi1_cs0.mcspi1_cs0 */
                 >;
         };
 
         dss_hdmi_pins: pinmux_dss_hdmi_pins {
                 pinctrl-single,pins = <
-                        0x5a 0x118      /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
-                        0x5c 0x118      /* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */
-                        0x5e 0x118      /* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */
+                        0x5a (PIN_INPUT_PULLUP | MUX_MODE0)     /* hdmi_cec.hdmi_cec */
+                        0x5c (PIN_INPUT_PULLUP | MUX_MODE0)     /* hdmi_scl.hdmi_scl */
+                        0x5e (PIN_INPUT_PULLUP | MUX_MODE0)     /* hdmi_sda.hdmi_sda */
                 >;
         };
 
         tpd12s015_pins: pinmux_tpd12s015_pins {
                 pinctrl-single,pins = <
-                        0x22 0x3        /* gpmc_a17.gpio_41 OUTPUT | MODE3 */
-                        0x48 0x3        /* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */
-                        0x58 0x10b      /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */
+                        0x22 (PIN_OUTPUT | MUX_MODE3)           /* gpmc_a17.gpio_41 */
+                        0x48 (PIN_OUTPUT | MUX_MODE3)           /* gpmc_nbe1.gpio_60 */
+                        0x58 (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* hdmi_hpd.gpio_63 */
                 >;
         };
 
         i2c1_pins: pinmux_i2c1_pins {
                 pinctrl-single,pins = <
-                        0xe2 0x118        /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */
-                        0xe4 0x118       /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */
+                        0xe2 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c1_scl */
+                        0xe4 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c1_sda */
                 >;
         };
 
         i2c2_pins: pinmux_i2c2_pins {
                 pinctrl-single,pins = <
-                        0xe6 0x118        /* i2c2_scl PULLUP | INPUTENABLE | MODE0 */
-                        0xe8 0x118        /* i2c2_sda PULLUP | INPUTENABLE | MODE0 */
+                        0xe6 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c2_scl */
+                        0xe8 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c2_sda */
                 >;
         };
 
         i2c3_pins: pinmux_i2c3_pins {
                 pinctrl-single,pins = <
-                        0xea 0x118        /* i2c3_scl PULLUP | INPUTENABLE | MODE0 */
-                        0xec 0x118     /* i2c3_sda PULLUP | INPUTENABLE | MODE0 */
+                        0xea (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c3_scl */
+                        0xec (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c3_sda */
                 >;
         };
 
         i2c4_pins: pinmux_i2c4_pins {
                 pinctrl-single,pins = <
-                        0xee 0x118        /* i2c4_scl PULLUP | INPUTENABLE | MODE0 */
-                        0xf0 0x118     /* i2c4_sda PULLUP | INPUTENABLE | MODE0 */
+                        0xee (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c4_scl */
+                        0xf0 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c4_sda */
                 >;
         };
 };
@@ -306,7 +306,7 @@
         twl: twl@48 {
                 reg = <0x48>;
                 /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
-                interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
+                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
                 interrupt-parent = <&gic>;
         };
 
@@ -314,7 +314,7 @@
                 compatible = "ti,twl6040";
                 reg = <0x4b>;
                 /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
-                interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
+                interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
                 interrupt-parent = <&gic>;
                 ti,audpwron-gpio = <&gpio4 31 0>;  /* gpio line 127 */
 
@@ -336,7 +336,7 @@
         };
 };
 
-/include/ "twl6030.dtsi"
+#include "twl6030.dtsi"
 
 &i2c2 {
         pinctrl-names = "default";
@@ -395,7 +395,7 @@
                 spi-max-frequency = <24000000>;
                 reg = <0>;
                 interrupt-parent = <&gpio2>;
-                interrupts = <2 8>; /* gpio line 34, low triggered */
+                interrupts = <2 IRQ_TYPE_LEVEL_LOW>; /* gpio line 34 */
                 vdd-supply = <&vdd_eth>;
         };
 };
diff --git a/arch/arm/boot/dts/omap4-var-som.dts b/arch/arm/boot/dts/omap4-var-som.dts
index 7e04103779c4..b41269e871dd 100644
--- a/arch/arm/boot/dts/omap4-var-som.dts
+++ b/arch/arm/boot/dts/omap4-var-som.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap443x.dtsi"
+#include "omap443x.dtsi"
 
 / {
         model = "Variscite OMAP4 SOM";
@@ -34,12 +34,12 @@
         twl: twl@48 {
                 reg = <0x48>;
                 /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
-                interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
+                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
                 interrupt-parent = <&gic>;
         };
 };
 
-/include/ "twl6030.dtsi"
+#include "twl6030.dtsi"
 
 &i2c2 {
         clock-frequency = <400000>;
@@ -68,7 +68,7 @@
                 spi-max-frequency = <24000000>;
                 reg = <0>;
                 interrupt-parent = <&gpio6>;
-                interrupts = <11 8>; /* gpio line 171, low triggered */
+                interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* gpio line 171 */
                 vdd-supply = <&vdd_eth>;
         };
 };
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 2a5642882c8a..22d9f2b593d4 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -6,15 +6,11 @@
  * published by the Free Software Foundation.
  */
 
-/*
- * Carveout for multimedia usecases
- * It should be the last 48MB of the first 512MB memory part
- * In theory, it should not even exist. That zone should be reserved
- * dynamically during the .reserve callback.
- */
-/memreserve/ 0x9d000000 0x03000000;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/omap.h>
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
         compatible = "ti,omap4430", "ti,omap4";
@@ -28,13 +24,20 @@
         };
 
         cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
                 cpu@0 {
                         compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                         next-level-cache = <&L2>;
+                        reg = <0x0>;
                 };
                 cpu@1 {
                         compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                         next-level-cache = <&L2>;
+                        reg = <0x1>;
                 };
         };
 
@@ -56,7 +59,7 @@
         local-timer@0x48240600 {
                 compatible = "arm,cortex-a9-twd-timer";
                 reg = <0x48240600 0x20>;
-                interrupts = <1 13 0x304>;
+                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
         };
 
         /*
@@ -97,8 +100,8 @@
                 reg = <0x44000000 0x1000>,
                       <0x44800000 0x2000>,
                       <0x45000000 0x1000>;
-                interrupts = <0 9 0x4>,
-                             <0 10 0x4>;
+                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
                 counter32k: counter@4a304000 {
                         compatible = "ti,omap-counter32k";
@@ -126,10 +129,10 @@
                 sdma: dma-controller@4a056000 {
                         compatible = "ti,omap4430-sdma";
                         reg = <0x4a056000 0x1000>;
-                        interrupts = <0 12 0x4>,
-                                     <0 13 0x4>,
-                                     <0 14 0x4>,
-                                     <0 15 0x4>;
+                        interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                         #dma-cells = <1>;
                         #dma-channels = <32>;
                         #dma-requests = <127>;
@@ -138,7 +141,7 @@
                 gpio1: gpio@4a310000 {
                         compatible = "ti,omap4-gpio";
                         reg = <0x4a310000 0x200>;
-                        interrupts = <0 29 0x4>;
+                        interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "gpio1";
                         ti,gpio-always-on;
                         gpio-controller;
@@ -150,7 +153,7 @@
                 gpio2: gpio@48055000 {
                         compatible = "ti,omap4-gpio";
                         reg = <0x48055000 0x200>;
-                        interrupts = <0 30 0x4>;
+                        interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "gpio2";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -161,7 +164,7 @@
                 gpio3: gpio@48057000 {
                         compatible = "ti,omap4-gpio";
                         reg = <0x48057000 0x200>;
-                        interrupts = <0 31 0x4>;
+                        interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "gpio3";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -172,7 +175,7 @@
                 gpio4: gpio@48059000 {
                         compatible = "ti,omap4-gpio";
                         reg = <0x48059000 0x200>;
-                        interrupts = <0 32 0x4>;
+                        interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "gpio4";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -183,7 +186,7 @@
                 gpio5: gpio@4805b000 {
                         compatible = "ti,omap4-gpio";
                         reg = <0x4805b000 0x200>;
-                        interrupts = <0 33 0x4>;
+                        interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "gpio5";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -194,7 +197,7 @@
                 gpio6: gpio@4805d000 {
                         compatible = "ti,omap4-gpio";
                         reg = <0x4805d000 0x200>;
-                        interrupts = <0 34 0x4>;
+                        interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "gpio6";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -207,7 +210,7 @@
                         reg = <0x50000000 0x1000>;
                         #address-cells = <2>;
                         #size-cells = <1>;
-                        interrupts = <0 20 0x4>;
+                        interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
                         gpmc,num-cs = <8>;
                         gpmc,num-waitpins = <4>;
                         ti,hwmods = "gpmc";
@@ -216,7 +219,7 @@
                 uart1: serial@4806a000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x4806a000 0x100>;
-                        interrupts = <0 72 0x4>;
+                        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart1";
                         clock-frequency = <48000000>;
                 };
@@ -224,7 +227,7 @@
                 uart2: serial@4806c000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x4806c000 0x100>;
-                        interrupts = <0 73 0x4>;
+                        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart2";
                         clock-frequency = <48000000>;
                 };
@@ -232,7 +235,7 @@
                 uart3: serial@48020000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x48020000 0x100>;
-                        interrupts = <0 74 0x4>;
+                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart3";
                         clock-frequency = <48000000>;
                 };
@@ -240,7 +243,7 @@
                 uart4: serial@4806e000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x4806e000 0x100>;
-                        interrupts = <0 70 0x4>;
+                        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart4";
                         clock-frequency = <48000000>;
                 };
@@ -248,7 +251,7 @@
                 i2c1: i2c@48070000 {
                         compatible = "ti,omap4-i2c";
                         reg = <0x48070000 0x100>;
-                        interrupts = <0 56 0x4>;
+                        interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c1";
@@ -257,7 +260,7 @@
                 i2c2: i2c@48072000 {
                         compatible = "ti,omap4-i2c";
                         reg = <0x48072000 0x100>;
-                        interrupts = <0 57 0x4>;
+                        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c2";
@@ -266,7 +269,7 @@
                 i2c3: i2c@48060000 {
                         compatible = "ti,omap4-i2c";
                         reg = <0x48060000 0x100>;
-                        interrupts = <0 61 0x4>;
+                        interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c3";
@@ -275,7 +278,7 @@
                 i2c4: i2c@48350000 {
                         compatible = "ti,omap4-i2c";
                         reg = <0x48350000 0x100>;
-                        interrupts = <0 62 0x4>;
+                        interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c4";
@@ -284,7 +287,7 @@
                 mcspi1: spi@48098000 {
                         compatible = "ti,omap4-mcspi";
                         reg = <0x48098000 0x200>;
-                        interrupts = <0 65 0x4>;
+                        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "mcspi1";
@@ -304,7 +307,7 @@
                 mcspi2: spi@4809a000 {
                         compatible = "ti,omap4-mcspi";
                         reg = <0x4809a000 0x200>;
-                        interrupts = <0 66 0x4>;
+                        interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "mcspi2";
@@ -319,7 +322,7 @@
                 mcspi3: spi@480b8000 {
                         compatible = "ti,omap4-mcspi";
                         reg = <0x480b8000 0x200>;
-                        interrupts = <0 91 0x4>;
+                        interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "mcspi3";
@@ -331,7 +334,7 @@
                 mcspi4: spi@480ba000 {
                         compatible = "ti,omap4-mcspi";
                         reg = <0x480ba000 0x200>;
-                        interrupts = <0 48 0x4>;
+                        interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "mcspi4";
@@ -343,7 +346,7 @@
                 mmc1: mmc@4809c000 {
                         compatible = "ti,omap4-hsmmc";
                         reg = <0x4809c000 0x400>;
-                        interrupts = <0 83 0x4>;
+                        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mmc1";
                         ti,dual-volt;
                         ti,needs-special-reset;
@@ -354,7 +357,7 @@
                 mmc2: mmc@480b4000 {
                         compatible = "ti,omap4-hsmmc";
                         reg = <0x480b4000 0x400>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mmc2";
                         ti,needs-special-reset;
                         dmas = <&sdma 47>, <&sdma 48>;
@@ -364,7 +367,7 @@
                 mmc3: mmc@480ad000 {
                         compatible = "ti,omap4-hsmmc";
                         reg = <0x480ad000 0x400>;
-                        interrupts = <0 94 0x4>;
+                        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mmc3";
                         ti,needs-special-reset;
                         dmas = <&sdma 77>, <&sdma 78>;
@@ -374,7 +377,7 @@
                 mmc4: mmc@480d1000 {
                         compatible = "ti,omap4-hsmmc";
                         reg = <0x480d1000 0x400>;
-                        interrupts = <0 96 0x4>;
+                        interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mmc4";
                         ti,needs-special-reset;
                         dmas = <&sdma 57>, <&sdma 58>;
@@ -384,7 +387,7 @@
                 mmc5: mmc@480d5000 {
                         compatible = "ti,omap4-hsmmc";
                         reg = <0x480d5000 0x400>;
-                        interrupts = <0 59 0x4>;
+                        interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mmc5";
                         ti,needs-special-reset;
                         dmas = <&sdma 59>, <&sdma 60>;
@@ -394,7 +397,7 @@
                 wdt2: wdt@4a314000 {
                         compatible = "ti,omap4-wdt", "ti,omap3-wdt";
                         reg = <0x4a314000 0x80>;
-                        interrupts = <0 80 0x4>;
+                        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "wd_timer2";
                 };
 
@@ -403,7 +406,7 @@
                         reg = <0x40132000 0x7f>, /* MPU private access */
                               <0x49032000 0x7f>; /* L3 Interconnect */
                         reg-names = "mpu", "dma";
-                        interrupts = <0 112 0x4>;
+                        interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mcpdm";
                         dmas = <&sdma 65>,
                                <&sdma 66>;
@@ -415,7 +418,7 @@
                         reg = <0x4012e000 0x7f>, /* MPU private access */
                               <0x4902e000 0x7f>; /* L3 Interconnect */
                         reg-names = "mpu", "dma";
-                        interrupts = <0 114 0x4>;
+                        interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "dmic";
                         dmas = <&sdma 67>;
                         dma-names = "up_link";
@@ -426,7 +429,7 @@
                         reg = <0x40122000 0xff>, /* MPU private access */
                               <0x49022000 0xff>; /* L3 Interconnect */
                         reg-names = "mpu", "dma";
-                        interrupts = <0 17 0x4>;
+                        interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "common";
                         ti,buffer-size = <128>;
                         ti,hwmods = "mcbsp1";
@@ -440,7 +443,7 @@
                         reg = <0x40124000 0xff>, /* MPU private access */
                               <0x49024000 0xff>; /* L3 Interconnect */
                         reg-names = "mpu", "dma";
-                        interrupts = <0 22 0x4>;
+                        interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "common";
                         ti,buffer-size = <128>;
                         ti,hwmods = "mcbsp2";
@@ -454,7 +457,7 @@
                         reg = <0x40126000 0xff>, /* MPU private access */
                               <0x49026000 0xff>; /* L3 Interconnect */
                         reg-names = "mpu", "dma";
-                        interrupts = <0 23 0x4>;
+                        interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "common";
                         ti,buffer-size = <128>;
                         ti,hwmods = "mcbsp3";
@@ -467,7 +470,7 @@
                         compatible = "ti,omap4-mcbsp";
                         reg = <0x48096000 0xff>; /* L4 Interconnect */
                         reg-names = "mpu";
-                        interrupts = <0 16 0x4>;
+                        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "common";
                         ti,buffer-size = <128>;
                         ti,hwmods = "mcbsp4";
@@ -479,7 +482,7 @@
                 keypad: keypad@4a31c000 {
                         compatible = "ti,omap4-keypad";
                         reg = <0x4a31c000 0x80>;
-                        interrupts = <0 120 0x4>;
+                        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
                         reg-names = "mpu";
                         ti,hwmods = "kbd";
                 };
@@ -487,7 +490,7 @@
                 emif1: emif@4c000000 {
                         compatible = "ti,emif-4d";
                         reg = <0x4c000000 0x100>;
-                        interrupts = <0 110 0x4>;
+                        interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "emif1";
                         phy-type = <1>;
                         hw-caps-read-idle-ctrl;
@@ -498,7 +501,7 @@
                 emif2: emif@4d000000 {
                         compatible = "ti,emif-4d";
                         reg = <0x4d000000 0x100>;
-                        interrupts = <0 111 0x4>;
+                        interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "emif2";
                         phy-type = <1>;
                         hw-caps-read-idle-ctrl;
@@ -523,7 +526,7 @@
                 timer1: timer@4a318000 {
                         compatible = "ti,omap3430-timer";
                         reg = <0x4a318000 0x80>;
-                        interrupts = <0 37 0x4>;
+                        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer1";
                         ti,timer-alwon;
                 };
@@ -531,21 +534,21 @@
                 timer2: timer@48032000 {
                         compatible = "ti,omap3430-timer";
                         reg = <0x48032000 0x80>;
-                        interrupts = <0 38 0x4>;
+                        interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer2";
                 };
 
                 timer3: timer@48034000 {
                         compatible = "ti,omap4430-timer";
                         reg = <0x48034000 0x80>;
-                        interrupts = <0 39 0x4>;
+                        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer3";
                 };
 
                 timer4: timer@48036000 {
                         compatible = "ti,omap4430-timer";
                         reg = <0x48036000 0x80>;
-                        interrupts = <0 40 0x4>;
+                        interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer4";
                 };
 
@@ -553,7 +556,7 @@
                         compatible = "ti,omap4430-timer";
                         reg = <0x40138000 0x80>,
                               <0x49038000 0x80>;
-                        interrupts = <0 41 0x4>;
+                        interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer5";
                         ti,timer-dsp;
                 };
@@ -562,7 +565,7 @@
                         compatible = "ti,omap4430-timer";
                         reg = <0x4013a000 0x80>,
                               <0x4903a000 0x80>;
-                        interrupts = <0 42 0x4>;
+                        interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer6";
                         ti,timer-dsp;
                 };
@@ -571,7 +574,7 @@
                         compatible = "ti,omap4430-timer";
                         reg = <0x4013c000 0x80>,
                               <0x4903c000 0x80>;
-                        interrupts = <0 43 0x4>;
+                        interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer7";
                         ti,timer-dsp;
                 };
@@ -580,7 +583,7 @@
                         compatible = "ti,omap4430-timer";
                         reg = <0x4013e000 0x80>,
                               <0x4903e000 0x80>;
-                        interrupts = <0 44 0x4>;
+                        interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer8";
                         ti,timer-pwm;
                         ti,timer-dsp;
@@ -589,7 +592,7 @@
                 timer9: timer@4803e000 {
                         compatible = "ti,omap4430-timer";
                         reg = <0x4803e000 0x80>;
-                        interrupts = <0 45 0x4>;
+                        interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer9";
                         ti,timer-pwm;
                 };
@@ -597,7 +600,7 @@
                 timer10: timer@48086000 {
                         compatible = "ti,omap3430-timer";
                         reg = <0x48086000 0x80>;
-                        interrupts = <0 46 0x4>;
+                        interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer10";
                         ti,timer-pwm;
                 };
@@ -605,7 +608,7 @@
                 timer11: timer@48088000 {
                         compatible = "ti,omap4430-timer";
                         reg = <0x48088000 0x80>;
-                        interrupts = <0 47 0x4>;
+                        interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer11";
                         ti,timer-pwm;
                 };
@@ -613,7 +616,7 @@
                 usbhstll: usbhstll@4a062000 {
                         compatible = "ti,usbhs-tll";
                         reg = <0x4a062000 0x1000>;
-                        interrupts = <0 78 0x4>;
+                        interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "usb_tll_hs";
                 };
 
@@ -629,14 +632,14 @@
                                 compatible = "ti,ohci-omap3", "usb-ohci";
                                 reg = <0x4a064800 0x400>;
                                 interrupt-parent = <&gic>;
-                                interrupts = <0 76 0x4>;
+                                interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
                         };
 
                         usbhsehci: ehci@4a064c00 {
                                 compatible = "ti,ehci-omap", "usb-ehci";
                                 reg = <0x4a064c00 0x400>;
                                 interrupt-parent = <&gic>;
-                                interrupts = <0 77 0x4>;
+                                interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
                         };
                 };
 
@@ -651,7 +654,7 @@
                 usb_otg_hs: usb_otg_hs@4a0ab000 {
                         compatible = "ti,omap4-musb";
                         reg = <0x4a0ab000 0x7ff>;
-                        interrupts = <0 92 0x4>, <0 93 0x4>;
+                        interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "mc", "dma";
                         ti,hwmods = "usb_otg_hs";
                         usb-phy = <&usb2_phy>;
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index cccf39af4925..bcf455efe18d 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap4.dtsi"
+#include "omap4.dtsi"
 
 / {
         cpus {
@@ -24,4 +24,10 @@
                         clock-latency = <300000>; /* From legacy driver */
                 };
         };
+
+        bandgap {
+                reg = <0x4a002260 0x4
+                       0x4a00232C 0x4>;
+                compatible = "ti,omap4430-bandgap";
+        };
 };
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index 2cf227c86099..c2f0f39b5a24 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -7,7 +7,7 @@
  * version 2.  This program is licensed "as is" without any warranty of any
  * kind, whether express or implied.
  */
-/include/ "omap4.dtsi"
+#include "omap4.dtsi"
 
 / {
         cpus {
@@ -25,8 +25,17 @@
 
         pmu {
                 compatible = "arm,cortex-a9-pmu";
-                interrupts = <0 54 0x4>,
-                             <0 55 0x4>;
+                interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
                 ti,hwmods = "debugss";
         };
+
+        bandgap {
+                reg = <0x4a002260 0x4
+                       0x4a00232C 0x4
+                       0x4a002378 0x18>;
+                compatible = "ti,omap4460-bandgap";
+                interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
+                gpios = <&gpio3 22 0>; /* tshut */
+        };
 };
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
deleted file mode 100644
index 982acd19477d..000000000000
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ /dev/null
@@ -1,261 +0,0 @@
-/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-/dts-v1/;
-
-/include/ "omap5.dtsi"
-/include/ "samsung_k3pe0e000b.dtsi"
-
-/ {
-        model = "TI OMAP5 EVM board";
-        compatible = "ti,omap5-evm", "ti,omap5";
-
-        memory {
-                device_type = "memory";
-                reg = <0x80000000 0x7F000000>; /* 2032 MB */
-        };
-
-        vmmcsd_fixed: fixedregulator-mmcsd {
-                compatible = "regulator-fixed";
-                regulator-name = "vmmcsd_fixed";
-                regulator-min-microvolt = <3000000>;
-                regulator-max-microvolt = <3000000>;
-        };
-
-};
-
-&omap5_pmx_core {
-        pinctrl-names = "default";
-        pinctrl-0 = <
-                        &twl6040_pins
-                        &mcpdm_pins
-                        &dmic_pins
-                        &mcbsp1_pins
-                        &mcbsp2_pins
-        >;
-
-        twl6040_pins: pinmux_twl6040_pins {
-                pinctrl-single,pins = <
-                        0x18a 0x6       /* perslimbus2_clock.gpio5_145 OUTPUT | MODE6 */
-                >;
-        };
-
-        mcpdm_pins: pinmux_mcpdm_pins {
-                pinctrl-single,pins = <
-                        0x142 0x108     /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
-                        0x15c 0x108     /* abemcpdm_ul_data.abemcpdm_ul_data INPUT PULLDOWN | MODE0 */
-                        0x15e 0x108     /* abemcpdm_dl_data.abemcpdm_dl_data INPUT PULLDOWN | MODE0 */
-                        0x160 0x118     /* abemcpdm_frame.abemcpdm_frame INPUT PULLUP | MODE0 */
-                        0x162 0x108     /* abemcpdm_lb_clk.abemcpdm_lb_clk INPUT PULLDOWN | MODE0 */
-                >;
-        };
-
-        dmic_pins: pinmux_dmic_pins {
-                pinctrl-single,pins = <
-                        0x144 0x100     /* abedmic_din1.abedmic_din1 INPUT | MODE0 */
-                        0x146 0x100     /* abedmic_din2.abedmic_din2 INPUT | MODE0 */
-                        0x148 0x100     /* abedmic_din3.abedmic_din3 INPUT | MODE0 */
-                        0x14a 0         /* abedmic_clk1.abedmic_clk1 OUTPUT | MODE0 */
-                >;
-        };
-
-        mcbsp1_pins: pinmux_mcbsp1_pins {
-                pinctrl-single,pins = <
-                        0x14c 0x101     /* abedmic_clk2.abemcbsp1_fsx INPUT | MODE1 */
-                        0x14e 0x9       /* abedmic_clk3.abemcbsp1_dx OUTPUT PULLDOWN | MODE1 */
-                        0x150 0x101     /* abeslimbus1_clock.abemcbsp1_clkx INPUT | MODE0 */
-                        0x152 0x109     /* abeslimbus1_data.abemcbsp1_dr INPUT PULLDOWN | MODE1 */
-                >;
-        };
-
-        mcbsp2_pins: pinmux_mcbsp2_pins {
-                pinctrl-single,pins = <
-                        0x154 0x108     /* abemcbsp2_dr.abemcbsp2_dr INPUT PULLDOWN | MODE0 */
-                        0x156 0x8       /* abemcbsp2_dx.abemcbsp2_dx OUTPUT PULLDOWN | MODE0 */
-                        0x158 0x100     /* abemcbsp2_fsx.abemcbsp2_fsx INPUT | MODE0 */
-                        0x15a 0x100     /* abemcbsp2_clkx.abemcbsp2_clkx INPUT | MODE0 */
-                >;
-        };
-
-        i2c1_pins: pinmux_i2c1_pins {
-                pinctrl-single,pins = <
-                        0x1b2 0x118        /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */
-                        0x1b4 0x118        /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */
-                >;
-        };
-
-        i2c2_pins: pinmux_i2c2_pins {
-                pinctrl-single,pins = <
-                        0x178 0x100        /* i2c2_scl INPUTENABLE | MODE0 */
-                        0x17a 0x100        /* i2c2_sda INPUTENABLE | MODE0 */
-                >;
-        };
-
-        i2c3_pins: pinmux_i2c3_pins {
-                pinctrl-single,pins = <
-                        0x13a 0x100        /* i2c3_scl INPUTENABLE | MODE0 */
-                        0x13c 0x100     /* i2c3_sda INPUTENABLE | MODE0 */
-                >;
-        };
-
-        i2c4_pins: pinmux_i2c4_pins {
-                pinctrl-single,pins = <
-                        0xb8 0x100        /* i2c4_scl INPUTENABLE | MODE0 */
-                        0xba 0x100     /* i2c4_sda INPUTENABLE | MODE0 */
-                >;
-        };
-
-        i2c5_pins: pinmux_i2c5_pins {
-                pinctrl-single,pins = <
-                        0x184 0x100        /* i2c5_scl INPUTENABLE | MODE0 */
-                        0x186 0x100     /* i2c5_sda INPUTENABLE | MODE0 */
-                >;
-        };
-
-        mcspi2_pins: pinmux_mcspi2_pins {
-                pinctrl-single,pins = <
-                        0xbc 0x100      /*  MCSPI2_CLK INPUTENABLE | MODE0 */
-                        0xbe 0x100      /*  MCSPI2_SIMO INPUTENABLE | MODE0 */
-                        0xc0 0x118      /*  MCSPI2_SOMI PULLUP | INPUTENABLE | MODE0*/
-                        0xc2 0x0        /*  MCSPI2_CS MODE0*/
-                >;
-        };
-
-        mcspi3_pins: pinmux_mcspi3_pins {
-                pinctrl-single,pins = <
-                        0x78 0x101      /*  MCSPI2_SOMI INPUTENABLE | MODE1 */
-                        0x7a 0x101      /*  MCSPI2_CS INPUTENABLE | MODE1 */
-                        0x7c 0x101      /*  MCSPI2_SIMO INPUTENABLE | MODE1 */
-                        0x7e 0x101      /*  MCSPI2_CLK INPUTENABLE | MODE1 */
-                >;
-        };
-
-        mcspi4_pins: pinmux_mcspi4_pins {
-                pinctrl-single,pins = <
-                        0x164 0x101     /*  MCSPI2_CLK INPUTENABLE | MODE1 */
-                        0x168 0x101     /*  MCSPI2_SIMO INPUTENABLE | MODE1 */
-                        0x16a 0x101     /*  MCSPI2_SOMI INPUTENABLE | MODE1 */
-                        0x16c 0x101     /*  MCSPI2_CS INPUTENABLE | MODE1 */
-                >;
-        };
-};
-
-&mmc1 {
-        vmmc-supply = <&vmmcsd_fixed>;
-        bus-width = <4>;
-};
-
-&mmc2 {
-        vmmc-supply = <&vmmcsd_fixed>;
-        bus-width = <8>;
-        ti,non-removable;
-};
-
-&mmc3 {
-        bus-width = <4>;
-        ti,non-removable;
-};
-
-&mmc4 {
-        status = "disabled";
-};
-
-&mmc5 {
-        status = "disabled";
-};
-
-&i2c1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c1_pins>;
-
-        clock-frequency = <400000>;
-};
-
-&i2c2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c2_pins>;
-
-        clock-frequency = <400000>;
-
-        /* Pressure Sensor */
-        bmp085@77 {
-                compatible = "bosch,bmp085";
-                reg = <0x77>;
-        };
-};
-
-&i2c3 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c3_pins>;
-
-        clock-frequency = <400000>;
-};
-
-&i2c4 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c4_pins>;
-
-        clock-frequency = <400000>;
-
-        /* Temperature Sensor */
-        tmp102@48{
-                compatible = "ti,tmp102";
-                reg = <0x48>;
-        };
-};
-
-&i2c5 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c5_pins>;
-
-        clock-frequency = <400000>;
-};
-
-&keypad {
-        keypad,num-rows = <8>;
-        keypad,num-columns = <8>;
-        linux,keymap = <0x02020073      /* VOLUP */
-                        0x02030072      /* VOLDOWM */
-                        0x020400e7      /* SEND */
-                        0x02050066      /* HOME */
-                        0x0206006b      /* END */
-                        0x020700d9>;    /* SEARCH */
-        linux,input-no-autorepeat;
-};
-
-&mcbsp3 {
-        status = "disabled";
-};
-
-&emif1 {
-        cs1-used;
-        device-handle = <&samsung_K3PE0E000B>;
-};
-
-&emif2 {
-        cs1-used;
-        device-handle = <&samsung_K3PE0E000B>;
-};
-
-&mcspi1 {
-
-};
-
-&mcspi2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mcspi2_pins>;
-};
-
-&mcspi3 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mcspi3_pins>;
-};
-
-&mcspi4 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mcspi4_pins>;
-};
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
new file mode 100644
index 000000000000..08b72678abff
--- /dev/null
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -0,0 +1,485 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "omap5.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+        model = "TI OMAP5 uEVM board";
+        compatible = "ti,omap5-uevm", "ti,omap5";
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x7F000000>; /* 2032 MB */
+        };
+
+        vmmcsd_fixed: fixedregulator-mmcsd {
+                compatible = "regulator-fixed";
+                regulator-name = "vmmcsd_fixed";
+                regulator-min-microvolt = <3000000>;
+                regulator-max-microvolt = <3000000>;
+        };
+
+        /* HS USB Port 2 RESET */
+        hsusb2_reset: hsusb2_reset_reg {
+                compatible = "regulator-fixed";
+                regulator-name = "hsusb2_reset";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; /* gpio3_80 HUB_NRESET */
+                startup-delay-us = <70000>;
+                enable-active-high;
+        };
+
+        /* HS USB Host PHY on PORT 2 */
+        hsusb2_phy: hsusb2_phy {
+                compatible = "usb-nop-xceiv";
+                reset-supply = <&hsusb2_reset>;
+        /**
+          * FIXME
+          * Put the right clock phandle here when available
+          *     clocks = <&auxclk1>;
+          *     clock-names = "main_clk";
+          */
+                clock-frequency = <19200000>;
+        };
+
+        /* HS USB Port 3 RESET */
+        hsusb3_reset: hsusb3_reset_reg {
+                compatible = "regulator-fixed";
+                regulator-name = "hsusb3_reset";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; /* gpio3_79 ETH_NRESET */
+                startup-delay-us = <70000>;
+                enable-active-high;
+        };
+
+        /* HS USB Host PHY on PORT 3 */
+        hsusb3_phy: hsusb3_phy {
+                compatible = "usb-nop-xceiv";
+                reset-supply = <&hsusb3_reset>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                led@1 {
+                        label = "omap5:blue:usr1";
+                        gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */
+                        linux,default-trigger = "heartbeat";
+                        default-state = "off";
+                };
+        };
+};
+
+&omap5_pmx_core {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &twl6040_pins
+                        &mcpdm_pins
+                        &dmic_pins
+                        &mcbsp1_pins
+                        &mcbsp2_pins
+                        &usbhost_pins
+                        &led_gpio_pins
+        >;
+
+        twl6040_pins: pinmux_twl6040_pins {
+                pinctrl-single,pins = <
+                        0x18a (PIN_OUTPUT | MUX_MODE6)  /* perslimbus2_clock.gpio5_145 */
+                >;
+        };
+
+        mcpdm_pins: pinmux_mcpdm_pins {
+                pinctrl-single,pins = <
+                        0x142 (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* abe_clks.abe_clks */
+                        0x15c (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* abemcpdm_ul_data.abemcpdm_ul_data */
+                        0x15e (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* abemcpdm_dl_data.abemcpdm_dl_data */
+                        0x160 (PIN_INPUT_PULLUP | MUX_MODE0)    /* abemcpdm_frame.abemcpdm_frame */
+                        0x162 (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* abemcpdm_lb_clk.abemcpdm_lb_clk */
+                >;
+        };
+
+        dmic_pins: pinmux_dmic_pins {
+                pinctrl-single,pins = <
+                        0x144 (PIN_INPUT | MUX_MODE0)           /* abedmic_din1.abedmic_din1 */
+                        0x146 (PIN_INPUT | MUX_MODE0)           /* abedmic_din2.abedmic_din2 */
+                        0x148 (PIN_INPUT | MUX_MODE0)           /* abedmic_din3.abedmic_din3 */
+                        0x14a (PIN_OUTPUT | MUX_MODE0)          /* abedmic_clk1.abedmic_clk1 */
+                >;
+        };
+
+        mcbsp1_pins: pinmux_mcbsp1_pins {
+                pinctrl-single,pins = <
+                        0x14c (PIN_INPUT | MUX_MODE1)           /* abedmic_clk2.abemcbsp1_fsx */
+                        0x14e (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* abedmic_clk3.abemcbsp1_dx */
+                        0x150 (PIN_INPUT | MUX_MODE1)           /* abeslimbus1_clock.abemcbsp1_clkx */
+                        0x152 (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* abeslimbus1_data.abemcbsp1_dr */
+                >;
+        };
+
+        mcbsp2_pins: pinmux_mcbsp2_pins {
+                pinctrl-single,pins = <
+                        0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* abemcbsp2_dr.abemcbsp2_dr */
+                        0x156 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dx.abemcbsp2_dx */
+                        0x158 (PIN_INPUT | MUX_MODE0)           /* abemcbsp2_fsx.abemcbsp2_fsx */
+                        0x15a (PIN_INPUT | MUX_MODE0)           /* abemcbsp2_clkx.abemcbsp2_clkx */
+                >;
+        };
+
+        i2c1_pins: pinmux_i2c1_pins {
+                pinctrl-single,pins = <
+                        0x1b2 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c1_scl */
+                        0x1b4 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c1_sda */
+                >;
+        };
+
+        i2c5_pins: pinmux_i2c5_pins {
+                pinctrl-single,pins = <
+                        0x184 (PIN_INPUT | MUX_MODE0)           /* i2c5_scl */
+                        0x186 (PIN_INPUT | MUX_MODE0)           /* i2c5_sda */
+                >;
+        };
+
+        mcspi2_pins: pinmux_mcspi2_pins {
+                pinctrl-single,pins = <
+                        0xbc (PIN_INPUT | MUX_MODE0)            /*  mcspi2_clk */
+                        0xbe (PIN_INPUT | MUX_MODE0)            /*  mcspi2_simo */
+                        0xc0 (PIN_INPUT_PULLUP | MUX_MODE0)     /*  mcspi2_somi */
+                        0xc2 (PIN_OUTPUT | MUX_MODE0)           /*  mcspi2_cs */
+                >;
+        };
+
+        mcspi3_pins: pinmux_mcspi3_pins {
+                pinctrl-single,pins = <
+                        0x78 (PIN_INPUT | MUX_MODE1)            /*  mcspi2_somi */
+                        0x7a (PIN_INPUT | MUX_MODE1)            /*  mcspi2_cs */
+                        0x7c (PIN_INPUT | MUX_MODE1)            /*  mcspi2_simo */
+                        0x7e (PIN_INPUT | MUX_MODE1)            /*  mcspi2_clk */
+                >;
+        };
+
+        mcspi4_pins: pinmux_mcspi4_pins {
+                pinctrl-single,pins = <
+                        0x164 (PIN_INPUT | MUX_MODE1)           /*  mcspi2_clk */
+                        0x168 (PIN_INPUT | MUX_MODE1)           /*  mcspi2_simo */
+                        0x16a (PIN_INPUT | MUX_MODE1)           /*  mcspi2_somi */
+                        0x16c (PIN_INPUT | MUX_MODE1)           /*  mcspi2_cs */
+                >;
+        };
+
+        usbhost_pins: pinmux_usbhost_pins {
+                pinctrl-single,pins = <
+                        0x84 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */
+                        0x86 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */
+
+                        0x19e (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */
+                        0x1a0 (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */
+
+                        0x70 (PIN_OUTPUT | MUX_MODE6) /* gpio3_80 HUB_NRESET */
+                        0x6e (PIN_OUTPUT | MUX_MODE6) /* gpio3_79 ETH_NRESET */
+                >;
+        };
+
+        led_gpio_pins: pinmux_led_gpio_pins {
+                pinctrl-single,pins = <
+                        0x196 (PIN_OUTPUT | MUX_MODE6) /* uart3_cts_rctx.gpio5_153 */
+                >;
+        };
+
+        uart1_pins: pinmux_uart1_pins {
+                pinctrl-single,pins = <
+                        0x60 (PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_cts */
+                        0x62 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_tx.uart1_cts */
+                        0x64 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rx.uart1_rts */
+                        0x66 (PIN_OUTPUT | MUX_MODE0) /* uart1_rx.uart1_rts */
+                >;
+        };
+
+        uart3_pins: pinmux_uart3_pins {
+                pinctrl-single,pins = <
+                        0x19a (PIN_OUTPUT | MUX_MODE0) /* uart3_rts_irsd.uart3_tx_irtx */
+                        0x19c (PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_rx_irrx.uart3_usbb3_hsic */
+                >;
+        };
+
+        uart5_pins: pinmux_uart5_pins {
+                pinctrl-single,pins = <
+                        0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_rx.uart5_rx */
+                        0x172 (PIN_OUTPUT | MUX_MODE0) /* uart5_tx.uart5_tx */
+                        0x174 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_cts.uart5_rts */
+                        0x176 (PIN_OUTPUT | MUX_MODE0) /* uart5_cts.uart5_rts */
+                >;
+        };
+
+};
+
+&omap5_pmx_wkup {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &usbhost_wkup_pins
+        >;
+
+        usbhost_wkup_pins: pinmux_usbhost_wkup_pins {
+                pinctrl-single,pins = <
+                        0x1A (PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */
+                >;
+        };
+};
+
+&mmc1 {
+        vmmc-supply = <&vmmcsd_fixed>;
+        bus-width = <4>;
+};
+
+&mmc2 {
+        vmmc-supply = <&vmmcsd_fixed>;
+        bus-width = <8>;
+        ti,non-removable;
+};
+
+&mmc3 {
+        bus-width = <4>;
+        ti,non-removable;
+};
+
+&mmc4 {
+        status = "disabled";
+};
+
+&mmc5 {
+        status = "disabled";
+};
+
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_pins>;
+
+        clock-frequency = <400000>;
+
+        palmas: palmas@48 {
+                compatible = "ti,palmas";
+                interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
+                interrupt-parent = <&gic>;
+                reg = <0x48>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+
+                palmas_pmic {
+                        compatible = "ti,palmas-pmic";
+                        interrupt-parent = <&palmas>;
+                        interrupts = <14 IRQ_TYPE_NONE>;
+                        interrupt-name = "short-irq";
+
+                        ti,ldo6-vibrator;
+
+                        regulators {
+                                smps123_reg: smps123 {
+                                        regulator-name = "smps123";
+                                        regulator-min-microvolt = < 600000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                smps45_reg: smps45 {
+                                        regulator-name = "smps45";
+                                        regulator-min-microvolt = < 600000>;
+                                        regulator-max-microvolt = <1310000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                smps6_reg: smps6 {
+                                        regulator-name = "smps6";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                smps7_reg: smps7 {
+                                        regulator-name = "smps7";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                smps8_reg: smps8 {
+                                        regulator-name = "smps8";
+                                        regulator-min-microvolt = < 600000>;
+                                        regulator-max-microvolt = <1310000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                smps9_reg: smps9 {
+                                        regulator-name = "smps9";
+                                        regulator-min-microvolt = <2100000>;
+                                        regulator-max-microvolt = <2100000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        ti,smps-range = <0x80>;
+                                };
+
+                                smps10_reg: smps10 {
+                                        regulator-name = "smps10";
+                                        regulator-min-microvolt = <5000000>;
+                                        regulator-max-microvolt = <5000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo1_reg: ldo1 {
+                                        regulator-name = "ldo1";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo2_reg: ldo2 {
+                                        regulator-name = "ldo2";
+                                        regulator-min-microvolt = <2900000>;
+                                        regulator-max-microvolt = <2900000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo3_reg: ldo3 {
+                                        regulator-name = "ldo3";
+                                        regulator-min-microvolt = <3000000>;
+                                        regulator-max-microvolt = <3000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo4_reg: ldo4 {
+                                        regulator-name = "ldo4";
+                                        regulator-min-microvolt = <2200000>;
+                                        regulator-max-microvolt = <2200000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo5_reg: ldo5 {
+                                        regulator-name = "ldo5";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo6_reg: ldo6 {
+                                        regulator-name = "ldo6";
+                                        regulator-min-microvolt = <1500000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo7_reg: ldo7 {
+                                        regulator-name = "ldo7";
+                                        regulator-min-microvolt = <1500000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo8_reg: ldo8 {
+                                        regulator-name = "ldo8";
+                                        regulator-min-microvolt = <1500000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo9_reg: ldo9 {
+                                        regulator-name = "ldo9";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldoln_reg: ldoln {
+                                        regulator-name = "ldoln";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldousb_reg: ldousb {
+                                        regulator-name = "ldousb";
+                                        regulator-min-microvolt = <3250000>;
+                                        regulator-max-microvolt = <3250000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                        };
+                };
+        };
+};
+
+&i2c5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c5_pins>;
+
+        clock-frequency = <400000>;
+};
+
+&mcbsp3 {
+        status = "disabled";
+};
+
+&usbhshost {
+        port2-mode = "ehci-hsic";
+        port3-mode = "ehci-hsic";
+};
+
+&usbhsehci {
+        phys = <0 &hsusb2_phy &hsusb3_phy>;
+};
+
+&mcspi1 {
+
+};
+
+&mcspi2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcspi2_pins>;
+};
+
+&mcspi3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcspi3_pins>;
+};
+
+&mcspi4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcspi4_pins>;
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart1_pins>;
+};
+
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins>;
+};
+
+&uart5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart5_pins>;
+};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 635cae283011..e643620417a9 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -7,15 +7,11 @@
  * Based on "omap4.dtsi"
  */
 
-/*
- * Carveout for multimedia usecases
- * It should be the last 48MB of the first 512MB memory part
- * In theory, it should not even exist. That zone should be reserved
- * dynamically during the .reserve callback.
- */
-/memreserve/ 0x9d000000 0x03000000;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/omap.h>
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
         #address-cells = <1>;
@@ -34,21 +30,28 @@
         };
 
         cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
                 cpu@0 {
+                        device_type = "cpu";
                         compatible = "arm,cortex-a15";
+                        reg = <0x0>;
                 };
                 cpu@1 {
+                        device_type = "cpu";
                         compatible = "arm,cortex-a15";
+                        reg = <0x1>;
                 };
         };
 
         timer {
                 compatible = "arm,armv7-timer";
-                /* PPI secure/nonsecure IRQ, active low level-sensitive */
-                interrupts = <1 13 0x308>,
-                             <1 14 0x308>,
-                             <1 11 0x308>,
-                             <1 10 0x308>;
+                /* PPI secure/nonsecure IRQ */
+                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
                 clock-frequency = <6144000>;
         };
 
@@ -90,8 +93,8 @@
                 reg = <0x44000000 0x2000>,
                       <0x44800000 0x3000>,
                       <0x45000000 0x4000>;
-                interrupts = <0 9 0x4>,
-                             <0 10 0x4>;
+                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
                 counter32k: counter@4ae04000 {
                         compatible = "ti,omap-counter32k";
@@ -119,10 +122,10 @@
                 sdma: dma-controller@4a056000 {
                         compatible = "ti,omap4430-sdma";
                         reg = <0x4a056000 0x1000>;
-                        interrupts = <0 12 0x4>,
-                                     <0 13 0x4>,
-                                     <0 14 0x4>,
-                                     <0 15 0x4>;
+                        interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                         #dma-cells = <1>;
                         #dma-channels = <32>;
                         #dma-requests = <127>;
@@ -131,7 +134,7 @@
                 gpio1: gpio@4ae10000 {
                         compatible = "ti,omap4-gpio";
                         reg = <0x4ae10000 0x200>;
-                        interrupts = <0 29 0x4>;
+                        interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "gpio1";
                         ti,gpio-always-on;
                         gpio-controller;
@@ -143,7 +146,7 @@
                 gpio2: gpio@48055000 {
                         compatible = "ti,omap4-gpio";
                         reg = <0x48055000 0x200>;
-                        interrupts = <0 30 0x4>;
+                        interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "gpio2";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -154,7 +157,7 @@
                 gpio3: gpio@48057000 {
                         compatible = "ti,omap4-gpio";
                         reg = <0x48057000 0x200>;
-                        interrupts = <0 31 0x4>;
+                        interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "gpio3";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -165,7 +168,7 @@
                 gpio4: gpio@48059000 {
                         compatible = "ti,omap4-gpio";
                         reg = <0x48059000 0x200>;
-                        interrupts = <0 32 0x4>;
+                        interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "gpio4";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -176,7 +179,7 @@
                 gpio5: gpio@4805b000 {
                         compatible = "ti,omap4-gpio";
                         reg = <0x4805b000 0x200>;
-                        interrupts = <0 33 0x4>;
+                        interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "gpio5";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -187,7 +190,7 @@
                 gpio6: gpio@4805d000 {
                         compatible = "ti,omap4-gpio";
                         reg = <0x4805d000 0x200>;
-                        interrupts = <0 34 0x4>;
+                        interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "gpio6";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -198,7 +201,7 @@
                 gpio7: gpio@48051000 {
                         compatible = "ti,omap4-gpio";
                         reg = <0x48051000 0x200>;
-                        interrupts = <0 35 0x4>;
+                        interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "gpio7";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -209,7 +212,7 @@
                 gpio8: gpio@48053000 {
                         compatible = "ti,omap4-gpio";
                         reg = <0x48053000 0x200>;
-                        interrupts = <0 121 0x4>;
+                        interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "gpio8";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -222,7 +225,7 @@
                         reg = <0x50000000 0x1000>;
                         #address-cells = <2>;
                         #size-cells = <1>;
-                        interrupts = <0 20 0x4>;
+                        interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
                         gpmc,num-cs = <8>;
                         gpmc,num-waitpins = <4>;
                         ti,hwmods = "gpmc";
@@ -231,7 +234,7 @@
                 i2c1: i2c@48070000 {
                         compatible = "ti,omap4-i2c";
                         reg = <0x48070000 0x100>;
-                        interrupts = <0 56 0x4>;
+                        interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c1";
@@ -240,7 +243,7 @@
                 i2c2: i2c@48072000 {
                         compatible = "ti,omap4-i2c";
                         reg = <0x48072000 0x100>;
-                        interrupts = <0 57 0x4>;
+                        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c2";
@@ -249,7 +252,7 @@
                 i2c3: i2c@48060000 {
                         compatible = "ti,omap4-i2c";
                         reg = <0x48060000 0x100>;
-                        interrupts = <0 61 0x4>;
+                        interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c3";
@@ -258,7 +261,7 @@
                 i2c4: i2c@4807a000 {
                         compatible = "ti,omap4-i2c";
                         reg = <0x4807a000 0x100>;
-                        interrupts = <0 62 0x4>;
+                        interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c4";
@@ -267,7 +270,7 @@
                 i2c5: i2c@4807c000 {
                         compatible = "ti,omap4-i2c";
                         reg = <0x4807c000 0x100>;
-                        interrupts = <0 60 0x4>;
+                        interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c5";
@@ -276,7 +279,7 @@
                 mcspi1: spi@48098000 {
                         compatible = "ti,omap4-mcspi";
                         reg = <0x48098000 0x200>;
-                        interrupts = <0 65 0x4>;
+                        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "mcspi1";
@@ -296,7 +299,7 @@
                 mcspi2: spi@4809a000 {
                         compatible = "ti,omap4-mcspi";
                         reg = <0x4809a000 0x200>;
-                        interrupts = <0 66 0x4>;
+                        interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "mcspi2";
@@ -311,7 +314,7 @@
                 mcspi3: spi@480b8000 {
                         compatible = "ti,omap4-mcspi";
                         reg = <0x480b8000 0x200>;
-                        interrupts = <0 91 0x4>;
+                        interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "mcspi3";
@@ -323,7 +326,7 @@
                 mcspi4: spi@480ba000 {
                         compatible = "ti,omap4-mcspi";
                         reg = <0x480ba000 0x200>;
-                        interrupts = <0 48 0x4>;
+                        interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "mcspi4";
@@ -335,7 +338,7 @@
                 uart1: serial@4806a000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x4806a000 0x100>;
-                        interrupts = <0 72 0x4>;
+                        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart1";
                         clock-frequency = <48000000>;
                 };
@@ -343,7 +346,7 @@
                 uart2: serial@4806c000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x4806c000 0x100>;
-                        interrupts = <0 73 0x4>;
+                        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart2";
                         clock-frequency = <48000000>;
                 };
@@ -351,7 +354,7 @@
                 uart3: serial@48020000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x48020000 0x100>;
-                        interrupts = <0 74 0x4>;
+                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart3";
                         clock-frequency = <48000000>;
                 };
@@ -359,7 +362,7 @@
                 uart4: serial@4806e000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x4806e000 0x100>;
-                        interrupts = <0 70 0x4>;
+                        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart4";
                         clock-frequency = <48000000>;
                 };
@@ -367,7 +370,7 @@
                 uart5: serial@48066000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x48066000 0x100>;
-                        interrupts = <0 105 0x4>;
+                        interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart5";
                         clock-frequency = <48000000>;
                 };
@@ -375,7 +378,7 @@
                 uart6: serial@48068000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x48068000 0x100>;
-                        interrupts = <0 106 0x4>;
+                        interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart6";
                         clock-frequency = <48000000>;
                 };
@@ -383,7 +386,7 @@
                 mmc1: mmc@4809c000 {
                         compatible = "ti,omap4-hsmmc";
                         reg = <0x4809c000 0x400>;
-                        interrupts = <0 83 0x4>;
+                        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mmc1";
                         ti,dual-volt;
                         ti,needs-special-reset;
@@ -394,7 +397,7 @@
                 mmc2: mmc@480b4000 {
                         compatible = "ti,omap4-hsmmc";
                         reg = <0x480b4000 0x400>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mmc2";
                         ti,needs-special-reset;
                         dmas = <&sdma 47>, <&sdma 48>;
@@ -404,7 +407,7 @@
                 mmc3: mmc@480ad000 {
                         compatible = "ti,omap4-hsmmc";
                         reg = <0x480ad000 0x400>;
-                        interrupts = <0 94 0x4>;
+                        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mmc3";
                         ti,needs-special-reset;
                         dmas = <&sdma 77>, <&sdma 78>;
@@ -414,7 +417,7 @@
                 mmc4: mmc@480d1000 {
                         compatible = "ti,omap4-hsmmc";
                         reg = <0x480d1000 0x400>;
-                        interrupts = <0 96 0x4>;
+                        interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mmc4";
                         ti,needs-special-reset;
                         dmas = <&sdma 57>, <&sdma 58>;
@@ -424,7 +427,7 @@
                 mmc5: mmc@480d5000 {
                         compatible = "ti,omap4-hsmmc";
                         reg = <0x480d5000 0x400>;
-                        interrupts = <0 59 0x4>;
+                        interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mmc5";
                         ti,needs-special-reset;
                         dmas = <&sdma 59>, <&sdma 60>;
@@ -442,7 +445,7 @@
                         reg = <0x40132000 0x7f>, /* MPU private access */
                               <0x49032000 0x7f>; /* L3 Interconnect */
                         reg-names = "mpu", "dma";
-                        interrupts = <0 112 0x4>;
+                        interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mcpdm";
                         dmas = <&sdma 65>,
                                <&sdma 66>;
@@ -454,7 +457,7 @@
                         reg = <0x4012e000 0x7f>, /* MPU private access */
                               <0x4902e000 0x7f>; /* L3 Interconnect */
                         reg-names = "mpu", "dma";
-                        interrupts = <0 114 0x4>;
+                        interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "dmic";
                         dmas = <&sdma 67>;
                         dma-names = "up_link";
@@ -465,7 +468,7 @@
                         reg = <0x40122000 0xff>, /* MPU private access */
                               <0x49022000 0xff>; /* L3 Interconnect */
                         reg-names = "mpu", "dma";
-                        interrupts = <0 17 0x4>;
+                        interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "common";
                         ti,buffer-size = <128>;
                         ti,hwmods = "mcbsp1";
@@ -479,7 +482,7 @@
                         reg = <0x40124000 0xff>, /* MPU private access */
                               <0x49024000 0xff>; /* L3 Interconnect */
                         reg-names = "mpu", "dma";
-                        interrupts = <0 22 0x4>;
+                        interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "common";
                         ti,buffer-size = <128>;
                         ti,hwmods = "mcbsp2";
@@ -493,7 +496,7 @@
                         reg = <0x40126000 0xff>, /* MPU private access */
                               <0x49026000 0xff>; /* L3 Interconnect */
                         reg-names = "mpu", "dma";
-                        interrupts = <0 23 0x4>;
+                        interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "common";
                         ti,buffer-size = <128>;
                         ti,hwmods = "mcbsp3";
@@ -505,7 +508,7 @@
                 timer1: timer@4ae18000 {
                         compatible = "ti,omap5430-timer";
                         reg = <0x4ae18000 0x80>;
-                        interrupts = <0 37 0x4>;
+                        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer1";
                         ti,timer-alwon;
                 };
@@ -513,21 +516,21 @@
                 timer2: timer@48032000 {
                         compatible = "ti,omap5430-timer";
                         reg = <0x48032000 0x80>;
-                        interrupts = <0 38 0x4>;
+                        interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer2";
                 };
 
                 timer3: timer@48034000 {
                         compatible = "ti,omap5430-timer";
                         reg = <0x48034000 0x80>;
-                        interrupts = <0 39 0x4>;
+                        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer3";
                 };
 
                 timer4: timer@48036000 {
                         compatible = "ti,omap5430-timer";
                         reg = <0x48036000 0x80>;
-                        interrupts = <0 40 0x4>;
+                        interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer4";
                 };
 
@@ -535,7 +538,7 @@
                         compatible = "ti,omap5430-timer";
                         reg = <0x40138000 0x80>,
                               <0x49038000 0x80>;
-                        interrupts = <0 41 0x4>;
+                        interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer5";
                         ti,timer-dsp;
                         ti,timer-pwm;
@@ -545,7 +548,7 @@
                         compatible = "ti,omap5430-timer";
                         reg = <0x4013a000 0x80>,
                               <0x4903a000 0x80>;
-                        interrupts = <0 42 0x4>;
+                        interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer6";
                         ti,timer-dsp;
                         ti,timer-pwm;
@@ -555,7 +558,7 @@
                         compatible = "ti,omap5430-timer";
                         reg = <0x4013c000 0x80>,
                               <0x4903c000 0x80>;
-                        interrupts = <0 43 0x4>;
+                        interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer7";
                         ti,timer-dsp;
                 };
@@ -564,7 +567,7 @@
                         compatible = "ti,omap5430-timer";
                         reg = <0x4013e000 0x80>,
                               <0x4903e000 0x80>;
-                        interrupts = <0 44 0x4>;
+                        interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer8";
                         ti,timer-dsp;
                         ti,timer-pwm;
@@ -573,7 +576,7 @@
                 timer9: timer@4803e000 {
                         compatible = "ti,omap5430-timer";
                         reg = <0x4803e000 0x80>;
-                        interrupts = <0 45 0x4>;
+                        interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer9";
                         ti,timer-pwm;
                 };
@@ -581,7 +584,7 @@
                 timer10: timer@48086000 {
                         compatible = "ti,omap5430-timer";
                         reg = <0x48086000 0x80>;
-                        interrupts = <0 46 0x4>;
+                        interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer10";
                         ti,timer-pwm;
                 };
@@ -589,7 +592,7 @@
                 timer11: timer@48088000 {
                         compatible = "ti,omap5430-timer";
                         reg = <0x48088000 0x80>;
-                        interrupts = <0 47 0x4>;
+                        interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer11";
                         ti,timer-pwm;
                 };
@@ -597,7 +600,7 @@
                 wdt2: wdt@4ae14000 {
                         compatible = "ti,omap5-wdt", "ti,omap3-wdt";
                         reg = <0x4ae14000 0x80>;
-                        interrupts = <0 80 0x4>;
+                        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "wd_timer2";
                 };
 
@@ -606,7 +609,7 @@
                         ti,hwmods       = "emif1";
                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
                         reg = <0x4c000000 0x400>;
-                        interrupts = <0 110 0x4>;
+                        interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
                         hw-caps-read-idle-ctrl;
                         hw-caps-ll-interface;
                         hw-caps-temp-alert;
@@ -617,7 +620,7 @@
                         ti,hwmods       = "emif2";
                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
                         reg = <0x4d000000 0x400>;
-                        interrupts = <0 111 0x4>;
+                        interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
                         hw-caps-read-idle-ctrl;
                         hw-caps-ll-interface;
                         hw-caps-temp-alert;
@@ -635,7 +638,7 @@
                         compatible = "ti,dwc3";
                         ti,hwmods = "usb_otg_ss";
                         reg = <0x4a020000 0x1000>;
-                        interrupts = <0 93 4>;
+                        interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <1>;
                         utmi-mode = <2>;
@@ -643,7 +646,7 @@
                         dwc3@4a030000 {
                                 compatible = "synopsys,dwc3";
                                 reg = <0x4a030000 0x1000>;
-                                interrupts = <0 92 4>;
+                                interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
                                 usb-phy = <&usb2_phy>, <&usb3_phy>;
                                 tx-fifo-resize;
                         };
@@ -670,5 +673,44 @@
                                 ctrl-module = <&omap_control_usb>;
                         };
                 };
+
+                usbhstll: usbhstll@4a062000 {
+                        compatible = "ti,usbhs-tll";
+                        reg = <0x4a062000 0x1000>;
+                        interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+                        ti,hwmods = "usb_tll_hs";
+                };
+
+                usbhshost: usbhshost@4a064000 {
+                        compatible = "ti,usbhs-host";
+                        reg = <0x4a064000 0x800>;
+                        ti,hwmods = "usb_host_hs";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        usbhsohci: ohci@4a064800 {
+                                compatible = "ti,ohci-omap3", "usb-ohci";
+                                reg = <0x4a064800 0x400>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+
+                        usbhsehci: ehci@4a064c00 {
+                                compatible = "ti,ehci-omap", "usb-ehci";
+                                reg = <0x4a064c00 0x400>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                };
+
+                bandgap@4a0021e0 {
+                        reg = <0x4a0021e0 0xc
+                               0x4a00232c 0xc
+                               0x4a002380 0x2c
+                               0x4a0023C0 0x3c>;
+                        interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+                        compatible = "ti,omap5430-bandgap";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
index f0a8c2068ea7..533919e96eae 100644
--- a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
+++ b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
@@ -18,13 +18,13 @@
         #size-cells = <1>;
 
         cpus {
-                #address-cells = <1>;
+                #address-cells = <0>;
                 #size-cells = <0>;
 
-                cpu@0 {
-                        compatible = "arm,1176jz-s";
+                cpu {
+                        compatible = "arm,arm1176jz-s";
+                        device_type = "cpu";
                         clock-frequency = <400000000>;
-                        reg = <0>;
                         d-cache-line-size = <32>;
                         d-cache-size = <32768>;
                         i-cache-line-size = <32>;
diff --git a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
index daa962d191e6..ab3e80085511 100644
--- a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
+++ b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
@@ -18,13 +18,13 @@
         #size-cells = <1>;
 
         cpus {
-                #address-cells = <1>;
+                #address-cells = <0>;
                 #size-cells = <0>;
 
-                cpu@0 {
-                        compatible = "arm,1176jz-s";
+                cpu {
+                        compatible = "arm,arm1176jz-s";
+                        device_type = "cpu";
                         cpu-clock = <&arm_clk>, "cpu";
-                        reg = <0>;
                         d-cache-line-size = <32>;
                         d-cache-size = <32768>;
                         i-cache-line-size = <32>;
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 3329719a9412..02edd8965f8a 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -18,6 +18,8 @@
                 #size-cells = <0>;
 
                 cpu@0 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                         reg = <0x0>;
                         d-cache-line-size = <32>;
                         i-cache-line-size = <32>;
diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi
index f18aad35e8b3..a5e90f078aa9 100644
--- a/arch/arm/boot/dts/pxa2xx.dtsi
+++ b/arch/arm/boot/dts/pxa2xx.dtsi
@@ -23,8 +23,11 @@
         };
 
         cpus {
-                cpu@0 {
-                        compatible = "arm,xscale";
+                #address-cells = <0>;
+                #size-cells = <0>;
+                cpu {
+                        compatible = "marvell,xscale";
+                        device_type = "cpu";
                 };
         };
 
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index fde2a337d1ff..4ff2019c0e30 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -37,12 +37,6 @@
                         <0 0xf1004000 0 0x2000>,
                         <0 0xf1006000 0 0x2000>;
                 interrupts = <1 9 0xf04>;
-
-                gic-cpuif@4 {
-                        compatible = "arm,gic-cpuif";
-                        cpuif-id = <4>;
-                        cpu = <&cpu0>;
-                };
         };
 
         timer {
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
new file mode 100644
index 000000000000..09ea22c26359
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
@@ -0,0 +1,45 @@
+/*
+ * Reference Device Tree Source for the armadillo 800 eva board
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "r8a7740.dtsi"
+
+/ {
+        model = "armadillo 800 eva reference";
+        compatible = "renesas,armadillo800eva-reference", "renesas,r8a7740";
+
+        chosen {
+                bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096 rw";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x40000000 0x20000000>;
+        };
+
+        reg_3p3v: regulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+
+};
+
+&i2c0 {
+        touchscreen: st1232@55 {
+                compatible = "sitronix,st1232";
+                reg = <0x55>;
+                interrupt-parent = <&irqpin1>;
+                interrupts = <2 0>; /* IRQ10: hwirq 2 on irqpin1 */
+        };
+};
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 798fa35c0005..24e930643821 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -14,8 +14,129 @@
         compatible = "renesas,r8a7740";
 
         cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
                 cpu@0 {
                         compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        reg = <0x0>;
                 };
         };
+
+        gic: interrupt-controller@c2800000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <1>;
+                interrupt-controller;
+                reg = <0xc2800000 0x1000>,
+                      <0xc2000000 0x1000>;
+        };
+
+        /* irqpin0: IRQ0 - IRQ7 */
+        irqpin0: irqpin@e6900000 {
+                compatible = "renesas,intc-irqpin";
+                #interrupt-cells = <2>;
+                interrupt-controller;
+                reg = <0xe6900000 4>,
+                        <0xe6900010 4>,
+                        <0xe6900020 1>,
+                        <0xe6900040 1>,
+                        <0xe6900060 1>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4>;
+        };
+
+        /* irqpin1: IRQ8 - IRQ15 */
+        irqpin1: irqpin@e6900004 {
+                compatible = "renesas,intc-irqpin";
+                #interrupt-cells = <2>;
+                interrupt-controller;
+                reg = <0xe6900004 4>,
+                        <0xe6900014 4>,
+                        <0xe6900024 1>,
+                        <0xe6900044 1>,
+                        <0xe6900064 1>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4>;
+        };
+
+        /* irqpin2: IRQ16 - IRQ23 */
+        irqpin2: irqpin@e6900008 {
+                compatible = "renesas,intc-irqpin";
+                #interrupt-cells = <2>;
+                interrupt-controller;
+                reg = <0xe6900008 4>,
+                        <0xe6900018 4>,
+                        <0xe6900028 1>,
+                        <0xe6900048 1>,
+                        <0xe6900068 1>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4>;
+        };
+
+        /* irqpin3: IRQ24 - IRQ31 */
+        irqpin3: irqpin@e690000c {
+                compatible = "renesas,intc-irqpin";
+                #interrupt-cells = <2>;
+                interrupt-controller;
+                reg = <0xe690000c 4>,
+                        <0xe690001c 4>,
+                        <0xe690002c 1>,
+                        <0xe690004c 1>,
+                        <0xe690006c 1>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4>;
+        };
+
+        i2c0: i2c@fff20000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0xfff20000 0x425>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 201 0x4
+                              0 202 0x4
+                              0 203 0x4
+                              0 204 0x4>;
+        };
+
+        i2c1: i2c@e6c20000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0xe6c20000 0x425>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 70 0x4
+                              0 71 0x4
+                              0 72 0x4
+                              0 73 0x4>;
+        };
 };
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index fe5c6f213271..7f146c6bf756 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -48,6 +48,23 @@
                       <0xf0000100 0x100>;
         };
 
+        irqpin0: irqpin@fe780010 {
+                compatible = "renesas,intc-irqpin";
+                #interrupt-cells = <2>;
+                interrupt-controller;
+                reg = <0xfe78001c 4>,
+                        <0xfe780010 4>,
+                        <0xfe780024 4>,
+                        <0xfe780044 4>,
+                        <0xfe780064 4>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 27 0x4
+                                0 28 0x4
+                                0 29 0x4
+                                0 30 0x4>;
+                sense-bitfield-width = <2>;
+        };
+
         i2c0: i2c@0xffc70000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 7a1711027e41..339d9b11721c 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -36,12 +36,6 @@
                         <0 0xf1004000 0 0x2000>,
                         <0 0xf1006000 0 0x2000>;
                 interrupts = <1 9 0xf04>;
-
-                gic-cpuif@4 {
-                        compatible = "arm,gic-cpuif";
-                        cpuif-id = <4>;
-                        cpu = <&cpu0>;
-                };
         };
 
         timer {
diff --git a/arch/arm/boot/dts/s3c2416-pinctrl.dtsi b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi
new file mode 100644
index 000000000000..527e3193817f
--- /dev/null
+++ b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi
@@ -0,0 +1,173 @@
+/*
+ * Samsung S3C2416 pinctrl settings
+ *
+ * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+&pinctrl_0 {
+        /*
+         * Pin banks
+         */
+
+        gpa: gpa {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpb: gpb {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpc: gpc {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpd: gpd {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpe: gpe {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpf: gpf {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpg: gpg {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gph: gph {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpj: gpj {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpk: gpk {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpl: gpl {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpm: gpm {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        /*
+         * Pin groups
+         */
+
+        uart0_data: uart0-data {
+                samsung,pins = "gph-0", "gph-1";
+                samsung,pin-function = <2>;
+        };
+
+        uart0_fctl: uart0-fctl {
+                samsung,pins = "gph-8", "gph-9";
+                samsung,pin-function = <2>;
+        };
+
+        uart1_data: uart1-data {
+                samsung,pins = "gph-2", "gph-3";
+                samsung,pin-function = <2>;
+        };
+
+        uart1_fctl: uart1-fctl {
+                samsung,pins = "gph-10", "gph-11";
+                samsung,pin-function = <2>;
+        };
+
+        uart2_data: uart2-data {
+                samsung,pins = "gph-4", "gph-5";
+                samsung,pin-function = <2>;
+        };
+
+        uart2_fctl: uart2-fctl {
+                samsung,pins = "gph-6", "gph-7";
+                samsung,pin-function = <2>;
+        };
+
+        uart3_data: uart3-data {
+                samsung,pins = "gph-6", "gph-7";
+                samsung,pin-function = <2>;
+        };
+
+        extuart_clk: extuart-clk {
+                samsung,pins = "gph-12";
+                samsung,pin-function = <2>;
+        };
+
+        i2c0_bus: i2c0-bus {
+                samsung,pins = "gpe-14", "gpe-15";
+                samsung,pin-function = <2>;
+        };
+
+        spi0_bus: spi0-bus {
+                samsung,pins = "gpe-11", "gpe-12", "gpe-13";
+                samsung,pin-function = <2>;
+        };
+
+        sd0_clk: sd0-clk {
+                samsung,pins = "gpe-5";
+                samsung,pin-function = <2>;
+        };
+
+        sd0_cmd: sd0-cmd {
+                samsung,pins = "gpe-6";
+                samsung,pin-function = <2>;
+        };
+
+        sd0_bus1: sd0-bus1 {
+                samsung,pins = "gpe-7";
+                samsung,pin-function = <2>;
+        };
+
+        sd0_bus4: sd0-bus4 {
+                samsung,pins = "gpe-8", "gpe-9", "gpe-10";
+                samsung,pin-function = <2>;
+        };
+
+        sd1_cmd: sd1-cmd {
+                samsung,pins = "gpl-8";
+                samsung,pin-function = <2>;
+        };
+
+        sd1_clk: sd1-clk {
+                samsung,pins = "gpl-9";
+                samsung,pin-function = <2>;
+        };
+
+        sd1_bus1: sd1-bus1 {
+                samsung,pins = "gpl-0";
+                samsung,pin-function = <2>;
+        };
+
+        sd1_bus4: sd1-bus4 {
+                samsung,pins = "gpl-1", "gpl-2", "gpl-3";
+                samsung,pin-function = <2>;
+        };
+};
diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts
new file mode 100644
index 000000000000..ad1dd09c10eb
--- /dev/null
+++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts
@@ -0,0 +1,72 @@
+/*
+ * SAMSUNG SMDK2416 board device tree source
+ *
+ * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+/include/ "s3c2416.dtsi"
+
+/ {
+        model = "SMDK2416";
+        compatible = "samsung,s3c2416";
+
+        memory {
+                reg =  <0x30000000 0x4000000>;
+        };
+
+        serial@50000000 {
+                status = "okay";
+                pinctrl-names = "default";
+                pinctrl-0 = <&uart0_data>, <&uart0_fctl>;
+        };
+
+        serial@50004000 {
+                status = "okay";
+                pinctrl-names = "default";
+                pinctrl-0 = <&uart1_data>, <&uart1_fctl>;
+        };
+
+        serial@50008000 {
+                status = "okay";
+                pinctrl-names = "default";
+                pinctrl-0 = <&uart2_data>;
+        };
+
+        serial@5000C000 {
+                status = "okay";
+                pinctrl-names = "default";
+                pinctrl-0 = <&uart3_data>;
+        };
+
+        watchdog@53000000 {
+                status = "okay";
+        };
+
+        rtc@57000000 {
+                status = "okay";
+        };
+
+        sdhci@4AC00000 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&sd0_clk>, <&sd0_cmd>,
+                                <&sd0_bus1>, <&sd0_bus4>;
+                bus-width = <4>;
+                cd-gpios = <&gpf 1 0>;
+                cd-inverted;
+                status = "okay";
+        };
+
+        sdhci@4A800000 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&sd1_clk>, <&sd1_cmd>,
+                                <&sd1_bus1>, <&sd1_bus4>;
+                bus-width = <4>;
+                broken-cd;
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi
new file mode 100644
index 000000000000..6809324934a3
--- /dev/null
+++ b/arch/arm/boot/dts/s3c2416.dtsi
@@ -0,0 +1,79 @@
+/*
+ * Samsung's S3C2416 SoC device tree source
+ *
+ * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/include/ "s3c24xx.dtsi"
+/include/ "s3c2416-pinctrl.dtsi"
+
+/ {
+        model = "Samsung S3C2416 SoC";
+        compatible = "samsung,s3c2416";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu {
+                        compatible = "arm,arm926ejs";
+                };
+        };
+
+        interrupt-controller@4a000000 {
+                compatible = "samsung,s3c2416-irq";
+        };
+
+        pinctrl@56000000 {
+                compatible = "samsung,s3c2416-pinctrl";
+        };
+
+        serial@50000000 {
+                compatible = "samsung,s3c2440-uart";
+        };
+
+        serial@50004000 {
+                compatible = "samsung,s3c2440-uart";
+        };
+
+        serial@50008000 {
+                compatible = "samsung,s3c2440-uart";
+        };
+
+        serial@5000C000 {
+                compatible = "samsung,s3c2440-uart";
+                reg = <0x5000C000 0x4000>;
+                interrupts = <1 18 24 4>, <1 18 25 4>;
+                status = "disabled";
+        };
+
+        sdhci@4AC00000 {
+                compatible = "samsung,s3c6410-sdhci";
+                reg = <0x4AC00000 0x100>;
+                interrupts = <0 0 21 3>;
+                status = "disabled";
+        };
+
+        sdhci@4A800000 {
+                compatible = "samsung,s3c6410-sdhci";
+                reg = <0x4A800000 0x100>;
+                interrupts = <0 0 20 3>;
+                status = "disabled";
+        };
+
+        watchdog@53000000 {
+                interrupts = <1 9 27 3>;
+        };
+
+        rtc@57000000 {
+                compatible = "samsung,s3c2416-rtc";
+        };
+
+        i2c@54000000 {
+                compatible = "samsung,s3c2440-i2c";
+        };
+};
diff --git a/arch/arm/boot/dts/s3c24xx.dtsi b/arch/arm/boot/dts/s3c24xx.dtsi
new file mode 100644
index 000000000000..cab46ff5fb4d
--- /dev/null
+++ b/arch/arm/boot/dts/s3c24xx.dtsi
@@ -0,0 +1,92 @@
+/*
+ * Samsung's S3C24XX family device tree source
+ *
+ * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "samsung,s3c24xx";
+        interrupt-parent = <&intc>;
+
+        aliases {
+                pinctrl0 = &pinctrl_0;
+        };
+
+        intc:interrupt-controller@4a000000 {
+                compatible = "samsung,s3c2410-irq";
+                reg = <0x4a000000 0x100>;
+                interrupt-controller;
+                #interrupt-cells = <4>;
+        };
+
+        pinctrl_0: pinctrl@56000000 {
+                reg = <0x56000000 0x1000>;
+
+                wakeup-interrupt-controller {
+                        compatible = "samsung,s3c2410-wakeup-eint";
+                        interrupts = <0 0 0 3>,
+                                     <0 0 1 3>,
+                                     <0 0 2 3>,
+                                     <0 0 3 3>,
+                                     <0 0 4 4>,
+                                     <0 0 5 4>;
+                };
+        };
+
+        timer@51000000 {
+                compatible = "samsung,s3c2410-pwm";
+                reg = <0x51000000 0x1000>;
+                interrupts = <0 0 10 3>, <0 0 11 3>, <0 0 12 3>, <0 0 13 3>, <0 0 14 3>;
+                #pwm-cells = <4>;
+        };
+
+        serial@50000000 {
+                compatible = "samsung,s3c2410-uart";
+                reg = <0x50000000 0x4000>;
+                interrupts = <1 28 0 4>, <1 28 1 4>;
+                status = "disabled";
+        };
+
+        serial@50004000 {
+                compatible = "samsung,s3c2410-uart";
+                reg = <0x50004000 0x4000>;
+                interrupts = <1 23 3 4>, <1 23 4 4>;
+                status = "disabled";
+        };
+
+        serial@50008000 {
+                compatible = "samsung,s3c2410-uart";
+                reg = <0x50008000 0x4000>;
+                interrupts = <1 15 6 4>, <1 15 7 4>;
+                status = "disabled";
+        };
+
+        watchdog@53000000 {
+                compatible = "samsung,s3c2410-wdt";
+                reg = <0x53000000 0x100>;
+                interrupts = <0 0 9 3>;
+                status = "disabled";
+        };
+
+        rtc@57000000 {
+                compatible = "samsung,s3c2410-rtc";
+                reg = <0x57000000 0x100>;
+                interrupts = <0 0 30 3>, <0 0 8 3>;
+                status = "disabled";
+        };
+
+        i2c@54000000 {
+                compatible = "samsung,s3c2410-i2c";
+                reg = <0x54000000 0x100>;
+                interrupts = <0 0 27 3>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index d5922935523f..a1d5e25a6698 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -9,6 +9,7 @@
  */
 
 #include "skeleton.dtsi"
+#include <dt-bindings/dma/at91.h>
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
@@ -38,8 +39,12 @@
                 ssc1 = &ssc1;
         };
         cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
                 cpu@0 {
+                        device_type = "cpu";
                         compatible = "arm,cortex-a5";
+                        reg = <0x0>;
                 };
         };
 
@@ -63,7 +68,7 @@
                                 compatible = "atmel,hsmci";
                                 reg = <0xf0000000 0x600>;
                                 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
-                                dmas = <&dma0 2 0>;
+                                dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>;
                                 dma-names = "rxtx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
@@ -75,9 +80,12 @@
                         spi0: spi@f0004000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
-                                compatible = "atmel,at91sam9x5-spi";
+                                compatible = "atmel,at91rm9200-spi";
                                 reg = <0xf0004000 0x100>;
                                 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
+                                dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>,
+                                       <&dma0 2 AT91_DMA_CFG_PER_ID(2)>;
+                                dma-names = "tx", "rx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_spi0>;
                                 status = "disabled";
@@ -111,8 +119,8 @@
                                 compatible = "atmel,at91sam9x5-i2c";
                                 reg = <0xf0014000 0x4000>;
                                 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>;
-                                dmas = <&dma0 2 7>,
-                                       <&dma0 2 8>;
+                                dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>,
+                                       <&dma0 2 AT91_DMA_CFG_PER_ID(8)>;
                                 dma-names = "tx", "rx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_i2c0>;
@@ -125,8 +133,8 @@
                                 compatible = "atmel,at91sam9x5-i2c";
                                 reg = <0xf0018000 0x4000>;
                                 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>;
-                                dmas = <&dma0 2 9>,
-                                       <&dma0 2 10>;
+                                dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>,
+                                       <&dma0 2 AT91_DMA_CFG_PER_ID(10)>;
                                 dma-names = "tx", "rx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_i2c1>;
@@ -173,7 +181,7 @@
                                 compatible = "atmel,hsmci";
                                 reg = <0xf8000000 0x600>;
                                 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>;
-                                dmas = <&dma1 2 0>;
+                                dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>;
                                 dma-names = "rxtx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
@@ -186,7 +194,7 @@
                                 compatible = "atmel,hsmci";
                                 reg = <0xf8004000 0x600>;
                                 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
-                                dmas = <&dma1 2 1>;
+                                dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>;
                                 dma-names = "rxtx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
@@ -198,9 +206,12 @@
                         spi1: spi@f8008000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
-                                compatible = "atmel,at91sam9x5-spi";
+                                compatible = "atmel,at91rm9200-spi";
                                 reg = <0xf8008000 0x100>;
                                 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
+                                dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>,
+                                       <&dma1 2 AT91_DMA_CFG_PER_ID(16)>;
+                                dma-names = "tx", "rx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_spi1>;
                                 status = "disabled";
@@ -299,8 +310,8 @@
                                 compatible = "atmel,at91sam9x5-i2c";
                                 reg = <0xf801c000 0x4000>;
                                 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>;
-                                dmas = <&dma1 2 11>,
-                                       <&dma1 2 12>;
+                                dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
+                                       <&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
                                 dma-names = "tx", "rx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi
index 677fc603f8b3..7bf020ecadf5 100644
--- a/arch/arm/boot/dts/sh7372.dtsi
+++ b/arch/arm/boot/dts/sh7372.dtsi
@@ -14,8 +14,13 @@
         compatible = "renesas,sh7372";
 
         cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
                 cpu@0 {
                         compatible = "arm,cortex-a8";
+                        device_type = "cpu";
+                        reg = <0x0>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index 5972abb55f9c..b6f759e830ed 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -18,6 +18,19 @@
         model = "KZM-A9-GT";
         compatible = "renesas,kzm9g-reference", "renesas,sh73a0";
 
+        cpus {
+                cpu@0 {
+                        cpu0-supply = <&vdd_dvfs>;
+                        operating-points = <
+                                /* kHz  uV */
+                                1196000 1315000
+                                 598000 1175000
+                                 398667 1065000
+                        >;
+                        voltage-tolerance = <1>; /* 1% */
+                };
+        };
+
         chosen {
                 bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200";
         };
@@ -59,6 +72,79 @@
         };
 };
 
+&i2c0 {
+        as3711@40 {
+                compatible = "ams,as3711";
+                reg = <0x40>;
+
+                regulators {
+                        vdd_dvfs: sd1 {
+                                regulator-name = "1.315V CPU";
+                                regulator-min-microvolt = <1050000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        sd2 {
+                                regulator-name = "1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        sd4 {
+                                regulator-name = "1.215V";
+                                regulator-min-microvolt = <1215000>;
+                                regulator-max-microvolt = <1235000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        ldo2 {
+                                regulator-name = "2.8V CPU";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        ldo3 {
+                                regulator-name = "3.0V CPU";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        ldo4 {
+                                regulator-name = "2.8V";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        ldo5 {
+                                regulator-name = "2.8V #2";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        ldo7 {
+                                regulator-name = "1.15V CPU";
+                                regulator-min-microvolt = <1150000>;
+                                regulator-max-microvolt = <1150000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        ldo8 {
+                                regulator-name = "1.15V CPU #2";
+                                regulator-min-microvolt = <1150000>;
+                                regulator-max-microvolt = <1150000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                };
+        };
+};
+
 &mmcif {
         bus-width = <8>;
         vmmc-supply = <&reg_1p8v>;
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index ec40bf78289e..b97750256003 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -119,7 +119,7 @@
                               0 32 0x4>;
         };
 
-        i2c0: i2c@0xe6820000 {
+        i2c0: i2c@e6820000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
                 compatible = "renesas,rmobile-iic";
@@ -131,7 +131,7 @@
                               0 170 0x4>;
         };
 
-        i2c1: i2c@0xe6822000 {
+        i2c1: i2c@e6822000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
                 compatible = "renesas,rmobile-iic";
@@ -143,7 +143,7 @@
                               0 54 0x4>;
         };
 
-        i2c2: i2c@0xe6824000 {
+        i2c2: i2c@e6824000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
                 compatible = "renesas,rmobile-iic";
@@ -155,7 +155,7 @@
                               0 174 0x4>;
         };
 
-        i2c3: i2c@0xe6826000 {
+        i2c3: i2c@e6826000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
                 compatible = "renesas,rmobile-iic";
@@ -167,7 +167,7 @@
                               0 186 0x4>;
         };
 
-        i2c4: i2c@0xe6828000 {
+        i2c4: i2c@e6828000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
                 compatible = "renesas,rmobile-iic";
@@ -179,7 +179,7 @@
                               0 190 0x4>;
         };
 
-        mmcif: mmcif@0x10010000 {
+        mmcif: mmcif@e6bd0000 {
                 compatible = "renesas,sh-mmcif";
                 reg = <0xe6bd0000 0x100>;
                 interrupt-parent = <&gic>;
@@ -189,7 +189,7 @@
                 status = "disabled";
         };
 
-        sdhi0: sdhi@0xee100000 {
+        sdhi0: sdhi@ee100000 {
                 compatible = "renesas,r8a7740-sdhi";
                 reg = <0xee100000 0x100>;
                 interrupt-parent = <&gic>;
@@ -201,7 +201,7 @@
         };
 
         /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
-        sdhi1: sdhi@0xee120000 {
+        sdhi1: sdhi@ee120000 {
                 compatible = "renesas,r8a7740-sdhi";
                 reg = <0xee120000 0x100>;
                 interrupt-parent = <&gic>;
@@ -212,7 +212,7 @@
                 status = "disabled";
         };
 
-        sdhi2: sdhi@0xee140000 {
+        sdhi2: sdhi@ee140000 {
                 compatible = "renesas,r8a7740-sdhi";
                 reg = <0xee140000 0x100>;
                 interrupt-parent = <&gic>;
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index db5db24fd544..fb9dce529da6 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -10,7 +10,7 @@
  */
 
 /dts-v1/;
-/include/ "dbx5x0.dtsi"
+#include "dbx5x0.dtsi"
 
 / {
         model = "Calao Systems Snowball platform with device tree";
@@ -82,7 +82,7 @@
                 };
         };
 
-        soc-u9500 {
+        soc {
 
                 sound {
                         compatible = "stericsson,snd-soc-mop500";
@@ -99,40 +99,13 @@
                         status = "okay";
                 };
 
-                prcmu@80157000 {
-                        thermal@801573c0 {
-                                num-trips = <4>;
-
-                                trip0-temp = <70000>;
-                                trip0-type = "active";
-                                trip0-cdev-num = <1>;
-                                trip0-cdev-name0 = "thermal-cpufreq-0";
-
-                                trip1-temp = <75000>;
-                                trip1-type = "active";
-                                trip1-cdev-num = <1>;
-                                trip1-cdev-name0 = "thermal-cpufreq-0";
-
-                                trip2-temp = <80000>;
-                                trip2-type = "active";
-                                trip2-cdev-num = <1>;
-                                trip2-cdev-name0 = "thermal-cpufreq-0";
-
-                                trip3-temp = <85000>;
-                                trip3-type = "critical";
-                                trip3-cdev-num = <0>;
-
-                                status = "okay";
-                         };
-                };
-
                 external-bus@50000000 {
                         status = "okay";
 
                         ethernet@0 {
                                 compatible = "smsc,lan9115";
                                 reg = <0 0x10000>;
-                                interrupts = <12 0x1>;
+                                interrupts = <12 IRQ_TYPE_EDGE_RISING>;
                                 interrupt-parent = <&gpio4>;
                                 vdd33a-supply = <&en_3v3_reg>;
                                 vddvario-supply = <&db8500_vape_reg>;
@@ -146,13 +119,21 @@
                         };
                 };
 
+                vmmci: regulator-gpio {
+                        gpios = <&gpio6 25 0x4>;
+                        enable-gpio = <&gpio7 4 0x4>;
+
+                        status = "okay";
+                };
+
                 // External Micro SD slot
                 sdi0_per1@80126000 {
                         arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                         bus-width = <4>;
                         mmc-cap-mmc-highspeed;
                         vmmc-supply = <&ab8500_ldo_aux3_reg>;
+                        vqmmc-supply = <&vmmci>;
 
                         cd-gpios  = <&gpio6 26 0x4>; // 218
                         cd-inverted;
@@ -163,7 +144,7 @@
                 // On-board eMMC
                 sdi4_per2@80114000 {
                         arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                         bus-width = <8>;
                         mmc-cap-mmc-highspeed;
                         vmmc-supply = <&ab8500_ldo_aux2_reg>;
@@ -197,15 +178,15 @@
                 };
 
                 i2c@80128000 {
-                        lp5521@0x33 {
+                        lp5521@33 {
                                 // compatible = "lp5521";
                                 reg = <0x33>;
                         };
-                        lp5521@0x34 {
+                        lp5521@34 {
                                 // compatible = "lp5521";
                                 reg = <0x34>;
                         };
-                        bh1780@0x29 {
+                        bh1780@29 {
                                 // compatible = "rohm,bh1780gli";
                                 reg = <0x33>;
                         };
@@ -298,6 +279,31 @@
                                 };
                         };
 
+                        thermal@801573c0 {
+                                num-trips = <4>;
+
+                                trip0-temp = <70000>;
+                                trip0-type = "active";
+                                trip0-cdev-num = <1>;
+                                trip0-cdev-name0 = "thermal-cpufreq-0";
+
+                                trip1-temp = <75000>;
+                                trip1-type = "active";
+                                trip1-cdev-num = <1>;
+                                trip1-cdev-name0 = "thermal-cpufreq-0";
+
+                                trip2-temp = <80000>;
+                                trip2-type = "active";
+                                trip2-cdev-num = <1>;
+                                trip2-cdev-name0 = "thermal-cpufreq-0";
+
+                                trip3-temp = <85000>;
+                                trip3-type = "critical";
+                                trip3-cdev-num = <0>;
+
+                                status = "okay";
+                        };
+
                         ab8500 {
                                 ab8500-gpio {
                                         compatible = "stericsson,ab8500-gpio";
@@ -316,7 +322,7 @@
                                                 regulator-name = "V-MMC-SD";
                                         };
 
-                                        ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
+                                        ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
                                                 regulator-name = "V-INTCORE";
                                         };
 
@@ -336,7 +342,7 @@
                                                 regulator-name = "V-AMIC1";
                                         };
 
-                                        ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
+                                        ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
                                                 regulator-name = "V-AMIC2";
                                         };
 
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 16a6e13e08b4..bee62a2cf6d6 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -23,6 +23,7 @@
 
         aliases {
                 ethernet0 = &gmac0;
+                ethernet1 = &gmac1;
                 serial0 = &uart0;
                 serial1 = &uart1;
                 timer0 = &timer0;
@@ -94,6 +95,12 @@
                                                 compatible = "fixed-clock";
                                         };
 
+                                        f2s_periph_ref_clk: f2s_periph_ref_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "fixed-clock";
+                                                clock-frequency = <10000000>;
+                                        };
+
                                         main_pll: main_pll {
                                                 #address-cells = <1>;
                                                 #size-cells = <0>;
@@ -235,16 +242,222 @@
                                                         reg = <0xD4>;
                                                 };
                                         };
+
+                                mpu_periph_clk: mpu_periph_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&mpuclk>;
+                                        fixed-divider = <4>;
+                                        };
+
+                                mpu_l2_ram_clk: mpu_l2_ram_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&mpuclk>;
+                                        fixed-divider = <2>;
+                                        };
+
+                                l4_main_clk: l4_main_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&mainclk>;
+                                        clk-gate = <0x60 0>;
+                                        };
+
+                                l3_main_clk: l3_main_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&mainclk>;
+                                        };
+
+                                l3_mp_clk: l3_mp_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&mainclk>;
+                                        div-reg = <0x64 0 2>;
+                                        clk-gate = <0x60 1>;
+                                        };
+
+                                l3_sp_clk: l3_sp_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&mainclk>;
+                                        div-reg = <0x64 2 2>;
+                                };
+
+                                l4_mp_clk: l4_mp_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&mainclk>, <&per_base_clk>;
+                                        div-reg = <0x64 4 3>;
+                                        clk-gate = <0x60 2>;
+                                        };
+
+                                l4_sp_clk: l4_sp_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&mainclk>, <&per_base_clk>;
+                                        div-reg = <0x64 7 3>;
+                                        clk-gate = <0x60 3>;
+                                        };
+
+                                dbg_at_clk: dbg_at_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&dbg_base_clk>;
+                                        div-reg = <0x68 0 2>;
+                                        clk-gate = <0x60 4>;
+                                        };
+
+                                dbg_clk: dbg_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&dbg_base_clk>;
+                                        div-reg = <0x68 2 2>;
+                                        clk-gate = <0x60 5>;
+                                        };
+
+                                dbg_trace_clk: dbg_trace_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&dbg_base_clk>;
+                                        div-reg = <0x6C 0 3>;
+                                        clk-gate = <0x60 6>;
+                                        };
+
+                                dbg_timer_clk: dbg_timer_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&dbg_base_clk>;
+                                        clk-gate = <0x60 7>;
+                                        };
+
+                                cfg_clk: cfg_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&cfg_s2f_usr0_clk>;
+                                        clk-gate = <0x60 8>;
+                                        };
+
+                                s2f_user0_clk: s2f_user0_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&cfg_s2f_usr0_clk>;
+                                        clk-gate = <0x60 9>;
+                                        };
+
+                                emac_0_clk: emac_0_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&emac0_clk>;
+                                        clk-gate = <0xa0 0>;
+                                        };
+
+                                emac_1_clk: emac_1_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&emac1_clk>;
+                                        clk-gate = <0xa0 1>;
+                                        };
+
+                                usb_mp_clk: usb_mp_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&per_base_clk>;
+                                        clk-gate = <0xa0 2>;
+                                        div-reg = <0xa4 0 3>;
+                                        };
+
+                                spi_m_clk: spi_m_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&per_base_clk>;
+                                        clk-gate = <0xa0 3>;
+                                        div-reg = <0xa4 3 3>;
+                                        };
+
+                                can0_clk: can0_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&per_base_clk>;
+                                        clk-gate = <0xa0 4>;
+                                        div-reg = <0xa4 6 3>;
+                                        };
+
+                                can1_clk: can1_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&per_base_clk>;
+                                        clk-gate = <0xa0 5>;
+                                        div-reg = <0xa4 9 3>;
+                                        };
+
+                                gpio_db_clk: gpio_db_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&per_base_clk>;
+                                        clk-gate = <0xa0 6>;
+                                        div-reg = <0xa8 0 24>;
+                                        };
+
+                                s2f_user1_clk: s2f_user1_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&s2f_usr1_clk>;
+                                        clk-gate = <0xa0 7>;
+                                        };
+
+                                sdmmc_clk: sdmmc_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+                                        clk-gate = <0xa0 8>;
+                                        };
+
+                                nand_x_clk: nand_x_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+                                        clk-gate = <0xa0 9>;
+                                        };
+
+                                nand_clk: nand_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+                                        clk-gate = <0xa0 10>;
+                                        fixed-divider = <4>;
+                                        };
+
+                                qspi_clk: qspi_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
+                                        clk-gate = <0xa0 11>;
+                                        };
                                 };
                         };
 
-                gmac0: stmmac@ff700000 {
+                gmac0: ethernet@ff700000 {
                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
                         reg = <0xff700000 0x2000>;
                         interrupts = <0 115 4>;
                         interrupt-names = "macirq";
                         mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
-                        phy-mode = "gmii";
+                        clocks = <&emac0_clk>;
+                        clock-names = "stmmaceth";
+                        status = "disabled";
+                };
+
+                gmac1: ethernet@ff702000 {
+                        compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
+                        reg = <0xff702000 0x2000>;
+                        interrupts = <0 120 4>;
+                        interrupt-names = "macirq";
+                        mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
+                        clocks = <&emac1_clk>;
+                        clock-names = "stmmaceth";
+                        status = "disabled";
                 };
 
                 L2: l2-cache@fffef000 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
index 2495958f1016..973999d2c697 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -32,6 +32,13 @@
                 reg = <0x0 0x40000000>; /* 1GB */
         };
 
+        aliases {
+                /* this allow the ethaddr uboot environmnet variable contents
+                 * to be added to the gmac1 device tree blob.
+                 */
+                ethernet0 = &gmac1;
+        };
+
         soc {
                 clkmgr@ffd04000 {
                         clocks {
@@ -41,6 +48,12 @@
                         };
                 };
 
+                ethernet@ff702000 {
+                        phy-mode = "rgmii";
+                        phy-addr = <0xffffffff>; /* probe for phy addr */
+                        status = "okay";
+                };
+
                 timer0@ffc08000 {
                         clock-frequency = <100000000>;
                 };
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index 0bf035d607f0..d1ec0cab2dee 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -41,6 +41,11 @@
                         };
                 };
 
+                ethernet@ff700000 {
+                        phy-mode = "gmii";
+                        status = "okay";
+                };
+
                 timer0@ffc08000 {
                         clock-frequency = <7000000>;
                 };
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 45597fd91050..4382547df58a 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -22,12 +22,14 @@
 
                 cpu@0 {
                         compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                         reg = <0>;
                         next-level-cache = <&L2>;
                 };
 
                 cpu@1 {
                         compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                         reg = <1>;
                         next-level-cache = <&L2>;
                 };
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
index c2a852d43c48..f0e3fcf8e323 100644
--- a/arch/arm/boot/dts/spear3xx.dtsi
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -17,8 +17,12 @@
         interrupt-parent = <&vic>;
 
         cpus {
-                cpu@0 {
-                        compatible = "arm,arm926ejs";
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                 };
         };
 
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index 19f99dc4115e..9f60a7b6a42b 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -15,8 +15,12 @@
         compatible = "st,spear600";
 
         cpus {
-                cpu@0 {
-                        compatible = "arm,arm926ejs";
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                 };
         };
 
diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/ste-nomadik-s8815.dts
index 6f82d9368948..16c3888b7b15 100644
--- a/arch/arm/boot/dts/ste-nomadik-s8815.dts
+++ b/arch/arm/boot/dts/ste-nomadik-s8815.dts
@@ -22,6 +22,49 @@
                 };
         };
 
+        src@101e0000 {
+                /* These chrystal drivers are not used on this board */
+                disable-sxtalo;
+                disable-mxtalo;
+        };
+
+        pinctrl {
+                /* Hog CD pins */
+                pinctrl-names = "default";
+                pinctrl-0 = <&cd_default_mode>;
+
+                mmcsd-cd {
+                        cd_default_mode: cd_default {
+                                cd_default_cfg1 {
+                                        /* CD input GPIO */
+                                        ste,pins = "GPIO111_H21";
+                                        ste,input = <0>;
+                                };
+                                cd_default_cfg2 {
+                                        /* CD GPIO biasing */
+                                        ste,pins = "GPIO112_J21";
+                                        ste,output = <0>;
+                                };
+                        };
+                };
+                user-led {
+                        user_led_default_mode: user_led_default {
+                                user_led_default_cfg {
+                                        ste,pins = "GPIO2_C5";
+                                        ste,output = <1>;
+                                };
+                        };
+                };
+                user-button {
+                        user_button_default_mode: user_button_default {
+                                user_button_default_cfg {
+                                        ste,pins = "GPIO3_A4";
+                                        ste,input = <0>;
+                                };
+                        };
+                };
+        };
+
         /* Custom board node with GPIO pins to active etc */
         usb-s8815 {
                 /* The S8815 is using this very GPIO pin for the SMSC91x IRQs */
@@ -33,4 +76,30 @@
                         gpios = <&gpio3 16 0x1>;
                 };
         };
+
+        /* The user LED on the board is set up to be used for heartbeat */
+        leds {
+                compatible = "gpio-leds";
+                user-led {
+                        label = "user_led";
+                        gpios = <&gpio0 2 0x1>;
+                        default-state = "off";
+                        linux,default-trigger = "heartbeat";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&user_led_default_mode>;
+                };
+        };
+
+        /* User key mapped in as "escape" */
+        gpio-keys {
+                compatible = "gpio-keys";
+                user-button {
+                        label = "user_button";
+                        gpios = <&gpio0 3 0x1>;
+                        linux,code = <1>; /* KEY_ESC */
+                        gpio-key,wakeup;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&user_button_default_mode>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
index 4a4aab395141..a3acfa7b3dc9 100644
--- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
+++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
@@ -21,18 +21,23 @@
                 cache-level = <2>;
         };
 
-        mtu0 {
+        mtu0: mtu@101e2000 {
                 /* Nomadik system timer */
+                compatible = "st,nomadik-mtu";
                 reg = <0x101e2000 0x1000>;
                 interrupt-parent = <&vica>;
                 interrupts = <4>;
+                clocks = <&timclk>, <&pclk>;
+                clock-names = "timclk", "apb_pclk";
         };
 
-        mtu1 {
+        mtu1: mtu@101e3000 {
                 /* Secondary timer */
                 reg = <0x101e3000 0x1000>;
                 interrupt-parent = <&vica>;
                 interrupts = <5>;
+                clocks = <&timclk>, <&pclk>;
+                clock-names = "timclk", "apb_pclk";
         };
 
         gpio0: gpio@101e4000 {
@@ -45,6 +50,7 @@
                 gpio-controller;
                 #gpio-cells = <2>;
                 gpio-bank = <0>;
+                clocks = <&pclk>;
         };
 
         gpio1: gpio@101e5000 {
@@ -57,6 +63,7 @@
                 gpio-controller;
                 #gpio-cells = <2>;
                 gpio-bank = <1>;
+                clocks = <&pclk>;
         };
 
         gpio2: gpio@101e6000 {
@@ -69,6 +76,7 @@
                 gpio-controller;
                 #gpio-cells = <2>;
                 gpio-bank = <2>;
+                clocks = <&pclk>;
         };
 
         gpio3: gpio@101e7000 {
@@ -81,10 +89,544 @@
                 gpio-controller;
                 #gpio-cells = <2>;
                 gpio-bank = <3>;
+                clocks = <&pclk>;
         };
 
         pinctrl {
-                compatible = "stericsson,nmk-pinctrl-stn8815";
+                compatible = "stericsson,stn8815-pinctrl";
+                /* Pin configurations */
+                uart0 {
+                        uart0_default_mux: uart0_mux {
+                                u0_default_mux {
+                                        ste,function = "u0";
+                                        ste,pins = "u0_a_1";
+                                };
+                        };
+                };
+                uart1 {
+                        uart1_default_mux: uart1_mux {
+                                u1_default_mux {
+                                        ste,function = "u1";
+                                        ste,pins = "u1_a_1";
+                                };
+                        };
+                };
+                mmcsd {
+                        mmcsd_default_mux: mmcsd_mux {
+                                mmcsd_default_mux {
+                                        ste,function = "mmcsd";
+                                        ste,pins = "mmcsd_a_1";
+                                };
+                        };
+                        mmcsd_default_mode: mmcsd_default {
+                                mmcsd_default_cfg1 {
+                                        /* MCCLK */
+                                        ste,pins = "GPIO8_B10";
+                                        ste,output = <0>;
+                                };
+                                mmcsd_default_cfg2 {
+                                        /* MCCMDDIR, MCDAT0DIR, MCDAT31DIR */
+                                        ste,pins = "GPIO10_C11", "GPIO15_A12",
+                                        "GPIO16_C13";
+                                        ste,output = <1>;
+                                };
+                                mmcsd_default_cfg3 {
+                                        /* MCCMD, MCDAT3-0, MCMSFBCLK */
+                                        ste,pins = "GPIO9_A10", "GPIO11_B11",
+                                        "GPIO12_A11", "GPIO13_C12",
+                                        "GPIO14_B12", "GPIO24_C15";
+                                        ste,input = <1>;
+                                };
+                        };
+                };
+                i2c0 {
+                        i2c0_default_mode: i2c0_default {
+                                i2c0_default_cfg {
+                                        ste,pins = "GPIO62_D3", "GPIO63_D2";
+                                        ste,input = <1>;
+                                };
+                        };
+                };
+                i2c1 {
+                        i2c1_default_mode: i2c1_default {
+                                i2c1_default_cfg {
+                                        ste,pins = "GPIO53_L4", "GPIO54_L3";
+                                        ste,input = <1>;
+                                };
+                        };
+                };
+                i2c2 {
+                        i2c2_default_mode: i2c2_default {
+                                i2c2_default_cfg {
+                                        ste,pins = "GPIO73_C21", "GPIO74_C20";
+                                        ste,input = <1>;
+                                };
+                        };
+                };
+        };
+
+        src: src@101e0000 {
+                compatible = "stericsson,nomadik-src";
+                reg = <0x101e0000 0x1000>;
+                disable-sxtalo;
+                disable-mxtalo;
+
+                /*
+                 * MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz
+                 * that is parent of TIMCLK, PLL1 and PLL2
+                 */
+                mxtal: mxtal@19.2M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <19200000>;
+                };
+
+                /*
+                 * The 2.4 MHz TIMCLK reference clock is active at
+                 * boot time, this is actually the MXTALCLK @19.2 MHz
+                 * divided by 8. This clock is used by the timers and
+                 * watchdog. See page 105 ff.
+                 */
+                timclk: timclk@2.4M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <8>;
+                        clock-mult = <1>;
+                        clocks = <&mxtal>;
+                };
+
+                /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */
+                pll1: pll1@0 {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-pll-clock";
+                        pll-id = <1>;
+                        clocks = <&mxtal>;
+                };
+
+                /* HCLK divides the PLL1 with 1,2,3 or 4 */
+                hclk: hclk@0 {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-hclk-clock";
+                        clocks = <&pll1>;
+                };
+                /* The PCLK domain uses HCLK right off */
+                pclk: pclk@0 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <1>;
+                        clock-mult = <1>;
+                        clocks = <&hclk>;
+                };
+
+                /* PLL2 is usually 864 MHz and divided into a few fixed rates */
+                pll2: pll2@0 {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-pll-clock";
+                        pll-id = <2>;
+                        clocks = <&mxtal>;
+                };
+                clk216: clk216@216M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <4>;
+                        clock-mult = <1>;
+                        clocks = <&pll2>;
+                };
+                clk108: clk108@108M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clocks = <&clk216>;
+                };
+                clk72: clk72@72M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        /* The data sheet does not say how this is derived */
+                        clock-div = <12>;
+                        clock-mult = <1>;
+                        clocks = <&pll2>;
+                };
+                clk48: clk48@48M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        /* The data sheet does not say how this is derived */
+                        clock-div = <18>;
+                        clock-mult = <1>;
+                        clocks = <&pll2>;
+                };
+                clk27: clk27@27M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <4>;
+                        clock-mult = <1>;
+                        clocks = <&clk108>;
+                };
+
+                /* This apparently exists as well */
+                ulpiclk: ulpiclk@60M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <60000000>;
+                };
+
+                /*
+                 * IP AMBA bus clocks, driving the bus side of the
+                 * peripheral clocking, clock gates.
+                 */
+
+                hclkdma0: hclkdma0@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <0>;
+                        clocks = <&hclk>;
+                };
+                hclksmc: hclksmc@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <1>;
+                        clocks = <&hclk>;
+                };
+                hclksdram: hclksdram@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <2>;
+                        clocks = <&hclk>;
+                };
+                hclkdma1: hclkdma1@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <3>;
+                        clocks = <&hclk>;
+                };
+                hclkclcd: hclkclcd@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <4>;
+                        clocks = <&hclk>;
+                };
+                pclkirda: pclkirda@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <5>;
+                        clocks = <&pclk>;
+                };
+                pclkssp: pclkssp@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <6>;
+                        clocks = <&pclk>;
+                };
+                pclkuart0: pclkuart0@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <7>;
+                        clocks = <&pclk>;
+                };
+                pclksdi: pclksdi@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <8>;
+                        clocks = <&pclk>;
+                };
+                pclki2c0: pclki2c0@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <9>;
+                        clocks = <&pclk>;
+                };
+                pclki2c1: pclki2c1@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <10>;
+                        clocks = <&pclk>;
+                };
+                pclkuart1: pclkuart1@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <11>;
+                        clocks = <&pclk>;
+                };
+                pclkmsp0: pclkmsp0@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <12>;
+                        clocks = <&pclk>;
+                };
+                hclkusb: hclkusb@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <13>;
+                        clocks = <&hclk>;
+                };
+                hclkdif: hclkdif@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <14>;
+                        clocks = <&hclk>;
+                };
+                hclksaa: hclksaa@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <15>;
+                        clocks = <&hclk>;
+                };
+                hclksva: hclksva@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <16>;
+                        clocks = <&hclk>;
+                };
+                pclkhsi: pclkhsi@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <17>;
+                        clocks = <&pclk>;
+                };
+                pclkxti: pclkxti@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <18>;
+                        clocks = <&pclk>;
+                };
+                pclkuart2: pclkuart2@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <19>;
+                        clocks = <&pclk>;
+                };
+                pclkmsp1: pclkmsp1@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <20>;
+                        clocks = <&pclk>;
+                };
+                pclkmsp2: pclkmsp2@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <21>;
+                        clocks = <&pclk>;
+                };
+                pclkowm: pclkowm@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <22>;
+                        clocks = <&pclk>;
+                };
+                hclkhpi: hclkhpi@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <23>;
+                        clocks = <&hclk>;
+                };
+                pclkske: pclkske@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <24>;
+                        clocks = <&pclk>;
+                };
+                pclkhsem: pclkhsem@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <25>;
+                        clocks = <&pclk>;
+                };
+                hclk3d: hclk3d@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <26>;
+                        clocks = <&hclk>;
+                };
+                hclkhash: hclkhash@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <27>;
+                        clocks = <&hclk>;
+                };
+                hclkcryp: hclkcryp@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <28>;
+                        clocks = <&hclk>;
+                };
+                pclkmshc: pclkmshc@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <29>;
+                        clocks = <&pclk>;
+                };
+                hclkusbm: hclkusbm@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <30>;
+                        clocks = <&hclk>;
+                };
+                hclkrng: hclkrng@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <31>;
+                        clocks = <&hclk>;
+                };
+
+                /* IP kernel clocks */
+                clcdclk: clcdclk@0 {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <36>;
+                        clocks = <&clk72 &clk48>;
+                };
+                irdaclk: irdaclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <37>;
+                        clocks = <&clk48>;
+                };
+                sspiclk: sspiclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <38>;
+                        clocks = <&clk48>;
+                };
+                uart0clk: uart0clk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <39>;
+                        clocks = <&clk48>;
+                };
+                sdiclk: sdiclk@48M {
+                        /* Also called MCCLK in some documents */
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <40>;
+                        clocks = <&clk48>;
+                };
+                i2c0clk: i2c0clk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <41>;
+                        clocks = <&clk48>;
+                };
+                i2c1clk: i2c1clk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <42>;
+                        clocks = <&clk48>;
+                };
+                uart1clk: uart1clk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <43>;
+                        clocks = <&clk48>;
+                };
+                mspclk0: mspclk0@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <44>;
+                        clocks = <&clk48>;
+                };
+                usbclk: usbclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <45>;
+                        clocks = <&clk48>; /* 48 MHz not ULPI */
+                };
+                difclk: difclk@72M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <46>;
+                        clocks = <&clk72>;
+                };
+                ipi2cclk: ipi2cclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <47>;
+                        clocks = <&clk48>; /* Guess */
+                };
+                ipbmcclk: ipbmcclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <48>;
+                        clocks = <&clk48>; /* Guess */
+                };
+                hsiclkrx: hsiclkrx@216M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <49>;
+                        clocks = <&clk216>;
+                };
+                hsiclktx: hsiclktx@108M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <50>;
+                        clocks = <&clk108>;
+                };
+                uart2clk: uart2clk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <51>;
+                        clocks = <&clk48>;
+                };
+                mspclk1: mspclk1@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <52>;
+                        clocks = <&clk48>;
+                };
+                mspclk2: mspclk2@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <53>;
+                        clocks = <&clk48>;
+                };
+                owmclk: owmclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <54>;
+                        clocks = <&clk48>; /* Guess */
+                };
+                skeclk: skeclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <56>;
+                        clocks = <&clk48>; /* Guess */
+                };
+                x3dclk: x3dclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <58>;
+                        clocks = <&clk48>; /* Guess */
+                };
+                pclkmsp3: pclkmsp3@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <59>;
+                        clocks = <&pclk>;
+                };
+                mspclk3: mspclk3@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <60>;
+                        clocks = <&clk48>;
+                };
+                mshcclk: mshcclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <61>;
+                        clocks = <&clk48>; /* Guess */
+                };
+                usbmclk: usbmclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <62>;
+                        /* Stated as "48 MHz not ULPI clock" */
+                        clocks = <&clk48>;
+                };
+                rngcclk: rngcclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <63>;
+                        clocks = <&clk48>; /* Guess */
+                };
         };
 
         /* A NAND flash of 128 MiB */
@@ -97,6 +639,7 @@
                         <0x41000000 0x2000>,    /* NAND Base ADDR */
                         <0x40800000 0x2000>;    /* NAND Base CMD */
                 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
+                clocks = <&hclksmc>;
                 status = "okay";
 
                 partition@0 {
@@ -144,6 +687,8 @@
                         <&gpio1 30 0>; /* scl */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c0_default_mode>;
 
                 stw4811@2d {
                            compatible = "st,stw4811";
@@ -158,6 +703,8 @@
                         <&gpio1 21 0>; /* scl */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c1_default_mode>;
 
                 camera@2d {
                            compatible = "st,camera";
@@ -180,6 +727,9 @@
                         <&gpio2 9 0>; /* scl */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c2_default_mode>;
+
                 stw4811@2d {
                            compatible = "st,stw4811-usb";
                            reg = <0x2d>;
@@ -211,6 +761,10 @@
                         reg = <0x101fd000 0x1000>;
                         interrupt-parent = <&vica>;
                         interrupts = <12>;
+                        clocks = <&uart0clk>, <&pclkuart0>;
+                        clock-names = "uartclk", "apb_pclk";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_default_mux>;
                 };
 
                 uart1: uart@101fb000 {
@@ -218,6 +772,10 @@
                         reg = <0x101fb000 0x1000>;
                         interrupt-parent = <&vica>;
                         interrupts = <17>;
+                        clocks = <&uart1clk>, <&pclkuart1>;
+                        clock-names = "uartclk", "apb_pclk";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart1_default_mux>;
                 };
 
                 uart2: uart@101f2000 {
@@ -225,17 +783,23 @@
                         reg = <0x101f2000 0x1000>;
                         interrupt-parent = <&vica>;
                         interrupts = <28>;
+                        clocks = <&uart2clk>, <&pclkuart2>;
+                        clock-names = "uartclk", "apb_pclk";
                         status = "disabled";
                 };
 
                 rng: rng@101b0000 {
                         compatible = "arm,primecell";
                         reg = <0x101b0000 0x1000>;
+                        clocks = <&rngcclk>, <&hclkrng>;
+                        clock-names = "rng", "apb_pclk";
                 };
 
                 rtc: rtc@101e8000 {
                         compatible = "arm,pl031", "arm,primecell";
                         reg = <0x101e8000 0x1000>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                         interrupt-parent = <&vica>;
                         interrupts = <10>;
                 };
@@ -243,6 +807,8 @@
                 mmcsd: sdi@101f6000 {
                         compatible = "arm,pl18x", "arm,primecell";
                         reg = <0x101f6000 0x1000>;
+                        clocks = <&sdiclk>, <&pclksdi>;
+                        clock-names = "mclk", "apb_pclk";
                         interrupt-parent = <&vica>;
                         interrupts = <22>;
                         max-frequency = <48000000>;
@@ -251,6 +817,8 @@
                         mmc-cap-sd-highspeed;
                         cd-gpios = <&gpio3 15 0x1>;
                         cd-inverted;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/stuib.dtsi b/arch/arm/boot/dts/stuib.dtsi
index 615392a75676..524e33240ad4 100644
--- a/arch/arm/boot/dts/stuib.dtsi
+++ b/arch/arm/boot/dts/stuib.dtsi
@@ -9,13 +9,15 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
+#include <dt-bindings/interrupt-controller/irq.h>
+
 / {
-        soc-u9500 {
+        soc {
                 i2c@80004000 {
                         stmpe1601: stmpe1601@40 {
                                 compatible = "st,stmpe1601";
                                 reg = <0x40>;
-                                interrupts = <26 0x2>;
+                                interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
                                 interrupt-parent = <&gpio6>;
                                 interrupt-controller;
 
@@ -52,26 +54,26 @@
                 };
 
                 i2c@80110000 {
-                        bu21013_tp@0x5c {
-                                compatible = "rhom,bu21013_tp";
+                        bu21013_tp@5c {
+                                compatible = "rohm,bu21013_tp";
                                 reg = <0x5c>;
                                 touch-gpio = <&gpio2 20 0x4>;
                                 avdd-supply = <&ab8500_ldo_aux1_reg>;
 
-                                rhom,touch-max-x = <384>;
-                                rhom,touch-max-y = <704>;
-                                rhom,flip-y;
+                                rohm,touch-max-x = <384>;
+                                rohm,touch-max-y = <704>;
+                                rohm,flip-y;
                         };
 
-                        bu21013_tp@0x5d {
-                                compatible = "rhom,bu21013_tp";
+                        bu21013_tp@5d {
+                                compatible = "rohm,bu21013_tp";
                                 reg = <0x5d>;
                                 touch-gpio = <&gpio2 20 0x4>;
                                 avdd-supply = <&ab8500_ldo_aux1_reg>;
 
-                                rhom,touch-max-x = <384>;
-                                rhom,touch-max-y = <704>;
-                                rhom,flip-y;
+                                rohm,touch-max-x = <384>;
+                                rohm,touch-max-y = <704>;
+                                rohm,flip-y;
                         };
                 };
         };
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index b70fe0db6bb7..0e22a285dfe0 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -41,6 +41,18 @@
                         pinctrl-0 = <&uart0_pins_a>;
                         status = "okay";
                 };
+
+                i2c0: i2c@01c2ac00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins_a>;
+                        status = "okay";
+                };
+
+                i2c1: i2c@01c2b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c1_pins_a>;
+                        status = "okay";
+                };
         };
 
         leds {
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index e7ef619a70a2..82e03d22f913 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -16,8 +16,12 @@
         interrupt-parent = <&intc>;
 
         cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
                 cpu@0 {
+                        device_type = "cpu";
                         compatible = "arm,cortex-a8";
+                        reg = <0x0>;
                 };
         };
 
@@ -173,8 +177,10 @@
                 pio: pinctrl@01c20800 {
                         compatible = "allwinner,sun4i-a10-pinctrl";
                         reg = <0x01c20800 0x400>;
+                        interrupts = <28>;
                         clocks = <&apb0_gates 5>;
                         gpio-controller;
+                        interrupt-controller;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         #gpio-cells = <3>;
@@ -199,6 +205,27 @@
                                 allwinner,drive = <0>;
                                 allwinner,pull = <0>;
                         };
+
+                        i2c0_pins_a: i2c0@0 {
+                                allwinner,pins = "PB0", "PB1";
+                                allwinner,function = "i2c0";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        i2c1_pins_a: i2c1@0 {
+                                allwinner,pins = "PB18", "PB19";
+                                allwinner,function = "i2c1";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        i2c2_pins_a: i2c2@0 {
+                                allwinner,pins = "PB20", "PB21";
+                                allwinner,function = "i2c2";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
                 };
 
                 timer@01c20c00 {
@@ -292,5 +319,32 @@
                         clocks = <&apb1_gates 23>;
                         status = "disabled";
                 };
+
+                i2c0: i2c@01c2ac00 {
+                        compatible = "allwinner,sun4i-i2c";
+                        reg = <0x01c2ac00 0x400>;
+                        interrupts = <7>;
+                        clocks = <&apb1_gates 0>;
+                        clock-frequency = <100000>;
+                        status = "disabled";
+                };
+
+                i2c1: i2c@01c2b000 {
+                        compatible = "allwinner,sun4i-i2c";
+                        reg = <0x01c2b000 0x400>;
+                        interrupts = <8>;
+                        clocks = <&apb1_gates 1>;
+                        clock-frequency = <100000>;
+                        status = "disabled";
+                };
+
+                i2c2: i2c@01c2b400 {
+                        compatible = "allwinner,sun4i-i2c";
+                        reg = <0x01c2b400 0x400>;
+                        interrupts = <9>;
+                        clocks = <&apb1_gates 2>;
+                        clock-frequency = <100000>;
+                        status = "disabled";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
new file mode 100644
index 000000000000..64dc0c42c43a
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "sun5i-a10s.dtsi"
+
+/ {
+        model = "Olimex A10s-Olinuxino Micro";
+        compatible = "olimex,a10s-olinuxino-micro", "allwinner,sun5i-a10s";
+
+        soc@01c20000 {
+                emac: ethernet@01c0b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&emac_pins_a>;
+                        phy = <&phy1>;
+                        status = "okay";
+                };
+
+                mdio@01c0b080 {
+                        status = "okay";
+
+                        phy1: ethernet-phy@1 {
+                                reg = <1>;
+                        };
+                };
+
+                pinctrl@01c20800 {
+                        led_pins_olinuxino: led_pins@0 {
+                                allwinner,pins = "PE3";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <1>;
+                                allwinner,pull = <0>;
+                        };
+                };
+
+                uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
+                        status = "okay";
+                };
+
+                uart2: serial@01c28800 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart2_pins_a>;
+                        status = "okay";
+                };
+
+                uart3: serial@01c28c00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart3_pins_a>;
+                        status = "okay";
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_olinuxino>;
+
+                green {
+                        label = "a10s-olinuxino-micro:green:usr";
+                        gpios = <&pio 4 3 0>;
+                        default-state = "on";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
new file mode 100644
index 000000000000..2307ce827ae0
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -0,0 +1,286 @@
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        interrupt-parent = <&intc>;
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,cortex-a8";
+                };
+        };
+
+        memory {
+                reg = <0x40000000 0x20000000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                /*
+                 * This is a dummy clock, to be used as placeholder on
+                 * other mux clocks when a specific parent clock is not
+                 * yet implemented. It should be dropped when the driver
+                 * is complete.
+                 */
+                dummy: dummy {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <0>;
+                };
+
+                osc24M: osc24M@01c20050 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-osc-clk";
+                        reg = <0x01c20050 0x4>;
+                        clock-frequency = <24000000>;
+                };
+
+                osc32k: osc32k {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+
+                pll1: pll1@01c20000 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-pll1-clk";
+                        reg = <0x01c20000 0x4>;
+                        clocks = <&osc24M>;
+                };
+
+                /* dummy is 200M */
+                cpu: cpu@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-cpu-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
+                };
+
+                axi: axi@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-axi-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&cpu>;
+                };
+
+                axi_gates: axi_gates@01c2005c {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-axi-gates-clk";
+                        reg = <0x01c2005c 0x4>;
+                        clocks = <&axi>;
+                        clock-output-names = "axi_dram";
+                };
+
+                ahb: ahb@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-ahb-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&axi>;
+                };
+
+                ahb_gates: ahb_gates@01c20060 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-ahb-gates-clk";
+                        reg = <0x01c20060 0x8>;
+                        clocks = <&ahb>;
+                        clock-output-names = "ahb_usb0", "ahb_ehci0",
+                                "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
+                                "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
+                                "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
+                                "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
+                                "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
+                                "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
+                                "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
+                                "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
+                                "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
+                                "ahb_de_fe1", "ahb_mp", "ahb_mali400";
+                };
+
+                apb0: apb0@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb0-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&ahb>;
+                };
+
+                apb0_gates: apb0_gates@01c20068 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-apb0-gates-clk";
+                        reg = <0x01c20068 0x4>;
+                        clocks = <&apb0>;
+                        clock-output-names = "apb0_codec", "apb0_spdif",
+                                "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
+                                "apb0_ir1", "apb0_keypad";
+                };
+
+                /* dummy is pll62 */
+                apb1_mux: apb1_mux@01c20058 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb1-mux-clk";
+                        reg = <0x01c20058 0x4>;
+                        clocks = <&osc24M>, <&dummy>, <&osc32k>;
+                };
+
+                apb1: apb1@01c20058 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb1-clk";
+                        reg = <0x01c20058 0x4>;
+                        clocks = <&apb1_mux>;
+                };
+
+                apb1_gates: apb1_gates@01c2006c {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-apb1-gates-clk";
+                        reg = <0x01c2006c 0x4>;
+                        clocks = <&apb1>;
+                        clock-output-names = "apb1_i2c0", "apb1_i2c1",
+                                "apb1_i2c2", "apb1_can", "apb1_scr",
+                                "apb1_ps20", "apb1_ps21", "apb1_uart0",
+                                "apb1_uart1", "apb1_uart2", "apb1_uart3",
+                                "apb1_uart4", "apb1_uart5", "apb1_uart6",
+                                "apb1_uart7";
+                };
+        };
+
+        soc@01c20000 {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0x01c20000 0x300000>;
+                ranges;
+
+                emac: ethernet@01c0b000 {
+                        compatible = "allwinner,sun4i-emac";
+                        reg = <0x01c0b000 0x1000>;
+                        interrupts = <55>;
+                        clocks = <&ahb_gates 17>;
+                        status = "disabled";
+                };
+
+                mdio@01c0b080 {
+                        compatible = "allwinner,sun4i-mdio";
+                        reg = <0x01c0b080 0x14>;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                intc: interrupt-controller@01c20400 {
+                        compatible = "allwinner,sun4i-ic";
+                        reg = <0x01c20400 0x400>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                pio: pinctrl@01c20800 {
+                        compatible = "allwinner,sun5i-a10s-pinctrl";
+                        reg = <0x01c20800 0x400>;
+                        interrupts = <28>;
+                        clocks = <&apb0_gates 5>;
+                        gpio-controller;
+                        interrupt-controller;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        #gpio-cells = <3>;
+
+                        uart0_pins_a: uart0@0 {
+                                allwinner,pins = "PB19", "PB20";
+                                allwinner,function = "uart0";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        uart2_pins_a: uart2@0 {
+                                allwinner,pins = "PC18", "PC19";
+                                allwinner,function = "uart2";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        uart3_pins_a: uart3@0 {
+                                allwinner,pins = "PG9", "PG10";
+                                allwinner,function = "uart3";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        emac_pins_a: emac0@0 {
+                                allwinner,pins = "PA0", "PA1", "PA2",
+                                                "PA3", "PA4", "PA5", "PA6",
+                                                "PA7", "PA8", "PA9", "PA10",
+                                                "PA11", "PA12", "PA13", "PA14",
+                                                "PA15", "PA16";
+                                allwinner,function = "emac";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
+
+                timer@01c20c00 {
+                        compatible = "allwinner,sun4i-timer";
+                        reg = <0x01c20c00 0x90>;
+                        interrupts = <22>;
+                        clocks = <&osc24M>;
+                };
+
+                wdt: watchdog@01c20c90 {
+                        compatible = "allwinner,sun4i-wdt";
+                        reg = <0x01c20c90 0x10>;
+                };
+
+                uart0: serial@01c28000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28000 0x400>;
+                        interrupts = <1>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 16>;
+                        status = "disabled";
+                };
+
+                uart1: serial@01c28400 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28400 0x400>;
+                        interrupts = <2>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 17>;
+                        status = "disabled";
+                };
+
+                uart2: serial@01c28800 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28800 0x400>;
+                        interrupts = <3>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 18>;
+                        status = "disabled";
+                };
+
+                uart3: serial@01c28c00 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28c00 0x400>;
+                        interrupts = <4>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 19>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 3ca55067f868..80497e376706 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -37,6 +37,24 @@
                         pinctrl-0 = <&uart1_pins_b>;
                         status = "okay";
                 };
+
+                i2c0: i2c@01c2ac00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins_a>;
+                        status = "okay";
+                };
+
+                i2c1: i2c@01c2b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c1_pins_a>;
+                        status = "okay";
+                };
+
+                i2c2: i2c@01c2b400 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c2_pins_a>;
+                        status = "okay";
+                };
         };
 
         leds {
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 31fa38f8cc98..7363211daf84 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -17,8 +17,12 @@
         interrupt-parent = <&intc>;
 
         cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
                 cpu@0 {
+                        device_type = "cpu";
                         compatible = "arm,cortex-a8";
+                        reg = <0x0>;
                 };
         };
 
@@ -95,20 +99,15 @@
 
                 ahb_gates: ahb_gates@01c20060 {
                         #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-ahb-gates-clk";
+                        compatible = "allwinner,sun5i-a13-ahb-gates-clk";
                         reg = <0x01c20060 0x8>;
                         clocks = <&ahb>;
-                        clock-output-names = "ahb_usb0", "ahb_ehci0",
-                                "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
-                                "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
-                                "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
-                                "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
-                                "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
-                                "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
-                                "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
-                                "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
-                                "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
-                                "ahb_de_fe1", "ahb_mp", "ahb_mali400";
+                        clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
+                                "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
+                                "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
+                                "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",
+                                "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",
+                                "ahb_de_fe", "ahb_iep", "ahb_mali400";
                 };
 
                 apb0: apb0@01c20054 {
@@ -120,15 +119,13 @@
 
                 apb0_gates: apb0_gates@01c20068 {
                         #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-apb0-gates-clk";
+                        compatible = "allwinner,sun5i-a13-apb0-gates-clk";
                         reg = <0x01c20068 0x4>;
                         clocks = <&apb0>;
-                        clock-output-names = "apb0_codec", "apb0_spdif",
-                                "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
-                                "apb0_ir1", "apb0_keypad";
+                        clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
                 };
 
-                /* dummy is pll62 */
+                /* dummy is pll6 */
                 apb1_mux: apb1_mux@01c20058 {
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-apb1-mux-clk";
@@ -145,15 +142,11 @@
 
                 apb1_gates: apb1_gates@01c2006c {
                         #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-apb1-gates-clk";
+                        compatible = "allwinner,sun5i-a13-apb1-gates-clk";
                         reg = <0x01c2006c 0x4>;
                         clocks = <&apb1>;
                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
-                                "apb1_i2c2", "apb1_can", "apb1_scr",
-                                "apb1_ps20", "apb1_ps21", "apb1_uart0",
-                                "apb1_uart1", "apb1_uart2", "apb1_uart3",
-                                "apb1_uart4", "apb1_uart5", "apb1_uart6",
-                                "apb1_uart7";
+                                "apb1_i2c2", "apb1_uart1", "apb1_uart3";
                 };
         };
 
@@ -174,8 +167,10 @@
                 pio: pinctrl@01c20800 {
                         compatible = "allwinner,sun5i-a13-pinctrl";
                         reg = <0x01c20800 0x400>;
+                        interrupts = <28>;
                         clocks = <&apb0_gates 5>;
                         gpio-controller;
+                        interrupt-controller;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         #gpio-cells = <3>;
@@ -193,6 +188,27 @@
                                 allwinner,drive = <0>;
                                 allwinner,pull = <0>;
                         };
+
+                        i2c0_pins_a: i2c0@0 {
+                                allwinner,pins = "PB0", "PB1";
+                                allwinner,function = "i2c0";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        i2c1_pins_a: i2c1@0 {
+                                allwinner,pins = "PB15", "PB16";
+                                allwinner,function = "i2c1";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        i2c2_pins_a: i2c2@0 {
+                                allwinner,pins = "PB17", "PB18";
+                                allwinner,function = "i2c2";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
                 };
 
                 timer@01c20c00 {
@@ -226,5 +242,32 @@
                         clocks = <&apb1_gates 19>;
                         status = "disabled";
                 };
+
+                i2c0: i2c@01c2ac00 {
+                        compatible = "allwinner,sun4i-i2c";
+                        reg = <0x01c2ac00 0x400>;
+                        interrupts = <7>;
+                        clocks = <&apb1_gates 0>;
+                        clock-frequency = <100000>;
+                        status = "disabled";
+                };
+
+                i2c1: i2c@01c2b000 {
+                        compatible = "allwinner,sun4i-i2c";
+                        reg = <0x01c2b000 0x400>;
+                        interrupts = <8>;
+                        clocks = <&apb1_gates 1>;
+                        clock-frequency = <100000>;
+                        status = "disabled";
+                };
+
+                i2c2: i2c@01c2b400 {
+                        compatible = "allwinner,sun4i-i2c";
+                        reg = <0x01c2b400 0x400>;
+                        interrupts = <9>;
+                        clocks = <&apb1_gates 2>;
+                        clock-frequency = <100000>;
+                        status = "disabled";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index 72c1f27af7f3..cb640eb6c932 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra114.dtsi"
+#include "tegra114.dtsi"
 
 / {
         model = "NVIDIA Tegra114 Dalmore evaluation board";
@@ -727,6 +727,16 @@
                         battery-name = "battery";
                         sbs,i2c-retry-count = <2>;
                         sbs,poll-retry-count = <100>;
+                        power-supplies = <&charger>;
+                };
+
+                rt5640: rt5640 {
+                        compatible = "realtek,rt5640";
+                        reg = <0x1c>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>;
+                        realtek,ldo1-en-gpios =
+                                <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -748,7 +758,7 @@
                         compatible = "ti,tps65090";
                         reg = <0x48>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <72 0x04>; /* gpio PJ0 */
+                        interrupts = <TEGRA_GPIO(J, 0) IRQ_TYPE_LEVEL_HIGH>;
 
                         vsys1-supply = <&vdd_ac_bat_reg>;
                         vsys2-supply = <&vdd_ac_bat_reg>;
@@ -763,6 +773,11 @@
                         vsys-l1-supply = <&vdd_ac_bat_reg>;
                         vsys-l2-supply = <&vdd_ac_bat_reg>;
 
+                        charger: charger {
+                                compatible = "ti,tps65090-charger";
+                                ti,enable-low-current-chrg;
+                        };
+
                         regulators {
                                 tps65090_dcdc1_reg: dcdc1 {
                                         regulator-name = "vdd-sys-5v0";
@@ -823,12 +838,28 @@
                 };
         };
 
+        spi@7000da00 {
+                status = "okay";
+                spi-max-frequency = <25000000>;
+                spi-flash@0 {
+                        compatible = "winbond,w25q32dw";
+                        reg = <0>;
+                        spi-max-frequency = <20000000>;
+                };
+        };
+
         pmc {
                 nvidia,invert-interrupt;
         };
 
+        ahub {
+                i2s@70080400 {
+                        status = "okay";
+                };
+        };
+
         sdhci@78000400 {
-                cd-gpios = <&gpio 170 1>; /* gpio PV2 */
+                cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
                 bus-width = <4>;
                 status = "okay";
         };
@@ -873,7 +904,7 @@
                         regulator-min-microvolt = <1800000>;
                         regulator-max-microvolt = <1800000>;
                         enable-active-high;
-                        gpio = <&gpio 61 0>; /* GPIO PH5 */
+                        gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
                 };
 
                 lcd_bl_en_reg: regulator@2 {
@@ -883,7 +914,7 @@
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
                         enable-active-high;
-                        gpio = <&gpio 58 0>; /* GPIO PH2 */
+                        gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
                 };
 
                 usb1_vbus_reg: regulator@3 {
@@ -893,7 +924,7 @@
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
                         enable-active-high;
-                        gpio = <&gpio 108 0>; /* GPIO PN4 */
+                        gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
                         gpio-open-drain;
                         vin-supply = <&tps65090_dcdc1_reg>;
                 };
@@ -905,7 +936,7 @@
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
                         enable-active-high;
-                        gpio = <&gpio 86 0>; /* GPIO PK6 */
+                        gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
                         gpio-open-drain;
                         vin-supply = <&tps65090_dcdc1_reg>;
                 };
@@ -917,8 +948,32 @@
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
                         enable-active-high;
-                        gpio = <&gpio 81 0>; /* GPIO PK1 */
+                        gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
                         vin-supply = <&tps65090_dcdc1_reg>;
                 };
         };
+
+        sound {
+                compatible = "nvidia,tegra-audio-rt5640-dalmore",
+                             "nvidia,tegra-audio-rt5640";
+                nvidia,model = "NVIDIA Tegra Dalmore";
+
+                nvidia,audio-routing =
+                        "Headphones", "HPOR",
+                        "Headphones", "HPOL",
+                        "Speakers", "SPORP",
+                        "Speakers", "SPORN",
+                        "Speakers", "SPOLP",
+                        "Speakers", "SPOLN";
+
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&rt5640>;
+
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
+
+                clocks = <&tegra_car TEGRA114_CLK_PLL_A>,
+                         <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA114_CLK_EXTERN1>;
+                clock-names = "pll_a", "pll_a_out0", "mclk";
+        };
 };
diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts
index 6bbc8efae9c0..d5f8d3e0bde2 100644
--- a/arch/arm/boot/dts/tegra114-pluto.dts
+++ b/arch/arm/boot/dts/tegra114-pluto.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra114.dtsi"
+#include "tegra114.dtsi"
 
 / {
         model = "NVIDIA Tegra114 Pluto evaluation board";
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 629415ffd8dc..abf6c40d28c6 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -1,4 +1,8 @@
-/include/ "skeleton.dtsi"
+#include <dt-bindings/clock/tegra114-car.h>
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "skeleton.dtsi"
 
 / {
         compatible = "nvidia,tegra114";
@@ -19,19 +23,20 @@
                       <0x50042000 0x1000>,
                       <0x50044000 0x2000>,
                       <0x50046000 0x2000>;
-                interrupts = <1 9 0xf04>;
+                interrupts = <GIC_PPI 9
+                        (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
         };
 
         timer@60005000 {
                 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
                 reg = <0x60005000 0x400>;
-                interrupts = <0 0 0x04
-                              0 1 0x04
-                              0 41 0x04
-                              0 42 0x04
-                              0 121 0x04
-                              0 122 0x04>;
-                clocks = <&tegra_car 5>;
+                interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA114_CLK_TIMER>;
         };
 
         tegra_car: clock {
@@ -43,39 +48,39 @@
         apbdma: dma {
                 compatible = "nvidia,tegra114-apbdma";
                 reg = <0x6000a000 0x1400>;
-                interrupts = <0 104 0x04
-                              0 105 0x04
-                              0 106 0x04
-                              0 107 0x04
-                              0 108 0x04
-                              0 109 0x04
-                              0 110 0x04
-                              0 111 0x04
-                              0 112 0x04
-                              0 113 0x04
-                              0 114 0x04
-                              0 115 0x04
-                              0 116 0x04
-                              0 117 0x04
-                              0 118 0x04
-                              0 119 0x04
-                              0 128 0x04
-                              0 129 0x04
-                              0 130 0x04
-                              0 131 0x04
-                              0 132 0x04
-                              0 133 0x04
-                              0 134 0x04
-                              0 135 0x04
-                              0 136 0x04
-                              0 137 0x04
-                              0 138 0x04
-                              0 139 0x04
-                              0 140 0x04
-                              0 141 0x04
-                              0 142 0x04
-                              0 143 0x04>;
-                clocks = <&tegra_car 34>;
+                interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
         };
 
         ahb: ahb {
@@ -86,14 +91,14 @@
         gpio: gpio {
                 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
                 reg = <0x6000d000 0x1000>;
-                interrupts = <0 32 0x04
-                              0 33 0x04
-                              0 34 0x04
-                              0 35 0x04
-                              0 55 0x04
-                              0 87 0x04
-                              0 89 0x04
-                              0 125 0x04>;
+                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 #interrupt-cells = <2>;
@@ -118,57 +123,57 @@
                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
                 reg = <0x70006000 0x40>;
                 reg-shift = <2>;
-                interrupts = <0 36 0x04>;
+                interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 8>;
                 status = "disabled";
-                clocks = <&tegra_car 6>;
+                clocks = <&tegra_car TEGRA114_CLK_UARTA>;
         };
 
         uartb: serial@70006040 {
                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
                 reg = <0x70006040 0x40>;
                 reg-shift = <2>;
-                interrupts = <0 37 0x04>;
+                interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 9>;
                 status = "disabled";
-                clocks = <&tegra_car 192>;
+                clocks = <&tegra_car TEGRA114_CLK_UARTB>;
         };
 
         uartc: serial@70006200 {
                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
                 reg = <0x70006200 0x100>;
                 reg-shift = <2>;
-                interrupts = <0 46 0x04>;
+                interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 10>;
                 status = "disabled";
-                clocks = <&tegra_car 55>;
+                clocks = <&tegra_car TEGRA114_CLK_UARTC>;
         };
 
         uartd: serial@70006300 {
                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
                 reg = <0x70006300 0x100>;
                 reg-shift = <2>;
-                interrupts = <0 90 0x04>;
+                interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 19>;
                 status = "disabled";
-                clocks = <&tegra_car 65>;
+                clocks = <&tegra_car TEGRA114_CLK_UARTD>;
         };
 
         pwm: pwm {
                 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
                 reg = <0x7000a000 0x100>;
                 #pwm-cells = <2>;
-                clocks = <&tegra_car 17>;
+                clocks = <&tegra_car TEGRA114_CLK_PWM>;
                 status = "disabled";
         };
 
         i2c@7000c000 {
                 compatible = "nvidia,tegra114-i2c";
                 reg = <0x7000c000 0x100>;
-                interrupts = <0 38 0x04>;
+                interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 12>;
+                clocks = <&tegra_car TEGRA114_CLK_I2C1>;
                 clock-names = "div-clk";
                 status = "disabled";
         };
@@ -176,10 +181,10 @@
         i2c@7000c400 {
                 compatible = "nvidia,tegra114-i2c";
                 reg = <0x7000c400 0x100>;
-                interrupts = <0 84 0x04>;
+                interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 54>;
+                clocks = <&tegra_car TEGRA114_CLK_I2C2>;
                 clock-names = "div-clk";
                 status = "disabled";
         };
@@ -187,10 +192,10 @@
         i2c@7000c500 {
                 compatible = "nvidia,tegra114-i2c";
                 reg = <0x7000c500 0x100>;
-                interrupts = <0 92 0x04>;
+                interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 67>;
+                clocks = <&tegra_car TEGRA114_CLK_I2C3>;
                 clock-names = "div-clk";
                 status = "disabled";
         };
@@ -198,10 +203,10 @@
         i2c@7000c700 {
                 compatible = "nvidia,tegra114-i2c";
                 reg = <0x7000c700 0x100>;
-                interrupts = <0 120 0x04>;
+                interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 103>;
+                clocks = <&tegra_car TEGRA114_CLK_I2C4>;
                 clock-names = "div-clk";
                 status = "disabled";
         };
@@ -209,10 +214,10 @@
         i2c@7000d000 {
                 compatible = "nvidia,tegra114-i2c";
                 reg = <0x7000d000 0x100>;
-                interrupts = <0 53 0x04>;
+                interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 47>;
+                clocks = <&tegra_car TEGRA114_CLK_I2C5>;
                 clock-names = "div-clk";
                 status = "disabled";
         };
@@ -220,11 +225,11 @@
         spi@7000d400 {
                 compatible = "nvidia,tegra114-spi";
                 reg = <0x7000d400 0x200>;
-                interrupts = <0 59 0x04>;
+                interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 15>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 41>;
+                clocks = <&tegra_car TEGRA114_CLK_SBC1>;
                 clock-names = "spi";
                 status = "disabled";
         };
@@ -232,11 +237,11 @@
         spi@7000d600 {
                 compatible = "nvidia,tegra114-spi";
                 reg = <0x7000d600 0x200>;
-                interrupts = <0 82 0x04>;
+                interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 16>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 44>;
+                clocks = <&tegra_car TEGRA114_CLK_SBC2>;
                 clock-names = "spi";
                 status = "disabled";
         };
@@ -244,11 +249,11 @@
         spi@7000d800 {
                 compatible = "nvidia,tegra114-spi";
                 reg = <0x7000d800 0x200>;
-                interrupts = <0 83 0x04>;
+                interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 17>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 46>;
+                clocks = <&tegra_car TEGRA114_CLK_SBC3>;
                 clock-names = "spi";
                 status = "disabled";
         };
@@ -256,11 +261,11 @@
         spi@7000da00 {
                 compatible = "nvidia,tegra114-spi";
                 reg = <0x7000da00 0x200>;
-                interrupts = <0 93 0x04>;
+                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 18>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 68>;
+                clocks = <&tegra_car TEGRA114_CLK_SBC4>;
                 clock-names = "spi";
                 status = "disabled";
         };
@@ -268,11 +273,11 @@
         spi@7000dc00 {
                 compatible = "nvidia,tegra114-spi";
                 reg = <0x7000dc00 0x200>;
-                interrupts = <0 94 0x04>;
+                interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 27>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 104>;
+                clocks = <&tegra_car TEGRA114_CLK_SBC5>;
                 clock-names = "spi";
                 status = "disabled";
         };
@@ -280,11 +285,11 @@
         spi@7000de00 {
                 compatible = "nvidia,tegra114-spi";
                 reg = <0x7000de00 0x200>;
-                interrupts = <0 79 0x04>;
+                interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 28>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 105>;
+                clocks = <&tegra_car TEGRA114_CLK_SBC6>;
                 clock-names = "spi";
                 status = "disabled";
         };
@@ -292,22 +297,22 @@
         rtc {
                 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
                 reg = <0x7000e000 0x100>;
-                interrupts = <0 2 0x04>;
-                clocks = <&tegra_car 4>;
+                interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA114_CLK_RTC>;
         };
 
         kbc {
                 compatible = "nvidia,tegra114-kbc";
                 reg = <0x7000e200 0x100>;
-                interrupts = <0 85 0x04>;
-                clocks = <&tegra_car 36>;
+                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA114_CLK_KBC>;
                 status = "disabled";
         };
 
         pmc {
                 compatible = "nvidia,tegra114-pmc";
                 reg = <0x7000e400 0x400>;
-                clocks = <&tegra_car 261>, <&clk32k_in>;
+                clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
                 clock-names = "pclk", "clk32k_in";
         };
 
@@ -322,35 +327,106 @@
                 nvidia,ahb = <&ahb>;
         };
 
+        ahub {
+                compatible = "nvidia,tegra114-ahub";
+                reg = <0x70080000 0x200>,
+                      <0x70080200 0x100>,
+                      <0x70081000 0x200>;
+                interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+                nvidia,dma-request-selector = <&apbdma 1>, <&apbdma 2>,
+                        <&apbdma 3>, <&apbdma 4>, <&apbdma 6>, <&apbdma 7>,
+                        <&apbdma 12>, <&apbdma 13>, <&apbdma 14>,
+                        <&apbdma 29>;
+                clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
+                         <&tegra_car TEGRA114_CLK_APBIF>,
+                         <&tegra_car TEGRA114_CLK_I2S0>,
+                         <&tegra_car TEGRA114_CLK_I2S1>,
+                         <&tegra_car TEGRA114_CLK_I2S2>,
+                         <&tegra_car TEGRA114_CLK_I2S3>,
+                         <&tegra_car TEGRA114_CLK_I2S4>,
+                         <&tegra_car TEGRA114_CLK_DAM0>,
+                         <&tegra_car TEGRA114_CLK_DAM1>,
+                         <&tegra_car TEGRA114_CLK_DAM2>,
+                         <&tegra_car TEGRA114_CLK_SPDIF_IN>,
+                         <&tegra_car TEGRA114_CLK_AMX>,
+                         <&tegra_car TEGRA114_CLK_ADX>;
+                clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
+                              "i2s3", "i2s4", "dam0", "dam1", "dam2",
+                              "spdif_in", "amx", "adx";
+                ranges;
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                tegra_i2s0: i2s@70080300 {
+                        compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
+                        reg = <0x70080300 0x100>;
+                        nvidia,ahub-cif-ids = <4 4>;
+                        clocks = <&tegra_car TEGRA114_CLK_I2S0>;
+                        status = "disabled";
+                };
+
+                tegra_i2s1: i2s@70080400 {
+                        compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
+                        reg = <0x70080400 0x100>;
+                        nvidia,ahub-cif-ids = <5 5>;
+                        clocks = <&tegra_car TEGRA114_CLK_I2S1>;
+                        status = "disabled";
+                };
+
+                tegra_i2s2: i2s@70080500 {
+                        compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
+                        reg = <0x70080500 0x100>;
+                        nvidia,ahub-cif-ids = <6 6>;
+                        clocks = <&tegra_car TEGRA114_CLK_I2S2>;
+                        status = "disabled";
+                };
+
+                tegra_i2s3: i2s@70080600 {
+                        compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
+                        reg = <0x70080600 0x100>;
+                        nvidia,ahub-cif-ids = <7 7>;
+                        clocks = <&tegra_car TEGRA114_CLK_I2S3>;
+                        status = "disabled";
+                };
+
+                tegra_i2s4: i2s@70080700 {
+                        compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
+                        reg = <0x70080700 0x100>;
+                        nvidia,ahub-cif-ids = <8 8>;
+                        clocks = <&tegra_car TEGRA114_CLK_I2S4>;
+                        status = "disabled";
+                };
+        };
+
         sdhci@78000000 {
                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
                 reg = <0x78000000 0x200>;
-                interrupts = <0 14 0x04>;
-                clocks = <&tegra_car 14>;
+                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
                 status = "disable";
         };
 
         sdhci@78000200 {
                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
                 reg = <0x78000200 0x200>;
-                interrupts = <0 15 0x04>;
-                clocks = <&tegra_car 9>;
+                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
                 status = "disable";
         };
 
         sdhci@78000400 {
                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
                 reg = <0x78000400 0x200>;
-                interrupts = <0 19 0x04>;
-                clocks = <&tegra_car 69>;
+                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
                 status = "disable";
         };
 
         sdhci@78000600 {
                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
                 reg = <0x78000600 0x200>;
-                interrupts = <0 31 0x04>;
-                clocks = <&tegra_car 15>;
+                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
                 status = "disable";
         };
 
@@ -385,9 +461,14 @@
 
         timer {
                 compatible = "arm,armv7-timer";
-                interrupts = <1 13 0xf08>,
-                             <1 14 0xf08>,
-                             <1 11 0xf08>,
-                             <1 10 0xf08>;
+                interrupts =
+                        <GIC_PPI 13
+                                (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                        <GIC_PPI 14
+                                (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                        <GIC_PPI 11
+                                (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                        <GIC_PPI 10
+                                (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
         };
 };
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index c12af78e479c..2fcb3f2ca160 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -1,4 +1,4 @@
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 
 / {
         model = "Toradex Colibri T20 512MB";
@@ -14,7 +14,8 @@
                         pll-supply = <&hdmi_pll_reg>;
 
                         nvidia,ddc-i2c-bus = <&i2c_ddc>;
-                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+                                GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -217,7 +218,7 @@
                 pmic: tps6586x@34 {
                         compatible = "ti,tps6586x";
                         reg = <0x34>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 
                         ti,system-power-controller;
 
@@ -443,21 +444,25 @@
 
         ac97: ac97 {
                 status = "okay";
-                nvidia,codec-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
-                nvidia,codec-sync-gpio = <&gpio 120 0>; /* gpio PP0 */
+                nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+                        GPIO_ACTIVE_HIGH>;
+                nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
+                        GPIO_ACTIVE_HIGH>;
         };
 
         usb@c5004000 {
                 status = "okay";
-                nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+                        GPIO_ACTIVE_LOW>;
         };
 
         usb-phy@c5004000 {
-                nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+                        GPIO_ACTIVE_LOW>;
         };
 
         sdhci@c8000600 {
-                cd-gpios = <&gpio 23 1>; /* gpio PC7 */
+                cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
         };
 
         clocks {
@@ -487,7 +492,9 @@
 
                 nvidia,ac97-controller = <&ac97>;
 
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                 clock-names = "pll_a", "pll_a_out0", "mclk";
         };
 
@@ -514,7 +521,7 @@
                         enable-active-high;
                         regulator-boot-on;
                         regulator-always-on;
-                        gpio = <&gpio 217 0>;
+                        gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index ec5293758753..d9f89cd879a7 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 
 / {
         model = "NVIDIA Tegra20 Harmony evaluation board";
@@ -18,7 +18,8 @@
                         pll-supply = <&hdmi_pll_reg>;
 
                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+                                GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -262,7 +263,7 @@
                         compatible = "wlf,wm8903";
                         reg = <0x1a>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <187 0x04>;
+                        interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
 
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -290,7 +291,7 @@
                 pmic: tps6586x@34 {
                         compatible = "ti,tps6586x";
                         reg = <0x34>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 
                         ti,system-power-controller;
 
@@ -434,12 +435,14 @@
 
         usb@c5004000 {
                 status = "okay";
-                nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+                        GPIO_ACTIVE_LOW>;
         };
 
         usb-phy@c5004000 {
                 status = "okay";
-                nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+                        GPIO_ACTIVE_LOW>;
         };
 
         usb@c5008000 {
@@ -452,17 +455,17 @@
 
         sdhci@c8000200 {
                 status = "okay";
-                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-                wp-gpios = <&gpio 57 0>; /* gpio PH1 */
-                power-gpios = <&gpio 155 0>; /* gpio PT3 */
+                cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+                wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+                power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
                 bus-width = <4>;
         };
 
         sdhci@c8000600 {
                 status = "okay";
-                cd-gpios = <&gpio 58 1>; /* gpio PH2 */
-                wp-gpios = <&gpio 59 0>; /* gpio PH3 */
-                power-gpios = <&gpio 70 0>; /* gpio PI6 */
+                cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
+                wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
+                power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
                 bus-width = <8>;
         };
 
@@ -484,7 +487,7 @@
 
                 power {
                         label = "Power";
-                        gpios = <&gpio 170 1>; /* gpio PV2, active low */
+                        gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
                         linux,code = <116>; /* KEY_POWER */
                         gpio-key,wakeup;
                 };
@@ -627,7 +630,7 @@
                         regulator-name = "vdd_1v5";
                         regulator-min-microvolt = <1500000>;
                         regulator-max-microvolt = <1500000>;
-                        gpio = <&pmic 0 0>;
+                        gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
                 };
 
                 regulator@2 {
@@ -636,7 +639,7 @@
                         regulator-name = "vdd_1v2";
                         regulator-min-microvolt = <1200000>;
                         regulator-max-microvolt = <1200000>;
-                        gpio = <&pmic 1 0>;
+                        gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
                         enable-active-high;
                 };
 
@@ -646,7 +649,7 @@
                         regulator-name = "vdd_1v05";
                         regulator-min-microvolt = <1050000>;
                         regulator-max-microvolt = <1050000>;
-                        gpio = <&pmic 2 0>;
+                        gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
                         enable-active-high;
                         /* Hack until board-harmony-pcie.c is removed */
                         status = "disabled";
@@ -658,7 +661,7 @@
                         regulator-name = "vdd_pnl";
                         regulator-min-microvolt = <2800000>;
                         regulator-max-microvolt = <2800000>;
-                        gpio = <&gpio 22 0>; /* gpio PC6 */
+                        gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
                         enable-active-high;
                 };
 
@@ -668,7 +671,7 @@
                         regulator-name = "vdd_bl";
                         regulator-min-microvolt = <2800000>;
                         regulator-max-microvolt = <2800000>;
-                        gpio = <&gpio 176 0>; /* gpio PW0 */
+                        gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
                         enable-active-high;
                 };
         };
@@ -691,12 +694,17 @@
                 nvidia,i2s-controller = <&tegra_i2s1>;
                 nvidia,audio-codec = <&wm8903>;
 
-                nvidia,spkr-en-gpios = <&wm8903 2 0>;
-                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
-                nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
-                nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
-
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+                        GPIO_ACTIVE_HIGH>;
+                nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
+                        GPIO_ACTIVE_HIGH>;
+                nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
+                        GPIO_ACTIVE_HIGH>;
+
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                 clock-names = "pll_a", "pll_a_out0", "mclk";
         };
 };
diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts
index 9f64f7086881..f2222bd74eab 100644
--- a/arch/arm/boot/dts/tegra20-iris-512.dts
+++ b/arch/arm/boot/dts/tegra20-iris-512.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20-colibri-512.dtsi"
+#include "tegra20-colibri-512.dtsi"
 
 / {
         model = "Toradex Colibri T20 512MB on Iris";
@@ -80,7 +80,7 @@
                         regulator-max-microvolt = <5000000>;
                         regulator-boot-on;
                         regulator-always-on;
-                        gpio = <&gpio 178 0>;
+                        gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
                 };
 
                 vcc_sd_reg: regulator@1 {
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
index ace23437da89..7580578903cf 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20-tamonten.dtsi"
+#include "tegra20-tamonten.dtsi"
 
 / {
         model = "Avionic Design Medcom-Wide board";
@@ -15,7 +15,7 @@
                         compatible = "wlf,wm8903";
                         reg = <0x1a>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <187 0x04>;
+                        interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
 
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -56,10 +56,12 @@
                 nvidia,i2s-controller = <&tegra_i2s1>;
                 nvidia,audio-codec = <&wm8903>;
 
-                nvidia,spkr-en-gpios = <&wm8903 2 0>;
-                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+                nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
 
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                 clock-names = "pll_a", "pll_a_out0", "mclk";
         };
 };
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 1c17ffaff1ad..cfd12763b1b2 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 
 / {
         model = "Toshiba AC100 / Dynabook AZ";
@@ -18,7 +18,8 @@
                         pll-supply = <&hdmi_pll_reg>;
 
                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+                                GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -270,13 +271,14 @@
         nvec {
                 compatible = "nvidia,nvec";
                 reg = <0x7000c500 0x100>;
-                interrupts = <0 92 0x04>;
+                interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
                 clock-frequency = <80000>;
-                request-gpios = <&gpio 170 0>; /* gpio PV2 */
+                request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
                 slave-addr = <138>;
-                clocks = <&tegra_car 67>, <&tegra_car 124>;
+                clocks = <&tegra_car TEGRA20_CLK_I2C3>,
+                         <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
         };
 
@@ -287,7 +289,7 @@
                 pmic: tps6586x@34 {
                         compatible = "ti,tps6586x";
                         reg = <0x34>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 
                         #gpio-cells = <2>;
                         gpio-controller;
@@ -433,12 +435,14 @@
 
         usb@c5004000 {
                 status = "okay";
-                nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+                        GPIO_ACTIVE_LOW>;
         };
 
         usb-phy@c5004000 {
                 status = "okay";
-                nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+                        GPIO_ACTIVE_LOW>;
         };
 
         usb@c5008000 {
@@ -451,9 +455,9 @@
 
         sdhci@c8000000 {
                 status = "okay";
-                cd-gpios = <&gpio 173 1>; /* gpio PV5 */
-                wp-gpios = <&gpio 57 0>;  /* gpio PH1 */
-                power-gpios = <&gpio 169 0>; /* gpio PV1 */
+                cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
+                wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+                power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
                 bus-width = <4>;
         };
 
@@ -481,7 +485,7 @@
 
                 power {
                         label = "Power";
-                        gpios = <&gpio 79 1>; /* gpio PJ7, active low */
+                        gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
                         linux,code = <116>; /* KEY_POWER */
                         gpio-key,wakeup;
                 };
@@ -492,7 +496,7 @@
 
                 wifi {
                         label = "wifi-led";
-                        gpios = <&gpio 24 0>; /* gpio PD0 */
+                        gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
                         linux,default-trigger = "rfkill0";
                 };
         };
@@ -529,9 +533,12 @@
 
                 nvidia,audio-codec = <&alc5632>;
                 nvidia,i2s-controller = <&tegra_i2s1>;
-                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+                        GPIO_ACTIVE_HIGH>;
 
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                 clock-names = "pll_a", "pll_a_out0", "mclk";
         };
 };
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
index 1a17cc30bb9d..d7a358a6a647 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20-tamonten.dtsi"
+#include "tegra20-tamonten.dtsi"
 
 / {
         model = "Avionic Design Plutux board";
@@ -17,7 +17,7 @@
                         compatible = "wlf,wm8903";
                         reg = <0x1a>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <187 0x04>;
+                        interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
 
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -50,10 +50,12 @@
                 nvidia,i2s-controller = <&tegra_i2s1>;
                 nvidia,audio-codec = <&wm8903>;
 
-                nvidia,spkr-en-gpios = <&wm8903 2 0>;
-                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+                nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
 
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                 clock-names = "pll_a", "pll_a_out0", "mclk";
         };
 };
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 009dafecf88b..ab177b406b78 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 
 / {
         model = "NVIDIA Seaboard";
@@ -18,7 +18,8 @@
                         pll-supply = <&hdmi_pll_reg>;
 
                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+                                GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -313,7 +314,7 @@
                         compatible = "wlf,wm8903";
                         reg = <0x1a>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <187 0x04>;
+                        interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
 
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -328,14 +329,14 @@
                         compatible = "isil,isl29018";
                         reg = <0x44>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <202 0x04>; /* GPIO PZ2 */
+                        interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
                 };
 
                 gyrometer@68 {
                         compatible = "invn,mpu3050";
                         reg = <0x68>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <204 0x04>; /* gpio PZ4 */
+                        interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>;
                 };
         };
 
@@ -388,7 +389,7 @@
                 pmic: tps6586x@34 {
                         compatible = "ti,tps6586x";
                         reg = <0x34>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 
                         ti,system-power-controller;
 
@@ -511,7 +512,7 @@
                         compatible = "ak,ak8975";
                         reg = <0xc>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <109 0x04>; /* gpio PN5 */
+                        interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
                 };
         };
 
@@ -565,7 +566,7 @@
 
         usb@c5000000 {
                 status = "okay";
-                nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
+                nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
                 dr_mode = "otg";
         };
 
@@ -577,12 +578,14 @@
 
         usb@c5004000 {
                 status = "okay";
-                nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+                        GPIO_ACTIVE_LOW>;
         };
 
         usb-phy@c5004000 {
                 status = "okay";
-                nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+                        GPIO_ACTIVE_LOW>;
         };
 
         usb@c5008000 {
@@ -595,16 +598,16 @@
 
         sdhci@c8000000 {
                 status = "okay";
-                power-gpios = <&gpio 86 0>; /* gpio PK6 */
+                power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
                 bus-width = <4>;
                 keep-power-in-suspend;
         };
 
         sdhci@c8000400 {
                 status = "okay";
-                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-                wp-gpios = <&gpio 57 0>; /* gpio PH1 */
-                power-gpios = <&gpio 70 0>; /* gpio PI6 */
+                cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+                wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+                power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
                 bus-width = <4>;
         };
 
@@ -632,14 +635,14 @@
 
                 power {
                         label = "Power";
-                        gpios = <&gpio 170 1>; /* gpio PV2, active low */
+                        gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
                         linux,code = <116>; /* KEY_POWER */
                         gpio-key,wakeup;
                 };
 
                 lid {
                         label = "Lid";
-                        gpios = <&gpio 23 0>; /* gpio PC7 */
+                        gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
                         linux,input-type = <5>; /* EV_SW */
                         linux,code = <0>; /* SW_LID */
                         debounce-interval = <1>;
@@ -806,7 +809,7 @@
                         regulator-name = "vdd_1v5";
                         regulator-min-microvolt = <1500000>;
                         regulator-max-microvolt = <1500000>;
-                        gpio = <&pmic 0 0>;
+                        gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
                 };
 
                 regulator@2 {
@@ -815,7 +818,7 @@
                         regulator-name = "vdd_1v2";
                         regulator-min-microvolt = <1200000>;
                         regulator-max-microvolt = <1200000>;
-                        gpio = <&pmic 1 0>;
+                        gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
                         enable-active-high;
                 };
 
@@ -847,10 +850,12 @@
                 nvidia,i2s-controller = <&tegra_i2s1>;
                 nvidia,audio-codec = <&wm8903>;
 
-                nvidia,spkr-en-gpios = <&wm8903 2 0>;
-                nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
+                nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
 
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                 clock-names = "pll_a", "pll_a_out0", "mclk";
         };
 };
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index fc2f7d6e70b2..c54faae7cfb3 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -1,4 +1,4 @@
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 
 / {
         model = "Avionic Design Tamonten SOM";
@@ -14,7 +14,8 @@
                         pll-supply = <&hdmi_pll_reg>;
 
                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+                                GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -321,7 +322,7 @@
                 pmic: tps6586x@34 {
                         compatible = "ti,tps6586x";
                         reg = <0x34>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 
                         ti,system-power-controller;
 
@@ -475,8 +476,8 @@
         };
 
         sdhci@c8000600 {
-                cd-gpios = <&gpio 58 1>; /* gpio PH2 */
-                wp-gpios = <&gpio 59 0>; /* gpio PH3 */
+                cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
+                wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
                 bus-width = <4>;
                 status = "okay";
         };
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
index 742f0b38d21d..c572c43751b1 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20-tamonten.dtsi"
+#include "tegra20-tamonten.dtsi"
 
 / {
         model = "Avionic Design Tamonten Evaluation Carrier";
@@ -17,7 +17,7 @@
                         compatible = "wlf,wm8903";
                         reg = <0x1a>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <187 0x04>;
+                        interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
 
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -50,10 +50,13 @@
                 nvidia,i2s-controller = <&tegra_i2s1>;
                 nvidia,audio-codec = <&wm8903>;
 
-                nvidia,spkr-en-gpios = <&wm8903 2 0>;
-                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+                nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+                        GPIO_ACTIVE_HIGH>;
 
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                 clock-names = "pll_a", "pll_a_out0", "mclk";
         };
 };
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 0e65c00ec732..170159910455 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 
 / {
         model = "Compulab TrimSlice board";
@@ -18,7 +18,8 @@
                         pll-supply = <&hdmi_pll_reg>;
 
                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+                                GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -311,7 +312,7 @@
 
         usb@c5000000 {
                 status = "okay";
-                nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */
+                nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
         };
 
         usb-phy@c5000000 {
@@ -321,12 +322,14 @@
 
         usb@c5004000 {
                 status = "okay";
-                nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+                        GPIO_ACTIVE_LOW>;
         };
 
         usb-phy@c5004000 {
                 status = "okay";
-                nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+                        GPIO_ACTIVE_LOW>;
         };
 
         usb@c5008000 {
@@ -344,8 +347,8 @@
 
         sdhci@c8000600 {
                 status = "okay";
-                cd-gpios = <&gpio 121 1>; /* gpio PP1 */
-                wp-gpios = <&gpio 122 0>; /* gpio PP2 */
+                cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
+                wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
                 bus-width = <4>;
         };
 
@@ -367,7 +370,7 @@
 
                 power {
                         label = "Power";
-                        gpios = <&gpio 190 1>; /* gpio PX6, active low */
+                        gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
                         linux,code = <116>; /* KEY_POWER */
                         gpio-key,wakeup;
                 };
@@ -375,7 +378,7 @@
 
         poweroff {
                 compatible = "gpio-poweroff";
-                gpios = <&gpio 191 1>; /* gpio PX7, active low */
+                gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
         };
 
         regulators {
@@ -416,7 +419,9 @@
                 nvidia,i2s-controller = <&tegra_i2s1>;
                 nvidia,audio-codec = <&codec>;
 
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                 clock-names = "pll_a", "pll_a_out0", "mclk";
         };
 };
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index e00f89e645f9..7f8c28d1121f 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 
 / {
         model = "NVIDIA Tegra20 Ventana evaluation board";
@@ -18,7 +18,8 @@
                         pll-supply = <&hdmi_pll_reg>;
 
                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+                                GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -310,7 +311,7 @@
                         compatible = "wlf,wm8903";
                         reg = <0x1a>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <187 0x04>;
+                        interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
 
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -325,7 +326,7 @@
                         compatible = "isil,isl29018";
                         reg = <0x44>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <202 0x04>; /*gpio PZ2 */
+                        interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
                 };
         };
 
@@ -371,7 +372,7 @@
                 pmic: tps6586x@34 {
                         compatible = "ti,tps6586x";
                         reg = <0x34>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 
                         ti,system-power-controller;
 
@@ -511,12 +512,14 @@
 
         usb@c5004000 {
                 status = "okay";
-                nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+                        GPIO_ACTIVE_LOW>;
         };
 
         usb-phy@c5004000 {
                 status = "okay";
-                nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+                        GPIO_ACTIVE_LOW>;
         };
 
         usb@c5008000 {
@@ -529,16 +532,16 @@
 
         sdhci@c8000000 {
                 status = "okay";
-                power-gpios = <&gpio 86 0>; /* gpio PK6 */
+                power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
                 bus-width = <4>;
                 keep-power-in-suspend;
         };
 
         sdhci@c8000400 {
                 status = "okay";
-                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-                wp-gpios = <&gpio 57 0>; /* gpio PH1 */
-                power-gpios = <&gpio 70 0>; /* gpio PI6 */
+                cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+                wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+                power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
                 bus-width = <4>;
         };
 
@@ -566,7 +569,7 @@
 
                 power {
                         label = "Power";
-                        gpios = <&gpio 170 1>; /* gpio PV2, active low */
+                        gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
                         linux,code = <116>; /* KEY_POWER */
                         gpio-key,wakeup;
                 };
@@ -592,7 +595,7 @@
                         regulator-name = "vdd_1v5";
                         regulator-min-microvolt = <1500000>;
                         regulator-max-microvolt = <1500000>;
-                        gpio = <&pmic 0 0>;
+                        gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
                 };
 
                 regulator@2 {
@@ -601,7 +604,7 @@
                         regulator-name = "vdd_1v2";
                         regulator-min-microvolt = <1200000>;
                         regulator-max-microvolt = <1200000>;
-                        gpio = <&pmic 1 0>;
+                        gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
                         enable-active-high;
                 };
 
@@ -611,7 +614,7 @@
                         regulator-name = "vdd_pnl";
                         regulator-min-microvolt = <2800000>;
                         regulator-max-microvolt = <2800000>;
-                        gpio = <&gpio 22 0>; /* gpio PC6 */
+                        gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
                         enable-active-high;
                 };
 
@@ -621,7 +624,7 @@
                         regulator-name = "vdd_bl";
                         regulator-min-microvolt = <2800000>;
                         regulator-max-microvolt = <2800000>;
-                        gpio = <&gpio 176 0>; /* gpio PW0 */
+                        gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
                         enable-active-high;
                 };
         };
@@ -644,12 +647,16 @@
                 nvidia,i2s-controller = <&tegra_i2s1>;
                 nvidia,audio-codec = <&wm8903>;
 
-                nvidia,spkr-en-gpios = <&wm8903 2 0>;
-                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
-                nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
-                nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
+                nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
+                nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
+                        GPIO_ACTIVE_HIGH>;
+                nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
+                        GPIO_ACTIVE_HIGH>;
 
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                 clock-names = "pll_a", "pll_a_out0", "mclk";
         };
 };
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index 3c24c9b92b44..ea078ab8edeb 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 
 / {
         model = "NVIDIA Tegra20 Whistler evaluation board";
@@ -18,7 +18,8 @@
                         pll-supply = <&hdmi_pll_reg>;
 
                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+                                GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -281,7 +282,7 @@
                 max8907@3c {
                         compatible = "maxim,max8907";
                         reg = <0x3c>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 
                         maxim,system-power-controller;
 
@@ -508,7 +509,7 @@
 
         usb@c5000000 {
                 status = "okay";
-                nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
+                nvidia,vbus-gpio = <&tca6416 0 GPIO_ACTIVE_HIGH>;
         };
 
         usb-phy@c5000000 {
@@ -518,7 +519,7 @@
 
         usb@c5008000 {
                 status = "okay";
-                nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
+                nvidia,vbus-gpio = <&tca6416 1 GPIO_ACTIVE_HIGH>;
         };
 
         usb-phy@c5008000 {
@@ -528,8 +529,8 @@
 
         sdhci@c8000400 {
                 status = "okay";
-                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-                wp-gpios = <&gpio 173 0>; /* gpio PV5 */
+                cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+                wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
                 bus-width = <8>;
         };
 
@@ -612,7 +613,9 @@
                 nvidia,i2s-controller = <&tegra_i2s1>;
                 nvidia,audio-codec = <&codec>;
 
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                 clock-names = "pll_a", "pll_a_out0", "mclk";
         };
 };
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 96d6d8a3aa72..9653fd8288d2 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -1,4 +1,8 @@
-/include/ "skeleton.dtsi"
+#include <dt-bindings/clock/tegra20-car.h>
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "skeleton.dtsi"
 
 / {
         compatible = "nvidia,tegra20";
@@ -15,9 +19,9 @@
         host1x {
                 compatible = "nvidia,tegra20-host1x", "simple-bus";
                 reg = <0x50000000 0x00024000>;
-                interrupts = <0 65 0x04   /* mpcore syncpt */
-                              0 67 0x04>; /* mpcore general */
-                clocks = <&tegra_car 28>;
+                interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
+                             <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
+                clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
 
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -27,49 +31,50 @@
                 mpe {
                         compatible = "nvidia,tegra20-mpe";
                         reg = <0x54040000 0x00040000>;
-                        interrupts = <0 68 0x04>;
-                        clocks = <&tegra_car 60>;
+                        interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA20_CLK_MPE>;
                 };
 
                 vi {
                         compatible = "nvidia,tegra20-vi";
                         reg = <0x54080000 0x00040000>;
-                        interrupts = <0 69 0x04>;
-                        clocks = <&tegra_car 100>;
+                        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA20_CLK_VI>;
                 };
 
                 epp {
                         compatible = "nvidia,tegra20-epp";
                         reg = <0x540c0000 0x00040000>;
-                        interrupts = <0 70 0x04>;
-                        clocks = <&tegra_car 19>;
+                        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA20_CLK_EPP>;
                 };
 
                 isp {
                         compatible = "nvidia,tegra20-isp";
                         reg = <0x54100000 0x00040000>;
-                        interrupts = <0 71 0x04>;
-                        clocks = <&tegra_car 23>;
+                        interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA20_CLK_ISP>;
                 };
 
                 gr2d {
                         compatible = "nvidia,tegra20-gr2d";
                         reg = <0x54140000 0x00040000>;
-                        interrupts = <0 72 0x04>;
-                        clocks = <&tegra_car 21>;
+                        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA20_CLK_GR2D>;
                 };
 
                 gr3d {
                         compatible = "nvidia,tegra20-gr3d";
                         reg = <0x54180000 0x00040000>;
-                        clocks = <&tegra_car 24>;
+                        clocks = <&tegra_car TEGRA20_CLK_GR3D>;
                 };
 
                 dc@54200000 {
                         compatible = "nvidia,tegra20-dc";
                         reg = <0x54200000 0x00040000>;
-                        interrupts = <0 73 0x04>;
-                        clocks = <&tegra_car 27>, <&tegra_car 121>;
+                        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA20_CLK_DISP1>,
+                                 <&tegra_car TEGRA20_CLK_PLL_P>;
                         clock-names = "disp1", "parent";
 
                         rgb {
@@ -80,8 +85,9 @@
                 dc@54240000 {
                         compatible = "nvidia,tegra20-dc";
                         reg = <0x54240000 0x00040000>;
-                        interrupts = <0 74 0x04>;
-                        clocks = <&tegra_car 26>, <&tegra_car 121>;
+                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA20_CLK_DISP2>,
+                                 <&tegra_car TEGRA20_CLK_PLL_P>;
                         clock-names = "disp2", "parent";
 
                         rgb {
@@ -92,8 +98,9 @@
                 hdmi {
                         compatible = "nvidia,tegra20-hdmi";
                         reg = <0x54280000 0x00040000>;
-                        interrupts = <0 75 0x04>;
-                        clocks = <&tegra_car 51>, <&tegra_car 117>;
+                        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA20_CLK_HDMI>,
+                                 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
                         clock-names = "hdmi", "parent";
                         status = "disabled";
                 };
@@ -101,15 +108,15 @@
                 tvo {
                         compatible = "nvidia,tegra20-tvo";
                         reg = <0x542c0000 0x00040000>;
-                        interrupts = <0 76 0x04>;
-                        clocks = <&tegra_car 102>;
+                        interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA20_CLK_TVO>;
                         status = "disabled";
                 };
 
                 dsi {
                         compatible = "nvidia,tegra20-dsi";
                         reg = <0x54300000 0x00040000>;
-                        clocks = <&tegra_car 48>;
+                        clocks = <&tegra_car TEGRA20_CLK_DSI>;
                         status = "disabled";
                 };
         };
@@ -117,8 +124,9 @@
         timer@50004600 {
                 compatible = "arm,cortex-a9-twd-timer";
                 reg = <0x50040600 0x20>;
-                interrupts = <1 13 0x304>;
-                clocks = <&tegra_car 132>;
+                interrupts = <GIC_PPI 13
+                        (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+                clocks = <&tegra_car TEGRA20_CLK_TWD>;
         };
 
         intc: interrupt-controller {
@@ -141,11 +149,11 @@
         timer@60005000 {
                 compatible = "nvidia,tegra20-timer";
                 reg = <0x60005000 0x60>;
-                interrupts = <0 0 0x04
-                              0 1 0x04
-                              0 41 0x04
-                              0 42 0x04>;
-                clocks = <&tegra_car 5>;
+                interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA20_CLK_TIMER>;
         };
 
         tegra_car: clock {
@@ -157,23 +165,23 @@
         apbdma: dma {
                 compatible = "nvidia,tegra20-apbdma";
                 reg = <0x6000a000 0x1200>;
-                interrupts = <0 104 0x04
-                              0 105 0x04
-                              0 106 0x04
-                              0 107 0x04
-                              0 108 0x04
-                              0 109 0x04
-                              0 110 0x04
-                              0 111 0x04
-                              0 112 0x04
-                              0 113 0x04
-                              0 114 0x04
-                              0 115 0x04
-                              0 116 0x04
-                              0 117 0x04
-                              0 118 0x04
-                              0 119 0x04>;
-                clocks = <&tegra_car 34>;
+                interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
         };
 
         ahb {
@@ -184,13 +192,13 @@
         gpio: gpio {
                 compatible = "nvidia,tegra20-gpio";
                 reg = <0x6000d000 0x1000>;
-                interrupts = <0 32 0x04
-                              0 33 0x04
-                              0 34 0x04
-                              0 35 0x04
-                              0 55 0x04
-                              0 87 0x04
-                              0 89 0x04>;
+                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 #interrupt-cells = <2>;
@@ -213,27 +221,27 @@
         tegra_ac97: ac97 {
                 compatible = "nvidia,tegra20-ac97";
                 reg = <0x70002000 0x200>;
-                interrupts = <0 81 0x04>;
+                interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 12>;
-                clocks = <&tegra_car 3>;
+                clocks = <&tegra_car TEGRA20_CLK_AC97>;
                 status = "disabled";
         };
 
         tegra_i2s1: i2s@70002800 {
                 compatible = "nvidia,tegra20-i2s";
                 reg = <0x70002800 0x200>;
-                interrupts = <0 13 0x04>;
+                interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 2>;
-                clocks = <&tegra_car 11>;
+                clocks = <&tegra_car TEGRA20_CLK_I2S1>;
                 status = "disabled";
         };
 
         tegra_i2s2: i2s@70002a00 {
                 compatible = "nvidia,tegra20-i2s";
                 reg = <0x70002a00 0x200>;
-                interrupts = <0 3 0x04>;
+                interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 1>;
-                clocks = <&tegra_car 18>;
+                clocks = <&tegra_car TEGRA20_CLK_I2S2>;
                 status = "disabled";
         };
 
@@ -248,9 +256,9 @@
                 compatible = "nvidia,tegra20-uart";
                 reg = <0x70006000 0x40>;
                 reg-shift = <2>;
-                interrupts = <0 36 0x04>;
+                interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 8>;
-                clocks = <&tegra_car 6>;
+                clocks = <&tegra_car TEGRA20_CLK_UARTA>;
                 status = "disabled";
         };
 
@@ -258,9 +266,9 @@
                 compatible = "nvidia,tegra20-uart";
                 reg = <0x70006040 0x40>;
                 reg-shift = <2>;
-                interrupts = <0 37 0x04>;
+                interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 9>;
-                clocks = <&tegra_car 96>;
+                clocks = <&tegra_car TEGRA20_CLK_UARTB>;
                 status = "disabled";
         };
 
@@ -268,9 +276,9 @@
                 compatible = "nvidia,tegra20-uart";
                 reg = <0x70006200 0x100>;
                 reg-shift = <2>;
-                interrupts = <0 46 0x04>;
+                interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 10>;
-                clocks = <&tegra_car 55>;
+                clocks = <&tegra_car TEGRA20_CLK_UARTC>;
                 status = "disabled";
         };
 
@@ -278,9 +286,9 @@
                 compatible = "nvidia,tegra20-uart";
                 reg = <0x70006300 0x100>;
                 reg-shift = <2>;
-                interrupts = <0 90 0x04>;
+                interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 19>;
-                clocks = <&tegra_car 65>;
+                clocks = <&tegra_car TEGRA20_CLK_UARTD>;
                 status = "disabled";
         };
 
@@ -288,9 +296,9 @@
                 compatible = "nvidia,tegra20-uart";
                 reg = <0x70006400 0x100>;
                 reg-shift = <2>;
-                interrupts = <0 91 0x04>;
+                interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 20>;
-                clocks = <&tegra_car 66>;
+                clocks = <&tegra_car TEGRA20_CLK_UARTE>;
                 status = "disabled";
         };
 
@@ -298,24 +306,25 @@
                 compatible = "nvidia,tegra20-pwm";
                 reg = <0x7000a000 0x100>;
                 #pwm-cells = <2>;
-                clocks = <&tegra_car 17>;
+                clocks = <&tegra_car TEGRA20_CLK_PWM>;
                 status = "disabled";
         };
 
         rtc {
                 compatible = "nvidia,tegra20-rtc";
                 reg = <0x7000e000 0x100>;
-                interrupts = <0 2 0x04>;
-                clocks = <&tegra_car 4>;
+                interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA20_CLK_RTC>;
         };
 
         i2c@7000c000 {
                 compatible = "nvidia,tegra20-i2c";
                 reg = <0x7000c000 0x100>;
-                interrupts = <0 38 0x04>;
+                interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 12>, <&tegra_car 124>;
+                clocks = <&tegra_car TEGRA20_CLK_I2C1>,
+                         <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
                 status = "disabled";
         };
@@ -323,21 +332,22 @@
         spi@7000c380 {
                 compatible = "nvidia,tegra20-sflash";
                 reg = <0x7000c380 0x80>;
-                interrupts = <0 39 0x04>;
+                interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 11>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 43>;
+                clocks = <&tegra_car TEGRA20_CLK_SPI>;
                 status = "disabled";
         };
 
         i2c@7000c400 {
                 compatible = "nvidia,tegra20-i2c";
                 reg = <0x7000c400 0x100>;
-                interrupts = <0 84 0x04>;
+                interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 54>, <&tegra_car 124>;
+                clocks = <&tegra_car TEGRA20_CLK_I2C2>,
+                         <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
                 status = "disabled";
         };
@@ -345,10 +355,11 @@
         i2c@7000c500 {
                 compatible = "nvidia,tegra20-i2c";
                 reg = <0x7000c500 0x100>;
-                interrupts = <0 92 0x04>;
+                interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 67>, <&tegra_car 124>;
+                clocks = <&tegra_car TEGRA20_CLK_I2C3>,
+                         <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
                 status = "disabled";
         };
@@ -356,10 +367,11 @@
         i2c@7000d000 {
                 compatible = "nvidia,tegra20-i2c-dvc";
                 reg = <0x7000d000 0x200>;
-                interrupts = <0 53 0x04>;
+                interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 47>, <&tegra_car 124>;
+                clocks = <&tegra_car TEGRA20_CLK_DVC>,
+                         <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
                 status = "disabled";
         };
@@ -367,59 +379,59 @@
         spi@7000d400 {
                 compatible = "nvidia,tegra20-slink";
                 reg = <0x7000d400 0x200>;
-                interrupts = <0 59 0x04>;
+                interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 15>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 41>;
+                clocks = <&tegra_car TEGRA20_CLK_SBC1>;
                 status = "disabled";
         };
 
         spi@7000d600 {
                 compatible = "nvidia,tegra20-slink";
                 reg = <0x7000d600 0x200>;
-                interrupts = <0 82 0x04>;
+                interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 16>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 44>;
+                clocks = <&tegra_car TEGRA20_CLK_SBC2>;
                 status = "disabled";
         };
 
         spi@7000d800 {
                 compatible = "nvidia,tegra20-slink";
                 reg = <0x7000d800 0x200>;
-                interrupts = <0 83 0x04>;
+                interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 17>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 46>;
+                clocks = <&tegra_car TEGRA20_CLK_SBC3>;
                 status = "disabled";
         };
 
         spi@7000da00 {
                 compatible = "nvidia,tegra20-slink";
                 reg = <0x7000da00 0x200>;
-                interrupts = <0 93 0x04>;
+                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 18>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 68>;
+                clocks = <&tegra_car TEGRA20_CLK_SBC4>;
                 status = "disabled";
         };
 
         kbc {
                 compatible = "nvidia,tegra20-kbc";
                 reg = <0x7000e200 0x100>;
-                interrupts = <0 85 0x04>;
-                clocks = <&tegra_car 36>;
+                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA20_CLK_KBC>;
                 status = "disabled";
         };
 
         pmc {
                 compatible = "nvidia,tegra20-pmc";
                 reg = <0x7000e400 0x400>;
-                clocks = <&tegra_car 110>, <&clk32k_in>;
+                clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
                 clock-names = "pclk", "clk32k_in";
         };
 
@@ -427,7 +439,7 @@
                 compatible = "nvidia,tegra20-mc";
                 reg = <0x7000f000 0x024
                        0x7000f03c 0x3c4>;
-                interrupts = <0 77 0x04>;
+                interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         iommu {
@@ -446,10 +458,10 @@
         usb@c5000000 {
                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
                 reg = <0xc5000000 0x4000>;
-                interrupts = <0 20 0x04>;
+                interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
                 phy_type = "utmi";
                 nvidia,has-legacy-mode;
-                clocks = <&tegra_car 22>;
+                clocks = <&tegra_car TEGRA20_CLK_USBD>;
                 nvidia,needs-double-reset;
                 nvidia,phy = <&phy1>;
                 status = "disabled";
@@ -459,10 +471,10 @@
                 compatible = "nvidia,tegra20-usb-phy";
                 reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
                 phy_type = "utmi";
-                clocks = <&tegra_car 22>,
-                         <&tegra_car 127>,
-                         <&tegra_car 106>,
-                         <&tegra_car 22>;
+                clocks = <&tegra_car TEGRA20_CLK_USBD>,
+                         <&tegra_car TEGRA20_CLK_PLL_U>,
+                         <&tegra_car TEGRA20_CLK_CLK_M>,
+                         <&tegra_car TEGRA20_CLK_USBD>;
                 clock-names = "reg", "pll_u", "timer", "utmi-pads";
                 nvidia,has-legacy-mode;
                 hssync_start_delay = <9>;
@@ -478,9 +490,9 @@
         usb@c5004000 {
                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
                 reg = <0xc5004000 0x4000>;
-                interrupts = <0 21 0x04>;
+                interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
                 phy_type = "ulpi";
-                clocks = <&tegra_car 58>;
+                clocks = <&tegra_car TEGRA20_CLK_USB2>;
                 nvidia,phy = <&phy2>;
                 status = "disabled";
         };
@@ -489,9 +501,9 @@
                 compatible = "nvidia,tegra20-usb-phy";
                 reg = <0xc5004000 0x4000>;
                 phy_type = "ulpi";
-                clocks = <&tegra_car 58>,
-                         <&tegra_car 127>,
-                         <&tegra_car 93>;
+                clocks = <&tegra_car TEGRA20_CLK_USB2>,
+                         <&tegra_car TEGRA20_CLK_PLL_U>,
+                         <&tegra_car TEGRA20_CLK_CDEV2>;
                 clock-names = "reg", "pll_u", "ulpi-link";
                 status = "disabled";
         };
@@ -499,9 +511,9 @@
         usb@c5008000 {
                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
                 reg = <0xc5008000 0x4000>;
-                interrupts = <0 97 0x04>;
+                interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
                 phy_type = "utmi";
-                clocks = <&tegra_car 59>;
+                clocks = <&tegra_car TEGRA20_CLK_USB3>;
                 nvidia,phy = <&phy3>;
                 status = "disabled";
         };
@@ -510,10 +522,10 @@
                 compatible = "nvidia,tegra20-usb-phy";
                 reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
                 phy_type = "utmi";
-                clocks = <&tegra_car 59>,
-                         <&tegra_car 127>,
-                         <&tegra_car 106>,
-                         <&tegra_car 22>;
+                clocks = <&tegra_car TEGRA20_CLK_USB3>,
+                         <&tegra_car TEGRA20_CLK_PLL_U>,
+                         <&tegra_car TEGRA20_CLK_CLK_M>,
+                         <&tegra_car TEGRA20_CLK_USBD>;
                 clock-names = "reg", "pll_u", "timer", "utmi-pads";
                 hssync_start_delay = <9>;
                 idle_wait_delay = <17>;
@@ -528,32 +540,32 @@
         sdhci@c8000000 {
                 compatible = "nvidia,tegra20-sdhci";
                 reg = <0xc8000000 0x200>;
-                interrupts = <0 14 0x04>;
-                clocks = <&tegra_car 14>;
+                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
                 status = "disabled";
         };
 
         sdhci@c8000200 {
                 compatible = "nvidia,tegra20-sdhci";
                 reg = <0xc8000200 0x200>;
-                interrupts = <0 15 0x04>;
-                clocks = <&tegra_car 9>;
+                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
                 status = "disabled";
         };
 
         sdhci@c8000400 {
                 compatible = "nvidia,tegra20-sdhci";
                 reg = <0xc8000400 0x200>;
-                interrupts = <0 19 0x04>;
-                clocks = <&tegra_car 69>;
+                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
                 status = "disabled";
         };
 
         sdhci@c8000600 {
                 compatible = "nvidia,tegra20-sdhci";
                 reg = <0xc8000600 0x200>;
-                interrupts = <0 31 0x04>;
-                clocks = <&tegra_car 15>;
+                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
                 status = "disabled";
         };
 
@@ -576,7 +588,7 @@
 
         pmu {
                 compatible = "arm,cortex-a9-pmu";
-                interrupts = <0 56 0x04
-                              0 57 0x04>;
+                interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
         };
 };
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index b732f7c13a66..87c5f7b7c271 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -1,13 +1,13 @@
 /dts-v1/;
 
-/include/ "tegra30.dtsi"
+#include "tegra30.dtsi"
 
 / {
         model = "NVIDIA Tegra30 Beaver evaluation board";
         compatible = "nvidia,beaver", "nvidia,tegra30";
 
         memory {
-                reg = <0x80000000 0x80000000>;
+                reg = <0x80000000 0x7ff00000>;
         };
 
         pinmux {
@@ -116,6 +116,15 @@
                 status = "okay";
                 clock-frequency = <100000>;
 
+                rt5640: rt5640 {
+                        compatible = "realtek,rt5640";
+                        reg = <0x1c>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(X, 3) GPIO_ACTIVE_HIGH>;
+                        realtek,ldo1-en-gpios =
+                                <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>;
+                };
+
                 tps62361 {
                         compatible = "ti,tps62361";
                         reg = <0x60>;
@@ -133,7 +142,7 @@
                         compatible = "ti,tps65911";
                         reg = <0x2d>;
 
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
                         #interrupt-cells = <2>;
                         interrupt-controller;
 
@@ -264,9 +273,9 @@
 
         sdhci@78000000 {
                 status = "okay";
-                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-                wp-gpios = <&gpio 155 0>; /* gpio PT3 */
-                power-gpios = <&gpio 31 0>; /* gpio PD7 */
+                cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+                wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
+                power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
                 bus-width = <4>;
         };
 
@@ -312,7 +321,7 @@
                         regulator-boot-on;
                         regulator-always-on;
                         enable-active-high;
-                        gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
+                        gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
                 };
 
                 ddr_reg: regulator@2 {
@@ -324,7 +333,7 @@
                         regulator-always-on;
                         regulator-boot-on;
                         enable-active-high;
-                        gpio = <&pmic 7 0>; /* PMIC TPS65911 GPIO7 */
+                        gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
                         vin-supply = <&vdd_5v_in_reg>;
                 };
 
@@ -337,7 +346,7 @@
                         regulator-always-on;
                         regulator-boot-on;
                         enable-active-high;
-                        gpio = <&gpio 30 0>; /* gpio PD6 */
+                        gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
                         vin-supply = <&vdd_5v_in_reg>;
                 };
 
@@ -348,7 +357,7 @@
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
                         enable-active-high;
-                        gpio = <&gpio 68 0>; /* GPIO PI4 */
+                        gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>;
                         gpio-open-drain;
                         vin-supply = <&vdd_5v_in_reg>;
                 };
@@ -360,7 +369,7 @@
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
                         enable-active-high;
-                        gpio = <&gpio 63 0>; /* GPIO PH7 */
+                        gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
                         gpio-open-drain;
                         vin-supply = <&vdd_5v_in_reg>;
                 };
@@ -374,7 +383,7 @@
                         regulator-always-on;
                         regulator-boot-on;
                         enable-active-high;
-                        gpio = <&pmic 6 0>; /* PMIC TPS65911 GPIO6 */
+                        gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
                         vin-supply = <&vdd_5v_in_reg>;
                 };
 
@@ -387,8 +396,41 @@
                         regulator-always-on;
                         regulator-boot-on;
                         enable-active-high;
-                        gpio = <&gpio 95 0>; /* gpio PL7 */
+                        gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
                         vin-supply = <&sys_3v3_reg>;
                 };
         };
+
+        gpio-leds {
+                compatible = "gpio-leds";
+
+                gpled1 {
+                        label = "LED1"; /* CR5A1 (blue) */
+                        gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>;
+                };
+                gpled2 {
+                        label = "LED2"; /* CR4A2 (green) */
+                        gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>;
+                };
+        };
+
+        sound {
+                compatible = "nvidia,tegra-audio-rt5640-beaver",
+                             "nvidia,tegra-audio-rt5640";
+                nvidia,model = "NVIDIA Tegra Beaver";
+
+                nvidia,audio-routing =
+                        "Headphones", "HPOR",
+                        "Headphones", "HPOL";
+
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&rt5640>;
+
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
+
+                clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
+                         <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA30_CLK_EXTERN1>;
+                clock-names = "pll_a", "pll_a_out0", "mclk";
+        };
 };
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
index e392bd2dab9b..1082c5ed90d1 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra30-cardhu.dtsi"
+#include "tegra30-cardhu.dtsi"
 
 /* This dts file support the cardhu A02 version of board */
 
@@ -22,7 +22,7 @@
                         regulator-always-on;
                         regulator-boot-on;
                         enable-active-high;
-                        gpio = <&pmic 6 0>;
+                        gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
                 };
 
                 sys_3v3_reg: regulator@101 {
@@ -34,7 +34,7 @@
                         regulator-always-on;
                         regulator-boot-on;
                         enable-active-high;
-                        gpio = <&pmic 7 0>;
+                        gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
                 };
 
                 usb1_vbus_reg: regulator@102 {
@@ -44,7 +44,7 @@
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
                         enable-active-high;
-                        gpio = <&gpio 68 0>; /* GPIO PI4 */
+                        gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>;
                         gpio-open-drain;
                         vin-supply = <&vdd_5v0_reg>;
                 };
@@ -56,7 +56,7 @@
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
                         enable-active-high;
-                        gpio = <&gpio 63 0>; /* GPIO PH7 */
+                        gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
                         gpio-open-drain;
                         vin-supply = <&vdd_5v0_reg>;
                 };
@@ -68,7 +68,7 @@
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
                         enable-active-high;
-                        gpio = <&pmic 2 0>;
+                        gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
                 };
 
                 vdd_bl_reg: regulator@105 {
@@ -80,13 +80,13 @@
                         regulator-always-on;
                         regulator-boot-on;
                         enable-active-high;
-                        gpio = <&gpio 83 0>; /* GPIO PK3 */
+                        gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>;
                 };
         };
 
         sdhci@78000400 {
                 status = "okay";
-                power-gpios = <&gpio 28 0>; /* gpio PD4 */
+                power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
                 bus-width = <4>;
                 keep-power-in-suspend;
         };
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
index d0db6c7e774f..bf012bddaafb 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra30-cardhu.dtsi"
+#include "tegra30-cardhu.dtsi"
 
 /* This dts file support the cardhu A04 and later versions of board */
 
@@ -22,7 +22,7 @@
                         regulator-always-on;
                         regulator-boot-on;
                         enable-active-high;
-                        gpio = <&pmic 7 0>;
+                        gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
                 };
 
                 sys_3v3_reg: regulator@101 {
@@ -34,7 +34,7 @@
                         regulator-always-on;
                         regulator-boot-on;
                         enable-active-high;
-                        gpio = <&pmic 6 0>;
+                        gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
                 };
 
                 usb1_vbus_reg: regulator@102 {
@@ -44,7 +44,7 @@
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
                         enable-active-high;
-                        gpio = <&gpio 238 0>; /* GPIO PDD6 */
+                        gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
                         gpio-open-drain;
                         vin-supply = <&vdd_5v0_reg>;
                 };
@@ -56,7 +56,7 @@
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
                         enable-active-high;
-                        gpio = <&gpio 236 0>; /* GPIO PDD4 */
+                        gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
                         gpio-open-drain;
                         vin-supply = <&vdd_5v0_reg>;
                 };
@@ -68,7 +68,7 @@
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
                         enable-active-high;
-                        gpio = <&pmic 8 0>;
+                        gpio = <&pmic 8 GPIO_ACTIVE_HIGH>;
                 };
 
                 vdd_bl_reg: regulator@105 {
@@ -80,7 +80,7 @@
                         regulator-always-on;
                         regulator-boot-on;
                         enable-active-high;
-                        gpio = <&gpio 234 0>; /* GPIO PDD2 */
+                        gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
                 };
 
                 vdd_bl2_reg: regulator@106 {
@@ -92,13 +92,13 @@
                         regulator-always-on;
                         regulator-boot-on;
                         enable-active-high;
-                        gpio = <&gpio 232 0>; /* GPIO PDD0 */
+                        gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
                 };
         };
 
         sdhci@78000400 {
                 status = "okay";
-                power-gpios = <&gpio 27 0>; /* gpio PD3 */
+                power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
                 bus-width = <4>;
                 keep-power-in-suspend;
         };
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 01b4c26fad96..f65b53d32416 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -1,4 +1,4 @@
-/include/ "tegra30.dtsi"
+#include "tegra30.dtsi"
 
 /**
  * This file contains common DT entry for all fab version of Cardhu.
@@ -146,7 +146,7 @@
                         compatible = "isil,isl29028";
                         reg = <0x44>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <88 0x04>; /*gpio PL0 */
+                        interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
                 };
         };
 
@@ -163,7 +163,7 @@
                         compatible = "wlf,wm8903";
                         reg = <0x1a>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <179 0x04>; /* gpio PW3 */
+                        interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
 
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -190,7 +190,7 @@
                         compatible = "ti,tps65911";
                         reg = <0x2d>;
 
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
                         #interrupt-cells = <2>;
                         interrupt-controller;
 
@@ -318,9 +318,9 @@
 
         sdhci@78000000 {
                 status = "okay";
-                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-                wp-gpios = <&gpio 155 0>; /* gpio PT3 */
-                power-gpios = <&gpio 31 0>; /* gpio PD7 */
+                cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+                wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
+                power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
                 bus-width = <4>;
         };
 
@@ -364,7 +364,7 @@
                         regulator-min-microvolt = <1800000>;
                         regulator-max-microvolt = <1800000>;
                         enable-active-high;
-                        gpio = <&gpio 220 0>; /* gpio PBB4 */
+                        gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
                         vin-supply = <&vio_reg>;
                 };
 
@@ -377,7 +377,7 @@
                         regulator-boot-on;
                         regulator-always-on;
                         enable-active-high;
-                        gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
+                        gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
                 };
 
                 emmc_3v3_reg: regulator@3 {
@@ -389,7 +389,7 @@
                         regulator-always-on;
                         regulator-boot-on;
                         enable-active-high;
-                        gpio = <&gpio 25 0>; /* gpio PD1 */
+                        gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
                         vin-supply = <&sys_3v3_reg>;
                 };
 
@@ -400,7 +400,7 @@
                         regulator-min-microvolt = <3300000>;
                         regulator-max-microvolt = <3300000>;
                         enable-active-high;
-                        gpio = <&gpio 30 0>; /* gpio PD6 */
+                        gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
                 };
 
                 pex_hvdd_3v3_reg: regulator@5 {
@@ -410,7 +410,7 @@
                         regulator-min-microvolt = <3300000>;
                         regulator-max-microvolt = <3300000>;
                         enable-active-high;
-                        gpio = <&gpio 95 0>; /* gpio PL7 */
+                        gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
                         vin-supply = <&sys_3v3_reg>;
                 };
 
@@ -421,7 +421,7 @@
                         regulator-min-microvolt = <2800000>;
                         regulator-max-microvolt = <2800000>;
                         enable-active-high;
-                        gpio = <&gpio 142 0>; /* gpio PR6 */
+                        gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
                         vin-supply = <&sys_3v3_reg>;
                 };
 
@@ -432,7 +432,7 @@
                         regulator-min-microvolt = <2800000>;
                         regulator-max-microvolt = <2800000>;
                         enable-active-high;
-                        gpio = <&gpio 143 0>; /* gpio PR7 */
+                        gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
                         vin-supply = <&sys_3v3_reg>;
                 };
 
@@ -443,7 +443,7 @@
                         regulator-min-microvolt = <3300000>;
                         regulator-max-microvolt = <3300000>;
                         enable-active-high;
-                        gpio = <&gpio 144 0>; /* gpio PS0 */
+                        gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
                         vin-supply = <&sys_3v3_reg>;
                 };
 
@@ -456,7 +456,7 @@
                         regulator-always-on;
                         regulator-boot-on;
                         enable-active-high;
-                        gpio = <&gpio 24 0>; /* gpio PD0 */
+                        gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
                         vin-supply = <&sys_3v3_reg>;
                 };
 
@@ -467,7 +467,7 @@
                         regulator-min-microvolt = <3300000>;
                         regulator-max-microvolt = <3300000>;
                         enable-active-high;
-                        gpio = <&gpio 94 0>; /* gpio PL6 */
+                        gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
                         vin-supply = <&sys_3v3_reg>;
                 };
 
@@ -480,7 +480,7 @@
                         regulator-always-on;
                         regulator-boot-on;
                         enable-active-high;
-                        gpio = <&gpio 92 0>; /* gpio PL4 */
+                        gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
                         vin-supply = <&sys_3v3_reg>;
                 };
 
@@ -491,7 +491,7 @@
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
                         enable-active-high;
-                        gpio = <&gpio 152 0>; /* GPIO PT0 */
+                        gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
                         gpio-open-drain;
                         vin-supply = <&vdd_5v0_reg>;
                 };
@@ -515,10 +515,13 @@
                 nvidia,i2s-controller = <&tegra_i2s1>;
                 nvidia,audio-codec = <&wm8903>;
 
-                nvidia,spkr-en-gpios = <&wm8903 2 0>;
-                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+                nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+                        GPIO_ACTIVE_HIGH>;
 
-                clocks = <&tegra_car 184>, <&tegra_car 185>, <&tegra_car 120>;
+                clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
+                         <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA30_CLK_EXTERN1>;
                 clock-names = "pll_a", "pll_a_out0", "mclk";
         };
 };
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 15ded605142a..d8783f0fae63 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -1,4 +1,8 @@
-/include/ "skeleton.dtsi"
+#include <dt-bindings/clock/tegra30-car.h>
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "skeleton.dtsi"
 
 / {
         compatible = "nvidia,tegra30";
@@ -15,9 +19,9 @@
         host1x {
                 compatible = "nvidia,tegra30-host1x", "simple-bus";
                 reg = <0x50000000 0x00024000>;
-                interrupts = <0 65 0x04   /* mpcore syncpt */
-                              0 67 0x04>; /* mpcore general */
-                clocks = <&tegra_car 28>;
+                interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
+                             <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
+                clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
 
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -27,36 +31,36 @@
                 mpe {
                         compatible = "nvidia,tegra30-mpe";
                         reg = <0x54040000 0x00040000>;
-                        interrupts = <0 68 0x04>;
-                        clocks = <&tegra_car 60>;
+                        interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA30_CLK_MPE>;
                 };
 
                 vi {
                         compatible = "nvidia,tegra30-vi";
                         reg = <0x54080000 0x00040000>;
-                        interrupts = <0 69 0x04>;
-                        clocks = <&tegra_car 164>;
+                        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA30_CLK_VI>;
                 };
 
                 epp {
                         compatible = "nvidia,tegra30-epp";
                         reg = <0x540c0000 0x00040000>;
-                        interrupts = <0 70 0x04>;
-                        clocks = <&tegra_car 19>;
+                        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA30_CLK_EPP>;
                 };
 
                 isp {
                         compatible = "nvidia,tegra30-isp";
                         reg = <0x54100000 0x00040000>;
-                        interrupts = <0 71 0x04>;
-                        clocks = <&tegra_car 23>;
+                        interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA30_CLK_ISP>;
                 };
 
                 gr2d {
                         compatible = "nvidia,tegra30-gr2d";
                         reg = <0x54140000 0x00040000>;
-                        interrupts = <0 72 0x04>;
-                        clocks = <&tegra_car 21>;
+                        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA30_CLK_GR2D>;
                 };
 
                 gr3d {
@@ -69,8 +73,9 @@
                 dc@54200000 {
                         compatible = "nvidia,tegra30-dc";
                         reg = <0x54200000 0x00040000>;
-                        interrupts = <0 73 0x04>;
-                        clocks = <&tegra_car 27>, <&tegra_car 179>;
+                        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA30_CLK_DISP1>,
+                                 <&tegra_car TEGRA30_CLK_PLL_P>;
                         clock-names = "disp1", "parent";
 
                         rgb {
@@ -81,8 +86,9 @@
                 dc@54240000 {
                         compatible = "nvidia,tegra30-dc";
                         reg = <0x54240000 0x00040000>;
-                        interrupts = <0 74 0x04>;
-                        clocks = <&tegra_car 26>, <&tegra_car 179>;
+                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA30_CLK_DISP2>,
+                                 <&tegra_car TEGRA30_CLK_PLL_P>;
                         clock-names = "disp2", "parent";
 
                         rgb {
@@ -93,8 +99,9 @@
                 hdmi {
                         compatible = "nvidia,tegra30-hdmi";
                         reg = <0x54280000 0x00040000>;
-                        interrupts = <0 75 0x04>;
-                        clocks = <&tegra_car 51>, <&tegra_car 189>;
+                        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA30_CLK_HDMI>,
+                                 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
                         clock-names = "hdmi", "parent";
                         status = "disabled";
                 };
@@ -102,15 +109,15 @@
                 tvo {
                         compatible = "nvidia,tegra30-tvo";
                         reg = <0x542c0000 0x00040000>;
-                        interrupts = <0 76 0x04>;
-                        clocks = <&tegra_car 169>;
+                        interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA30_CLK_TVO>;
                         status = "disabled";
                 };
 
                 dsi {
                         compatible = "nvidia,tegra30-dsi";
                         reg = <0x54300000 0x00040000>;
-                        clocks = <&tegra_car 48>;
+                        clocks = <&tegra_car TEGRA30_CLK_DSIA>;
                         status = "disabled";
                 };
         };
@@ -118,8 +125,9 @@
         timer@50004600 {
                 compatible = "arm,cortex-a9-twd-timer";
                 reg = <0x50040600 0x20>;
-                interrupts = <1 13 0xf04>;
-                clocks = <&tegra_car 214>;
+                interrupts = <GIC_PPI 13
+                        (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+                clocks = <&tegra_car TEGRA30_CLK_TWD>;
         };
 
         intc: interrupt-controller {
@@ -142,13 +150,13 @@
         timer@60005000 {
                 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
                 reg = <0x60005000 0x400>;
-                interrupts = <0 0 0x04
-                              0 1 0x04
-                              0 41 0x04
-                              0 42 0x04
-                              0 121 0x04
-                              0 122 0x04>;
-                clocks = <&tegra_car 5>;
+                interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA30_CLK_TIMER>;
         };
 
         tegra_car: clock {
@@ -160,39 +168,39 @@
         apbdma: dma {
                 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
                 reg = <0x6000a000 0x1400>;
-                interrupts = <0 104 0x04
-                              0 105 0x04
-                              0 106 0x04
-                              0 107 0x04
-                              0 108 0x04
-                              0 109 0x04
-                              0 110 0x04
-                              0 111 0x04
-                              0 112 0x04
-                              0 113 0x04
-                              0 114 0x04
-                              0 115 0x04
-                              0 116 0x04
-                              0 117 0x04
-                              0 118 0x04
-                              0 119 0x04
-                              0 128 0x04
-                              0 129 0x04
-                              0 130 0x04
-                              0 131 0x04
-                              0 132 0x04
-                              0 133 0x04
-                              0 134 0x04
-                              0 135 0x04
-                              0 136 0x04
-                              0 137 0x04
-                              0 138 0x04
-                              0 139 0x04
-                              0 140 0x04
-                              0 141 0x04
-                              0 142 0x04
-                              0 143 0x04>;
-                clocks = <&tegra_car 34>;
+                interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
         };
 
         ahb: ahb {
@@ -203,14 +211,14 @@
         gpio: gpio {
                 compatible = "nvidia,tegra30-gpio";
                 reg = <0x6000d000 0x1000>;
-                interrupts = <0 32 0x04
-                              0 33 0x04
-                              0 34 0x04
-                              0 35 0x04
-                              0 55 0x04
-                              0 87 0x04
-                              0 89 0x04
-                              0 125 0x04>;
+                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 #interrupt-cells = <2>;
@@ -235,9 +243,9 @@
                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                 reg = <0x70006000 0x40>;
                 reg-shift = <2>;
-                interrupts = <0 36 0x04>;
+                interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 8>;
-                clocks = <&tegra_car 6>;
+                clocks = <&tegra_car TEGRA30_CLK_UARTA>;
                 status = "disabled";
         };
 
@@ -245,9 +253,9 @@
                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                 reg = <0x70006040 0x40>;
                 reg-shift = <2>;
-                interrupts = <0 37 0x04>;
+                interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 9>;
-                clocks = <&tegra_car 160>;
+                clocks = <&tegra_car TEGRA30_CLK_UARTB>;
                 status = "disabled";
         };
 
@@ -255,9 +263,9 @@
                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                 reg = <0x70006200 0x100>;
                 reg-shift = <2>;
-                interrupts = <0 46 0x04>;
+                interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 10>;
-                clocks = <&tegra_car 55>;
+                clocks = <&tegra_car TEGRA30_CLK_UARTC>;
                 status = "disabled";
         };
 
@@ -265,9 +273,9 @@
                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                 reg = <0x70006300 0x100>;
                 reg-shift = <2>;
-                interrupts = <0 90 0x04>;
+                interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 19>;
-                clocks = <&tegra_car 65>;
+                clocks = <&tegra_car TEGRA30_CLK_UARTD>;
                 status = "disabled";
         };
 
@@ -275,9 +283,9 @@
                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                 reg = <0x70006400 0x100>;
                 reg-shift = <2>;
-                interrupts = <0 91 0x04>;
+                interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 20>;
-                clocks = <&tegra_car 66>;
+                clocks = <&tegra_car TEGRA30_CLK_UARTE>;
                 status = "disabled";
         };
 
@@ -285,24 +293,25 @@
                 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
                 reg = <0x7000a000 0x100>;
                 #pwm-cells = <2>;
-                clocks = <&tegra_car 17>;
+                clocks = <&tegra_car TEGRA30_CLK_PWM>;
                 status = "disabled";
         };
 
         rtc {
                 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
                 reg = <0x7000e000 0x100>;
-                interrupts = <0 2 0x04>;
-                clocks = <&tegra_car 4>;
+                interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA30_CLK_RTC>;
         };
 
         i2c@7000c000 {
                 compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
                 reg = <0x7000c000 0x100>;
-                interrupts = <0 38 0x04>;
+                interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 12>, <&tegra_car 182>;
+                clocks = <&tegra_car TEGRA30_CLK_I2C1>,
+                         <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
                 status = "disabled";
         };
@@ -310,10 +319,11 @@
         i2c@7000c400 {
                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
                 reg = <0x7000c400 0x100>;
-                interrupts = <0 84 0x04>;
+                interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 54>, <&tegra_car 182>;
+                clocks = <&tegra_car TEGRA30_CLK_I2C2>,
+                         <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
                 status = "disabled";
         };
@@ -321,10 +331,11 @@
         i2c@7000c500 {
                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
                 reg = <0x7000c500 0x100>;
-                interrupts = <0 92 0x04>;
+                interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 67>, <&tegra_car 182>;
+                clocks = <&tegra_car TEGRA30_CLK_I2C3>,
+                         <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
                 status = "disabled";
         };
@@ -332,10 +343,11 @@
         i2c@7000c700 {
                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
                 reg = <0x7000c700 0x100>;
-                interrupts = <0 120 0x04>;
+                interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 103>, <&tegra_car 182>;
+                clocks = <&tegra_car TEGRA30_CLK_I2C4>,
+                         <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
                 status = "disabled";
         };
@@ -343,10 +355,11 @@
         i2c@7000d000 {
                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
                 reg = <0x7000d000 0x100>;
-                interrupts = <0 53 0x04>;
+                interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 47>, <&tegra_car 182>;
+                clocks = <&tegra_car TEGRA30_CLK_I2C5>,
+                         <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
                 status = "disabled";
         };
@@ -354,81 +367,81 @@
         spi@7000d400 {
                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                 reg = <0x7000d400 0x200>;
-                interrupts = <0 59 0x04>;
+                interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 15>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 41>;
+                clocks = <&tegra_car TEGRA30_CLK_SBC1>;
                 status = "disabled";
         };
 
         spi@7000d600 {
                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                 reg = <0x7000d600 0x200>;
-                interrupts = <0 82 0x04>;
+                interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 16>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 44>;
+                clocks = <&tegra_car TEGRA30_CLK_SBC2>;
                 status = "disabled";
         };
 
         spi@7000d800 {
                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                 reg = <0x7000d800 0x200>;
-                interrupts = <0 83 0x04>;
+                interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 17>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 46>;
+                clocks = <&tegra_car TEGRA30_CLK_SBC3>;
                 status = "disabled";
         };
 
         spi@7000da00 {
                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                 reg = <0x7000da00 0x200>;
-                interrupts = <0 93 0x04>;
+                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 18>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 68>;
+                clocks = <&tegra_car TEGRA30_CLK_SBC4>;
                 status = "disabled";
         };
 
         spi@7000dc00 {
                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                 reg = <0x7000dc00 0x200>;
-                interrupts = <0 94 0x04>;
+                interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 27>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 104>;
+                clocks = <&tegra_car TEGRA30_CLK_SBC5>;
                 status = "disabled";
         };
 
         spi@7000de00 {
                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                 reg = <0x7000de00 0x200>;
-                interrupts = <0 79 0x04>;
+                interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 28>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 105>;
+                clocks = <&tegra_car TEGRA30_CLK_SBC6>;
                 status = "disabled";
         };
 
         kbc {
                 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
                 reg = <0x7000e200 0x100>;
-                interrupts = <0 85 0x04>;
-                clocks = <&tegra_car 36>;
+                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA30_CLK_KBC>;
                 status = "disabled";
         };
 
         pmc {
                 compatible = "nvidia,tegra30-pmc";
                 reg = <0x7000e400 0x400>;
-                clocks = <&tegra_car 218>, <&clk32k_in>;
+                clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
                 clock-names = "pclk", "clk32k_in";
         };
 
@@ -438,7 +451,7 @@
                        0x7000f03c 0x1b4
                        0x7000f200 0x028
                        0x7000f284 0x17c>;
-                interrupts = <0 77 0x04>;
+                interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         iommu {
@@ -455,12 +468,19 @@
                 compatible = "nvidia,tegra30-ahub";
                 reg = <0x70080000 0x200
                        0x70080200 0x100>;
-                interrupts = <0 103 0x04>;
+                interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 1>;
-                clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
-                         <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
-                         <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
-                         <&tegra_car 110>, <&tegra_car 162>;
+                clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
+                         <&tegra_car TEGRA30_CLK_APBIF>,
+                         <&tegra_car TEGRA30_CLK_I2S0>,
+                         <&tegra_car TEGRA30_CLK_I2S1>,
+                         <&tegra_car TEGRA30_CLK_I2S2>,
+                         <&tegra_car TEGRA30_CLK_I2S3>,
+                         <&tegra_car TEGRA30_CLK_I2S4>,
+                         <&tegra_car TEGRA30_CLK_DAM0>,
+                         <&tegra_car TEGRA30_CLK_DAM1>,
+                         <&tegra_car TEGRA30_CLK_DAM2>,
+                         <&tegra_car TEGRA30_CLK_SPDIF_IN>;
                 clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
                               "spdif_in";
@@ -472,7 +492,7 @@
                         compatible = "nvidia,tegra30-i2s";
                         reg = <0x70080300 0x100>;
                         nvidia,ahub-cif-ids = <4 4>;
-                        clocks = <&tegra_car 30>;
+                        clocks = <&tegra_car TEGRA30_CLK_I2S0>;
                         status = "disabled";
                 };
 
@@ -480,7 +500,7 @@
                         compatible = "nvidia,tegra30-i2s";
                         reg = <0x70080400 0x100>;
                         nvidia,ahub-cif-ids = <5 5>;
-                        clocks = <&tegra_car 11>;
+                        clocks = <&tegra_car TEGRA30_CLK_I2S1>;
                         status = "disabled";
                 };
 
@@ -488,7 +508,7 @@
                         compatible = "nvidia,tegra30-i2s";
                         reg = <0x70080500 0x100>;
                         nvidia,ahub-cif-ids = <6 6>;
-                        clocks = <&tegra_car 18>;
+                        clocks = <&tegra_car TEGRA30_CLK_I2S2>;
                         status = "disabled";
                 };
 
@@ -496,7 +516,7 @@
                         compatible = "nvidia,tegra30-i2s";
                         reg = <0x70080600 0x100>;
                         nvidia,ahub-cif-ids = <7 7>;
-                        clocks = <&tegra_car 101>;
+                        clocks = <&tegra_car TEGRA30_CLK_I2S3>;
                         status = "disabled";
                 };
 
@@ -504,7 +524,7 @@
                         compatible = "nvidia,tegra30-i2s";
                         reg = <0x70080700 0x100>;
                         nvidia,ahub-cif-ids = <8 8>;
-                        clocks = <&tegra_car 102>;
+                        clocks = <&tegra_car TEGRA30_CLK_I2S4>;
                         status = "disabled";
                 };
         };
@@ -512,32 +532,32 @@
         sdhci@78000000 {
                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                 reg = <0x78000000 0x200>;
-                interrupts = <0 14 0x04>;
-                clocks = <&tegra_car 14>;
+                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
                 status = "disabled";
         };
 
         sdhci@78000200 {
                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                 reg = <0x78000200 0x200>;
-                interrupts = <0 15 0x04>;
-                clocks = <&tegra_car 9>;
+                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
                 status = "disabled";
         };
 
         sdhci@78000400 {
                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                 reg = <0x78000400 0x200>;
-                interrupts = <0 19 0x04>;
-                clocks = <&tegra_car 69>;
+                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
                 status = "disabled";
         };
 
         sdhci@78000600 {
                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                 reg = <0x78000600 0x200>;
-                interrupts = <0 31 0x04>;
-                clocks = <&tegra_car 15>;
+                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
                 status = "disabled";
         };
 
@@ -572,9 +592,9 @@
 
         pmu {
                 compatible = "arm,cortex-a9-pmu";
-                interrupts = <0 144 0x04
-                              0 145 0x04
-                              0 146 0x04
-                              0 147 0x04>;
+                interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
         };
 };
diff --git a/arch/arm/boot/dts/twl4030_omap3.dtsi b/arch/arm/boot/dts/twl4030_omap3.dtsi
new file mode 100644
index 000000000000..c353ef0a6ac7
--- /dev/null
+++ b/arch/arm/boot/dts/twl4030_omap3.dtsi
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2013 Linaro, Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+&twl {
+        pinctrl-names = "default";
+        pinctrl-0 = <&twl4030_pins>;
+};
+
+&omap3_pmx_core {
+        /*
+         * On most OMAP3 platforms, the twl4030 IRQ line is connected
+         * to the SYS_NIRQ line on OMAP.  Therefore, configure the
+         * defaults for the SYS_NIRQ pin here.
+         */
+        twl4030_pins: pinmux_twl4030_pins {
+                pinctrl-single,pins = <
+                        0x1b0 (PIN_INPUT_PULLUP | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* sys_nirq.sys_nirq */
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/usb_a9260.dts b/arch/arm/boot/dts/usb_a9260.dts
index a604107eb474..de0c24f5210a 100644
--- a/arch/arm/boot/dts/usb_a9260.dts
+++ b/arch/arm/boot/dts/usb_a9260.dts
@@ -20,4 +20,13 @@
         memory {
                 reg = <0x20000000 0x4000000>;
         };
+
+        ahb {
+                apb {
+                        shdwc@fffffd10 {
+                                atmel,wakeup-counter = <10>;
+                                atmel,wakeup-rtt-timer;
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts
index f8ec36cb036b..290e60383baf 100644
--- a/arch/arm/boot/dts/usb_a9263.dts
+++ b/arch/arm/boot/dts/usb_a9263.dts
@@ -47,6 +47,20 @@
                                 status = "okay";
                         };
 
+                        spi0: spi@fffa4000 {
+                                cs-gpios = <&pioB 15 GPIO_ACTIVE_HIGH>;
+                                status = "okay";
+                                mtd_dataflash@0 {
+                                        compatible = "atmel,at45", "atmel,dataflash";
+                                        reg = <0>;
+                                        spi-max-frequency = <15000000>;
+                                };
+                        };
+
+                        shdwc@fffffd10 {
+                                atmel,wakeup-counter = <10>;
+                                atmel,wakeup-rtt-timer;
+                        };
                 };
 
                 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts
index c979c06cf697..ec77cf8f9695 100644
--- a/arch/arm/boot/dts/usb_a9g20.dts
+++ b/arch/arm/boot/dts/usb_a9g20.dts
@@ -6,25 +6,9 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-#include "at91sam9g20.dtsi"
-#include "usb_a9260_common.dtsi"
+#include "usb_a9g20_common.dtsi"
 
 / {
         model = "Calao USB A9G20";
         compatible = "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9";
-
-        chosen {
-                bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
-        };
-
-        memory {
-                reg = <0x20000000 0x4000000>;
-        };
-
-        i2c@0 {
-                rv3029c2@56 {
-                        compatible = "rv3029c2";
-                        reg = <0x56>;
-                };
-        };
 };
diff --git a/arch/arm/boot/dts/usb_a9g20_common.dtsi b/arch/arm/boot/dts/usb_a9g20_common.dtsi
new file mode 100644
index 000000000000..0b3b36182fe5
--- /dev/null
+++ b/arch/arm/boot/dts/usb_a9g20_common.dtsi
@@ -0,0 +1,27 @@
+/*
+ * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board
+ *
+ *  Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include "at91sam9g20.dtsi"
+#include "usb_a9260_common.dtsi"
+
+/ {
+        chosen {
+                bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
+        };
+
+        memory {
+                reg = <0x20000000 0x4000000>;
+        };
+
+        i2c@0 {
+                rv3029c2@56 {
+                        compatible = "rv3029c2";
+                        reg = <0x56>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/usb_a9g20_lpw.dts b/arch/arm/boot/dts/usb_a9g20_lpw.dts
new file mode 100644
index 000000000000..f8cb1b9a01c5
--- /dev/null
+++ b/arch/arm/boot/dts/usb_a9g20_lpw.dts
@@ -0,0 +1,31 @@
+/*
+ * usb_a9g20_lpw.dts - Device Tree file for Caloa USB A9G20 Low Power board
+ *
+ *  Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+#include "usb_a9g20_common.dtsi"
+
+/ {
+        model = "Calao USB A9G20 Low Power";
+        compatible = "calao,usb-a9g20-lpw", "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9";
+
+        ahb {
+                apb {
+                        spi1: spi@fffcc000 {
+                                cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>;
+                                status = "okay";
+                                mmc-slot@0 {
+                                        compatible = "mmc-spi-slot";
+                                        reg = <0>;
+                                        voltage-ranges = <3200 3400>;
+                                        spi-max-frequency = <25000000>;
+                                        interrupt-parent = <&pioC>;
+                                        interrupts = <4 IRQ_TYPE_EDGE_BOTH>;
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/vf610-pinfunc.h b/arch/arm/boot/dts/vf610-pinfunc.h
new file mode 100644
index 000000000000..1ee681f7ce2f
--- /dev/null
+++ b/arch/arm/boot/dts/vf610-pinfunc.h
@@ -0,0 +1,810 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_VF610_PINFUNC_H
+#define __DTS_VF610_PINFUNC_H
+
+/*
+ * The pin function ID for VF610 is a tuple of:
+ * <mux_reg input_reg mux_mode input_val>
+ */
+
+#define ALT0    0x0
+#define ALT1    0x1
+#define ALT2    0x2
+#define ALT3    0x3
+#define ALT4    0x4
+#define ALT5    0x5
+#define ALT6    0x6
+#define ALT7    0x7
+
+
+#define VF610_PAD_PTA6__GPIO_0                  0x000 0x000 ALT0 0x0
+#define VF610_PAD_PTA6__RMII_CLKOUT             0x000 0x000 ALT1 0x0
+#define VF610_PAD_PTA6__RMII_CLKIN              0x000 0x2F0 ALT2 0x0
+#define VF610_PAD_PTA6__DCU1_TCON11             0x000 0x000 ALT4 0x0
+#define VF610_PAD_PTA6__DCU1_R2                 0x000 0x000 ALT7 0x0
+#define VF610_PAD_PTA8__GPIO_1                  0x004 0x000 ALT0 0x0
+#define VF610_PAD_PTA8__TCLK                    0x004 0x000 ALT1 0x0
+#define VF610_PAD_PTA8__DCU0_R0                 0x004 0x000 ALT4 0x0
+#define VF610_PAD_PTA8__MLB_CLK                 0x004 0x354 ALT7 0x0
+#define VF610_PAD_PTA9__GPIO_2                  0x008 0x000 ALT0 0x0
+#define VF610_PAD_PTA9__TDI                     0x008 0x000 ALT1 0x0
+#define VF610_PAD_PTA9__RMII_CLKOUT             0x008 0x000 ALT2 0x0
+#define VF610_PAD_PTA9__RMII_CLKIN              0x008 0x2F0 ALT3 0x1
+#define VF610_PAD_PTA9__DCU0_R1                 0x008 0x000 ALT4 0x0
+#define VF610_PAD_PTA9__WDOG_B                  0x008 0x000 ALT6 0x0
+#define VF610_PAD_PTA10__GPIO_3                 0x00C 0x000 ALT0 0x0
+#define VF610_PAD_PTA10__TDO                    0x00C 0x000 ALT1 0x0
+#define VF610_PAD_PTA10__EXT_AUDIO_MCLK         0x00C 0x2EC ALT2 0x0
+#define VF610_PAD_PTA10__DCU0_G0                0x00C 0x000 ALT4 0x0
+#define VF610_PAD_PTA10__ENET_TS_CLKIN          0x00C 0x2F4 ALT6 0x0
+#define VF610_PAD_PTA10__MLB_SIGNAL             0x00C 0x35C ALT7 0x0
+#define VF610_PAD_PTA11__GPIO_4                 0x010 0x000 ALT0 0x0
+#define VF610_PAD_PTA11__TMS                    0x010 0x000 ALT1 0x0
+#define VF610_PAD_PTA11__DCU0_G1                0x010 0x000 ALT4 0x0
+#define VF610_PAD_PTA11__MLB_DATA               0x010 0x358 ALT7 0x0
+#define VF610_PAD_PTA12__GPIO_5                 0x014 0x000 ALT0 0x0
+#define VF610_PAD_PTA12__TRACECK                0x014 0x000 ALT1 0x0
+#define VF610_PAD_PTA12__EXT_AUDIO_MCLK         0x014 0x2EC ALT2 0x1
+#define VF610_PAD_PTA12__VIU_DATA13             0x014 0x000 ALT6 0x0
+#define VF610_PAD_PTA12__I2C0_SCL               0x014 0x33C ALT7 0x0
+#define VF610_PAD_PTA16__GPIO_6                 0x018 0x000 ALT0 0x0
+#define VF610_PAD_PTA16__TRACED0                0x018 0x000 ALT1 0x0
+#define VF610_PAD_PTA16__USB0_VBUS_EN           0x018 0x000 ALT2 0x0
+#define VF610_PAD_PTA16__ADC1_SE0               0x018 0x000 ALT3 0x0
+#define VF610_PAD_PTA16__LCD29                  0x018 0x000 ALT4 0x0
+#define VF610_PAD_PTA16__SAI2_TX_BCLK           0x018 0x370 ALT5 0x0
+#define VF610_PAD_PTA16__VIU_DATA14             0x018 0x000 ALT6 0x0
+#define VF610_PAD_PTA16__I2C0_SDA               0x018 0x340 ALT7 0x0
+#define VF610_PAD_PTA17__GPIO_7                 0x01C 0x000 ALT0 0x0
+#define VF610_PAD_PTA17__TRACED1                0x01C 0x000 ALT1 0x0
+#define VF610_PAD_PTA17__USB0_VBUS_OC           0x01C 0x000 ALT2 0x0
+#define VF610_PAD_PTA17__ADC1_SE1               0x01C 0x000 ALT3 0x0
+#define VF610_PAD_PTA17__LCD30                  0x01C 0x000 ALT4 0x0
+#define VF610_PAD_PTA17__USB0_SOF_PULSE         0x01C 0x000 ALT5 0x0
+#define VF610_PAD_PTA17__VIU_DATA15             0x01C 0x000 ALT6 0x0
+#define VF610_PAD_PTA17__I2C1_SCL               0x01C 0x344 ALT7 0x0
+#define VF610_PAD_PTA18__GPIO_8                 0x020 0x000 ALT0 0x0
+#define VF610_PAD_PTA18__TRACED2                0x020 0x000 ALT1 0x0
+#define VF610_PAD_PTA18__ADC0_SE0               0x020 0x000 ALT2 0x0
+#define VF610_PAD_PTA18__FTM1_QD_PHA            0x020 0x334 ALT3 0x0
+#define VF610_PAD_PTA18__LCD31                  0x020 0x000 ALT4 0x0
+#define VF610_PAD_PTA18__SAI2_TX_DATA           0x020 0x000 ALT5 0x0
+#define VF610_PAD_PTA18__VIU_DATA16             0x020 0x000 ALT6 0x0
+#define VF610_PAD_PTA18__I2C1_SDA               0x020 0x348 ALT7 0x0
+#define VF610_PAD_PTA19__GPIO_9                 0x024 0x000 ALT0 0x0
+#define VF610_PAD_PTA19__TRACED3                0x024 0x000 ALT1 0x0
+#define VF610_PAD_PTA19__ADC0_SE1               0x024 0x000 ALT2 0x0
+#define VF610_PAD_PTA19__FTM1_QD_PHB            0x024 0x338 ALT3 0x0
+#define VF610_PAD_PTA19__LCD32                  0x024 0x000 ALT4 0x0
+#define VF610_PAD_PTA19__SAI2_TX_SYNC           0x024 0x000 ALT5 0x0
+#define VF610_PAD_PTA19__VIU_DATA17             0x024 0x000 ALT6 0x0
+#define VF610_PAD_PTA19__QSPI1_A_QSCK           0x024 0x374 ALT7 0x0
+#define VF610_PAD_PTA20__GPIO_10                0x028 0x000 ALT0 0x0
+#define VF610_PAD_PTA20__TRACED4                0x028 0x000 ALT1 0x0
+#define VF610_PAD_PTA20__LCD33                  0x028 0x000 ALT4 0x0
+#define VF610_PAD_PTA20__UART3_TX               0x028 0x394 ALT6 0x0
+#define VF610_PAD_PTA20__DCU1_HSYNC             0x028 0x000 ALT7 0x0
+#define VF610_PAD_PTA21__GPIO_11                0x02C 0x000 ALT0 0x0
+#define VF610_PAD_PTA21__TRACED5                0x02C 0x000 ALT1 0x0
+#define VF610_PAD_PTA21__SAI2_RX_BCLK           0x02C 0x364 ALT5 0x0
+#define VF610_PAD_PTA21__UART3_RX               0x02C 0x390 ALT6 0x0
+#define VF610_PAD_PTA21__DCU1_VSYNC             0x02C 0x000 ALT7 0x0
+#define VF610_PAD_PTA22__GPIO_12                0x030 0x000 ALT0 0x0
+#define VF610_PAD_PTA22__TRACED6                0x030 0x000 ALT1 0x0
+#define VF610_PAD_PTA22__SAI2_RX_DATA           0x030 0x368 ALT5 0x0
+#define VF610_PAD_PTA22__I2C2_SCL               0x030 0x34C ALT6 0x0
+#define VF610_PAD_PTA22__DCU1_TAG               0x030 0x000 ALT7 0x0
+#define VF610_PAD_PTA23__GPIO_13                0x034 0x000 ALT0 0x0
+#define VF610_PAD_PTA23__TRACED7                0x034 0x000 ALT1 0x0
+#define VF610_PAD_PTA23__SAI2_RX_SYNC           0x034 0x36C ALT5 0x0
+#define VF610_PAD_PTA23__I2C2_SDA               0x034 0x350 ALT6 0x0
+#define VF610_PAD_PTA23__DCU1_DE                0x034 0x000 ALT7 0x0
+#define VF610_PAD_PTA24__GPIO_14                0x038 0x000 ALT0 0x0
+#define VF610_PAD_PTA24__TRACED8                0x038 0x000 ALT1 0x0
+#define VF610_PAD_PTA24__USB1_VBUS_EN           0x038 0x000 ALT2 0x0
+#define VF610_PAD_PTA24__ESDHC1_CLK             0x038 0x000 ALT5 0x0
+#define VF610_PAD_PTA24__DCU1_TCON4             0x038 0x000 ALT6 0x0
+#define VF610_PAD_PTA24__DDR_TEST_PAD_CTRL      0x038 0x000 ALT7 0x0
+#define VF610_PAD_PTA25__GPIO_15                0x03C 0x000 ALT0 0x0
+#define VF610_PAD_PTA25__TRACED9                0x03C 0x000 ALT1 0x0
+#define VF610_PAD_PTA25__USB1_VBUS_OC           0x03C 0x000 ALT2 0x0
+#define VF610_PAD_PTA25__ESDHC1_CMD             0x03C 0x000 ALT5 0x0
+#define VF610_PAD_PTA25__DCU1_TCON5             0x03C 0x000 ALT6 0x0
+#define VF610_PAD_PTA26__GPIO_16                0x040 0x000 ALT0 0x0
+#define VF610_PAD_PTA26__TRACED10               0x040 0x000 ALT1 0x0
+#define VF610_PAD_PTA26__SAI3_TX_BCLK           0x040 0x000 ALT2 0x0
+#define VF610_PAD_PTA26__ESDHC1_DAT0            0x040 0x000 ALT5 0x0
+#define VF610_PAD_PTA26__DCU1_TCON6             0x040 0x000 ALT6 0x0
+#define VF610_PAD_PTA27__GPIO_17                0x044 0x000 ALT0 0x0
+#define VF610_PAD_PTA27__TRACED11               0x044 0x000 ALT1 0x0
+#define VF610_PAD_PTA27__SAI3_RX_BCLK           0x044 0x000 ALT2 0x0
+#define VF610_PAD_PTA27__ESDHC1_DAT1            0x044 0x000 ALT5 0x0
+#define VF610_PAD_PTA27__DCU1_TCON7             0x044 0x000 ALT6 0x0
+#define VF610_PAD_PTA28__GPIO_18                0x048 0x000 ALT0 0x0
+#define VF610_PAD_PTA28__TRACED12               0x048 0x000 ALT1 0x0
+#define VF610_PAD_PTA28__SAI3_RX_DATA           0x048 0x000 ALT2 0x0
+#define VF610_PAD_PTA28__ENET1_1588_TMR0        0x048 0x000 ALT3 0x0
+#define VF610_PAD_PTA28__UART4_TX               0x048 0x000 ALT4 0x0
+#define VF610_PAD_PTA28__ESDHC1_DATA2           0x048 0x000 ALT5 0x0
+#define VF610_PAD_PTA28__DCU1_TCON8             0x048 0x000 ALT6 0x0
+#define VF610_PAD_PTA29__GPIO_19                0x04C 0x000 ALT0 0x0
+#define VF610_PAD_PTA29__TRACED13               0x04C 0x000 ALT1 0x0
+#define VF610_PAD_PTA29__SAI3_TX_DATA           0x04C 0x000 ALT2 0x0
+#define VF610_PAD_PTA29__ENET1_1588_TMR1        0x04C 0x000 ALT3 0x0
+#define VF610_PAD_PTA29__UART4_RX               0x04C 0x000 ALT4 0x0
+#define VF610_PAD_PTA29__ESDHC1_DAT3            0x04C 0x000 ALT5 0x0
+#define VF610_PAD_PTA29__DCU1_TCON9             0x04C 0x000 ALT6 0x0
+#define VF610_PAD_PTA30__GPIO_20                0x050 0x000 ALT0 0x0
+#define VF610_PAD_PTA30__TRACED14               0x050 0x000 ALT1 0x0
+#define VF610_PAD_PTA30__SAI3_RX_SYNC           0x050 0x000 ALT2 0x0
+#define VF610_PAD_PTA30__ENET1_1588_TMR2        0x050 0x000 ALT3 0x0
+#define VF610_PAD_PTA30__UART4_RTS              0x050 0x000 ALT4 0x0
+#define VF610_PAD_PTA30__I2C3_SCL               0x050 0x000 ALT5 0x0
+#define VF610_PAD_PTA30__UART3_TX               0x050 0x394 ALT7 0x1
+#define VF610_PAD_PTA31__GPIO_21                0x054 0x000 ALT0 0x0
+#define VF610_PAD_PTA31__TRACED15               0x054 0x000 ALT1 0x0
+#define VF610_PAD_PTA31__SAI3_TX_SYNC           0x054 0x000 ALT2 0x0
+#define VF610_PAD_PTA31__ENET1_1588_TMR3        0x054 0x000 ALT3 0x0
+#define VF610_PAD_PTA31__UART4_CTS              0x054 0x000 ALT4 0x0
+#define VF610_PAD_PTA31__I2C3_SDA               0x054 0x000 ALT5 0x0
+#define VF610_PAD_PTA31__UART3_RX               0x054 0x390 ALT7 0x1
+#define VF610_PAD_PTB0__GPIO_22                 0x058 0x000 ALT0 0x0
+#define VF610_PAD_PTB0__FTM0_CH0                0x058 0x000 ALT1 0x0
+#define VF610_PAD_PTB0__ADC0_SE2                0x058 0x000 ALT2 0x0
+#define VF610_PAD_PTB0__TRACE_CTL               0x058 0x000 ALT3 0x0
+#define VF610_PAD_PTB0__LCD34                   0x058 0x000 ALT4 0x0
+#define VF610_PAD_PTB0__SAI2_RX_BCLK            0x058 0x364 ALT5 0x1
+#define VF610_PAD_PTB0__VIU_DATA18              0x058 0x000 ALT6 0x0
+#define VF610_PAD_PTB0__QSPI1_A_QPCS0           0x058 0x000 ALT7 0x0
+#define VF610_PAD_PTB1__GPIO_23                 0x05C 0x000 ALT0 0x0
+#define VF610_PAD_PTB1__FTM0_CH1                0x05C 0x000 ALT1 0x0
+#define VF610_PAD_PTB1__ADC0_SE3                0x05C 0x000 ALT2 0x0
+#define VF610_PAD_PTB1__SRC_RCON30              0x05C 0x000 ALT3 0x0
+#define VF610_PAD_PTB1__LCD35                   0x05C 0x000 ALT4 0x0
+#define VF610_PAD_PTB1__SAI2_RX_DATA            0x05C 0x368 ALT5 0x1
+#define VF610_PAD_PTB1__VIU_DATA19              0x05C 0x000 ALT6 0x0
+#define VF610_PAD_PTB1__QSPI1_A_DATA3           0x05C 0x000 ALT7 0x0
+#define VF610_PAD_PTB2__GPIO_24                 0x060 0x000 ALT0 0x0
+#define VF610_PAD_PTB2__FTM0_CH2                0x060 0x000 ALT1 0x0
+#define VF610_PAD_PTB2__ADC1_SE2                0x060 0x000 ALT2 0x0
+#define VF610_PAD_PTB2__SRC_RCON31              0x060 0x000 ALT3 0x0
+#define VF610_PAD_PTB2__LCD36                   0x060 0x000 ALT4 0x0
+#define VF610_PAD_PTB2__SAI2_RX_SYNC            0x060 0x36C ALT5 0x1
+#define VF610_PAD_PTB2__VIDEO_IN0_DATA20        0x060 0x000 ALT6 0x0
+#define VF610_PAD_PTB2__QSPI1_A_DATA2           0x060 0x000 ALT7 0x0
+#define VF610_PAD_PTB3__GPIO_25                 0x064 0x000 ALT0 0x0
+#define VF610_PAD_PTB3__FTM0_CH3                0x064 0x000 ALT1 0x0
+#define VF610_PAD_PTB3__ADC1_SE3                0x064 0x000 ALT2 0x0
+#define VF610_PAD_PTB3__PDB_EXTRIG              0x064 0x000 ALT3 0x0
+#define VF610_PAD_PTB3__LCD37                   0x064 0x000 ALT4 0x0
+#define VF610_PAD_PTB3__VIU_DATA21              0x064 0x000 ALT6 0x0
+#define VF610_PAD_PTB3__QSPI1_A_DATA1           0x064 0x000 ALT7 0x0
+#define VF610_PAD_PTB4__GPIO_26                 0x068 0x000 ALT0 0x0
+#define VF610_PAD_PTB4__FTM0_CH4                0x068 0x000 ALT1 0x0
+#define VF610_PAD_PTB4__UART1_TX                0x068 0x380 ALT2 0x0
+#define VF610_PAD_PTB4__ADC0_SE4                0x068 0x000 ALT3 0x0
+#define VF610_PAD_PTB4__LCD38                   0x068 0x000 ALT4 0x0
+#define VF610_PAD_PTB4__VIU_FID                 0x068 0x3A8 ALT5 0x0
+#define VF610_PAD_PTB4__VIU_DATA22              0x068 0x000 ALT6 0x0
+#define VF610_PAD_PTB4__QSPI1_A_DATA0           0x068 0x000 ALT7 0x0
+#define VF610_PAD_PTB5__GPIO_27                 0x06C 0x000 ALT0 0x0
+#define VF610_PAD_PTB5__FTM0_CH5                0x06C 0x000 ALT1 0x0
+#define VF610_PAD_PTB5__UART1_RX                0x06C 0x37C ALT2 0x0
+#define VF610_PAD_PTB5__ADC1_SE4                0x06C 0x000 ALT3 0x0
+#define VF610_PAD_PTB5__LCD39                   0x06C 0x000 ALT4 0x0
+#define VF610_PAD_PTB5__VIU_DE                  0x06C 0x3A4 ALT5 0x0
+#define VF610_PAD_PTB5__QSPI1_A_DQS             0x06C 0x000 ALT7 0x0
+#define VF610_PAD_PTB6__GPIO_28                 0x070 0x000 ALT0 0x0
+#define VF610_PAD_PTB6__FTM0_CH6                0x070 0x000 ALT1 0x0
+#define VF610_PAD_PTB6__UART1_RTS               0x070 0x000 ALT2 0x0
+#define VF610_PAD_PTB6__QSPI0_QPCS1_A           0x070 0x000 ALT3 0x0
+#define VF610_PAD_PTB6__LCD_LCD40               0x070 0x000 ALT4 0x0
+#define VF610_PAD_PTB6__FB_CLKOUT               0x070 0x000 ALT5 0x0
+#define VF610_PAD_PTB6__VIU_HSYNC               0x070 0x000 ALT6 0x0
+#define VF610_PAD_PTB6__UART2_TX                0x070 0x38C ALT7 0x0
+#define VF610_PAD_PTB7__GPIO_29                 0x074 0x000 ALT0 0x0
+#define VF610_PAD_PTB7__FTM0_CH7                0x074 0x000 ALT1 0x0
+#define VF610_PAD_PTB7__UART1_CTS               0x074 0x378 ALT2 0x0
+#define VF610_PAD_PTB7__QSPI0_B_QPCS1           0x074 0x000 ALT3 0x0
+#define VF610_PAD_PTB7__LCD41                   0x074 0x000 ALT4 0x0
+#define VF610_PAD_PTB7__VIU_VSYNC               0x074 0x000 ALT6 0x0
+#define VF610_PAD_PTB7__UART2_RX                0x074 0x388 ALT7 0x0
+#define VF610_PAD_PTB8__GPIO_30                 0x078 0x000 ALT0 0x0
+#define VF610_PAD_PTB8__FTM1_CH0                0x078 0x32C ALT1 0x0
+#define VF610_PAD_PTB8__FTM1_QD_PHA             0x078 0x334 ALT3 0x1
+#define VF610_PAD_PTB8__VIU_DE                  0x078 0x3A4 ALT5 0x1
+#define VF610_PAD_PTB8__DCU1_R6                 0x078 0x000 ALT7 0x0
+#define VF610_PAD_PTB9__GPIO_31                 0x07C 0x000 ALT0 0x0
+#define VF610_PAD_PTB9__FTM1_CH1                0x07C 0x330 ALT1 0x0
+#define VF610_PAD_PTB9__FTM1_QD_PHB             0x07C 0x338 ALT3 0x1
+#define VF610_PAD_PTB9__DCU1_R7                 0x07C 0x000 ALT7 0x0
+#define VF610_PAD_PTB10__GPIO_32                0x080 0x000 ALT0 0x0
+#define VF610_PAD_PTB10__UART0_TX               0x080 0x000 ALT1 0x0
+#define VF610_PAD_PTB10__DCU0_TCON4             0x080 0x000 ALT4 0x0
+#define VF610_PAD_PTB10__VIU_DE                 0x080 0x3A4 ALT5 0x2
+#define VF610_PAD_PTB10__CKO1                   0x080 0x000 ALT6 0x0
+#define VF610_PAD_PTB10__ENET_TS_CLKIN          0x080 0x2F4 ALT7 0x1
+#define VF610_PAD_PTB11__GPIO_33                0x084 0x000 ALT0 0x0
+#define VF610_PAD_PTB11__UART0_RX               0x084 0x000 ALT1 0x0
+#define VF610_PAD_PTB11__DCU0_TCON5             0x084 0x000 ALT4 0x0
+#define VF610_PAD_PTB11__SNVS_ALARM_OUT_B       0x084 0x000 ALT5 0x0
+#define VF610_PAD_PTB11__CKO2                   0x084 0x000 ALT6 0x0
+#define VF610_PAD_PTB11_ENET0_1588_TMR0         0x084 0x304 ALT7 0x0
+#define VF610_PAD_PTB12__GPIO_34                0x088 0x000 ALT0 0x0
+#define VF610_PAD_PTB12__UART0_RTS              0x088 0x000 ALT1 0x0
+#define VF610_PAD_PTB12__DSPI0_CS5              0x088 0x000 ALT3 0x0
+#define VF610_PAD_PTB12__DCU0_TCON6             0x088 0x000 ALT4 0x0
+#define VF610_PAD_PTB12__FB_AD1                 0x088 0x000 ALT5 0x0
+#define VF610_PAD_PTB12__NMI                    0x088 0x000 ALT6 0x0
+#define VF610_PAD_PTB12__ENET0_1588_TMR1        0x088 0x308 ALT7 0x0
+#define VF610_PAD_PTB13__GPIO_35                0x08C 0x000 ALT0 0x0
+#define VF610_PAD_PTB13__UART0_CTS              0x08C 0x000 ALT1 0x0
+#define VF610_PAD_PTB13__DSPI0_CS4              0x08C 0x000 ALT3 0x0
+#define VF610_PAD_PTB13__DCU0_TCON7             0x08C 0x000 ALT4 0x0
+#define VF610_PAD_PTB13__FB_AD0                 0x08C 0x000 ALT5 0x0
+#define VF610_PAD_PTB13__TRACE_CTL              0x08C 0x000 ALT6 0x0
+#define VF610_PAD_PTB14__GPIO_36                0x090 0x000 ALT0 0x0
+#define VF610_PAD_PTB14__CAN0_RX                0x090 0x000 ALT1 0x0
+#define VF610_PAD_PTB14__I2C0_SCL               0x090 0x33C ALT2 0x1
+#define VF610_PAD_PTB14__DCU0_TCON8             0x090 0x000 ALT4 0x0
+#define VF610_PAD_PTB14__DCU1_PCLK              0x090 0x000 ALT7 0x0
+#define VF610_PAD_PTB15__GPIO_37                0x094 0x000 ALT0 0x0
+#define VF610_PAD_PTB15__CAN0_TX                0x094 0x000 ALT1 0x0
+#define VF610_PAD_PTB15__I2C0_SDA               0x094 0x340 ALT2 0x1
+#define VF610_PAD_PTB15__DCU0_TCON9             0x094 0x000 ALT4 0x0
+#define VF610_PAD_PTB15__VIU_PIX_CLK            0x094 0x3AC ALT7 0x0
+#define VF610_PAD_PTB16__GPIO_38                0x098 0x000 ALT0 0x0
+#define VF610_PAD_PTB16__CAN1_RX                0x098 0x000 ALT1 0x0
+#define VF610_PAD_PTB16__I2C1_SCL               0x098 0x344 ALT2 0x1
+#define VF610_PAD_PTB16__DCU0_TCON10            0x098 0x000 ALT4 0x0
+#define VF610_PAD_PTB17__GPIO_39                0x09C 0x000 ALT0 0x0
+#define VF610_PAD_PTB17__CAN1_TX                0x09C 0x000 ALT1 0x0
+#define VF610_PAD_PTB17__I2C1_SDA               0x09C 0x348 ALT2 0x1
+#define VF610_PAD_PTB17__DCU0_TCON11            0x09C 0x000 ALT4 0x0
+#define VF610_PAD_PTB18__GPIO_40                0x0A0 0x000 ALT0 0x0
+#define VF610_PAD_PTB18__DSPI0_CS1              0x0A0 0x000 ALT1 0x0
+#define VF610_PAD_PTB18__EXT_AUDIO_MCLK         0x0A0 0x2EC ALT2 0x2
+#define VF610_PAD_PTB18__VIU_DATA9              0x0A0 0x000 ALT6 0x0
+#define VF610_PAD_PTB19__GPIO_41                0x0A4 0x000 ALT0 0x0
+#define VF610_PAD_PTB19__DSPI0_CS0              0x0A4 0x000 ALT1 0x0
+#define VF610_PAD_PTB19__VIU_DATA10             0x0A4 0x000 ALT6 0x0
+#define VF610_PAD_PTB20__GPIO_42                0x0A8 0x000 ALT0 0x0
+#define VF610_PAD_PTB20__DSPI0_SIN              0x0A8 0x000 ALT1 0x0
+#define VF610_PAD_PTB20__LCD42                  0x0A8 0x000 ALT4 0x0
+#define VF610_PAD_PTB20__VIU_DATA11             0x0A8 0x000 ALT6 0x0
+#define VF610_PAD_PTB21__GPIO_43                0x0AC 0x000 ALT0 0x0
+#define VF610_PAD_PTB21__DSPI0_SOUT             0x0AC 0x000 ALT1 0x0
+#define VF610_PAD_PTB21__LCD43                  0x0AC 0x000 ALT4 0x0
+#define VF610_PAD_PTB21__VIU_DATA12             0x0AC 0x000 ALT6 0x0
+#define VF610_PAD_PTB21__DCU1_PCLK              0x0AC 0x000 ALT7 0x0
+#define VF610_PAD_PTB22__GPIO_44                0x0B0 0x000 ALT0 0x0
+#define VF610_PAD_PTB22__DSPI0_SCK              0x0B0 0x000 ALT1 0x0
+#define VF610_PAD_PTB22__VLCD                   0x0B0 0x000 ALT4 0x0
+#define VF610_PAD_PTB22__VIU_FID                0x0B0 0x3A8 ALT5 0x1
+#define VF610_PAD_PTC0__GPIO_45                 0x0B4 0x000 ALT0 0x0
+#define VF610_PAD_PTC0__ENET_RMII0_MDC          0x0B4 0x000 ALT1 0x0
+#define VF610_PAD_PTC0__FTM1_CH0                0x0B4 0x32C ALT2 0x1
+#define VF610_PAD_PTC0__DSPI0_CS3               0x0B4 0x000 ALT3 0x0
+#define VF610_PAD_PTC0__ESAI_SCKT               0x0B4 0x310 ALT4 0x0
+#define VF610_PAD_PTC0__ESDHC0_CLK              0x0B4 0x000 ALT5 0x0
+#define VF610_PAD_PTC0__VIU_DATA0               0x0B4 0x000 ALT6 0x0
+#define VF610_PAD_PTC0__SRC_RCON18              0x0B4 0x398 ALT7 0x0
+#define VF610_PAD_PTC1__GPIO_46                 0x0B8 0x000 ALT0 0x0
+#define VF610_PAD_PTC1__ENET_RMII0_MDIO         0x0B8 0x000 ALT1 0x0
+#define VF610_PAD_PTC1__FTM1_CH1                0x0B8 0x330 ALT2 0x1
+#define VF610_PAD_PTC1__DSPI0_CS2               0x0B8 0x000 ALT3 0x0
+#define VF610_PAD_PTC1__ESAI_FST                0x0B8 0x30C ALT4 0x0
+#define VF610_PAD_PTC1__ESDHC0_CMD              0x0B8 0x000 ALT5 0x0
+#define VF610_PAD_PTC1__VIU_DATA1               0x0B8 0x000 ALT6 0x0
+#define VF610_PAD_PTC1__SRC_RCON19              0x0B8 0x39C ALT7 0x0
+#define VF610_PAD_PTC2__GPIO_47                 0x0BC 0x000 ALT0 0x0
+#define VF610_PAD_PTC2__ENET_RMII0_CRS          0x0BC 0x000 ALT1 0x0
+#define VF610_PAD_PTC2__UART1_TX                0x0BC 0x380 ALT2 0x1
+#define VF610_PAD_PTC2__ESAI_SDO0               0x0BC 0x314 ALT4 0x0
+#define VF610_PAD_PTC2__ESDHC0_DAT0             0x0BC 0x000 ALT5 0x0
+#define VF610_PAD_PTC2__VIU_DATA2               0x0BC 0x000 ALT6 0x0
+#define VF610_PAD_PTC2__SRC_RCON20              0x0BC 0x3A0 ALT7 0x0
+#define VF610_PAD_PTC3__GPIO_48                 0x0C0 0x000 ALT0 0x0
+#define VF610_PAD_PTC3__ENET_RMII0_RXD1         0x0C0 0x000 ALT1 0x0
+#define VF610_PAD_PTC3__UART1_RX                0x0C0 0x37C ALT2 0x1
+#define VF610_PAD_PTC3__ESAI_SDO1               0x0C0 0x318 ALT4 0x0
+#define VF610_PAD_PTC3__ESDHC0_DAT1             0x0C0 0x000 ALT5 0x0
+#define VF610_PAD_PTC3__VIU_DATA3               0x0C0 0x000 ALT6 0x0
+#define VF610_PAD_PTC3__DCU0_R0                 0x0C0 0x000 ALT7 0x0
+#define VF610_PAD_PTC4__GPIO_49                 0x0C4 0x000 ALT0 0x0
+#define VF610_PAD_PTC4__ENET_RMII0_RXD0         0x0C4 0x000 ALT1 0x0
+#define VF610_PAD_PTC4__UART1_RTS               0x0C4 0x000 ALT2 0x0
+#define VF610_PAD_PTC4__DSPI1_CS1               0x0C4 0x000 ALT3 0x0
+#define VF610_PAD_PTC4__ESAI_SDO2               0x0C4 0x31C ALT4 0x0
+#define VF610_PAD_PTC4__ESDHC0_DAT2             0x0C4 0x000 ALT5 0x0
+#define VF610_PAD_PTC4__VIU_DATA4               0x0C4 0x000 ALT6 0x0
+#define VF610_PAD_PTC4__DCU0_R1                 0x0C4 0x000 ALT7 0x0
+#define VF610_PAD_PTC5__GPIO_50                 0x0C8 0x000 ALT0 0x0
+#define VF610_PAD_PTC5__ENET_RMII0_RXER         0x0C8 0x000 ALT1 0x0
+#define VF610_PAD_PTC5__UART1_CTS               0x0C8 0x378 ALT2 0x1
+#define VF610_PAD_PTC5__DSPI1_CS0               0x0C8 0x300 ALT3 0x0
+#define VF610_PAD_PTC5__ESAI_SDO3               0x0C8 0x320 ALT4 0x0
+#define VF610_PAD_PTC5__ESDHC0_DAT3             0x0C8 0x000 ALT5 0x0
+#define VF610_PAD_PTC5__VIU_DATA5               0x0C8 0x000 ALT6 0x0
+#define VF610_PAD_PTC5__DCU0_G0                 0x0C8 0x000 ALT7 0x0
+#define VF610_PAD_PTC6__GPIO_51                 0x0CC 0x000 ALT0 0x0
+#define VF610_PAD_PTC6__ENET_RMII0_TXD1         0x0CC 0x000 ALT1 0x0
+#define VF610_PAD_PTC6__DSPI1_SIN               0x0CC 0x2FC ALT3 0x0
+#define VF610_PAD_PTC6__ESAI_SDI0               0x0CC 0x328 ALT4 0x0
+#define VF610_PAD_PTC6__ESDHC0_WP               0x0CC 0x000 ALT5 0x0
+#define VF610_PAD_PTC6__VIU_DATA6               0x0CC 0x000 ALT6 0x0
+#define VF610_PAD_PTC6__DCU0_G1                 0x0CC 0x000 ALT7 0x0
+#define VF610_PAD_PTC7__GPIO_52                 0x0D0 0x000 ALT0 0x0
+#define VF610_PAD_PTC7__ENET_RMII0_TXD0         0x0D0 0x000 ALT1 0x0
+#define VF610_PAD_PTC7__DSPI1_SOUT              0x0D0 0x000 ALT3 0x0
+#define VF610_PAD_PTC7__ESAI_SDI1               0x0D0 0x324 ALT4 0x0
+#define VF610_PAD_PTC7__VIU_DATA7               0x0D0 0x000 ALT6 0x0
+#define VF610_PAD_PTC7__DCU0_B0                 0x0D0 0x000 ALT7 0x0
+#define VF610_PAD_PTC8__GPIO_53                 0x0D4 0x000 ALT0 0x0
+#define VF610_PAD_PTC8__ENET_RMII0_TXEN         0x0D4 0x000 ALT1 0x0
+#define VF610_PAD_PTC8__DSPI1_SCK               0x0D4 0x2F8 ALT3 0x0
+#define VF610_PAD_PTC8__VIU_DATA8               0x0D4 0x000 ALT6 0x0
+#define VF610_PAD_PTC8__DCU0_B1                 0x0D4 0x000 ALT7 0x0
+#define VF610_PAD_PTC9__GPIO_54                 0x0D8 0x000 ALT0 0x0
+#define VF610_PAD_PTC9__ENET_RMII1_MDC          0x0D8 0x000 ALT1 0x0
+#define VF610_PAD_PTC9__ESAI_SCKT               0x0D8 0x310 ALT3 0x1
+#define VF610_PAD_PTC9__MLB_CLK                 0x0D8 0x354 ALT6 0x1
+#define VF610_PAD_PTC9__DEBUG_OUT0              0x0D8 0x000 ALT7 0x0
+#define VF610_PAD_PTC10__GPIO_55                0x0DC 0x000 ALT0 0x0
+#define VF610_PAD_PTC10__ENET_RMII1_MDIO        0x0DC 0x000 ALT1 0x0
+#define VF610_PAD_PTC10__ESAI_FST               0x0DC 0x30C ALT3 0x1
+#define VF610_PAD_PTC10__MLB_SIGNAL             0x0DC 0x35C ALT6 0x1
+#define VF610_PAD_PTC10__DEBUG_OUT1             0x0DC 0x000 ALT7 0x0
+#define VF610_PAD_PTC11__GPIO_56                0x0E0 0x000 ALT0 0x0
+#define VF610_PAD_PTC11__ENET_RMII1_CRS         0x0E0 0x000 ALT1 0x0
+#define VF610_PAD_PTC11__ESAI_SDO0              0x0E0 0x314 ALT3 0x1
+#define VF610_PAD_PTC11__MLB_DATA               0x0E0 0x358 ALT6 0x1
+#define VF610_PAD_PTC11__DEBUG_OUT              0x0E0 0x000 ALT7 0x0
+#define VF610_PAD_PTC12__GPIO_57                0x0E4 0x000 ALT0 0x0
+#define VF610_PAD_PTC12__ENET_RMII_RXD1         0x0E4 0x000 ALT1 0x0
+#define VF610_PAD_PTC12__ESAI_SDO1              0x0E4 0x318 ALT3 0x1
+#define VF610_PAD_PTC12__SAI2_TX_BCLK           0x0E4 0x370 ALT5 0x1
+#define VF610_PAD_PTC12__DEBUG_OUT3             0x0E4 0x000 ALT7 0x0
+#define VF610_PAD_PTC13__GPIO_58                0x0E8 0x000 ALT0 0x0
+#define VF610_PAD_PTC13__ENET_RMII1_RXD0        0x0E8 0x000 ALT1 0x0
+#define VF610_PAD_PTC13__ESAI_SDO2              0x0E8 0x31C ALT3 0x1
+#define VF610_PAD_PTC13__SAI2_RX_BCLK           0x0E8 0x364 ALT5 0x2
+#define VF610_PAD_PTC13__DEBUG_OUT4             0x0E8 0x000 ALT7 0x0
+#define VF610_PAD_PTC14__GPIO_59                0x0EC 0x000 ALT0 0x0
+#define VF610_PAD_PTC14__ENET_RMII1_RXER        0x0EC 0x000 ALT1 0x0
+#define VF610_PAD_PTC14__ESAI_SDO3              0x0EC 0x320 ALT3 0x1
+#define VF610_PAD_PTC14__UART5_TX               0x0EC 0x000 ALT4 0x0
+#define VF610_PAD_PTC14__SAI2_RX_DATA           0x0EC 0x368 ALT5 0x2
+#define VF610_PAD_PTC14__ADC0_SE6               0x0EC 0x000 ALT6 0x0
+#define VF610_PAD_PTC14__DEBUG_OUT5             0x0EC 0x000 ALT7 0x0
+#define VF610_PAD_PTC15__GPIO_60                0x0F0 0x000 ALT0 0x0
+#define VF610_PAD_PTC15__ENET_RMII1_TXD1        0x0F0 0x000 ALT1 0x0
+#define VF610_PAD_PTC15__ESAI_SDI0              0x0F0 0x328 ALT3 0x1
+#define VF610_PAD_PTC15__UART5_RX               0x0F0 0x000 ALT4 0x0
+#define VF610_PAD_PTC15__SAI2_TX_DATA           0x0F0 0x000 ALT5 0x0
+#define VF610_PAD_PTC15__ADC0_SE7               0x0F0 0x000 ALT6 0x0
+#define VF610_PAD_PTC15__DEBUG_OUT6             0x0F0 0x000 ALT7 0x0
+#define VF610_PAD_PTC16__GPIO_61                0x0F4 0x000 ALT0 0x0
+#define VF610_PAD_PTC16__ENET_RMII1_TXD0        0x0F4 0x000 ALT1 0x0
+#define VF610_PAD_PTC16__ESAI_SDI1              0x0F4 0x324 ALT3 0x1
+#define VF610_PAD_PTC16__UART5_RTS              0x0F4 0x000 ALT4 0x0
+#define VF610_PAD_PTC16__SAI2_RX_SYNC           0x0F4 0x36C ALT5 0x2
+#define VF610_PAD_PTC16__ADC1_SE6               0x0F4 0x000 ALT6 0x0
+#define VF610_PAD_PTC16__DEBUG_OUT7             0x0F4 0x000 ALT7 0x0
+#define VF610_PAD_PTC17__GPIO_62                0x0F8 0x000 ALT0 0x0
+#define VF610_PAD_PTC17__ENET_RMII1_TXEN        0x0F8 0x000 ALT1 0x0
+#define VF610_PAD_PTC17__ADC1_SE7               0x0F8 0x000 ALT3 0x0
+#define VF610_PAD_PTC17__UART5_CTS              0x0F8 0x000 ALT4 0x0
+#define VF610_PAD_PTC17__SAI2_TX_SYNC           0x0F8 0x374 ALT5 0x1
+#define VF610_PAD_PTC17__USB1_SOF_PULSE         0x0F8 0x000 ALT6 0x0
+#define VF610_PAD_PTC17__DEBUG_OUT8             0x0F8 0x000 ALT7 0x0
+#define VF610_PAD_PTD31__GPIO_63                0x0FC 0x000 ALT0 0x0
+#define VF610_PAD_PTD31__FB_AD31                0x0FC 0x000 ALT1 0x0
+#define VF610_PAD_PTD31__NF_IO15                0x0FC 0x000 ALT2 0x0
+#define VF610_PAD_PTD31__FTM3_CH0               0x0FC 0x000 ALT4 0x0
+#define VF610_PAD_PTD31__DSPI2_CS1              0x0FC 0x000 ALT5 0x0
+#define VF610_PAD_PTD31__DEBUG_OUT9             0x0FC 0x000 ALT7 0x0
+#define VF610_PAD_PTD30__GPIO_64                0x100 0x000 ALT0 0x0
+#define VF610_PAD_PTD30__FB_AD30                0x100 0x000 ALT1 0x0
+#define VF610_PAD_PTD30__NF_IO14                0x100 0x000 ALT2 0x0
+#define VF610_PAD_PTD30__FTM3_CH1               0x100 0x000 ALT4 0x0
+#define VF610_PAD_PTD30__DSPI2_CS0              0x100 0x000 ALT5 0x0
+#define VF610_PAD_PTD30__DEBUG_OUT10            0x100 0x000 ALT7 0x0
+#define VF610_PAD_PTD29__GPIO_65                0x104 0x000 ALT0 0x0
+#define VF610_PAD_PTD29__FB_AD29                0x104 0x000 ALT1 0x0
+#define VF610_PAD_PTD29__NF_IO13                0x104 0x000 ALT2 0x0
+#define VF610_PAD_PTD29__FTM3_CH2               0x104 0x000 ALT4 0x0
+#define VF610_PAD_PTD29__DSPI2_SIN              0x104 0x000 ALT5 0x0
+#define VF610_PAD_PTD29__DEBUG_OUT11            0x104 0x000 ALT7 0x0
+#define VF610_PAD_PTD28__GPIO_66                0x108 0x000 ALT0 0x0
+#define VF610_PAD_PTD28__FB_AD28                0x108 0x000 ALT1 0x0
+#define VF610_PAD_PTD28__NF_IO12                0x108 0x000 ALT2 0x0
+#define VF610_PAD_PTD28__I2C2_SCL               0x108 0x34C ALT3 0x1
+#define VF610_PAD_PTD28__FTM3_CH3               0x108 0x000 ALT4 0x0
+#define VF610_PAD_PTD28__DSPI2_SOUT             0x108 0x000 ALT5 0x0
+#define VF610_PAD_PTD28__DEBUG_OUT12            0x108 0x000 ALT7 0x0
+#define VF610_PAD_PTD27__GPIO_67                0x10C 0x000 ALT0 0x0
+#define VF610_PAD_PTD27__FB_AD27                0x10C 0x000 ALT1 0x0
+#define VF610_PAD_PTD27__NF_IO11                0x10C 0x000 ALT2 0x0
+#define VF610_PAD_PTD27__I2C2_SDA               0x10C 0x350 ALT3 0x1
+#define VF610_PAD_PTD27__FTM3_CH4               0x10C 0x000 ALT4 0x0
+#define VF610_PAD_PTD27__DSPI2_SCK              0x10C 0x000 ALT5 0x0
+#define VF610_PAD_PTD27__DEBUG_OUT13            0x10C 0x000 ALT7 0x0
+#define VF610_PAD_PTD26__GPIO_68                0x110 0x000 ALT0 0x0
+#define VF610_PAD_PTD26__FB_AD26                0x110 0x000 ALT1 0x0
+#define VF610_PAD_PTD26__NF_IO10                0x110 0x000 ALT2 0x0
+#define VF610_PAD_PTD26__FTM3_CH5               0x110 0x000 ALT4 0x0
+#define VF610_PAD_PTD26__ESDHC1_WP              0x110 0x000 ALT5 0x0
+#define VF610_PAD_PTD26__DEBUG_OUT14            0x110 0x000 ALT7 0x0
+#define VF610_PAD_PTD25__GPIO_69                0x114 0x000 ALT0 0x0
+#define VF610_PAD_PTD25__FB_AD25                0x114 0x000 ALT1 0x0
+#define VF610_PAD_PTD25__NF_IO9                 0x114 0x000 ALT2 0x0
+#define VF610_PAD_PTD25__FTM3_CH6               0x114 0x000 ALT4 0x0
+#define VF610_PAD_PTD25__DEBUG_OUT15            0x114 0x000 ALT7 0x0
+#define VF610_PAD_PTD24__GPIO_70                0x118 0x000 ALT0 0x0
+#define VF610_PAD_PTD24__FB_AD24                0x118 0x000 ALT1 0x0
+#define VF610_PAD_PTD24__NF_IO8                 0x118 0x000 ALT2 0x0
+#define VF610_PAD_PTD24__FTM3_CH7               0x118 0x000 ALT4 0x0
+#define VF610_PAD_PTD24__DEBUG_OUT16            0x118 0x000 ALT7 0x0
+#define VF610_PAD_PTD23__GPIO_71                0x11C 0x000 ALT0 0x0
+#define VF610_PAD_PTD23__FB_AD23                0x11C 0x000 ALT1 0x0
+#define VF610_PAD_PTD23__NF_IO7                 0x11C 0x000 ALT2 0x0
+#define VF610_PAD_PTD23__FTM2_CH0               0x11C 0x000 ALT3 0x0
+#define VF610_PAD_PTD23__ENET0_1588_TMR0        0x11C 0x304 ALT4 0x1
+#define VF610_PAD_PTD23__ESDHC0_DAT4            0x11C 0x000 ALT5 0x0
+#define VF610_PAD_PTD23__UART2_TX               0x11C 0x38C ALT6 0x1
+#define VF610_PAD_PTD23__DCU1_R3                0x11C 0x000 ALT7 0x0
+#define VF610_PAD_PTD22__GPIO_72                0x120 0x000 ALT0 0x0
+#define VF610_PAD_PTD22__FB_AD22                0x120 0x000 ALT1 0x0
+#define VF610_PAD_PTD22__NF_IO6                 0x120 0x000 ALT2 0x0
+#define VF610_PAD_PTD22__FTM2_CH1               0x120 0x000 ALT3 0x0
+#define VF610_PAD_PTD22__ENET0_1588_TMR1        0x120 0x308 ALT4 0x1
+#define VF610_PAD_PTD22__ESDHC0_DAT5            0x120 0x000 ALT5 0x0
+#define VF610_PAD_PTD22__UART2_RX               0x120 0x388 ALT6 0x1
+#define VF610_PAD_PTD22__DCU1_R4                0x120 0x000 ALT7 0x0
+#define VF610_PAD_PTD21__GPIO_73                0x124 0x000 ALT0 0x0
+#define VF610_PAD_PTD21__FB_AD21                0x124 0x000 ALT1 0x0
+#define VF610_PAD_PTD21__NF_IO5                 0x124 0x000 ALT2 0x0
+#define VF610_PAD_PTD21__ENET0_1588_TMR2        0x124 0x000 ALT4 0x0
+#define VF610_PAD_PTD21__ESDHC0_DAT6            0x124 0x000 ALT5 0x0
+#define VF610_PAD_PTD21__UART2_RTS              0x124 0x000 ALT6 0x0
+#define VF610_PAD_PTD21__DCU1_R5                0x124 0x000 ALT7 0x0
+#define VF610_PAD_PTD20__GPIO_74                0x128 0x000 ALT0 0x0
+#define VF610_PAD_PTD20__FB_AD20                0x128 0x000 ALT1 0x0
+#define VF610_PAD_PTD20__NF_IO4                 0x128 0x000 ALT2 0x0
+#define VF610_PAD_PTD20__ENET0_1588_TMR3        0x128 0x000 ALT4 0x0
+#define VF610_PAD_PTD20__ESDHC0_DAT7            0x128 0x000 ALT5 0x0
+#define VF610_PAD_PTD20__UART2_CTS              0x128 0x384 ALT6 0x0
+#define VF610_PAD_PTD20__DCU1_R0                0x128 0x000 ALT7 0x0
+#define VF610_PAD_PTD19__GPIO_75                0x12C 0x000 ALT0 0x0
+#define VF610_PAD_PTD19__FB_AD19                0x12C 0x000 ALT1 0x0
+#define VF610_PAD_PTD19__NF_IO3                 0x12C 0x000 ALT2 0x0
+#define VF610_PAD_PTD19__ESAI_SCKR              0x12C 0x000 ALT3 0x0
+#define VF610_PAD_PTD19__I2C0_SCL               0x12C 0x33C ALT4 0x2
+#define VF610_PAD_PTD19__FTM2_QD_PHA            0x12C 0x000 ALT5 0x0
+#define VF610_PAD_PTD19__DCU1_R1                0x12C 0x000 ALT7 0x0
+#define VF610_PAD_PTD18__GPIO_76                0x130 0x000 ALT0 0x0
+#define VF610_PAD_PTD18__FB_AD18                0x130 0x000 ALT1 0x0
+#define VF610_PAD_PTD18__NF_IO2                 0x130 0x000 ALT2 0x0
+#define VF610_PAD_PTD18__ESAI_FSR               0x130 0x000 ALT3 0x0
+#define VF610_PAD_PTD18__I2C0_SDA               0x130 0x340 ALT4 0x2
+#define VF610_PAD_PTD18__FTM2_QD_PHB            0x130 0x000 ALT5 0x0
+#define VF610_PAD_PTD18__DCU1_G0                0x130 0x000 ALT7 0x0
+#define VF610_PAD_PTD17__GPIO_77                0x134 0x000 ALT0 0x0
+#define VF610_PAD_PTD17__FB_AD17                0x134 0x000 ALT1 0x0
+#define VF610_PAD_PTD17__NF_IO1                 0x134 0x000 ALT2 0x0
+#define VF610_PAD_PTD17__ESAI_HCKR              0x134 0x000 ALT3 0x0
+#define VF610_PAD_PTD17__I2C1_SCL               0x134 0x344 ALT4 0x2
+#define VF610_PAD_PTD17__DCU1_G1                0x134 0x000 ALT7 0x0
+#define VF610_PAD_PTD16__GPIO_78                0x138 0x000 ALT0 0x0
+#define VF610_PAD_PTD16__FB_AD16                0x138 0x000 ALT1 0x0
+#define VF610_PAD_PTD16__NF_IO0                 0x138 0x000 ALT2 0x0
+#define VF610_PAD_PTD16__ESAI_HCKT              0x138 0x000 ALT3 0x0
+#define VF610_PAD_PTD16__I2C1_SDA               0x138 0x348 ALT4 0x2
+#define VF610_PAD_PTD16__DCU1_G2                0x138 0x000 ALT7 0x0
+#define VF610_PAD_PTD0__GPIO_79                 0x13C 0x000 ALT0 0x0
+#define VF610_PAD_PTD0__QSPI0_A_QSCK            0x13C 0x000 ALT1 0x0
+#define VF610_PAD_PTD0__UART2_TX                0x13C 0x38C ALT2 0x2
+#define VF610_PAD_PTD0__FB_AD15                 0x13C 0x000 ALT4 0x0
+#define VF610_PAD_PTD0__SPDIF_EXTCLK            0x13C 0x000 ALT5 0x0
+#define VF610_PAD_PTD0__DEBUG_OUT17             0x13C 0x000 ALT7 0x0
+#define VF610_PAD_PTD1__GPIO_80                 0x140 0x000 ALT0 0x0
+#define VF610_PAD_PTD1__QSPI0_A_CS0             0x140 0x000 ALT1 0x0
+#define VF610_PAD_PTD1__UART2_RX                0x140 0x388 ALT2 0x2
+#define VF610_PAD_PTD1__FB_AD14                 0x140 0x000 ALT4 0x0
+#define VF610_PAD_PTD1__SPDIF_IN1               0x140 0x000 ALT5 0x0
+#define VF610_PAD_PTD1__DEBUG_OUT18             0x140 0x000 ALT7 0x0
+#define VF610_PAD_PTD2__GPIO_81                 0x144 0x000 ALT0 0x0
+#define VF610_PAD_PTD2__QSPI0_A_DATA3           0x144 0x000 ALT1 0x0
+#define VF610_PAD_PTD2__UART2_RTS               0x144 0x000 ALT2 0x0
+#define VF610_PAD_PTD2__DSPI1_CS3               0x144 0x000 ALT3 0x0
+#define VF610_PAD_PTD2__FB_AD13                 0x144 0x000 ALT4 0x0
+#define VF610_PAD_PTD2__SPDIF_OUT1              0x144 0x000 ALT5 0x0
+#define VF610_PAD_PTD2__DEBUG_OUT19             0x144 0x000 ALT7 0x0
+#define VF610_PAD_PTD3__GPIO_82                 0x148 0x000 ALT0 0x0
+#define VF610_PAD_PTD3__QSPI0_A_DATA2           0x148 0x000 ALT1 0x0
+#define VF610_PAD_PTD3__UART2_CTS               0x148 0x384 ALT2 0x1
+#define VF610_PAD_PTD3__DSPI1_CS2               0x148 0x000 ALT3 0x0
+#define VF610_PAD_PTD3__FB_AD12                 0x148 0x000 ALT4 0x0
+#define VF610_PAD_PTD3__SPDIF_PLOCK             0x148 0x000 ALT5 0x0
+#define VF610_PAD_PTD3__DEBUG_OUT20             0x148 0x000 ALT7 0x0
+#define VF610_PAD_PTD4__GPIO_83                 0x14C 0x000 ALT0 0x0
+#define VF610_PAD_PTD4__QSPI0_A_DATA1           0x14C 0x000 ALT1 0x0
+#define VF610_PAD_PTD4__DSPI1_CS1               0x14C 0x000 ALT3 0x0
+#define VF610_PAD_PTD4__FB_AD11                 0x14C 0x000 ALT4 0x0
+#define VF610_PAD_PTD4__SPDIF_SRCLK             0x14C 0x000 ALT5 0x0
+#define VF610_PAD_PTD4__DEBUG_OUT21             0x14C 0x000 ALT7 0x0
+#define VF610_PAD_PTD5__GPIO_84                 0x150 0x000 ALT0 0x0
+#define VF610_PAD_PTD5__QSPI0_A_DATA0           0x150 0x000 ALT1 0x0
+#define VF610_PAD_PTD5__DSPI1_CS0               0x150 0x300 ALT3 0x1
+#define VF610_PAD_PTD5__FB_AD10                 0x150 0x000 ALT4 0x0
+#define VF610_PAD_PTD5__DEBUG_OUT22             0x150 0x000 ALT7 0x0
+#define VF610_PAD_PTD6__GPIO_85                 0x154 0x000 ALT0 0x0
+#define VF610_PAD_PTD6__QSPI1_A_DQS             0x154 0x000 ALT1 0x0
+#define VF610_PAD_PTD6__DSPI1_SIN               0x154 0x2FC ALT3 0x1
+#define VF610_PAD_PTD6__FB_AD9                  0x154 0x000 ALT4 0x0
+#define VF610_PAD_PTD6__DEBUG_OUT23             0x154 0x000 ALT7 0x0
+#define VF610_PAD_PTD7__GPIO_86                 0x158 0x000 ALT0 0x0
+#define VF610_PAD_PTD7__QSPI0_B_QSCK            0x158 0x000 ALT1 0x0
+#define VF610_PAD_PTD7__DSPI1_SOUT              0x158 0x000 ALT3 0x0
+#define VF610_PAD_PTD7__FB_AD8                  0x158 0x000 ALT4 0x0
+#define VF610_PAD_PTD7__DEBUG_OUT24             0x158 0x000 ALT7 0x0
+#define VF610_PAD_PTD8__GPIO_87                 0x15C 0x000 ALT0 0x0
+#define VF610_PAD_PTD8__QSPI0_B_CS0             0x15C 0x000 ALT1 0x0
+#define VF610_PAD_PTD8__FB_CLKOUT               0x15C 0x000 ALT2 0x0
+#define VF610_PAD_PTD8__DSPI1_SCK               0x15C 0x2F8 ALT3 0x1
+#define VF610_PAD_PTD8__FB_AD7                  0x15C 0x000 ALT4 0x0
+#define VF610_PAD_PTD8__DEBUG_OUT25             0x15C 0x000 ALT7 0x0
+#define VF610_PAD_PTD9__GPIO_88                 0x160 0x000 ALT0 0x0
+#define VF610_PAD_PTD9__QSPI0_B_DATA3           0x160 0x000 ALT1 0x0
+#define VF610_PAD_PTD9__DSPI3_CS1               0x160 0x000 ALT2 0x0
+#define VF610_PAD_PTD9__FB_AD6                  0x160 0x000 ALT4 0x0
+#define VF610_PAD_PTD9__SAI1_TX_SYNC            0x160 0x360 ALT6 0x0
+#define VF610_PAD_PTD9__DCU1_B0                 0x160 0x000 ALT7 0x0
+#define VF610_PAD_PTD10__GPIO_89                0x164 0x000 ALT0 0x0
+#define VF610_PAD_PTD10__QSPI0_B_DATA2          0x164 0x000 ALT1 0x0
+#define VF610_PAD_PTD10__DSPI3_CS0              0x164 0x000 ALT2 0x0
+#define VF610_PAD_PTD10__FB_AD5                 0x164 0x000 ALT4 0x0
+#define VF610_PAD_PTD10__DCU1_B1                0x164 0x000 ALT7 0x0
+#define VF610_PAD_PTD11__GPIO_90                0x168 0x000 ALT0 0x0
+#define VF610_PAD_PTD11__QSPI0_B_DATA1          0x168 0x000 ALT1 0x0
+#define VF610_PAD_PTD11__DSPI3_SIN              0x168 0x000 ALT2 0x0
+#define VF610_PAD_PTD11__FB_AD4                 0x168 0x000 ALT4 0x0
+#define VF610_PAD_PTD11__DEBUG_OUT26            0x168 0x000 ALT7 0x0
+#define VF610_PAD_PTD12__GPIO_91                0x16C 0x000 ALT0 0x0
+#define VF610_PAD_PTD12__QSPI0_B_DATA0          0x16C 0x000 ALT1 0x0
+#define VF610_PAD_PTD12__DSPI3_SOUT             0x16C 0x000 ALT2 0x0
+#define VF610_PAD_PTD12__FB_AD3                 0x16C 0x000 ALT4 0x0
+#define VF610_PAD_PTD12__DEBUG_OUT27            0x16C 0x000 ALT7 0x0
+#define VF610_PAD_PTD13__GPIO_92                0x170 0x000 ALT0 0x0
+#define VF610_PAD_PTD13__QSPI0_B_DQS            0x170 0x000 ALT1 0x0
+#define VF610_PAD_PTD13__DSPI3_SCK              0x170 0x000 ALT2 0x0
+#define VF610_PAD_PTD13__FB_AD2                 0x170 0x000 ALT4 0x0
+#define VF610_PAD_PTD13__DEBUG_OUT28            0x170 0x000 ALT7 0x0
+#define VF610_PAD_PTB23__GPIO_93                0x174 0x000 ALT0 0x0
+#define VF610_PAD_PTB23__SAI0_TX_BCLK           0x174 0x000 ALT1 0x0
+#define VF610_PAD_PTB23__UART1_TX               0x174 0x380 ALT2 0x2
+#define VF610_PAD_PTB23__SRC_RCON18             0x174 0x398 ALT3 0x1
+#define VF610_PAD_PTB23__FB_MUXED_ALE           0x174 0x000 ALT4 0x0
+#define VF610_PAD_PTB23__FB_TS_B                0x174 0x000 ALT5 0x0
+#define VF610_PAD_PTB23__UART3_RTS              0x174 0x000 ALT6 0x0
+#define VF610_PAD_PTB23__DCU1_G3                0x174 0x000 ALT7 0x0
+#define VF610_PAD_PTB24__GPIO_94                0x178 0x000 ALT0 0x0
+#define VF610_PAD_PTB24__SAI0_RX_BCLK           0x178 0x000 ALT1 0x0
+#define VF610_PAD_PTB24__UART1_RX               0x178 0x37C ALT2 0x2
+#define VF610_PAD_PTB24__SRC_RCON19             0x178 0x39C ALT3 0x1
+#define VF610_PAD_PTB24__FB_MUXED_TSIZ0         0x178 0x000 ALT4 0x0
+#define VF610_PAD_PTB24__NF_WE_B                0x178 0x000 ALT5 0x0
+#define VF610_PAD_PTB24__UART3_CTS              0x178 0x000 ALT6 0x0
+#define VF610_PAD_PTB24__DCU1_G4                0x178 0x000 ALT7 0x0
+#define VF610_PAD_PTB25__GPIO_95                0x17C 0x000 ALT0 0x0
+#define VF610_PAD_PTB25__SAI0_RX_DATA           0x17C 0x000 ALT1 0x0
+#define VF610_PAD_PTB25__UART1_RTS              0x17C 0x000 ALT2 0x0
+#define VF610_PAD_PTB25__SRC_RCON20             0x17C 0x3A0 ALT3 0x1
+#define VF610_PAD_PTB25__FB_CS1_B               0x17C 0x000 ALT4 0x0
+#define VF610_PAD_PTB25__NF_CE0_B               0x17C 0x000 ALT5 0x0
+#define VF610_PAD_PTB25__DCU1_G5                0x17C 0x000 ALT7 0x0
+#define VF610_PAD_PTB26__GPIO_96                0x180 0x000 ALT0 0x0
+#define VF610_PAD_PTB26__SAI0_TX_DATA           0x180 0x000 ALT1 0x0
+#define VF610_PAD_PTB26__UART1_CTS              0x180 0x378 ALT2 0x2
+#define VF610_PAD_PTB26__SRC_RCON21             0x180 0x000 ALT3 0x0
+#define VF610_PAD_PTB26__FB_CS0_B               0x180 0x000 ALT4 0x0
+#define VF610_PAD_PTB26__NF_CE1_B               0x180 0x000 ALT5 0x0
+#define VF610_PAD_PTB26__DCU1_G6                0x180 0x000 ALT7 0x0
+#define VF610_PAD_PTB27__GPIO_97                0x184 0x000 ALT0 0x0
+#define VF610_PAD_PTB27__SAI0_RX_SYNC           0x184 0x000 ALT1 0x0
+#define VF610_PAD_PTB27__SRC_RCON22             0x184 0x000 ALT3 0x0
+#define VF610_PAD_PTB27__FB_OE_B                0x184 0x000 ALT4 0x0
+#define VF610_PAD_PTB27__FB_MUXED_TBST_B        0x184 0x000 ALT5 0x0
+#define VF610_PAD_PTB27__NF_RE_B                0x184 0x000 ALT6 0x0
+#define VF610_PAD_PTB27__DCU1_G7                0x184 0x000 ALT7 0x0
+#define VF610_PAD_PTB28__GPIO_98                0x188 0x000 ALT0 0x0
+#define VF610_PAD_PTB28__SAI0_TX_SYNC           0x188 0x000 ALT1 0x0
+#define VF610_PAD_PTB28__SRC_RCON23             0x188 0x000 ALT3 0x0
+#define VF610_PAD_PTB28__FB_RW_B                0x188 0x000 ALT4 0x0
+#define VF610_PAD_PTB28__DCU1_B6                0x188 0x000 ALT7 0x0
+#define VF610_PAD_PTC26__GPIO_99                0x18C 0x000 ALT0 0x0
+#define VF610_PAD_PTC26__SAI1_TX_BCLK           0x18C 0x000 ALT1 0x0
+#define VF610_PAD_PTC26__DSPI0_CS5              0x18C 0x000 ALT2 0x0
+#define VF610_PAD_PTC26__SRC_RCON24             0x18C 0x000 ALT3 0x0
+#define VF610_PAD_PTC26__FB_TA_B                0x18C 0x000 ALT4 0x0
+#define VF610_PAD_PTC26__NF_RB_B                0x18C 0x000 ALT5 0x0
+#define VF610_PAD_PTC26__DCU1_B7                0x18C 0x000 ALT7 0x0
+#define VF610_PAD_PTC27__GPIO_100               0x190 0x000 ALT0 0x0
+#define VF610_PAD_PTC27__SAI1_RX_BCLK           0x190 0x000 ALT1 0x0
+#define VF610_PAD_PTC27__DSPI0_CS4              0x190 0x000 ALT2 0x0
+#define VF610_PAD_PTC27__SRC_RCON25             0x190 0x000 ALT3 0x0
+#define VF610_PAD_PTC27__FB_BE3_B               0x190 0x000 ALT4 0x0
+#define VF610_PAD_PTC27__FB_CS3_B               0x190 0x000 ALT5 0x0
+#define VF610_PAD_PTC27__NF_ALE                 0x190 0x000 ALT6 0x0
+#define VF610_PAD_PTC27__DCU1_B2                0x190 0x000 ALT7 0x0
+#define VF610_PAD_PTC28__GPIO_101               0x194 0x000 ALT0 0x0
+#define VF610_PAD_PTC28__SAI1_RX_DATA           0x194 0x000 ALT1 0x0
+#define VF610_PAD_PTC28__DSPI0_CS3              0x194 0x000 ALT2 0x0
+#define VF610_PAD_PTC28__SRC_RCON26             0x194 0x000 ALT3 0x0
+#define VF610_PAD_PTC28__FB_BE2_B               0x194 0x000 ALT4 0x0
+#define VF610_PAD_PTC28__FB_CS2_B               0x194 0x000 ALT5 0x0
+#define VF610_PAD_PTC28__NF_CLE                 0x194 0x000 ALT6 0x0
+#define VF610_PAD_PTC28__DCU1_B3                0x194 0x000 ALT7 0x0
+#define VF610_PAD_PTC29__GPIO_102               0x198 0x000 ALT0 0x0
+#define VF610_PAD_PTC29__SAI1_TX_DATA           0x198 0x000 ALT1 0x0
+#define VF610_PAD_PTC29__DSPI0_CS2              0x198 0x000 ALT2 0x0
+#define VF610_PAD_PTC29__SRC_RCON27             0x198 0x000 ALT3 0x0
+#define VF610_PAD_PTC29__FB_BE1_B               0x198 0x000 ALT4 0x0
+#define VF610_PAD_PTC29__FB_MUXED_TSIZE1        0x198 0x000 ALT5 0x0
+#define VF610_PAD_PTC29__DCU1_B4                0x198 0x000 ALT7 0x0
+#define VF610_PAD_PTC30__GPIO_103               0x19C 0x000 ALT0 0x0
+#define VF610_PAD_PTC30__SAI1_RX_SYNC           0x19C 0x000 ALT1 0x0
+#define VF610_PAD_PTC30__DSPI1_CS2              0x19C 0x000 ALT2 0x0
+#define VF610_PAD_PTC30__SRC_RCON28             0x19C 0x000 ALT3 0x0
+#define VF610_PAD_PTC30__FB_MUXED_BE0_B         0x19C 0x000 ALT4 0x0
+#define VF610_PAD_PTC30__FB_TSIZ0               0x19C 0x000 ALT5 0x0
+#define VF610_PAD_PTC30__ADC0_SE5               0x19C 0x000 ALT6 0x0
+#define VF610_PAD_PTC30__DCU1_B5                0x19C 0x000 ALT7 0x0
+#define VF610_PAD_PTC31__GPIO_104               0x1A0 0x000 ALT0 0x0
+#define VF610_PAD_PTC31__SAI1_TX_SYNC           0x1A0 0x360 ALT1 0x1
+#define VF610_PAD_PTC31__SRC_RCON29             0x1A0 0x000 ALT3 0x0
+#define VF610_PAD_PTC31__ADC1_SE5               0x1A0 0x000 ALT6 0x0
+#define VF610_PAD_PTC31__DCU1_B6                0x1A0 0x000 ALT7 0x0
+#define VF610_PAD_PTE0__GPIO_105                0x1A4 0x000 ALT0 0x0
+#define VF610_PAD_PTE0__DCU0_HSYNC              0x1A4 0x000 ALT1 0x0
+#define VF610_PAD_PTE0__SRC_BMODE1              0x1A4 0x000 ALT2 0x0
+#define VF610_PAD_PTE0__LCD0                    0x1A4 0x000 ALT4 0x0
+#define VF610_PAD_PTE0__DEBUG_OUT29             0x1A4 0x000 ALT7 0x0
+#define VF610_PAD_PTE1__GPIO_106                0x1A8 0x000 ALT0 0x0
+#define VF610_PAD_PTE1__DCU0_VSYNC              0x1A8 0x000 ALT1 0x0
+#define VF610_PAD_PTE1__SRC_BMODE0              0x1A8 0x000 ALT2 0x0
+#define VF610_PAD_PTE1__LCD1                    0x1A8 0x000 ALT4 0x0
+#define VF610_PAD_PTE1__DEBUG_OUT30             0x1A8 0x000 ALT7 0x0
+#define VF610_PAD_PTE2__GPIO_107                0x1AC 0x000 ALT0 0x0
+#define VF610_PAD_PTE2__DCU0_PCLK               0x1AC 0x000 ALT1 0x0
+#define VF610_PAD_PTE2__LCD2                    0x1AC 0x000 ALT4 0x0
+#define VF610_PAD_PTE2__DEBUG_OUT31             0x1AC 0x000 ALT7 0x0
+#define VF610_PAD_PTE3__GPIO_108                0x1B0 0x000 ALT0 0x0
+#define VF610_PAD_PTE3__DCU0_TAG                0x1B0 0x000 ALT1 0x0
+#define VF610_PAD_PTE3__LCD3                    0x1B0 0x000 ALT4 0x0
+#define VF610_PAD_PTE3__DEBUG_OUT32             0x1B0 0x000 ALT7 0x0
+#define VF610_PAD_PTE4__GPIO_109                0x1B4 0x000 ALT0 0x0
+#define VF610_PAD_PTE4__DCU0_DE                 0x1B4 0x000 ALT1 0x0
+#define VF610_PAD_PTE4__LCD4                    0x1B4 0x000 ALT4 0x0
+#define VF610_PAD_PTE4__DEBUG_OUT33             0x1B4 0x000 ALT7 0x0
+#define VF610_PAD_PTE5__GPIO_110                0x1B8 0x000 ALT0 0x0
+#define VF610_PAD_PTE5__DCU0_R0                 0x1B8 0x000 ALT1 0x0
+#define VF610_PAD_PTE5__LCD5                    0x1B8 0x000 ALT4 0x0
+#define VF610_PAD_PTE5__DEBUG_OUT34             0x1B8 0x000 ALT7 0x0
+#define VF610_PAD_PTE6__GPIO_111                0x1BC 0x000 ALT0 0x0
+#define VF610_PAD_PTE6__DCU0_R1                 0x1BC 0x000 ALT1 0x0
+#define VF610_PAD_PTE6__LCD6                    0x1BC 0x000 ALT4 0x0
+#define VF610_PAD_PTE6__DEBUG_OUT35             0x1BC 0x000 ALT7 0x0
+#define VF610_PAD_PTE7__GPIO_112                0x1C0 0x000 ALT0 0x0
+#define VF610_PAD_PTE7__DCU0_R2                 0x1C0 0x000 ALT1 0x0
+#define VF610_PAD_PTE7__SRC_RCON0               0x1C0 0x000 ALT3 0x0
+#define VF610_PAD_PTE7__LCD7                    0x1C0 0x000 ALT4 0x0
+#define VF610_PAD_PTE7__DEBUG_OUT36             0x1C0 0x000 ALT7 0x0
+#define VF610_PAD_PTE8__GPIO_113                0x1C4 0x000 ALT0 0x0
+#define VF610_PAD_PTE8__DCU0_R3                 0x1C4 0x000 ALT1 0x0
+#define VF610_PAD_PTE8__SRC_RCON1               0x1C4 0x000 ALT3 0x0
+#define VF610_PAD_PTE8__LCD8                    0x1C4 0x000 ALT4 0x0
+#define VF610_PAD_PTE8__DEBUG_OUT37             0x1C4 0x000 ALT7 0x0
+#define VF610_PAD_PTE9__GPIO_114                0x1C8 0x000 ALT0 0x0
+#define VF610_PAD_PTE9__DCU0_R4                 0x1C8 0x000 ALT1 0x0
+#define VF610_PAD_PTE9__SRC_RCON2               0x1C8 0x000 ALT3 0x0
+#define VF610_PAD_PTE9__LCD9                    0x1C8 0x000 ALT4 0x0
+#define VF610_PAD_PTE9__DEBUG_OUT38             0x1C8 0x000 ALT7 0x0
+#define VF610_PAD_PTE10__GPIO_115               0x1CC 0x000 ALT0 0x0
+#define VF610_PAD_PTE10__DCU0_R5                0x1CC 0x000 ALT1 0x0
+#define VF610_PAD_PTE10__SRC_RCON3              0x1CC 0x000 ALT3 0x0
+#define VF610_PAD_PTE10__LCD10                  0x1CC 0x000 ALT4 0x0
+#define VF610_PAD_PTE10__DEBUG_OUT39            0x1CC 0x000 ALT7 0x0
+#define VF610_PAD_PTE11__GPIO_116               0x1D0 0x000 ALT0 0x0
+#define VF610_PAD_PTE11__DCU0_R6                0x1D0 0x000 ALT1 0x0
+#define VF610_PAD_PTE11__SRC_RCON4              0x1D0 0x000 ALT3 0x0
+#define VF610_PAD_PTE11__LCD11                  0x1D0 0x000 ALT4 0x0
+#define VF610_PAD_PTE11__DEBUG_OUT40            0x1D0 0x000 ALT7 0x0
+#define VF610_PAD_PTE12__GPIO_117               0x1D4 0x000 ALT0 0x0
+#define VF610_PAD_PTE12__DCU0_R7                0x1D4 0x000 ALT1 0x0
+#define VF610_PAD_PTE12__DSPI1_CS3              0x1D4 0x000 ALT2 0x0
+#define VF610_PAD_PTE12__SRC_RCON5              0x1D4 0x000 ALT3 0x0
+#define VF610_PAD_PTE12__LCD12                  0x1D4 0x000 ALT4 0x0
+#define VF610_PAD_PTE12__LPT_ALT0               0x1D4 0x000 ALT7 0x0
+#define VF610_PAD_PTE13__GPIO_118               0x1D8 0x000 ALT0 0x0
+#define VF610_PAD_PTE13__DCU0_G0                0x1D8 0x000 ALT1 0x0
+#define VF610_PAD_PTE13__LCD13                  0x1D8 0x000 ALT4 0x0
+#define VF610_PAD_PTE13__DEBUG_OUT41            0x1D8 0x000 ALT7 0x0
+#define VF610_PAD_PTE14__GPIO_119               0x1DC 0x000 ALT0 0x0
+#define VF610_PAD_PTE14__DCU0_G1                0x1DC 0x000 ALT1 0x0
+#define VF610_PAD_PTE14__LCD14                  0x1DC 0x000 ALT4 0x0
+#define VF610_PAD_PTE14__DEBUG_OUT42            0x1DC 0x000 ALT7 0x0
+#define VF610_PAD_PTE15__GPIO_120               0x1E0 0x000 ALT0 0x0
+#define VF610_PAD_PTE15__DCU0_G2                0x1E0 0x000 ALT1 0x0
+#define VF610_PAD_PTE15__SRC_RCON6              0x1E0 0x000 ALT3 0x0
+#define VF610_PAD_PTE15__LCD15                  0x1E0 0x000 ALT4 0x0
+#define VF610_PAD_PTE15__DEBUG_OUT43            0x1E0 0x000 ALT7 0x0
+#define VF610_PAD_PTE16__GPIO_121               0x1E4 0x000 ALT0 0x0
+#define VF610_PAD_PTE16__DCU0_G3                0x1E4 0x000 ALT1 0x0
+#define VF610_PAD_PTE16__SRC_RCON7              0x1E4 0x000 ALT3 0x0
+#define VF610_PAD_PTE16__LCD16                  0x1E4 0x000 ALT4 0x0
+#define VF610_PAD_PTE17__GPIO_122               0x1E8 0x000 ALT0 0x0
+#define VF610_PAD_PTE17__DCU0_G4                0x1E8 0x000 ALT1 0x0
+#define VF610_PAD_PTE17__SRC_RCON8              0x1E8 0x000 ALT3 0x0
+#define VF610_PAD_PTE17__LCD17                  0x1E8 0x000 ALT4 0x0
+#define VF610_PAD_PTE18__GPIO_123               0x1EC 0x000 ALT0 0x0
+#define VF610_PAD_PTE18__DCU0_G5                0x1EC 0x000 ALT1 0x0
+#define VF610_PAD_PTE18__SRC_RCON9              0x1EC 0x000 ALT3 0x0
+#define VF610_PAD_PTE18__LCD18                  0x1EC 0x000 ALT4 0x0
+#define VF610_PAD_PTE19__GPIO_124               0x1F0 0x000 ALT0 0x0
+#define VF610_PAD_PTE19__DCU0_G6                0x1F0 0x000 ALT1 0x0
+#define VF610_PAD_PTE19__SRC_RCON10             0x1F0 0x000 ALT3 0x0
+#define VF610_PAD_PTE19__LCD19                  0x1F0 0x000 ALT4 0x0
+#define VF610_PAD_PTE19__I2C0_SCL               0x1F0 0x33C ALT5 0x3
+#define VF610_PAD_PTE20__GPIO_125               0x1F4 0x000 ALT0 0x0
+#define VF610_PAD_PTE20__DCU0_G7                0x1F4 0x000 ALT1 0x0
+#define VF610_PAD_PTE20__SRC_RCON11             0x1F4 0x000 ALT3 0x0
+#define VF610_PAD_PTE20__LCD20                  0x1F4 0x000 ALT4 0x0
+#define VF610_PAD_PTE20__I2C0_SDA               0x1F4 0x340 ALT5 0x3
+#define VF610_PAD_PTE20__EWM_IN                 0x1F4 0x000 ALT7 0x0
+#define VF610_PAD_PTE21__GPIO_126               0x1F8 0x000 ALT0 0x0
+#define VF610_PAD_PTE21__DCU0_B0                0x1F8 0x000 ALT1 0x0
+#define VF610_PAD_PTE21__LCD21                  0x1F8 0x000 ALT4 0x0
+#define VF610_PAD_PTE22__GPIO_127               0x1FC 0x000 ALT0 0x0
+#define VF610_PAD_PTE22__DCU0_B1                0x1FC 0x000 ALT1 0x0
+#define VF610_PAD_PTE22__LCD22                  0x1FC 0x000 ALT4 0x0
+#define VF610_PAD_PTE23__GPIO_128               0x200 0x000 ALT0 0x0
+#define VF610_PAD_PTE23__DCU0_B2                0x200 0x000 ALT1 0x0
+#define VF610_PAD_PTE23__SRC_RCON12             0x200 0x000 ALT3 0x0
+#define VF610_PAD_PTE23__LCD23                  0x200 0x000 ALT4 0x0
+#define VF610_PAD_PTE24__GPIO_129               0x204 0x000 ALT0 0x0
+#define VF610_PAD_PTE24__DCU0_B3                0x204 0x000 ALT1 0x0
+#define VF610_PAD_PTE24__SRC_RCON13             0x204 0x000 ALT3 0x0
+#define VF610_PAD_PTE24__LCD24                  0x204 0x000 ALT4 0x0
+#define VF610_PAD_PTE25__GPIO_130               0x208 0x000 ALT0 0x0
+#define VF610_PAD_PTE25__DCU0_B4                0x208 0x000 ALT1 0x0
+#define VF610_PAD_PTE25__SRC_RCON14             0x208 0x000 ALT3 0x0
+#define VF610_PAD_PTE25__LCD25                  0x208 0x000 ALT4 0x0
+#define VF610_PAD_PTE26__GPIO_131               0x20C 0x000 ALT0 0x0
+#define VF610_PAD_PTE26__DCU0_B5                0x20C 0x000 ALT1 0x0
+#define VF610_PAD_PTE26__SRC_RCON15             0x20C 0x000 ALT3 0x0
+#define VF610_PAD_PTE26__LCD26                  0x20C 0x000 ALT4 0x0
+#define VF610_PAD_PTE27__GPIO_132               0x210 0x000 ALT0 0x0
+#define VF610_PAD_PTE27__DCU0_B6                0x210 0x000 ALT1 0x0
+#define VF610_PAD_PTE27__SRC_RCON16             0x210 0x000 ALT3 0x0
+#define VF610_PAD_PTE27__LCD27                  0x210 0x000 ALT4 0x0
+#define VF610_PAD_PTE27__I2C1_SCL               0x210 0x344 ALT5 0x3
+#define VF610_PAD_PTE28__GPIO_133               0x214 0x000 ALT0 0x0
+#define VF610_PAD_PTE28__DCU0_B7                0x214 0x000 ALT1 0x0
+#define VF610_PAD_PTE28__SRC_RCON17             0x214 0x000 ALT3 0x0
+#define VF610_PAD_PTE28__LCD28                  0x214 0x000 ALT4 0x0
+#define VF610_PAD_PTE28__I2C1_SDA               0x214 0x348 ALT5 0x3
+#define VF610_PAD_PTE28__EWM_OUT                0x214 0x000 ALT7 0x0
+#define VF610_PAD_PTA7__GPIO_134                0x218 0x000 ALT0 0x0
+#define VF610_PAD_PTA7__VIU_PIX_CLK             0x218 0x3AC ALT1 0x1
+
+#endif
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
new file mode 100644
index 000000000000..b3905f5bcaf9
--- /dev/null
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/dts-v1/;
+#include "vf610.dtsi"
+
+/ {
+        model = "VF610 Tower Board";
+        compatible = "fsl,vf610-twr", "fsl,vf610";
+
+        chosen {
+                bootargs = "console=ttyLP1,115200";
+        };
+
+        memory {
+                reg = <0x80000000 0x8000000>;
+        };
+
+        clocks {
+                audio_ext {
+                        compatible = "fixed-clock";
+                        clock-frequency = <24576000>;
+                };
+
+                enet_ext {
+                        compatible = "fixed-clock";
+                        clock-frequency = <50000000>;
+                };
+        };
+
+};
+
+&fec0 {
+        phy-mode = "rmii";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec0_1>;
+        status = "okay";
+};
+
+&fec1 {
+        phy-mode = "rmii";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec1_1>;
+        status = "okay";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1_1>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
new file mode 100644
index 000000000000..e1eb7dadda80
--- /dev/null
+++ b/arch/arm/boot/dts/vf610.dtsi
@@ -0,0 +1,464 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "skeleton.dtsi"
+#include "vf610-pinfunc.h"
+#include <dt-bindings/clock/vf610-clock.h>
+
+/ {
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+                serial4 = &uart4;
+                serial5 = &uart5;
+                gpio0 = &gpio1;
+                gpio1 = &gpio2;
+                gpio2 = &gpio3;
+                gpio3 = &gpio4;
+                gpio4 = &gpio5;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        compatible = "arm,cortex-a5";
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        next-level-cache = <&L2>;
+                };
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                sxosc {
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+
+                fxosc {
+                        compatible = "fixed-clock";
+                        clock-frequency = <24000000>;
+                };
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&intc>;
+                ranges;
+
+                aips0: aips-bus@40000000 {
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        interrupt-parent = <&intc>;
+                        reg = <0x40000000 0x70000>;
+                        ranges;
+
+                        intc: interrupt-controller@40002000 {
+                                compatible = "arm,cortex-a9-gic";
+                                #interrupt-cells = <3>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                interrupt-controller;
+                                reg = <0x40003000 0x1000>,
+                                      <0x40002100 0x100>;
+                        };
+
+                        L2: l2-cache@40006000 {
+                                compatible = "arm,pl310-cache";
+                                reg = <0x40006000 0x1000>;
+                                cache-unified;
+                                cache-level = <2>;
+                                arm,data-latency = <1 1 1>;
+                                arm,tag-latency = <2 2 2>;
+                        };
+
+                        uart0: serial@40027000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x40027000 0x1000>;
+                                interrupts = <0 61 0x00>;
+                                clocks = <&clks VF610_CLK_UART0>;
+                                clock-names = "ipg";
+                                status = "disabled";
+                        };
+
+                        uart1: serial@40028000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x40028000 0x1000>;
+                                interrupts = <0 62 0x04>;
+                                clocks = <&clks VF610_CLK_UART1>;
+                                clock-names = "ipg";
+                                status = "disabled";
+                        };
+
+                        uart2: serial@40029000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x40029000 0x1000>;
+                                interrupts = <0 63 0x04>;
+                                clocks = <&clks VF610_CLK_UART2>;
+                                clock-names = "ipg";
+                                status = "disabled";
+                        };
+
+                        uart3: serial@4002a000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x4002a000 0x1000>;
+                                interrupts = <0 64 0x04>;
+                                clocks = <&clks VF610_CLK_UART3>;
+                                clock-names = "ipg";
+                                status = "disabled";
+                        };
+
+                        sai2: sai@40031000 {
+                                compatible = "fsl,vf610-sai";
+                                reg = <0x40031000 0x1000>;
+                                interrupts = <0 86 0x04>;
+                                clocks = <&clks VF610_CLK_SAI2>;
+                                clock-names = "sai";
+                                status = "disabled";
+                        };
+
+                        pit: pit@40037000 {
+                                compatible = "fsl,vf610-pit";
+                                reg = <0x40037000 0x1000>;
+                                interrupts = <0 39 0x04>;
+                                clocks = <&clks VF610_CLK_PIT>;
+                                clock-names = "pit";
+                        };
+
+                        wdog@4003e000 {
+                                compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
+                                reg = <0x4003e000 0x1000>;
+                                clocks = <&clks VF610_CLK_WDT>;
+                                clock-names = "wdog";
+                        };
+
+                        qspi0: quadspi@40044000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,vf610-qspi";
+                                reg = <0x40044000 0x1000>;
+                                interrupts = <0 24 0x04>;
+                                clocks = <&clks VF610_CLK_QSPI0_EN>,
+                                        <&clks VF610_CLK_QSPI0>;
+                                clock-names = "qspi_en", "qspi";
+                                status = "disabled";
+                        };
+
+                        iomuxc: iomuxc@40048000 {
+                                compatible = "fsl,vf610-iomuxc";
+                                reg = <0x40048000 0x1000>;
+                                #gpio-range-cells = <3>;
+
+                                /* functions and groups pins */
+
+                                dcu0 {
+                                        pinctrl_dcu0_1: dcu0grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTB8__GPIO_30         0x42
+                                                VF610_PAD_PTE0__DCU0_HSYNC      0x42
+                                                VF610_PAD_PTE1__DCU0_VSYNC      0x42
+                                                VF610_PAD_PTE2__DCU0_PCLK       0x42
+                                                VF610_PAD_PTE4__DCU0_DE         0x42
+                                                VF610_PAD_PTE5__DCU0_R0         0x42
+                                                VF610_PAD_PTE6__DCU0_R1         0x42
+                                                VF610_PAD_PTE7__DCU0_R2         0x42
+                                                VF610_PAD_PTE8__DCU0_R3         0x42
+                                                VF610_PAD_PTE9__DCU0_R4         0x42
+                                                VF610_PAD_PTE10__DCU0_R5        0x42
+                                                VF610_PAD_PTE11__DCU0_R6        0x42
+                                                VF610_PAD_PTE12__DCU0_R7        0x42
+                                                VF610_PAD_PTE13__DCU0_G0        0x42
+                                                VF610_PAD_PTE14__DCU0_G1        0x42
+                                                VF610_PAD_PTE15__DCU0_G2        0x42
+                                                VF610_PAD_PTE16__DCU0_G3        0x42
+                                                VF610_PAD_PTE17__DCU0_G4        0x42
+                                                VF610_PAD_PTE18__DCU0_G5        0x42
+                                                VF610_PAD_PTE19__DCU0_G6        0x42
+                                                VF610_PAD_PTE20__DCU0_G7        0x42
+                                                VF610_PAD_PTE21__DCU0_B0        0x42
+                                                VF610_PAD_PTE22__DCU0_B1        0x42
+                                                VF610_PAD_PTE23__DCU0_B2        0x42
+                                                VF610_PAD_PTE24__DCU0_B3        0x42
+                                                VF610_PAD_PTE25__DCU0_B4        0x42
+                                                VF610_PAD_PTE26__DCU0_B5        0x42
+                                                VF610_PAD_PTE27__DCU0_B6        0x42
+                                                VF610_PAD_PTE28__DCU0_B7        0x42
+                                                >;
+                                        };
+                                };
+
+                                dspi0 {
+                                        pinctrl_dspi0_1: dspi0grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTB19__DSPI0_CS0      0x1182
+                                                VF610_PAD_PTB20__DSPI0_SIN      0x1181
+                                                VF610_PAD_PTB21__DSPI0_SOUT     0x1182
+                                                VF610_PAD_PTB22__DSPI0_SCK      0x1182
+                                                >;
+                                        };
+                                };
+
+                                esdhc1 {
+                                        pinctrl_esdhc1_1: esdhc1grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTA24__ESDHC1_CLK     0x31ef
+                                                VF610_PAD_PTA25__ESDHC1_CMD     0x31ef
+                                                VF610_PAD_PTA26__ESDHC1_DAT0    0x31ef
+                                                VF610_PAD_PTA27__ESDHC1_DAT1    0x31ef
+                                                VF610_PAD_PTA28__ESDHC1_DATA2   0x31ef
+                                                VF610_PAD_PTA29__ESDHC1_DAT3    0x31ef
+                                                VF610_PAD_PTA7__GPIO_134        0x219d
+                                                >;
+                                        };
+                                };
+
+                                fec0 {
+                                        pinctrl_fec0_1: fec0grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTA6__RMII_CLKIN      0x30d1
+                                                VF610_PAD_PTC0__ENET_RMII0_MDC  0x30d3
+                                                VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1
+                                                VF610_PAD_PTC2__ENET_RMII0_CRS  0x30d1
+                                                VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
+                                                VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
+                                                VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
+                                                VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
+                                                VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
+                                                VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
+                                                >;
+                                        };
+                                };
+
+                                fec1 {
+                                        pinctrl_fec1_1: fec1grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
+                                                VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
+                                                VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
+                                                VF610_PAD_PTC12__ENET_RMII_RXD1         0x30d1
+                                                VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
+                                                VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
+                                                VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
+                                                VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
+                                                VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
+                                                >;
+                                        };
+                                };
+
+                                i2c0 {
+                                        pinctrl_i2c0_1: i2c0grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTB14__I2C0_SCL       0x30d3
+                                                VF610_PAD_PTB15__I2C0_SDA       0x30d3
+                                                >;
+                                        };
+                                };
+
+                                pwm0 {
+                                        pinctrl_pwm0_1: pwm0grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTB0__FTM0_CH0        0x1582
+                                                VF610_PAD_PTB1__FTM0_CH1        0x1582
+                                                VF610_PAD_PTB2__FTM0_CH2        0x1582
+                                                VF610_PAD_PTB3__FTM0_CH3        0x1582
+                                                VF610_PAD_PTB6__FTM0_CH6        0x1582
+                                                VF610_PAD_PTB7__FTM0_CH7        0x1582
+                                                >;
+                                        };
+                                };
+
+                                qspi0 {
+                                        pinctrl_qspi0_1: qspi0grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTD0__QSPI0_A_QSCK    0x307b
+                                                VF610_PAD_PTD1__QSPI0_A_CS0     0x307f
+                                                VF610_PAD_PTD2__QSPI0_A_DATA3   0x3073
+                                                VF610_PAD_PTD3__QSPI0_A_DATA2   0x3073
+                                                VF610_PAD_PTD4__QSPI0_A_DATA1   0x3073
+                                                VF610_PAD_PTD5__QSPI0_A_DATA0   0x307b
+                                                VF610_PAD_PTD7__QSPI0_B_QSCK    0x307b
+                                                VF610_PAD_PTD8__QSPI0_B_CS0     0x307f
+                                                VF610_PAD_PTD9__QSPI0_B_DATA3   0x3073
+                                                VF610_PAD_PTD10__QSPI0_B_DATA2  0x3073
+                                                VF610_PAD_PTD11__QSPI0_B_DATA1  0x3073
+                                                VF610_PAD_PTD12__QSPI0_B_DATA0  0x307b
+                                                >;
+                                        };
+                                };
+
+                                sai2 {
+                                        pinctrl_sai2_1: sai2grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTA16__SAI2_TX_BCLK   0x02ed
+                                                VF610_PAD_PTA18__SAI2_TX_DATA   0x02ee
+                                                VF610_PAD_PTA19__SAI2_TX_SYNC   0x02ed
+                                                VF610_PAD_PTA21__SAI2_RX_BCLK   0x02ed
+                                                VF610_PAD_PTA22__SAI2_RX_DATA   0x02ed
+                                                VF610_PAD_PTA23__SAI2_RX_SYNC   0x02ed
+                                                VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed
+                                                >;
+                                        };
+                                };
+
+                                uart1 {
+                                        pinctrl_uart1_1: uart1grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTB4__UART1_TX        0x21a2
+                                                VF610_PAD_PTB5__UART1_RX        0x21a1
+                                                >;
+                                        };
+                                };
+
+                                usbvbus {
+                                        pinctrl_usbvbus_1: usbvbusgrp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTA24__USB1_VBUS_EN   0x219c
+                                                VF610_PAD_PTA16__USB0_VBUS_EN   0x219c
+                                                >;
+                                        };
+                                };
+
+                        };
+
+                        gpio1: gpio@40049000 {
+                                compatible = "fsl,vf610-gpio";
+                                reg = <0x40049000 0x1000 0x400ff000 0x40>;
+                                interrupts = <0 107 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 0 32>;
+                        };
+
+                        gpio2: gpio@4004a000 {
+                                compatible = "fsl,vf610-gpio";
+                                reg = <0x4004a000 0x1000 0x400ff040 0x40>;
+                                interrupts = <0 108 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 32 32>;
+                        };
+
+                        gpio3: gpio@4004b000 {
+                                compatible = "fsl,vf610-gpio";
+                                reg = <0x4004b000 0x1000 0x400ff080 0x40>;
+                                interrupts = <0 109 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 64 32>;
+                        };
+
+                        gpio4: gpio@4004c000 {
+                                compatible = "fsl,vf610-gpio";
+                                reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
+                                interrupts = <0 110 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 96 32>;
+                        };
+
+                        gpio5: gpio@4004d000 {
+                                compatible = "fsl,vf610-gpio";
+                                reg = <0x4004d000 0x1000 0x400ff100 0x40>;
+                                interrupts = <0 111 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 128 7>;
+                        };
+
+                        anatop@40050000 {
+                                compatible = "fsl,vf610-anatop";
+                                reg = <0x40050000 0x1000>;
+                        };
+
+                        i2c0: i2c@40066000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,vf610-i2c";
+                                reg = <0x40066000 0x1000>;
+                                interrupts =<0 71 0x04>;
+                                clocks = <&clks VF610_CLK_I2C0>;
+                                clock-names = "ipg";
+                                status = "disabled";
+                        };
+
+                        clks: ccm@4006b000 {
+                                compatible = "fsl,vf610-ccm";
+                                reg = <0x4006b000 0x1000>;
+                                #clock-cells = <1>;
+                        };
+                };
+
+                aips1: aips-bus@40080000 {
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x40080000 0x80000>;
+                        ranges;
+
+                        uart4: serial@400a9000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x400a9000 0x1000>;
+                                interrupts = <0 65 0x04>;
+                                clocks = <&clks VF610_CLK_UART4>;
+                                clock-names = "ipg";
+                                status = "disabled";
+                        };
+
+                        uart5: serial@400aa000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x400aa000 0x1000>;
+                                interrupts = <0 66 0x04>;
+                                clocks = <&clks VF610_CLK_UART5>;
+                                clock-names = "ipg";
+                                status = "disabled";
+                        };
+
+                        fec0: ethernet@400d0000 {
+                                compatible = "fsl,mvf600-fec";
+                                reg = <0x400d0000 0x1000>;
+                                interrupts = <0 78 0x04>;
+                                clocks = <&clks VF610_CLK_ENET>,
+                                        <&clks VF610_CLK_ENET>,
+                                        <&clks VF610_CLK_ENET>;
+                                clock-names = "ipg", "ahb", "ptp";
+                                status = "disabled";
+                        };
+
+                        fec1: ethernet@400d1000 {
+                                compatible = "fsl,mvf600-fec";
+                                reg = <0x400d1000 0x1000>;
+                                interrupts = <0 79 0x04>;
+                                clocks = <&clks VF610_CLK_ENET>,
+                                        <&clks VF610_CLK_ENET>,
+                                        <&clks VF610_CLK_ENET>;
+                                clock-names = "ipg", "ahb", "ptp";
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/vt8500-bv07.dts b/arch/arm/boot/dts/vt8500-bv07.dts
index 877b33afa7ed..87f33310e2bc 100644
--- a/arch/arm/boot/dts/vt8500-bv07.dts
+++ b/arch/arm/boot/dts/vt8500-bv07.dts
@@ -30,3 +30,7 @@
                 };
         };
 };
+
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi
index 4a4b96f6827e..51d0e912c8f5 100644
--- a/arch/arm/boot/dts/vt8500.dtsi
+++ b/arch/arm/boot/dts/vt8500.dtsi
@@ -11,6 +11,23 @@
 / {
         compatible = "via,vt8500";
 
+        cpus {
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        device_type = "cpu";
+                        compatible = "arm,arm926ej-s";
+                };
+        };
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+        };
+
         soc {
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -111,32 +128,36 @@
                         reg = <0xd8050400 0x100>;
                 };
 
-                uart@d8200000 {
+                uart0: serial@d8200000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd8200000 0x1040>;
                         interrupts = <32>;
                         clocks = <&clkuart0>;
+                        status = "disabled";
                 };
 
-                uart@d82b0000 {
+                uart1: serial@d82b0000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd82b0000 0x1040>;
                         interrupts = <33>;
                         clocks = <&clkuart1>;
+                        status = "disabled";
                 };
 
-                uart@d8210000 {
+                uart2: serial@d8210000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd8210000 0x1040>;
                         interrupts = <47>;
                         clocks = <&clkuart2>;
+                        status = "disabled";
                 };
 
-                uart@d82c0000 {
+                uart3: serial@d82c0000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd82c0000 0x1040>;
                         interrupts = <50>;
                         clocks = <&clkuart3>;
+                        status = "disabled";
                 };
 
                 rtc@d8100000 {
diff --git a/arch/arm/boot/dts/wm8505-ref.dts b/arch/arm/boot/dts/wm8505-ref.dts
index edd2cec3d37f..e3e6b9eb09d0 100644
--- a/arch/arm/boot/dts/wm8505-ref.dts
+++ b/arch/arm/boot/dts/wm8505-ref.dts
@@ -30,3 +30,7 @@
                 };
         };
 };
+
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi
index b2bf359e852f..a1a854b8a454 100644
--- a/arch/arm/boot/dts/wm8505.dtsi
+++ b/arch/arm/boot/dts/wm8505.dtsi
@@ -12,11 +12,24 @@
         compatible = "wm,wm8505";
 
         cpus {
-                cpu@0 {
-                        compatible = "arm,arm926ejs";
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        device_type = "cpu";
+                        compatible = "arm,arm926ej-s";
                 };
         };
 
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+                serial4 = &uart4;
+                serial5 = &uart5;
+        };
+
         soc {
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -68,6 +81,13 @@
                                         clock-frequency = <25000000>;
                                 };
 
+                                plla: plla {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x200>;
+                                };
+
                                 pllb: pllb {
                                         #clock-cells = <0>;
                                         compatible = "via,vt8500-pll-clock";
@@ -75,6 +95,48 @@
                                         reg = <0x204>;
                                 };
 
+                                pllc: pllc {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x208>;
+                                };
+
+                                plld: plld {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x20c>;
+                                };
+
+                                clkarm: arm {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plla>;
+                                        divisor-reg = <0x300>;
+                                };
+
+                                clkahb: ahb {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x304>;
+                                };
+
+                                clkapb: apb {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x350>;
+                                };
+
+                                clkddr: ddr {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plld>;
+                                        divisor-reg = <0x310>;
+                                };
+
                                 clkuart0: uart0 {
                                         #clock-cells = <0>;
                                         compatible = "via,vt8500-device-clock";
@@ -163,46 +225,52 @@
                         reg = <0xd8050400 0x100>;
                 };
 
-                uart@d8200000 {
+                uart0: serial@d8200000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd8200000 0x1040>;
                         interrupts = <32>;
                         clocks = <&clkuart0>;
+                        status = "disabled";
                 };
 
-                uart@d82b0000 {
+                uart1: serial@d82b0000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd82b0000 0x1040>;
                         interrupts = <33>;
                         clocks = <&clkuart1>;
+                        status = "disabled";
                 };
 
-                uart@d8210000 {
+                uart2: serial@d8210000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd8210000 0x1040>;
                         interrupts = <47>;
                         clocks = <&clkuart2>;
+                        status = "disabled";
                 };
 
-                uart@d82c0000 {
+                uart3: serial@d82c0000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd82c0000 0x1040>;
                         interrupts = <50>;
                         clocks = <&clkuart3>;
+                        status = "disabled";
                 };
 
-                uart@d8370000 {
+                uart4: serial@d8370000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd8370000 0x1040>;
                         interrupts = <31>;
                         clocks = <&clkuart4>;
+                        status = "disabled";
                 };
 
-                uart@d8380000 {
+                uart5: serial@d8380000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd8380000 0x1040>;
                         interrupts = <30>;
                         clocks = <&clkuart5>;
+                        status = "disabled";
                 };
 
                 rtc@d8100000 {
diff --git a/arch/arm/boot/dts/wm8650-mid.dts b/arch/arm/boot/dts/wm8650-mid.dts
index 61671a0d9ede..dd0d1b602388 100644
--- a/arch/arm/boot/dts/wm8650-mid.dts
+++ b/arch/arm/boot/dts/wm8650-mid.dts
@@ -32,3 +32,6 @@
         };
 };
 
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi
index dd8464eeb40d..7525982262ac 100644
--- a/arch/arm/boot/dts/wm8650.dtsi
+++ b/arch/arm/boot/dts/wm8650.dtsi
@@ -11,6 +11,21 @@
 / {
         compatible = "wm,wm8650";
 
+        cpus {
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        device_type = "cpu";
+                        compatible = "arm,arm926ej-s";
+                };
+        };
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+        };
+
         soc {
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -77,6 +92,55 @@
                                         reg = <0x204>;
                                 };
 
+                                pllc: pllc {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8650-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x208>;
+                                };
+
+                                plld: plld {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8650-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x20c>;
+                                };
+
+                                plle: plle {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8650-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x210>;
+                                };
+
+                                clkarm: arm {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plla>;
+                                        divisor-reg = <0x300>;
+                                };
+
+                                clkahb: ahb {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x304>;
+                                };
+
+                                clkapb: apb {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x320>;
+                                };
+
+                                clkddr: ddr {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plld>;
+                                        divisor-reg = <0x310>;
+                                };
+
                                 clkuart0: uart0 {
                                         #clock-cells = <0>;
                                         compatible = "via,vt8500-device-clock";
@@ -93,14 +157,7 @@
                                         enable-bit = <2>;
                                 };
 
-                                arm: arm {
-                                        #clock-cells = <0>;
-                                        compatible = "via,vt8500-device-clock";
-                                        clocks = <&plla>;
-                                        divisor-reg = <0x300>;
-                                };
-
-                                sdhc: sdhc {
+                                clksdhc: sdhc {
                                         #clock-cells = <0>;
                                         compatible = "via,vt8500-device-clock";
                                         clocks = <&pllb>;
@@ -140,18 +197,20 @@
                         reg = <0xd8050400 0x100>;
                 };
 
-                uart@d8200000 {
+                uart0: serial@d8200000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd8200000 0x1040>;
                         interrupts = <32>;
                         clocks = <&clkuart0>;
+                        status = "disabled";
                 };
 
-                uart@d82b0000 {
+                uart1: serial@d82b0000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd82b0000 0x1040>;
                         interrupts = <33>;
                         clocks = <&clkuart1>;
+                        status = "disabled";
                 };
 
                 rtc@d8100000 {
diff --git a/arch/arm/boot/dts/wm8750-apc8750.dts b/arch/arm/boot/dts/wm8750-apc8750.dts
new file mode 100644
index 000000000000..37e4a408bf39
--- /dev/null
+++ b/arch/arm/boot/dts/wm8750-apc8750.dts
@@ -0,0 +1,30 @@
+/*
+ * wm8750-apc8750.dts
+ *  - Device tree file for VIA APC8750
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+/include/ "wm8750.dtsi"
+
+/ {
+        model = "VIA APC8750";
+};
+
+&pinctrl {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c>;
+
+        i2c: i2c {
+                wm,pins = <168 169 170 171>;
+                wm,function = <2>;      /* alt */
+                wm,pull = <2>;  /* pull-up */
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/wm8750.dtsi b/arch/arm/boot/dts/wm8750.dtsi
new file mode 100644
index 000000000000..557a9c2ace49
--- /dev/null
+++ b/arch/arm/boot/dts/wm8750.dtsi
@@ -0,0 +1,347 @@
+/*
+ * wm8750.dtsi - Device tree file for Wondermedia WM8750 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "wm,wm8750";
+
+        cpus {
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        device_type = "cpu";
+                        compatible = "arm,arm1176ej-s";
+                };
+        };
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+                serial4 = &uart4;
+                serial5 = &uart5;
+                i2c0 = &i2c_0;
+                i2c1 = &i2c_1;
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges;
+                interrupt-parent = <&intc0>;
+
+                intc0: interrupt-controller@d8140000 {
+                        compatible = "via,vt8500-intc";
+                        interrupt-controller;
+                        reg = <0xd8140000 0x10000>;
+                        #interrupt-cells = <1>;
+                };
+
+                /* Secondary IC cascaded to intc0 */
+                intc1: interrupt-controller@d8150000 {
+                        compatible = "via,vt8500-intc";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        reg = <0xD8150000 0x10000>;
+                        interrupts = <56 57 58 59 60 61 62 63>;
+                };
+
+                pinctrl: pinctrl@d8110000 {
+                        compatible = "wm,wm8750-pinctrl";
+                        reg = <0xd8110000 0x10000>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                pmc@d8130000 {
+                        compatible = "via,vt8500-pmc";
+                        reg = <0xd8130000 0x1000>;
+
+                        clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                ref24: ref24M {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <24000000>;
+                                };
+
+                                ref25: ref25M {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <25000000>;
+                                };
+
+                                plla: plla {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8750-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x200>;
+                                };
+
+                                pllb: pllb {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8750-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x204>;
+                                };
+
+                                pllc: pllc {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8750-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x208>;
+                                };
+
+                                plld: plld {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8750-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x20C>;
+                                };
+
+                                plle: plle {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8750-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x210>;
+                                };
+
+                                clkarm: arm {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plla>;
+                                        divisor-reg = <0x300>;
+                                };
+
+                                clkahb: ahb {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x304>;
+                                };
+
+                                clkapb: apb {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x320>;
+                                };
+
+                                clkddr: ddr {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plld>;
+                                        divisor-reg = <0x310>;
+                                };
+
+                                clkuart0: uart0 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <24>;
+                                };
+
+                                clkuart1: uart1 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <25>;
+                                };
+
+                                clkuart2: uart2 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <26>;
+                                };
+
+                                clkuart3: uart3 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <27>;
+                                };
+
+                                clkuart4: uart4 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <28>;
+                                };
+
+                                clkuart5: uart5 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <29>;
+                                };
+
+                                clkpwm: pwm {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x350>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <17>;
+                                };
+
+                                clksdhc: sdhc {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x330>;
+                                        divisor-mask = <0x3f>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <0>;
+                                };
+
+                                clki2c0: i2c0clk {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x3A0>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <8>;
+                                };
+
+                                clki2c1: i2c1clk {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x3A4>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <9>;
+                                };
+                        };
+                };
+
+                pwm: pwm@d8220000 {
+                        #pwm-cells = <3>;
+                        compatible = "via,vt8500-pwm";
+                        reg = <0xd8220000 0x100>;
+                        clocks = <&clkpwm>;
+                };
+
+                timer@d8130100 {
+                        compatible = "via,vt8500-timer";
+                        reg = <0xd8130100 0x28>;
+                        interrupts = <36>;
+                };
+
+                ehci@d8007900 {
+                        compatible = "via,vt8500-ehci";
+                        reg = <0xd8007900 0x200>;
+                        interrupts = <26>;
+                };
+
+                uhci@d8007b00 {
+                        compatible = "platform-uhci";
+                        reg = <0xd8007b00 0x200>;
+                        interrupts = <26>;
+                };
+
+                uhci@d8008d00 {
+                        compatible = "platform-uhci";
+                        reg = <0xd8008d00 0x200>;
+                        interrupts = <26>;
+                };
+
+                uart0: serial@d8200000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8200000 0x1040>;
+                        interrupts = <32>;
+                        clocks = <&clkuart0>;
+                        status = "disabled";
+                };
+
+                uart1: serial@d82b0000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd82b0000 0x1040>;
+                        interrupts = <33>;
+                        clocks = <&clkuart1>;
+                        status = "disabled";
+                };
+
+                uart2: serial@d8210000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8210000 0x1040>;
+                        interrupts = <47>;
+                        clocks = <&clkuart2>;
+                        status = "disabled";
+                };
+
+                uart3: serial@d82c0000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd82c0000 0x1040>;
+                        interrupts = <50>;
+                        clocks = <&clkuart3>;
+                        status = "disabled";
+                };
+
+                uart4: serial@d8370000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8370000 0x1040>;
+                        interrupts = <30>;
+                        clocks = <&clkuart4>;
+                        status = "disabled";
+                };
+
+                uart5: serial@d8380000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8380000 0x1040>;
+                        interrupts = <43>;
+                        clocks = <&clkuart5>;
+                        status = "disabled";
+                };
+
+                rtc@d8100000 {
+                        compatible = "via,vt8500-rtc";
+                        reg = <0xd8100000 0x10000>;
+                        interrupts = <48>;
+                };
+
+                sdhc@d800a000 {
+                        compatible = "wm,wm8505-sdhc";
+                        reg = <0xd800a000 0x1000>;
+                        interrupts = <20 21>;
+                        clocks = <&clksdhc>;
+                        bus-width = <4>;
+                        sdon-inverted;
+                };
+
+                i2c_0: i2c@d8280000 {
+                        compatible = "wm,wm8505-i2c";
+                        reg = <0xd8280000 0x1000>;
+                        interrupts = <19>;
+                        clocks = <&clki2c0>;
+                        clock-frequency = <400000>;
+                };
+
+                i2c_1: i2c@d8320000 {
+                        compatible = "wm,wm8505-i2c";
+                        reg = <0xd8320000 0x1000>;
+                        interrupts = <18>;
+                        clocks = <&clki2c1>;
+                        clock-frequency = <400000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/wm8850-w70v2.dts b/arch/arm/boot/dts/wm8850-w70v2.dts
index 32d22532cd6c..90e913fb64be 100644
--- a/arch/arm/boot/dts/wm8850-w70v2.dts
+++ b/arch/arm/boot/dts/wm8850-w70v2.dts
@@ -41,3 +41,7 @@
                 };
         };
 };
+
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi
index fc790d0aee66..d98386dd2882 100644
--- a/arch/arm/boot/dts/wm8850.dtsi
+++ b/arch/arm/boot/dts/wm8850.dtsi
@@ -11,6 +11,17 @@
 / {
         compatible = "wm,wm8850";
 
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0x0>;
+                };
+        };
+
         aliases {
                 serial0 = &uart0;
                 serial1 = &uart1;
@@ -72,18 +83,81 @@
 
                                 plla: plla {
                                         #clock-cells = <0>;
-                                        compatible = "wm,wm8750-pll-clock";
-                                        clocks = <&ref25>;
+                                        compatible = "wm,wm8850-pll-clock";
+                                        clocks = <&ref24>;
                                         reg = <0x200>;
                                 };
 
                                 pllb: pllb {
                                         #clock-cells = <0>;
-                                        compatible = "wm,wm8750-pll-clock";
-                                        clocks = <&ref25>;
+                                        compatible = "wm,wm8850-pll-clock";
+                                        clocks = <&ref24>;
                                         reg = <0x204>;
                                 };
 
+                                pllc: pllc {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8850-pll-clock";
+                                        clocks = <&ref24>;
+                                        reg = <0x208>;
+                                };
+
+                                plld: plld {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8850-pll-clock";
+                                        clocks = <&ref24>;
+                                        reg = <0x20c>;
+                                };
+
+                                plle: plle {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8850-pll-clock";
+                                        clocks = <&ref24>;
+                                        reg = <0x210>;
+                                };
+
+                                pllf: pllf {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8850-pll-clock";
+                                        clocks = <&ref24>;
+                                        reg = <0x214>;
+                                };
+
+                                pllg: pllg {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8850-pll-clock";
+                                        clocks = <&ref24>;
+                                        reg = <0x218>;
+                                };
+
+                                clkarm: arm {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plla>;
+                                        divisor-reg = <0x300>;
+                                };
+
+                                clkahb: ahb {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x304>;
+                                };
+
+                                clkapb: apb {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x320>;
+                                };
+
+                                clkddr: ddr {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plld>;
+                                        divisor-reg = <0x310>;
+                                };
+
                                 clkuart0: uart0 {
                                         #clock-cells = <0>;
                                         compatible = "via,vt8500-device-clock";
@@ -178,32 +252,36 @@
                         interrupts = <26>;
                 };
 
-                uart0: uart@d8200000 {
+                uart0: serial@d8200000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd8200000 0x1040>;
                         interrupts = <32>;
                         clocks = <&clkuart0>;
+                        status = "disabled";
                 };
 
-                uart1: uart@d82b0000 {
+                uart1: serial@d82b0000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd82b0000 0x1040>;
                         interrupts = <33>;
                         clocks = <&clkuart1>;
+                        status = "disabled";
                 };
 
-                uart2: uart@d8210000 {
+                uart2: serial@d8210000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd8210000 0x1040>;
                         interrupts = <47>;
                         clocks = <&clkuart2>;
+                        status = "disabled";
                 };
 
-                uart3: uart@d82c0000 {
+                uart3: serial@d82c0000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd82c0000 0x1040>;
                         interrupts = <50>;
                         clocks = <&clkuart3>;
+                        status = "disabled";
                 };
 
                 rtc@d8100000 {
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 0dbee2c23905..6f54a64850eb 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -49,6 +49,7 @@
 
                 uart0: uart@e0000000 {
                         compatible = "xlnx,xuartps";
+                        status = "disabled";
                         clocks = <&clkc 23>, <&clkc 40>;
                         clock-names = "ref_clk", "aper_clk";
                         reg = <0xE0000000 0x1000>;
@@ -57,6 +58,7 @@
 
                 uart1: uart@e0001000 {
                         compatible = "xlnx,xuartps";
+                        status = "disabled";
                         clocks = <&clkc 24>, <&clkc 41>;
                         clock-names = "ref_clk", "aper_clk";
                         reg = <0xE0001000 0x1000>;
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index e25a307438ad..21aea99a067b 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -24,7 +24,11 @@
         };
 
         chosen {
-                bootargs = "console=ttyPS1,115200 earlyprintk";
+                bootargs = "console=ttyPS0,115200 earlyprintk";
         };
 
 };
+
+&uart1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts
new file mode 100644
index 000000000000..79009e0b74b9
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-zc706.dts
@@ -0,0 +1,35 @@
+/*
+ *  Copyright (C) 2011 Xilinx
+ *  Copyright (C) 2012 National Instruments Corp.
+ *  Copyright (C) 2013 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+        model = "Zynq ZC706 Development Board";
+        compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
+
+        memory {
+                device_type = "memory";
+                reg = <0 0x40000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyPS0,115200 earlyprintk";
+        };
+
+};
+
+&uart1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts
new file mode 100644
index 000000000000..d6acf2b1cdf4
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-zed.dts
@@ -0,0 +1,35 @@
+/*
+ *  Copyright (C) 2011 Xilinx
+ *  Copyright (C) 2012 National Instruments Corp.
+ *  Copyright (C) 2013 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+        model = "Zynq Zed Development Board";
+        compatible = "xlnx,zynq-7000";
+
+        memory {
+                device_type = "memory";
+                reg = <0 0x20000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyPS0,115200 earlyprintk";
+        };
+
+};
+
+&uart1 {
+        status = "okay";
+};
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index a8800d361805..75fd842d4071 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -161,6 +161,7 @@ CONFIG_USB_ATMEL_USBA=y
 CONFIG_USB_G_SERIAL=y
 CONFIG_MMC=y
 CONFIG_MMC_ATMELMCI=y
+CONFIG_MMC_SPI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
@@ -169,6 +170,7 @@ CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_LEDS_TRIGGER_GPIO=y
 CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_RV3029C2=y
 CONFIG_RTC_DRV_AT91RM9200=y
 CONFIG_RTC_DRV_AT91SAM9=y
 CONFIG_DMADEVICES=y
diff --git a/arch/arm/configs/at91sam9260_9g20_defconfig b/arch/arm/configs/at91sam9260_9g20_defconfig
index f50c404f0d3f..69b6928d3d9d 100644
--- a/arch/arm/configs/at91sam9260_9g20_defconfig
+++ b/arch/arm/configs/at91sam9260_9g20_defconfig
@@ -15,7 +15,6 @@ CONFIG_MACH_AT91SAM9260EK=y
 CONFIG_MACH_CAM60=y
 CONFIG_MACH_SAM9_L9260=y
 CONFIG_MACH_AFEB9260=y
-CONFIG_MACH_USB_A9260=y
 CONFIG_MACH_QIL_A9260=y
 CONFIG_MACH_CPU9260=y
 CONFIG_MACH_FLEXIBITY=y
diff --git a/arch/arm/configs/at91sam9263_defconfig b/arch/arm/configs/at91sam9263_defconfig
index 9d72ab684829..e40026364e57 100644
--- a/arch/arm/configs/at91sam9263_defconfig
+++ b/arch/arm/configs/at91sam9263_defconfig
@@ -15,7 +15,6 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9263=y
 CONFIG_MACH_AT91SAM9263EK=y
-CONFIG_MACH_USB_A9263=y
 CONFIG_MTD_AT91_DATAFLASH_CARD=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_AEABI=y
diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig
index b01e7632ed2e..35f8cf299fa2 100644
--- a/arch/arm/configs/nhk8815_defconfig
+++ b/arch/arm/configs/nhk8815_defconfig
@@ -81,6 +81,7 @@ CONFIG_PPP_SYNC_TTY=m
 # CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
 # CONFIG_MOUSE_PS2 is not set
 # CONFIG_SERIO is not set
 # CONFIG_LEGACY_PTYS is not set
@@ -96,6 +97,11 @@ CONFIG_DEBUG_GPIO=y
 CONFIG_MMC=y
 CONFIG_MMC_CLKGATE=y
 CONFIG_MMC_ARMMMCI=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_PL031=y
 CONFIG_DMADEVICES=y
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt
index 3a78bdcd0a43..ca900be144ce 100644
--- a/arch/arm/mach-at91/Kconfig.non_dt
+++ b/arch/arm/mach-at91/Kconfig.non_dt
@@ -176,12 +176,6 @@ config MACH_AFEB9260
           <svn://194.85.238.22/home/users/george/svn/arm9eb>
           <http://groups.google.com/group/arm9fpga-evolution-board>
 
-config MACH_USB_A9260
-        bool "CALAO USB-A9260"
-        help
-          Select this if you are using a Calao Systems USB-A9260.
-          <http://www.calao-systems.com>
-
 config MACH_QIL_A9260
         bool "CALAO QIL-A9260 board"
         help
@@ -257,13 +251,6 @@ config MACH_GSIA18S
           produced by GeoSIG Ltd company. This is an internet accelerograph.
           <http://www.geosig.com>
 
-config MACH_USB_A9G20
-        bool "CALAO USB-A9G20"
-        depends on ARCH_AT91SAM9G20
-        help
-          Select this if you are using a Calao Systems USB-A9G20.
-          <http://www.calao-systems.com>
-
 config MACH_SNAPPER_9260
         bool "Bluewater Systems Snapper 9260/9G20 module"
         help
@@ -309,12 +296,6 @@ config MACH_AT91SAM9263EK
           Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit.
           <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057>
 
-config MACH_USB_A9263
-        bool "CALAO USB-A9263"
-        help
-          Select this if you are using a Calao Systems USB-A9263.
-          <http://www.calao-systems.com>
-
 endif
 
 # ----------------------------------------------------------
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 07e89b4db7e7..3b0a9538093c 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -52,7 +52,6 @@ obj-$(CONFIG_MACH_RSI_EWS)	+= board-rsi-ews.o
 obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
 obj-$(CONFIG_MACH_CAM60)        += board-cam60.o
 obj-$(CONFIG_MACH_SAM9_L9260)   += board-sam9-l9260.o
-obj-$(CONFIG_MACH_USB_A9260)    += board-usb-a926x.o
 obj-$(CONFIG_MACH_QIL_A9260)    += board-qil-a9260.o
 obj-$(CONFIG_MACH_AFEB9260)     += board-afeb-9260v1.o
 obj-$(CONFIG_MACH_CPU9260)      += board-cpu9krea.o
@@ -64,7 +63,6 @@ obj-$(CONFIG_MACH_AT91SAM9G10EK) += board-sam9261ek.o
 
 # AT91SAM9263 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o
-obj-$(CONFIG_MACH_USB_A9263)    += board-usb-a926x.o
 
 # AT91SAM9RL board-specific support
 obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o
@@ -77,7 +75,6 @@ obj-$(CONFIG_MACH_STAMP9G20)	+= board-stamp9g20.o
 obj-$(CONFIG_MACH_PORTUXG20)    += board-stamp9g20.o
 obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o board-stamp9g20.o
 obj-$(CONFIG_MACH_GSIA18S)      += board-gsia18s.o board-stamp9g20.o
-obj-$(CONFIG_MACH_USB_A9G20)    += board-usb-a926x.o
 
 # AT91SAM9260/AT91SAM9G20 board-specific support
 obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index fda502691686..474ee04d24b9 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -266,6 +266,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
         CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
         CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
+        CLKDEV_CON_DEV_ID("hclk", "600000.gadget", &utmi_clk),
+        CLKDEV_CON_DEV_ID("pclk", "600000.gadget", &udphs_clk),
         /* fake hclk clock */
         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
         CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index e631fec040ce..2abee6626aac 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -249,6 +249,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
         CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
         CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
+        CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
+        CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
 };
 
 /*
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
deleted file mode 100644
index 2487d944a1bc..000000000000
--- a/arch/arm/mach-at91/board-usb-a926x.c
+++ /dev/null
@@ -1,384 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-usb-a926x.c
- *
- *  Copyright (C) 2005 SAN People
- *  Copyright (C) 2007 Atmel Corporation.
- *  Copyright (C) 2007 Calao-systems
- *  Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/gpio_keys.h>
-#include <linux/gpio.h>
-#include <linux/input.h>
-#include <linux/spi/mmc_spi.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <mach/hardware.h>
-#include <mach/at91sam9_smc.h>
-
-#include "at91_aic.h"
-#include "at91_shdwc.h"
-#include "board.h"
-#include "sam9_smc.h"
-#include "generic.h"
-
-
-static void __init ek_init_early(void)
-{
-        /* Initialize processor: 12.00 MHz crystal */
-        at91_initialize(12000000);
-}
-
-/*
- * USB Host port
- */
-static struct at91_usbh_data __initdata ek_usbh_data = {
-        .ports          = 2,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-
-/*
- * USB Device port
- */
-static struct at91_udc_data __initdata ek_udc_data = {
-        .vbus_pin       = AT91_PIN_PB11,
-        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
-};
-
-static void __init ek_add_device_udc(void)
-{
-        if (machine_is_usb_a9260() || machine_is_usb_a9g20())
-                ek_udc_data.vbus_pin = AT91_PIN_PC5;
-
-        at91_add_device_udc(&ek_udc_data);
-}
-
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
-#define MMC_SPI_CARD_DETECT_INT AT91_PIN_PC4
-static int at91_mmc_spi_init(struct device *dev,
-        irqreturn_t (*detect_int)(int, void *), void *data)
-{
-        /* Configure Interrupt pin as input, no pull-up */
-        at91_set_gpio_input(MMC_SPI_CARD_DETECT_INT, 0);
-        return request_irq(gpio_to_irq(MMC_SPI_CARD_DETECT_INT), detect_int,
-                IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
-                "mmc-spi-detect", data);
-}
-
-static void at91_mmc_spi_exit(struct device *dev, void *data)
-{
-        free_irq(gpio_to_irq(MMC_SPI_CARD_DETECT_INT), data);
-}
-
-static struct mmc_spi_platform_data at91_mmc_spi_pdata = {
-        .init = at91_mmc_spi_init,
-        .exit = at91_mmc_spi_exit,
-        .detect_delay = 100, /* msecs */
-};
-#endif
-
-/*
- * SPI devices.
- */
-static struct spi_board_info usb_a9263_spi_devices[] = {
-        {       /* DataFlash chip */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 0,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-        }
-};
-
-static struct spi_board_info usb_a9g20_spi_devices[] = {
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
-        {
-                .modalias = "mmc_spi",
-                .max_speed_hz = 20000000,       /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
-                .chip_select = 0,
-                .platform_data = &at91_mmc_spi_pdata,
-                .mode = SPI_MODE_3,
-        },
-#endif
-};
-
-static void __init ek_add_device_spi(void)
-{
-        if (machine_is_usb_a9263())
-                at91_add_device_spi(usb_a9263_spi_devices, ARRAY_SIZE(usb_a9263_spi_devices));
-        else if (machine_is_usb_a9g20())
-                at91_add_device_spi(usb_a9g20_spi_devices, ARRAY_SIZE(usb_a9g20_spi_devices));
-}
-
-/*
- * MACB Ethernet device
- */
-static struct macb_platform_data __initdata ek_macb_data = {
-        .phy_irq_pin    = AT91_PIN_PE31,
-        .is_rmii        = 1,
-};
-
-static void __init ek_add_device_eth(void)
-{
-        if (machine_is_usb_a9260() || machine_is_usb_a9g20())
-                ek_macb_data.phy_irq_pin = AT91_PIN_PA31;
-
-        at91_add_device_eth(&ek_macb_data);
-}
-
-/*
- * NAND flash
- */
-static struct mtd_partition __initdata ek_nand_partition[] = {
-        {
-                .name   = "barebox",
-                .offset = 0,
-                .size   = 3 * SZ_128K,
-        }, {
-                .name   = "bareboxenv",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = SZ_128K,
-        }, {
-                .name   = "bareboxenv2",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = SZ_128K,
-        }, {
-                .name   = "oftree",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = SZ_128K,
-        }, {
-                .name   = "kernel",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = 4 * SZ_1M,
-        }, {
-                .name   = "rootfs",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = 120 * SZ_1M,
-        }, {
-                .name   = "data",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = MTDPART_SIZ_FULL,
-        }
-};
-
-static struct atmel_nand_data __initdata ek_nand_data = {
-        .ale            = 21,
-        .cle            = 22,
-        .det_pin        = -EINVAL,
-        .rdy_pin        = AT91_PIN_PA22,
-        .enable_pin     = AT91_PIN_PD15,
-        .ecc_mode       = NAND_ECC_SOFT,
-        .on_flash_bbt   = 1,
-        .parts          = ek_nand_partition,
-        .num_parts      = ARRAY_SIZE(ek_nand_partition),
-};
-
-static struct sam9_smc_config __initdata usb_a9260_nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 1,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 1,
-
-        .ncs_read_pulse         = 3,
-        .nrd_pulse              = 3,
-        .ncs_write_pulse        = 3,
-        .nwe_pulse              = 3,
-
-        .read_cycle             = 5,
-        .write_cycle            = 5,
-
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
-        .tdf_cycles             = 2,
-};
-
-static struct sam9_smc_config __initdata usb_a9g20_nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 2,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 2,
-
-        .ncs_read_pulse         = 4,
-        .nrd_pulse              = 4,
-        .ncs_write_pulse        = 4,
-        .nwe_pulse              = 4,
-
-        .read_cycle             = 7,
-        .write_cycle            = 7,
-
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
-        .tdf_cycles             = 3,
-};
-
-static void __init ek_add_device_nand(void)
-{
-        if (machine_is_usb_a9260() || machine_is_usb_a9g20()) {
-                ek_nand_data.rdy_pin    = AT91_PIN_PC13;
-                ek_nand_data.enable_pin = AT91_PIN_PC14;
-        }
-
-        /* configure chip-select 3 (NAND) */
-        if (machine_is_usb_a9g20())
-                sam9_smc_configure(0, 3, &usb_a9g20_nand_smc_config);
-        else
-                sam9_smc_configure(0, 3, &usb_a9260_nand_smc_config);
-
-        at91_add_device_nand(&ek_nand_data);
-}
-
-
-/*
- * GPIO Buttons
- */
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-static struct gpio_keys_button ek_buttons[] = {
-        {       /* USER PUSH BUTTON */
-                .code           = KEY_ENTER,
-                .gpio           = AT91_PIN_PB10,
-                .active_low     = 1,
-                .desc           = "user_pb",
-                .wakeup         = 1,
-        }
-};
-
-static struct gpio_keys_platform_data ek_button_data = {
-        .buttons        = ek_buttons,
-        .nbuttons       = ARRAY_SIZE(ek_buttons),
-};
-
-static struct platform_device ek_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &ek_button_data,
-        }
-};
-
-static void __init ek_add_device_buttons(void)
-{
-        at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* user push button, pull up enabled */
-        at91_set_deglitch(AT91_PIN_PB10, 1);
-
-        platform_device_register(&ek_button_device);
-}
-#else
-static void __init ek_add_device_buttons(void) {}
-#endif
-
-/*
- * LEDs
- */
-static struct gpio_led ek_leds[] = {
-        {       /* user_led (green) */
-                .name                   = "user_led",
-                .gpio                   = AT91_PIN_PB21,
-                .active_low             = 1,
-                .default_trigger        = "heartbeat",
-        }
-};
-
-static struct i2c_board_info __initdata ek_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("rv3029c2", 0x56),
-        },
-};
-
-static void __init ek_add_device_leds(void)
-{
-        if (machine_is_usb_a9260() || machine_is_usb_a9g20())
-                ek_leds[0].active_low = 0;
-
-        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
-}
-
-static void __init ek_board_init(void)
-{
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        at91_add_device_serial();
-        /* USB Host */
-        at91_add_device_usbh(&ek_usbh_data);
-        /* USB Device */
-        ek_add_device_udc();
-        /* SPI */
-        ek_add_device_spi();
-        /* Ethernet */
-        ek_add_device_eth();
-        /* NAND */
-        ek_add_device_nand();
-        /* Push Buttons */
-        ek_add_device_buttons();
-        /* LEDs */
-        ek_add_device_leds();
-
-        if (machine_is_usb_a9g20()) {
-                /* I2C */
-                at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
-        } else {
-                /* I2C */
-                at91_add_device_i2c(NULL, 0);
-                /* shutdown controller, wakeup button (5 msec low) */
-                at91_shdwc_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10)
-                                | AT91_SHDW_WKMODE0_LOW
-                                | AT91_SHDW_RTTWKEN);
-        }
-}
-
-MACHINE_START(USB_A9263, "CALAO USB_A9263")
-        /* Maintainer: calao-systems */
-        .init_time      = at91sam926x_pit_init,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = ek_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = ek_board_init,
-MACHINE_END
-
-MACHINE_START(USB_A9260, "CALAO USB_A9260")
-        /* Maintainer: calao-systems */
-        .init_time      = at91sam926x_pit_init,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = ek_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = ek_board_init,
-MACHINE_END
-
-MACHINE_START(USB_A9G20, "CALAO USB_A92G0")
-        /* Maintainer: Jean-Christophe PLAGNIOL-VILLARD */
-        .init_time      = at91sam926x_pit_init,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = ek_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = ek_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 04b1bad68350..9afac26fa1cc 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -327,8 +327,6 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
         clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
         clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
         clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
-        clk_register_clkdev(clk[ssi_ext1_gate], "ssi_ext1", NULL);
-        clk_register_clkdev(clk[ssi_ext2_gate], "ssi_ext2", NULL);
         clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
         clk_register_clkdev(clk[cpu_podf], NULL, "cpufreq-cpu0.0");
         clk_register_clkdev(clk[iim_gate], "iim", NULL);
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index 74e7b94c22e7..98c58944015a 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -24,26 +24,10 @@
 #include "hardware.h"
 #include "mx53.h"
 
-static void __init imx53_qsb_init(void)
-{
-        struct clk *clk;
-
-        clk = clk_get_sys(NULL, "ssi_ext1");
-        if (IS_ERR(clk)) {
-                pr_err("failed to get clk ssi_ext1\n");
-                return;
-        }
-
-        clk_register_clkdev(clk, NULL, "0-000a");
-}
-
 static void __init imx53_dt_init(void)
 {
         mxc_arch_reset_init_dt();
 
-        if (of_machine_is_compatible("fsl,imx53-qsb"))
-                imx53_qsb_init();
-
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 3a66635e7d17..616fe0210da1 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -23,6 +23,7 @@ config ARCH_MXS
         select GENERIC_CLOCKEVENTS
         select HAVE_CLK_PREPARE
         select PINCTRL
+        select SOC_BUS
         select SOC_IMX23
         select SOC_IMX28
         select STMP_DEVICE
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index d67ecc1c8847..7fa611c1b287 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -19,13 +19,13 @@
 #include <linux/err.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
-#include <linux/irqchip.h>
 #include <linux/irqchip/mxs.h>
 #include <linux/micrel_phy.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
 #include <linux/phy.h>
 #include <linux/pinctrl/consumer.h>
+#include <linux/sys_soc.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
@@ -39,12 +39,28 @@
 #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0         0x2
 #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1         0x3
 
+#define HW_DIGCTL_CHIPID        0x310
+#define HW_DIGCTL_CHIPID_MASK   (0xffff << 16)
+#define HW_DIGCTL_REV_MASK      0xff
+#define HW_DIGCTL_CHIPID_MX23   (0x3780 << 16)
+#define HW_DIGCTL_CHIPID_MX28   (0x2800 << 16)
+
+#define MXS_CHIP_REVISION_1_0   0x10
+#define MXS_CHIP_REVISION_1_1   0x11
+#define MXS_CHIP_REVISION_1_2   0x12
+#define MXS_CHIP_REVISION_1_3   0x13
+#define MXS_CHIP_REVISION_1_4   0x14
+#define MXS_CHIP_REV_UNKNOWN    0xff
+
 #define MXS_GPIO_NR(bank, nr)   ((bank) * 32 + (nr))
 
 #define MXS_SET_ADDR            0x4
 #define MXS_CLR_ADDR            0x8
 #define MXS_TOG_ADDR            0xc
 
+static u32 chipid;
+static u32 socid;
+
 static inline void __mxs_setl(u32 mask, void __iomem *reg)
 {
         __raw_writel(mask, reg + MXS_SET_ADDR);
@@ -352,29 +368,123 @@ static void __init tx28_post_init(void)
         pinctrl_put(pctl);
 }
 
-static void __init cfa10049_init(void)
+static void __init crystalfontz_init(void)
 {
         update_fec_mac_prop(OUI_CRYSTALFONTZ);
 }
 
-static void __init cfa10037_init(void)
+static const char __init *mxs_get_soc_id(void)
 {
-        update_fec_mac_prop(OUI_CRYSTALFONTZ);
+        struct device_node *np;
+        void __iomem *digctl_base;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx23-digctl");
+        digctl_base = of_iomap(np, 0);
+        WARN_ON(!digctl_base);
+
+        chipid = readl(digctl_base + HW_DIGCTL_CHIPID);
+        socid = chipid & HW_DIGCTL_CHIPID_MASK;
+
+        iounmap(digctl_base);
+        of_node_put(np);
+
+        switch (socid) {
+        case HW_DIGCTL_CHIPID_MX23:
+                return "i.MX23";
+        case HW_DIGCTL_CHIPID_MX28:
+                return "i.MX28";
+        default:
+                return "Unknown";
+        }
+}
+
+static u32 __init mxs_get_cpu_rev(void)
+{
+        u32 rev = chipid & HW_DIGCTL_REV_MASK;
+
+        switch (socid) {
+        case HW_DIGCTL_CHIPID_MX23:
+                switch (rev) {
+                case 0x0:
+                        return MXS_CHIP_REVISION_1_0;
+                case 0x1:
+                        return MXS_CHIP_REVISION_1_1;
+                case 0x2:
+                        return MXS_CHIP_REVISION_1_2;
+                case 0x3:
+                        return MXS_CHIP_REVISION_1_3;
+                case 0x4:
+                        return MXS_CHIP_REVISION_1_4;
+                default:
+                        return MXS_CHIP_REV_UNKNOWN;
+                }
+        case HW_DIGCTL_CHIPID_MX28:
+                switch (rev) {
+                case 0x0:
+                        return MXS_CHIP_REVISION_1_1;
+                case 0x1:
+                        return MXS_CHIP_REVISION_1_2;
+                default:
+                        return MXS_CHIP_REV_UNKNOWN;
+                }
+        default:
+                return MXS_CHIP_REV_UNKNOWN;
+        }
+}
+
+static const char __init *mxs_get_revision(void)
+{
+        u32 rev = mxs_get_cpu_rev();
+
+        if (rev != MXS_CHIP_REV_UNKNOWN)
+                return kasprintf(GFP_KERNEL, "TO%d.%d", (rev >> 4) & 0xf,
+                                rev & 0xf);
+        else
+                return kasprintf(GFP_KERNEL, "%s", "Unknown");
 }
 
 static void __init mxs_machine_init(void)
 {
+        struct device_node *root;
+        struct device *parent;
+        struct soc_device *soc_dev;
+        struct soc_device_attribute *soc_dev_attr;
+        int ret;
+
+        soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+        if (!soc_dev_attr)
+                return;
+
+        root = of_find_node_by_path("/");
+        ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
+        if (ret)
+                return;
+
+        soc_dev_attr->family = "Freescale MXS Family";
+        soc_dev_attr->soc_id = mxs_get_soc_id();
+        soc_dev_attr->revision = mxs_get_revision();
+
+        soc_dev = soc_device_register(soc_dev_attr);
+        if (IS_ERR(soc_dev)) {
+                kfree(soc_dev_attr->revision);
+                kfree(soc_dev_attr);
+                return;
+        }
+
+        parent = soc_device_to_device(soc_dev);
+
         if (of_machine_is_compatible("fsl,imx28-evk"))
                 imx28_evk_init();
         else if (of_machine_is_compatible("bluegiga,apx4devkit"))
                 apx4devkit_init();
-        else if (of_machine_is_compatible("crystalfontz,cfa10037"))
-                cfa10037_init();
-        else if (of_machine_is_compatible("crystalfontz,cfa10049"))
-                cfa10049_init();
+        else if (of_machine_is_compatible("crystalfontz,cfa10037") ||
+                 of_machine_is_compatible("crystalfontz,cfa10049") ||
+                 of_machine_is_compatible("crystalfontz,cfa10055") ||
+                 of_machine_is_compatible("crystalfontz,cfa10057"))
+                crystalfontz_init();
 
         of_platform_populate(NULL, of_default_bus_match_table,
-                             mxs_auxdata_lookup, NULL);
+                             mxs_auxdata_lookup, parent);
 
         if (of_machine_is_compatible("karo,tx28"))
                 tx28_post_init();
@@ -434,7 +544,6 @@ static const char *mxs_dt_compat[] __initdata = {
 };
 
 DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)")
-        .init_irq       = irqchip_init,
         .handle_irq     = icoll_handle_irq,
         .init_time      = mxs_timer_init,
         .init_machine   = mxs_machine_init,
diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig
index 9b9d105f194c..5981c3db9b41 100644
--- a/arch/arm/mach-nomadik/Kconfig
+++ b/arch/arm/mach-nomadik/Kconfig
@@ -6,6 +6,7 @@ config ARCH_NOMADIK
         select ARM_VIC
         select CLKSRC_NOMADIK_MTU
         select CLKSRC_NOMADIK_MTU_SCHED_CLOCK
+        select CLKSRC_OF
         select COMMON_CLK
         select CPU_ARM926T
         select GENERIC_CLOCKEVENTS
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 46cce9baa129..2df209ed1a07 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -26,9 +26,7 @@
 #include <linux/irq.h>
 #include <linux/dma-mapping.h>
 #include <linux/platform_data/clk-nomadik.h>
-#include <linux/platform_data/pinctrl-nomadik.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/platform_data/clocksource-nomadik-mtu.h>
+#include <linux/clocksource.h>
 #include <linux/of_irq.h>
 #include <linux/of_gpio.h>
 #include <linux/of_address.h>
@@ -90,48 +88,6 @@
 #define NOMADIK_L2CC_BASE       0x10210000      /* L2 Cache controller */
 #define NOMADIK_UART1_VBASE     0xF01FB000
 
-static unsigned long out_low[] = { PIN_OUTPUT_LOW };
-static unsigned long out_high[] = { PIN_OUTPUT_HIGH };
-static unsigned long in_nopull[] = { PIN_INPUT_NOPULL };
-static unsigned long in_pullup[] = { PIN_INPUT_PULLUP };
-
-static struct pinctrl_map __initdata nhk8815_pinmap[] = {
-        PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-stn8815", "u0_a_1", "u0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("uart1", "pinctrl-stn8815", "u1_a_1", "u1"),
-        /* Hog in MMC/SD card mux */
-        PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-stn8815", "mmcsd_a_1", "mmcsd"),
-        /* MCCLK */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO8_B10", out_low),
-        /* MCCMD */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO9_A10", in_pullup),
-        /* MCCMDDIR */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO10_C11", out_high),
-        /* MCDAT3-0 */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO11_B11", in_pullup),
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO12_A11", in_pullup),
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO13_C12", in_pullup),
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO14_B12", in_pullup),
-        /* MCDAT0DIR */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO15_A12", out_high),
-        /* MCDAT31DIR */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO16_C13", out_high),
-        /* MCMSFBCLK */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO24_C15", in_pullup),
-        /* CD input GPIO */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO111_H21", in_nopull),
-        /* CD bias drive */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO112_J21", out_low),
-        /* I2C0 */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO62_D3", in_pullup),
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO63_D2", in_pullup),
-        /* I2C1 */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO53_L4", in_pullup),
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO54_L3", in_pullup),
-        /* I2C2 */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO73_C21", in_pullup),
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO74_C20", in_pullup),
-};
-
 /* This is needed for LL-debug/earlyprintk/debug-macro.S */
 static struct map_desc cpu8815_io_desc[] __initdata = {
         {
@@ -171,7 +127,7 @@ static void __init cpu8815_timer_init_of(void)
         /* We need this to be up now */
         nomadik_clk_init();
 
-        mtu = of_find_node_by_path("/mtu0");
+        mtu = of_find_node_by_path("/mtu@101e2000");
         if (!mtu)
                 return;
         base = of_iomap(mtu, 0);
@@ -187,7 +143,7 @@ static void __init cpu8815_timer_init_of(void)
         src_cr |= SRC_CR_INIT_VAL;
         writel(src_cr, base);
 
-        nmdk_timer_init(base, irq);
+        clocksource_of_init();
 }
 
 static struct fsmc_nand_timings cpu8815_nand_timings = {
@@ -279,28 +235,10 @@ device_initcall(cpu8815_mmcsd_init);
 
 /* These are mostly to get the right device names for the clock lookups */
 static struct of_dev_auxdata cpu8815_auxdata_lookup[] __initdata = {
-        OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO0_BASE,
-                "gpio.0", NULL),
-        OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO1_BASE,
-                "gpio.1", NULL),
-        OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO2_BASE,
-                "gpio.2", NULL),
-        OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO3_BASE,
-                "gpio.3", NULL),
-        OF_DEV_AUXDATA("stericsson,nmk-pinctrl-stn8815", 0,
-                "pinctrl-stn8815", NULL),
-        OF_DEV_AUXDATA("arm,primecell", NOMADIK_UART0_BASE,
-                "uart0", NULL),
-        OF_DEV_AUXDATA("arm,primecell", NOMADIK_UART1_BASE,
-                "uart1", NULL),
-        OF_DEV_AUXDATA("arm,primecell", NOMADIK_RNG_BASE,
-                "rng", NULL),
-        OF_DEV_AUXDATA("arm,primecell", NOMADIK_RTC_BASE,
-                "rtc-pl031", NULL),
         OF_DEV_AUXDATA("stericsson,fsmc-nand", NOMADIK_FSMC_BASE,
-                "fsmc-nand", &cpu8815_nand_data),
+                NULL, &cpu8815_nand_data),
         OF_DEV_AUXDATA("arm,primecell", NOMADIK_SDI_BASE,
-                "mmci", &mmcsd_plat_data),
+                NULL, &mmcsd_plat_data),
         { /* sentinel */ },
 };
 
@@ -310,7 +248,6 @@ static void __init cpu8815_init_of(void)
         /* At full speed latency must be >=2, so 0x249 in low bits */
         l2x0_of_init(0x00730249, 0xfe000fff);
 #endif
-        pinctrl_register_mappings(nhk8815_pinmap, ARRAY_SIZE(nhk8815_pinmap));
         of_platform_populate(NULL, of_default_bus_match_table,
                         cpu8815_auxdata_lookup, NULL);
 }
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index 0346de56436c..ba6534d7f155 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -431,15 +431,11 @@ DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
  *  - Driver code is not yet migrated to use hwmod/runtime pm
  *  - Modules outside kernel access (to disable them by default)
  *
- *     - debugss
  *     - mmu (gfx domain)
  *     - cefuse
  *     - usbotg_fck (its additional clock and not really a modulemode)
  *     - ieee5000
  */
-DEFINE_CLK_GATE(debugss_ick, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
-                AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
-                0x0, NULL);
 
 DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
                 AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
@@ -890,6 +886,42 @@ DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm",
                          NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
 
 /*
+ * debugss optional clocks
+ */
+DEFINE_CLK_GATE(dbg_sysclk_ck, "sys_clkin_ck", &sys_clkin_ck,
+                0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
+                AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT, 0x0, NULL);
+
+DEFINE_CLK_GATE(dbg_clka_ck, "dpll_core_m4_ck", &dpll_core_m4_ck,
+                0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
+                AM33XX_OPTCLK_DEBUG_CLKA_SHIFT, 0x0, NULL);
+
+static const char *stm_pmd_clock_mux_ck_parents[] = {
+        "dbg_sysclk_ck", "dbg_clka_ck",
+};
+
+DEFINE_CLK_MUX(stm_pmd_clock_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
+               AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_STM_PMD_CLKSEL_SHIFT,
+               AM33XX_STM_PMD_CLKSEL_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(trace_pmd_clk_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
+               AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
+               AM33XX_TRC_PMD_CLKSEL_SHIFT,
+               AM33XX_TRC_PMD_CLKSEL_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_DIVIDER(stm_clk_div_ck, "stm_pmd_clock_mux_ck",
+                   &stm_pmd_clock_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
+                   AM33XX_STM_PMD_CLKDIVSEL_SHIFT,
+                   AM33XX_STM_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
+                   NULL);
+
+DEFINE_CLK_DIVIDER(trace_clk_div_ck, "trace_pmd_clk_mux_ck",
+                   &trace_pmd_clk_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
+                   AM33XX_TRC_PMD_CLKDIVSEL_SHIFT,
+                   AM33XX_TRC_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
+                   NULL);
+
+/*
  * clkdev
  */
 static struct omap_clk am33xx_clks[] = {
@@ -926,7 +958,6 @@ static struct omap_clk am33xx_clks[] = {
         CLK("481cc000.d_can",   NULL,           &dcan0_fck),
         CLK(NULL,       "dcan1_fck",            &dcan1_fck),
         CLK("481d0000.d_can",   NULL,           &dcan1_fck),
-        CLK(NULL,       "debugss_ick",          &debugss_ick),
         CLK(NULL,       "pruss_ocp_gclk",       &pruss_ocp_gclk),
         CLK(NULL,       "mcasp0_fck",           &mcasp0_fck),
         CLK(NULL,       "mcasp1_fck",           &mcasp1_fck),
@@ -969,6 +1000,13 @@ static struct omap_clk am33xx_clks[] = {
         CLK(NULL,       "clkout2_div_ck",       &clkout2_div_ck),
         CLK(NULL,       "timer_32k_ck",         &clkdiv32k_ick),
         CLK(NULL,       "timer_sys_ck",         &sys_clkin_ck),
+        CLK(NULL,       "dbg_sysclk_ck",        &dbg_sysclk_ck),
+        CLK(NULL,       "dbg_clka_ck",          &dbg_clka_ck),
+        CLK(NULL,       "stm_pmd_clock_mux_ck", &stm_pmd_clock_mux_ck),
+        CLK(NULL,       "trace_pmd_clk_mux_ck", &trace_pmd_clk_mux_ck),
+        CLK(NULL,       "stm_clk_div_ck",       &stm_clk_div_ck),
+        CLK(NULL,       "trace_clk_div_ck",     &trace_clk_div_ck),
+        CLK(NULL,       "clkout2_ck",           &clkout2_ck),
         CLK("48300200.ehrpwm",  "tbclk",        &ehrpwm0_tbclk),
         CLK("48302200.ehrpwm",  "tbclk",        &ehrpwm1_tbclk),
         CLK("48304200.ehrpwm",  "tbclk",        &ehrpwm2_tbclk),
@@ -982,6 +1020,7 @@ static const char *enable_init_clks[] = {
         "l4hs_gclk",
         "l4fw_gclk",
         "l4ls_gclk",
+        "clkout2_ck",   /* Required for external peripherals like, Audio codecs */
 };
 
 int __init am33xx_clk_init(void)
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index f8d1912f103e..0adb2b85f830 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -492,6 +492,18 @@ config MACH_SMDK2416
         help
           Say Y here if you are using an SMDK2416
 
+config MACH_S3C2416_DT
+        bool "Samsung S3C2416 machine using devicetree"
+        select CLKSRC_OF
+        select USE_OF
+        select PINCTRL
+        select PINCTRL_S3C24XX
+        help
+          Machine support for Samsung S3C2416 machines with device tree enabled.
+          Select this if a fdt blob is available for the S3C2416 SoC based board.
+          Note: This is under development and not all peripherals can be supported
+          with this machine file.
+
 endif   # CPU_S3C2416
 
 if CPU_S3C2440
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 6f46ecfc8396..6de730bada4d 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -85,6 +85,7 @@ obj-$(CONFIG_MACH_SMDK2413)		+= mach-smdk2413.o
 obj-$(CONFIG_MACH_VSTMS)                += mach-vstms.o
 
 obj-$(CONFIG_MACH_SMDK2416)             += mach-smdk2416.o
+obj-$(CONFIG_MACH_S3C2416_DT)           += mach-s3c2416-dt.o
 
 obj-$(CONFIG_MACH_ANUBIS)               += mach-anubis.o
 obj-$(CONFIG_MACH_AT2440EVB)            += mach-at2440evb.o
diff --git a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
new file mode 100644
index 000000000000..f50454a34f72
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
@@ -0,0 +1,91 @@
+/*
+ * Samsung's S3C2416 flattened device tree enabled machine
+ *
+ * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
+ *
+ * based on mach-exynos/mach-exynos4-dt.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ * Copyright (c) 2010-2011 Linaro Ltd.
+ *              www.linaro.org
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/clocksource.h>
+#include <linux/irqchip.h>
+#include <linux/of_platform.h>
+#include <linux/serial_core.h>
+
+#include <asm/mach/arch.h>
+#include <mach/map.h>
+
+#include <plat/cpu.h>
+#include <plat/pm.h>
+#include <plat/regs-serial.h>
+
+#include "common.h"
+
+/*
+ * The following lookup table is used to override device names when devices
+ * are registered from device tree. This is temporarily added to enable
+ * device tree support addition for the S3C2416 architecture.
+ *
+ * For drivers that require platform data to be provided from the machine
+ * file, a platform data pointer can also be supplied along with the
+ * devices names. Usually, the platform data elements that cannot be parsed
+ * from the device tree by the drivers (example: function pointers) are
+ * supplied. But it should be noted that this is a temporary mechanism and
+ * at some point, the drivers should be capable of parsing all the platform
+ * data from the device tree.
+ */
+static const struct of_dev_auxdata s3c2416_auxdata_lookup[] __initconst = {
+        OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART,
+                                "s3c2440-uart.0", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0x4000,
+                                "s3c2440-uart.1", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0x8000,
+                                "s3c2440-uart.2", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0xC000,
+                                "s3c2440-uart.3", NULL),
+        OF_DEV_AUXDATA("samsung,s3c6410-sdhci", S3C_PA_HSMMC0,
+                                "s3c-sdhci.0", NULL),
+        OF_DEV_AUXDATA("samsung,s3c6410-sdhci", S3C_PA_HSMMC1,
+                                "s3c-sdhci.1", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", S3C_PA_IIC,
+                                "s3c2440-i2c.0", NULL),
+        {},
+};
+
+static void __init s3c2416_dt_map_io(void)
+{
+        s3c24xx_init_io(NULL, 0);
+        s3c24xx_init_clocks(12000000);
+}
+
+static void __init s3c2416_dt_machine_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table,
+                                s3c2416_auxdata_lookup, NULL);
+
+        s3c_pm_init();
+}
+
+static char const *s3c2416_dt_compat[] __initdata = {
+        "samsung,s3c2416",
+        "samsung,s3c2450",
+        NULL
+};
+
+DT_MACHINE_START(S3C2416_DT, "Samsung S3C2416 (Flattened Device Tree)")
+        /* Maintainer: Heiko Stuebner <heiko@sntech.de> */
+        .dt_compat      = s3c2416_dt_compat,
+        .map_io         = s3c2416_dt_map_io,
+        .init_irq       = irqchip_init,
+        .init_machine   = s3c2416_dt_machine_init,
+         .init_time     = clocksource_of_init,
+        .restart        = s3c2416_restart,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 65e1547678b0..db27e8eef192 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -105,6 +105,20 @@ config MACH_ARMADILLO800EVA
         select SND_SOC_WM8978 if SND_SIMPLE_CARD
         select USE_OF
 
+config MACH_ARMADILLO800EVA_REFERENCE
+        bool "Armadillo-800 EVA board - Reference Device Tree Implementation"
+        depends on ARCH_R8A7740
+        select ARCH_REQUIRE_GPIOLIB
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
+        select SND_SOC_WM8978 if SND_SIMPLE_CARD
+        select USE_OF
+        ---help---
+           Use reference implementation of Aramdillo800 EVA board support
+           which makes a greater use of device tree at the expense
+           of not supporting a number of devices.
+
+           This is intended to aid developers
+
 config MACH_BOCKW
         bool "BOCK-W platform"
         depends on ARCH_R8A7778
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 76f1639c5945..6165a517f580 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_MACH_MARZEN)	+= board-marzen.o
 obj-$(CONFIG_MACH_MARZEN_REFERENCE)     += board-marzen-reference.o
 obj-$(CONFIG_MACH_LAGER)        += board-lager.o
 obj-$(CONFIG_MACH_ARMADILLO800EVA)      += board-armadillo800eva.o
+obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE)    += board-armadillo800eva-reference.o
 obj-$(CONFIG_MACH_KZM9D)        += board-kzm9d.o
 obj-$(CONFIG_MACH_KZM9G)        += board-kzm9g.o
 obj-$(CONFIG_MACH_KZM9G_REFERENCE)      += board-kzm9g-reference.o
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
new file mode 100644
index 000000000000..03b85fec2ddb
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
@@ -0,0 +1,213 @@
+/*
+ * armadillo 800 eva board support
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/pinctrl/machine.h>
+#include <mach/common.h>
+#include <mach/r8a7740.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware/cache-l2x0.h>
+
+/*
+ * CON1         Camera Module
+ * CON2         Extension Bus
+ * CON3         HDMI Output
+ * CON4         Composite Video Output
+ * CON5         H-UDI JTAG
+ * CON6         ARM JTAG
+ * CON7         SD1
+ * CON8         SD2
+ * CON9         RTC BackUp
+ * CON10        Monaural Mic Input
+ * CON11        Stereo Headphone Output
+ * CON12        Audio Line Output(L)
+ * CON13        Audio Line Output(R)
+ * CON14        AWL13 Module
+ * CON15        Extension
+ * CON16        LCD1
+ * CON17        LCD2
+ * CON19        Power Input
+ * CON20        USB1
+ * CON21        USB2
+ * CON22        Serial
+ * CON23        LAN
+ * CON24        USB3
+ * LED1         Camera LED(Yellow)
+ * LED2         Power LED (Green)
+ * ED3-LED6     User LED(Yellow)
+ * LED7         LAN link LED(Green)
+ * LED8         LAN activity LED(Yellow)
+ */
+
+/*
+ * DipSwitch
+ *
+ *                    SW1
+ *
+ * -12345678-+---------------+----------------------------
+ *  1        | boot          | hermit
+ *  0        | boot          | OS auto boot
+ * -12345678-+---------------+----------------------------
+ *   00      | boot device   | eMMC
+ *   10      | boot device   | SDHI0 (CON7)
+ *   01      | boot device   | -
+ *   11      | boot device   | Extension Buss (CS0)
+ * -12345678-+---------------+----------------------------
+ *     0     | Extension Bus | D8-D15 disable, eMMC enable
+ *     1     | Extension Bus | D8-D15 enable,  eMMC disable
+ * -12345678-+---------------+----------------------------
+ *      0    | SDHI1         | COM8 disable, COM14 enable
+ *      1    | SDHI1         | COM8 enable,  COM14 disable
+ * -12345678-+---------------+----------------------------
+ *       0   | USB0          | COM20 enable,  COM24 disable
+ *       1   | USB0          | COM20 disable, COM24 enable
+ * -12345678-+---------------+----------------------------
+ *        00 | JTAG          | SH-X2
+ *        10 | JTAG          | ARM
+ *        01 | JTAG          | -
+ *        11 | JTAG          | Boundary Scan
+ *-----------+---------------+----------------------------
+ */
+
+/*
+ * FSI-WM8978
+ *
+ * this command is required when playback.
+ *
+ * # amixer set "Headphone" 50
+ *
+ * this command is required when capture.
+ *
+ * # amixer set "Input PGA" 15
+ * # amixer set "Left Input Mixer MicP" on
+ * # amixer set "Left Input Mixer MicN" on
+ * # amixer set "Right Input Mixer MicN" on
+ * # amixer set "Right Input Mixer MicP" on
+ */
+
+/*
+ * USB function
+ *
+ * When you use USB Function,
+ * set SW1.6 ON, and connect cable to CN24.
+ *
+ * USBF needs workaround on R8A7740 chip.
+ * These are a little bit complex.
+ * see
+ *      usbhsf_power_ctrl()
+ */
+
+static const struct pinctrl_map eva_pinctrl_map[] = {
+        /* SCIFA1 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.1", "pfc-r8a7740",
+                                  "scifa1_data", "scifa1"),
+};
+
+static void __init eva_clock_init(void)
+{
+        struct clk *system      = clk_get(NULL, "system_clk");
+        struct clk *xtal1       = clk_get(NULL, "extal1");
+        struct clk *usb24s      = clk_get(NULL, "usb24s");
+        struct clk *fsibck      = clk_get(NULL, "fsibck");
+
+        if (IS_ERR(system)      ||
+            IS_ERR(xtal1)       ||
+            IS_ERR(usb24s)      ||
+            IS_ERR(fsibck)) {
+                pr_err("armadillo800eva board clock init failed\n");
+                goto clock_error;
+        }
+
+        /* armadillo 800 eva extal1 is 24MHz */
+        clk_set_rate(xtal1, 24000000);
+
+        /* usb24s use extal1 (= system) clock (= 24MHz) */
+        clk_set_parent(usb24s, system);
+
+        /* FSIBCK is 12.288MHz, and it is parent of FSI-B */
+        clk_set_rate(fsibck, 12288000);
+
+clock_error:
+        if (!IS_ERR(system))
+                clk_put(system);
+        if (!IS_ERR(xtal1))
+                clk_put(xtal1);
+        if (!IS_ERR(usb24s))
+                clk_put(usb24s);
+        if (!IS_ERR(fsibck))
+                clk_put(fsibck);
+}
+
+/*
+ * board init
+ */
+static void __init eva_init(void)
+{
+
+        r8a7740_clock_init(MD_CK0 | MD_CK2);
+        eva_clock_init();
+
+        pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map));
+        r8a7740_pinmux_init();
+
+        r8a7740_meram_workaround();
+
+        /*
+         * Touchscreen
+         * TODO: Move reset GPIO over to .dts when we can reference it
+         */
+        gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
+
+#ifdef CONFIG_CACHE_L2X0
+        /* Early BRESP enable, Shared attribute override enable, 32K*8way */
+        l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
+#endif
+
+        r8a7740_add_standard_devices_dt();
+        r8a7740_pm_init();
+}
+
+#define RESCNT2 IOMEM(0xe6188020)
+static void eva_restart(char mode, const char *cmd)
+{
+        /* Do soft power on reset */
+        writel((1 << 31), RESCNT2);
+}
+
+static const char *eva_boards_compat_dt[] __initdata = {
+        "renesas,armadillo800eva-reference",
+        NULL,
+};
+
+DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva-reference")
+        .map_io         = r8a7740_map_io,
+        .init_early     = r8a7740_init_delay,
+        .init_irq       = r8a7740_init_irq_of,
+        .init_machine   = eva_init,
+        .init_time      = shmobile_timer_init,
+        .init_late      = shmobile_init_late,
+        .dt_compat      = eva_boards_compat_dt,
+        .restart        = eva_restart,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index 9c9a66ccaf6f..b34d19b5ca5c 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -45,10 +45,13 @@ enum {
 };
 
 extern void r8a7740_meram_workaround(void);
+extern void r8a7740_init_delay(void);
 extern void r8a7740_init_irq(void);
+extern void r8a7740_init_irq_of(void);
 extern void r8a7740_map_io(void);
 extern void r8a7740_add_early_devices(void);
 extern void r8a7740_add_standard_devices(void);
+extern void r8a7740_add_standard_devices_dt(void);
 extern void r8a7740_clock_init(u8 md_ck);
 extern void r8a7740_pinmux_init(void);
 extern void r8a7740_pm_init(void);
diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c
index b741c8409a5a..8871f7717dc8 100644
--- a/arch/arm/mach-shmobile/intc-r8a7740.c
+++ b/arch/arm/mach-shmobile/intc-r8a7740.c
@@ -20,19 +20,15 @@
 
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/irqchip.h>
 #include <linux/irqchip/arm-gic.h>
 
-void __init r8a7740_init_irq(void)
+static void __init r8a7740_init_irq_common(void)
 {
-        void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000);
-        void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000);
         void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
         void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
         void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
 
-        /* initialize the Generic Interrupt Controller PL390 r0p0 */
-        gic_init(0, 29, gic_dist_base, gic_cpu_base);
-
         /* route signals to GIC */
         iowrite32(0x0, pfc_inta_ctrl);
 
@@ -54,3 +50,19 @@ void __init r8a7740_init_irq(void)
         iounmap(intc_msk_base);
         iounmap(pfc_inta_ctrl);
 }
+
+void __init r8a7740_init_irq_of(void)
+{
+        irqchip_init();
+        r8a7740_init_irq_common();
+}
+
+void __init r8a7740_init_irq(void)
+{
+        void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000);
+        void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000);
+
+        /* initialize the Generic Interrupt Controller PL390 r0p0 */
+        gic_init(0, 29, gic_dist_base, gic_cpu_base);
+        r8a7740_init_irq_common();
+}
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 3a6b6fe7b6c0..00c5a707238b 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -517,11 +517,7 @@ static struct platform_device ipmmu_device = {
         .num_resources  = ARRAY_SIZE(ipmmu_resources),
 };
 
-static struct platform_device *r8a7740_early_devices[] __initdata = {
-        &irqpin0_device,
-        &irqpin1_device,
-        &irqpin2_device,
-        &irqpin3_device,
+static struct platform_device *r8a7740_devices_dt[] __initdata = {
         &scif0_device,
         &scif1_device,
         &scif2_device,
@@ -532,6 +528,13 @@ static struct platform_device *r8a7740_early_devices[] __initdata = {
         &scif7_device,
         &scifb_device,
         &cmt10_device,
+};
+
+static struct platform_device *r8a7740_early_devices[] __initdata = {
+        &irqpin0_device,
+        &irqpin1_device,
+        &irqpin2_device,
+        &irqpin3_device,
         &tmu00_device,
         &tmu01_device,
         &tmu02_device,
@@ -951,6 +954,8 @@ void __init r8a7740_add_standard_devices(void)
         /* add devices */
         platform_add_devices(r8a7740_early_devices,
                             ARRAY_SIZE(r8a7740_early_devices));
+        platform_add_devices(r8a7740_devices_dt,
+                            ARRAY_SIZE(r8a7740_devices_dt));
         platform_add_devices(r8a7740_late_devices,
                              ARRAY_SIZE(r8a7740_late_devices));
 
@@ -972,6 +977,8 @@ void __init r8a7740_add_early_devices(void)
 {
         early_platform_add_devices(r8a7740_early_devices,
                                    ARRAY_SIZE(r8a7740_early_devices));
+        early_platform_add_devices(r8a7740_devices_dt,
+                                   ARRAY_SIZE(r8a7740_devices_dt));
 
         /* setup early console here as well */
         shmobile_setup_console();
@@ -979,33 +986,29 @@ void __init r8a7740_add_early_devices(void)
 
 #ifdef CONFIG_USE_OF
 
-void __init r8a7740_add_early_devices_dt(void)
-{
-        shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
-
-        early_platform_add_devices(r8a7740_early_devices,
-                                   ARRAY_SIZE(r8a7740_early_devices));
-
-        /* setup early console here as well */
-        shmobile_setup_console();
-}
-
 static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = {
         { }
 };
 
 void __init r8a7740_add_standard_devices_dt(void)
 {
-        /* clocks are setup late during boot in the case of DT */
-        r8a7740_clock_init(0);
-
-        platform_add_devices(r8a7740_early_devices,
-                            ARRAY_SIZE(r8a7740_early_devices));
-
+        platform_add_devices(r8a7740_devices_dt,
+                            ARRAY_SIZE(r8a7740_devices_dt));
         of_platform_populate(NULL, of_default_bus_match_table,
                              r8a7740_auxdata_lookup, NULL);
 }
 
+void __init r8a7740_init_delay(void)
+{
+        shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
+};
+
+static void __init r8a7740_generic_init(void)
+{
+        r8a7740_clock_init(0);
+        r8a7740_add_standard_devices_dt();
+}
+
 static const char *r8a7740_boards_compat_dt[] __initdata = {
         "renesas,r8a7740",
         NULL,
@@ -1013,9 +1016,10 @@ static const char *r8a7740_boards_compat_dt[] __initdata = {
 
 DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
         .map_io         = r8a7740_map_io,
-        .init_early     = r8a7740_add_early_devices_dt,
-        .init_irq       = r8a7740_init_irq,
-        .init_machine   = r8a7740_add_standard_devices_dt,
+        .init_early     = r8a7740_init_delay,
+        .init_irq       = r8a7740_init_irq_of,
+        .init_machine   = r8a7740_generic_init,
+        .init_time      = shmobile_timer_init,
         .dt_compat      = r8a7740_boards_compat_dt,
 MACHINE_END
 
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 46cca52890bc..7669a49fb6fb 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -274,11 +274,16 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL),
         OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL),
         OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
+        OF_DEV_AUXDATA("stericsson,db8500-musb", 0xa03e0000, "musb-ux500.0", NULL),
         OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
                         &db8500_prcmu_pdata),
         OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x.0", NULL),
+        OF_DEV_AUXDATA("stericsson,ux500-cryp", 0xa03cb000, "cryp1", NULL),
+        OF_DEV_AUXDATA("stericsson,ux500-hash", 0xa03c2000, "hash1", NULL),
+        OF_DEV_AUXDATA("stericsson,snd-soc-mop500", 0, "snd-soc-mop500.0",
+                        NULL),
         /* Requires device name bindings. */
-        OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE,
+        OF_DEV_AUXDATA("stericsson,db8500-pinctrl", U8500_PRCMU_BASE,
                 "pinctrl-db8500", NULL),
         /* Requires clock name and DMA bindings. */
         OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
@@ -292,6 +297,16 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
         {},
 };
 
+static struct of_dev_auxdata u8540_auxdata_lookup[] __initdata = {
+        /* Requires DMA bindings. */
+        OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", NULL),
+        OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL),
+        OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL),
+        OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
+                        &db8500_prcmu_pdata),
+        {},
+};
+
 static const struct of_device_id u8500_local_bus_nodes[] = {
         /* only create devices below soc node */
         { .compatible = "stericsson,db8500", },
@@ -318,8 +333,13 @@ static void __init u8500_init_machine(void)
         /* TODO: Export SoC, USB, cpu-freq and DMA40 */
         parent = u8500_of_init_devices();
 
-        /* automatically probe child nodes of db8500 device */
-        of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent);
+        /* automatically probe child nodes of dbx5x0 devices */
+        if (of_machine_is_compatible("st-ericsson,u8540"))
+                of_platform_populate(NULL, u8500_local_bus_nodes,
+                                     u8540_auxdata_lookup, parent);
+        else
+                of_platform_populate(NULL, u8500_local_bus_nodes,
+                                     u8500_auxdata_lookup, parent);
 }
 
 static const char * stericsson_dt_platform_compat[] = {
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 4c0199b88a04..4130e65a0e3f 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -97,7 +97,6 @@ static void zynq_system_reset(char mode, const char *cmd)
 }
 
 static const char * const zynq_dt_match[] = {
-        "xlnx,zynq-zc702",
         "xlnx,zynq-7000",
         NULL
 };