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Diffstat (limited to 'arch/arm/boot/dts/imx53-mba53.dts')
-rw-r--r--arch/arm/boot/dts/imx53-mba53.dts175
1 files changed, 138 insertions, 37 deletions
diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts
index 445a01119cc5..aaa33bc99f78 100644
--- a/arch/arm/boot/dts/imx53-mba53.dts
+++ b/arch/arm/boot/dts/imx53-mba53.dts
@@ -16,27 +16,81 @@
16/ { 16/ {
17 model = "TQ MBa53 starter kit"; 17 model = "TQ MBa53 starter kit";
18 compatible = "tq,mba53", "tq,tqma53", "fsl,imx53"; 18 compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
19
20 reg_backlight: fixed@0 {
21 compatible = "regulator-fixed";
22 regulator-name = "lcd-supply";
23 gpio = <&gpio2 5 0>;
24 startup-delay-us = <5000>;
25 enable-active-low;
26 };
27
28 backlight {
29 compatible = "pwm-backlight";
30 pwms = <&pwm2 0 50000 0 0>;
31 brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>;
32 default-brightness-level = <10>;
33 enable-gpios = <&gpio7 7 0>;
34 power-supply = <&reg_backlight>;
35 };
36
37 disp1: display@disp1 {
38 compatible = "fsl,imx-parallel-display";
39 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_disp1_1>;
41 crtcs = <&ipu 1>;
42 interface-pix-fmt = "rgb24";
43 status = "disabled";
44 };
45
46 reg_3p2v: 3p2v {
47 compatible = "regulator-fixed";
48 regulator-name = "3P2V";
49 regulator-min-microvolt = <3200000>;
50 regulator-max-microvolt = <3200000>;
51 regulator-always-on;
52 };
53
54 sound {
55 compatible = "tq,imx53-mba53-sgtl5000",
56 "fsl,imx-audio-sgtl5000";
57 model = "imx53-mba53-sgtl5000";
58 ssi-controller = <&ssi2>;
59 audio-codec = <&codec>;
60 audio-routing =
61 "MIC_IN", "Mic Jack",
62 "Mic Jack", "Mic Bias",
63 "Headphone Jack", "HP_OUT";
64 mux-int-port = <2>;
65 mux-ext-port = <5>;
66 };
67};
68
69&ldb {
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_lvds1_1>;
72 status = "disabled";
19}; 73};
20 74
21&iomuxc { 75&iomuxc {
22 lvds1 { 76 lvds1 {
23 pinctrl_lvds1_1: lvds1-grp1 { 77 pinctrl_lvds1_1: lvds1-grp1 {
24 fsl,pins = < 78 fsl,pins = <
25 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x10000 79 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
26 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x10000 80 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
27 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x10000 81 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
28 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x10000 82 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
29 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x10000 83 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
30 >; 84 >;
31 }; 85 };
32 86
33 pinctrl_lvds1_2: lvds1-grp2 { 87 pinctrl_lvds1_2: lvds1-grp2 {
34 fsl,pins = < 88 fsl,pins = <
35 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x10000 89 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
36 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x10000 90 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
37 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x10000 91 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
38 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x10000 92 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
39 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x10000 93 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
40 >; 94 >;
41 }; 95 };
42 }; 96 };
@@ -44,33 +98,44 @@
44 disp1 { 98 disp1 {
45 pinctrl_disp1_1: disp1-grp1 { 99 pinctrl_disp1_1: disp1-grp1 {
46 fsl,pins = < 100 fsl,pins = <
47 MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x10000 /* DISP1_DRDY */ 101 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */
48 MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x10000 /* DISP1_HSYNC */ 102 MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x80000000 /* DISP1_DRDY */
49 MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x10000 /* DISP1_VSYNC */ 103 MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x80000000 /* DISP1_HSYNC */
50 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x10000 104 MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x80000000 /* DISP1_VSYNC */
51 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x10000 105 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000
52 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x10000 106 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000
53 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x10000 107 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000
54 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x10000 108 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000
55 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x10000 109 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000
56 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x10000 110 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000
57 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x10000 111 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000
58 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x10000 112 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000
59 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x10000 113 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000
60 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x10000 114 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000
61 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x10000 115 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000
62 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x10000 116 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000
63 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x10000 117 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000
64 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x10000 118 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000
65 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x10000 119 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x80000000
66 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x10000 120 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x80000000
67 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x10000 121 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x80000000
68 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x10000 122 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x80000000
69 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x10000 123 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x80000000
70 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x10000 124 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x80000000
71 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x10000 125 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x80000000
72 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x10000 126 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x80000000
73 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x10000 127 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x80000000
128 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x80000000
129 >;
130 };
131 };
132
133 tve {
134 pinctrl_vga_sync_1: vgasync-grp1 {
135 fsl,pins = <
136 /* VGA_VSYNC, HSYNC with max drive strength */
137 MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0xe6
138 MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0xe6
74 >; 139 >;
75 }; 140 };
76 }; 141 };
@@ -80,16 +145,27 @@
80 status = "okay"; 145 status = "okay";
81}; 146};
82 147
148&audmux {
149 status = "okay";
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_audmux_1>;
152};
153
83&i2c2 { 154&i2c2 {
84 codec: sgtl5000@a { 155 codec: sgtl5000@a {
85 compatible = "fsl,sgtl5000"; 156 compatible = "fsl,sgtl5000";
86 reg = <0x0a>; 157 reg = <0x0a>;
158 clocks = <&clks 150>;
159 VDDA-supply = <&reg_3p2v>;
160 VDDIO-supply = <&reg_3p2v>;
87 }; 161 };
88 162
89 expander: pca9554@20 { 163 expander: pca9554@20 {
90 compatible = "pca9554"; 164 compatible = "pca9554";
91 reg = <0x20>; 165 reg = <0x20>;
92 interrupts = <109>; 166 interrupts = <109>;
167 #gpio-cells = <2>;
168 gpio-controller;
93 }; 169 };
94 170
95 sensor2: lm75@49 { 171 sensor2: lm75@49 {
@@ -99,6 +175,7 @@
99}; 175};
100 176
101&fec { 177&fec {
178 phy-reset-gpios = <&gpio7 6 0>;
102 status = "okay"; 179 status = "okay";
103}; 180};
104 181
@@ -114,10 +191,24 @@
114 status = "okay"; 191 status = "okay";
115}; 192};
116 193
194&usbotg {
195 dr_mode = "host";
196 status = "okay";
197};
198
199&usbh1 {
200 status = "okay";
201};
202
117&uart1 { 203&uart1 {
118 status = "okay"; 204 status = "okay";
119}; 205};
120 206
207&ssi2 {
208 fsl,mode = "i2s-slave";
209 status = "okay";
210};
211
121&uart2 { 212&uart2 {
122 status = "okay"; 213 status = "okay";
123}; 214};
@@ -133,3 +224,13 @@
133&i2c3 { 224&i2c3 {
134 status = "okay"; 225 status = "okay";
135}; 226};
227
228&tve {
229 pinctrl-names = "default";
230 pinctrl-0 = <&pinctrl_vga_sync_1>;
231 ddc = <&i2c3>;
232 fsl,tve-mode = "vga";
233 fsl,hsync-pin = <4>;
234 fsl,vsync-pin = <6>;
235 status = "okay";
236};
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-12 00:26:34 -0400