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-rw-r--r--arch/arm/boot/dts/tegra114.dtsi277
1 files changed, 179 insertions, 98 deletions
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 629415ffd8dc..abf6c40d28c6 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -1,4 +1,8 @@
1/include/ "skeleton.dtsi" 1#include <dt-bindings/clock/tegra114-car.h>
2#include <dt-bindings/gpio/tegra-gpio.h>
3#include <dt-bindings/interrupt-controller/arm-gic.h>
4
5#include "skeleton.dtsi"
2 6
3/ { 7/ {
4 compatible = "nvidia,tegra114"; 8 compatible = "nvidia,tegra114";
@@ -19,19 +23,20 @@
19 <0x50042000 0x1000>, 23 <0x50042000 0x1000>,
20 <0x50044000 0x2000>, 24 <0x50044000 0x2000>,
21 <0x50046000 0x2000>; 25 <0x50046000 0x2000>;
22 interrupts = <1 9 0xf04>; 26 interrupts = <GIC_PPI 9
27 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
23 }; 28 };
24 29
25 timer@60005000 { 30 timer@60005000 {
26 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer"; 31 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
27 reg = <0x60005000 0x400>; 32 reg = <0x60005000 0x400>;
28 interrupts = <0 0 0x04 33 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
29 0 1 0x04 34 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
30 0 41 0x04 35 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
31 0 42 0x04 36 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
32 0 121 0x04 37 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
33 0 122 0x04>; 38 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
34 clocks = <&tegra_car 5>; 39 clocks = <&tegra_car TEGRA114_CLK_TIMER>;
35 }; 40 };
36 41
37 tegra_car: clock { 42 tegra_car: clock {
@@ -43,39 +48,39 @@
43 apbdma: dma { 48 apbdma: dma {
44 compatible = "nvidia,tegra114-apbdma"; 49 compatible = "nvidia,tegra114-apbdma";
45 reg = <0x6000a000 0x1400>; 50 reg = <0x6000a000 0x1400>;
46 interrupts = <0 104 0x04 51 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
47 0 105 0x04 52 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
48 0 106 0x04 53 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
49 0 107 0x04 54 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
50 0 108 0x04 55 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
51 0 109 0x04 56 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
52 0 110 0x04 57 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
53 0 111 0x04 58 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
54 0 112 0x04 59 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
55 0 113 0x04 60 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
56 0 114 0x04 61 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
57 0 115 0x04 62 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
58 0 116 0x04 63 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
59 0 117 0x04 64 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
60 0 118 0x04 65 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
61 0 119 0x04 66 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
62 0 128 0x04 67 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
63 0 129 0x04 68 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
64 0 130 0x04 69 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
65 0 131 0x04 70 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
66 0 132 0x04 71 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
67 0 133 0x04 72 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
68 0 134 0x04 73 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
69 0 135 0x04 74 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
70 0 136 0x04 75 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
71 0 137 0x04 76 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
72 0 138 0x04 77 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
73 0 139 0x04 78 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
74 0 140 0x04 79 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
75 0 141 0x04 80 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
76 0 142 0x04 81 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
77 0 143 0x04>; 82 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
78 clocks = <&tegra_car 34>; 83 clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
79 }; 84 };
80 85
81 ahb: ahb { 86 ahb: ahb {
@@ -86,14 +91,14 @@
86 gpio: gpio { 91 gpio: gpio {
87 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; 92 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
88 reg = <0x6000d000 0x1000>; 93 reg = <0x6000d000 0x1000>;
89 interrupts = <0 32 0x04 94 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
90 0 33 0x04 95 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
91 0 34 0x04 96 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
92 0 35 0x04 97 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
93 0 55 0x04 98 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
94 0 87 0x04 99 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
95 0 89 0x04 100 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
96 0 125 0x04>; 101 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
97 #gpio-cells = <2>; 102 #gpio-cells = <2>;
98 gpio-controller; 103 gpio-controller;
99 #interrupt-cells = <2>; 104 #interrupt-cells = <2>;
@@ -118,57 +123,57 @@
118 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 123 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
119 reg = <0x70006000 0x40>; 124 reg = <0x70006000 0x40>;
120 reg-shift = <2>; 125 reg-shift = <2>;
121 interrupts = <0 36 0x04>; 126 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
122 nvidia,dma-request-selector = <&apbdma 8>; 127 nvidia,dma-request-selector = <&apbdma 8>;
123 status = "disabled"; 128 status = "disabled";
124 clocks = <&tegra_car 6>; 129 clocks = <&tegra_car TEGRA114_CLK_UARTA>;
125 }; 130 };
126 131
127 uartb: serial@70006040 { 132 uartb: serial@70006040 {
128 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 133 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
129 reg = <0x70006040 0x40>; 134 reg = <0x70006040 0x40>;
130 reg-shift = <2>; 135 reg-shift = <2>;
131 interrupts = <0 37 0x04>; 136 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
132 nvidia,dma-request-selector = <&apbdma 9>; 137 nvidia,dma-request-selector = <&apbdma 9>;
133 status = "disabled"; 138 status = "disabled";
134 clocks = <&tegra_car 192>; 139 clocks = <&tegra_car TEGRA114_CLK_UARTB>;
135 }; 140 };
136 141
137 uartc: serial@70006200 { 142 uartc: serial@70006200 {
138 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 143 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
139 reg = <0x70006200 0x100>; 144 reg = <0x70006200 0x100>;
140 reg-shift = <2>; 145 reg-shift = <2>;
141 interrupts = <0 46 0x04>; 146 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
142 nvidia,dma-request-selector = <&apbdma 10>; 147 nvidia,dma-request-selector = <&apbdma 10>;
143 status = "disabled"; 148 status = "disabled";
144 clocks = <&tegra_car 55>; 149 clocks = <&tegra_car TEGRA114_CLK_UARTC>;
145 }; 150 };
146 151
147 uartd: serial@70006300 { 152 uartd: serial@70006300 {
148 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 153 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
149 reg = <0x70006300 0x100>; 154 reg = <0x70006300 0x100>;
150 reg-shift = <2>; 155 reg-shift = <2>;
151 interrupts = <0 90 0x04>; 156 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
152 nvidia,dma-request-selector = <&apbdma 19>; 157 nvidia,dma-request-selector = <&apbdma 19>;
153 status = "disabled"; 158 status = "disabled";
154 clocks = <&tegra_car 65>; 159 clocks = <&tegra_car TEGRA114_CLK_UARTD>;
155 }; 160 };
156 161
157 pwm: pwm { 162 pwm: pwm {
158 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; 163 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
159 reg = <0x7000a000 0x100>; 164 reg = <0x7000a000 0x100>;
160 #pwm-cells = <2>; 165 #pwm-cells = <2>;
161 clocks = <&tegra_car 17>; 166 clocks = <&tegra_car TEGRA114_CLK_PWM>;
162 status = "disabled"; 167 status = "disabled";
163 }; 168 };
164 169
165 i2c@7000c000 { 170 i2c@7000c000 {
166 compatible = "nvidia,tegra114-i2c"; 171 compatible = "nvidia,tegra114-i2c";
167 reg = <0x7000c000 0x100>; 172 reg = <0x7000c000 0x100>;
168 interrupts = <0 38 0x04>; 173 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
169 #address-cells = <1>; 174 #address-cells = <1>;
170 #size-cells = <0>; 175 #size-cells = <0>;
171 clocks = <&tegra_car 12>; 176 clocks = <&tegra_car TEGRA114_CLK_I2C1>;
172 clock-names = "div-clk"; 177 clock-names = "div-clk";
173 status = "disabled"; 178 status = "disabled";
174 }; 179 };
@@ -176,10 +181,10 @@
176 i2c@7000c400 { 181 i2c@7000c400 {
177 compatible = "nvidia,tegra114-i2c"; 182 compatible = "nvidia,tegra114-i2c";
178 reg = <0x7000c400 0x100>; 183 reg = <0x7000c400 0x100>;
179 interrupts = <0 84 0x04>; 184 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
180 #address-cells = <1>; 185 #address-cells = <1>;
181 #size-cells = <0>; 186 #size-cells = <0>;
182 clocks = <&tegra_car 54>; 187 clocks = <&tegra_car TEGRA114_CLK_I2C2>;
183 clock-names = "div-clk"; 188 clock-names = "div-clk";
184 status = "disabled"; 189 status = "disabled";
185 }; 190 };
@@ -187,10 +192,10 @@
187 i2c@7000c500 { 192 i2c@7000c500 {
188 compatible = "nvidia,tegra114-i2c"; 193 compatible = "nvidia,tegra114-i2c";
189 reg = <0x7000c500 0x100>; 194 reg = <0x7000c500 0x100>;
190 interrupts = <0 92 0x04>; 195 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
191 #address-cells = <1>; 196 #address-cells = <1>;
192 #size-cells = <0>; 197 #size-cells = <0>;
193 clocks = <&tegra_car 67>; 198 clocks = <&tegra_car TEGRA114_CLK_I2C3>;
194 clock-names = "div-clk"; 199 clock-names = "div-clk";
195 status = "disabled"; 200 status = "disabled";
196 }; 201 };
@@ -198,10 +203,10 @@
198 i2c@7000c700 { 203 i2c@7000c700 {
199 compatible = "nvidia,tegra114-i2c"; 204 compatible = "nvidia,tegra114-i2c";
200 reg = <0x7000c700 0x100>; 205 reg = <0x7000c700 0x100>;
201 interrupts = <0 120 0x04>; 206 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
202 #address-cells = <1>; 207 #address-cells = <1>;
203 #size-cells = <0>; 208 #size-cells = <0>;
204 clocks = <&tegra_car 103>; 209 clocks = <&tegra_car TEGRA114_CLK_I2C4>;
205 clock-names = "div-clk"; 210 clock-names = "div-clk";
206 status = "disabled"; 211 status = "disabled";
207 }; 212 };
@@ -209,10 +214,10 @@
209 i2c@7000d000 { 214 i2c@7000d000 {
210 compatible = "nvidia,tegra114-i2c"; 215 compatible = "nvidia,tegra114-i2c";
211 reg = <0x7000d000 0x100>; 216 reg = <0x7000d000 0x100>;
212 interrupts = <0 53 0x04>; 217 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
213 #address-cells = <1>; 218 #address-cells = <1>;
214 #size-cells = <0>; 219 #size-cells = <0>;
215 clocks = <&tegra_car 47>; 220 clocks = <&tegra_car TEGRA114_CLK_I2C5>;
216 clock-names = "div-clk"; 221 clock-names = "div-clk";
217 status = "disabled"; 222 status = "disabled";
218 }; 223 };
@@ -220,11 +225,11 @@
220 spi@7000d400 { 225 spi@7000d400 {
221 compatible = "nvidia,tegra114-spi"; 226 compatible = "nvidia,tegra114-spi";
222 reg = <0x7000d400 0x200>; 227 reg = <0x7000d400 0x200>;
223 interrupts = <0 59 0x04>; 228 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
224 nvidia,dma-request-selector = <&apbdma 15>; 229 nvidia,dma-request-selector = <&apbdma 15>;
225 #address-cells = <1>; 230 #address-cells = <1>;
226 #size-cells = <0>; 231 #size-cells = <0>;
227 clocks = <&tegra_car 41>; 232 clocks = <&tegra_car TEGRA114_CLK_SBC1>;
228 clock-names = "spi"; 233 clock-names = "spi";
229 status = "disabled"; 234 status = "disabled";
230 }; 235 };
@@ -232,11 +237,11 @@
232 spi@7000d600 { 237 spi@7000d600 {
233 compatible = "nvidia,tegra114-spi"; 238 compatible = "nvidia,tegra114-spi";
234 reg = <0x7000d600 0x200>; 239 reg = <0x7000d600 0x200>;
235 interrupts = <0 82 0x04>; 240 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
236 nvidia,dma-request-selector = <&apbdma 16>; 241 nvidia,dma-request-selector = <&apbdma 16>;
237 #address-cells = <1>; 242 #address-cells = <1>;
238 #size-cells = <0>; 243 #size-cells = <0>;
239 clocks = <&tegra_car 44>; 244 clocks = <&tegra_car TEGRA114_CLK_SBC2>;
240 clock-names = "spi"; 245 clock-names = "spi";
241 status = "disabled"; 246 status = "disabled";
242 }; 247 };
@@ -244,11 +249,11 @@
244 spi@7000d800 { 249 spi@7000d800 {
245 compatible = "nvidia,tegra114-spi"; 250 compatible = "nvidia,tegra114-spi";
246 reg = <0x7000d800 0x200>; 251 reg = <0x7000d800 0x200>;
247 interrupts = <0 83 0x04>; 252 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
248 nvidia,dma-request-selector = <&apbdma 17>; 253 nvidia,dma-request-selector = <&apbdma 17>;
249 #address-cells = <1>; 254 #address-cells = <1>;
250 #size-cells = <0>; 255 #size-cells = <0>;
251 clocks = <&tegra_car 46>; 256 clocks = <&tegra_car TEGRA114_CLK_SBC3>;
252 clock-names = "spi"; 257 clock-names = "spi";
253 status = "disabled"; 258 status = "disabled";
254 }; 259 };
@@ -256,11 +261,11 @@
256 spi@7000da00 { 261 spi@7000da00 {
257 compatible = "nvidia,tegra114-spi"; 262 compatible = "nvidia,tegra114-spi";
258 reg = <0x7000da00 0x200>; 263 reg = <0x7000da00 0x200>;
259 interrupts = <0 93 0x04>; 264 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
260 nvidia,dma-request-selector = <&apbdma 18>; 265 nvidia,dma-request-selector = <&apbdma 18>;
261 #address-cells = <1>; 266 #address-cells = <1>;
262 #size-cells = <0>; 267 #size-cells = <0>;
263 clocks = <&tegra_car 68>; 268 clocks = <&tegra_car TEGRA114_CLK_SBC4>;
264 clock-names = "spi"; 269 clock-names = "spi";
265 status = "disabled"; 270 status = "disabled";
266 }; 271 };
@@ -268,11 +273,11 @@
268 spi@7000dc00 { 273 spi@7000dc00 {
269 compatible = "nvidia,tegra114-spi"; 274 compatible = "nvidia,tegra114-spi";
270 reg = <0x7000dc00 0x200>; 275 reg = <0x7000dc00 0x200>;
271 interrupts = <0 94 0x04>; 276 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
272 nvidia,dma-request-selector = <&apbdma 27>; 277 nvidia,dma-request-selector = <&apbdma 27>;
273 #address-cells = <1>; 278 #address-cells = <1>;
274 #size-cells = <0>; 279 #size-cells = <0>;
275 clocks = <&tegra_car 104>; 280 clocks = <&tegra_car TEGRA114_CLK_SBC5>;
276 clock-names = "spi"; 281 clock-names = "spi";
277 status = "disabled"; 282 status = "disabled";
278 }; 283 };
@@ -280,11 +285,11 @@
280 spi@7000de00 { 285 spi@7000de00 {
281 compatible = "nvidia,tegra114-spi"; 286 compatible = "nvidia,tegra114-spi";
282 reg = <0x7000de00 0x200>; 287 reg = <0x7000de00 0x200>;
283 interrupts = <0 79 0x04>; 288 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
284 nvidia,dma-request-selector = <&apbdma 28>; 289 nvidia,dma-request-selector = <&apbdma 28>;
285 #address-cells = <1>; 290 #address-cells = <1>;
286 #size-cells = <0>; 291 #size-cells = <0>;
287 clocks = <&tegra_car 105>; 292 clocks = <&tegra_car TEGRA114_CLK_SBC6>;
288 clock-names = "spi"; 293 clock-names = "spi";
289 status = "disabled"; 294 status = "disabled";
290 }; 295 };
@@ -292,22 +297,22 @@
292 rtc { 297 rtc {
293 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; 298 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
294 reg = <0x7000e000 0x100>; 299 reg = <0x7000e000 0x100>;
295 interrupts = <0 2 0x04>; 300 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&tegra_car 4>; 301 clocks = <&tegra_car TEGRA114_CLK_RTC>;
297 }; 302 };
298 303
299 kbc { 304 kbc {
300 compatible = "nvidia,tegra114-kbc"; 305 compatible = "nvidia,tegra114-kbc";
301 reg = <0x7000e200 0x100>; 306 reg = <0x7000e200 0x100>;
302 interrupts = <0 85 0x04>; 307 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&tegra_car 36>; 308 clocks = <&tegra_car TEGRA114_CLK_KBC>;
304 status = "disabled"; 309 status = "disabled";
305 }; 310 };
306 311
307 pmc { 312 pmc {
308 compatible = "nvidia,tegra114-pmc"; 313 compatible = "nvidia,tegra114-pmc";
309 reg = <0x7000e400 0x400>; 314 reg = <0x7000e400 0x400>;
310 clocks = <&tegra_car 261>, <&clk32k_in>; 315 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
311 clock-names = "pclk", "clk32k_in"; 316 clock-names = "pclk", "clk32k_in";
312 }; 317 };
313 318
@@ -322,35 +327,106 @@
322 nvidia,ahb = <&ahb>; 327 nvidia,ahb = <&ahb>;
323 }; 328 };
324 329
330 ahub {
331 compatible = "nvidia,tegra114-ahub";
332 reg = <0x70080000 0x200>,
333 <0x70080200 0x100>,
334 <0x70081000 0x200>;
335 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
336 nvidia,dma-request-selector = <&apbdma 1>, <&apbdma 2>,
337 <&apbdma 3>, <&apbdma 4>, <&apbdma 6>, <&apbdma 7>,
338 <&apbdma 12>, <&apbdma 13>, <&apbdma 14>,
339 <&apbdma 29>;
340 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
341 <&tegra_car TEGRA114_CLK_APBIF>,
342 <&tegra_car TEGRA114_CLK_I2S0>,
343 <&tegra_car TEGRA114_CLK_I2S1>,
344 <&tegra_car TEGRA114_CLK_I2S2>,
345 <&tegra_car TEGRA114_CLK_I2S3>,
346 <&tegra_car TEGRA114_CLK_I2S4>,
347 <&tegra_car TEGRA114_CLK_DAM0>,
348 <&tegra_car TEGRA114_CLK_DAM1>,
349 <&tegra_car TEGRA114_CLK_DAM2>,
350 <&tegra_car TEGRA114_CLK_SPDIF_IN>,
351 <&tegra_car TEGRA114_CLK_AMX>,
352 <&tegra_car TEGRA114_CLK_ADX>;
353 clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
354 "i2s3", "i2s4", "dam0", "dam1", "dam2",
355 "spdif_in", "amx", "adx";
356 ranges;
357 #address-cells = <1>;
358 #size-cells = <1>;
359
360 tegra_i2s0: i2s@70080300 {
361 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
362 reg = <0x70080300 0x100>;
363 nvidia,ahub-cif-ids = <4 4>;
364 clocks = <&tegra_car TEGRA114_CLK_I2S0>;
365 status = "disabled";
366 };
367
368 tegra_i2s1: i2s@70080400 {
369 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
370 reg = <0x70080400 0x100>;
371 nvidia,ahub-cif-ids = <5 5>;
372 clocks = <&tegra_car TEGRA114_CLK_I2S1>;
373 status = "disabled";
374 };
375
376 tegra_i2s2: i2s@70080500 {
377 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
378 reg = <0x70080500 0x100>;
379 nvidia,ahub-cif-ids = <6 6>;
380 clocks = <&tegra_car TEGRA114_CLK_I2S2>;
381 status = "disabled";
382 };
383
384 tegra_i2s3: i2s@70080600 {
385 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
386 reg = <0x70080600 0x100>;
387 nvidia,ahub-cif-ids = <7 7>;
388 clocks = <&tegra_car TEGRA114_CLK_I2S3>;
389 status = "disabled";
390 };
391
392 tegra_i2s4: i2s@70080700 {
393 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
394 reg = <0x70080700 0x100>;
395 nvidia,ahub-cif-ids = <8 8>;
396 clocks = <&tegra_car TEGRA114_CLK_I2S4>;
397 status = "disabled";
398 };
399 };
400
325 sdhci@78000000 { 401 sdhci@78000000 {
326 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; 402 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
327 reg = <0x78000000 0x200>; 403 reg = <0x78000000 0x200>;
328 interrupts = <0 14 0x04>; 404 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&tegra_car 14>; 405 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
330 status = "disable"; 406 status = "disable";
331 }; 407 };
332 408
333 sdhci@78000200 { 409 sdhci@78000200 {
334 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; 410 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
335 reg = <0x78000200 0x200>; 411 reg = <0x78000200 0x200>;
336 interrupts = <0 15 0x04>; 412 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&tegra_car 9>; 413 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
338 status = "disable"; 414 status = "disable";
339 }; 415 };
340 416
341 sdhci@78000400 { 417 sdhci@78000400 {
342 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; 418 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
343 reg = <0x78000400 0x200>; 419 reg = <0x78000400 0x200>;
344 interrupts = <0 19 0x04>; 420 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&tegra_car 69>; 421 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
346 status = "disable"; 422 status = "disable";
347 }; 423 };
348 424
349 sdhci@78000600 { 425 sdhci@78000600 {
350 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; 426 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
351 reg = <0x78000600 0x200>; 427 reg = <0x78000600 0x200>;
352 interrupts = <0 31 0x04>; 428 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&tegra_car 15>; 429 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
354 status = "disable"; 430 status = "disable";
355 }; 431 };
356 432
@@ -385,9 +461,14 @@
385 461
386 timer { 462 timer {
387 compatible = "arm,armv7-timer"; 463 compatible = "arm,armv7-timer";
388 interrupts = <1 13 0xf08>, 464 interrupts =
389 <1 14 0xf08>, 465 <GIC_PPI 13
390 <1 11 0xf08>, 466 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
391 <1 10 0xf08>; 467 <GIC_PPI 14
468 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
469 <GIC_PPI 11
470 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
471 <GIC_PPI 10
472 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
392 }; 473 };
393}; 474};
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-12 00:27:09 -0400