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-rw-r--r--arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi74
1 files changed, 74 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
new file mode 100644
index 000000000000..f5e1981025ed
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
@@ -0,0 +1,74 @@
1/*
2 * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include "imx6q.dtsi"
13
14/ {
15 model = "Phytec phyFLEX-i.MX6 Ouad";
16 compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
17
18 memory {
19 reg = <0x10000000 0x80000000>;
20 };
21};
22
23&iomuxc {
24 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_hog>;
26
27 hog {
28 pinctrl_hog: hoggrp {
29 fsl,pins = <
30 MX6Q_PAD_EIM_D23__GPIO3_IO23 0x80000000
31 >;
32 };
33 };
34
35 pfla02 {
36 pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 {
37 fsl,pins = <
38 MX6Q_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
39 MX6Q_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
40 >;
41 };
42 };
43};
44
45&fec {
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_enet_3>;
48 phy-mode = "rgmii";
49 phy-reset-gpios = <&gpio3 23 0>;
50 status = "disabled";
51};
52
53&uart4 {
54 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_uart4_1>;
56 status = "disabled";
57};
58
59&usdhc2 {
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_usdhc2_2>;
62 cd-gpios = <&gpio1 4 0>;
63 wp-gpios = <&gpio1 2 0>;
64 status = "disabled";
65};
66
67&usdhc3 {
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_usdhc3_2
70 &pinctrl_usdhc3_pfla02>;
71 cd-gpios = <&gpio1 27 0>;
72 wp-gpios = <&gpio1 29 0>;
73 status = "disabled";
74};