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authorLinus Torvalds <torvalds@linux-foundation.org>2013-07-13 17:52:21 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-07-13 17:52:21 -0400
commitd1447464789918db1e1a3d0aaf50d3d0f6487a4f (patch)
tree490bd5c493cdba742dc90d3731962226838e5f33 /arch
parent833e68340d108d88f4cb79b7d7223f6859d362ca (diff)
parent6ac5310e649df5fcd240d764503bf16a1317ea39 (diff)
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle: "MIPS updates: - All the things that didn't make 3.10. - Removes the Windriver PPMC platform. Nobody will miss it. - Remove a workaround from kernel/irq/irqdomain.c which was there exclusivly for MIPS. Patch by Grant Likely. - More small improvments for the SEAD 3 platform - Improvments on the BMIPS / SMP support for the BCM63xx series. - Various cleanups of dead leftovers. - Platform support for the Cavium Octeon-based EdgeRouter Lite. Two large KVM patchsets didn't make it for this pull request because their respective authors are vacationing" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (124 commits) MIPS: Kconfig: Add missing MODULES dependency to VPE_LOADER MIPS: BCM63xx: CLK: Add dummy clk_{set,round}_rate() functions MIPS: SEAD3: Disable L2 cache on SEAD-3. MIPS: BCM63xx: Enable second core SMP on BCM6328 if available MIPS: BCM63xx: Add SMP support to prom.c MIPS: define write{b,w,l,q}_relaxed MIPS: Expose missing pci_io{map,unmap} declarations MIPS: Malta: Update GCMP detection. Revert "MIPS: make CAC_ADDR and UNCAC_ADDR account for PHYS_OFFSET" MIPS: APSP: Remove <asm/kspd.h> SSB: Kconfig: Amend SSB_EMBEDDED dependencies MIPS: microMIPS: Fix improper definition of ISA exception bit. MIPS: Don't try to decode microMIPS branch instructions where they cannot exist. MIPS: Declare emulate_load_store_microMIPS as a static function. MIPS: Fix typos and cleanup comment MIPS: Cleanup indentation and whitespace MIPS: BMIPS: support booting from physical CPU other than 0 MIPS: Only set cpu_has_mmips if SYS_SUPPORTS_MICROMIPS MIPS: GIC: Fix gic_set_affinity infinite loop MIPS: Don't save/restore OCTEON wide multiplier state on syscalls. ...
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/Kbuild.platforms1
-rw-r--r--arch/mips/Kconfig76
-rw-r--r--arch/mips/Makefile4
-rw-r--r--arch/mips/ath79/mach-ap136.c2
-rw-r--r--arch/mips/bcm63xx/Kconfig9
-rw-r--r--arch/mips/bcm63xx/boards/board_bcm963xx.c53
-rw-r--r--arch/mips/bcm63xx/clk.c30
-rw-r--r--arch/mips/bcm63xx/cpu.c28
-rw-r--r--arch/mips/bcm63xx/dev-flash.c1
-rw-r--r--arch/mips/bcm63xx/dev-spi.c6
-rw-r--r--arch/mips/bcm63xx/dev-uart.c3
-rw-r--r--arch/mips/bcm63xx/irq.c23
-rw-r--r--arch/mips/bcm63xx/nvram.c10
-rw-r--r--arch/mips/bcm63xx/prom.c49
-rw-r--r--arch/mips/bcm63xx/reset.c29
-rw-r--r--arch/mips/bcm63xx/setup.c3
-rw-r--r--arch/mips/boot/compressed/Makefile2
-rw-r--r--arch/mips/boot/compressed/uart-16550.c22
-rw-r--r--arch/mips/cavium-octeon/Kconfig17
-rw-r--r--arch/mips/cavium-octeon/Makefile5
-rw-r--r--arch/mips/cavium-octeon/Platform8
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-helper-board.c13
-rw-r--r--arch/mips/cavium-octeon/octeon-platform.c9
-rw-r--r--arch/mips/cavium-octeon/serial.c109
-rw-r--r--arch/mips/cavium-octeon/setup.c32
-rw-r--r--arch/mips/configs/cavium_octeon_defconfig6
-rw-r--r--arch/mips/configs/wrppmc_defconfig97
-rw-r--r--arch/mips/dec/Makefile1
-rw-r--r--arch/mips/dec/promcon.c54
-rw-r--r--arch/mips/fw/cfe/cfe_api.c4
-rw-r--r--arch/mips/include/asm/cop2.h29
-rw-r--r--arch/mips/include/asm/cpu-features.h49
-rw-r--r--arch/mips/include/asm/cpu.h23
-rw-r--r--arch/mips/include/asm/fw/cfe/cfe_api.h4
-rw-r--r--arch/mips/include/asm/gic.h2
-rw-r--r--arch/mips/include/asm/io.h10
-rw-r--r--arch/mips/include/asm/kspd.h32
-rw-r--r--arch/mips/include/asm/mach-ar7/spaces.h7
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h112
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h1
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h52
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h6
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/ioremap.h4
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h7
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h7
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/spaces.h24
-rw-r--r--arch/mips/include/asm/mach-generic/dma-coherence.h12
-rw-r--r--arch/mips/include/asm/mach-generic/kernel-entry-init.h4
-rw-r--r--arch/mips/include/asm/mach-ip27/kernel-entry-init.h47
-rw-r--r--arch/mips/include/asm/mach-ip28/spaces.h9
-rw-r--r--arch/mips/include/asm/mach-pmcs-msp71xx/gpio.h46
-rw-r--r--arch/mips/include/asm/mach-wrppmc/mach-gt64120.h83
-rw-r--r--arch/mips/include/asm/mach-wrppmc/war.h24
-rw-r--r--arch/mips/include/asm/mips-boards/generic.h6
-rw-r--r--arch/mips/include/asm/mipsregs.h2
-rw-r--r--arch/mips/include/asm/mmu_context.h6
-rw-r--r--arch/mips/include/asm/netlogic/common.h21
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/pic.h2
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/xlp.h1
-rw-r--r--arch/mips/include/asm/netlogic/xlr/fmn.h12
-rw-r--r--arch/mips/include/asm/octeon/cvmx-bootinfo.h2
-rw-r--r--arch/mips/include/asm/page.h6
-rw-r--r--arch/mips/include/asm/pci.h1
-rw-r--r--arch/mips/include/asm/processor.h35
-rw-r--r--arch/mips/include/asm/stackframe.h29
-rw-r--r--arch/mips/include/asm/stackprotector.h40
-rw-r--r--arch/mips/include/asm/switch_to.h19
-rw-r--r--arch/mips/include/asm/thread_info.h11
-rw-r--r--arch/mips/include/asm/xtalk/xtalk.h9
-rw-r--r--arch/mips/include/uapi/asm/fcntl.h16
-rw-r--r--arch/mips/include/uapi/asm/inst.h9
-rw-r--r--arch/mips/include/uapi/asm/msgbuf.h12
-rw-r--r--arch/mips/include/uapi/asm/resource.h2
-rw-r--r--arch/mips/include/uapi/asm/siginfo.h4
-rw-r--r--arch/mips/include/uapi/asm/swab.h12
-rw-r--r--arch/mips/kernel/asm-offsets.c3
-rw-r--r--arch/mips/kernel/branch.c1
-rw-r--r--arch/mips/kernel/cpu-bugs64.c5
-rw-r--r--arch/mips/kernel/cpu-probe.c12
-rw-r--r--arch/mips/kernel/head.S39
-rw-r--r--arch/mips/kernel/irq-gic.c15
-rw-r--r--arch/mips/kernel/mcount.S4
-rw-r--r--arch/mips/kernel/octeon_switch.S34
-rw-r--r--arch/mips/kernel/proc.c4
-rw-r--r--arch/mips/kernel/process.c9
-rw-r--r--arch/mips/kernel/prom.c2
-rw-r--r--arch/mips/kernel/ptrace.c12
-rw-r--r--arch/mips/kernel/r2300_switch.S7
-rw-r--r--arch/mips/kernel/r4k_switch.S6
-rw-r--r--arch/mips/kernel/rtlx.c1
-rw-r--r--arch/mips/kernel/scall32-o32.S2
-rw-r--r--arch/mips/kernel/scall64-64.S2
-rw-r--r--arch/mips/kernel/scall64-n32.S2
-rw-r--r--arch/mips/kernel/scall64-o32.S2
-rw-r--r--arch/mips/kernel/signal.c5
-rw-r--r--arch/mips/kernel/smp-bmips.c29
-rw-r--r--arch/mips/kernel/traps.c104
-rw-r--r--arch/mips/kernel/unaligned.c8
-rw-r--r--arch/mips/kernel/watch.c8
-rw-r--r--arch/mips/lantiq/prom.c2
-rw-r--r--arch/mips/lasat/sysctl.c14
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_isa.c14
-rw-r--r--arch/mips/math-emu/cp1emu.c3
-rw-r--r--arch/mips/mm/Makefile2
-rw-r--r--arch/mips/mm/cerr-sb1.c4
-rw-r--r--arch/mips/mm/dma-default.c3
-rw-r--r--arch/mips/mm/fault.c15
-rw-r--r--arch/mips/mm/page.c2
-rw-r--r--arch/mips/mm/tlb-funcs.S37
-rw-r--r--arch/mips/mm/tlbex.c183
-rw-r--r--arch/mips/mti-malta/Makefile1
-rw-r--r--arch/mips/mti-malta/malta-int.c4
-rw-r--r--arch/mips/mti-malta/malta-reset.c33
-rw-r--r--arch/mips/mti-sead3/sead3-reset.c5
-rw-r--r--arch/mips/netlogic/Kconfig11
-rw-r--r--arch/mips/netlogic/common/Makefile2
-rw-r--r--arch/mips/netlogic/common/irq.c7
-rw-r--r--arch/mips/netlogic/common/nlm-dma.c107
-rw-r--r--arch/mips/netlogic/common/reset.S230
-rw-r--r--arch/mips/netlogic/common/smp.c18
-rw-r--r--arch/mips/netlogic/common/smpboot.S194
-rw-r--r--arch/mips/netlogic/xlp/Makefile2
-rw-r--r--arch/mips/netlogic/xlp/cop2-ex.c118
-rw-r--r--arch/mips/netlogic/xlp/dt.c99
-rw-r--r--arch/mips/netlogic/xlp/setup.c95
-rw-r--r--arch/mips/netlogic/xlp/wakeup.c26
-rw-r--r--arch/mips/netlogic/xlr/fmn.c18
-rw-r--r--arch/mips/netlogic/xlr/setup.c7
-rw-r--r--arch/mips/netlogic/xlr/wakeup.c3
-rw-r--r--arch/mips/pci/Makefile7
-rw-r--r--arch/mips/pci/fixup-wrppmc.c37
-rw-r--r--arch/mips/pci/pci-bcm63xx.c3
-rw-r--r--arch/mips/pci/pci-ip27.c2
-rw-r--r--arch/mips/pci/pci-malta.c (renamed from arch/mips/mti-malta/malta-pci.c)0
-rw-r--r--arch/mips/pmcs-msp71xx/Makefile1
-rw-r--r--arch/mips/pmcs-msp71xx/gpio.c216
-rw-r--r--arch/mips/pmcs-msp71xx/gpio_extended.c146
-rw-r--r--arch/mips/powertv/asic/asic_devices.c13
-rw-r--r--arch/mips/ralink/of.c2
-rw-r--r--arch/mips/sgi-ip27/Makefile1
-rw-r--r--arch/mips/sgi-ip27/ip27-irq-pci.c266
-rw-r--r--arch/mips/sgi-ip27/ip27-irq.c214
-rw-r--r--arch/mips/sibyte/Kconfig3
-rw-r--r--arch/mips/sibyte/Platform5
-rw-r--r--arch/mips/sibyte/common/Makefile1
-rw-r--r--arch/mips/sibyte/common/bus_watcher.c (renamed from arch/mips/sibyte/sb1250/bus_watcher.c)14
-rw-r--r--arch/mips/sibyte/common/sb_tbprof.c1
-rw-r--r--arch/mips/sibyte/sb1250/Makefile1
-rw-r--r--arch/mips/sni/pcimt.c2
-rw-r--r--arch/mips/sni/pcit.c16
-rw-r--r--arch/mips/wrppmc/Makefile12
-rw-r--r--arch/mips/wrppmc/Platform7
-rw-r--r--arch/mips/wrppmc/irq.c56
-rw-r--r--arch/mips/wrppmc/pci.c52
-rw-r--r--arch/mips/wrppmc/reset.c41
-rw-r--r--arch/mips/wrppmc/serial.c80
-rw-r--r--arch/mips/wrppmc/setup.c128
-rw-r--r--arch/mips/wrppmc/time.c39
158 files changed, 2189 insertions, 2309 deletions
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index 4b597d91a8d5..d9d81c219253 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -30,7 +30,6 @@ platforms += sibyte
30platforms += sni 30platforms += sni
31platforms += txx9 31platforms += txx9
32platforms += vr41xx 32platforms += vr41xx
33platforms += wrppmc
34 33
35# include the platform specific files 34# include the platform specific files
36include $(patsubst %, $(srctree)/arch/mips/%/Platform, $(platforms)) 35include $(patsubst %, $(srctree)/arch/mips/%/Platform, $(platforms))
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index beeff436b22f..4758a8fd3e99 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1,6 +1,7 @@
1config MIPS 1config MIPS
2 bool 2 bool
3 default y 3 default y
4 select HAVE_CONTEXT_TRACKING
4 select HAVE_GENERIC_DMA_COHERENT 5 select HAVE_GENERIC_DMA_COHERENT
5 select HAVE_IDE 6 select HAVE_IDE
6 select HAVE_OPROFILE 7 select HAVE_OPROFILE
@@ -27,6 +28,7 @@ config MIPS
27 select HAVE_GENERIC_HARDIRQS 28 select HAVE_GENERIC_HARDIRQS
28 select GENERIC_IRQ_PROBE 29 select GENERIC_IRQ_PROBE
29 select GENERIC_IRQ_SHOW 30 select GENERIC_IRQ_SHOW
31 select GENERIC_PCI_IOMAP
30 select HAVE_ARCH_JUMP_LABEL 32 select HAVE_ARCH_JUMP_LABEL
31 select ARCH_WANT_IPC_PARSE_VERSION 33 select ARCH_WANT_IPC_PARSE_VERSION
32 select IRQ_FORCED_THREADING 34 select IRQ_FORCED_THREADING
@@ -46,9 +48,6 @@ config MIPS
46 48
47menu "Machine selection" 49menu "Machine selection"
48 50
49config ZONE_DMA
50 bool
51
52choice 51choice
53 prompt "System type" 52 prompt "System type"
54 default SGI_IP22 53 default SGI_IP22
@@ -124,11 +123,14 @@ config BCM47XX
124 123
125config BCM63XX 124config BCM63XX
126 bool "Broadcom BCM63XX based boards" 125 bool "Broadcom BCM63XX based boards"
126 select BOOT_RAW
127 select CEVT_R4K 127 select CEVT_R4K
128 select CSRC_R4K 128 select CSRC_R4K
129 select DMA_NONCOHERENT 129 select DMA_NONCOHERENT
130 select IRQ_CPU 130 select IRQ_CPU
131 select SYS_HAS_CPU_MIPS32_R1 131 select SYS_HAS_CPU_MIPS32_R1
132 select SYS_HAS_CPU_BMIPS4350 if !BCM63XX_CPU_6338 && !BCM63XX_CPU_6345 && !BCM63XX_CPU_6348
133 select NR_CPUS_DEFAULT_2
132 select SYS_SUPPORTS_32BIT_KERNEL 134 select SYS_SUPPORTS_32BIT_KERNEL
133 select SYS_SUPPORTS_BIG_ENDIAN 135 select SYS_SUPPORTS_BIG_ENDIAN
134 select SYS_HAS_EARLY_PRINTK 136 select SYS_HAS_EARLY_PRINTK
@@ -341,7 +343,6 @@ config MIPS_SEAD3
341 select DMA_NONCOHERENT 343 select DMA_NONCOHERENT
342 select IRQ_CPU 344 select IRQ_CPU
343 select IRQ_GIC 345 select IRQ_GIC
344 select MIPS_CPU_SCACHE
345 select MIPS_MSC 346 select MIPS_MSC
346 select SYS_HAS_CPU_MIPS32_R1 347 select SYS_HAS_CPU_MIPS32_R1
347 select SYS_HAS_CPU_MIPS32_R2 348 select SYS_HAS_CPU_MIPS32_R2
@@ -420,7 +421,6 @@ config POWERTV
420 select CSRC_POWERTV 421 select CSRC_POWERTV
421 select DMA_NONCOHERENT 422 select DMA_NONCOHERENT
422 select HW_HAS_PCI 423 select HW_HAS_PCI
423 select SYS_HAS_EARLY_PRINTK
424 select SYS_HAS_CPU_MIPS32_R2 424 select SYS_HAS_CPU_MIPS32_R2
425 select SYS_SUPPORTS_32BIT_KERNEL 425 select SYS_SUPPORTS_32BIT_KERNEL
426 select SYS_SUPPORTS_BIG_ENDIAN 426 select SYS_SUPPORTS_BIG_ENDIAN
@@ -713,46 +713,8 @@ config MIKROTIK_RB532
713 Support the Mikrotik(tm) RouterBoard 532 series, 713 Support the Mikrotik(tm) RouterBoard 532 series,
714 based on the IDT RC32434 SoC. 714 based on the IDT RC32434 SoC.
715 715
716config WR_PPMC 716config CAVIUM_OCTEON_SOC
717 bool "Wind River PPMC board" 717 bool "Cavium Networks Octeon SoC based boards"
718 select CEVT_R4K
719 select CSRC_R4K
720 select IRQ_CPU
721 select BOOT_ELF32
722 select DMA_NONCOHERENT
723 select HW_HAS_PCI
724 select PCI_GT64XXX_PCI0
725 select SWAP_IO_SPACE
726 select SYS_HAS_CPU_MIPS32_R1
727 select SYS_HAS_CPU_MIPS32_R2
728 select SYS_HAS_CPU_MIPS64_R1
729 select SYS_HAS_CPU_NEVADA
730 select SYS_HAS_CPU_RM7000
731 select SYS_SUPPORTS_32BIT_KERNEL
732 select SYS_SUPPORTS_64BIT_KERNEL
733 select SYS_SUPPORTS_BIG_ENDIAN
734 select SYS_SUPPORTS_LITTLE_ENDIAN
735 help
736 This enables support for the Wind River MIPS32 4KC PPMC evaluation
737 board, which is based on GT64120 bridge chip.
738
739config CAVIUM_OCTEON_SIMULATOR
740 bool "Cavium Networks Octeon Simulator"
741 select CEVT_R4K
742 select 64BIT_PHYS_ADDR
743 select DMA_COHERENT
744 select SYS_SUPPORTS_64BIT_KERNEL
745 select SYS_SUPPORTS_BIG_ENDIAN
746 select SYS_SUPPORTS_HOTPLUG_CPU
747 select SYS_HAS_CPU_CAVIUM_OCTEON
748 select HOLES_IN_ZONE
749 help
750 The Octeon simulator is software performance model of the Cavium
751 Octeon Processor. It supports simulating Octeon processors on x86
752 hardware.
753
754config CAVIUM_OCTEON_REFERENCE_BOARD
755 bool "Cavium Networks Octeon reference board"
756 select CEVT_R4K 718 select CEVT_R4K
757 select 64BIT_PHYS_ADDR 719 select 64BIT_PHYS_ADDR
758 select DMA_COHERENT 720 select DMA_COHERENT
@@ -806,6 +768,8 @@ config NLM_XLR_BOARD
806 select SYS_HAS_EARLY_PRINTK 768 select SYS_HAS_EARLY_PRINTK
807 select USB_ARCH_HAS_OHCI if USB_SUPPORT 769 select USB_ARCH_HAS_OHCI if USB_SUPPORT
808 select USB_ARCH_HAS_EHCI if USB_SUPPORT 770 select USB_ARCH_HAS_EHCI if USB_SUPPORT
771 select SYS_SUPPORTS_ZBOOT
772 select SYS_SUPPORTS_ZBOOT_UART16550
809 help 773 help
810 Support for systems based on Netlogic XLR and XLS processors. 774 Support for systems based on Netlogic XLR and XLS processors.
811 Say Y here if you have a XLR or XLS based board. 775 Say Y here if you have a XLR or XLS based board.
@@ -832,6 +796,8 @@ config NLM_XLP_BOARD
832 select SYNC_R4K 796 select SYNC_R4K
833 select SYS_HAS_EARLY_PRINTK 797 select SYS_HAS_EARLY_PRINTK
834 select USE_OF 798 select USE_OF
799 select SYS_SUPPORTS_ZBOOT
800 select SYS_SUPPORTS_ZBOOT_UART16550
835 help 801 help
836 This board is based on Netlogic XLP Processor. 802 This board is based on Netlogic XLP Processor.
837 Say Y here if you have a XLP based board. 803 Say Y here if you have a XLP based board.
@@ -1031,7 +997,6 @@ config CPU_BIG_ENDIAN
1031config CPU_LITTLE_ENDIAN 997config CPU_LITTLE_ENDIAN
1032 bool "Little endian" 998 bool "Little endian"
1033 depends on SYS_SUPPORTS_LITTLE_ENDIAN 999 depends on SYS_SUPPORTS_LITTLE_ENDIAN
1034 help
1035 1000
1036endchoice 1001endchoice
1037 1002
@@ -1964,7 +1929,7 @@ config MIPS_MT_FPAFF
1964 1929
1965config MIPS_VPE_LOADER 1930config MIPS_VPE_LOADER
1966 bool "VPE loader support." 1931 bool "VPE loader support."
1967 depends on SYS_SUPPORTS_MULTITHREADING 1932 depends on SYS_SUPPORTS_MULTITHREADING && MODULES
1968 select CPU_MIPSR2_IRQ_VI 1933 select CPU_MIPSR2_IRQ_VI
1969 select CPU_MIPSR2_IRQ_EI 1934 select CPU_MIPSR2_IRQ_EI
1970 select MIPS_MT 1935 select MIPS_MT
@@ -2382,6 +2347,19 @@ config SECCOMP
2382 2347
2383 If unsure, say Y. Only embedded should say N here. 2348 If unsure, say Y. Only embedded should say N here.
2384 2349
2350config CC_STACKPROTECTOR
2351 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
2352 help
2353 This option turns on the -fstack-protector GCC feature. This
2354 feature puts, at the beginning of functions, a canary value on
2355 the stack just before the return address, and validates
2356 the value just before actually returning. Stack based buffer
2357 overflows (that need to overwrite this return address) now also
2358 overwrite the canary, which gets detected and the attack is then
2359 neutralized via a kernel panic.
2360
2361 This feature requires gcc version 4.2 or above.
2362
2385config USE_OF 2363config USE_OF
2386 bool 2364 bool
2387 select OF 2365 select OF
@@ -2413,7 +2391,6 @@ config PCI
2413 bool "Support for PCI controller" 2391 bool "Support for PCI controller"
2414 depends on HW_HAS_PCI 2392 depends on HW_HAS_PCI
2415 select PCI_DOMAINS 2393 select PCI_DOMAINS
2416 select GENERIC_PCI_IOMAP
2417 select NO_GENERIC_PCI_IOPORT_MAP 2394 select NO_GENERIC_PCI_IOPORT_MAP
2418 help 2395 help
2419 Find out whether you have a PCI motherboard. PCI is the name of a 2396 Find out whether you have a PCI motherboard. PCI is the name of a
@@ -2479,6 +2456,9 @@ config I8253
2479 select CLKEVT_I8253 2456 select CLKEVT_I8253
2480 select MIPS_EXTERNAL_TIMER 2457 select MIPS_EXTERNAL_TIMER
2481 2458
2459config ZONE_DMA
2460 bool
2461
2482config ZONE_DMA32 2462config ZONE_DMA32
2483 bool 2463 bool
2484 2464
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index dd58a04ef4bc..37f9ef324f2f 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -227,6 +227,10 @@ KBUILD_CPPFLAGS += -DDATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0)
227 227
228LDFLAGS += -m $(ld-emul) 228LDFLAGS += -m $(ld-emul)
229 229
230ifdef CONFIG_CC_STACKPROTECTOR
231 KBUILD_CFLAGS += -fstack-protector
232endif
233
230ifdef CONFIG_MIPS 234ifdef CONFIG_MIPS
231CHECKFLAGS += $(shell $(CC) $(KBUILD_CFLAGS) -dM -E -x c /dev/null | \ 235CHECKFLAGS += $(shell $(CC) $(KBUILD_CFLAGS) -dM -E -x c /dev/null | \
232 egrep -vw '__GNUC_(|MINOR_|PATCHLEVEL_)_' | \ 236 egrep -vw '__GNUC_(|MINOR_|PATCHLEVEL_)_' | \
diff --git a/arch/mips/ath79/mach-ap136.c b/arch/mips/ath79/mach-ap136.c
index 479dd4b1d0d2..07eac58c3641 100644
--- a/arch/mips/ath79/mach-ap136.c
+++ b/arch/mips/ath79/mach-ap136.c
@@ -132,7 +132,7 @@ static void __init ap136_pci_init(u8 *eeprom)
132 ath79_register_pci(); 132 ath79_register_pci();
133} 133}
134#else 134#else
135static inline void ap136_pci_init(void) {} 135static inline void ap136_pci_init(u8 *eeprom) {}
136#endif /* CONFIG_PCI */ 136#endif /* CONFIG_PCI */
137 137
138static void __init ap136_setup(void) 138static void __init ap136_setup(void)
diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig
index 5639662fd503..b78306ce56c7 100644
--- a/arch/mips/bcm63xx/Kconfig
+++ b/arch/mips/bcm63xx/Kconfig
@@ -1,6 +1,10 @@
1menu "CPU support" 1menu "CPU support"
2 depends on BCM63XX 2 depends on BCM63XX
3 3
4config BCM63XX_CPU_3368
5 bool "support 3368 CPU"
6 select HW_HAS_PCI
7
4config BCM63XX_CPU_6328 8config BCM63XX_CPU_6328
5 bool "support 6328 CPU" 9 bool "support 6328 CPU"
6 select HW_HAS_PCI 10 select HW_HAS_PCI
@@ -8,14 +12,9 @@ config BCM63XX_CPU_6328
8config BCM63XX_CPU_6338 12config BCM63XX_CPU_6338
9 bool "support 6338 CPU" 13 bool "support 6338 CPU"
10 select HW_HAS_PCI 14 select HW_HAS_PCI
11 select USB_ARCH_HAS_OHCI
12 select USB_OHCI_BIG_ENDIAN_DESC
13 select USB_OHCI_BIG_ENDIAN_MMIO
14 15
15config BCM63XX_CPU_6345 16config BCM63XX_CPU_6345
16 bool "support 6345 CPU" 17 bool "support 6345 CPU"
17 select USB_OHCI_BIG_ENDIAN_DESC
18 select USB_OHCI_BIG_ENDIAN_MMIO
19 18
20config BCM63XX_CPU_6348 19config BCM63XX_CPU_6348
21 bool "support 6348 CPU" 20 bool "support 6348 CPU"
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
index 9c0ddafafb6c..5b974eb125fc 100644
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -28,11 +28,47 @@
28#include <bcm63xx_dev_usb_usbd.h> 28#include <bcm63xx_dev_usb_usbd.h>
29#include <board_bcm963xx.h> 29#include <board_bcm963xx.h>
30 30
31#include <uapi/linux/bcm933xx_hcs.h>
32
31#define PFX "board_bcm963xx: " 33#define PFX "board_bcm963xx: "
32 34
35#define HCS_OFFSET_128K 0x20000
36
33static struct board_info board; 37static struct board_info board;
34 38
35/* 39/*
40 * known 3368 boards
41 */
42#ifdef CONFIG_BCM63XX_CPU_3368
43static struct board_info __initdata board_cvg834g = {
44 .name = "CVG834G_E15R3921",
45 .expected_cpu_id = 0x3368,
46
47 .has_uart0 = 1,
48 .has_uart1 = 1,
49
50 .has_enet0 = 1,
51 .has_pci = 1,
52
53 .enet0 = {
54 .has_phy = 1,
55 .use_internal_phy = 1,
56 },
57
58 .leds = {
59 {
60 .name = "CVG834G:green:power",
61 .gpio = 37,
62 .default_trigger= "default-on",
63 },
64 },
65
66 .ephy_reset_gpio = 36,
67 .ephy_reset_gpio_flags = GPIOF_INIT_HIGH,
68};
69#endif
70
71/*
36 * known 6328 boards 72 * known 6328 boards
37 */ 73 */
38#ifdef CONFIG_BCM63XX_CPU_6328 74#ifdef CONFIG_BCM63XX_CPU_6328
@@ -639,6 +675,9 @@ static struct board_info __initdata board_DWVS0 = {
639 * all boards 675 * all boards
640 */ 676 */
641static const struct board_info __initconst *bcm963xx_boards[] = { 677static const struct board_info __initconst *bcm963xx_boards[] = {
678#ifdef CONFIG_BCM63XX_CPU_3368
679 &board_cvg834g,
680#endif
642#ifdef CONFIG_BCM63XX_CPU_6328 681#ifdef CONFIG_BCM63XX_CPU_6328
643 &board_96328avng, 682 &board_96328avng,
644#endif 683#endif
@@ -722,8 +761,9 @@ void __init board_prom_init(void)
722 unsigned int i; 761 unsigned int i;
723 u8 *boot_addr, *cfe; 762 u8 *boot_addr, *cfe;
724 char cfe_version[32]; 763 char cfe_version[32];
725 char *board_name; 764 char *board_name = NULL;
726 u32 val; 765 u32 val;
766 struct bcm_hcs *hcs;
727 767
728 /* read base address of boot chip select (0) 768 /* read base address of boot chip select (0)
729 * 6328/6362 do not have MPI but boot from a fixed address 769 * 6328/6362 do not have MPI but boot from a fixed address
@@ -747,7 +787,12 @@ void __init board_prom_init(void)
747 787
748 bcm63xx_nvram_init(boot_addr + BCM963XX_NVRAM_OFFSET); 788 bcm63xx_nvram_init(boot_addr + BCM963XX_NVRAM_OFFSET);
749 789
750 board_name = bcm63xx_nvram_get_name(); 790 if (BCMCPU_IS_3368()) {
791 hcs = (struct bcm_hcs *)boot_addr;
792 board_name = hcs->filename;
793 } else {
794 board_name = bcm63xx_nvram_get_name();
795 }
751 /* find board by name */ 796 /* find board by name */
752 for (i = 0; i < ARRAY_SIZE(bcm963xx_boards); i++) { 797 for (i = 0; i < ARRAY_SIZE(bcm963xx_boards); i++) {
753 if (strncmp(board_name, bcm963xx_boards[i]->name, 16)) 798 if (strncmp(board_name, bcm963xx_boards[i]->name, 16))
@@ -877,5 +922,9 @@ int __init board_register_devices(void)
877 922
878 platform_device_register(&bcm63xx_gpio_leds); 923 platform_device_register(&bcm63xx_gpio_leds);
879 924
925 if (board.ephy_reset_gpio && board.ephy_reset_gpio_flags)
926 gpio_request_one(board.ephy_reset_gpio,
927 board.ephy_reset_gpio_flags, "ephy-reset");
928
880 return 0; 929 return 0;
881} 930}
diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
index c726a97fc798..43da4ae04cc2 100644
--- a/arch/mips/bcm63xx/clk.c
+++ b/arch/mips/bcm63xx/clk.c
@@ -84,7 +84,7 @@ static void enetx_set(struct clk *clk, int enable)
84 else 84 else
85 clk_disable_unlocked(&clk_enet_misc); 85 clk_disable_unlocked(&clk_enet_misc);
86 86
87 if (BCMCPU_IS_6358()) { 87 if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) {
88 u32 mask; 88 u32 mask;
89 89
90 if (clk->id == 0) 90 if (clk->id == 0)
@@ -110,9 +110,8 @@ static struct clk clk_enet1 = {
110 */ 110 */
111static void ephy_set(struct clk *clk, int enable) 111static void ephy_set(struct clk *clk, int enable)
112{ 112{
113 if (!BCMCPU_IS_6358()) 113 if (BCMCPU_IS_3368() || BCMCPU_IS_6358())
114 return; 114 bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);
115 bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);
116} 115}
117 116
118 117
@@ -155,9 +154,10 @@ static struct clk clk_enetsw = {
155 */ 154 */
156static void pcm_set(struct clk *clk, int enable) 155static void pcm_set(struct clk *clk, int enable)
157{ 156{
158 if (!BCMCPU_IS_6358()) 157 if (BCMCPU_IS_3368())
159 return; 158 bcm_hwclock_set(CKCTL_3368_PCM_EN, enable);
160 bcm_hwclock_set(CKCTL_6358_PCM_EN, enable); 159 if (BCMCPU_IS_6358())
160 bcm_hwclock_set(CKCTL_6358_PCM_EN, enable);
161} 161}
162 162
163static struct clk clk_pcm = { 163static struct clk clk_pcm = {
@@ -211,7 +211,7 @@ static void spi_set(struct clk *clk, int enable)
211 mask = CKCTL_6338_SPI_EN; 211 mask = CKCTL_6338_SPI_EN;
212 else if (BCMCPU_IS_6348()) 212 else if (BCMCPU_IS_6348())
213 mask = CKCTL_6348_SPI_EN; 213 mask = CKCTL_6348_SPI_EN;
214 else if (BCMCPU_IS_6358()) 214 else if (BCMCPU_IS_3368() || BCMCPU_IS_6358())
215 mask = CKCTL_6358_SPI_EN; 215 mask = CKCTL_6358_SPI_EN;
216 else if (BCMCPU_IS_6362()) 216 else if (BCMCPU_IS_6362())
217 mask = CKCTL_6362_SPI_EN; 217 mask = CKCTL_6362_SPI_EN;
@@ -318,6 +318,18 @@ unsigned long clk_get_rate(struct clk *clk)
318 318
319EXPORT_SYMBOL(clk_get_rate); 319EXPORT_SYMBOL(clk_get_rate);
320 320
321int clk_set_rate(struct clk *clk, unsigned long rate)
322{
323 return 0;
324}
325EXPORT_SYMBOL_GPL(clk_set_rate);
326
327long clk_round_rate(struct clk *clk, unsigned long rate)
328{
329 return 0;
330}
331EXPORT_SYMBOL_GPL(clk_round_rate);
332
321struct clk *clk_get(struct device *dev, const char *id) 333struct clk *clk_get(struct device *dev, const char *id)
322{ 334{
323 if (!strcmp(id, "enet0")) 335 if (!strcmp(id, "enet0"))
@@ -338,7 +350,7 @@ struct clk *clk_get(struct device *dev, const char *id)
338 return &clk_xtm; 350 return &clk_xtm;
339 if (!strcmp(id, "periph")) 351 if (!strcmp(id, "periph"))
340 return &clk_periph; 352 return &clk_periph;
341 if (BCMCPU_IS_6358() && !strcmp(id, "pcm")) 353 if ((BCMCPU_IS_3368() || BCMCPU_IS_6358()) && !strcmp(id, "pcm"))
342 return &clk_pcm; 354 return &clk_pcm;
343 if ((BCMCPU_IS_6362() || BCMCPU_IS_6368()) && !strcmp(id, "ipsec")) 355 if ((BCMCPU_IS_6362() || BCMCPU_IS_6368()) && !strcmp(id, "ipsec"))
344 return &clk_ipsec; 356 return &clk_ipsec;
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
index 79fe32df5e96..7e17374a9ae8 100644
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -29,6 +29,14 @@ static u8 bcm63xx_cpu_rev;
29static unsigned int bcm63xx_cpu_freq; 29static unsigned int bcm63xx_cpu_freq;
30static unsigned int bcm63xx_memory_size; 30static unsigned int bcm63xx_memory_size;
31 31
32static const unsigned long bcm3368_regs_base[] = {
33 __GEN_CPU_REGS_TABLE(3368)
34};
35
36static const int bcm3368_irqs[] = {
37 __GEN_CPU_IRQ_TABLE(3368)
38};
39
32static const unsigned long bcm6328_regs_base[] = { 40static const unsigned long bcm6328_regs_base[] = {
33 __GEN_CPU_REGS_TABLE(6328) 41 __GEN_CPU_REGS_TABLE(6328)
34}; 42};
@@ -116,6 +124,9 @@ unsigned int bcm63xx_get_memory_size(void)
116static unsigned int detect_cpu_clock(void) 124static unsigned int detect_cpu_clock(void)
117{ 125{
118 switch (bcm63xx_get_cpu_id()) { 126 switch (bcm63xx_get_cpu_id()) {
127 case BCM3368_CPU_ID:
128 return 300000000;
129
119 case BCM6328_CPU_ID: 130 case BCM6328_CPU_ID:
120 { 131 {
121 unsigned int tmp, mips_pll_fcvo; 132 unsigned int tmp, mips_pll_fcvo;
@@ -266,7 +277,7 @@ static unsigned int detect_memory_size(void)
266 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1; 277 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
267 } 278 }
268 279
269 if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) { 280 if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
270 val = bcm_memc_readl(MEMC_CFG_REG); 281 val = bcm_memc_readl(MEMC_CFG_REG);
271 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT; 282 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
272 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT; 283 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
@@ -302,10 +313,17 @@ void __init bcm63xx_cpu_init(void)
302 chipid_reg = BCM_6345_PERF_BASE; 313 chipid_reg = BCM_6345_PERF_BASE;
303 break; 314 break;
304 case CPU_BMIPS4350: 315 case CPU_BMIPS4350:
305 if ((read_c0_prid() & 0xf0) == 0x10) 316 switch ((read_c0_prid() & 0xff)) {
317 case 0x04:
318 chipid_reg = BCM_3368_PERF_BASE;
319 break;
320 case 0x10:
306 chipid_reg = BCM_6345_PERF_BASE; 321 chipid_reg = BCM_6345_PERF_BASE;
307 else 322 break;
323 default:
308 chipid_reg = BCM_6368_PERF_BASE; 324 chipid_reg = BCM_6368_PERF_BASE;
325 break;
326 }
309 break; 327 break;
310 } 328 }
311 329
@@ -322,6 +340,10 @@ void __init bcm63xx_cpu_init(void)
322 bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT; 340 bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
323 341
324 switch (bcm63xx_cpu_id) { 342 switch (bcm63xx_cpu_id) {
343 case BCM3368_CPU_ID:
344 bcm63xx_regs_base = bcm3368_regs_base;
345 bcm63xx_irqs = bcm3368_irqs;
346 break;
325 case BCM6328_CPU_ID: 347 case BCM6328_CPU_ID:
326 bcm63xx_regs_base = bcm6328_regs_base; 348 bcm63xx_regs_base = bcm6328_regs_base;
327 bcm63xx_irqs = bcm6328_irqs; 349 bcm63xx_irqs = bcm6328_irqs;
diff --git a/arch/mips/bcm63xx/dev-flash.c b/arch/mips/bcm63xx/dev-flash.c
index 588d1ec622e4..172dd8397178 100644
--- a/arch/mips/bcm63xx/dev-flash.c
+++ b/arch/mips/bcm63xx/dev-flash.c
@@ -71,6 +71,7 @@ static int __init bcm63xx_detect_flash_type(void)
71 case BCM6348_CPU_ID: 71 case BCM6348_CPU_ID:
72 /* no way to auto detect so assume parallel */ 72 /* no way to auto detect so assume parallel */
73 return BCM63XX_FLASH_TYPE_PARALLEL; 73 return BCM63XX_FLASH_TYPE_PARALLEL;
74 case BCM3368_CPU_ID:
74 case BCM6358_CPU_ID: 75 case BCM6358_CPU_ID:
75 val = bcm_gpio_readl(GPIO_STRAPBUS_REG); 76 val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
76 if (val & STRAPBUS_6358_BOOT_SEL_PARALLEL) 77 if (val & STRAPBUS_6358_BOOT_SEL_PARALLEL)
diff --git a/arch/mips/bcm63xx/dev-spi.c b/arch/mips/bcm63xx/dev-spi.c
index 3065bb61820d..d12daed749bc 100644
--- a/arch/mips/bcm63xx/dev-spi.c
+++ b/arch/mips/bcm63xx/dev-spi.c
@@ -37,7 +37,8 @@ static __init void bcm63xx_spi_regs_init(void)
37{ 37{
38 if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) 38 if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
39 bcm63xx_regs_spi = bcm6348_regs_spi; 39 bcm63xx_regs_spi = bcm6348_regs_spi;
40 if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) 40 if (BCMCPU_IS_3368() || BCMCPU_IS_6358() ||
41 BCMCPU_IS_6362() || BCMCPU_IS_6368())
41 bcm63xx_regs_spi = bcm6358_regs_spi; 42 bcm63xx_regs_spi = bcm6358_regs_spi;
42} 43}
43#else 44#else
@@ -87,7 +88,8 @@ int __init bcm63xx_spi_register(void)
87 spi_pdata.msg_ctl_width = SPI_6348_MSG_CTL_WIDTH; 88 spi_pdata.msg_ctl_width = SPI_6348_MSG_CTL_WIDTH;
88 } 89 }
89 90
90 if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) { 91 if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6362() ||
92 BCMCPU_IS_6368()) {
91 spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1; 93 spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;
92 spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE; 94 spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE;
93 spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT; 95 spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT;
diff --git a/arch/mips/bcm63xx/dev-uart.c b/arch/mips/bcm63xx/dev-uart.c
index d6e42c608325..3bc7f3bfc9ad 100644
--- a/arch/mips/bcm63xx/dev-uart.c
+++ b/arch/mips/bcm63xx/dev-uart.c
@@ -54,7 +54,8 @@ int __init bcm63xx_uart_register(unsigned int id)
54 if (id >= ARRAY_SIZE(bcm63xx_uart_devices)) 54 if (id >= ARRAY_SIZE(bcm63xx_uart_devices))
55 return -ENODEV; 55 return -ENODEV;
56 56
57 if (id == 1 && (!BCMCPU_IS_6358() && !BCMCPU_IS_6368())) 57 if (id == 1 && (!BCMCPU_IS_3368() && !BCMCPU_IS_6358() &&
58 !BCMCPU_IS_6368()))
58 return -ENODEV; 59 return -ENODEV;
59 60
60 if (id == 0) { 61 if (id == 0) {
diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
index c0ab3887f42e..1525f8a3841b 100644
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -27,6 +27,17 @@ static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
27static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused; 27static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
28 28
29#ifndef BCMCPU_RUNTIME_DETECT 29#ifndef BCMCPU_RUNTIME_DETECT
30#ifdef CONFIG_BCM63XX_CPU_3368
31#define irq_stat_reg PERF_IRQSTAT_3368_REG
32#define irq_mask_reg PERF_IRQMASK_3368_REG
33#define irq_bits 32
34#define is_ext_irq_cascaded 0
35#define ext_irq_start 0
36#define ext_irq_end 0
37#define ext_irq_count 4
38#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_3368
39#define ext_irq_cfg_reg2 0
40#endif
30#ifdef CONFIG_BCM63XX_CPU_6328 41#ifdef CONFIG_BCM63XX_CPU_6328
31#define irq_stat_reg PERF_IRQSTAT_6328_REG 42#define irq_stat_reg PERF_IRQSTAT_6328_REG
32#define irq_mask_reg PERF_IRQMASK_6328_REG 43#define irq_mask_reg PERF_IRQMASK_6328_REG
@@ -140,6 +151,13 @@ static void bcm63xx_init_irq(void)
140 irq_mask_addr = bcm63xx_regset_address(RSET_PERF); 151 irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
141 152
142 switch (bcm63xx_get_cpu_id()) { 153 switch (bcm63xx_get_cpu_id()) {
154 case BCM3368_CPU_ID:
155 irq_stat_addr += PERF_IRQSTAT_3368_REG;
156 irq_mask_addr += PERF_IRQMASK_3368_REG;
157 irq_bits = 32;
158 ext_irq_count = 4;
159 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
160 break;
143 case BCM6328_CPU_ID: 161 case BCM6328_CPU_ID:
144 irq_stat_addr += PERF_IRQSTAT_6328_REG; 162 irq_stat_addr += PERF_IRQSTAT_6328_REG;
145 irq_mask_addr += PERF_IRQMASK_6328_REG; 163 irq_mask_addr += PERF_IRQMASK_6328_REG;
@@ -294,6 +312,10 @@ asmlinkage void plat_irq_dispatch(void)
294 312
295 if (cause & CAUSEF_IP7) 313 if (cause & CAUSEF_IP7)
296 do_IRQ(7); 314 do_IRQ(7);
315 if (cause & CAUSEF_IP0)
316 do_IRQ(0);
317 if (cause & CAUSEF_IP1)
318 do_IRQ(1);
297 if (cause & CAUSEF_IP2) 319 if (cause & CAUSEF_IP2)
298 dispatch_internal(); 320 dispatch_internal();
299 if (!is_ext_irq_cascaded) { 321 if (!is_ext_irq_cascaded) {
@@ -475,6 +497,7 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d,
475 reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq); 497 reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
476 break; 498 break;
477 499
500 case BCM3368_CPU_ID:
478 case BCM6328_CPU_ID: 501 case BCM6328_CPU_ID:
479 case BCM6338_CPU_ID: 502 case BCM6338_CPU_ID:
480 case BCM6345_CPU_ID: 503 case BCM6345_CPU_ID:
diff --git a/arch/mips/bcm63xx/nvram.c b/arch/mips/bcm63xx/nvram.c
index a4b8864f9307..e652e578a679 100644
--- a/arch/mips/bcm63xx/nvram.c
+++ b/arch/mips/bcm63xx/nvram.c
@@ -42,6 +42,7 @@ void __init bcm63xx_nvram_init(void *addr)
42{ 42{
43 unsigned int check_len; 43 unsigned int check_len;
44 u32 crc, expected_crc; 44 u32 crc, expected_crc;
45 u8 hcs_mac_addr[ETH_ALEN] = { 0x00, 0x10, 0x18, 0xff, 0xff, 0xff };
45 46
46 /* extract nvram data */ 47 /* extract nvram data */
47 memcpy(&nvram, addr, sizeof(nvram)); 48 memcpy(&nvram, addr, sizeof(nvram));
@@ -62,6 +63,15 @@ void __init bcm63xx_nvram_init(void *addr)
62 if (crc != expected_crc) 63 if (crc != expected_crc)
63 pr_warn("nvram checksum failed, contents may be invalid (expected %08x, got %08x)\n", 64 pr_warn("nvram checksum failed, contents may be invalid (expected %08x, got %08x)\n",
64 expected_crc, crc); 65 expected_crc, crc);
66
67 /* Cable modems have a different NVRAM which is embedded in the eCos
68 * firmware and not easily extractible, give at least a MAC address
69 * pool.
70 */
71 if (BCMCPU_IS_3368()) {
72 memcpy(nvram.mac_addr_base, hcs_mac_addr, ETH_ALEN);
73 nvram.mac_addr_count = 2;
74 }
65} 75}
66 76
67u8 *bcm63xx_nvram_get_name(void) 77u8 *bcm63xx_nvram_get_name(void)
diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
index fd698087fbfd..8ac4e095e68e 100644
--- a/arch/mips/bcm63xx/prom.c
+++ b/arch/mips/bcm63xx/prom.c
@@ -8,7 +8,11 @@
8 8
9#include <linux/init.h> 9#include <linux/init.h>
10#include <linux/bootmem.h> 10#include <linux/bootmem.h>
11#include <linux/smp.h>
11#include <asm/bootinfo.h> 12#include <asm/bootinfo.h>
13#include <asm/bmips.h>
14#include <asm/smp-ops.h>
15#include <asm/mipsregs.h>
12#include <bcm63xx_board.h> 16#include <bcm63xx_board.h>
13#include <bcm63xx_cpu.h> 17#include <bcm63xx_cpu.h>
14#include <bcm63xx_io.h> 18#include <bcm63xx_io.h>
@@ -26,7 +30,9 @@ void __init prom_init(void)
26 bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG); 30 bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG);
27 31
28 /* disable all hardware blocks clock for now */ 32 /* disable all hardware blocks clock for now */
29 if (BCMCPU_IS_6328()) 33 if (BCMCPU_IS_3368())
34 mask = CKCTL_3368_ALL_SAFE_EN;
35 else if (BCMCPU_IS_6328())
30 mask = CKCTL_6328_ALL_SAFE_EN; 36 mask = CKCTL_6328_ALL_SAFE_EN;
31 else if (BCMCPU_IS_6338()) 37 else if (BCMCPU_IS_6338())
32 mask = CKCTL_6338_ALL_SAFE_EN; 38 mask = CKCTL_6338_ALL_SAFE_EN;
@@ -52,6 +58,47 @@ void __init prom_init(void)
52 58
53 /* do low level board init */ 59 /* do low level board init */
54 board_prom_init(); 60 board_prom_init();
61
62 if (IS_ENABLED(CONFIG_CPU_BMIPS4350) && IS_ENABLED(CONFIG_SMP)) {
63 /* set up SMP */
64 register_smp_ops(&bmips_smp_ops);
65
66 /*
67 * BCM6328 might not have its second CPU enabled, while BCM6358
68 * needs special handling for its shared TLB, so disable SMP
69 * for now.
70 */
71 if (BCMCPU_IS_6328()) {
72 reg = bcm_readl(BCM_6328_OTP_BASE +
73 OTP_USER_BITS_6328_REG(3));
74
75 if (reg & OTP_6328_REG3_TP1_DISABLED)
76 bmips_smp_enabled = 0;
77 } else if (BCMCPU_IS_6358()) {
78 bmips_smp_enabled = 0;
79 }
80
81 if (!bmips_smp_enabled)
82 return;
83
84 /*
85 * The bootloader has set up the CPU1 reset vector at
86 * 0xa000_0200.
87 * This conflicts with the special interrupt vector (IV).
88 * The bootloader has also set up CPU1 to respond to the wrong
89 * IPI interrupt.
90 * Here we will start up CPU1 in the background and ask it to
91 * reconfigure itself then go back to sleep.
92 */
93 memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20);
94 __sync();
95 set_c0_cause(C_SW0);
96 cpumask_set_cpu(1, &bmips_booted_mask);
97
98 /*
99 * FIXME: we really should have some sort of hazard barrier here
100 */
101 }
55} 102}
56 103
57void __init prom_free_prom_memory(void) 104void __init prom_free_prom_memory(void)
diff --git a/arch/mips/bcm63xx/reset.c b/arch/mips/bcm63xx/reset.c
index 317931c6cf58..acbeb1fe7c57 100644
--- a/arch/mips/bcm63xx/reset.c
+++ b/arch/mips/bcm63xx/reset.c
@@ -30,6 +30,19 @@
30 [BCM63XX_RESET_PCIE] = BCM## __cpu ##_RESET_PCIE, \ 30 [BCM63XX_RESET_PCIE] = BCM## __cpu ##_RESET_PCIE, \
31 [BCM63XX_RESET_PCIE_EXT] = BCM## __cpu ##_RESET_PCIE_EXT, 31 [BCM63XX_RESET_PCIE_EXT] = BCM## __cpu ##_RESET_PCIE_EXT,
32 32
33#define BCM3368_RESET_SPI SOFTRESET_3368_SPI_MASK
34#define BCM3368_RESET_ENET SOFTRESET_3368_ENET_MASK
35#define BCM3368_RESET_USBH 0
36#define BCM3368_RESET_USBD SOFTRESET_3368_USBS_MASK
37#define BCM3368_RESET_DSL 0
38#define BCM3368_RESET_SAR 0
39#define BCM3368_RESET_EPHY SOFTRESET_3368_EPHY_MASK
40#define BCM3368_RESET_ENETSW 0
41#define BCM3368_RESET_PCM SOFTRESET_3368_PCM_MASK
42#define BCM3368_RESET_MPI SOFTRESET_3368_MPI_MASK
43#define BCM3368_RESET_PCIE 0
44#define BCM3368_RESET_PCIE_EXT 0
45
33#define BCM6328_RESET_SPI SOFTRESET_6328_SPI_MASK 46#define BCM6328_RESET_SPI SOFTRESET_6328_SPI_MASK
34#define BCM6328_RESET_ENET 0 47#define BCM6328_RESET_ENET 0
35#define BCM6328_RESET_USBH SOFTRESET_6328_USBH_MASK 48#define BCM6328_RESET_USBH SOFTRESET_6328_USBH_MASK
@@ -117,6 +130,10 @@
117/* 130/*
118 * core reset bits 131 * core reset bits
119 */ 132 */
133static const u32 bcm3368_reset_bits[] = {
134 __GEN_RESET_BITS_TABLE(3368)
135};
136
120static const u32 bcm6328_reset_bits[] = { 137static const u32 bcm6328_reset_bits[] = {
121 __GEN_RESET_BITS_TABLE(6328) 138 __GEN_RESET_BITS_TABLE(6328)
122}; 139};
@@ -146,7 +163,10 @@ static int reset_reg;
146 163
147static int __init bcm63xx_reset_bits_init(void) 164static int __init bcm63xx_reset_bits_init(void)
148{ 165{
149 if (BCMCPU_IS_6328()) { 166 if (BCMCPU_IS_3368()) {
167 reset_reg = PERF_SOFTRESET_6358_REG;
168 bcm63xx_reset_bits = bcm3368_reset_bits;
169 } else if (BCMCPU_IS_6328()) {
150 reset_reg = PERF_SOFTRESET_6328_REG; 170 reset_reg = PERF_SOFTRESET_6328_REG;
151 bcm63xx_reset_bits = bcm6328_reset_bits; 171 bcm63xx_reset_bits = bcm6328_reset_bits;
152 } else if (BCMCPU_IS_6338()) { 172 } else if (BCMCPU_IS_6338()) {
@@ -170,6 +190,13 @@ static int __init bcm63xx_reset_bits_init(void)
170} 190}
171#else 191#else
172 192
193#ifdef CONFIG_BCM63XX_CPU_3368
194static const u32 bcm63xx_reset_bits[] = {
195 __GEN_RESET_BITS_TABLE(3368)
196};
197#define reset_reg PERF_SOFTRESET_6358_REG
198#endif
199
173#ifdef CONFIG_BCM63XX_CPU_6328 200#ifdef CONFIG_BCM63XX_CPU_6328
174static const u32 bcm63xx_reset_bits[] = { 201static const u32 bcm63xx_reset_bits[] = {
175 __GEN_RESET_BITS_TABLE(6328) 202 __GEN_RESET_BITS_TABLE(6328)
diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
index 24a24445db64..6660c7ddf87b 100644
--- a/arch/mips/bcm63xx/setup.c
+++ b/arch/mips/bcm63xx/setup.c
@@ -68,6 +68,9 @@ void bcm63xx_machine_reboot(void)
68 68
69 /* mask and clear all external irq */ 69 /* mask and clear all external irq */
70 switch (bcm63xx_get_cpu_id()) { 70 switch (bcm63xx_get_cpu_id()) {
71 case BCM3368_CPU_ID:
72 perf_regs[0] = PERF_EXTIRQ_CFG_REG_3368;
73 break;
71 case BCM6328_CPU_ID: 74 case BCM6328_CPU_ID:
72 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328; 75 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328;
73 break; 76 break;
diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile
index bbaa1d4beb6d..bb1dbf4abb9d 100644
--- a/arch/mips/boot/compressed/Makefile
+++ b/arch/mips/boot/compressed/Makefile
@@ -18,6 +18,8 @@ BOOT_HEAP_SIZE := 0x400000
18# Disable Function Tracer 18# Disable Function Tracer
19KBUILD_CFLAGS := $(shell echo $(KBUILD_CFLAGS) | sed -e "s/-pg//") 19KBUILD_CFLAGS := $(shell echo $(KBUILD_CFLAGS) | sed -e "s/-pg//")
20 20
21KBUILD_CFLAGS := $(filter-out -fstack-protector, $(KBUILD_CFLAGS))
22
21KBUILD_CFLAGS := $(LINUXINCLUDE) $(KBUILD_CFLAGS) -D__KERNEL__ \ 23KBUILD_CFLAGS := $(LINUXINCLUDE) $(KBUILD_CFLAGS) -D__KERNEL__ \
22 -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) -D"VMLINUX_LOAD_ADDRESS_ULL=$(VMLINUX_LOAD_ADDRESS)ull" 24 -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) -D"VMLINUX_LOAD_ADDRESS_ULL=$(VMLINUX_LOAD_ADDRESS)ull"
23 25
diff --git a/arch/mips/boot/compressed/uart-16550.c b/arch/mips/boot/compressed/uart-16550.c
index 1c7b739b6a1d..c01d343ce6ad 100644
--- a/arch/mips/boot/compressed/uart-16550.c
+++ b/arch/mips/boot/compressed/uart-16550.c
@@ -23,23 +23,39 @@
23#define PORT(offset) (UART0_BASE + (4 * offset)) 23#define PORT(offset) (UART0_BASE + (4 * offset))
24#endif 24#endif
25 25
26#ifdef CONFIG_CPU_XLR
27#define UART0_BASE 0x1EF14000
28#define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset))
29#define IOTYPE unsigned int
30#endif
31
32#ifdef CONFIG_CPU_XLP
33#define UART0_BASE 0x18030100
34#define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset))
35#define IOTYPE unsigned int
36#endif
37
38#ifndef IOTYPE
39#define IOTYPE char
40#endif
41
26#ifndef PORT 42#ifndef PORT
27#error please define the serial port address for your own machine 43#error please define the serial port address for your own machine
28#endif 44#endif
29 45
30static inline unsigned int serial_in(int offset) 46static inline unsigned int serial_in(int offset)
31{ 47{
32 return *((char *)PORT(offset)); 48 return *((volatile IOTYPE *)PORT(offset)) & 0xFF;
33} 49}
34 50
35static inline void serial_out(int offset, int value) 51static inline void serial_out(int offset, int value)
36{ 52{
37 *((char *)PORT(offset)) = value; 53 *((volatile IOTYPE *)PORT(offset)) = value & 0xFF;
38} 54}
39 55
40void putc(char c) 56void putc(char c)
41{ 57{
42 int timeout = 1024; 58 int timeout = 1000000;
43 59
44 while (((serial_in(UART_LSR) & UART_LSR_THRE) == 0) && (timeout-- > 0)) 60 while (((serial_in(UART_LSR) & UART_LSR_THRE) == 0) && (timeout-- > 0))
45 ; 61 ;
diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index 75a6df7fd265..227705d9d5ae 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -10,6 +10,10 @@ config CAVIUM_CN63XXP1
10 non-CN63XXP1 hardware, so it is recommended to select "n" 10 non-CN63XXP1 hardware, so it is recommended to select "n"
11 unless it is known the workarounds are needed. 11 unless it is known the workarounds are needed.
12 12
13endif # CPU_CAVIUM_OCTEON
14
15if CAVIUM_OCTEON_SOC
16
13config CAVIUM_OCTEON_2ND_KERNEL 17config CAVIUM_OCTEON_2ND_KERNEL
14 bool "Build the kernel to be used as a 2nd kernel on the same chip" 18 bool "Build the kernel to be used as a 2nd kernel on the same chip"
15 default "n" 19 default "n"
@@ -19,17 +23,6 @@ config CAVIUM_OCTEON_2ND_KERNEL
19 with this option to be run at the same time as one built without this 23 with this option to be run at the same time as one built without this
20 option. 24 option.
21 25
22config CAVIUM_OCTEON_HW_FIX_UNALIGNED
23 bool "Enable hardware fixups of unaligned loads and stores"
24 default "y"
25 help
26 Configure the Octeon hardware to automatically fix unaligned loads
27 and stores. Normally unaligned accesses are fixed using a kernel
28 exception handler. This option enables the hardware automatic fixups,
29 which requires only an extra 3 cycles. Disable this option if you
30 are running code that relies on address exceptions on unaligned
31 accesses.
32
33config CAVIUM_OCTEON_CVMSEG_SIZE 26config CAVIUM_OCTEON_CVMSEG_SIZE
34 int "Number of L1 cache lines reserved for CVMSEG memory" 27 int "Number of L1 cache lines reserved for CVMSEG memory"
35 range 0 54 28 range 0 54
@@ -103,4 +96,4 @@ config OCTEON_ILM
103 To compile this driver as a module, choose M here. The module 96 To compile this driver as a module, choose M here. The module
104 will be called octeon-ilm 97 will be called octeon-ilm
105 98
106endif # CPU_CAVIUM_OCTEON 99endif # CAVIUM_OCTEON_SOC
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 3595affb9772..4e952043c922 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -12,11 +12,12 @@
12CFLAGS_octeon-platform.o = -I$(src)/../../../scripts/dtc/libfdt 12CFLAGS_octeon-platform.o = -I$(src)/../../../scripts/dtc/libfdt
13CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt 13CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt
14 14
15obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o 15obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o
16obj-y += dma-octeon.o flash_setup.o 16obj-y += dma-octeon.o
17obj-y += octeon-memcpy.o 17obj-y += octeon-memcpy.o
18obj-y += executive/ 18obj-y += executive/
19 19
20obj-$(CONFIG_MTD) += flash_setup.o
20obj-$(CONFIG_SMP) += smp.o 21obj-$(CONFIG_SMP) += smp.o
21obj-$(CONFIG_OCTEON_ILM) += oct_ilm.o 22obj-$(CONFIG_OCTEON_ILM) += oct_ilm.o
22 23
diff --git a/arch/mips/cavium-octeon/Platform b/arch/mips/cavium-octeon/Platform
index 1e43ccf1a792..8a301cb12d68 100644
--- a/arch/mips/cavium-octeon/Platform
+++ b/arch/mips/cavium-octeon/Platform
@@ -1,11 +1,11 @@
1# 1#
2# Cavium Octeon 2# Cavium Octeon
3# 3#
4platform-$(CONFIG_CPU_CAVIUM_OCTEON) += cavium-octeon/ 4platform-$(CONFIG_CAVIUM_OCTEON_SOC) += cavium-octeon/
5cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += \ 5cflags-$(CONFIG_CAVIUM_OCTEON_SOC) += \
6 -I$(srctree)/arch/mips/include/asm/mach-cavium-octeon 6 -I$(srctree)/arch/mips/include/asm/mach-cavium-octeon
7ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 7ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
8load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff84100000 8load-$(CONFIG_CAVIUM_OCTEON_SOC) += 0xffffffff84100000
9else 9else
10load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff81100000 10load-$(CONFIG_CAVIUM_OCTEON_SOC) += 0xffffffff81100000
11endif 11endif
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
index 7c6497781895..0a1283ce47f5 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
@@ -181,6 +181,11 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
181 return ipd_port - 16 + 4; 181 return ipd_port - 16 + 4;
182 else 182 else
183 return -1; 183 return -1;
184 case CVMX_BOARD_TYPE_UBNT_E100:
185 if (ipd_port >= 0 && ipd_port <= 2)
186 return 7 - ipd_port;
187 else
188 return -1;
184 } 189 }
185 190
186 /* Some unknown board. Somebody forgot to update this function... */ 191 /* Some unknown board. Somebody forgot to update this function... */
@@ -706,6 +711,14 @@ int __cvmx_helper_board_hardware_enable(int interface)
706 } 711 }
707 } 712 }
708 } 713 }
714 } else if (cvmx_sysinfo_get()->board_type ==
715 CVMX_BOARD_TYPE_UBNT_E100) {
716 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), 0);
717 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), 0x10);
718 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0);
719 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0x10);
720 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(2, interface), 0);
721 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(2, interface), 0x10);
709 } 722 }
710 return 0; 723 return 0;
711} 724}
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
index 389512e2abd6..7b746e7bf7a1 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -490,8 +490,15 @@ int __init octeon_prune_device_tree(void)
490 490
491 if (alias_prop) { 491 if (alias_prop) {
492 uart = fdt_path_offset(initial_boot_params, alias_prop); 492 uart = fdt_path_offset(initial_boot_params, alias_prop);
493 if (uart_mask & (1 << i)) 493 if (uart_mask & (1 << i)) {
494 __be32 f;
495
496 f = cpu_to_be32(octeon_get_io_clock_rate());
497 fdt_setprop_inplace(initial_boot_params,
498 uart, "clock-frequency",
499 &f, sizeof(f));
494 continue; 500 continue;
501 }
495 pr_debug("Deleting uart%d\n", i); 502 pr_debug("Deleting uart%d\n", i);
496 fdt_nop_node(initial_boot_params, uart); 503 fdt_nop_node(initial_boot_params, uart);
497 fdt_nop_property(initial_boot_params, aliases, 504 fdt_nop_property(initial_boot_params, aliases,
diff --git a/arch/mips/cavium-octeon/serial.c b/arch/mips/cavium-octeon/serial.c
deleted file mode 100644
index f393f65f3923..000000000000
--- a/arch/mips/cavium-octeon/serial.c
+++ /dev/null
@@ -1,109 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2007 Cavium Networks
7 */
8#include <linux/console.h>
9#include <linux/module.h>
10#include <linux/init.h>
11#include <linux/platform_device.h>
12#include <linux/serial.h>
13#include <linux/serial_8250.h>
14#include <linux/serial_reg.h>
15#include <linux/tty.h>
16#include <linux/irq.h>
17
18#include <asm/time.h>
19
20#include <asm/octeon/octeon.h>
21
22#define DEBUG_UART 1
23
24unsigned int octeon_serial_in(struct uart_port *up, int offset)
25{
26 int rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3)));
27 if (offset == UART_IIR && (rv & 0xf) == 7) {
28 /* Busy interrupt, read the USR (39) and try again. */
29 cvmx_read_csr((uint64_t)(up->membase + (39 << 3)));
30 rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3)));
31 }
32 return rv;
33}
34
35void octeon_serial_out(struct uart_port *up, int offset, int value)
36{
37 /*
38 * If bits 6 or 7 of the OCTEON UART's LCR are set, it quits
39 * working.
40 */
41 if (offset == UART_LCR)
42 value &= 0x9f;
43 cvmx_write_csr((uint64_t)(up->membase + (offset << 3)), (u8)value);
44}
45
46static int octeon_serial_probe(struct platform_device *pdev)
47{
48 int irq, res;
49 struct resource *res_mem;
50 struct uart_8250_port up;
51
52 /* All adaptors have an irq. */
53 irq = platform_get_irq(pdev, 0);
54 if (irq < 0)
55 return irq;
56
57 memset(&up, 0, sizeof(up));
58
59 up.port.flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
60 up.port.type = PORT_OCTEON;
61 up.port.iotype = UPIO_MEM;
62 up.port.regshift = 3;
63 up.port.dev = &pdev->dev;
64
65 if (octeon_is_simulation())
66 /* Make simulator output fast*/
67 up.port.uartclk = 115200 * 16;
68 else
69 up.port.uartclk = octeon_get_io_clock_rate();
70
71 up.port.serial_in = octeon_serial_in;
72 up.port.serial_out = octeon_serial_out;
73 up.port.irq = irq;
74
75 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
76 if (res_mem == NULL) {
77 dev_err(&pdev->dev, "found no memory resource\n");
78 return -ENXIO;
79 }
80 up.port.mapbase = res_mem->start;
81 up.port.membase = ioremap(res_mem->start, resource_size(res_mem));
82
83 res = serial8250_register_8250_port(&up);
84
85 return res >= 0 ? 0 : res;
86}
87
88static struct of_device_id octeon_serial_match[] = {
89 {
90 .compatible = "cavium,octeon-3860-uart",
91 },
92 {},
93};
94MODULE_DEVICE_TABLE(of, octeon_serial_match);
95
96static struct platform_driver octeon_serial_driver = {
97 .probe = octeon_serial_probe,
98 .driver = {
99 .owner = THIS_MODULE,
100 .name = "octeon_serial",
101 .of_match_table = octeon_serial_match,
102 },
103};
104
105static int __init octeon_serial_init(void)
106{
107 return platform_driver_register(&octeon_serial_driver);
108}
109late_initcall(octeon_serial_init);
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 01b1b3f94feb..48b08eb9d9e4 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -7,6 +7,7 @@
7 * Copyright (C) 2008, 2009 Wind River Systems 7 * Copyright (C) 2008, 2009 Wind River Systems
8 * written by Ralf Baechle <ralf@linux-mips.org> 8 * written by Ralf Baechle <ralf@linux-mips.org>
9 */ 9 */
10#include <linux/compiler.h>
10#include <linux/init.h> 11#include <linux/init.h>
11#include <linux/kernel.h> 12#include <linux/kernel.h>
12#include <linux/console.h> 13#include <linux/console.h>
@@ -40,12 +41,6 @@
40#include <asm/octeon/pci-octeon.h> 41#include <asm/octeon/pci-octeon.h>
41#include <asm/octeon/cvmx-mio-defs.h> 42#include <asm/octeon/cvmx-mio-defs.h>
42 43
43#ifdef CONFIG_CAVIUM_DECODE_RSL
44extern void cvmx_interrupt_rsl_decode(void);
45extern int __cvmx_interrupt_ecc_report_single_bit_errors;
46extern void cvmx_interrupt_rsl_enable(void);
47#endif
48
49extern struct plat_smp_ops octeon_smp_ops; 44extern struct plat_smp_ops octeon_smp_ops;
50 45
51#ifdef CONFIG_PCI 46#ifdef CONFIG_PCI
@@ -463,18 +458,6 @@ static void octeon_halt(void)
463} 458}
464 459
465/** 460/**
466 * Handle all the error condition interrupts that might occur.
467 *
468 */
469#ifdef CONFIG_CAVIUM_DECODE_RSL
470static irqreturn_t octeon_rlm_interrupt(int cpl, void *dev_id)
471{
472 cvmx_interrupt_rsl_decode();
473 return IRQ_HANDLED;
474}
475#endif
476
477/**
478 * Return a string representing the system type 461 * Return a string representing the system type
479 * 462 *
480 * Returns 463 * Returns
@@ -712,7 +695,7 @@ void __init prom_init(void)
712 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) { 695 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) {
713 pr_info("Skipping L2 locking due to reduced L2 cache size\n"); 696 pr_info("Skipping L2 locking due to reduced L2 cache size\n");
714 } else { 697 } else {
715 uint32_t ebase = read_c0_ebase() & 0x3ffff000; 698 uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000;
716#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB 699#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB
717 /* TLB refill */ 700 /* TLB refill */
718 cvmx_l2c_lock_mem_region(ebase, 0x100); 701 cvmx_l2c_lock_mem_region(ebase, 0x100);
@@ -996,7 +979,7 @@ void __init plat_mem_setup(void)
996 cvmx_bootmem_unlock(); 979 cvmx_bootmem_unlock();
997 /* Add the memory region for the kernel. */ 980 /* Add the memory region for the kernel. */
998 kernel_start = (unsigned long) _text; 981 kernel_start = (unsigned long) _text;
999 kernel_size = ALIGN(_end - _text, 0x100000); 982 kernel_size = _end - _text;
1000 983
1001 /* Adjust for physical offset. */ 984 /* Adjust for physical offset. */
1002 kernel_start &= ~0xffffffff80000000ULL; 985 kernel_start &= ~0xffffffff80000000ULL;
@@ -1064,15 +1047,6 @@ void prom_free_prom_memory(void)
1064 panic("Core-14449 WAR not in place (%04x).\n" 1047 panic("Core-14449 WAR not in place (%04x).\n"
1065 "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", insn); 1048 "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", insn);
1066 } 1049 }
1067#ifdef CONFIG_CAVIUM_DECODE_RSL
1068 cvmx_interrupt_rsl_enable();
1069
1070 /* Add an interrupt handler for general failures. */
1071 if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED,
1072 "RML/RSL", octeon_rlm_interrupt)) {
1073 panic("Unable to request_irq(OCTEON_IRQ_RML)");
1074 }
1075#endif
1076} 1050}
1077 1051
1078int octeon_prune_device_tree(void); 1052int octeon_prune_device_tree(void);
diff --git a/arch/mips/configs/cavium_octeon_defconfig b/arch/mips/configs/cavium_octeon_defconfig
index 014ba4bbba7d..dace58268ce1 100644
--- a/arch/mips/configs/cavium_octeon_defconfig
+++ b/arch/mips/configs/cavium_octeon_defconfig
@@ -1,13 +1,11 @@
1CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD=y 1CONFIG_CAVIUM_OCTEON_SOC=y
2CONFIG_CAVIUM_CN63XXP1=y 2CONFIG_CAVIUM_CN63XXP1=y
3CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=2 3CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=2
4CONFIG_SPARSEMEM_MANUAL=y
5CONFIG_TRANSPARENT_HUGEPAGE=y 4CONFIG_TRANSPARENT_HUGEPAGE=y
6CONFIG_SMP=y 5CONFIG_SMP=y
7CONFIG_NR_CPUS=32 6CONFIG_NR_CPUS=32
8CONFIG_HZ_100=y 7CONFIG_HZ_100=y
9CONFIG_PREEMPT=y 8CONFIG_PREEMPT=y
10CONFIG_EXPERIMENTAL=y
11CONFIG_SYSVIPC=y 9CONFIG_SYSVIPC=y
12CONFIG_POSIX_MQUEUE=y 10CONFIG_POSIX_MQUEUE=y
13CONFIG_BSD_PROCESS_ACCT=y 11CONFIG_BSD_PROCESS_ACCT=y
@@ -50,7 +48,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
50# CONFIG_FW_LOADER is not set 48# CONFIG_FW_LOADER is not set
51CONFIG_MTD=y 49CONFIG_MTD=y
52# CONFIG_MTD_OF_PARTS is not set 50# CONFIG_MTD_OF_PARTS is not set
53CONFIG_MTD_CHAR=y
54CONFIG_MTD_BLOCK=y 51CONFIG_MTD_BLOCK=y
55CONFIG_MTD_CFI=y 52CONFIG_MTD_CFI=y
56CONFIG_MTD_CFI_AMDSTD=y 53CONFIG_MTD_CFI_AMDSTD=y
@@ -114,6 +111,7 @@ CONFIG_SERIAL_8250=y
114CONFIG_SERIAL_8250_CONSOLE=y 111CONFIG_SERIAL_8250_CONSOLE=y
115CONFIG_SERIAL_8250_NR_UARTS=2 112CONFIG_SERIAL_8250_NR_UARTS=2
116CONFIG_SERIAL_8250_RUNTIME_UARTS=2 113CONFIG_SERIAL_8250_RUNTIME_UARTS=2
114CONFIG_SERIAL_8250_DW=y
117# CONFIG_HW_RANDOM is not set 115# CONFIG_HW_RANDOM is not set
118CONFIG_I2C=y 116CONFIG_I2C=y
119CONFIG_I2C_OCTEON=y 117CONFIG_I2C_OCTEON=y
diff --git a/arch/mips/configs/wrppmc_defconfig b/arch/mips/configs/wrppmc_defconfig
deleted file mode 100644
index 44a451be359e..000000000000
--- a/arch/mips/configs/wrppmc_defconfig
+++ /dev/null
@@ -1,97 +0,0 @@
1CONFIG_WR_PPMC=y
2CONFIG_HZ_1000=y
3CONFIG_EXPERIMENTAL=y
4# CONFIG_SWAP is not set
5CONFIG_SYSVIPC=y
6CONFIG_BSD_PROCESS_ACCT=y
7CONFIG_LOG_BUF_SHIFT=14
8CONFIG_BLK_DEV_INITRD=y
9# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
10CONFIG_EXPERT=y
11CONFIG_KALLSYMS_EXTRA_PASS=y
12# CONFIG_EPOLL is not set
13CONFIG_SLAB=y
14CONFIG_MODULES=y
15CONFIG_MODULE_UNLOAD=y
16CONFIG_MODVERSIONS=y
17CONFIG_MODULE_SRCVERSION_ALL=y
18CONFIG_PCI=y
19CONFIG_HOTPLUG_PCI=y
20CONFIG_BINFMT_MISC=y
21CONFIG_PM=y
22CONFIG_NET=y
23CONFIG_PACKET=y
24CONFIG_UNIX=y
25CONFIG_XFRM_MIGRATE=y
26CONFIG_INET=y
27CONFIG_IP_MULTICAST=y
28CONFIG_IP_PNP=y
29CONFIG_IP_PNP_DHCP=y
30CONFIG_IP_PNP_BOOTP=y
31CONFIG_IP_PNP_RARP=y
32CONFIG_IP_MROUTE=y
33CONFIG_ARPD=y
34CONFIG_INET_XFRM_MODE_TRANSPORT=m
35CONFIG_INET_XFRM_MODE_TUNNEL=m
36CONFIG_INET_XFRM_MODE_BEET=m
37CONFIG_TCP_MD5SIG=y
38# CONFIG_IPV6 is not set
39CONFIG_NETWORK_SECMARK=y
40CONFIG_FW_LOADER=m
41CONFIG_BLK_DEV_RAM=y
42CONFIG_SGI_IOC4=m
43CONFIG_NETDEVICES=y
44CONFIG_PHYLIB=y
45CONFIG_VITESSE_PHY=m
46CONFIG_SMSC_PHY=m
47CONFIG_NET_ETHERNET=y
48CONFIG_NET_PCI=y
49CONFIG_E100=y
50CONFIG_QLA3XXX=m
51CONFIG_CHELSIO_T3=m
52CONFIG_NETXEN_NIC=m
53# CONFIG_INPUT is not set
54# CONFIG_SERIO is not set
55# CONFIG_VT is not set
56CONFIG_SERIAL_8250=y
57CONFIG_SERIAL_8250_CONSOLE=y
58CONFIG_SERIAL_8250_NR_UARTS=1
59CONFIG_SERIAL_8250_RUNTIME_UARTS=1
60# CONFIG_HW_RANDOM is not set
61CONFIG_PROC_KCORE=y
62CONFIG_TMPFS=y
63CONFIG_TMPFS_POSIX_ACL=y
64CONFIG_NFS_FS=y
65CONFIG_NFS_V3=y
66CONFIG_ROOT_NFS=y
67CONFIG_DLM=m
68CONFIG_CMDLINE_BOOL=y
69CONFIG_CMDLINE="console=ttyS0,115200n8"
70CONFIG_CRYPTO_NULL=m
71CONFIG_CRYPTO_CBC=m
72CONFIG_CRYPTO_ECB=m
73CONFIG_CRYPTO_LRW=m
74CONFIG_CRYPTO_PCBC=m
75CONFIG_CRYPTO_XCBC=m
76CONFIG_CRYPTO_MD4=m
77CONFIG_CRYPTO_MICHAEL_MIC=m
78CONFIG_CRYPTO_SHA256=m
79CONFIG_CRYPTO_SHA512=m
80CONFIG_CRYPTO_TGR192=m
81CONFIG_CRYPTO_WP512=m
82CONFIG_CRYPTO_ANUBIS=m
83CONFIG_CRYPTO_ARC4=m
84CONFIG_CRYPTO_BLOWFISH=m
85CONFIG_CRYPTO_CAMELLIA=m
86CONFIG_CRYPTO_CAST5=m
87CONFIG_CRYPTO_CAST6=m
88CONFIG_CRYPTO_DES=m
89CONFIG_CRYPTO_FCRYPT=m
90CONFIG_CRYPTO_KHAZAD=m
91CONFIG_CRYPTO_SERPENT=m
92CONFIG_CRYPTO_TEA=m
93CONFIG_CRYPTO_TWOFISH=m
94CONFIG_CRYPTO_DEFLATE=m
95CONFIG_CRC_CCITT=y
96CONFIG_CRC16=y
97CONFIG_LIBCRC32C=y
diff --git a/arch/mips/dec/Makefile b/arch/mips/dec/Makefile
index 9eb2f9c036aa..3d5d2c56de8d 100644
--- a/arch/mips/dec/Makefile
+++ b/arch/mips/dec/Makefile
@@ -5,6 +5,5 @@
5obj-y := ecc-berr.o int-handler.o ioasic-irq.o kn01-berr.o \ 5obj-y := ecc-berr.o int-handler.o ioasic-irq.o kn01-berr.o \
6 kn02-irq.o kn02xa-berr.o reset.o setup.o time.o 6 kn02-irq.o kn02xa-berr.o reset.o setup.o time.o
7 7
8obj-$(CONFIG_PROM_CONSOLE) += promcon.o
9obj-$(CONFIG_TC) += tc.o 8obj-$(CONFIG_TC) += tc.o
10obj-$(CONFIG_CPU_HAS_WB) += wbflush.o 9obj-$(CONFIG_CPU_HAS_WB) += wbflush.o
diff --git a/arch/mips/dec/promcon.c b/arch/mips/dec/promcon.c
deleted file mode 100644
index c239c25b79ff..000000000000
--- a/arch/mips/dec/promcon.c
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * Wrap-around code for a console using the
3 * DECstation PROM io-routines.
4 *
5 * Copyright (c) 1998 Harald Koerfgen
6 */
7
8#include <linux/tty.h>
9#include <linux/ptrace.h>
10#include <linux/init.h>
11#include <linux/console.h>
12#include <linux/fs.h>
13
14#include <asm/dec/prom.h>
15
16static void prom_console_write(struct console *co, const char *s,
17 unsigned count)
18{
19 unsigned i;
20
21 /*
22 * Now, do each character
23 */
24 for (i = 0; i < count; i++) {
25 if (*s == 10)
26 prom_printf("%c", 13);
27 prom_printf("%c", *s++);
28 }
29}
30
31static int __init prom_console_setup(struct console *co, char *options)
32{
33 return 0;
34}
35
36static struct console sercons = {
37 .name = "ttyS",
38 .write = prom_console_write,
39 .setup = prom_console_setup,
40 .flags = CON_PRINTBUFFER,
41 .index = -1,
42};
43
44/*
45 * Register console.
46 */
47
48static int __init prom_console_init(void)
49{
50 register_console(&sercons);
51
52 return 0;
53}
54console_initcall(prom_console_init);
diff --git a/arch/mips/fw/cfe/cfe_api.c b/arch/mips/fw/cfe/cfe_api.c
index d06dc5a6b8d3..cf84f01931c5 100644
--- a/arch/mips/fw/cfe/cfe_api.c
+++ b/arch/mips/fw/cfe/cfe_api.c
@@ -406,12 +406,12 @@ int cfe_setenv(char *name, char *val)
406 return xiocb.xiocb_status; 406 return xiocb.xiocb_status;
407} 407}
408 408
409int cfe_write(int handle, unsigned char *buffer, int length) 409int cfe_write(int handle, const char *buffer, int length)
410{ 410{
411 return cfe_writeblk(handle, 0, buffer, length); 411 return cfe_writeblk(handle, 0, buffer, length);
412} 412}
413 413
414int cfe_writeblk(int handle, s64 offset, unsigned char *buffer, int length) 414int cfe_writeblk(int handle, s64 offset, const char *buffer, int length)
415{ 415{
416 struct cfe_xiocb xiocb; 416 struct cfe_xiocb xiocb;
417 417
diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h
index 3532e2c5f098..c1516cc0285f 100644
--- a/arch/mips/include/asm/cop2.h
+++ b/arch/mips/include/asm/cop2.h
@@ -11,6 +11,35 @@
11 11
12#include <linux/notifier.h> 12#include <linux/notifier.h>
13 13
14#if defined(CONFIG_CPU_CAVIUM_OCTEON)
15
16extern void octeon_cop2_save(struct octeon_cop2_state *);
17extern void octeon_cop2_restore(struct octeon_cop2_state *);
18
19#define cop2_save(r) octeon_cop2_save(r)
20#define cop2_restore(r) octeon_cop2_restore(r)
21
22#define cop2_present 1
23#define cop2_lazy_restore 1
24
25#elif defined(CONFIG_CPU_XLP)
26
27extern void nlm_cop2_save(struct nlm_cop2_state *);
28extern void nlm_cop2_restore(struct nlm_cop2_state *);
29#define cop2_save(r) nlm_cop2_save(r)
30#define cop2_restore(r) nlm_cop2_restore(r)
31
32#define cop2_present 1
33#define cop2_lazy_restore 0
34
35#else
36
37#define cop2_present 0
38#define cop2_lazy_restore 0
39#define cop2_save(r)
40#define cop2_restore(r)
41#endif
42
14enum cu2_ops { 43enum cu2_ops {
15 CU2_EXCEPTION, 44 CU2_EXCEPTION,
16 CU2_LWC2_OP, 45 CU2_LWC2_OP,
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index e5ec8fcd8afa..1dc086087a72 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -24,6 +24,16 @@
24#ifndef cpu_has_tlb 24#ifndef cpu_has_tlb
25#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) 25#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
26#endif 26#endif
27
28/*
29 * For the moment we don't consider R6000 and R8000 so we can assume that
30 * anything that doesn't support R4000-style exceptions and interrupts is
31 * R3000-like. Users should still treat these two macro definitions as
32 * opaque.
33 */
34#ifndef cpu_has_3kex
35#define cpu_has_3kex (!cpu_has_4kex)
36#endif
27#ifndef cpu_has_4kex 37#ifndef cpu_has_4kex
28#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX) 38#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
29#endif 39#endif
@@ -87,19 +97,23 @@
87#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16) 97#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
88#endif 98#endif
89#ifndef cpu_has_mdmx 99#ifndef cpu_has_mdmx
90#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX) 100#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
91#endif 101#endif
92#ifndef cpu_has_mips3d 102#ifndef cpu_has_mips3d
93#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D) 103#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
94#endif 104#endif
95#ifndef cpu_has_smartmips 105#ifndef cpu_has_smartmips
96#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) 106#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
97#endif 107#endif
98#ifndef cpu_has_rixi 108#ifndef cpu_has_rixi
99#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) 109#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
100#endif 110#endif
101#ifndef cpu_has_mmips 111#ifndef cpu_has_mmips
102#define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS) 112# ifdef CONFIG_SYS_SUPPORTS_MICROMIPS
113# define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS)
114# else
115# define cpu_has_mmips 0
116# endif
103#endif 117#endif
104#ifndef cpu_has_vtag_icache 118#ifndef cpu_has_vtag_icache
105#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) 119#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
@@ -111,7 +125,7 @@
111#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) 125#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
112#endif 126#endif
113#ifndef cpu_has_pindexed_dcache 127#ifndef cpu_has_pindexed_dcache
114#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) 128#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
115#endif 129#endif
116#ifndef cpu_has_local_ebase 130#ifndef cpu_has_local_ebase
117#define cpu_has_local_ebase 1 131#define cpu_has_local_ebase 1
@@ -136,7 +150,6 @@
136#endif 150#endif
137#endif 151#endif
138 152
139# define cpu_has_mips_1 (cpu_data[0].isa_level & MIPS_CPU_ISA_I)
140#ifndef cpu_has_mips_2 153#ifndef cpu_has_mips_2
141# define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II) 154# define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II)
142#endif 155#endif
@@ -149,18 +162,18 @@
149#ifndef cpu_has_mips_5 162#ifndef cpu_has_mips_5
150# define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V) 163# define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V)
151#endif 164#endif
152# ifndef cpu_has_mips32r1 165#ifndef cpu_has_mips32r1
153# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) 166# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
154# endif 167#endif
155# ifndef cpu_has_mips32r2 168#ifndef cpu_has_mips32r2
156# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) 169# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
157# endif 170#endif
158# ifndef cpu_has_mips64r1 171#ifndef cpu_has_mips64r1
159# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) 172# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
160# endif 173#endif
161# ifndef cpu_has_mips64r2 174#ifndef cpu_has_mips64r2
162# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) 175# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
163# endif 176#endif
164 177
165/* 178/*
166 * Shortcuts ... 179 * Shortcuts ...
@@ -182,9 +195,9 @@
182 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels 195 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels
183 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. 196 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
184 */ 197 */
185# ifndef cpu_has_clo_clz 198#ifndef cpu_has_clo_clz
186# define cpu_has_clo_clz cpu_has_mips_r 199#define cpu_has_clo_clz cpu_has_mips_r
187# endif 200#endif
188 201
189#ifndef cpu_has_dsp 202#ifndef cpu_has_dsp
190#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) 203#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
@@ -210,7 +223,7 @@
210# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 223# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
211# endif 224# endif
212# ifndef cpu_has_64bit_zero_reg 225# ifndef cpu_has_64bit_zero_reg
213# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 226# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
214# endif 227# endif
215# ifndef cpu_has_64bit_gp_regs 228# ifndef cpu_has_64bit_gp_regs
216# define cpu_has_64bit_gp_regs 0 229# define cpu_has_64bit_gp_regs 0
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index dd86ab205483..632bbe5a79ea 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -282,18 +282,17 @@ enum cpu_type_enum {
282 * ISA Level encodings 282 * ISA Level encodings
283 * 283 *
284 */ 284 */
285#define MIPS_CPU_ISA_I 0x00000001 285#define MIPS_CPU_ISA_II 0x00000001
286#define MIPS_CPU_ISA_II 0x00000002 286#define MIPS_CPU_ISA_III 0x00000002
287#define MIPS_CPU_ISA_III 0x00000004 287#define MIPS_CPU_ISA_IV 0x00000004
288#define MIPS_CPU_ISA_IV 0x00000008 288#define MIPS_CPU_ISA_V 0x00000008
289#define MIPS_CPU_ISA_V 0x00000010 289#define MIPS_CPU_ISA_M32R1 0x00000010
290#define MIPS_CPU_ISA_M32R1 0x00000020 290#define MIPS_CPU_ISA_M32R2 0x00000020
291#define MIPS_CPU_ISA_M32R2 0x00000040 291#define MIPS_CPU_ISA_M64R1 0x00000040
292#define MIPS_CPU_ISA_M64R1 0x00000080 292#define MIPS_CPU_ISA_M64R2 0x00000080
293#define MIPS_CPU_ISA_M64R2 0x00000100 293
294 294#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \
295#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \ 295 MIPS_CPU_ISA_M32R2)
296 MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2)
297#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ 296#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
298 MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2) 297 MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)
299 298
diff --git a/arch/mips/include/asm/fw/cfe/cfe_api.h b/arch/mips/include/asm/fw/cfe/cfe_api.h
index 17347551a1b2..a0ea69e91e2e 100644
--- a/arch/mips/include/asm/fw/cfe/cfe_api.h
+++ b/arch/mips/include/asm/fw/cfe/cfe_api.h
@@ -115,8 +115,8 @@ int cfe_read(int handle, unsigned char *buffer, int length);
115int cfe_readblk(int handle, int64_t offset, unsigned char *buffer, 115int cfe_readblk(int handle, int64_t offset, unsigned char *buffer,
116 int length); 116 int length);
117int cfe_setenv(char *name, char *val); 117int cfe_setenv(char *name, char *val);
118int cfe_write(int handle, unsigned char *buffer, int length); 118int cfe_write(int handle, const char *buffer, int length);
119int cfe_writeblk(int handle, int64_t offset, unsigned char *buffer, 119int cfe_writeblk(int handle, int64_t offset, const char *buffer,
120 int length); 120 int length);
121 121
122#endif /* CFE_API_H */ 122#endif /* CFE_API_H */
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h
index 7153b32de18e..b2e3e93dd7d8 100644
--- a/arch/mips/include/asm/gic.h
+++ b/arch/mips/include/asm/gic.h
@@ -347,7 +347,7 @@ struct gic_shared_intr_map {
347#define GIC_CPU_INT2 2 /* . */ 347#define GIC_CPU_INT2 2 /* . */
348#define GIC_CPU_INT3 3 /* . */ 348#define GIC_CPU_INT3 3 /* . */
349#define GIC_CPU_INT4 4 /* . */ 349#define GIC_CPU_INT4 4 /* . */
350#define GIC_CPU_INT5 5 /* Core Interrupt 5 */ 350#define GIC_CPU_INT5 5 /* Core Interrupt 7 */
351 351
352/* Local GIC interrupts. */ 352/* Local GIC interrupts. */
353#define GIC_INT_TMR (GIC_CPU_INT5) 353#define GIC_INT_TMR (GIC_CPU_INT5)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index b7e59853fd33..3321dd5a8872 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -170,6 +170,11 @@ static inline void * isa_bus_to_virt(unsigned long address)
170extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags); 170extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags);
171extern void __iounmap(const volatile void __iomem *addr); 171extern void __iounmap(const volatile void __iomem *addr);
172 172
173#ifndef CONFIG_PCI
174struct pci_dev;
175static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
176#endif
177
173static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, 178static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
174 unsigned long flags) 179 unsigned long flags)
175{ 180{
@@ -449,6 +454,11 @@ __BUILDIO(q, u64)
449#define readl_relaxed readl 454#define readl_relaxed readl
450#define readq_relaxed readq 455#define readq_relaxed readq
451 456
457#define writeb_relaxed writeb
458#define writew_relaxed writew
459#define writel_relaxed writel
460#define writeq_relaxed writeq
461
452#define readb_be(addr) \ 462#define readb_be(addr) \
453 __raw_readb((__force unsigned *)(addr)) 463 __raw_readb((__force unsigned *)(addr))
454#define readw_be(addr) \ 464#define readw_be(addr) \
diff --git a/arch/mips/include/asm/kspd.h b/arch/mips/include/asm/kspd.h
deleted file mode 100644
index ec6832950ace..000000000000
--- a/arch/mips/include/asm/kspd.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
3 *
4 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 *
17 */
18
19#ifndef _ASM_KSPD_H
20#define _ASM_KSPD_H
21
22struct kspd_notifications {
23 void (*kspd_sp_exit)(int sp_id);
24
25 struct list_head list;
26};
27
28static inline void kspd_notify(struct kspd_notifications *notify)
29{
30}
31
32#endif
diff --git a/arch/mips/include/asm/mach-ar7/spaces.h b/arch/mips/include/asm/mach-ar7/spaces.h
index ac28f273449c..660ab64c0fc9 100644
--- a/arch/mips/include/asm/mach-ar7/spaces.h
+++ b/arch/mips/include/asm/mach-ar7/spaces.h
@@ -14,8 +14,11 @@
14 * This handles the memory map. 14 * This handles the memory map.
15 * We handle pages at KSEG0 for kernels with 32 bit address space. 15 * We handle pages at KSEG0 for kernels with 32 bit address space.
16 */ 16 */
17#define PAGE_OFFSET 0x94000000UL 17#define PAGE_OFFSET _AC(0x94000000, UL)
18#define PHYS_OFFSET 0x14000000UL 18#define PHYS_OFFSET _AC(0x14000000, UL)
19
20#define UNCAC_BASE _AC(0xb4000000, UL) /* 0xa0000000 + PHYS_OFFSET */
21#define IO_BASE UNCAC_BASE
19 22
20#include <asm/mach-generic/spaces.h> 23#include <asm/mach-generic/spaces.h>
21 24
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index e6e65dc7d502..19f9134bfe2f 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -9,6 +9,7 @@
9 * compile time if only one CPU support is enabled (idea stolen from 9 * compile time if only one CPU support is enabled (idea stolen from
10 * arm mach-types) 10 * arm mach-types)
11 */ 11 */
12#define BCM3368_CPU_ID 0x3368
12#define BCM6328_CPU_ID 0x6328 13#define BCM6328_CPU_ID 0x6328
13#define BCM6338_CPU_ID 0x6338 14#define BCM6338_CPU_ID 0x6338
14#define BCM6345_CPU_ID 0x6345 15#define BCM6345_CPU_ID 0x6345
@@ -22,6 +23,19 @@ u16 __bcm63xx_get_cpu_id(void);
22u8 bcm63xx_get_cpu_rev(void); 23u8 bcm63xx_get_cpu_rev(void);
23unsigned int bcm63xx_get_cpu_freq(void); 24unsigned int bcm63xx_get_cpu_freq(void);
24 25
26#ifdef CONFIG_BCM63XX_CPU_3368
27# ifdef bcm63xx_get_cpu_id
28# undef bcm63xx_get_cpu_id
29# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
30# define BCMCPU_RUNTIME_DETECT
31# else
32# define bcm63xx_get_cpu_id() BCM3368_CPU_ID
33# endif
34# define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID)
35#else
36# define BCMCPU_IS_3368() (0)
37#endif
38
25#ifdef CONFIG_BCM63XX_CPU_6328 39#ifdef CONFIG_BCM63XX_CPU_6328
26# ifdef bcm63xx_get_cpu_id 40# ifdef bcm63xx_get_cpu_id
27# undef bcm63xx_get_cpu_id 41# undef bcm63xx_get_cpu_id
@@ -194,6 +208,53 @@ enum bcm63xx_regs_set {
194#define RSET_RNG_SIZE 20 208#define RSET_RNG_SIZE 20
195 209
196/* 210/*
211 * 3368 register sets base address
212 */
213#define BCM_3368_DSL_LMEM_BASE (0xdeadbeef)
214#define BCM_3368_PERF_BASE (0xfff8c000)
215#define BCM_3368_TIMER_BASE (0xfff8c040)
216#define BCM_3368_WDT_BASE (0xfff8c080)
217#define BCM_3368_UART0_BASE (0xfff8c100)
218#define BCM_3368_UART1_BASE (0xfff8c120)
219#define BCM_3368_GPIO_BASE (0xfff8c080)
220#define BCM_3368_SPI_BASE (0xfff8c800)
221#define BCM_3368_HSSPI_BASE (0xdeadbeef)
222#define BCM_3368_UDC0_BASE (0xdeadbeef)
223#define BCM_3368_USBDMA_BASE (0xdeadbeef)
224#define BCM_3368_OHCI0_BASE (0xdeadbeef)
225#define BCM_3368_OHCI_PRIV_BASE (0xdeadbeef)
226#define BCM_3368_USBH_PRIV_BASE (0xdeadbeef)
227#define BCM_3368_USBD_BASE (0xdeadbeef)
228#define BCM_3368_MPI_BASE (0xfff80000)
229#define BCM_3368_PCMCIA_BASE (0xfff80054)
230#define BCM_3368_PCIE_BASE (0xdeadbeef)
231#define BCM_3368_SDRAM_REGS_BASE (0xdeadbeef)
232#define BCM_3368_DSL_BASE (0xdeadbeef)
233#define BCM_3368_UBUS_BASE (0xdeadbeef)
234#define BCM_3368_ENET0_BASE (0xfff98000)
235#define BCM_3368_ENET1_BASE (0xfff98800)
236#define BCM_3368_ENETDMA_BASE (0xfff99800)
237#define BCM_3368_ENETDMAC_BASE (0xfff99900)
238#define BCM_3368_ENETDMAS_BASE (0xfff99a00)
239#define BCM_3368_ENETSW_BASE (0xdeadbeef)
240#define BCM_3368_EHCI0_BASE (0xdeadbeef)
241#define BCM_3368_SDRAM_BASE (0xdeadbeef)
242#define BCM_3368_MEMC_BASE (0xfff84000)
243#define BCM_3368_DDR_BASE (0xdeadbeef)
244#define BCM_3368_M2M_BASE (0xdeadbeef)
245#define BCM_3368_ATM_BASE (0xdeadbeef)
246#define BCM_3368_XTM_BASE (0xdeadbeef)
247#define BCM_3368_XTMDMA_BASE (0xdeadbeef)
248#define BCM_3368_XTMDMAC_BASE (0xdeadbeef)
249#define BCM_3368_XTMDMAS_BASE (0xdeadbeef)
250#define BCM_3368_PCM_BASE (0xfff9c200)
251#define BCM_3368_PCMDMA_BASE (0xdeadbeef)
252#define BCM_3368_PCMDMAC_BASE (0xdeadbeef)
253#define BCM_3368_PCMDMAS_BASE (0xdeadbeef)
254#define BCM_3368_RNG_BASE (0xdeadbeef)
255#define BCM_3368_MISC_BASE (0xdeadbeef)
256
257/*
197 * 6328 register sets base address 258 * 6328 register sets base address
198 */ 259 */
199#define BCM_6328_DSL_LMEM_BASE (0xdeadbeef) 260#define BCM_6328_DSL_LMEM_BASE (0xdeadbeef)
@@ -238,6 +299,8 @@ enum bcm63xx_regs_set {
238#define BCM_6328_PCMDMAS_BASE (0xdeadbeef) 299#define BCM_6328_PCMDMAS_BASE (0xdeadbeef)
239#define BCM_6328_RNG_BASE (0xdeadbeef) 300#define BCM_6328_RNG_BASE (0xdeadbeef)
240#define BCM_6328_MISC_BASE (0xb0001800) 301#define BCM_6328_MISC_BASE (0xb0001800)
302#define BCM_6328_OTP_BASE (0xb0000600)
303
241/* 304/*
242 * 6338 register sets base address 305 * 6338 register sets base address
243 */ 306 */
@@ -623,6 +686,9 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
623#ifdef BCMCPU_RUNTIME_DETECT 686#ifdef BCMCPU_RUNTIME_DETECT
624 return bcm63xx_regs_base[set]; 687 return bcm63xx_regs_base[set];
625#else 688#else
689#ifdef CONFIG_BCM63XX_CPU_3368
690 __GEN_RSET(3368)
691#endif
626#ifdef CONFIG_BCM63XX_CPU_6328 692#ifdef CONFIG_BCM63XX_CPU_6328
627 __GEN_RSET(6328) 693 __GEN_RSET(6328)
628#endif 694#endif
@@ -690,6 +756,52 @@ enum bcm63xx_irq {
690}; 756};
691 757
692/* 758/*
759 * 3368 irqs
760 */
761#define BCM_3368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
762#define BCM_3368_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
763#define BCM_3368_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
764#define BCM_3368_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
765#define BCM_3368_DSL_IRQ 0
766#define BCM_3368_UDC0_IRQ 0
767#define BCM_3368_OHCI0_IRQ 0
768#define BCM_3368_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
769#define BCM_3368_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
770#define BCM_3368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
771#define BCM_3368_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
772#define BCM_3368_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
773#define BCM_3368_HSSPI_IRQ 0
774#define BCM_3368_EHCI0_IRQ 0
775#define BCM_3368_USBD_IRQ 0
776#define BCM_3368_USBD_RXDMA0_IRQ 0
777#define BCM_3368_USBD_TXDMA0_IRQ 0
778#define BCM_3368_USBD_RXDMA1_IRQ 0
779#define BCM_3368_USBD_TXDMA1_IRQ 0
780#define BCM_3368_USBD_RXDMA2_IRQ 0
781#define BCM_3368_USBD_TXDMA2_IRQ 0
782#define BCM_3368_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
783#define BCM_3368_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
784#define BCM_3368_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
785#define BCM_3368_PCMCIA_IRQ 0
786#define BCM_3368_ATM_IRQ 0
787#define BCM_3368_ENETSW_RXDMA0_IRQ 0
788#define BCM_3368_ENETSW_RXDMA1_IRQ 0
789#define BCM_3368_ENETSW_RXDMA2_IRQ 0
790#define BCM_3368_ENETSW_RXDMA3_IRQ 0
791#define BCM_3368_ENETSW_TXDMA0_IRQ 0
792#define BCM_3368_ENETSW_TXDMA1_IRQ 0
793#define BCM_3368_ENETSW_TXDMA2_IRQ 0
794#define BCM_3368_ENETSW_TXDMA3_IRQ 0
795#define BCM_3368_XTM_IRQ 0
796#define BCM_3368_XTM_DMA0_IRQ 0
797
798#define BCM_3368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25)
799#define BCM_3368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26)
800#define BCM_3368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
801#define BCM_3368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
802
803
804/*
693 * 6328 irqs 805 * 6328 irqs
694 */ 806 */
695#define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) 807#define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
index 35baa1a60a64..565ff36a1119 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
@@ -11,6 +11,7 @@ static inline unsigned long bcm63xx_gpio_count(void)
11 switch (bcm63xx_get_cpu_id()) { 11 switch (bcm63xx_get_cpu_id()) {
12 case BCM6328_CPU_ID: 12 case BCM6328_CPU_ID:
13 return 32; 13 return 32;
14 case BCM3368_CPU_ID:
14 case BCM6358_CPU_ID: 15 case BCM6358_CPU_ID:
15 return 40; 16 return 40;
16 case BCM6338_CPU_ID: 17 case BCM6338_CPU_ID:
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index eff7ca7d12b0..9875db31d883 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -15,6 +15,39 @@
15/* Clock Control register */ 15/* Clock Control register */
16#define PERF_CKCTL_REG 0x4 16#define PERF_CKCTL_REG 0x4
17 17
18#define CKCTL_3368_MAC_EN (1 << 3)
19#define CKCTL_3368_TC_EN (1 << 5)
20#define CKCTL_3368_US_TOP_EN (1 << 6)
21#define CKCTL_3368_DS_TOP_EN (1 << 7)
22#define CKCTL_3368_APM_EN (1 << 8)
23#define CKCTL_3368_SPI_EN (1 << 9)
24#define CKCTL_3368_USBS_EN (1 << 10)
25#define CKCTL_3368_BMU_EN (1 << 11)
26#define CKCTL_3368_PCM_EN (1 << 12)
27#define CKCTL_3368_NTP_EN (1 << 13)
28#define CKCTL_3368_ACP_B_EN (1 << 14)
29#define CKCTL_3368_ACP_A_EN (1 << 15)
30#define CKCTL_3368_EMUSB_EN (1 << 17)
31#define CKCTL_3368_ENET0_EN (1 << 18)
32#define CKCTL_3368_ENET1_EN (1 << 19)
33#define CKCTL_3368_USBU_EN (1 << 20)
34#define CKCTL_3368_EPHY_EN (1 << 21)
35
36#define CKCTL_3368_ALL_SAFE_EN (CKCTL_3368_MAC_EN | \
37 CKCTL_3368_TC_EN | \
38 CKCTL_3368_US_TOP_EN | \
39 CKCTL_3368_DS_TOP_EN | \
40 CKCTL_3368_APM_EN | \
41 CKCTL_3368_SPI_EN | \
42 CKCTL_3368_USBS_EN | \
43 CKCTL_3368_BMU_EN | \
44 CKCTL_3368_PCM_EN | \
45 CKCTL_3368_NTP_EN | \
46 CKCTL_3368_ACP_B_EN | \
47 CKCTL_3368_ACP_A_EN | \
48 CKCTL_3368_EMUSB_EN | \
49 CKCTL_3368_USBU_EN)
50
18#define CKCTL_6328_PHYMIPS_EN (1 << 0) 51#define CKCTL_6328_PHYMIPS_EN (1 << 0)
19#define CKCTL_6328_ADSL_QPROC_EN (1 << 1) 52#define CKCTL_6328_ADSL_QPROC_EN (1 << 1)
20#define CKCTL_6328_ADSL_AFE_EN (1 << 2) 53#define CKCTL_6328_ADSL_AFE_EN (1 << 2)
@@ -181,6 +214,7 @@
181#define SYS_PLL_SOFT_RESET 0x1 214#define SYS_PLL_SOFT_RESET 0x1
182 215
183/* Interrupt Mask register */ 216/* Interrupt Mask register */
217#define PERF_IRQMASK_3368_REG 0xc
184#define PERF_IRQMASK_6328_REG 0x20 218#define PERF_IRQMASK_6328_REG 0x20
185#define PERF_IRQMASK_6338_REG 0xc 219#define PERF_IRQMASK_6338_REG 0xc
186#define PERF_IRQMASK_6345_REG 0xc 220#define PERF_IRQMASK_6345_REG 0xc
@@ -190,6 +224,7 @@
190#define PERF_IRQMASK_6368_REG 0x20 224#define PERF_IRQMASK_6368_REG 0x20
191 225
192/* Interrupt Status register */ 226/* Interrupt Status register */
227#define PERF_IRQSTAT_3368_REG 0x10
193#define PERF_IRQSTAT_6328_REG 0x28 228#define PERF_IRQSTAT_6328_REG 0x28
194#define PERF_IRQSTAT_6338_REG 0x10 229#define PERF_IRQSTAT_6338_REG 0x10
195#define PERF_IRQSTAT_6345_REG 0x10 230#define PERF_IRQSTAT_6345_REG 0x10
@@ -199,6 +234,7 @@
199#define PERF_IRQSTAT_6368_REG 0x28 234#define PERF_IRQSTAT_6368_REG 0x28
200 235
201/* External Interrupt Configuration register */ 236/* External Interrupt Configuration register */
237#define PERF_EXTIRQ_CFG_REG_3368 0x14
202#define PERF_EXTIRQ_CFG_REG_6328 0x18 238#define PERF_EXTIRQ_CFG_REG_6328 0x18
203#define PERF_EXTIRQ_CFG_REG_6338 0x14 239#define PERF_EXTIRQ_CFG_REG_6338 0x14
204#define PERF_EXTIRQ_CFG_REG_6345 0x14 240#define PERF_EXTIRQ_CFG_REG_6345 0x14
@@ -236,6 +272,13 @@
236#define PERF_SOFTRESET_6362_REG 0x10 272#define PERF_SOFTRESET_6362_REG 0x10
237#define PERF_SOFTRESET_6368_REG 0x10 273#define PERF_SOFTRESET_6368_REG 0x10
238 274
275#define SOFTRESET_3368_SPI_MASK (1 << 0)
276#define SOFTRESET_3368_ENET_MASK (1 << 2)
277#define SOFTRESET_3368_MPI_MASK (1 << 3)
278#define SOFTRESET_3368_EPHY_MASK (1 << 6)
279#define SOFTRESET_3368_USBS_MASK (1 << 11)
280#define SOFTRESET_3368_PCM_MASK (1 << 13)
281
239#define SOFTRESET_6328_SPI_MASK (1 << 0) 282#define SOFTRESET_6328_SPI_MASK (1 << 0)
240#define SOFTRESET_6328_EPHY_MASK (1 << 1) 283#define SOFTRESET_6328_EPHY_MASK (1 << 1)
241#define SOFTRESET_6328_SAR_MASK (1 << 2) 284#define SOFTRESET_6328_SAR_MASK (1 << 2)
@@ -1370,7 +1413,7 @@
1370#define SPI_6348_RX_DATA 0x80 1413#define SPI_6348_RX_DATA 0x80
1371#define SPI_6348_RX_DATA_SIZE 0x3f 1414#define SPI_6348_RX_DATA_SIZE 0x3f
1372 1415
1373/* BCM 6358/6262/6368 SPI core */ 1416/* BCM 3368/6358/6262/6368 SPI core */
1374#define SPI_6358_MSG_CTL 0x00 /* 16-bits register */ 1417#define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
1375#define SPI_6358_MSG_CTL_WIDTH 16 1418#define SPI_6358_MSG_CTL_WIDTH 16
1376#define SPI_6358_MSG_DATA 0x02 1419#define SPI_6358_MSG_DATA 0x02
@@ -1511,4 +1554,11 @@
1511 1554
1512#define PCIE_DEVICE_OFFSET 0x8000 1555#define PCIE_DEVICE_OFFSET 0x8000
1513 1556
1557/*************************************************************************
1558 * _REG relative to RSET_OTP
1559 *************************************************************************/
1560
1561#define OTP_USER_BITS_6328_REG(i) (0x20 + (i) * 4)
1562#define OTP_6328_REG3_TP1_DISABLED BIT(9)
1563
1514#endif /* BCM63XX_REGS_H_ */ 1564#endif /* BCM63XX_REGS_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
index d9aee1a833f3..b86a0efba665 100644
--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
@@ -47,6 +47,12 @@ struct board_info {
47 47
48 /* GPIO LEDs */ 48 /* GPIO LEDs */
49 struct gpio_led leds[5]; 49 struct gpio_led leds[5];
50
51 /* External PHY reset GPIO */
52 unsigned int ephy_reset_gpio;
53
54 /* External PHY reset GPIO flags from gpio.h */
55 unsigned long ephy_reset_gpio_flags;
50}; 56};
51 57
52#endif /* ! BOARD_BCM963XX_H_ */ 58#endif /* ! BOARD_BCM963XX_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
index 94e3011ba7df..ff15e3b14e7a 100644
--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
+++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
@@ -11,6 +11,10 @@ static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
11static inline int is_bcm63xx_internal_registers(phys_t offset) 11static inline int is_bcm63xx_internal_registers(phys_t offset)
12{ 12{
13 switch (bcm63xx_get_cpu_id()) { 13 switch (bcm63xx_get_cpu_id()) {
14 case BCM3368_CPU_ID:
15 if (offset >= 0xfff80000)
16 return 1;
17 break;
14 case BCM6338_CPU_ID: 18 case BCM6338_CPU_ID:
15 case BCM6345_CPU_ID: 19 case BCM6345_CPU_ID:
16 case BCM6348_CPU_ID: 20 case BCM6348_CPU_ID:
diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
index be8fb4240cec..47fb247f9663 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
@@ -13,6 +13,8 @@
13#ifndef __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H 13#ifndef __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
14#define __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H 14#define __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
15 15
16#include <linux/bug.h>
17
16struct device; 18struct device;
17 19
18extern void octeon_pci_dma_init(void); 20extern void octeon_pci_dma_init(void);
@@ -21,18 +23,21 @@ static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
21 size_t size) 23 size_t size)
22{ 24{
23 BUG(); 25 BUG();
26 return 0;
24} 27}
25 28
26static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, 29static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
27 struct page *page) 30 struct page *page)
28{ 31{
29 BUG(); 32 BUG();
33 return 0;
30} 34}
31 35
32static inline unsigned long plat_dma_addr_to_phys(struct device *dev, 36static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
33 dma_addr_t dma_addr) 37 dma_addr_t dma_addr)
34{ 38{
35 BUG(); 39 BUG();
40 return 0;
36} 41}
37 42
38static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, 43static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
@@ -44,6 +49,7 @@ static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
44static inline int plat_dma_supported(struct device *dev, u64 mask) 49static inline int plat_dma_supported(struct device *dev, u64 mask)
45{ 50{
46 BUG(); 51 BUG();
52 return 0;
47} 53}
48 54
49static inline void plat_extra_sync_for_device(struct device *dev) 55static inline void plat_extra_sync_for_device(struct device *dev)
@@ -60,6 +66,7 @@ static inline int plat_dma_mapping_error(struct device *dev,
60 dma_addr_t dma_addr) 66 dma_addr_t dma_addr)
61{ 67{
62 BUG(); 68 BUG();
69 return 0;
63} 70}
64 71
65dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr); 72dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index 1e7dbb192657..1668ee57acb9 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -34,15 +34,10 @@
34 ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE 34 ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
35 dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register 35 dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register
36 dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register 36 dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register
37#ifdef CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED
38 # Disable unaligned load/store support but leave HW fixup enabled 37 # Disable unaligned load/store support but leave HW fixup enabled
38 # Needed for octeon specific memcpy
39 or v0, v0, 0x5001 39 or v0, v0, 0x5001
40 xor v0, v0, 0x1001 40 xor v0, v0, 0x1001
41#else
42 # Disable unaligned load/store and HW fixup support
43 or v0, v0, 0x5001
44 xor v0, v0, 0x5001
45#endif
46 # Read the processor ID register 41 # Read the processor ID register
47 mfc0 v1, CP0_PRID_REG 42 mfc0 v1, CP0_PRID_REG
48 # Disable instruction prefetching (Octeon Pass1 errata) 43 # Disable instruction prefetching (Octeon Pass1 errata)
diff --git a/arch/mips/include/asm/mach-cavium-octeon/spaces.h b/arch/mips/include/asm/mach-cavium-octeon/spaces.h
new file mode 100644
index 000000000000..daa91accf5ab
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/spaces.h
@@ -0,0 +1,24 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 Cavium, Inc.
7 */
8#ifndef _ASM_MACH_CAVIUM_OCTEON_SPACES_H
9#define _ASM_MACH_CAVIUM_OCTEON_SPACES_H
10
11#include <linux/const.h>
12
13#ifdef CONFIG_64BIT
14/* They are all the same and some OCTEON II cores cannot handle 0xa8.. */
15#define CAC_BASE _AC(0x8000000000000000, UL)
16#define UNCAC_BASE _AC(0x8000000000000000, UL)
17#define IO_BASE _AC(0x8000000000000000, UL)
18
19
20#endif /* CONFIG_64BIT */
21
22#include <asm/mach-generic/spaces.h>
23
24#endif /* _ASM_MACH_CAVIUM_OCTEON_SPACES_H */
diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h
index fe23034aaf72..74cb99257d5b 100644
--- a/arch/mips/include/asm/mach-generic/dma-coherence.h
+++ b/arch/mips/include/asm/mach-generic/dma-coherence.h
@@ -66,4 +66,16 @@ static inline int plat_device_is_coherent(struct device *dev)
66#endif 66#endif
67} 67}
68 68
69#ifdef CONFIG_SWIOTLB
70static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
71{
72 return paddr;
73}
74
75static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
76{
77 return daddr;
78}
79#endif
80
69#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */ 81#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-generic/kernel-entry-init.h b/arch/mips/include/asm/mach-generic/kernel-entry-init.h
index 7e66505fa574..13b0751b010a 100644
--- a/arch/mips/include/asm/mach-generic/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-generic/kernel-entry-init.h
@@ -12,8 +12,8 @@
12/* Intentionally empty macro, used in head.S. Override in 12/* Intentionally empty macro, used in head.S. Override in
13 * arch/mips/mach-xxx/kernel-entry-init.h when necessary. 13 * arch/mips/mach-xxx/kernel-entry-init.h when necessary.
14 */ 14 */
15.macro kernel_entry_setup 15 .macro kernel_entry_setup
16.endm 16 .endm
17 17
18/* 18/*
19 * Do SMP slave processor setup necessary before we can savely execute C code. 19 * Do SMP slave processor setup necessary before we can savely execute C code.
diff --git a/arch/mips/include/asm/mach-ip27/kernel-entry-init.h b/arch/mips/include/asm/mach-ip27/kernel-entry-init.h
index a323efb720dc..b087cb83da3a 100644
--- a/arch/mips/include/asm/mach-ip27/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-ip27/kernel-entry-init.h
@@ -24,6 +24,53 @@
24 .endm 24 .endm
25 25
26/* 26/*
27 * TLB bits
28 */
29#define PAGE_GLOBAL (1 << 6)
30#define PAGE_VALID (1 << 7)
31#define PAGE_DIRTY (1 << 8)
32#define CACHE_CACHABLE_COW (5 << 9)
33
34 /*
35 * inputs are the text nasid in t1, data nasid in t2.
36 */
37 .macro MAPPED_KERNEL_SETUP_TLB
38#ifdef CONFIG_MAPPED_KERNEL
39 /*
40 * This needs to read the nasid - assume 0 for now.
41 * Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0,
42 * 0+DVG in tlblo_1.
43 */
44 dli t0, 0xffffffffc0000000
45 dmtc0 t0, CP0_ENTRYHI
46 li t0, 0x1c000 # Offset of text into node memory
47 dsll t1, NASID_SHFT # Shift text nasid into place
48 dsll t2, NASID_SHFT # Same for data nasid
49 or t1, t1, t0 # Physical load address of kernel text
50 or t2, t2, t0 # Physical load address of kernel data
51 dsrl t1, 12 # 4K pfn
52 dsrl t2, 12 # 4K pfn
53 dsll t1, 6 # Get pfn into place
54 dsll t2, 6 # Get pfn into place
55 li t0, ((PAGE_GLOBAL | PAGE_VALID | CACHE_CACHABLE_COW) >> 6)
56 or t0, t0, t1
57 mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr
58 li t0, ((PAGE_GLOBAL | PAGE_VALID | PAGE_DIRTY | CACHE_CACHABLE_COW) >> 6)
59 or t0, t0, t2
60 mtc0 t0, CP0_ENTRYLO1 # physaddr, DVG, cach exlwr
61 li t0, 0x1ffe000 # MAPPED_KERN_TLBMASK, TLBPGMASK_16M
62 mtc0 t0, CP0_PAGEMASK
63 li t0, 0 # KMAP_INX
64 mtc0 t0, CP0_INDEX
65 li t0, 1
66 mtc0 t0, CP0_WIRED
67 tlbwi
68#else
69 mtc0 zero, CP0_WIRED
70#endif
71 .endm
72
73/*
27 * Intentionally empty macro, used in head.S. Override in 74 * Intentionally empty macro, used in head.S. Override in
28 * arch/mips/mach-xxx/kernel-entry-init.h when necessary. 75 * arch/mips/mach-xxx/kernel-entry-init.h when necessary.
29 */ 76 */
diff --git a/arch/mips/include/asm/mach-ip28/spaces.h b/arch/mips/include/asm/mach-ip28/spaces.h
index 5edf05d9dad8..5d6a76434d00 100644
--- a/arch/mips/include/asm/mach-ip28/spaces.h
+++ b/arch/mips/include/asm/mach-ip28/spaces.h
@@ -11,11 +11,14 @@
11#ifndef _ASM_MACH_IP28_SPACES_H 11#ifndef _ASM_MACH_IP28_SPACES_H
12#define _ASM_MACH_IP28_SPACES_H 12#define _ASM_MACH_IP28_SPACES_H
13 13
14#define CAC_BASE 0xa800000000000000 14#define CAC_BASE _AC(0xa800000000000000, UL)
15 15
16#define HIGHMEM_START (~0UL) 16#define HIGHMEM_START (~0UL)
17 17
18#define PHYS_OFFSET _AC(0x20000000, UL) 18#define PHYS_OFFSET _AC(0x20000000, UL)
19
20#define UNCAC_BASE _AC(0xc0000000, UL) /* 0xa0000000 + PHYS_OFFSET */
21#define IO_BASE UNCAC_BASE
19 22
20#include <asm/mach-generic/spaces.h> 23#include <asm/mach-generic/spaces.h>
21 24
diff --git a/arch/mips/include/asm/mach-pmcs-msp71xx/gpio.h b/arch/mips/include/asm/mach-pmcs-msp71xx/gpio.h
deleted file mode 100644
index ebdbab973e41..000000000000
--- a/arch/mips/include/asm/mach-pmcs-msp71xx/gpio.h
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * include/asm-mips/pmc-sierra/msp71xx/gpio.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * @author Patrick Glass <patrickglass@gmail.com>
9 */
10
11#ifndef __PMC_MSP71XX_GPIO_H
12#define __PMC_MSP71XX_GPIO_H
13
14/* Max number of gpio's is 28 on chip plus 3 banks of I2C IO Expanders */
15#define ARCH_NR_GPIOS (28 + (3 * 8))
16
17/* new generic GPIO API - see Documentation/gpio.txt */
18#include <asm-generic/gpio.h>
19
20#define gpio_get_value __gpio_get_value
21#define gpio_set_value __gpio_set_value
22#define gpio_cansleep __gpio_cansleep
23
24/* Setup calls for the gpio and gpio extended */
25extern void msp71xx_init_gpio(void);
26extern void msp71xx_init_gpio_extended(void);
27extern int msp71xx_set_output_drive(unsigned gpio, int value);
28
29/* Custom output drive functionss */
30static inline int gpio_set_output_drive(unsigned gpio, int value)
31{
32 return msp71xx_set_output_drive(gpio, value);
33}
34
35/* IRQ's are not supported for gpio lines */
36static inline int gpio_to_irq(unsigned gpio)
37{
38 return -EINVAL;
39}
40
41static inline int irq_to_gpio(unsigned irq)
42{
43 return -EINVAL;
44}
45
46#endif /* __PMC_MSP71XX_GPIO_H */
diff --git a/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h b/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h
deleted file mode 100644
index 00fa3684ac98..000000000000
--- a/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h
+++ /dev/null
@@ -1,83 +0,0 @@
1/*
2 * This is a direct copy of the ev96100.h file, with a global
3 * search and replace. The numbers are the same.
4 *
5 * The reason I'm duplicating this is so that the 64120/96100
6 * defines won't be confusing in the source code.
7 */
8#ifndef __ASM_MIPS_GT64120_H
9#define __ASM_MIPS_GT64120_H
10
11/*
12 * This is the CPU physical memory map of PPMC Board:
13 *
14 * 0x00000000-0x03FFFFFF - 64MB SDRAM (SCS[0]#)
15 * 0x1C000000-0x1C000000 - LED (CS0)
16 * 0x1C800000-0x1C800007 - UART 16550 port (CS1)
17 * 0x1F000000-0x1F000000 - MailBox (CS3)
18 * 0x1FC00000-0x20000000 - 4MB Flash (BOOT CS)
19 */
20
21#define WRPPMC_SDRAM_SCS0_BASE 0x00000000
22#define WRPPMC_SDRAM_SCS0_SIZE 0x04000000
23
24#define WRPPMC_UART16550_BASE 0x1C800000
25#define WRPPMC_UART16550_CLOCK 3686400 /* 3.68MHZ */
26
27#define WRPPMC_LED_BASE 0x1C000000
28#define WRPPMC_MBOX_BASE 0x1F000000
29
30#define WRPPMC_BOOTROM_BASE 0x1FC00000
31#define WRPPMC_BOOTROM_SIZE 0x00400000 /* 4M Flash */
32
33#define WRPPMC_MIPS_TIMER_IRQ 7 /* MIPS compare/count timer interrupt */
34#define WRPPMC_UART16550_IRQ 6
35#define WRPPMC_PCI_INTA_IRQ 3
36
37/*
38 * PCI Bus I/O and Memory resources allocation
39 *
40 * NOTE: We only have PCI_0 hose interface
41 */
42#define GT_PCI_MEM_BASE 0x13000000UL
43#define GT_PCI_MEM_SIZE 0x02000000UL
44#define GT_PCI_IO_BASE 0x11000000UL
45#define GT_PCI_IO_SIZE 0x02000000UL
46
47/*
48 * PCI interrupts will come in on either the INTA or INTD interrupt lines,
49 * which are mapped to the #2 and #5 interrupt pins of the MIPS. On our
50 * boards, they all either come in on IntD or they all come in on IntA, they
51 * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the
52 * "requested" interrupt numbers and go through the list whenever we get an
53 * IntA/D.
54 *
55 * Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and
56 * INTD is 11.
57 */
58#define GT_TIMER 4
59#define GT_INTA 2
60#define GT_INTD 5
61
62#ifndef __ASSEMBLY__
63
64/*
65 * GT64120 internal register space base address
66 */
67extern unsigned long gt64120_base;
68
69#define GT64120_BASE (gt64120_base)
70
71/* define WRPPMC_EARLY_DEBUG to enable early output something to UART */
72#undef WRPPMC_EARLY_DEBUG
73
74#ifdef WRPPMC_EARLY_DEBUG
75extern void wrppmc_led_on(int mask);
76extern void wrppmc_led_off(int mask);
77extern void wrppmc_early_printk(const char *fmt, ...);
78#else
79#define wrppmc_early_printk(fmt, ...) do {} while (0)
80#endif /* WRPPMC_EARLY_DEBUG */
81
82#endif /* __ASSEMBLY__ */
83#endif /* __ASM_MIPS_GT64120_H */
diff --git a/arch/mips/include/asm/mach-wrppmc/war.h b/arch/mips/include/asm/mach-wrppmc/war.h
deleted file mode 100644
index e86084c0bd6b..000000000000
--- a/arch/mips/include/asm/mach-wrppmc/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_WRPPMC_WAR_H
9#define __ASM_MIPS_MACH_WRPPMC_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define ICACHE_REFILLS_WORKAROUND_WAR 1
21#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0
23
24#endif /* __ASM_MIPS_MACH_WRPPMC_WAR_H */
diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h
index bd9746fbe4af..48616816bcbc 100644
--- a/arch/mips/include/asm/mips-boards/generic.h
+++ b/arch/mips/include/asm/mips-boards/generic.h
@@ -24,12 +24,6 @@
24#define ASCII_DISPLAY_POS_BASE 0x1f000418 24#define ASCII_DISPLAY_POS_BASE 0x1f000418
25 25
26/* 26/*
27 * Reset register.
28 */
29#define SOFTRES_REG 0x1f000500
30#define GORESET 0x42
31
32/*
33 * Revision register. 27 * Revision register.
34 */ 28 */
35#define MIPS_REVISION_REG 0x1fc00010 29#define MIPS_REVISION_REG 0x1fc00010
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 87e6207b05e4..fed1c3e9b486 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -596,7 +596,7 @@
596#define MIPS_CONF3_RXI (_ULCAST_(1) << 12) 596#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
597#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 597#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
598#define MIPS_CONF3_ISA (_ULCAST_(3) << 14) 598#define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
599#define MIPS_CONF3_ISA_OE (_ULCAST_(3) << 16) 599#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
600#define MIPS_CONF3_VZ (_ULCAST_(1) << 23) 600#define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
601 601
602#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) 602#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 516e6e9a5594..3b29079b5424 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -28,11 +28,7 @@
28 28
29#define TLBMISS_HANDLER_SETUP_PGD(pgd) \ 29#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
30do { \ 30do { \
31 void (*tlbmiss_handler_setup_pgd)(unsigned long); \ 31 extern void tlbmiss_handler_setup_pgd(unsigned long); \
32 extern u32 tlbmiss_handler_setup_pgd_array[16]; \
33 \
34 tlbmiss_handler_setup_pgd = \
35 (__typeof__(tlbmiss_handler_setup_pgd)) tlbmiss_handler_setup_pgd_array; \
36 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \ 32 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \
37} while (0) 33} while (0)
38 34
diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h
index aef560a51a7e..bb68c3398c80 100644
--- a/arch/mips/include/asm/netlogic/common.h
+++ b/arch/mips/include/asm/netlogic/common.h
@@ -39,11 +39,17 @@
39 * Common SMP definitions 39 * Common SMP definitions
40 */ 40 */
41#define RESET_VEC_PHYS 0x1fc00000 41#define RESET_VEC_PHYS 0x1fc00000
42#define RESET_VEC_SIZE 8192 /* 8KB reset code and data */
42#define RESET_DATA_PHYS (RESET_VEC_PHYS + (1<<10)) 43#define RESET_DATA_PHYS (RESET_VEC_PHYS + (1<<10))
44
45/* Offsets of parameters in the RESET_DATA_PHYS area */
43#define BOOT_THREAD_MODE 0 46#define BOOT_THREAD_MODE 0
44#define BOOT_NMI_LOCK 4 47#define BOOT_NMI_LOCK 4
45#define BOOT_NMI_HANDLER 8 48#define BOOT_NMI_HANDLER 8
46 49
50/* CPU ready flags for each CPU */
51#define BOOT_CPU_READY 2048
52
47#ifndef __ASSEMBLY__ 53#ifndef __ASSEMBLY__
48#include <linux/cpumask.h> 54#include <linux/cpumask.h>
49#include <linux/spinlock.h> 55#include <linux/spinlock.h>
@@ -59,23 +65,32 @@ int nlm_wakeup_secondary_cpus(void);
59void nlm_rmiboot_preboot(void); 65void nlm_rmiboot_preboot(void);
60void nlm_percpu_init(int hwcpuid); 66void nlm_percpu_init(int hwcpuid);
61 67
68static inline void *
69nlm_get_boot_data(int offset)
70{
71 return (void *)(CKSEG1ADDR(RESET_DATA_PHYS) + offset);
72}
73
62static inline void 74static inline void
63nlm_set_nmi_handler(void *handler) 75nlm_set_nmi_handler(void *handler)
64{ 76{
65 char *reset_data; 77 void *nmih = nlm_get_boot_data(BOOT_NMI_HANDLER);
66 78
67 reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS); 79 *(int64_t *)nmih = (long)handler;
68 *(int64_t *)(reset_data + BOOT_NMI_HANDLER) = (long)handler;
69} 80}
70 81
71/* 82/*
72 * Misc. 83 * Misc.
73 */ 84 */
85void nlm_init_boot_cpu(void);
74unsigned int nlm_get_cpu_frequency(void); 86unsigned int nlm_get_cpu_frequency(void);
75void nlm_node_init(int node); 87void nlm_node_init(int node);
76extern struct plat_smp_ops nlm_smp_ops; 88extern struct plat_smp_ops nlm_smp_ops;
77extern char nlm_reset_entry[], nlm_reset_entry_end[]; 89extern char nlm_reset_entry[], nlm_reset_entry_end[];
78 90
91/* SWIOTLB */
92extern struct dma_map_ops nlm_swiotlb_dma_ops;
93
79extern unsigned int nlm_threads_per_core; 94extern unsigned int nlm_threads_per_core;
80extern cpumask_t nlm_cpumask; 95extern cpumask_t nlm_cpumask;
81 96
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
index a981f4681a15..4b5108dfaa16 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -315,7 +315,7 @@ nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
315{ 315{
316 uint64_t ipi; 316 uint64_t ipi;
317 317
318 ipi = (nmi << 31) | (irq << 20); 318 ipi = ((uint64_t)nmi << 31) | (irq << 20);
319 ipi |= ((hwt >> 4) << 16) | (1 << (hwt & 0xf)); /* cpuset and mask */ 319 ipi |= ((hwt >> 4) << 16) | (1 << (hwt & 0xf)); /* cpuset and mask */
320 nlm_write_pic_reg(base, PIC_IPI_CTL, ipi); 320 nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
321} 321}
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
index 7e47209327a5..f4ea0f7f3965 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
@@ -59,6 +59,7 @@ void xlp_wakeup_secondary_cpus(void);
59 59
60void xlp_mmu_init(void); 60void xlp_mmu_init(void);
61void nlm_hal_init(void); 61void nlm_hal_init(void);
62void *xlp_dt_init(void *fdtp);
62 63
63#endif /* !__ASSEMBLY__ */ 64#endif /* !__ASSEMBLY__ */
64#endif /* _ASM_NLM_XLP_H */ 65#endif /* _ASM_NLM_XLP_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/fmn.h b/arch/mips/include/asm/netlogic/xlr/fmn.h
index 2a78929cef73..5604db3d1836 100644
--- a/arch/mips/include/asm/netlogic/xlr/fmn.h
+++ b/arch/mips/include/asm/netlogic/xlr/fmn.h
@@ -175,6 +175,10 @@
175#define nlm_write_c2_cc14(s, v) __write_32bit_c2_register($30, s, v) 175#define nlm_write_c2_cc14(s, v) __write_32bit_c2_register($30, s, v)
176#define nlm_write_c2_cc15(s, v) __write_32bit_c2_register($31, s, v) 176#define nlm_write_c2_cc15(s, v) __write_32bit_c2_register($31, s, v)
177 177
178#define nlm_read_c2_status0() __read_32bit_c2_register($2, 0)
179#define nlm_write_c2_status0(v) __write_32bit_c2_register($2, 0, v)
180#define nlm_read_c2_status1() __read_32bit_c2_register($2, 1)
181#define nlm_write_c2_status1(v) __write_32bit_c2_register($2, 1, v)
178#define nlm_read_c2_status(sel) __read_32bit_c2_register($2, 0) 182#define nlm_read_c2_status(sel) __read_32bit_c2_register($2, 0)
179#define nlm_read_c2_config() __read_32bit_c2_register($3, 0) 183#define nlm_read_c2_config() __read_32bit_c2_register($3, 0)
180#define nlm_write_c2_config(v) __write_32bit_c2_register($3, 0, v) 184#define nlm_write_c2_config(v) __write_32bit_c2_register($3, 0, v)
@@ -237,7 +241,7 @@ static inline void nlm_msgwait(unsigned int mask)
237/* 241/*
238 * Disable interrupts and enable COP2 access 242 * Disable interrupts and enable COP2 access
239 */ 243 */
240static inline uint32_t nlm_cop2_enable(void) 244static inline uint32_t nlm_cop2_enable_irqsave(void)
241{ 245{
242 uint32_t sr = read_c0_status(); 246 uint32_t sr = read_c0_status();
243 247
@@ -245,7 +249,7 @@ static inline uint32_t nlm_cop2_enable(void)
245 return sr; 249 return sr;
246} 250}
247 251
248static inline void nlm_cop2_restore(uint32_t sr) 252static inline void nlm_cop2_disable_irqrestore(uint32_t sr)
249{ 253{
250 write_c0_status(sr); 254 write_c0_status(sr);
251} 255}
@@ -296,7 +300,7 @@ static inline int nlm_fmn_send(unsigned int size, unsigned int code,
296 */ 300 */
297 for (i = 0; i < 8; i++) { 301 for (i = 0; i < 8; i++) {
298 nlm_msgsnd(dest); 302 nlm_msgsnd(dest);
299 status = nlm_read_c2_status(0); 303 status = nlm_read_c2_status0();
300 if ((status & 0x2) == 1) 304 if ((status & 0x2) == 1)
301 pr_info("Send pending fail!\n"); 305 pr_info("Send pending fail!\n");
302 if ((status & 0x4) == 0) 306 if ((status & 0x4) == 0)
@@ -316,7 +320,7 @@ static inline int nlm_fmn_receive(int bucket, int *size, int *code, int *stid,
316 320
317 /* wait for load pending to clear */ 321 /* wait for load pending to clear */
318 do { 322 do {
319 status = nlm_read_c2_status(1); 323 status = nlm_read_c2_status0();
320 } while ((status & 0x08) != 0); 324 } while ((status & 0x08) != 0);
321 325
322 /* receive error bits */ 326 /* receive error bits */
diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
index 284fa8d773ba..7b7818d1e4d5 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -227,6 +227,7 @@ enum cvmx_board_types_enum {
227 * use any numbers in this range. 227 * use any numbers in this range.
228 */ 228 */
229 CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001, 229 CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001,
230 CVMX_BOARD_TYPE_UBNT_E100 = 20002,
230 CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000, 231 CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000,
231 232
232 /* The remaining range is reserved for future use. */ 233 /* The remaining range is reserved for future use. */
@@ -325,6 +326,7 @@ static inline const char *cvmx_board_type_to_string(enum
325 326
326 /* Customer private range */ 327 /* Customer private range */
327 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN) 328 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN)
329 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100)
328 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX) 330 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX)
329 } 331 }
330 return "Unsupported Board"; 332 return "Unsupported Board";
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index f59552fae917..f6be4741f7e8 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -205,10 +205,8 @@ extern int __virt_addr_valid(const volatile void *kaddr);
205#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ 205#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
206 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) 206 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
207 207
208#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE + \ 208#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE)
209 PHYS_OFFSET) 209#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET)
210#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET - \
211 PHYS_OFFSET)
212 210
213#include <asm-generic/memory_model.h> 211#include <asm-generic/memory_model.h>
214#include <asm-generic/getorder.h> 212#include <asm-generic/getorder.h>
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index b8e24fd4cbc5..fa8e0aa250ca 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -52,7 +52,6 @@ struct pci_controller {
52/* 52/*
53 * Used by boards to register their PCI busses before the actual scanning. 53 * Used by boards to register their PCI busses before the actual scanning.
54 */ 54 */
55extern struct pci_controller * alloc_pci_controller(void);
56extern void register_pci_controller(struct pci_controller *hose); 55extern void register_pci_controller(struct pci_controller *hose);
57 56
58/* 57/*
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index 1470b7b68b0e..3605b844ad87 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -137,7 +137,7 @@ union mips_watch_reg_state {
137 struct mips3264_watch_reg_state mips3264; 137 struct mips3264_watch_reg_state mips3264;
138}; 138};
139 139
140#ifdef CONFIG_CPU_CAVIUM_OCTEON 140#if defined(CONFIG_CPU_CAVIUM_OCTEON)
141 141
142struct octeon_cop2_state { 142struct octeon_cop2_state {
143 /* DMFC2 rt, 0x0201 */ 143 /* DMFC2 rt, 0x0201 */
@@ -182,13 +182,26 @@ struct octeon_cop2_state {
182 /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */ 182 /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
183 unsigned long cop2_gfm_result[2]; 183 unsigned long cop2_gfm_result[2];
184}; 184};
185#define INIT_OCTEON_COP2 {0,} 185#define COP2_INIT \
186 .cp2 = {0,},
186 187
187struct octeon_cvmseg_state { 188struct octeon_cvmseg_state {
188 unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE] 189 unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
189 [cpu_dcache_line_size() / sizeof(unsigned long)]; 190 [cpu_dcache_line_size() / sizeof(unsigned long)];
190}; 191};
191 192
193#elif defined(CONFIG_CPU_XLP)
194struct nlm_cop2_state {
195 u64 rx[4];
196 u64 tx[4];
197 u32 tx_msg_status;
198 u32 rx_msg_status;
199};
200
201#define COP2_INIT \
202 .cp2 = {{0}, {0}, 0, 0},
203#else
204#define COP2_INIT
192#endif 205#endif
193 206
194typedef struct { 207typedef struct {
@@ -231,8 +244,11 @@ struct thread_struct {
231 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ 244 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
232 unsigned long error_code; 245 unsigned long error_code;
233#ifdef CONFIG_CPU_CAVIUM_OCTEON 246#ifdef CONFIG_CPU_CAVIUM_OCTEON
234 struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128))); 247 struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
235 struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128))); 248 struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
249#endif
250#ifdef CONFIG_CPU_XLP
251 struct nlm_cop2_state cp2;
236#endif 252#endif
237 struct mips_abi *abi; 253 struct mips_abi *abi;
238}; 254};
@@ -245,13 +261,6 @@ struct thread_struct {
245#define FPAFF_INIT 261#define FPAFF_INIT
246#endif /* CONFIG_MIPS_MT_FPAFF */ 262#endif /* CONFIG_MIPS_MT_FPAFF */
247 263
248#ifdef CONFIG_CPU_CAVIUM_OCTEON
249#define OCTEON_INIT \
250 .cp2 = INIT_OCTEON_COP2,
251#else
252#define OCTEON_INIT
253#endif /* CONFIG_CPU_CAVIUM_OCTEON */
254
255#define INIT_THREAD { \ 264#define INIT_THREAD { \
256 /* \ 265 /* \
257 * Saved main processor registers \ 266 * Saved main processor registers \
@@ -300,9 +309,9 @@ struct thread_struct {
300 .cp0_baduaddr = 0, \ 309 .cp0_baduaddr = 0, \
301 .error_code = 0, \ 310 .error_code = 0, \
302 /* \ 311 /* \
303 * Cavium Octeon specifics (null if not Octeon) \ 312 * Platform specific cop2 registers(null if no COP2) \
304 */ \ 313 */ \
305 OCTEON_INIT \ 314 COP2_INIT \
306} 315}
307 316
308struct task_struct; 317struct task_struct;
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index a89d1b10d027..23fc95e65673 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -70,6 +70,14 @@
70#ifndef CONFIG_CPU_HAS_SMARTMIPS 70#ifndef CONFIG_CPU_HAS_SMARTMIPS
71 LONG_S v1, PT_LO(sp) 71 LONG_S v1, PT_LO(sp)
72#endif 72#endif
73#ifdef CONFIG_CPU_CAVIUM_OCTEON
74 /*
75 * The Octeon multiplier state is affected by general
76 * multiply instructions. It must be saved before and
77 * kernel code might corrupt it
78 */
79 jal octeon_mult_save
80#endif
73 .endm 81 .endm
74 82
75 .macro SAVE_STATIC 83 .macro SAVE_STATIC
@@ -218,17 +226,8 @@
218 ori $28, sp, _THREAD_MASK 226 ori $28, sp, _THREAD_MASK
219 xori $28, _THREAD_MASK 227 xori $28, _THREAD_MASK
220#ifdef CONFIG_CPU_CAVIUM_OCTEON 228#ifdef CONFIG_CPU_CAVIUM_OCTEON
221 .set mips64 229 .set mips64
222 pref 0, 0($28) /* Prefetch the current pointer */ 230 pref 0, 0($28) /* Prefetch the current pointer */
223 pref 0, PT_R31(sp) /* Prefetch the $31(ra) */
224 /* The Octeon multiplier state is affected by general multiply
225 instructions. It must be saved before and kernel code might
226 corrupt it */
227 jal octeon_mult_save
228 LONG_L v1, 0($28) /* Load the current pointer */
229 /* Restore $31(ra) that was changed by the jal */
230 LONG_L ra, PT_R31(sp)
231 pref 0, 0(v1) /* Prefetch the current thread */
232#endif 231#endif
233 .set pop 232 .set pop
234 .endm 233 .endm
@@ -248,6 +247,10 @@
248 .endm 247 .endm
249 248
250 .macro RESTORE_TEMP 249 .macro RESTORE_TEMP
250#ifdef CONFIG_CPU_CAVIUM_OCTEON
251 /* Restore the Octeon multiplier state */
252 jal octeon_mult_restore
253#endif
251#ifdef CONFIG_CPU_HAS_SMARTMIPS 254#ifdef CONFIG_CPU_HAS_SMARTMIPS
252 LONG_L $24, PT_ACX(sp) 255 LONG_L $24, PT_ACX(sp)
253 mtlhx $24 256 mtlhx $24
@@ -360,10 +363,6 @@
360 DVPE 5 # dvpe a1 363 DVPE 5 # dvpe a1
361 jal mips_ihb 364 jal mips_ihb
362#endif /* CONFIG_MIPS_MT_SMTC */ 365#endif /* CONFIG_MIPS_MT_SMTC */
363#ifdef CONFIG_CPU_CAVIUM_OCTEON
364 /* Restore the Octeon multiplier state */
365 jal octeon_mult_restore
366#endif
367 mfc0 a0, CP0_STATUS 366 mfc0 a0, CP0_STATUS
368 ori a0, STATMASK 367 ori a0, STATMASK
369 xori a0, STATMASK 368 xori a0, STATMASK
diff --git a/arch/mips/include/asm/stackprotector.h b/arch/mips/include/asm/stackprotector.h
new file mode 100644
index 000000000000..eb9b1035e926
--- /dev/null
+++ b/arch/mips/include/asm/stackprotector.h
@@ -0,0 +1,40 @@
1/*
2 * GCC stack protector support.
3 *
4 * (This is directly adopted from the ARM implementation)
5 *
6 * Stack protector works by putting predefined pattern at the start of
7 * the stack frame and verifying that it hasn't been overwritten when
8 * returning from the function. The pattern is called stack canary
9 * and gcc expects it to be defined by a global variable called
10 * "__stack_chk_guard" on MIPS. This unfortunately means that on SMP
11 * we cannot have a different canary value per task.
12 */
13
14#ifndef _ASM_STACKPROTECTOR_H
15#define _ASM_STACKPROTECTOR_H 1
16
17#include <linux/random.h>
18#include <linux/version.h>
19
20extern unsigned long __stack_chk_guard;
21
22/*
23 * Initialize the stackprotector canary value.
24 *
25 * NOTE: this must only be called from functions that never return,
26 * and it must always be inlined.
27 */
28static __always_inline void boot_init_stack_canary(void)
29{
30 unsigned long canary;
31
32 /* Try to get a semi random initial value. */
33 get_random_bytes(&canary, sizeof(canary));
34 canary ^= LINUX_VERSION_CODE;
35
36 current->stack_canary = canary;
37 __stack_chk_guard = current->stack_canary;
38}
39
40#endif /* _ASM_STACKPROTECTOR_H */
diff --git a/arch/mips/include/asm/switch_to.h b/arch/mips/include/asm/switch_to.h
index fd16bcb6c311..eb0af15ac656 100644
--- a/arch/mips/include/asm/switch_to.h
+++ b/arch/mips/include/asm/switch_to.h
@@ -15,6 +15,7 @@
15#include <asm/cpu-features.h> 15#include <asm/cpu-features.h>
16#include <asm/watch.h> 16#include <asm/watch.h>
17#include <asm/dsp.h> 17#include <asm/dsp.h>
18#include <asm/cop2.h>
18 19
19struct task_struct; 20struct task_struct;
20 21
@@ -66,10 +67,18 @@ do { \
66 67
67#define switch_to(prev, next, last) \ 68#define switch_to(prev, next, last) \
68do { \ 69do { \
69 u32 __usedfpu; \ 70 u32 __usedfpu, __c0_stat; \
70 __mips_mt_fpaff_switch_to(prev); \ 71 __mips_mt_fpaff_switch_to(prev); \
71 if (cpu_has_dsp) \ 72 if (cpu_has_dsp) \
72 __save_dsp(prev); \ 73 __save_dsp(prev); \
74 if (cop2_present && (KSTK_STATUS(prev) & ST0_CU2)) { \
75 if (cop2_lazy_restore) \
76 KSTK_STATUS(prev) &= ~ST0_CU2; \
77 __c0_stat = read_c0_status(); \
78 write_c0_status(__c0_stat | ST0_CU2); \
79 cop2_save(&prev->thread.cp2); \
80 write_c0_status(__c0_stat & ~ST0_CU2); \
81 } \
73 __clear_software_ll_bit(); \ 82 __clear_software_ll_bit(); \
74 __usedfpu = test_and_clear_tsk_thread_flag(prev, TIF_USEDFPU); \ 83 __usedfpu = test_and_clear_tsk_thread_flag(prev, TIF_USEDFPU); \
75 (last) = resume(prev, next, task_thread_info(next), __usedfpu); \ 84 (last) = resume(prev, next, task_thread_info(next), __usedfpu); \
@@ -77,6 +86,14 @@ do { \
77 86
78#define finish_arch_switch(prev) \ 87#define finish_arch_switch(prev) \
79do { \ 88do { \
89 u32 __c0_stat; \
90 if (cop2_present && !cop2_lazy_restore && \
91 (KSTK_STATUS(current) & ST0_CU2)) { \
92 __c0_stat = read_c0_status(); \
93 write_c0_status(__c0_stat | ST0_CU2); \
94 cop2_restore(&current->thread.cp2); \
95 write_c0_status(__c0_stat & ~ST0_CU2); \
96 } \
80 if (cpu_has_dsp) \ 97 if (cpu_has_dsp) \
81 __restore_dsp(current); \ 98 __restore_dsp(current); \
82 if (cpu_has_userlocal) \ 99 if (cpu_has_userlocal) \
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 895320e25662..61215a34acc6 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -109,6 +109,7 @@ static inline struct thread_info *current_thread_info(void)
109#define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */ 109#define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */
110#define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */ 110#define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */
111#define TIF_MEMDIE 18 /* is terminating due to OOM killer */ 111#define TIF_MEMDIE 18 /* is terminating due to OOM killer */
112#define TIF_NOHZ 19 /* in adaptive nohz mode */
112#define TIF_FIXADE 20 /* Fix address errors in software */ 113#define TIF_FIXADE 20 /* Fix address errors in software */
113#define TIF_LOGADE 21 /* Log address errors to syslog */ 114#define TIF_LOGADE 21 /* Log address errors to syslog */
114#define TIF_32BIT_REGS 22 /* also implies 16/32 fprs */ 115#define TIF_32BIT_REGS 22 /* also implies 16/32 fprs */
@@ -124,6 +125,7 @@ static inline struct thread_info *current_thread_info(void)
124#define _TIF_SECCOMP (1<<TIF_SECCOMP) 125#define _TIF_SECCOMP (1<<TIF_SECCOMP)
125#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) 126#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
126#define _TIF_USEDFPU (1<<TIF_USEDFPU) 127#define _TIF_USEDFPU (1<<TIF_USEDFPU)
128#define _TIF_NOHZ (1<<TIF_NOHZ)
127#define _TIF_FIXADE (1<<TIF_FIXADE) 129#define _TIF_FIXADE (1<<TIF_FIXADE)
128#define _TIF_LOGADE (1<<TIF_LOGADE) 130#define _TIF_LOGADE (1<<TIF_LOGADE)
129#define _TIF_32BIT_REGS (1<<TIF_32BIT_REGS) 131#define _TIF_32BIT_REGS (1<<TIF_32BIT_REGS)
@@ -131,14 +133,19 @@ static inline struct thread_info *current_thread_info(void)
131#define _TIF_FPUBOUND (1<<TIF_FPUBOUND) 133#define _TIF_FPUBOUND (1<<TIF_FPUBOUND)
132#define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH) 134#define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH)
133 135
136#define _TIF_WORK_SYSCALL_ENTRY (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \
137 _TIF_SYSCALL_AUDIT)
138
134/* work to do in syscall_trace_leave() */ 139/* work to do in syscall_trace_leave() */
135#define _TIF_WORK_SYSCALL_EXIT (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT) 140#define _TIF_WORK_SYSCALL_EXIT (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \
141 _TIF_SYSCALL_AUDIT)
136 142
137/* work to do on interrupt/exception return */ 143/* work to do on interrupt/exception return */
138#define _TIF_WORK_MASK \ 144#define _TIF_WORK_MASK \
139 (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME) 145 (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME)
140/* work to do on any return to u-space */ 146/* work to do on any return to u-space */
141#define _TIF_ALLWORK_MASK (_TIF_WORK_MASK | _TIF_WORK_SYSCALL_EXIT) 147#define _TIF_ALLWORK_MASK (_TIF_NOHZ | _TIF_WORK_MASK | \
148 _TIF_WORK_SYSCALL_EXIT)
142 149
143#endif /* __KERNEL__ */ 150#endif /* __KERNEL__ */
144 151
diff --git a/arch/mips/include/asm/xtalk/xtalk.h b/arch/mips/include/asm/xtalk/xtalk.h
index 680e7efebbaf..26d2ed1fa917 100644
--- a/arch/mips/include/asm/xtalk/xtalk.h
+++ b/arch/mips/include/asm/xtalk/xtalk.h
@@ -47,6 +47,15 @@ typedef struct xtalk_piomap_s *xtalk_piomap_t;
47#define XIO_PORT(x) ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT)) 47#define XIO_PORT(x) ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT))
48#define XIO_PACK(p, o) ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS)) 48#define XIO_PACK(p, o) ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS))
49 49
50#ifdef CONFIG_PCI
51extern int bridge_probe(nasid_t nasid, int widget, int masterwid);
52#else
53static inline int bridge_probe(nasid_t nasid, int widget, int masterwid)
54{
55 return 0;
56}
57#endif
58
50#endif /* !__ASSEMBLY__ */ 59#endif /* !__ASSEMBLY__ */
51 60
52#endif /* _ASM_XTALK_XTALK_H */ 61#endif /* _ASM_XTALK_XTALK_H */
diff --git a/arch/mips/include/uapi/asm/fcntl.h b/arch/mips/include/uapi/asm/fcntl.h
index 0bda78f70e1e..6ca432f00860 100644
--- a/arch/mips/include/uapi/asm/fcntl.h
+++ b/arch/mips/include/uapi/asm/fcntl.h
@@ -5,9 +5,10 @@
5 * 5 *
6 * Copyright (C) 1995, 96, 97, 98, 99, 2003, 05 Ralf Baechle 6 * Copyright (C) 1995, 96, 97, 98, 99, 2003, 05 Ralf Baechle
7 */ 7 */
8#ifndef _ASM_FCNTL_H 8#ifndef _UAPI_ASM_FCNTL_H
9#define _ASM_FCNTL_H 9#define _UAPI_ASM_FCNTL_H
10 10
11#include <asm/sgidefs.h>
11 12
12#define O_APPEND 0x0008 13#define O_APPEND 0x0008
13#define O_DSYNC 0x0010 /* used to be O_SYNC, see below */ 14#define O_DSYNC 0x0010 /* used to be O_SYNC, see below */
@@ -55,14 +56,15 @@
55 * contain all the same fields as struct flock. 56 * contain all the same fields as struct flock.
56 */ 57 */
57 58
58#ifdef CONFIG_32BIT 59#if _MIPS_SIM != _MIPS_SIM_ABI64
60
59#include <linux/types.h> 61#include <linux/types.h>
60 62
61struct flock { 63struct flock {
62 short l_type; 64 short l_type;
63 short l_whence; 65 short l_whence;
64 off_t l_start; 66 __kernel_off_t l_start;
65 off_t l_len; 67 __kernel_off_t l_len;
66 long l_sysid; 68 long l_sysid;
67 __kernel_pid_t l_pid; 69 __kernel_pid_t l_pid;
68 long pad[4]; 70 long pad[4];
@@ -70,8 +72,8 @@ struct flock {
70 72
71#define HAVE_ARCH_STRUCT_FLOCK 73#define HAVE_ARCH_STRUCT_FLOCK
72 74
73#endif /* CONFIG_32BIT */ 75#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
74 76
75#include <asm-generic/fcntl.h> 77#include <asm-generic/fcntl.h>
76 78
77#endif /* _ASM_FCNTL_H */ 79#endif /* _UAPI_ASM_FCNTL_H */
diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index 0f4aec2ad1e6..e5a676e3d3c0 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -409,10 +409,11 @@ enum mm_32f_73_minor_op {
409enum mm_16c_minor_op { 409enum mm_16c_minor_op {
410 mm_lwm16_op = 0x04, 410 mm_lwm16_op = 0x04,
411 mm_swm16_op = 0x05, 411 mm_swm16_op = 0x05,
412 mm_jr16_op = 0x18, 412 mm_jr16_op = 0x0c,
413 mm_jrc_op = 0x1a, 413 mm_jrc_op = 0x0d,
414 mm_jalr16_op = 0x1c, 414 mm_jalr16_op = 0x0e,
415 mm_jalrs16_op = 0x1e, 415 mm_jalrs16_op = 0x0f,
416 mm_jraddiusp_op = 0x18,
416}; 417};
417 418
418/* 419/*
diff --git a/arch/mips/include/uapi/asm/msgbuf.h b/arch/mips/include/uapi/asm/msgbuf.h
index 0d6c7f14de31..df849e87d9ae 100644
--- a/arch/mips/include/uapi/asm/msgbuf.h
+++ b/arch/mips/include/uapi/asm/msgbuf.h
@@ -14,25 +14,25 @@
14 14
15struct msqid64_ds { 15struct msqid64_ds {
16 struct ipc64_perm msg_perm; 16 struct ipc64_perm msg_perm;
17#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN) 17#if !defined(__mips64) && defined(__MIPSEB__)
18 unsigned long __unused1; 18 unsigned long __unused1;
19#endif 19#endif
20 __kernel_time_t msg_stime; /* last msgsnd time */ 20 __kernel_time_t msg_stime; /* last msgsnd time */
21#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN) 21#if !defined(__mips64) && defined(__MIPSEL__)
22 unsigned long __unused1; 22 unsigned long __unused1;
23#endif 23#endif
24#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN) 24#if !defined(__mips64) && defined(__MIPSEB__)
25 unsigned long __unused2; 25 unsigned long __unused2;
26#endif 26#endif
27 __kernel_time_t msg_rtime; /* last msgrcv time */ 27 __kernel_time_t msg_rtime; /* last msgrcv time */
28#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN) 28#if !defined(__mips64) && defined(__MIPSEL__)
29 unsigned long __unused2; 29 unsigned long __unused2;
30#endif 30#endif
31#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN) 31#if !defined(__mips64) && defined(__MIPSEB__)
32 unsigned long __unused3; 32 unsigned long __unused3;
33#endif 33#endif
34 __kernel_time_t msg_ctime; /* last change time */ 34 __kernel_time_t msg_ctime; /* last change time */
35#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN) 35#if !defined(__mips64) && defined(__MIPSEL__)
36 unsigned long __unused3; 36 unsigned long __unused3;
37#endif 37#endif
38 unsigned long msg_cbytes; /* current number of bytes on queue */ 38 unsigned long msg_cbytes; /* current number of bytes on queue */
diff --git a/arch/mips/include/uapi/asm/resource.h b/arch/mips/include/uapi/asm/resource.h
index 87cb3085269c..b26439d4ab0b 100644
--- a/arch/mips/include/uapi/asm/resource.h
+++ b/arch/mips/include/uapi/asm/resource.h
@@ -26,7 +26,7 @@
26 * but we keep the old value on MIPS32, 26 * but we keep the old value on MIPS32,
27 * for compatibility: 27 * for compatibility:
28 */ 28 */
29#ifdef CONFIG_32BIT 29#ifndef __mips64
30# define RLIM_INFINITY 0x7fffffffUL 30# define RLIM_INFINITY 0x7fffffffUL
31#endif 31#endif
32 32
diff --git a/arch/mips/include/uapi/asm/siginfo.h b/arch/mips/include/uapi/asm/siginfo.h
index 6a8714193fb9..b7a23064841f 100644
--- a/arch/mips/include/uapi/asm/siginfo.h
+++ b/arch/mips/include/uapi/asm/siginfo.h
@@ -25,10 +25,10 @@ struct siginfo;
25/* 25/*
26 * Careful to keep union _sifields from shifting ... 26 * Careful to keep union _sifields from shifting ...
27 */ 27 */
28#ifdef CONFIG_32BIT 28#if __SIZEOF_LONG__ == 4
29#define __ARCH_SI_PREAMBLE_SIZE (3 * sizeof(int)) 29#define __ARCH_SI_PREAMBLE_SIZE (3 * sizeof(int))
30#endif 30#endif
31#ifdef CONFIG_64BIT 31#if __SIZEOF_LONG__ == 8
32#define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int)) 32#define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
33#endif 33#endif
34 34
diff --git a/arch/mips/include/uapi/asm/swab.h b/arch/mips/include/uapi/asm/swab.h
index 97c2f81b4b43..ac9a8f9cd1fb 100644
--- a/arch/mips/include/uapi/asm/swab.h
+++ b/arch/mips/include/uapi/asm/swab.h
@@ -13,7 +13,7 @@
13 13
14#define __SWAB_64_THRU_32__ 14#define __SWAB_64_THRU_32__
15 15
16#ifdef CONFIG_CPU_MIPSR2 16#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
17 17
18static inline __attribute_const__ __u16 __arch_swab16(__u16 x) 18static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
19{ 19{
@@ -39,10 +39,10 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
39#define __arch_swab32 __arch_swab32 39#define __arch_swab32 __arch_swab32
40 40
41/* 41/*
42 * Having already checked for CONFIG_CPU_MIPSR2, enable the 42 * Having already checked for MIPS R2, enable the optimized version for
43 * optimized version for 64-bit kernel on r2 CPUs. 43 * 64-bit kernel on r2 CPUs.
44 */ 44 */
45#ifdef CONFIG_64BIT 45#ifdef __mips64
46static inline __attribute_const__ __u64 __arch_swab64(__u64 x) 46static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
47{ 47{
48 __asm__( 48 __asm__(
@@ -54,6 +54,6 @@ static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
54 return x; 54 return x;
55} 55}
56#define __arch_swab64 __arch_swab64 56#define __arch_swab64 __arch_swab64
57#endif /* CONFIG_64BIT */ 57#endif /* __mips64 */
58#endif /* CONFIG_CPU_MIPSR2 */ 58#endif /* MIPS R2 or newer */
59#endif /* _ASM_SWAB_H */ 59#endif /* _ASM_SWAB_H */
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index 0845091ba480..0c2e853c3db4 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -82,6 +82,9 @@ void output_task_defines(void)
82 OFFSET(TASK_FLAGS, task_struct, flags); 82 OFFSET(TASK_FLAGS, task_struct, flags);
83 OFFSET(TASK_MM, task_struct, mm); 83 OFFSET(TASK_MM, task_struct, mm);
84 OFFSET(TASK_PID, task_struct, pid); 84 OFFSET(TASK_PID, task_struct, pid);
85#if defined(CONFIG_CC_STACKPROTECTOR)
86 OFFSET(TASK_STACK_CANARY, task_struct, stack_canary);
87#endif
85 DEFINE(TASK_STRUCT_SIZE, sizeof(struct task_struct)); 88 DEFINE(TASK_STRUCT_SIZE, sizeof(struct task_struct));
86 BLANK(); 89 BLANK();
87} 90}
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 46c2ad0703a0..4d78bf445a9c 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -467,5 +467,4 @@ unaligned:
467 printk("%s: unaligned epc - sending SIGBUS.\n", current->comm); 467 printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
468 force_sig(SIGBUS, current); 468 force_sig(SIGBUS, current);
469 return -EFAULT; 469 return -EFAULT;
470
471} 470}
diff --git a/arch/mips/kernel/cpu-bugs64.c b/arch/mips/kernel/cpu-bugs64.c
index de3c25ffd9f9..0c61df281ce6 100644
--- a/arch/mips/kernel/cpu-bugs64.c
+++ b/arch/mips/kernel/cpu-bugs64.c
@@ -6,6 +6,7 @@
6 * as published by the Free Software Foundation; either version 6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version. 7 * 2 of the License, or (at your option) any later version.
8 */ 8 */
9#include <linux/context_tracking.h>
9#include <linux/init.h> 10#include <linux/init.h>
10#include <linux/kernel.h> 11#include <linux/kernel.h>
11#include <linux/ptrace.h> 12#include <linux/ptrace.h>
@@ -171,8 +172,12 @@ static volatile int daddi_ov __cpuinitdata;
171 172
172asmlinkage void __init do_daddi_ov(struct pt_regs *regs) 173asmlinkage void __init do_daddi_ov(struct pt_regs *regs)
173{ 174{
175 enum ctx_state prev_state;
176
177 prev_state = exception_enter();
174 daddi_ov = 1; 178 daddi_ov = 1;
175 regs->cp0_epc += 4; 179 regs->cp0_epc += 4;
180 exception_exit(prev_state);
176} 181}
177 182
178static inline void check_daddi(void) 183static inline void check_daddi(void)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index c6568bf4b1b0..c7b1b3c5a761 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -146,8 +146,7 @@ static void __cpuinit set_isa(struct cpuinfo_mips *c, unsigned int isa)
146 case MIPS_CPU_ISA_IV: 146 case MIPS_CPU_ISA_IV:
147 c->isa_level |= MIPS_CPU_ISA_IV; 147 c->isa_level |= MIPS_CPU_ISA_IV;
148 case MIPS_CPU_ISA_III: 148 case MIPS_CPU_ISA_III:
149 c->isa_level |= MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | 149 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
150 MIPS_CPU_ISA_III;
151 break; 150 break;
152 151
153 case MIPS_CPU_ISA_M32R2: 152 case MIPS_CPU_ISA_M32R2:
@@ -156,8 +155,6 @@ static void __cpuinit set_isa(struct cpuinfo_mips *c, unsigned int isa)
156 c->isa_level |= MIPS_CPU_ISA_M32R1; 155 c->isa_level |= MIPS_CPU_ISA_M32R1;
157 case MIPS_CPU_ISA_II: 156 case MIPS_CPU_ISA_II:
158 c->isa_level |= MIPS_CPU_ISA_II; 157 c->isa_level |= MIPS_CPU_ISA_II;
159 case MIPS_CPU_ISA_I:
160 c->isa_level |= MIPS_CPU_ISA_I;
161 break; 158 break;
162 } 159 }
163} 160}
@@ -272,9 +269,6 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
272 c->options |= MIPS_CPU_ULRI; 269 c->options |= MIPS_CPU_ULRI;
273 if (config3 & MIPS_CONF3_ISA) 270 if (config3 & MIPS_CONF3_ISA)
274 c->options |= MIPS_CPU_MICROMIPS; 271 c->options |= MIPS_CPU_MICROMIPS;
275#ifdef CONFIG_CPU_MICROMIPS
276 write_c0_config3(read_c0_config3() | MIPS_CONF3_ISA_OE);
277#endif
278 if (config3 & MIPS_CONF3_VZ) 272 if (config3 & MIPS_CONF3_VZ)
279 c->ases |= MIPS_ASE_VZ; 273 c->ases |= MIPS_ASE_VZ;
280 274
@@ -332,7 +326,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
332 case PRID_IMP_R2000: 326 case PRID_IMP_R2000:
333 c->cputype = CPU_R2000; 327 c->cputype = CPU_R2000;
334 __cpu_name[cpu] = "R2000"; 328 __cpu_name[cpu] = "R2000";
335 set_isa(c, MIPS_CPU_ISA_I);
336 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 329 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
337 MIPS_CPU_NOFPUEX; 330 MIPS_CPU_NOFPUEX;
338 if (__cpu_has_fpu()) 331 if (__cpu_has_fpu())
@@ -352,7 +345,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
352 c->cputype = CPU_R3000; 345 c->cputype = CPU_R3000;
353 __cpu_name[cpu] = "R3000"; 346 __cpu_name[cpu] = "R3000";
354 } 347 }
355 set_isa(c, MIPS_CPU_ISA_I);
356 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 348 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
357 MIPS_CPU_NOFPUEX; 349 MIPS_CPU_NOFPUEX;
358 if (__cpu_has_fpu()) 350 if (__cpu_has_fpu())
@@ -455,7 +447,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
455 break; 447 break;
456 #endif 448 #endif
457 case PRID_IMP_TX39: 449 case PRID_IMP_TX39:
458 set_isa(c, MIPS_CPU_ISA_I);
459 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 450 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
460 451
461 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 452 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
@@ -959,6 +950,7 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
959 set_isa(c, MIPS_CPU_ISA_M64R1); 950 set_isa(c, MIPS_CPU_ISA_M64R1);
960 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; 951 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
961 } 952 }
953 c->kscratch_mask = 0xf;
962} 954}
963 955
964#ifdef CONFIG_64BIT 956#ifdef CONFIG_64BIT
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index c61cdaed2b1d..099912324423 100644
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -28,45 +28,6 @@
28#include <kernel-entry-init.h> 28#include <kernel-entry-init.h>
29 29
30 /* 30 /*
31 * inputs are the text nasid in t1, data nasid in t2.
32 */
33 .macro MAPPED_KERNEL_SETUP_TLB
34#ifdef CONFIG_MAPPED_KERNEL
35 /*
36 * This needs to read the nasid - assume 0 for now.
37 * Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0,
38 * 0+DVG in tlblo_1.
39 */
40 dli t0, 0xffffffffc0000000
41 dmtc0 t0, CP0_ENTRYHI
42 li t0, 0x1c000 # Offset of text into node memory
43 dsll t1, NASID_SHFT # Shift text nasid into place
44 dsll t2, NASID_SHFT # Same for data nasid
45 or t1, t1, t0 # Physical load address of kernel text
46 or t2, t2, t0 # Physical load address of kernel data
47 dsrl t1, 12 # 4K pfn
48 dsrl t2, 12 # 4K pfn
49 dsll t1, 6 # Get pfn into place
50 dsll t2, 6 # Get pfn into place
51 li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _CACHE_CACHABLE_COW) >> 6)
52 or t0, t0, t1
53 mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr
54 li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _PAGE_DIRTY|_CACHE_CACHABLE_COW) >> 6)
55 or t0, t0, t2
56 mtc0 t0, CP0_ENTRYLO1 # physaddr, DVG, cach exlwr
57 li t0, 0x1ffe000 # MAPPED_KERN_TLBMASK, TLBPGMASK_16M
58 mtc0 t0, CP0_PAGEMASK
59 li t0, 0 # KMAP_INX
60 mtc0 t0, CP0_INDEX
61 li t0, 1
62 mtc0 t0, CP0_WIRED
63 tlbwi
64#else
65 mtc0 zero, CP0_WIRED
66#endif
67 .endm
68
69 /*
70 * For the moment disable interrupts, mark the kernel mode and 31 * For the moment disable interrupts, mark the kernel mode and
71 * set ST0_KX so that the CPU does not spit fire when using 32 * set ST0_KX so that the CPU does not spit fire when using
72 * 64-bit addresses. A full initialization of the CPU's status 33 * 64-bit addresses. A full initialization of the CPU's status
diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c
index c01b307317a9..5b5ddb231f26 100644
--- a/arch/mips/kernel/irq-gic.c
+++ b/arch/mips/kernel/irq-gic.c
@@ -219,16 +219,15 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
219 219
220 /* Assumption : cpumask refers to a single CPU */ 220 /* Assumption : cpumask refers to a single CPU */
221 spin_lock_irqsave(&gic_lock, flags); 221 spin_lock_irqsave(&gic_lock, flags);
222 for (;;) {
223 /* Re-route this IRQ */
224 GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
225 222
226 /* Update the pcpu_masks */ 223 /* Re-route this IRQ */
227 for (i = 0; i < NR_CPUS; i++) 224 GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
228 clear_bit(irq, pcpu_masks[i].pcpu_mask); 225
229 set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask); 226 /* Update the pcpu_masks */
227 for (i = 0; i < NR_CPUS; i++)
228 clear_bit(irq, pcpu_masks[i].pcpu_mask);
229 set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);
230 230
231 }
232 cpumask_copy(d->affinity, cpumask); 231 cpumask_copy(d->affinity, cpumask);
233 spin_unlock_irqrestore(&gic_lock, flags); 232 spin_unlock_irqrestore(&gic_lock, flags);
234 233
diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S
index 33d067148e61..a03e93c4a946 100644
--- a/arch/mips/kernel/mcount.S
+++ b/arch/mips/kernel/mcount.S
@@ -168,15 +168,11 @@ NESTED(ftrace_graph_caller, PT_SIZE, ra)
168#endif 168#endif
169 169
170 /* arg3: Get frame pointer of current stack */ 170 /* arg3: Get frame pointer of current stack */
171#ifdef CONFIG_FRAME_POINTER
172 move a2, fp
173#else /* ! CONFIG_FRAME_POINTER */
174#ifdef CONFIG_64BIT 171#ifdef CONFIG_64BIT
175 PTR_LA a2, PT_SIZE(sp) 172 PTR_LA a2, PT_SIZE(sp)
176#else 173#else
177 PTR_LA a2, (PT_SIZE+8)(sp) 174 PTR_LA a2, (PT_SIZE+8)(sp)
178#endif 175#endif
179#endif
180 176
181 jal prepare_ftrace_return 177 jal prepare_ftrace_return
182 nop 178 nop
diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S
index 0e23343eb0a9..4204d76af854 100644
--- a/arch/mips/kernel/octeon_switch.S
+++ b/arch/mips/kernel/octeon_switch.S
@@ -40,33 +40,6 @@
40 cpu_save_nonscratch a0 40 cpu_save_nonscratch a0
41 LONG_S ra, THREAD_REG31(a0) 41 LONG_S ra, THREAD_REG31(a0)
42 42
43 /* check if we need to save COP2 registers */
44 PTR_L t2, TASK_THREAD_INFO(a0)
45 LONG_L t0, ST_OFF(t2)
46 bbit0 t0, 30, 1f
47
48 /* Disable COP2 in the stored process state */
49 li t1, ST0_CU2
50 xor t0, t1
51 LONG_S t0, ST_OFF(t2)
52
53 /* Enable COP2 so we can save it */
54 mfc0 t0, CP0_STATUS
55 or t0, t1
56 mtc0 t0, CP0_STATUS
57
58 /* Save COP2 */
59 daddu a0, THREAD_CP2
60 jal octeon_cop2_save
61 dsubu a0, THREAD_CP2
62
63 /* Disable COP2 now that we are done */
64 mfc0 t0, CP0_STATUS
65 li t1, ST0_CU2
66 xor t0, t1
67 mtc0 t0, CP0_STATUS
68
691:
70#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 43#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
71 /* Check if we need to store CVMSEG state */ 44 /* Check if we need to store CVMSEG state */
72 mfc0 t0, $11,7 /* CvmMemCtl */ 45 mfc0 t0, $11,7 /* CvmMemCtl */
@@ -98,6 +71,13 @@
98 mtc0 t0, $11,7 /* CvmMemCtl */ 71 mtc0 t0, $11,7 /* CvmMemCtl */
99#endif 72#endif
1003: 733:
74
75#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
76 PTR_L t8, __stack_chk_guard
77 LONG_L t9, TASK_STACK_CANARY(a1)
78 LONG_S t9, 0(t8)
79#endif
80
101 /* 81 /*
102 * The order of restoring the registers takes care of the race 82 * The order of restoring the registers takes care of the race
103 * updating $28, $29 and kernelsp without disabling ints. 83 * updating $28, $29 and kernelsp without disabling ints.
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index acb34373679e..8c58d8a84bf3 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -66,9 +66,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
66 seq_printf(m, "]\n"); 66 seq_printf(m, "]\n");
67 } 67 }
68 if (cpu_has_mips_r) { 68 if (cpu_has_mips_r) {
69 seq_printf(m, "isa\t\t\t:"); 69 seq_printf(m, "isa\t\t\t: mips1");
70 if (cpu_has_mips_1)
71 seq_printf(m, "%s", " mips1");
72 if (cpu_has_mips_2) 70 if (cpu_has_mips_2)
73 seq_printf(m, "%s", " mips2"); 71 seq_printf(m, "%s", " mips2");
74 if (cpu_has_mips_3) 72 if (cpu_has_mips_3)
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index c6a041d9d05d..ddc76103e78c 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -201,9 +201,12 @@ int dump_task_fpu(struct task_struct *t, elf_fpregset_t *fpr)
201 return 1; 201 return 1;
202} 202}
203 203
204/* 204#ifdef CONFIG_CC_STACKPROTECTOR
205 * 205#include <linux/stackprotector.h>
206 */ 206unsigned long __stack_chk_guard __read_mostly;
207EXPORT_SYMBOL(__stack_chk_guard);
208#endif
209
207struct mips_frame_info { 210struct mips_frame_info {
208 void *func; 211 void *func;
209 unsigned long func_size; 212 unsigned long func_size;
diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c
index 5712bb532245..7e954042f252 100644
--- a/arch/mips/kernel/prom.c
+++ b/arch/mips/kernel/prom.c
@@ -30,7 +30,7 @@ __init void mips_set_machine_name(const char *name)
30 if (name == NULL) 30 if (name == NULL)
31 return; 31 return;
32 32
33 strncpy(mips_machine_name, name, sizeof(mips_machine_name)); 33 strlcpy(mips_machine_name, name, sizeof(mips_machine_name));
34 pr_info("MIPS: machine is %s\n", mips_get_machine_name()); 34 pr_info("MIPS: machine is %s\n", mips_get_machine_name());
35} 35}
36 36
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index 9c6299c733a3..8ae1ebef8b71 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -15,6 +15,7 @@
15 * binaries. 15 * binaries.
16 */ 16 */
17#include <linux/compiler.h> 17#include <linux/compiler.h>
18#include <linux/context_tracking.h>
18#include <linux/kernel.h> 19#include <linux/kernel.h>
19#include <linux/sched.h> 20#include <linux/sched.h>
20#include <linux/mm.h> 21#include <linux/mm.h>
@@ -534,6 +535,8 @@ static inline int audit_arch(void)
534 */ 535 */
535asmlinkage void syscall_trace_enter(struct pt_regs *regs) 536asmlinkage void syscall_trace_enter(struct pt_regs *regs)
536{ 537{
538 user_exit();
539
537 /* do the secure computing check first */ 540 /* do the secure computing check first */
538 secure_computing_strict(regs->regs[2]); 541 secure_computing_strict(regs->regs[2]);
539 542
@@ -570,6 +573,13 @@ out:
570 */ 573 */
571asmlinkage void syscall_trace_leave(struct pt_regs *regs) 574asmlinkage void syscall_trace_leave(struct pt_regs *regs)
572{ 575{
576 /*
577 * We may come here right after calling schedule_user()
578 * or do_notify_resume(), in which case we can be in RCU
579 * user mode.
580 */
581 user_exit();
582
573 audit_syscall_exit(regs); 583 audit_syscall_exit(regs);
574 584
575 if (!(current->ptrace & PT_PTRACED)) 585 if (!(current->ptrace & PT_PTRACED))
@@ -592,4 +602,6 @@ asmlinkage void syscall_trace_leave(struct pt_regs *regs)
592 send_sig(current->exit_code, current, 1); 602 send_sig(current->exit_code, current, 1);
593 current->exit_code = 0; 603 current->exit_code = 0;
594 } 604 }
605
606 user_enter();
595} 607}
diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S
index 5266c6ee2b35..38af83f84c4a 100644
--- a/arch/mips/kernel/r2300_switch.S
+++ b/arch/mips/kernel/r2300_switch.S
@@ -65,6 +65,13 @@ LEAF(resume)
65 fpu_save_single a0, t0 # clobbers t0 65 fpu_save_single a0, t0 # clobbers t0
66 66
671: 671:
68
69#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
70 PTR_L t8, __stack_chk_guard
71 LONG_L t9, TASK_STACK_CANARY(a1)
72 LONG_S t9, 0(t8)
73#endif
74
68 /* 75 /*
69 * The order of restoring the registers takes care of the race 76 * The order of restoring the registers takes care of the race
70 * updating $28, $29 and kernelsp without disabling ints. 77 * updating $28, $29 and kernelsp without disabling ints.
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index 5e51219990aa..921238a6bd26 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -68,6 +68,12 @@
68 # clobbers t1 68 # clobbers t1
691: 691:
70 70
71#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
72 PTR_L t8, __stack_chk_guard
73 LONG_L t9, TASK_STACK_CANARY(a1)
74 LONG_S t9, 0(t8)
75#endif
76
71 /* 77 /*
72 * The order of restoring the registers takes care of the race 78 * The order of restoring the registers takes care of the race
73 * updating $28, $29 and kernelsp without disabling ints. 79 * updating $28, $29 and kernelsp without disabling ints.
diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c
index 6fa198db8999..d763f11e35e2 100644
--- a/arch/mips/kernel/rtlx.c
+++ b/arch/mips/kernel/rtlx.c
@@ -437,7 +437,6 @@ static ssize_t file_write(struct file *file, const char __user * buffer,
437 size_t count, loff_t * ppos) 437 size_t count, loff_t * ppos)
438{ 438{
439 int minor = iminor(file_inode(file)); 439 int minor = iminor(file_inode(file));
440 struct rtlx_channel *rt = &rtlx->channel[minor];
441 440
442 /* any space left... */ 441 /* any space left... */
443 if (!rtlx_write_poll(minor)) { 442 if (!rtlx_write_poll(minor)) {
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index e9127ec612ef..e774bb1088b5 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -52,7 +52,7 @@ NESTED(handle_sys, PT_SIZE, sp)
52 52
53stack_done: 53stack_done:
54 lw t0, TI_FLAGS($28) # syscall tracing enabled? 54 lw t0, TI_FLAGS($28) # syscall tracing enabled?
55 li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT 55 li t1, _TIF_WORK_SYSCALL_ENTRY
56 and t0, t1 56 and t0, t1
57 bnez t0, syscall_trace_entry # -> yes 57 bnez t0, syscall_trace_entry # -> yes
58 58
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index 97a5909a61cf..be6627ead619 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -54,7 +54,7 @@ NESTED(handle_sys64, PT_SIZE, sp)
54 54
55 sd a3, PT_R26(sp) # save a3 for syscall restarting 55 sd a3, PT_R26(sp) # save a3 for syscall restarting
56 56
57 li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT 57 li t1, _TIF_WORK_SYSCALL_ENTRY
58 LONG_L t0, TI_FLAGS($28) # syscall tracing enabled? 58 LONG_L t0, TI_FLAGS($28) # syscall tracing enabled?
59 and t0, t1, t0 59 and t0, t1, t0
60 bnez t0, syscall_trace_entry 60 bnez t0, syscall_trace_entry
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index edcb6594e7b5..cab150789c8d 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -47,7 +47,7 @@ NESTED(handle_sysn32, PT_SIZE, sp)
47 47
48 sd a3, PT_R26(sp) # save a3 for syscall restarting 48 sd a3, PT_R26(sp) # save a3 for syscall restarting
49 49
50 li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT 50 li t1, _TIF_WORK_SYSCALL_ENTRY
51 LONG_L t0, TI_FLAGS($28) # syscall tracing enabled? 51 LONG_L t0, TI_FLAGS($28) # syscall tracing enabled?
52 and t0, t1, t0 52 and t0, t1, t0
53 bnez t0, n32_syscall_trace_entry 53 bnez t0, n32_syscall_trace_entry
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 74f485d3c0ef..37605dc8eef7 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -81,7 +81,7 @@ NESTED(handle_sys, PT_SIZE, sp)
81 PTR 4b, bad_stack 81 PTR 4b, bad_stack
82 .previous 82 .previous
83 83
84 li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT 84 li t1, _TIF_WORK_SYSCALL_ENTRY
85 LONG_L t0, TI_FLAGS($28) # syscall tracing enabled? 85 LONG_L t0, TI_FLAGS($28) # syscall tracing enabled?
86 and t0, t1, t0 86 and t0, t1, t0
87 bnez t0, trace_a_syscall 87 bnez t0, trace_a_syscall
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index fd3ef2c2afbc..2f285abc76d5 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -8,6 +8,7 @@
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 */ 9 */
10#include <linux/cache.h> 10#include <linux/cache.h>
11#include <linux/context_tracking.h>
11#include <linux/irqflags.h> 12#include <linux/irqflags.h>
12#include <linux/sched.h> 13#include <linux/sched.h>
13#include <linux/mm.h> 14#include <linux/mm.h>
@@ -573,6 +574,8 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, void *unused,
573{ 574{
574 local_irq_enable(); 575 local_irq_enable();
575 576
577 user_exit();
578
576 /* deal with pending signal delivery */ 579 /* deal with pending signal delivery */
577 if (thread_info_flags & _TIF_SIGPENDING) 580 if (thread_info_flags & _TIF_SIGPENDING)
578 do_signal(regs); 581 do_signal(regs);
@@ -581,6 +584,8 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, void *unused,
581 clear_thread_flag(TIF_NOTIFY_RESUME); 584 clear_thread_flag(TIF_NOTIFY_RESUME);
582 tracehook_notify_resume(regs); 585 tracehook_notify_resume(regs);
583 } 586 }
587
588 user_enter();
584} 589}
585 590
586#ifdef CONFIG_SMP 591#ifdef CONFIG_SMP
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index 8e393b8443f7..aea6c0885838 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -63,7 +63,7 @@ static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id);
63 63
64static void __init bmips_smp_setup(void) 64static void __init bmips_smp_setup(void)
65{ 65{
66 int i; 66 int i, cpu = 1, boot_cpu = 0;
67 67
68#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) 68#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
69 /* arbitration priority */ 69 /* arbitration priority */
@@ -72,13 +72,22 @@ static void __init bmips_smp_setup(void)
72 /* NBK and weak order flags */ 72 /* NBK and weak order flags */
73 set_c0_brcm_config_0(0x30000); 73 set_c0_brcm_config_0(0x30000);
74 74
75 /* Find out if we are running on TP0 or TP1 */
76 boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
77
75 /* 78 /*
76 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread 79 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread
77 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output 80 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
78 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output 81 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
82 *
83 * If booting from TP1, leave the existing CMT interrupt routing
84 * such that TP0 responds to SW1 and TP1 responds to SW0.
79 */ 85 */
80 change_c0_brcm_cmt_intr(0xf8018000, 86 if (boot_cpu == 0)
81 (0x02 << 27) | (0x03 << 15)); 87 change_c0_brcm_cmt_intr(0xf8018000,
88 (0x02 << 27) | (0x03 << 15));
89 else
90 change_c0_brcm_cmt_intr(0xf8018000, (0x1d << 27));
82 91
83 /* single core, 2 threads (2 pipelines) */ 92 /* single core, 2 threads (2 pipelines) */
84 max_cpus = 2; 93 max_cpus = 2;
@@ -106,9 +115,15 @@ static void __init bmips_smp_setup(void)
106 if (!board_ebase_setup) 115 if (!board_ebase_setup)
107 board_ebase_setup = &bmips_ebase_setup; 116 board_ebase_setup = &bmips_ebase_setup;
108 117
118 __cpu_number_map[boot_cpu] = 0;
119 __cpu_logical_map[0] = boot_cpu;
120
109 for (i = 0; i < max_cpus; i++) { 121 for (i = 0; i < max_cpus; i++) {
110 __cpu_number_map[i] = 1; 122 if (i != boot_cpu) {
111 __cpu_logical_map[i] = 1; 123 __cpu_number_map[i] = cpu;
124 __cpu_logical_map[cpu] = i;
125 cpu++;
126 }
112 set_cpu_possible(i, 1); 127 set_cpu_possible(i, 1);
113 set_cpu_present(i, 1); 128 set_cpu_present(i, 1);
114 } 129 }
@@ -157,7 +172,9 @@ static void bmips_boot_secondary(int cpu, struct task_struct *idle)
157 bmips_send_ipi_single(cpu, 0); 172 bmips_send_ipi_single(cpu, 0);
158 else { 173 else {
159#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) 174#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
160 set_c0_brcm_cmt_ctrl(0x01); 175 /* Reset slave TP1 if booting from TP0 */
176 if (cpu_logical_map(cpu) == 0)
177 set_c0_brcm_cmt_ctrl(0x01);
161#elif defined(CONFIG_CPU_BMIPS5000) 178#elif defined(CONFIG_CPU_BMIPS5000)
162 if (cpu & 0x01) 179 if (cpu & 0x01)
163 write_c0_brcm_action(ACTION_BOOT_THREAD(cpu)); 180 write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index a75ae40184aa..0903d70b2cfe 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -13,6 +13,7 @@
13 */ 13 */
14#include <linux/bug.h> 14#include <linux/bug.h>
15#include <linux/compiler.h> 15#include <linux/compiler.h>
16#include <linux/context_tracking.h>
16#include <linux/kexec.h> 17#include <linux/kexec.h>
17#include <linux/init.h> 18#include <linux/init.h>
18#include <linux/kernel.h> 19#include <linux/kernel.h>
@@ -264,7 +265,7 @@ static void __show_regs(const struct pt_regs *regs)
264 265
265 printk("Status: %08x ", (uint32_t) regs->cp0_status); 266 printk("Status: %08x ", (uint32_t) regs->cp0_status);
266 267
267 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { 268 if (cpu_has_3kex) {
268 if (regs->cp0_status & ST0_KUO) 269 if (regs->cp0_status & ST0_KUO)
269 printk("KUo "); 270 printk("KUo ");
270 if (regs->cp0_status & ST0_IEO) 271 if (regs->cp0_status & ST0_IEO)
@@ -277,7 +278,7 @@ static void __show_regs(const struct pt_regs *regs)
277 printk("KUc "); 278 printk("KUc ");
278 if (regs->cp0_status & ST0_IEC) 279 if (regs->cp0_status & ST0_IEC)
279 printk("IEc "); 280 printk("IEc ");
280 } else { 281 } else if (cpu_has_4kex) {
281 if (regs->cp0_status & ST0_KX) 282 if (regs->cp0_status & ST0_KX)
282 printk("KX "); 283 printk("KX ");
283 if (regs->cp0_status & ST0_SX) 284 if (regs->cp0_status & ST0_SX)
@@ -423,7 +424,9 @@ asmlinkage void do_be(struct pt_regs *regs)
423 const struct exception_table_entry *fixup = NULL; 424 const struct exception_table_entry *fixup = NULL;
424 int data = regs->cp0_cause & 4; 425 int data = regs->cp0_cause & 4;
425 int action = MIPS_BE_FATAL; 426 int action = MIPS_BE_FATAL;
427 enum ctx_state prev_state;
426 428
429 prev_state = exception_enter();
427 /* XXX For now. Fixme, this searches the wrong table ... */ 430 /* XXX For now. Fixme, this searches the wrong table ... */
428 if (data && !user_mode(regs)) 431 if (data && !user_mode(regs))
429 fixup = search_dbe_tables(exception_epc(regs)); 432 fixup = search_dbe_tables(exception_epc(regs));
@@ -436,11 +439,11 @@ asmlinkage void do_be(struct pt_regs *regs)
436 439
437 switch (action) { 440 switch (action) {
438 case MIPS_BE_DISCARD: 441 case MIPS_BE_DISCARD:
439 return; 442 goto out;
440 case MIPS_BE_FIXUP: 443 case MIPS_BE_FIXUP:
441 if (fixup) { 444 if (fixup) {
442 regs->cp0_epc = fixup->nextinsn; 445 regs->cp0_epc = fixup->nextinsn;
443 return; 446 goto out;
444 } 447 }
445 break; 448 break;
446 default: 449 default:
@@ -455,10 +458,13 @@ asmlinkage void do_be(struct pt_regs *regs)
455 field, regs->cp0_epc, field, regs->regs[31]); 458 field, regs->cp0_epc, field, regs->regs[31]);
456 if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS) 459 if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS)
457 == NOTIFY_STOP) 460 == NOTIFY_STOP)
458 return; 461 goto out;
459 462
460 die_if_kernel("Oops", regs); 463 die_if_kernel("Oops", regs);
461 force_sig(SIGBUS, current); 464 force_sig(SIGBUS, current);
465
466out:
467 exception_exit(prev_state);
462} 468}
463 469
464/* 470/*
@@ -673,8 +679,10 @@ static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
673 679
674asmlinkage void do_ov(struct pt_regs *regs) 680asmlinkage void do_ov(struct pt_regs *regs)
675{ 681{
682 enum ctx_state prev_state;
676 siginfo_t info; 683 siginfo_t info;
677 684
685 prev_state = exception_enter();
678 die_if_kernel("Integer overflow", regs); 686 die_if_kernel("Integer overflow", regs);
679 687
680 info.si_code = FPE_INTOVF; 688 info.si_code = FPE_INTOVF;
@@ -682,6 +690,7 @@ asmlinkage void do_ov(struct pt_regs *regs)
682 info.si_errno = 0; 690 info.si_errno = 0;
683 info.si_addr = (void __user *) regs->cp0_epc; 691 info.si_addr = (void __user *) regs->cp0_epc;
684 force_sig_info(SIGFPE, &info, current); 692 force_sig_info(SIGFPE, &info, current);
693 exception_exit(prev_state);
685} 694}
686 695
687int process_fpemu_return(int sig, void __user *fault_addr) 696int process_fpemu_return(int sig, void __user *fault_addr)
@@ -713,11 +722,13 @@ int process_fpemu_return(int sig, void __user *fault_addr)
713 */ 722 */
714asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) 723asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
715{ 724{
725 enum ctx_state prev_state;
716 siginfo_t info = {0}; 726 siginfo_t info = {0};
717 727
728 prev_state = exception_enter();
718 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE) 729 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE)
719 == NOTIFY_STOP) 730 == NOTIFY_STOP)
720 return; 731 goto out;
721 die_if_kernel("FP exception in kernel code", regs); 732 die_if_kernel("FP exception in kernel code", regs);
722 733
723 if (fcr31 & FPU_CSR_UNI_X) { 734 if (fcr31 & FPU_CSR_UNI_X) {
@@ -753,7 +764,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
753 /* If something went wrong, signal */ 764 /* If something went wrong, signal */
754 process_fpemu_return(sig, fault_addr); 765 process_fpemu_return(sig, fault_addr);
755 766
756 return; 767 goto out;
757 } else if (fcr31 & FPU_CSR_INV_X) 768 } else if (fcr31 & FPU_CSR_INV_X)
758 info.si_code = FPE_FLTINV; 769 info.si_code = FPE_FLTINV;
759 else if (fcr31 & FPU_CSR_DIV_X) 770 else if (fcr31 & FPU_CSR_DIV_X)
@@ -770,6 +781,9 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
770 info.si_errno = 0; 781 info.si_errno = 0;
771 info.si_addr = (void __user *) regs->cp0_epc; 782 info.si_addr = (void __user *) regs->cp0_epc;
772 force_sig_info(SIGFPE, &info, current); 783 force_sig_info(SIGFPE, &info, current);
784
785out:
786 exception_exit(prev_state);
773} 787}
774 788
775static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, 789static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
@@ -835,9 +849,11 @@ static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
835asmlinkage void do_bp(struct pt_regs *regs) 849asmlinkage void do_bp(struct pt_regs *regs)
836{ 850{
837 unsigned int opcode, bcode; 851 unsigned int opcode, bcode;
852 enum ctx_state prev_state;
838 unsigned long epc; 853 unsigned long epc;
839 u16 instr[2]; 854 u16 instr[2];
840 855
856 prev_state = exception_enter();
841 if (get_isa16_mode(regs->cp0_epc)) { 857 if (get_isa16_mode(regs->cp0_epc)) {
842 /* Calculate EPC. */ 858 /* Calculate EPC. */
843 epc = exception_epc(regs); 859 epc = exception_epc(regs);
@@ -852,7 +868,7 @@ asmlinkage void do_bp(struct pt_regs *regs)
852 goto out_sigsegv; 868 goto out_sigsegv;
853 bcode = (instr[0] >> 6) & 0x3f; 869 bcode = (instr[0] >> 6) & 0x3f;
854 do_trap_or_bp(regs, bcode, "Break"); 870 do_trap_or_bp(regs, bcode, "Break");
855 return; 871 goto out;
856 } 872 }
857 } else { 873 } else {
858 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) 874 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
@@ -876,12 +892,12 @@ asmlinkage void do_bp(struct pt_regs *regs)
876 switch (bcode) { 892 switch (bcode) {
877 case BRK_KPROBE_BP: 893 case BRK_KPROBE_BP:
878 if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 894 if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
879 return; 895 goto out;
880 else 896 else
881 break; 897 break;
882 case BRK_KPROBE_SSTEPBP: 898 case BRK_KPROBE_SSTEPBP:
883 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 899 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
884 return; 900 goto out;
885 else 901 else
886 break; 902 break;
887 default: 903 default:
@@ -889,18 +905,24 @@ asmlinkage void do_bp(struct pt_regs *regs)
889 } 905 }
890 906
891 do_trap_or_bp(regs, bcode, "Break"); 907 do_trap_or_bp(regs, bcode, "Break");
908
909out:
910 exception_exit(prev_state);
892 return; 911 return;
893 912
894out_sigsegv: 913out_sigsegv:
895 force_sig(SIGSEGV, current); 914 force_sig(SIGSEGV, current);
915 goto out;
896} 916}
897 917
898asmlinkage void do_tr(struct pt_regs *regs) 918asmlinkage void do_tr(struct pt_regs *regs)
899{ 919{
900 u32 opcode, tcode = 0; 920 u32 opcode, tcode = 0;
921 enum ctx_state prev_state;
901 u16 instr[2]; 922 u16 instr[2];
902 unsigned long epc = msk_isa16_mode(exception_epc(regs)); 923 unsigned long epc = msk_isa16_mode(exception_epc(regs));
903 924
925 prev_state = exception_enter();
904 if (get_isa16_mode(regs->cp0_epc)) { 926 if (get_isa16_mode(regs->cp0_epc)) {
905 if (__get_user(instr[0], (u16 __user *)(epc + 0)) || 927 if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
906 __get_user(instr[1], (u16 __user *)(epc + 2))) 928 __get_user(instr[1], (u16 __user *)(epc + 2)))
@@ -918,10 +940,14 @@ asmlinkage void do_tr(struct pt_regs *regs)
918 } 940 }
919 941
920 do_trap_or_bp(regs, tcode, "Trap"); 942 do_trap_or_bp(regs, tcode, "Trap");
943
944out:
945 exception_exit(prev_state);
921 return; 946 return;
922 947
923out_sigsegv: 948out_sigsegv:
924 force_sig(SIGSEGV, current); 949 force_sig(SIGSEGV, current);
950 goto out;
925} 951}
926 952
927asmlinkage void do_ri(struct pt_regs *regs) 953asmlinkage void do_ri(struct pt_regs *regs)
@@ -929,17 +955,19 @@ asmlinkage void do_ri(struct pt_regs *regs)
929 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); 955 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
930 unsigned long old_epc = regs->cp0_epc; 956 unsigned long old_epc = regs->cp0_epc;
931 unsigned long old31 = regs->regs[31]; 957 unsigned long old31 = regs->regs[31];
958 enum ctx_state prev_state;
932 unsigned int opcode = 0; 959 unsigned int opcode = 0;
933 int status = -1; 960 int status = -1;
934 961
962 prev_state = exception_enter();
935 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL) 963 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL)
936 == NOTIFY_STOP) 964 == NOTIFY_STOP)
937 return; 965 goto out;
938 966
939 die_if_kernel("Reserved instruction in kernel code", regs); 967 die_if_kernel("Reserved instruction in kernel code", regs);
940 968
941 if (unlikely(compute_return_epc(regs) < 0)) 969 if (unlikely(compute_return_epc(regs) < 0))
942 return; 970 goto out;
943 971
944 if (get_isa16_mode(regs->cp0_epc)) { 972 if (get_isa16_mode(regs->cp0_epc)) {
945 unsigned short mmop[2] = { 0 }; 973 unsigned short mmop[2] = { 0 };
@@ -974,6 +1002,9 @@ asmlinkage void do_ri(struct pt_regs *regs)
974 regs->regs[31] = old31; 1002 regs->regs[31] = old31;
975 force_sig(status, current); 1003 force_sig(status, current);
976 } 1004 }
1005
1006out:
1007 exception_exit(prev_state);
977} 1008}
978 1009
979/* 1010/*
@@ -1025,21 +1056,16 @@ static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
1025{ 1056{
1026 struct pt_regs *regs = data; 1057 struct pt_regs *regs = data;
1027 1058
1028 switch (action) { 1059 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
1029 default:
1030 die_if_kernel("Unhandled kernel unaligned access or invalid "
1031 "instruction", regs); 1060 "instruction", regs);
1032 /* Fall through */ 1061 force_sig(SIGILL, current);
1033
1034 case CU2_EXCEPTION:
1035 force_sig(SIGILL, current);
1036 }
1037 1062
1038 return NOTIFY_OK; 1063 return NOTIFY_OK;
1039} 1064}
1040 1065
1041asmlinkage void do_cpu(struct pt_regs *regs) 1066asmlinkage void do_cpu(struct pt_regs *regs)
1042{ 1067{
1068 enum ctx_state prev_state;
1043 unsigned int __user *epc; 1069 unsigned int __user *epc;
1044 unsigned long old_epc, old31; 1070 unsigned long old_epc, old31;
1045 unsigned int opcode; 1071 unsigned int opcode;
@@ -1047,10 +1073,12 @@ asmlinkage void do_cpu(struct pt_regs *regs)
1047 int status; 1073 int status;
1048 unsigned long __maybe_unused flags; 1074 unsigned long __maybe_unused flags;
1049 1075
1050 die_if_kernel("do_cpu invoked from kernel context!", regs); 1076 prev_state = exception_enter();
1051
1052 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; 1077 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
1053 1078
1079 if (cpid != 2)
1080 die_if_kernel("do_cpu invoked from kernel context!", regs);
1081
1054 switch (cpid) { 1082 switch (cpid) {
1055 case 0: 1083 case 0:
1056 epc = (unsigned int __user *)exception_epc(regs); 1084 epc = (unsigned int __user *)exception_epc(regs);
@@ -1060,7 +1088,7 @@ asmlinkage void do_cpu(struct pt_regs *regs)
1060 status = -1; 1088 status = -1;
1061 1089
1062 if (unlikely(compute_return_epc(regs) < 0)) 1090 if (unlikely(compute_return_epc(regs) < 0))
1063 return; 1091 goto out;
1064 1092
1065 if (get_isa16_mode(regs->cp0_epc)) { 1093 if (get_isa16_mode(regs->cp0_epc)) {
1066 unsigned short mmop[2] = { 0 }; 1094 unsigned short mmop[2] = { 0 };
@@ -1093,7 +1121,7 @@ asmlinkage void do_cpu(struct pt_regs *regs)
1093 force_sig(status, current); 1121 force_sig(status, current);
1094 } 1122 }
1095 1123
1096 return; 1124 goto out;
1097 1125
1098 case 3: 1126 case 3:
1099 /* 1127 /*
@@ -1131,19 +1159,26 @@ asmlinkage void do_cpu(struct pt_regs *regs)
1131 mt_ase_fp_affinity(); 1159 mt_ase_fp_affinity();
1132 } 1160 }
1133 1161
1134 return; 1162 goto out;
1135 1163
1136 case 2: 1164 case 2:
1137 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); 1165 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1138 return; 1166 goto out;
1139 } 1167 }
1140 1168
1141 force_sig(SIGILL, current); 1169 force_sig(SIGILL, current);
1170
1171out:
1172 exception_exit(prev_state);
1142} 1173}
1143 1174
1144asmlinkage void do_mdmx(struct pt_regs *regs) 1175asmlinkage void do_mdmx(struct pt_regs *regs)
1145{ 1176{
1177 enum ctx_state prev_state;
1178
1179 prev_state = exception_enter();
1146 force_sig(SIGILL, current); 1180 force_sig(SIGILL, current);
1181 exception_exit(prev_state);
1147} 1182}
1148 1183
1149/* 1184/*
@@ -1151,8 +1186,10 @@ asmlinkage void do_mdmx(struct pt_regs *regs)
1151 */ 1186 */
1152asmlinkage void do_watch(struct pt_regs *regs) 1187asmlinkage void do_watch(struct pt_regs *regs)
1153{ 1188{
1189 enum ctx_state prev_state;
1154 u32 cause; 1190 u32 cause;
1155 1191
1192 prev_state = exception_enter();
1156 /* 1193 /*
1157 * Clear WP (bit 22) bit of cause register so we don't loop 1194 * Clear WP (bit 22) bit of cause register so we don't loop
1158 * forever. 1195 * forever.
@@ -1174,13 +1211,16 @@ asmlinkage void do_watch(struct pt_regs *regs)
1174 mips_clear_watch_registers(); 1211 mips_clear_watch_registers();
1175 local_irq_enable(); 1212 local_irq_enable();
1176 } 1213 }
1214 exception_exit(prev_state);
1177} 1215}
1178 1216
1179asmlinkage void do_mcheck(struct pt_regs *regs) 1217asmlinkage void do_mcheck(struct pt_regs *regs)
1180{ 1218{
1181 const int field = 2 * sizeof(unsigned long); 1219 const int field = 2 * sizeof(unsigned long);
1182 int multi_match = regs->cp0_status & ST0_TS; 1220 int multi_match = regs->cp0_status & ST0_TS;
1221 enum ctx_state prev_state;
1183 1222
1223 prev_state = exception_enter();
1184 show_regs(regs); 1224 show_regs(regs);
1185 1225
1186 if (multi_match) { 1226 if (multi_match) {
@@ -1202,6 +1242,7 @@ asmlinkage void do_mcheck(struct pt_regs *regs)
1202 panic("Caught Machine Check exception - %scaused by multiple " 1242 panic("Caught Machine Check exception - %scaused by multiple "
1203 "matching entries in the TLB.", 1243 "matching entries in the TLB.",
1204 (multi_match) ? "" : "not "); 1244 (multi_match) ? "" : "not ");
1245 exception_exit(prev_state);
1205} 1246}
1206 1247
1207asmlinkage void do_mt(struct pt_regs *regs) 1248asmlinkage void do_mt(struct pt_regs *regs)
@@ -1627,7 +1668,6 @@ void *set_vi_handler(int n, vi_handler_t addr)
1627} 1668}
1628 1669
1629extern void tlb_init(void); 1670extern void tlb_init(void);
1630extern void flush_tlb_handlers(void);
1631 1671
1632/* 1672/*
1633 * Timer interrupt 1673 * Timer interrupt
@@ -1837,6 +1877,15 @@ void __init trap_init(void)
1837 ebase += (read_c0_ebase() & 0x3ffff000); 1877 ebase += (read_c0_ebase() & 0x3ffff000);
1838 } 1878 }
1839 1879
1880 if (cpu_has_mmips) {
1881 unsigned int config3 = read_c0_config3();
1882
1883 if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
1884 write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
1885 else
1886 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
1887 }
1888
1840 if (board_ebase_setup) 1889 if (board_ebase_setup)
1841 board_ebase_setup(); 1890 board_ebase_setup();
1842 per_cpu_trap_init(true); 1891 per_cpu_trap_init(true);
@@ -1956,7 +2005,6 @@ void __init trap_init(void)
1956 set_handler(0x080, &except_vec3_generic, 0x80); 2005 set_handler(0x080, &except_vec3_generic, 0x80);
1957 2006
1958 local_flush_icache_range(ebase, ebase + 0x400); 2007 local_flush_icache_range(ebase, ebase + 0x400);
1959 flush_tlb_handlers();
1960 2008
1961 sort_extable(__start___dbe_table, __stop___dbe_table); 2009 sort_extable(__start___dbe_table, __stop___dbe_table);
1962 2010
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 203d8857070d..c369a5d35527 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -72,6 +72,7 @@
72 * A store crossing a page boundary might be executed only partially. 72 * A store crossing a page boundary might be executed only partially.
73 * Undo the partial store in this case. 73 * Undo the partial store in this case.
74 */ 74 */
75#include <linux/context_tracking.h>
75#include <linux/mm.h> 76#include <linux/mm.h>
76#include <linux/signal.h> 77#include <linux/signal.h>
77#include <linux/smp.h> 78#include <linux/smp.h>
@@ -684,7 +685,8 @@ const int reg16to32[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
684/* Recode table from 16-bit STORE register notation to 32-bit GPR. */ 685/* Recode table from 16-bit STORE register notation to 32-bit GPR. */
685const int reg16to32st[] = { 0, 17, 2, 3, 4, 5, 6, 7 }; 686const int reg16to32st[] = { 0, 17, 2, 3, 4, 5, 6, 7 };
686 687
687void emulate_load_store_microMIPS(struct pt_regs *regs, void __user * addr) 688static void emulate_load_store_microMIPS(struct pt_regs *regs,
689 void __user *addr)
688{ 690{
689 unsigned long value; 691 unsigned long value;
690 unsigned int res; 692 unsigned int res;
@@ -1548,11 +1550,14 @@ sigill:
1548 ("Unhandled kernel unaligned access or invalid instruction", regs); 1550 ("Unhandled kernel unaligned access or invalid instruction", regs);
1549 force_sig(SIGILL, current); 1551 force_sig(SIGILL, current);
1550} 1552}
1553
1551asmlinkage void do_ade(struct pt_regs *regs) 1554asmlinkage void do_ade(struct pt_regs *regs)
1552{ 1555{
1556 enum ctx_state prev_state;
1553 unsigned int __user *pc; 1557 unsigned int __user *pc;
1554 mm_segment_t seg; 1558 mm_segment_t seg;
1555 1559
1560 prev_state = exception_enter();
1556 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1561 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS,
1557 1, regs, regs->cp0_badvaddr); 1562 1, regs, regs->cp0_badvaddr);
1558 /* 1563 /*
@@ -1628,6 +1633,7 @@ sigbus:
1628 /* 1633 /*
1629 * XXX On return from the signal handler we should advance the epc 1634 * XXX On return from the signal handler we should advance the epc
1630 */ 1635 */
1636 exception_exit(prev_state);
1631} 1637}
1632 1638
1633#ifdef CONFIG_DEBUG_FS 1639#ifdef CONFIG_DEBUG_FS
diff --git a/arch/mips/kernel/watch.c b/arch/mips/kernel/watch.c
index 7726f6157d9e..cbdc4de85bb4 100644
--- a/arch/mips/kernel/watch.c
+++ b/arch/mips/kernel/watch.c
@@ -111,6 +111,7 @@ __cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c)
111 * disable the register. 111 * disable the register.
112 */ 112 */
113 write_c0_watchlo0(7); 113 write_c0_watchlo0(7);
114 back_to_back_c0_hazard();
114 t = read_c0_watchlo0(); 115 t = read_c0_watchlo0();
115 write_c0_watchlo0(0); 116 write_c0_watchlo0(0);
116 c->watch_reg_masks[0] = t & 7; 117 c->watch_reg_masks[0] = t & 7;
@@ -121,12 +122,14 @@ __cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c)
121 c->watch_reg_use_cnt = 1; 122 c->watch_reg_use_cnt = 1;
122 t = read_c0_watchhi0(); 123 t = read_c0_watchhi0();
123 write_c0_watchhi0(t | 0xff8); 124 write_c0_watchhi0(t | 0xff8);
125 back_to_back_c0_hazard();
124 t = read_c0_watchhi0(); 126 t = read_c0_watchhi0();
125 c->watch_reg_masks[0] |= (t & 0xff8); 127 c->watch_reg_masks[0] |= (t & 0xff8);
126 if ((t & 0x80000000) == 0) 128 if ((t & 0x80000000) == 0)
127 return; 129 return;
128 130
129 write_c0_watchlo1(7); 131 write_c0_watchlo1(7);
132 back_to_back_c0_hazard();
130 t = read_c0_watchlo1(); 133 t = read_c0_watchlo1();
131 write_c0_watchlo1(0); 134 write_c0_watchlo1(0);
132 c->watch_reg_masks[1] = t & 7; 135 c->watch_reg_masks[1] = t & 7;
@@ -135,12 +138,14 @@ __cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c)
135 c->watch_reg_use_cnt = 2; 138 c->watch_reg_use_cnt = 2;
136 t = read_c0_watchhi1(); 139 t = read_c0_watchhi1();
137 write_c0_watchhi1(t | 0xff8); 140 write_c0_watchhi1(t | 0xff8);
141 back_to_back_c0_hazard();
138 t = read_c0_watchhi1(); 142 t = read_c0_watchhi1();
139 c->watch_reg_masks[1] |= (t & 0xff8); 143 c->watch_reg_masks[1] |= (t & 0xff8);
140 if ((t & 0x80000000) == 0) 144 if ((t & 0x80000000) == 0)
141 return; 145 return;
142 146
143 write_c0_watchlo2(7); 147 write_c0_watchlo2(7);
148 back_to_back_c0_hazard();
144 t = read_c0_watchlo2(); 149 t = read_c0_watchlo2();
145 write_c0_watchlo2(0); 150 write_c0_watchlo2(0);
146 c->watch_reg_masks[2] = t & 7; 151 c->watch_reg_masks[2] = t & 7;
@@ -149,12 +154,14 @@ __cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c)
149 c->watch_reg_use_cnt = 3; 154 c->watch_reg_use_cnt = 3;
150 t = read_c0_watchhi2(); 155 t = read_c0_watchhi2();
151 write_c0_watchhi2(t | 0xff8); 156 write_c0_watchhi2(t | 0xff8);
157 back_to_back_c0_hazard();
152 t = read_c0_watchhi2(); 158 t = read_c0_watchhi2();
153 c->watch_reg_masks[2] |= (t & 0xff8); 159 c->watch_reg_masks[2] |= (t & 0xff8);
154 if ((t & 0x80000000) == 0) 160 if ((t & 0x80000000) == 0)
155 return; 161 return;
156 162
157 write_c0_watchlo3(7); 163 write_c0_watchlo3(7);
164 back_to_back_c0_hazard();
158 t = read_c0_watchlo3(); 165 t = read_c0_watchlo3();
159 write_c0_watchlo3(0); 166 write_c0_watchlo3(0);
160 c->watch_reg_masks[3] = t & 7; 167 c->watch_reg_masks[3] = t & 7;
@@ -163,6 +170,7 @@ __cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c)
163 c->watch_reg_use_cnt = 4; 170 c->watch_reg_use_cnt = 4;
164 t = read_c0_watchhi3(); 171 t = read_c0_watchhi3();
165 write_c0_watchhi3(t | 0xff8); 172 write_c0_watchhi3(t | 0xff8);
173 back_to_back_c0_hazard();
166 t = read_c0_watchhi3(); 174 t = read_c0_watchhi3();
167 c->watch_reg_masks[3] |= (t & 0xff8); 175 c->watch_reg_masks[3] |= (t & 0xff8);
168 if ((t & 0x80000000) == 0) 176 if ((t & 0x80000000) == 0)
diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
index 9f9e875967aa..49c460370285 100644
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -112,7 +112,7 @@ int __init plat_of_setup(void)
112 if (!of_have_populated_dt()) 112 if (!of_have_populated_dt())
113 panic("device tree not present"); 113 panic("device tree not present");
114 114
115 strncpy(of_ids[0].compatible, soc_info.compatible, 115 strlcpy(of_ids[0].compatible, soc_info.compatible,
116 sizeof(of_ids[0].compatible)); 116 sizeof(of_ids[0].compatible));
117 strncpy(of_ids[1].compatible, "simple-bus", 117 strncpy(of_ids[1].compatible, "simple-bus",
118 sizeof(of_ids[1].compatible)); 118 sizeof(of_ids[1].compatible));
diff --git a/arch/mips/lasat/sysctl.c b/arch/mips/lasat/sysctl.c
index f27694fb2ad1..3b7f65cc4218 100644
--- a/arch/mips/lasat/sysctl.c
+++ b/arch/mips/lasat/sysctl.c
@@ -39,7 +39,7 @@
39 39
40 40
41/* And the same for proc */ 41/* And the same for proc */
42int proc_dolasatstring(ctl_table *table, int write, 42int proc_dolasatstring(struct ctl_table *table, int write,
43 void *buffer, size_t *lenp, loff_t *ppos) 43 void *buffer, size_t *lenp, loff_t *ppos)
44{ 44{
45 int r; 45 int r;
@@ -54,7 +54,7 @@ int proc_dolasatstring(ctl_table *table, int write,
54} 54}
55 55
56/* proc function to write EEPROM after changing int entry */ 56/* proc function to write EEPROM after changing int entry */
57int proc_dolasatint(ctl_table *table, int write, 57int proc_dolasatint(struct ctl_table *table, int write,
58 void *buffer, size_t *lenp, loff_t *ppos) 58 void *buffer, size_t *lenp, loff_t *ppos)
59{ 59{
60 int r; 60 int r;
@@ -72,7 +72,7 @@ int proc_dolasatint(ctl_table *table, int write,
72static int rtctmp; 72static int rtctmp;
73 73
74/* proc function to read/write RealTime Clock */ 74/* proc function to read/write RealTime Clock */
75int proc_dolasatrtc(ctl_table *table, int write, 75int proc_dolasatrtc(struct ctl_table *table, int write,
76 void *buffer, size_t *lenp, loff_t *ppos) 76 void *buffer, size_t *lenp, loff_t *ppos)
77{ 77{
78 struct timespec ts; 78 struct timespec ts;
@@ -97,7 +97,7 @@ int proc_dolasatrtc(ctl_table *table, int write,
97#endif 97#endif
98 98
99#ifdef CONFIG_INET 99#ifdef CONFIG_INET
100int proc_lasat_ip(ctl_table *table, int write, 100int proc_lasat_ip(struct ctl_table *table, int write,
101 void *buffer, size_t *lenp, loff_t *ppos) 101 void *buffer, size_t *lenp, loff_t *ppos)
102{ 102{
103 unsigned int ip; 103 unsigned int ip;
@@ -157,7 +157,7 @@ int proc_lasat_ip(ctl_table *table, int write,
157} 157}
158#endif 158#endif
159 159
160int proc_lasat_prid(ctl_table *table, int write, 160int proc_lasat_prid(struct ctl_table *table, int write,
161 void *buffer, size_t *lenp, loff_t *ppos) 161 void *buffer, size_t *lenp, loff_t *ppos)
162{ 162{
163 int r; 163 int r;
@@ -176,7 +176,7 @@ int proc_lasat_prid(ctl_table *table, int write,
176 176
177extern int lasat_boot_to_service; 177extern int lasat_boot_to_service;
178 178
179static ctl_table lasat_table[] = { 179static struct ctl_table lasat_table[] = {
180 { 180 {
181 .procname = "cpu-hz", 181 .procname = "cpu-hz",
182 .data = &lasat_board_info.li_cpu_hz, 182 .data = &lasat_board_info.li_cpu_hz,
@@ -262,7 +262,7 @@ static ctl_table lasat_table[] = {
262 {} 262 {}
263}; 263};
264 264
265static ctl_table lasat_root_table[] = { 265static struct ctl_table lasat_root_table[] = {
266 { 266 {
267 .procname = "lasat", 267 .procname = "lasat",
268 .mode = 0555, 268 .mode = 0555,
diff --git a/arch/mips/loongson/common/cs5536/cs5536_isa.c b/arch/mips/loongson/common/cs5536/cs5536_isa.c
index a6eb2e853d94..924be39e7733 100644
--- a/arch/mips/loongson/common/cs5536/cs5536_isa.c
+++ b/arch/mips/loongson/common/cs5536/cs5536_isa.c
@@ -13,6 +13,7 @@
13 * option) any later version. 13 * option) any later version.
14 */ 14 */
15 15
16#include <linux/pci.h>
16#include <cs5536/cs5536.h> 17#include <cs5536/cs5536.h>
17#include <cs5536/cs5536_pci.h> 18#include <cs5536/cs5536_pci.h>
18 19
@@ -314,3 +315,16 @@ u32 pci_isa_read_reg(int reg)
314 315
315 return conf_data; 316 return conf_data;
316} 317}
318
319/*
320 * The mfgpt timer interrupt is running early, so we must keep the south bridge
321 * mmio always enabled. Otherwise we may race with the PCI configuration which
322 * may temporarily disable it. When that happens and the timer interrupt fires,
323 * we are not able to clear it and the system will hang.
324 */
325static void cs5536_isa_mmio_always_on(struct pci_dev *dev)
326{
327 dev->mmio_always_on = 1;
328}
329DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA,
330 PCI_CLASS_BRIDGE_ISA, 8, cs5536_isa_mmio_always_on);
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index f03771900813..e773659ccf9f 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -471,6 +471,9 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
471 unsigned int fcr31; 471 unsigned int fcr31;
472 unsigned int bit; 472 unsigned int bit;
473 473
474 if (!cpu_has_mmips)
475 return 0;
476
474 switch (insn.mm_i_format.opcode) { 477 switch (insn.mm_i_format.opcode) {
475 case mm_pool32a_op: 478 case mm_pool32a_op:
476 if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) == 479 if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) ==
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index e87aae1f2e80..7f4f93ab22b7 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -4,7 +4,7 @@
4 4
5obj-y += cache.o dma-default.o extable.o fault.o \ 5obj-y += cache.o dma-default.o extable.o fault.o \
6 gup.o init.o mmap.o page.o page-funcs.o \ 6 gup.o init.o mmap.o page.o page-funcs.o \
7 tlbex.o tlbex-fault.o uasm-mips.o 7 tlbex.o tlbex-fault.o tlb-funcs.o uasm-mips.o
8 8
9obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o 9obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o
10obj-$(CONFIG_64BIT) += pgtable-64.o 10obj-$(CONFIG_64BIT) += pgtable-64.o
diff --git a/arch/mips/mm/cerr-sb1.c b/arch/mips/mm/cerr-sb1.c
index 576add33bf5b..ee5c1ff861ae 100644
--- a/arch/mips/mm/cerr-sb1.c
+++ b/arch/mips/mm/cerr-sb1.c
@@ -182,11 +182,7 @@ asmlinkage void sb1_cache_error(void)
182 182
183#ifdef CONFIG_SIBYTE_BW_TRACE 183#ifdef CONFIG_SIBYTE_BW_TRACE
184 /* Freeze the trace buffer now */ 184 /* Freeze the trace buffer now */
185#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
186 csr_out32(M_BCM1480_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG));
187#else
188 csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG)); 185 csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG));
189#endif
190 printk("Trace buffer frozen\n"); 186 printk("Trace buffer frozen\n");
191#endif 187#endif
192 188
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index caf92ecb37d6..aaccf1c10699 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -246,6 +246,9 @@ static int mips_dma_map_sg(struct device *dev, struct scatterlist *sg,
246 if (!plat_device_is_coherent(dev)) 246 if (!plat_device_is_coherent(dev))
247 __dma_sync(sg_page(sg), sg->offset, sg->length, 247 __dma_sync(sg_page(sg), sg->offset, sg->length,
248 direction); 248 direction);
249#ifdef CONFIG_NEED_SG_DMA_LENGTH
250 sg->dma_length = sg->length;
251#endif
249 sg->dma_address = plat_map_dma_mem_page(dev, sg_page(sg)) + 252 sg->dma_address = plat_map_dma_mem_page(dev, sg_page(sg)) +
250 sg->offset; 253 sg->offset;
251 } 254 }
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index 0fead53d1c26..85df1cd8d446 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -5,6 +5,7 @@
5 * 5 *
6 * Copyright (C) 1995 - 2000 by Ralf Baechle 6 * Copyright (C) 1995 - 2000 by Ralf Baechle
7 */ 7 */
8#include <linux/context_tracking.h>
8#include <linux/signal.h> 9#include <linux/signal.h>
9#include <linux/sched.h> 10#include <linux/sched.h>
10#include <linux/interrupt.h> 11#include <linux/interrupt.h>
@@ -32,8 +33,8 @@
32 * and the problem, and then passes it off to one of the appropriate 33 * and the problem, and then passes it off to one of the appropriate
33 * routines. 34 * routines.
34 */ 35 */
35asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, unsigned long write, 36static void __kprobes __do_page_fault(struct pt_regs *regs, unsigned long write,
36 unsigned long address) 37 unsigned long address)
37{ 38{
38 struct vm_area_struct * vma = NULL; 39 struct vm_area_struct * vma = NULL;
39 struct task_struct *tsk = current; 40 struct task_struct *tsk = current;
@@ -312,3 +313,13 @@ vmalloc_fault:
312 } 313 }
313#endif 314#endif
314} 315}
316
317asmlinkage void __kprobes do_page_fault(struct pt_regs *regs,
318 unsigned long write, unsigned long address)
319{
320 enum ctx_state prev_state;
321
322 prev_state = exception_enter();
323 __do_page_fault(regs, write, address);
324 exception_exit(prev_state);
325}
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index 4eb8dcfaf1ce..2c0bd580b9da 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -232,7 +232,7 @@ static inline void __cpuinit build_clear_pref(u32 **buf, int off)
232 232
233 uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0); 233 uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
234 } 234 }
235 } 235 }
236} 236}
237 237
238extern u32 __clear_page_start; 238extern u32 __clear_page_start;
diff --git a/arch/mips/mm/tlb-funcs.S b/arch/mips/mm/tlb-funcs.S
new file mode 100644
index 000000000000..30a494db99c2
--- /dev/null
+++ b/arch/mips/mm/tlb-funcs.S
@@ -0,0 +1,37 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Micro-assembler generated tlb handler functions.
7 *
8 * Copyright (C) 2013 Broadcom Corporation.
9 *
10 * Based on mm/page-funcs.c
11 * Copyright (C) 2012 MIPS Technologies, Inc.
12 * Copyright (C) 2012 Ralf Baechle <ralf@linux-mips.org>
13 */
14#include <asm/asm.h>
15#include <asm/regdef.h>
16
17#define FASTPATH_SIZE 128
18
19LEAF(tlbmiss_handler_setup_pgd)
20 .space 16 * 4
21END(tlbmiss_handler_setup_pgd)
22EXPORT(tlbmiss_handler_setup_pgd_end)
23
24LEAF(handle_tlbm)
25 .space FASTPATH_SIZE * 4
26END(handle_tlbm)
27EXPORT(handle_tlbm_end)
28
29LEAF(handle_tlbs)
30 .space FASTPATH_SIZE * 4
31END(handle_tlbs)
32EXPORT(handle_tlbs_end)
33
34LEAF(handle_tlbl)
35 .space FASTPATH_SIZE * 4
36END(handle_tlbl)
37EXPORT(handle_tlbl_end)
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index afeef93f81a7..9ab0f907a52c 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -305,6 +305,17 @@ static int check_for_high_segbits __cpuinitdata;
305 305
306static unsigned int kscratch_used_mask __cpuinitdata; 306static unsigned int kscratch_used_mask __cpuinitdata;
307 307
308static inline int __maybe_unused c0_kscratch(void)
309{
310 switch (current_cpu_type()) {
311 case CPU_XLP:
312 case CPU_XLR:
313 return 22;
314 default:
315 return 31;
316 }
317}
318
308static int __cpuinit allocate_kscratch(void) 319static int __cpuinit allocate_kscratch(void)
309{ 320{
310 int r; 321 int r;
@@ -334,9 +345,9 @@ static struct work_registers __cpuinit build_get_work_registers(u32 **p)
334 int smp_processor_id_sel; 345 int smp_processor_id_sel;
335 int smp_processor_id_shift; 346 int smp_processor_id_shift;
336 347
337 if (scratch_reg > 0) { 348 if (scratch_reg >= 0) {
338 /* Save in CPU local C0_KScratch? */ 349 /* Save in CPU local C0_KScratch? */
339 UASM_i_MTC0(p, 1, 31, scratch_reg); 350 UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg);
340 r.r1 = K0; 351 r.r1 = K0;
341 r.r2 = K1; 352 r.r2 = K1;
342 r.r3 = 1; 353 r.r3 = 1;
@@ -384,8 +395,8 @@ static struct work_registers __cpuinit build_get_work_registers(u32 **p)
384 395
385static void __cpuinit build_restore_work_registers(u32 **p) 396static void __cpuinit build_restore_work_registers(u32 **p)
386{ 397{
387 if (scratch_reg > 0) { 398 if (scratch_reg >= 0) {
388 UASM_i_MFC0(p, 1, 31, scratch_reg); 399 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
389 return; 400 return;
390 } 401 }
391 /* K0 already points to save area, restore $1 and $2 */ 402 /* K0 already points to save area, restore $1 and $2 */
@@ -673,8 +684,8 @@ static __cpuinit void build_restore_pagemask(u32 **p,
673 uasm_i_mtc0(p, 0, C0_PAGEMASK); 684 uasm_i_mtc0(p, 0, C0_PAGEMASK);
674 uasm_il_b(p, r, lid); 685 uasm_il_b(p, r, lid);
675 } 686 }
676 if (scratch_reg > 0) 687 if (scratch_reg >= 0)
677 UASM_i_MFC0(p, 1, 31, scratch_reg); 688 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
678 else 689 else
679 UASM_i_LW(p, 1, scratchpad_offset(0), 0); 690 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
680 } else { 691 } else {
@@ -817,7 +828,7 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
817#ifdef CONFIG_MIPS_PGD_C0_CONTEXT 828#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
818 if (pgd_reg != -1) { 829 if (pgd_reg != -1) {
819 /* pgd is in pgd_reg */ 830 /* pgd is in pgd_reg */
820 UASM_i_MFC0(p, ptr, 31, pgd_reg); 831 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
821 } else { 832 } else {
822 /* 833 /*
823 * &pgd << 11 stored in CONTEXT [23..63]. 834 * &pgd << 11 stored in CONTEXT [23..63].
@@ -929,8 +940,8 @@ build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
929 uasm_i_jr(p, ptr); 940 uasm_i_jr(p, ptr);
930 941
931 if (mode == refill_scratch) { 942 if (mode == refill_scratch) {
932 if (scratch_reg > 0) 943 if (scratch_reg >= 0)
933 UASM_i_MFC0(p, 1, 31, scratch_reg); 944 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
934 else 945 else
935 UASM_i_LW(p, 1, scratchpad_offset(0), 0); 946 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
936 } else { 947 } else {
@@ -961,7 +972,7 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
961 uasm_i_srl(p, ptr, ptr, 19); 972 uasm_i_srl(p, ptr, ptr, 19);
962#else 973#else
963 /* 974 /*
964 * smp_processor_id() << 3 is stored in CONTEXT. 975 * smp_processor_id() << 2 is stored in CONTEXT.
965 */ 976 */
966 uasm_i_mfc0(p, ptr, C0_CONTEXT); 977 uasm_i_mfc0(p, ptr, C0_CONTEXT);
967 UASM_i_LA_mostly(p, tmp, pgdc); 978 UASM_i_LA_mostly(p, tmp, pgdc);
@@ -1096,7 +1107,7 @@ struct mips_huge_tlb_info {
1096static struct mips_huge_tlb_info __cpuinit 1107static struct mips_huge_tlb_info __cpuinit
1097build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, 1108build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
1098 struct uasm_reloc **r, unsigned int tmp, 1109 struct uasm_reloc **r, unsigned int tmp,
1099 unsigned int ptr, int c0_scratch) 1110 unsigned int ptr, int c0_scratch_reg)
1100{ 1111{
1101 struct mips_huge_tlb_info rv; 1112 struct mips_huge_tlb_info rv;
1102 unsigned int even, odd; 1113 unsigned int even, odd;
@@ -1110,12 +1121,12 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
1110 UASM_i_MFC0(p, tmp, C0_BADVADDR); 1121 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1111 1122
1112 if (pgd_reg != -1) 1123 if (pgd_reg != -1)
1113 UASM_i_MFC0(p, ptr, 31, pgd_reg); 1124 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
1114 else 1125 else
1115 UASM_i_MFC0(p, ptr, C0_CONTEXT); 1126 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1116 1127
1117 if (c0_scratch >= 0) 1128 if (c0_scratch_reg >= 0)
1118 UASM_i_MTC0(p, scratch, 31, c0_scratch); 1129 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1119 else 1130 else
1120 UASM_i_SW(p, scratch, scratchpad_offset(0), 0); 1131 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1121 1132
@@ -1130,14 +1141,14 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
1130 } 1141 }
1131 } else { 1142 } else {
1132 if (pgd_reg != -1) 1143 if (pgd_reg != -1)
1133 UASM_i_MFC0(p, ptr, 31, pgd_reg); 1144 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
1134 else 1145 else
1135 UASM_i_MFC0(p, ptr, C0_CONTEXT); 1146 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1136 1147
1137 UASM_i_MFC0(p, tmp, C0_BADVADDR); 1148 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1138 1149
1139 if (c0_scratch >= 0) 1150 if (c0_scratch_reg >= 0)
1140 UASM_i_MTC0(p, scratch, 31, c0_scratch); 1151 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1141 else 1152 else
1142 UASM_i_SW(p, scratch, scratchpad_offset(0), 0); 1153 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1143 1154
@@ -1242,8 +1253,8 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
1242 } 1253 }
1243 UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */ 1254 UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */
1244 1255
1245 if (c0_scratch >= 0) { 1256 if (c0_scratch_reg >= 0) {
1246 UASM_i_MFC0(p, scratch, 31, c0_scratch); 1257 UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1247 build_tlb_write_entry(p, l, r, tlb_random); 1258 build_tlb_write_entry(p, l, r, tlb_random);
1248 uasm_l_leave(l, *p); 1259 uasm_l_leave(l, *p);
1249 rv.restore_scratch = 1; 1260 rv.restore_scratch = 1;
@@ -1286,7 +1297,7 @@ static void __cpuinit build_r4000_tlb_refill_handler(void)
1286 memset(relocs, 0, sizeof(relocs)); 1297 memset(relocs, 0, sizeof(relocs));
1287 memset(final_handler, 0, sizeof(final_handler)); 1298 memset(final_handler, 0, sizeof(final_handler));
1288 1299
1289 if ((scratch_reg > 0 || scratchpad_available()) && use_bbit_insns()) { 1300 if ((scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) {
1290 htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1, 1301 htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1,
1291 scratch_reg); 1302 scratch_reg);
1292 vmalloc_mode = refill_scratch; 1303 vmalloc_mode = refill_scratch;
@@ -1444,27 +1455,25 @@ static void __cpuinit build_r4000_tlb_refill_handler(void)
1444 dump_handler("r4000_tlb_refill", (u32 *)ebase, 64); 1455 dump_handler("r4000_tlb_refill", (u32 *)ebase, 64);
1445} 1456}
1446 1457
1447/* 1458extern u32 handle_tlbl[], handle_tlbl_end[];
1448 * 128 instructions for the fastpath handler is generous and should 1459extern u32 handle_tlbs[], handle_tlbs_end[];
1449 * never be exceeded. 1460extern u32 handle_tlbm[], handle_tlbm_end[];
1450 */
1451#define FASTPATH_SIZE 128
1452 1461
1453u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned;
1454u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned;
1455u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned;
1456#ifdef CONFIG_MIPS_PGD_C0_CONTEXT 1462#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
1457u32 tlbmiss_handler_setup_pgd_array[16] __cacheline_aligned; 1463extern u32 tlbmiss_handler_setup_pgd[], tlbmiss_handler_setup_pgd_end[];
1458 1464
1459static void __cpuinit build_r4000_setup_pgd(void) 1465static void __cpuinit build_r4000_setup_pgd(void)
1460{ 1466{
1461 const int a0 = 4; 1467 const int a0 = 4;
1462 const int a1 = 5; 1468 const int a1 = 5;
1463 u32 *p = tlbmiss_handler_setup_pgd_array; 1469 u32 *p = tlbmiss_handler_setup_pgd_array;
1470 const int tlbmiss_handler_setup_pgd_size =
1471 tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd;
1464 struct uasm_label *l = labels; 1472 struct uasm_label *l = labels;
1465 struct uasm_reloc *r = relocs; 1473 struct uasm_reloc *r = relocs;
1466 1474
1467 memset(tlbmiss_handler_setup_pgd_array, 0, sizeof(tlbmiss_handler_setup_pgd_array)); 1475 memset(tlbmiss_handler_setup_pgd, 0, tlbmiss_handler_setup_pgd_size *
1476 sizeof(tlbmiss_handler_setup_pgd[0]));
1468 memset(labels, 0, sizeof(labels)); 1477 memset(labels, 0, sizeof(labels));
1469 memset(relocs, 0, sizeof(relocs)); 1478 memset(relocs, 0, sizeof(relocs));
1470 1479
@@ -1490,17 +1499,17 @@ static void __cpuinit build_r4000_setup_pgd(void)
1490 } else { 1499 } else {
1491 /* PGD in c0_KScratch */ 1500 /* PGD in c0_KScratch */
1492 uasm_i_jr(&p, 31); 1501 uasm_i_jr(&p, 31);
1493 UASM_i_MTC0(&p, a0, 31, pgd_reg); 1502 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
1494 } 1503 }
1495 if (p - tlbmiss_handler_setup_pgd_array > ARRAY_SIZE(tlbmiss_handler_setup_pgd_array)) 1504 if (p >= tlbmiss_handler_setup_pgd_end)
1496 panic("tlbmiss_handler_setup_pgd_array space exceeded"); 1505 panic("tlbmiss_handler_setup_pgd space exceeded");
1506
1497 uasm_resolve_relocs(relocs, labels); 1507 uasm_resolve_relocs(relocs, labels);
1498 pr_debug("Wrote tlbmiss_handler_setup_pgd_array (%u instructions).\n", 1508 pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n",
1499 (unsigned int)(p - tlbmiss_handler_setup_pgd_array)); 1509 (unsigned int)(p - tlbmiss_handler_setup_pgd));
1500 1510
1501 dump_handler("tlbmiss_handler", 1511 dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd,
1502 tlbmiss_handler_setup_pgd_array, 1512 tlbmiss_handler_setup_pgd_size);
1503 ARRAY_SIZE(tlbmiss_handler_setup_pgd_array));
1504} 1513}
1505#endif 1514#endif
1506 1515
@@ -1745,10 +1754,11 @@ build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
1745static void __cpuinit build_r3000_tlb_load_handler(void) 1754static void __cpuinit build_r3000_tlb_load_handler(void)
1746{ 1755{
1747 u32 *p = handle_tlbl; 1756 u32 *p = handle_tlbl;
1757 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl;
1748 struct uasm_label *l = labels; 1758 struct uasm_label *l = labels;
1749 struct uasm_reloc *r = relocs; 1759 struct uasm_reloc *r = relocs;
1750 1760
1751 memset(handle_tlbl, 0, sizeof(handle_tlbl)); 1761 memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0]));
1752 memset(labels, 0, sizeof(labels)); 1762 memset(labels, 0, sizeof(labels));
1753 memset(relocs, 0, sizeof(relocs)); 1763 memset(relocs, 0, sizeof(relocs));
1754 1764
@@ -1762,23 +1772,24 @@ static void __cpuinit build_r3000_tlb_load_handler(void)
1762 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 1772 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1763 uasm_i_nop(&p); 1773 uasm_i_nop(&p);
1764 1774
1765 if ((p - handle_tlbl) > FASTPATH_SIZE) 1775 if (p >= handle_tlbl_end)
1766 panic("TLB load handler fastpath space exceeded"); 1776 panic("TLB load handler fastpath space exceeded");
1767 1777
1768 uasm_resolve_relocs(relocs, labels); 1778 uasm_resolve_relocs(relocs, labels);
1769 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", 1779 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1770 (unsigned int)(p - handle_tlbl)); 1780 (unsigned int)(p - handle_tlbl));
1771 1781
1772 dump_handler("r3000_tlb_load", handle_tlbl, ARRAY_SIZE(handle_tlbl)); 1782 dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_size);
1773} 1783}
1774 1784
1775static void __cpuinit build_r3000_tlb_store_handler(void) 1785static void __cpuinit build_r3000_tlb_store_handler(void)
1776{ 1786{
1777 u32 *p = handle_tlbs; 1787 u32 *p = handle_tlbs;
1788 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs;
1778 struct uasm_label *l = labels; 1789 struct uasm_label *l = labels;
1779 struct uasm_reloc *r = relocs; 1790 struct uasm_reloc *r = relocs;
1780 1791
1781 memset(handle_tlbs, 0, sizeof(handle_tlbs)); 1792 memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0]));
1782 memset(labels, 0, sizeof(labels)); 1793 memset(labels, 0, sizeof(labels));
1783 memset(relocs, 0, sizeof(relocs)); 1794 memset(relocs, 0, sizeof(relocs));
1784 1795
@@ -1792,23 +1803,24 @@ static void __cpuinit build_r3000_tlb_store_handler(void)
1792 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1803 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1793 uasm_i_nop(&p); 1804 uasm_i_nop(&p);
1794 1805
1795 if ((p - handle_tlbs) > FASTPATH_SIZE) 1806 if (p >= handle_tlbs)
1796 panic("TLB store handler fastpath space exceeded"); 1807 panic("TLB store handler fastpath space exceeded");
1797 1808
1798 uasm_resolve_relocs(relocs, labels); 1809 uasm_resolve_relocs(relocs, labels);
1799 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", 1810 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1800 (unsigned int)(p - handle_tlbs)); 1811 (unsigned int)(p - handle_tlbs));
1801 1812
1802 dump_handler("r3000_tlb_store", handle_tlbs, ARRAY_SIZE(handle_tlbs)); 1813 dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_size);
1803} 1814}
1804 1815
1805static void __cpuinit build_r3000_tlb_modify_handler(void) 1816static void __cpuinit build_r3000_tlb_modify_handler(void)
1806{ 1817{
1807 u32 *p = handle_tlbm; 1818 u32 *p = handle_tlbm;
1819 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm;
1808 struct uasm_label *l = labels; 1820 struct uasm_label *l = labels;
1809 struct uasm_reloc *r = relocs; 1821 struct uasm_reloc *r = relocs;
1810 1822
1811 memset(handle_tlbm, 0, sizeof(handle_tlbm)); 1823 memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0]));
1812 memset(labels, 0, sizeof(labels)); 1824 memset(labels, 0, sizeof(labels));
1813 memset(relocs, 0, sizeof(relocs)); 1825 memset(relocs, 0, sizeof(relocs));
1814 1826
@@ -1822,14 +1834,14 @@ static void __cpuinit build_r3000_tlb_modify_handler(void)
1822 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1834 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1823 uasm_i_nop(&p); 1835 uasm_i_nop(&p);
1824 1836
1825 if ((p - handle_tlbm) > FASTPATH_SIZE) 1837 if (p >= handle_tlbm_end)
1826 panic("TLB modify handler fastpath space exceeded"); 1838 panic("TLB modify handler fastpath space exceeded");
1827 1839
1828 uasm_resolve_relocs(relocs, labels); 1840 uasm_resolve_relocs(relocs, labels);
1829 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", 1841 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
1830 (unsigned int)(p - handle_tlbm)); 1842 (unsigned int)(p - handle_tlbm));
1831 1843
1832 dump_handler("r3000_tlb_modify", handle_tlbm, ARRAY_SIZE(handle_tlbm)); 1844 dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_size);
1833} 1845}
1834#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ 1846#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
1835 1847
@@ -1893,11 +1905,12 @@ build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l,
1893static void __cpuinit build_r4000_tlb_load_handler(void) 1905static void __cpuinit build_r4000_tlb_load_handler(void)
1894{ 1906{
1895 u32 *p = handle_tlbl; 1907 u32 *p = handle_tlbl;
1908 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl;
1896 struct uasm_label *l = labels; 1909 struct uasm_label *l = labels;
1897 struct uasm_reloc *r = relocs; 1910 struct uasm_reloc *r = relocs;
1898 struct work_registers wr; 1911 struct work_registers wr;
1899 1912
1900 memset(handle_tlbl, 0, sizeof(handle_tlbl)); 1913 memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0]));
1901 memset(labels, 0, sizeof(labels)); 1914 memset(labels, 0, sizeof(labels));
1902 memset(relocs, 0, sizeof(relocs)); 1915 memset(relocs, 0, sizeof(relocs));
1903 1916
@@ -1935,6 +1948,19 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
1935 uasm_i_nop(&p); 1948 uasm_i_nop(&p);
1936 1949
1937 uasm_i_tlbr(&p); 1950 uasm_i_tlbr(&p);
1951
1952 switch (current_cpu_type()) {
1953 default:
1954 if (cpu_has_mips_r2) {
1955 uasm_i_ehb(&p);
1956
1957 case CPU_CAVIUM_OCTEON:
1958 case CPU_CAVIUM_OCTEON_PLUS:
1959 case CPU_CAVIUM_OCTEON2:
1960 break;
1961 }
1962 }
1963
1938 /* Examine entrylo 0 or 1 based on ptr. */ 1964 /* Examine entrylo 0 or 1 based on ptr. */
1939 if (use_bbit_insns()) { 1965 if (use_bbit_insns()) {
1940 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); 1966 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
@@ -1989,6 +2015,19 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
1989 uasm_i_nop(&p); 2015 uasm_i_nop(&p);
1990 2016
1991 uasm_i_tlbr(&p); 2017 uasm_i_tlbr(&p);
2018
2019 switch (current_cpu_type()) {
2020 default:
2021 if (cpu_has_mips_r2) {
2022 uasm_i_ehb(&p);
2023
2024 case CPU_CAVIUM_OCTEON:
2025 case CPU_CAVIUM_OCTEON_PLUS:
2026 case CPU_CAVIUM_OCTEON2:
2027 break;
2028 }
2029 }
2030
1992 /* Examine entrylo 0 or 1 based on ptr. */ 2031 /* Examine entrylo 0 or 1 based on ptr. */
1993 if (use_bbit_insns()) { 2032 if (use_bbit_insns()) {
1994 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); 2033 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
@@ -2036,24 +2075,25 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
2036 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 2075 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
2037 uasm_i_nop(&p); 2076 uasm_i_nop(&p);
2038 2077
2039 if ((p - handle_tlbl) > FASTPATH_SIZE) 2078 if (p >= handle_tlbl_end)
2040 panic("TLB load handler fastpath space exceeded"); 2079 panic("TLB load handler fastpath space exceeded");
2041 2080
2042 uasm_resolve_relocs(relocs, labels); 2081 uasm_resolve_relocs(relocs, labels);
2043 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", 2082 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
2044 (unsigned int)(p - handle_tlbl)); 2083 (unsigned int)(p - handle_tlbl));
2045 2084
2046 dump_handler("r4000_tlb_load", handle_tlbl, ARRAY_SIZE(handle_tlbl)); 2085 dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_size);
2047} 2086}
2048 2087
2049static void __cpuinit build_r4000_tlb_store_handler(void) 2088static void __cpuinit build_r4000_tlb_store_handler(void)
2050{ 2089{
2051 u32 *p = handle_tlbs; 2090 u32 *p = handle_tlbs;
2091 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs;
2052 struct uasm_label *l = labels; 2092 struct uasm_label *l = labels;
2053 struct uasm_reloc *r = relocs; 2093 struct uasm_reloc *r = relocs;
2054 struct work_registers wr; 2094 struct work_registers wr;
2055 2095
2056 memset(handle_tlbs, 0, sizeof(handle_tlbs)); 2096 memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0]));
2057 memset(labels, 0, sizeof(labels)); 2097 memset(labels, 0, sizeof(labels));
2058 memset(relocs, 0, sizeof(relocs)); 2098 memset(relocs, 0, sizeof(relocs));
2059 2099
@@ -2090,24 +2130,25 @@ static void __cpuinit build_r4000_tlb_store_handler(void)
2090 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 2130 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2091 uasm_i_nop(&p); 2131 uasm_i_nop(&p);
2092 2132
2093 if ((p - handle_tlbs) > FASTPATH_SIZE) 2133 if (p >= handle_tlbs_end)
2094 panic("TLB store handler fastpath space exceeded"); 2134 panic("TLB store handler fastpath space exceeded");
2095 2135
2096 uasm_resolve_relocs(relocs, labels); 2136 uasm_resolve_relocs(relocs, labels);
2097 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", 2137 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
2098 (unsigned int)(p - handle_tlbs)); 2138 (unsigned int)(p - handle_tlbs));
2099 2139
2100 dump_handler("r4000_tlb_store", handle_tlbs, ARRAY_SIZE(handle_tlbs)); 2140 dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_size);
2101} 2141}
2102 2142
2103static void __cpuinit build_r4000_tlb_modify_handler(void) 2143static void __cpuinit build_r4000_tlb_modify_handler(void)
2104{ 2144{
2105 u32 *p = handle_tlbm; 2145 u32 *p = handle_tlbm;
2146 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm;
2106 struct uasm_label *l = labels; 2147 struct uasm_label *l = labels;
2107 struct uasm_reloc *r = relocs; 2148 struct uasm_reloc *r = relocs;
2108 struct work_registers wr; 2149 struct work_registers wr;
2109 2150
2110 memset(handle_tlbm, 0, sizeof(handle_tlbm)); 2151 memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0]));
2111 memset(labels, 0, sizeof(labels)); 2152 memset(labels, 0, sizeof(labels));
2112 memset(relocs, 0, sizeof(relocs)); 2153 memset(relocs, 0, sizeof(relocs));
2113 2154
@@ -2145,14 +2186,28 @@ static void __cpuinit build_r4000_tlb_modify_handler(void)
2145 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 2186 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2146 uasm_i_nop(&p); 2187 uasm_i_nop(&p);
2147 2188
2148 if ((p - handle_tlbm) > FASTPATH_SIZE) 2189 if (p >= handle_tlbm_end)
2149 panic("TLB modify handler fastpath space exceeded"); 2190 panic("TLB modify handler fastpath space exceeded");
2150 2191
2151 uasm_resolve_relocs(relocs, labels); 2192 uasm_resolve_relocs(relocs, labels);
2152 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", 2193 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
2153 (unsigned int)(p - handle_tlbm)); 2194 (unsigned int)(p - handle_tlbm));
2154 2195
2155 dump_handler("r4000_tlb_modify", handle_tlbm, ARRAY_SIZE(handle_tlbm)); 2196 dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_size);
2197}
2198
2199static void __cpuinit flush_tlb_handlers(void)
2200{
2201 local_flush_icache_range((unsigned long)handle_tlbl,
2202 (unsigned long)handle_tlbl_end);
2203 local_flush_icache_range((unsigned long)handle_tlbs,
2204 (unsigned long)handle_tlbs_end);
2205 local_flush_icache_range((unsigned long)handle_tlbm,
2206 (unsigned long)handle_tlbm_end);
2207#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
2208 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd,
2209 (unsigned long)tlbmiss_handler_setup_pgd_end);
2210#endif
2156} 2211}
2157 2212
2158void __cpuinit build_tlb_refill_handler(void) 2213void __cpuinit build_tlb_refill_handler(void)
@@ -2187,6 +2242,7 @@ void __cpuinit build_tlb_refill_handler(void)
2187 build_r3000_tlb_load_handler(); 2242 build_r3000_tlb_load_handler();
2188 build_r3000_tlb_store_handler(); 2243 build_r3000_tlb_store_handler();
2189 build_r3000_tlb_modify_handler(); 2244 build_r3000_tlb_modify_handler();
2245 flush_tlb_handlers();
2190 run_once++; 2246 run_once++;
2191 } 2247 }
2192#else 2248#else
@@ -2214,23 +2270,10 @@ void __cpuinit build_tlb_refill_handler(void)
2214 build_r4000_tlb_modify_handler(); 2270 build_r4000_tlb_modify_handler();
2215 if (!cpu_has_local_ebase) 2271 if (!cpu_has_local_ebase)
2216 build_r4000_tlb_refill_handler(); 2272 build_r4000_tlb_refill_handler();
2273 flush_tlb_handlers();
2217 run_once++; 2274 run_once++;
2218 } 2275 }
2219 if (cpu_has_local_ebase) 2276 if (cpu_has_local_ebase)
2220 build_r4000_tlb_refill_handler(); 2277 build_r4000_tlb_refill_handler();
2221 } 2278 }
2222} 2279}
2223
2224void __cpuinit flush_tlb_handlers(void)
2225{
2226 local_flush_icache_range((unsigned long)handle_tlbl,
2227 (unsigned long)handle_tlbl + sizeof(handle_tlbl));
2228 local_flush_icache_range((unsigned long)handle_tlbs,
2229 (unsigned long)handle_tlbs + sizeof(handle_tlbs));
2230 local_flush_icache_range((unsigned long)handle_tlbm,
2231 (unsigned long)handle_tlbm + sizeof(handle_tlbm));
2232#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
2233 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd_array,
2234 (unsigned long)tlbmiss_handler_setup_pgd_array + sizeof(handle_tlbm));
2235#endif
2236}
diff --git a/arch/mips/mti-malta/Makefile b/arch/mips/mti-malta/Makefile
index 0388fc8b5613..72fdedbf76db 100644
--- a/arch/mips/mti-malta/Makefile
+++ b/arch/mips/mti-malta/Makefile
@@ -10,7 +10,6 @@ obj-y := malta-amon.o malta-display.o malta-init.o \
10 malta-reset.o malta-setup.o malta-time.o 10 malta-reset.o malta-setup.o malta-time.o
11 11
12obj-$(CONFIG_EARLY_PRINTK) += malta-console.o 12obj-$(CONFIG_EARLY_PRINTK) += malta-console.o
13obj-$(CONFIG_PCI) += malta-pci.o
14 13
15# FIXME FIXME FIXME 14# FIXME FIXME FIXME
16obj-$(CONFIG_MIPS_MT_SMTC) += malta-smtc.o 15obj-$(CONFIG_MIPS_MT_SMTC) += malta-smtc.o
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index 0a1339ac3ec8..c69da3734699 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -422,8 +422,10 @@ static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
422 */ 422 */
423int __init gcmp_probe(unsigned long addr, unsigned long size) 423int __init gcmp_probe(unsigned long addr, unsigned long size)
424{ 424{
425 if (mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) { 425 if ((mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) &&
426 (mips_revision_sconid != MIPS_REVISION_SCON_GT64120)) {
426 gcmp_present = 0; 427 gcmp_present = 0;
428 pr_debug("GCMP NOT present\n");
427 return gcmp_present; 429 return gcmp_present;
428 } 430 }
429 431
diff --git a/arch/mips/mti-malta/malta-reset.c b/arch/mips/mti-malta/malta-reset.c
index 329420536241..d627d4b2b47f 100644
--- a/arch/mips/mti-malta/malta-reset.c
+++ b/arch/mips/mti-malta/malta-reset.c
@@ -1,33 +1,18 @@
1/* 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
2 * Carsten Langgaard, carstenl@mips.com 6 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. 7 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 * Reset the MIPS boards.
23 *
24 */ 8 */
25#include <linux/init.h> 9#include <linux/io.h>
26#include <linux/pm.h> 10#include <linux/pm.h>
27 11
28#include <asm/io.h>
29#include <asm/reboot.h> 12#include <asm/reboot.h>
30#include <asm/mips-boards/generic.h> 13
14#define SOFTRES_REG 0x1f000500
15#define GORESET 0x42
31 16
32static void mips_machine_restart(char *command) 17static void mips_machine_restart(char *command)
33{ 18{
@@ -45,7 +30,6 @@ static void mips_machine_halt(void)
45 __raw_writel(GORESET, softres_reg); 30 __raw_writel(GORESET, softres_reg);
46} 31}
47 32
48
49static int __init mips_reboot_setup(void) 33static int __init mips_reboot_setup(void)
50{ 34{
51 _machine_restart = mips_machine_restart; 35 _machine_restart = mips_machine_restart;
@@ -54,5 +38,4 @@ static int __init mips_reboot_setup(void)
54 38
55 return 0; 39 return 0;
56} 40}
57
58arch_initcall(mips_reboot_setup); 41arch_initcall(mips_reboot_setup);
diff --git a/arch/mips/mti-sead3/sead3-reset.c b/arch/mips/mti-sead3/sead3-reset.c
index 20475c5e7b9c..e6fb24414a70 100644
--- a/arch/mips/mti-sead3/sead3-reset.c
+++ b/arch/mips/mti-sead3/sead3-reset.c
@@ -9,7 +9,9 @@
9#include <linux/pm.h> 9#include <linux/pm.h>
10 10
11#include <asm/reboot.h> 11#include <asm/reboot.h>
12#include <asm/mips-boards/generic.h> 12
13#define SOFTRES_REG 0x1f000050
14#define GORESET 0x4d
13 15
14static void mips_machine_restart(char *command) 16static void mips_machine_restart(char *command)
15{ 17{
@@ -35,5 +37,4 @@ static int __init mips_reboot_setup(void)
35 37
36 return 0; 38 return 0;
37} 39}
38
39arch_initcall(mips_reboot_setup); 40arch_initcall(mips_reboot_setup);
diff --git a/arch/mips/netlogic/Kconfig b/arch/mips/netlogic/Kconfig
index e0873a31ebaa..2447bf97d35a 100644
--- a/arch/mips/netlogic/Kconfig
+++ b/arch/mips/netlogic/Kconfig
@@ -51,4 +51,15 @@ endif
51config NLM_COMMON 51config NLM_COMMON
52 bool 52 bool
53 53
54config IOMMU_HELPER
55 bool
56
57config NEED_SG_DMA_LENGTH
58 bool
59
60config SWIOTLB
61 def_bool y
62 select NEED_SG_DMA_LENGTH
63 select IOMMU_HELPER
64
54endif 65endif
diff --git a/arch/mips/netlogic/common/Makefile b/arch/mips/netlogic/common/Makefile
index 291372a086f5..362739d62b1d 100644
--- a/arch/mips/netlogic/common/Makefile
+++ b/arch/mips/netlogic/common/Makefile
@@ -1,3 +1,5 @@
1obj-y += irq.o time.o 1obj-y += irq.o time.o
2obj-y += nlm-dma.o
3obj-y += reset.o
2obj-$(CONFIG_SMP) += smp.o smpboot.o 4obj-$(CONFIG_SMP) += smp.o smpboot.o
3obj-$(CONFIG_EARLY_PRINTK) += earlycons.o 5obj-$(CONFIG_EARLY_PRINTK) += earlycons.o
diff --git a/arch/mips/netlogic/common/irq.c b/arch/mips/netlogic/common/irq.c
index 9f84c60bf535..73facb2b33bb 100644
--- a/arch/mips/netlogic/common/irq.c
+++ b/arch/mips/netlogic/common/irq.c
@@ -253,13 +253,12 @@ asmlinkage void plat_irq_dispatch(void)
253 253
254 node = nlm_nodeid(); 254 node = nlm_nodeid();
255 eirr = read_c0_eirr_and_eimr(); 255 eirr = read_c0_eirr_and_eimr();
256 256 if (eirr == 0)
257 i = __ilog2_u64(eirr);
258 if (i == -1)
259 return; 257 return;
260 258
259 i = __ffs64(eirr);
261 /* per-CPU IRQs don't need translation */ 260 /* per-CPU IRQs don't need translation */
262 if (eirr & PERCPU_IRQ_MASK) { 261 if (i < PIC_IRQ_BASE) {
263 do_IRQ(i); 262 do_IRQ(i);
264 return; 263 return;
265 } 264 }
diff --git a/arch/mips/netlogic/common/nlm-dma.c b/arch/mips/netlogic/common/nlm-dma.c
new file mode 100644
index 000000000000..f3d4ae87abc7
--- /dev/null
+++ b/arch/mips/netlogic/common/nlm-dma.c
@@ -0,0 +1,107 @@
1/*
2* Copyright (C) 2003-2013 Broadcom Corporation
3* All Rights Reserved
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34#include <linux/dma-mapping.h>
35#include <linux/scatterlist.h>
36#include <linux/bootmem.h>
37#include <linux/export.h>
38#include <linux/swiotlb.h>
39#include <linux/types.h>
40#include <linux/init.h>
41#include <linux/mm.h>
42
43#include <asm/bootinfo.h>
44
45static char *nlm_swiotlb;
46
47static void *nlm_dma_alloc_coherent(struct device *dev, size_t size,
48 dma_addr_t *dma_handle, gfp_t gfp, struct dma_attrs *attrs)
49{
50 void *ret;
51
52 if (dma_alloc_from_coherent(dev, size, dma_handle, &ret))
53 return ret;
54
55 /* ignore region specifiers */
56 gfp &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM);
57
58#ifdef CONFIG_ZONE_DMA32
59 if (dev->coherent_dma_mask <= DMA_BIT_MASK(32))
60 gfp |= __GFP_DMA32;
61#endif
62
63 /* Don't invoke OOM killer */
64 gfp |= __GFP_NORETRY;
65
66 return swiotlb_alloc_coherent(dev, size, dma_handle, gfp);
67}
68
69static void nlm_dma_free_coherent(struct device *dev, size_t size,
70 void *vaddr, dma_addr_t dma_handle, struct dma_attrs *attrs)
71{
72 int order = get_order(size);
73
74 if (dma_release_from_coherent(dev, order, vaddr))
75 return;
76
77 swiotlb_free_coherent(dev, size, vaddr, dma_handle);
78}
79
80struct dma_map_ops nlm_swiotlb_dma_ops = {
81 .alloc = nlm_dma_alloc_coherent,
82 .free = nlm_dma_free_coherent,
83 .map_page = swiotlb_map_page,
84 .unmap_page = swiotlb_unmap_page,
85 .map_sg = swiotlb_map_sg_attrs,
86 .unmap_sg = swiotlb_unmap_sg_attrs,
87 .sync_single_for_cpu = swiotlb_sync_single_for_cpu,
88 .sync_single_for_device = swiotlb_sync_single_for_device,
89 .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
90 .sync_sg_for_device = swiotlb_sync_sg_for_device,
91 .mapping_error = swiotlb_dma_mapping_error,
92 .dma_supported = swiotlb_dma_supported
93};
94
95void __init plat_swiotlb_setup(void)
96{
97 size_t swiotlbsize;
98 unsigned long swiotlb_nslabs;
99
100 swiotlbsize = 1 << 20; /* 1 MB for now */
101 swiotlb_nslabs = swiotlbsize >> IO_TLB_SHIFT;
102 swiotlb_nslabs = ALIGN(swiotlb_nslabs, IO_TLB_SEGSIZE);
103 swiotlbsize = swiotlb_nslabs << IO_TLB_SHIFT;
104
105 nlm_swiotlb = alloc_bootmem_low_pages(swiotlbsize);
106 swiotlb_init_with_tbl(nlm_swiotlb, swiotlb_nslabs, 1);
107}
diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S
new file mode 100644
index 000000000000..adb18288a6c0
--- /dev/null
+++ b/arch/mips/netlogic/common/reset.S
@@ -0,0 +1,230 @@
1/*
2 * Copyright 2003-2013 Broadcom Corporation.
3 * All Rights Reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/init.h>
36
37#include <asm/asm.h>
38#include <asm/asm-offsets.h>
39#include <asm/regdef.h>
40#include <asm/mipsregs.h>
41#include <asm/stackframe.h>
42#include <asm/asmmacro.h>
43#include <asm/addrspace.h>
44
45#include <asm/netlogic/common.h>
46
47#include <asm/netlogic/xlp-hal/iomap.h>
48#include <asm/netlogic/xlp-hal/xlp.h>
49#include <asm/netlogic/xlp-hal/sys.h>
50#include <asm/netlogic/xlp-hal/cpucontrol.h>
51
52#define CP0_EBASE $15
53#define SYS_CPU_COHERENT_BASE(node) CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \
54 XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \
55 SYS_CPU_NONCOHERENT_MODE * 4
56
57/* Enable XLP features and workarounds in the LSU */
58.macro xlp_config_lsu
59 li t0, LSU_DEFEATURE
60 mfcr t1, t0
61
62 lui t2, 0xc080 /* SUE, Enable Unaligned Access, L2HPE */
63 or t1, t1, t2
64 mtcr t1, t0
65
66 li t0, ICU_DEFEATURE
67 mfcr t1, t0
68 ori t1, 0x1000 /* Enable Icache partitioning */
69 mtcr t1, t0
70
71 li t0, SCHED_DEFEATURE
72 lui t1, 0x0100 /* Disable BRU accepting ALU ops */
73 mtcr t1, t0
74.endm
75
76/*
77 * Low level flush for L1D cache on XLP, the normal cache ops does
78 * not do the complete and correct cache flush.
79 */
80.macro xlp_flush_l1_dcache
81 li t0, LSU_DEBUG_DATA0
82 li t1, LSU_DEBUG_ADDR
83 li t2, 0 /* index */
84 li t3, 0x1000 /* loop count */
851:
86 sll v0, t2, 5
87 mtcr zero, t0
88 ori v1, v0, 0x3 /* way0 | write_enable | write_active */
89 mtcr v1, t1
902:
91 mfcr v1, t1
92 andi v1, 0x1 /* wait for write_active == 0 */
93 bnez v1, 2b
94 nop
95 mtcr zero, t0
96 ori v1, v0, 0x7 /* way1 | write_enable | write_active */
97 mtcr v1, t1
983:
99 mfcr v1, t1
100 andi v1, 0x1 /* wait for write_active == 0 */
101 bnez v1, 3b
102 nop
103 addi t2, 1
104 bne t3, t2, 1b
105 nop
106.endm
107
108/*
109 * nlm_reset_entry will be copied to the reset entry point for
110 * XLR and XLP. The XLP cores start here when they are woken up. This
111 * is also the NMI entry point.
112 *
113 * We use scratch reg 6/7 to save k0/k1 and check for NMI first.
114 *
115 * The data corresponding to reset/NMI is stored at RESET_DATA_PHYS
116 * location, this will have the thread mask (used when core is woken up)
117 * and the current NMI handler in case we reached here for an NMI.
118 *
119 * When a core or thread is newly woken up, it marks itself ready and
120 * loops in a 'wait'. When the CPU really needs waking up, we send an NMI
121 * IPI to it, with the NMI handler set to prom_boot_secondary_cpus
122 */
123 .set noreorder
124 .set noat
125 .set arch=xlr /* for mfcr/mtcr, XLR is sufficient */
126
127FEXPORT(nlm_reset_entry)
128 dmtc0 k0, $22, 6
129 dmtc0 k1, $22, 7
130 mfc0 k0, CP0_STATUS
131 li k1, 0x80000
132 and k1, k0, k1
133 beqz k1, 1f /* go to real reset entry */
134 nop
135 li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */
136 ld k0, BOOT_NMI_HANDLER(k1)
137 jr k0
138 nop
139
1401: /* Entry point on core wakeup */
141 mfc0 t0, CP0_EBASE, 1
142 mfc0 t1, CP0_EBASE, 1
143 srl t1, 5
144 andi t1, 0x3 /* t1 <- node */
145 li t2, 0x40000
146 mul t3, t2, t1 /* t3 = node * 0x40000 */
147 srl t0, t0, 2
148 and t0, t0, 0x7 /* t0 <- core */
149 li t1, 0x1
150 sll t0, t1, t0
151 nor t0, t0, zero /* t0 <- ~(1 << core) */
152 li t2, SYS_CPU_COHERENT_BASE(0)
153 add t2, t2, t3 /* t2 <- SYS offset for node */
154 lw t1, 0(t2)
155 and t1, t1, t0
156 sw t1, 0(t2)
157
158 /* read back to ensure complete */
159 lw t1, 0(t2)
160 sync
161
162 /* Configure LSU on Non-0 Cores. */
163 xlp_config_lsu
164 /* FALL THROUGH */
165
166/*
167 * Wake up sibling threads from the initial thread in
168 * a core.
169 */
170EXPORT(nlm_boot_siblings)
171 /* core L1D flush before enable threads */
172 xlp_flush_l1_dcache
173 /* Enable hw threads by writing to MAP_THREADMODE of the core */
174 li t0, CKSEG1ADDR(RESET_DATA_PHYS)
175 lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
176 li t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE)
177 mfcr t2, t0
178 or t2, t2, t1
179 mtcr t2, t0
180
181 /*
182 * The new hardware thread starts at the next instruction
183 * For all the cases other than core 0 thread 0, we will
184 * jump to the secondary wait function.
185 */
186 mfc0 v0, CP0_EBASE, 1
187 andi v0, 0x3ff /* v0 <- node/core */
188
189 beqz v0, 4f /* boot cpu (cpuid == 0)? */
190 nop
191
192 /* setup status reg */
193 move t1, zero
194#ifdef CONFIG_64BIT
195 ori t1, ST0_KX
196#endif
197 mtc0 t1, CP0_STATUS
198
199 /* mark CPU ready, careful here, previous mtcr trashed registers */
200 li t3, CKSEG1ADDR(RESET_DATA_PHYS)
201 ADDIU t1, t3, BOOT_CPU_READY
202 sll v1, v0, 2
203 PTR_ADDU t1, v1
204 li t2, 1
205 sw t2, 0(t1)
206 /* Wait until NMI hits */
2073: wait
208 b 3b
209 nop
210
211 /*
212 * For the boot CPU, we have to restore registers and
213 * return
214 */
2154: dmfc0 t0, $4, 2 /* restore SP from UserLocal */
216 li t1, 0xfadebeef
217 dmtc0 t1, $4, 2 /* restore SP from UserLocal */
218 PTR_SUBU sp, t0, PT_SIZE
219 RESTORE_ALL
220 jr ra
221 nop
222EXPORT(nlm_reset_entry_end)
223
224LEAF(nlm_init_boot_cpu)
225#ifdef CONFIG_CPU_XLP
226 xlp_config_lsu
227#endif
228 jr ra
229 nop
230END(nlm_init_boot_cpu)
diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c
index ffba52489bef..885d293b61da 100644
--- a/arch/mips/netlogic/common/smp.c
+++ b/arch/mips/netlogic/common/smp.c
@@ -145,7 +145,6 @@ void nlm_cpus_done(void)
145 * Boot all other cpus in the system, initialize them, and bring them into 145 * Boot all other cpus in the system, initialize them, and bring them into
146 * the boot function 146 * the boot function
147 */ 147 */
148int nlm_cpu_ready[NR_CPUS];
149unsigned long nlm_next_gp; 148unsigned long nlm_next_gp;
150unsigned long nlm_next_sp; 149unsigned long nlm_next_sp;
151static cpumask_t phys_cpu_present_mask; 150static cpumask_t phys_cpu_present_mask;
@@ -168,6 +167,7 @@ void __init nlm_smp_setup(void)
168{ 167{
169 unsigned int boot_cpu; 168 unsigned int boot_cpu;
170 int num_cpus, i, ncore; 169 int num_cpus, i, ncore;
170 volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY);
171 char buf[64]; 171 char buf[64];
172 172
173 boot_cpu = hard_smp_processor_id(); 173 boot_cpu = hard_smp_processor_id();
@@ -181,10 +181,10 @@ void __init nlm_smp_setup(void)
181 num_cpus = 1; 181 num_cpus = 1;
182 for (i = 0; i < NR_CPUS; i++) { 182 for (i = 0; i < NR_CPUS; i++) {
183 /* 183 /*
184 * nlm_cpu_ready array is not set for the boot_cpu, 184 * cpu_ready array is not set for the boot_cpu,
185 * it is only set for ASPs (see smpboot.S) 185 * it is only set for ASPs (see smpboot.S)
186 */ 186 */
187 if (nlm_cpu_ready[i]) { 187 if (cpu_ready[i]) {
188 cpumask_set_cpu(i, &phys_cpu_present_mask); 188 cpumask_set_cpu(i, &phys_cpu_present_mask);
189 __cpu_number_map[i] = num_cpus; 189 __cpu_number_map[i] = num_cpus;
190 __cpu_logical_map[num_cpus] = i; 190 __cpu_logical_map[num_cpus] = i;
@@ -254,21 +254,15 @@ unsupp:
254 254
255int __cpuinit nlm_wakeup_secondary_cpus(void) 255int __cpuinit nlm_wakeup_secondary_cpus(void)
256{ 256{
257 unsigned long reset_vec; 257 u32 *reset_data;
258 char *reset_data;
259 int threadmode; 258 int threadmode;
260 259
261 /* Update reset entry point with CPU init code */
262 reset_vec = CKSEG1ADDR(RESET_VEC_PHYS);
263 memcpy((void *)reset_vec, (void *)nlm_reset_entry,
264 (nlm_reset_entry_end - nlm_reset_entry));
265
266 /* verify the mask and setup core config variables */ 260 /* verify the mask and setup core config variables */
267 threadmode = nlm_parse_cpumask(&nlm_cpumask); 261 threadmode = nlm_parse_cpumask(&nlm_cpumask);
268 262
269 /* Setup CPU init parameters */ 263 /* Setup CPU init parameters */
270 reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS); 264 reset_data = nlm_get_boot_data(BOOT_THREAD_MODE);
271 *(int *)(reset_data + BOOT_THREAD_MODE) = threadmode; 265 *reset_data = threadmode;
272 266
273#ifdef CONFIG_CPU_XLP 267#ifdef CONFIG_CPU_XLP
274 xlp_wakeup_secondary_cpus(); 268 xlp_wakeup_secondary_cpus();
diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S
index 026517488584..528c46c5a170 100644
--- a/arch/mips/netlogic/common/smpboot.S
+++ b/arch/mips/netlogic/common/smpboot.S
@@ -50,197 +50,12 @@
50#include <asm/netlogic/xlp-hal/cpucontrol.h> 50#include <asm/netlogic/xlp-hal/cpucontrol.h>
51 51
52#define CP0_EBASE $15 52#define CP0_EBASE $15
53#define SYS_CPU_COHERENT_BASE(node) CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \
54 XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \
55 SYS_CPU_NONCOHERENT_MODE * 4
56
57#define XLP_AX_WORKAROUND /* enable Ax silicon workarounds */
58
59/* Enable XLP features and workarounds in the LSU */
60.macro xlp_config_lsu
61 li t0, LSU_DEFEATURE
62 mfcr t1, t0
63
64 lui t2, 0xc080 /* SUE, Enable Unaligned Access, L2HPE */
65 or t1, t1, t2
66#ifdef XLP_AX_WORKAROUND
67 li t2, ~0xe /* S1RCM */
68 and t1, t1, t2
69#endif
70 mtcr t1, t0
71
72 li t0, ICU_DEFEATURE
73 mfcr t1, t0
74 ori t1, 0x1000 /* Enable Icache partitioning */
75 mtcr t1, t0
76
77
78#ifdef XLP_AX_WORKAROUND
79 li t0, SCHED_DEFEATURE
80 lui t1, 0x0100 /* Disable BRU accepting ALU ops */
81 mtcr t1, t0
82#endif
83.endm
84
85/*
86 * This is the code that will be copied to the reset entry point for
87 * XLR and XLP. The XLP cores start here when they are woken up. This
88 * is also the NMI entry point.
89 */
90.macro xlp_flush_l1_dcache
91 li t0, LSU_DEBUG_DATA0
92 li t1, LSU_DEBUG_ADDR
93 li t2, 0 /* index */
94 li t3, 0x1000 /* loop count */
951:
96 sll v0, t2, 5
97 mtcr zero, t0
98 ori v1, v0, 0x3 /* way0 | write_enable | write_active */
99 mtcr v1, t1
1002:
101 mfcr v1, t1
102 andi v1, 0x1 /* wait for write_active == 0 */
103 bnez v1, 2b
104 nop
105 mtcr zero, t0
106 ori v1, v0, 0x7 /* way1 | write_enable | write_active */
107 mtcr v1, t1
1083:
109 mfcr v1, t1
110 andi v1, 0x1 /* wait for write_active == 0 */
111 bnez v1, 3b
112 nop
113 addi t2, 1
114 bne t3, t2, 1b
115 nop
116.endm
117
118/*
119 * The cores can come start when they are woken up. This is also the NMI
120 * entry, so check that first.
121 *
122 * The data corresponding to reset/NMI is stored at RESET_DATA_PHYS
123 * location, this will have the thread mask (used when core is woken up)
124 * and the current NMI handler in case we reached here for an NMI.
125 *
126 * When a core or thread is newly woken up, it loops in a 'wait'. When
127 * the CPU really needs waking up, we send an NMI to it, with the NMI
128 * handler set to prom_boot_secondary_cpus
129 */
130 53
131 .set noreorder 54 .set noreorder
132 .set noat 55 .set noat
133 .set arch=xlr /* for mfcr/mtcr, XLR is sufficient */ 56 .set arch=xlr /* for mfcr/mtcr, XLR is sufficient */
134
135FEXPORT(nlm_reset_entry)
136 dmtc0 k0, $22, 6
137 dmtc0 k1, $22, 7
138 mfc0 k0, CP0_STATUS
139 li k1, 0x80000
140 and k1, k0, k1
141 beqz k1, 1f /* go to real reset entry */
142 nop
143 li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */
144 ld k0, BOOT_NMI_HANDLER(k1)
145 jr k0
146 nop
147
1481: /* Entry point on core wakeup */
149 mfc0 t0, CP0_EBASE, 1
150 mfc0 t1, CP0_EBASE, 1
151 srl t1, 5
152 andi t1, 0x3 /* t1 <- node */
153 li t2, 0x40000
154 mul t3, t2, t1 /* t3 = node * 0x40000 */
155 srl t0, t0, 2
156 and t0, t0, 0x7 /* t0 <- core */
157 li t1, 0x1
158 sll t0, t1, t0
159 nor t0, t0, zero /* t0 <- ~(1 << core) */
160 li t2, SYS_CPU_COHERENT_BASE(0)
161 add t2, t2, t3 /* t2 <- SYS offset for node */
162 lw t1, 0(t2)
163 and t1, t1, t0
164 sw t1, 0(t2)
165
166 /* read back to ensure complete */
167 lw t1, 0(t2)
168 sync
169
170 /* Configure LSU on Non-0 Cores. */
171 xlp_config_lsu
172 /* FALL THROUGH */
173
174/*
175 * Wake up sibling threads from the initial thread in
176 * a core.
177 */
178EXPORT(nlm_boot_siblings)
179 /* core L1D flush before enable threads */
180 xlp_flush_l1_dcache
181 /* Enable hw threads by writing to MAP_THREADMODE of the core */
182 li t0, CKSEG1ADDR(RESET_DATA_PHYS)
183 lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
184 li t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE)
185 mfcr t2, t0
186 or t2, t2, t1
187 mtcr t2, t0
188
189 /*
190 * The new hardware thread starts at the next instruction
191 * For all the cases other than core 0 thread 0, we will
192 * jump to the secondary wait function.
193 */
194 mfc0 v0, CP0_EBASE, 1
195 andi v0, 0x3ff /* v0 <- node/core */
196
197 /* Init MMU in the first thread after changing THREAD_MODE
198 * register (Ax Errata?)
199 */
200 andi v1, v0, 0x3 /* v1 <- thread id */
201 bnez v1, 2f
202 nop
203
204 li t0, MMU_SETUP
205 li t1, 0
206 mtcr t1, t0
207 _ehb
208
2092: beqz v0, 4f /* boot cpu (cpuid == 0)? */
210 nop
211
212 /* setup status reg */
213 move t1, zero
214#ifdef CONFIG_64BIT
215 ori t1, ST0_KX
216#endif
217 mtc0 t1, CP0_STATUS
218 /* mark CPU ready */
219 PTR_LA t1, nlm_cpu_ready
220 sll v1, v0, 2
221 PTR_ADDU t1, v1
222 li t2, 1
223 sw t2, 0(t1)
224 /* Wait until NMI hits */
2253: wait
226 j 3b
227 nop
228
229 /*
230 * For the boot CPU, we have to restore registers and
231 * return
232 */
2334: dmfc0 t0, $4, 2 /* restore SP from UserLocal */
234 li t1, 0xfadebeef
235 dmtc0 t1, $4, 2 /* restore SP from UserLocal */
236 PTR_SUBU sp, t0, PT_SIZE
237 RESTORE_ALL
238 jr ra
239 nop
240EXPORT(nlm_reset_entry_end)
241 57
242FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */ 58FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */
243 xlp_config_lsu
244 dmtc0 sp, $4, 2 /* SP saved in UserLocal */ 59 dmtc0 sp, $4, 2 /* SP saved in UserLocal */
245 SAVE_ALL 60 SAVE_ALL
246 sync 61 sync
@@ -294,8 +109,9 @@ NESTED(nlm_rmiboot_preboot, 16, sp)
294 andi t2, t0, 0x3 /* thread num */ 109 andi t2, t0, 0x3 /* thread num */
295 sll t0, 2 /* offset in cpu array */ 110 sll t0, 2 /* offset in cpu array */
296 111
297 PTR_LA t1, nlm_cpu_ready /* mark CPU ready */ 112 li t3, CKSEG1ADDR(RESET_DATA_PHYS)
298 PTR_ADDU t1, t0 113 ADDIU t1, t3, BOOT_CPU_READY
114 ADDU t1, t0
299 li t3, 1 115 li t3, 1
300 sw t3, 0(t1) 116 sw t3, 0(t1)
301 117
@@ -321,7 +137,7 @@ NESTED(nlm_rmiboot_preboot, 16, sp)
321 mtcr t1, t0 /* update core control */ 137 mtcr t1, t0 /* update core control */
322 138
3231: wait 1391: wait
324 j 1b 140 b 1b
325 nop 141 nop
326END(nlm_rmiboot_preboot) 142END(nlm_rmiboot_preboot)
327 __FINIT 143 __FINIT
diff --git a/arch/mips/netlogic/xlp/Makefile b/arch/mips/netlogic/xlp/Makefile
index a84d6ed3746c..85ac4a892ced 100644
--- a/arch/mips/netlogic/xlp/Makefile
+++ b/arch/mips/netlogic/xlp/Makefile
@@ -1,3 +1,3 @@
1obj-y += setup.o nlm_hal.o 1obj-y += setup.o nlm_hal.o cop2-ex.o dt.o
2obj-$(CONFIG_SMP) += wakeup.o 2obj-$(CONFIG_SMP) += wakeup.o
3obj-$(CONFIG_USB) += usb-init.o 3obj-$(CONFIG_USB) += usb-init.o
diff --git a/arch/mips/netlogic/xlp/cop2-ex.c b/arch/mips/netlogic/xlp/cop2-ex.c
new file mode 100644
index 000000000000..52bc5de42005
--- /dev/null
+++ b/arch/mips/netlogic/xlp/cop2-ex.c
@@ -0,0 +1,118 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2013 Broadcom Corporation.
7 *
8 * based on arch/mips/cavium-octeon/cpu.c
9 * Copyright (C) 2009 Wind River Systems,
10 * written by Ralf Baechle <ralf@linux-mips.org>
11 */
12#include <linux/init.h>
13#include <linux/irqflags.h>
14#include <linux/notifier.h>
15#include <linux/prefetch.h>
16#include <linux/sched.h>
17
18#include <asm/cop2.h>
19#include <asm/current.h>
20#include <asm/mipsregs.h>
21#include <asm/page.h>
22
23#include <asm/netlogic/mips-extns.h>
24
25/*
26 * 64 bit ops are done in inline assembly to support 32 bit
27 * compilation
28 */
29void nlm_cop2_save(struct nlm_cop2_state *r)
30{
31 asm volatile(
32 ".set push\n"
33 ".set noat\n"
34 "dmfc2 $1, $0, 0\n"
35 "sd $1, 0(%1)\n"
36 "dmfc2 $1, $0, 1\n"
37 "sd $1, 8(%1)\n"
38 "dmfc2 $1, $0, 2\n"
39 "sd $1, 16(%1)\n"
40 "dmfc2 $1, $0, 3\n"
41 "sd $1, 24(%1)\n"
42 "dmfc2 $1, $1, 0\n"
43 "sd $1, 0(%2)\n"
44 "dmfc2 $1, $1, 1\n"
45 "sd $1, 8(%2)\n"
46 "dmfc2 $1, $1, 2\n"
47 "sd $1, 16(%2)\n"
48 "dmfc2 $1, $1, 3\n"
49 "sd $1, 24(%2)\n"
50 ".set pop\n"
51 : "=m"(*r)
52 : "r"(r->tx), "r"(r->rx));
53
54 r->tx_msg_status = __read_32bit_c2_register($2, 0);
55 r->rx_msg_status = __read_32bit_c2_register($3, 0) & 0x0fffffff;
56}
57
58void nlm_cop2_restore(struct nlm_cop2_state *r)
59{
60 u32 rstat;
61
62 asm volatile(
63 ".set push\n"
64 ".set noat\n"
65 "ld $1, 0(%1)\n"
66 "dmtc2 $1, $0, 0\n"
67 "ld $1, 8(%1)\n"
68 "dmtc2 $1, $0, 1\n"
69 "ld $1, 16(%1)\n"
70 "dmtc2 $1, $0, 2\n"
71 "ld $1, 24(%1)\n"
72 "dmtc2 $1, $0, 3\n"
73 "ld $1, 0(%2)\n"
74 "dmtc2 $1, $1, 0\n"
75 "ld $1, 8(%2)\n"
76 "dmtc2 $1, $1, 1\n"
77 "ld $1, 16(%2)\n"
78 "dmtc2 $1, $1, 2\n"
79 "ld $1, 24(%2)\n"
80 "dmtc2 $1, $1, 3\n"
81 ".set pop\n"
82 : : "m"(*r), "r"(r->tx), "r"(r->rx));
83
84 __write_32bit_c2_register($2, 0, r->tx_msg_status);
85 rstat = __read_32bit_c2_register($3, 0) & 0xf0000000u;
86 __write_32bit_c2_register($3, 0, r->rx_msg_status | rstat);
87}
88
89static int nlm_cu2_call(struct notifier_block *nfb, unsigned long action,
90 void *data)
91{
92 unsigned long flags;
93 unsigned int status;
94
95 switch (action) {
96 case CU2_EXCEPTION:
97 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
98 break;
99 local_irq_save(flags);
100 KSTK_STATUS(current) |= ST0_CU2;
101 status = read_c0_status();
102 write_c0_status(status | ST0_CU2);
103 nlm_cop2_restore(&(current->thread.cp2));
104 write_c0_status(status & ~ST0_CU2);
105 local_irq_restore(flags);
106 pr_info("COP2 access enabled for pid %d (%s)\n",
107 current->pid, current->comm);
108 return NOTIFY_BAD; /* Don't call default notifier */
109 }
110
111 return NOTIFY_OK; /* Let default notifier send signals */
112}
113
114static int __init nlm_cu2_setup(void)
115{
116 return cu2_notifier(nlm_cu2_call, 0);
117}
118early_initcall(nlm_cu2_setup);
diff --git a/arch/mips/netlogic/xlp/dt.c b/arch/mips/netlogic/xlp/dt.c
new file mode 100644
index 000000000000..a15cdbb8d0bd
--- /dev/null
+++ b/arch/mips/netlogic/xlp/dt.c
@@ -0,0 +1,99 @@
1/*
2 * Copyright 2003-2013 Broadcom Corporation.
3 * All Rights Reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/bootmem.h>
37
38#include <linux/of_fdt.h>
39#include <linux/of_platform.h>
40#include <linux/of_device.h>
41
42extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[], __dtb_start[];
43
44void __init *xlp_dt_init(void *fdtp)
45{
46 if (!fdtp) {
47 switch (current_cpu_data.processor_id & 0xff00) {
48#ifdef CONFIG_DT_XLP_SVP
49 case PRID_IMP_NETLOGIC_XLP3XX:
50 fdtp = __dtb_xlp_svp_begin;
51 break;
52#endif
53#ifdef CONFIG_DT_XLP_EVP
54 case PRID_IMP_NETLOGIC_XLP8XX:
55 fdtp = __dtb_xlp_evp_begin;
56 break;
57#endif
58 default:
59 /* Pick a built-in if any, and hope for the best */
60 fdtp = __dtb_start;
61 break;
62 }
63 }
64 initial_boot_params = fdtp;
65 return fdtp;
66}
67
68void __init device_tree_init(void)
69{
70 unsigned long base, size;
71
72 if (!initial_boot_params)
73 return;
74
75 base = virt_to_phys((void *)initial_boot_params);
76 size = be32_to_cpu(initial_boot_params->totalsize);
77
78 /* Before we do anything, lets reserve the dt blob */
79 reserve_bootmem(base, size, BOOTMEM_DEFAULT);
80
81 unflatten_device_tree();
82
83 /* free the space reserved for the dt blob */
84 free_bootmem(base, size);
85}
86
87static struct of_device_id __initdata xlp_ids[] = {
88 { .compatible = "simple-bus", },
89 {},
90};
91
92int __init xlp8xx_ds_publish_devices(void)
93{
94 if (!of_have_populated_dt())
95 return 0;
96 return of_platform_bus_probe(NULL, xlp_ids, NULL);
97}
98
99device_initcall(xlp8xx_ds_publish_devices);
diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c
index eaa99d28cb8e..7b638f7be491 100644
--- a/arch/mips/netlogic/xlp/setup.c
+++ b/arch/mips/netlogic/xlp/setup.c
@@ -33,19 +33,13 @@
33 */ 33 */
34 34
35#include <linux/kernel.h> 35#include <linux/kernel.h>
36#include <linux/serial_8250.h> 36#include <linux/of_fdt.h>
37#include <linux/pm.h>
38#include <linux/bootmem.h>
39 37
40#include <asm/idle.h> 38#include <asm/idle.h>
41#include <asm/reboot.h> 39#include <asm/reboot.h>
42#include <asm/time.h> 40#include <asm/time.h>
43#include <asm/bootinfo.h> 41#include <asm/bootinfo.h>
44 42
45#include <linux/of_fdt.h>
46#include <linux/of_platform.h>
47#include <linux/of_device.h>
48
49#include <asm/netlogic/haldefs.h> 43#include <asm/netlogic/haldefs.h>
50#include <asm/netlogic/common.h> 44#include <asm/netlogic/common.h>
51 45
@@ -57,7 +51,6 @@ uint64_t nlm_io_base;
57struct nlm_soc_info nlm_nodes[NLM_NR_NODES]; 51struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
58cpumask_t nlm_cpumask = CPU_MASK_CPU0; 52cpumask_t nlm_cpumask = CPU_MASK_CPU0;
59unsigned int nlm_threads_per_core; 53unsigned int nlm_threads_per_core;
60extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[], __dtb_start[];
61 54
62static void nlm_linux_exit(void) 55static void nlm_linux_exit(void)
63{ 56{
@@ -68,41 +61,28 @@ static void nlm_linux_exit(void)
68 cpu_wait(); 61 cpu_wait();
69} 62}
70 63
71void __init plat_mem_setup(void) 64static void nlm_fixup_mem(void)
72{ 65{
73 void *fdtp; 66 const int pref_backup = 512;
67 int i;
68
69 for (i = 0; i < boot_mem_map.nr_map; i++) {
70 if (boot_mem_map.map[i].type != BOOT_MEM_RAM)
71 continue;
72 boot_mem_map.map[i].size -= pref_backup;
73 }
74}
74 75
76void __init plat_mem_setup(void)
77{
75 panic_timeout = 5; 78 panic_timeout = 5;
76 _machine_restart = (void (*)(char *))nlm_linux_exit; 79 _machine_restart = (void (*)(char *))nlm_linux_exit;
77 _machine_halt = nlm_linux_exit; 80 _machine_halt = nlm_linux_exit;
78 pm_power_off = nlm_linux_exit; 81 pm_power_off = nlm_linux_exit;
79 82
80 /* 83 /* memory and bootargs from DT */
81 * If no FDT pointer is passed in, use the built-in FDT. 84 early_init_devtree(initial_boot_params);
82 * device_tree_init() does not handle CKSEG0 pointers in 85 nlm_fixup_mem();
83 * 64-bit, so convert pointer.
84 */
85 fdtp = (void *)(long)fw_arg0;
86 if (!fdtp) {
87 switch (current_cpu_data.processor_id & 0xff00) {
88#ifdef CONFIG_DT_XLP_SVP
89 case PRID_IMP_NETLOGIC_XLP3XX:
90 fdtp = __dtb_xlp_svp_begin;
91 break;
92#endif
93#ifdef CONFIG_DT_XLP_EVP
94 case PRID_IMP_NETLOGIC_XLP8XX:
95 fdtp = __dtb_xlp_evp_begin;
96 break;
97#endif
98 default:
99 /* Pick a built-in if any, and hope for the best */
100 fdtp = __dtb_start;
101 break;
102 }
103 }
104 fdtp = phys_to_virt(__pa(fdtp));
105 early_init_devtree(fdtp);
106} 86}
107 87
108const char *get_system_type(void) 88const char *get_system_type(void)
@@ -131,9 +111,19 @@ void nlm_percpu_init(int hwcpuid)
131 111
132void __init prom_init(void) 112void __init prom_init(void)
133{ 113{
114 void *reset_vec;
115
134 nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE); 116 nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE);
117 nlm_init_boot_cpu();
135 xlp_mmu_init(); 118 xlp_mmu_init();
136 nlm_node_init(0); 119 nlm_node_init(0);
120 xlp_dt_init((void *)(long)fw_arg0);
121
122 /* Update reset entry point with CPU init code */
123 reset_vec = (void *)CKSEG1ADDR(RESET_VEC_PHYS);
124 memset(reset_vec, 0, RESET_VEC_SIZE);
125 memcpy(reset_vec, (void *)nlm_reset_entry,
126 (nlm_reset_entry_end - nlm_reset_entry));
137 127
138#ifdef CONFIG_SMP 128#ifdef CONFIG_SMP
139 cpumask_setall(&nlm_cpumask); 129 cpumask_setall(&nlm_cpumask);
@@ -145,36 +135,3 @@ void __init prom_init(void)
145 register_smp_ops(&nlm_smp_ops); 135 register_smp_ops(&nlm_smp_ops);
146#endif 136#endif
147} 137}
148
149void __init device_tree_init(void)
150{
151 unsigned long base, size;
152
153 if (!initial_boot_params)
154 return;
155
156 base = virt_to_phys((void *)initial_boot_params);
157 size = be32_to_cpu(initial_boot_params->totalsize);
158
159 /* Before we do anything, lets reserve the dt blob */
160 reserve_bootmem(base, size, BOOTMEM_DEFAULT);
161
162 unflatten_device_tree();
163
164 /* free the space reserved for the dt blob */
165 free_bootmem(base, size);
166}
167
168static struct of_device_id __initdata xlp_ids[] = {
169 { .compatible = "simple-bus", },
170 {},
171};
172
173int __init xlp8xx_ds_publish_devices(void)
174{
175 if (!of_have_populated_dt())
176 return 0;
177 return of_platform_bus_probe(NULL, xlp_ids, NULL);
178}
179
180device_initcall(xlp8xx_ds_publish_devices);
diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c
index abb3e08cc052..0cce37cbffef 100644
--- a/arch/mips/netlogic/xlp/wakeup.c
+++ b/arch/mips/netlogic/xlp/wakeup.c
@@ -77,12 +77,28 @@ static int xlp_wakeup_core(uint64_t sysbase, int node, int core)
77 return count != 0; 77 return count != 0;
78} 78}
79 79
80static int wait_for_cpus(int cpu, int bootcpu)
81{
82 volatile uint32_t *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY);
83 int i, count, notready;
84
85 count = 0x20000000;
86 do {
87 notready = nlm_threads_per_core;
88 for (i = 0; i < nlm_threads_per_core; i++)
89 if (cpu_ready[cpu + i] || cpu == bootcpu)
90 --notready;
91 } while (notready != 0 && --count > 0);
92
93 return count != 0;
94}
95
80static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask) 96static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
81{ 97{
82 struct nlm_soc_info *nodep; 98 struct nlm_soc_info *nodep;
83 uint64_t syspcibase; 99 uint64_t syspcibase;
84 uint32_t syscoremask; 100 uint32_t syscoremask;
85 int core, n, cpu, count, val; 101 int core, n, cpu;
86 102
87 for (n = 0; n < NLM_NR_NODES; n++) { 103 for (n = 0; n < NLM_NR_NODES; n++) {
88 syspcibase = nlm_get_sys_pcibase(n); 104 syspcibase = nlm_get_sys_pcibase(n);
@@ -122,11 +138,8 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
122 /* core is up */ 138 /* core is up */
123 nodep->coremask |= 1u << core; 139 nodep->coremask |= 1u << core;
124 140
125 /* spin until the first hw thread sets its ready */ 141 /* spin until the hw threads sets their ready */
126 count = 0x20000000; 142 wait_for_cpus(cpu, 0);
127 do {
128 val = *(volatile int *)&nlm_cpu_ready[cpu];
129 } while (val == 0 && --count > 0);
130 } 143 }
131 } 144 }
132} 145}
@@ -138,6 +151,7 @@ void xlp_wakeup_secondary_cpus()
138 * first wakeup core 0 threads 151 * first wakeup core 0 threads
139 */ 152 */
140 xlp_boot_core0_siblings(); 153 xlp_boot_core0_siblings();
154 wait_for_cpus(0, 0);
141 155
142 /* now get other cores out of reset */ 156 /* now get other cores out of reset */
143 xlp_enable_secondary_cores(&nlm_cpumask); 157 xlp_enable_secondary_cores(&nlm_cpumask);
diff --git a/arch/mips/netlogic/xlr/fmn.c b/arch/mips/netlogic/xlr/fmn.c
index 4d74f03de506..d428e8471eec 100644
--- a/arch/mips/netlogic/xlr/fmn.c
+++ b/arch/mips/netlogic/xlr/fmn.c
@@ -74,13 +74,13 @@ static irqreturn_t fmn_message_handler(int irq, void *data)
74 struct nlm_fmn_msg msg; 74 struct nlm_fmn_msg msg;
75 uint32_t mflags, bkt_status; 75 uint32_t mflags, bkt_status;
76 76
77 mflags = nlm_cop2_enable(); 77 mflags = nlm_cop2_enable_irqsave();
78 /* Disable message ring interrupt */ 78 /* Disable message ring interrupt */
79 nlm_fmn_setup_intr(irq, 0); 79 nlm_fmn_setup_intr(irq, 0);
80 while (1) { 80 while (1) {
81 /* 8 bkts per core, [24:31] each bit represents one bucket 81 /* 8 bkts per core, [24:31] each bit represents one bucket
82 * Bit is Zero if bucket is not empty */ 82 * Bit is Zero if bucket is not empty */
83 bkt_status = (nlm_read_c2_status() >> 24) & 0xff; 83 bkt_status = (nlm_read_c2_status0() >> 24) & 0xff;
84 if (bkt_status == 0xff) 84 if (bkt_status == 0xff)
85 break; 85 break;
86 for (bucket = 0; bucket < 8; bucket++) { 86 for (bucket = 0; bucket < 8; bucket++) {
@@ -97,16 +97,16 @@ static irqreturn_t fmn_message_handler(int irq, void *data)
97 pr_warn("No msgring handler for stnid %d\n", 97 pr_warn("No msgring handler for stnid %d\n",
98 src_stnid); 98 src_stnid);
99 else { 99 else {
100 nlm_cop2_restore(mflags); 100 nlm_cop2_disable_irqrestore(mflags);
101 hndlr->action(bucket, src_stnid, size, code, 101 hndlr->action(bucket, src_stnid, size, code,
102 &msg, hndlr->arg); 102 &msg, hndlr->arg);
103 mflags = nlm_cop2_enable(); 103 mflags = nlm_cop2_enable_irqsave();
104 } 104 }
105 } 105 }
106 }; 106 };
107 /* Enable message ring intr, to any thread in core */ 107 /* Enable message ring intr, to any thread in core */
108 nlm_fmn_setup_intr(irq, (1 << nlm_threads_per_core) - 1); 108 nlm_fmn_setup_intr(irq, (1 << nlm_threads_per_core) - 1);
109 nlm_cop2_restore(mflags); 109 nlm_cop2_disable_irqrestore(mflags);
110 return IRQ_HANDLED; 110 return IRQ_HANDLED;
111} 111}
112 112
@@ -128,7 +128,7 @@ void xlr_percpu_fmn_init(void)
128 128
129 bucket_sizes = xlr_board_fmn_config.bucket_size; 129 bucket_sizes = xlr_board_fmn_config.bucket_size;
130 cpu_fmn_info = &xlr_board_fmn_config.cpu[id]; 130 cpu_fmn_info = &xlr_board_fmn_config.cpu[id];
131 flags = nlm_cop2_enable(); 131 flags = nlm_cop2_enable_irqsave();
132 132
133 /* Setup bucket sizes for the core. */ 133 /* Setup bucket sizes for the core. */
134 nlm_write_c2_bucksize(0, bucket_sizes[id * 8 + 0]); 134 nlm_write_c2_bucksize(0, bucket_sizes[id * 8 + 0]);
@@ -166,7 +166,7 @@ void xlr_percpu_fmn_init(void)
166 166
167 /* enable FMN interrupts on this CPU */ 167 /* enable FMN interrupts on this CPU */
168 nlm_fmn_setup_intr(IRQ_FMN, (1 << nlm_threads_per_core) - 1); 168 nlm_fmn_setup_intr(IRQ_FMN, (1 << nlm_threads_per_core) - 1);
169 nlm_cop2_restore(flags); 169 nlm_cop2_disable_irqrestore(flags);
170} 170}
171 171
172 172
@@ -198,7 +198,7 @@ void nlm_setup_fmn_irq(void)
198 /* setup irq only once */ 198 /* setup irq only once */
199 setup_irq(IRQ_FMN, &fmn_irqaction); 199 setup_irq(IRQ_FMN, &fmn_irqaction);
200 200
201 flags = nlm_cop2_enable(); 201 flags = nlm_cop2_enable_irqsave();
202 nlm_fmn_setup_intr(IRQ_FMN, (1 << nlm_threads_per_core) - 1); 202 nlm_fmn_setup_intr(IRQ_FMN, (1 << nlm_threads_per_core) - 1);
203 nlm_cop2_restore(flags); 203 nlm_cop2_disable_irqrestore(flags);
204} 204}
diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c
index 89c8c1066632..214d123b79fa 100644
--- a/arch/mips/netlogic/xlr/setup.c
+++ b/arch/mips/netlogic/xlr/setup.c
@@ -196,6 +196,7 @@ void __init prom_init(void)
196{ 196{
197 int *argv, *envp; /* passed as 32 bit ptrs */ 197 int *argv, *envp; /* passed as 32 bit ptrs */
198 struct psb_info *prom_infop; 198 struct psb_info *prom_infop;
199 void *reset_vec;
199#ifdef CONFIG_SMP 200#ifdef CONFIG_SMP
200 int i; 201 int i;
201#endif 202#endif
@@ -208,6 +209,12 @@ void __init prom_init(void)
208 nlm_prom_info = *prom_infop; 209 nlm_prom_info = *prom_infop;
209 nlm_init_node(); 210 nlm_init_node();
210 211
212 /* Update reset entry point with CPU init code */
213 reset_vec = (void *)CKSEG1ADDR(RESET_VEC_PHYS);
214 memset(reset_vec, 0, RESET_VEC_SIZE);
215 memcpy(reset_vec, (void *)nlm_reset_entry,
216 (nlm_reset_entry_end - nlm_reset_entry));
217
211 nlm_early_serial_setup(); 218 nlm_early_serial_setup();
212 build_arcs_cmdline(argv); 219 build_arcs_cmdline(argv);
213 prom_add_memory(); 220 prom_add_memory();
diff --git a/arch/mips/netlogic/xlr/wakeup.c b/arch/mips/netlogic/xlr/wakeup.c
index 3ebf7411d67b..c06e4c9f0478 100644
--- a/arch/mips/netlogic/xlr/wakeup.c
+++ b/arch/mips/netlogic/xlr/wakeup.c
@@ -53,6 +53,7 @@ int __cpuinit xlr_wakeup_secondary_cpus(void)
53{ 53{
54 struct nlm_soc_info *nodep; 54 struct nlm_soc_info *nodep;
55 unsigned int i, j, boot_cpu; 55 unsigned int i, j, boot_cpu;
56 volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY);
56 57
57 /* 58 /*
58 * In case of RMI boot, hit with NMI to get the cores 59 * In case of RMI boot, hit with NMI to get the cores
@@ -71,7 +72,7 @@ int __cpuinit xlr_wakeup_secondary_cpus(void)
71 nodep->coremask = 1; 72 nodep->coremask = 1;
72 for (i = 1; i < NLM_CORES_PER_NODE; i++) { 73 for (i = 1; i < NLM_CORES_PER_NODE; i++) {
73 for (j = 1000000; j > 0; j--) { 74 for (j = 1000000; j > 0; j--) {
74 if (nlm_cpu_ready[i * NLM_THREADS_PER_CORE]) 75 if (cpu_ready[i * NLM_THREADS_PER_CORE])
75 break; 76 break;
76 udelay(10); 77 udelay(10);
77 } 78 }
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 2cb1d315d225..c382042911dd 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -29,7 +29,7 @@ obj-$(CONFIG_LASAT) += pci-lasat.o
29obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o 29obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
30obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o 30obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o
31obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o 31obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o
32obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o 32obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o pci-malta.o
33obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o 33obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o
34obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o 34obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o
35obj-$(CONFIG_PMC_MSP7120_FPGA) += fixup-pmcmsp.o ops-pmcmsp.o 35obj-$(CONFIG_PMC_MSP7120_FPGA) += fixup-pmcmsp.o ops-pmcmsp.o
@@ -52,12 +52,11 @@ obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o
52obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o 52obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o
53obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o 53obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
54obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o 54obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
55obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
56obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o 55obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
57obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o 56obj-$(CONFIG_CAVIUM_OCTEON_SOC) += pci-octeon.o pcie-octeon.o
58obj-$(CONFIG_CPU_XLR) += pci-xlr.o 57obj-$(CONFIG_CPU_XLR) += pci-xlr.o
59obj-$(CONFIG_CPU_XLP) += pci-xlp.o 58obj-$(CONFIG_CPU_XLP) += pci-xlp.o
60 59
61ifdef CONFIG_PCI_MSI 60ifdef CONFIG_PCI_MSI
62obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o 61obj-$(CONFIG_CAVIUM_OCTEON_SOC) += msi-octeon.o
63endif 62endif
diff --git a/arch/mips/pci/fixup-wrppmc.c b/arch/mips/pci/fixup-wrppmc.c
deleted file mode 100644
index 29737edd121f..000000000000
--- a/arch/mips/pci/fixup-wrppmc.c
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * fixup-wrppmc.c: PPMC board specific PCI fixup
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2006, Wind River Inc. Rongkai.zhan (rongkai.zhan@windriver.com)
9 */
10#include <linux/init.h>
11#include <linux/pci.h>
12#include <asm/gt64120.h>
13
14/* PCI interrupt pins */
15#define PCI_INTA 1
16#define PCI_INTB 2
17#define PCI_INTC 3
18#define PCI_INTD 4
19
20#define PCI_SLOT_MAXNR 32 /* Each PCI bus has 32 physical slots */
21
22static char pci_irq_tab[PCI_SLOT_MAXNR][5] __initdata = {
23 /* 0 INTA INTB INTC INTD */
24 [0] = {0, 0, 0, 0, 0}, /* Slot 0: GT64120 PCI bridge */
25 [6] = {0, WRPPMC_PCI_INTA_IRQ, 0, 0, 0},
26};
27
28int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
29{
30 return pci_irq_tab[slot][pin];
31}
32
33/* Do platform specific device initialization at pci_enable_device() time */
34int pcibios_plat_dev_init(struct pci_dev *dev)
35{
36 return 0;
37}
diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
index 2eb954239bc5..151d9b5870bb 100644
--- a/arch/mips/pci/pci-bcm63xx.c
+++ b/arch/mips/pci/pci-bcm63xx.c
@@ -266,7 +266,7 @@ static int __init bcm63xx_register_pci(void)
266 /* setup PCI to local bus access, used by PCI device to target 266 /* setup PCI to local bus access, used by PCI device to target
267 * local RAM while bus mastering */ 267 * local RAM while bus mastering */
268 bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3); 268 bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
269 if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) 269 if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368())
270 val = MPI_SP0_REMAP_ENABLE_MASK; 270 val = MPI_SP0_REMAP_ENABLE_MASK;
271 else 271 else
272 val = 0; 272 val = 0;
@@ -338,6 +338,7 @@ static int __init bcm63xx_pci_init(void)
338 case BCM6328_CPU_ID: 338 case BCM6328_CPU_ID:
339 case BCM6362_CPU_ID: 339 case BCM6362_CPU_ID:
340 return bcm63xx_register_pcie(); 340 return bcm63xx_register_pcie();
341 case BCM3368_CPU_ID:
341 case BCM6348_CPU_ID: 342 case BCM6348_CPU_ID:
342 case BCM6358_CPU_ID: 343 case BCM6358_CPU_ID:
343 case BCM6368_CPU_ID: 344 case BCM6368_CPU_ID:
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index 6eb65e44d9e4..7b2ac81e1f59 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -217,6 +217,7 @@ static void pci_fixup_ioc3(struct pci_dev *d)
217 pci_disable_swapping(d); 217 pci_disable_swapping(d);
218} 218}
219 219
220#ifdef CONFIG_NUMA
220int pcibus_to_node(struct pci_bus *bus) 221int pcibus_to_node(struct pci_bus *bus)
221{ 222{
222 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); 223 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
@@ -224,6 +225,7 @@ int pcibus_to_node(struct pci_bus *bus)
224 return bc->nasid; 225 return bc->nasid;
225} 226}
226EXPORT_SYMBOL(pcibus_to_node); 227EXPORT_SYMBOL(pcibus_to_node);
228#endif /* CONFIG_NUMA */
227 229
228DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 230DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
229 pci_fixup_ioc3); 231 pci_fixup_ioc3);
diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/pci/pci-malta.c
index 37134ddfeaa5..37134ddfeaa5 100644
--- a/arch/mips/mti-malta/malta-pci.c
+++ b/arch/mips/pci/pci-malta.c
diff --git a/arch/mips/pmcs-msp71xx/Makefile b/arch/mips/pmcs-msp71xx/Makefile
index cefba7733b73..9201c8b3858d 100644
--- a/arch/mips/pmcs-msp71xx/Makefile
+++ b/arch/mips/pmcs-msp71xx/Makefile
@@ -3,7 +3,6 @@
3# 3#
4obj-y += msp_prom.o msp_setup.o msp_irq.o \ 4obj-y += msp_prom.o msp_setup.o msp_irq.o \
5 msp_time.o msp_serial.o msp_elb.o 5 msp_time.o msp_serial.o msp_elb.o
6obj-$(CONFIG_HAVE_GPIO_LIB) += gpio.o gpio_extended.o
7obj-$(CONFIG_PMC_MSP7120_GW) += msp_hwbutton.o 6obj-$(CONFIG_PMC_MSP7120_GW) += msp_hwbutton.o
8obj-$(CONFIG_IRQ_MSP_SLP) += msp_irq_slp.o 7obj-$(CONFIG_IRQ_MSP_SLP) += msp_irq_slp.o
9obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o msp_irq_per.o 8obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o msp_irq_per.o
diff --git a/arch/mips/pmcs-msp71xx/gpio.c b/arch/mips/pmcs-msp71xx/gpio.c
deleted file mode 100644
index aaccbe524386..000000000000
--- a/arch/mips/pmcs-msp71xx/gpio.c
+++ /dev/null
@@ -1,216 +0,0 @@
1/*
2 * Generic PMC MSP71xx GPIO handling. These base gpio are controlled by two
3 * types of registers. The data register sets the output level when in output
4 * mode and when in input mode will contain the value at the input. The config
5 * register sets the various modes for each gpio.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * @author Patrick Glass <patrickglass@gmail.com>
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/gpio.h>
18#include <linux/spinlock.h>
19#include <linux/io.h>
20
21#define MSP71XX_CFG_OFFSET(gpio) (4 * (gpio))
22#define CONF_MASK 0x0F
23#define MSP71XX_GPIO_INPUT 0x01
24#define MSP71XX_GPIO_OUTPUT 0x08
25
26#define MSP71XX_GPIO_BASE 0x0B8400000L
27
28#define to_msp71xx_gpio_chip(c) container_of(c, struct msp71xx_gpio_chip, chip)
29
30static spinlock_t gpio_lock;
31
32/*
33 * struct msp71xx_gpio_chip - container for gpio chip and registers
34 * @chip: chip structure for the specified gpio bank
35 * @data_reg: register for reading and writing the gpio pin value
36 * @config_reg: register to set the mode for the gpio pin bank
37 * @out_drive_reg: register to set the output drive mode for the gpio pin bank
38 */
39struct msp71xx_gpio_chip {
40 struct gpio_chip chip;
41 void __iomem *data_reg;
42 void __iomem *config_reg;
43 void __iomem *out_drive_reg;
44};
45
46/*
47 * msp71xx_gpio_get() - return the chip's gpio value
48 * @chip: chip structure which controls the specified gpio
49 * @offset: gpio whose value will be returned
50 *
51 * It will return 0 if gpio value is low and other if high.
52 */
53static int msp71xx_gpio_get(struct gpio_chip *chip, unsigned offset)
54{
55 struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip);
56
57 return __raw_readl(msp_chip->data_reg) & (1 << offset);
58}
59
60/*
61 * msp71xx_gpio_set() - set the output value for the gpio
62 * @chip: chip structure who controls the specified gpio
63 * @offset: gpio whose value will be assigned
64 * @value: logic level to assign to the gpio initially
65 *
66 * This will set the gpio bit specified to the desired value. It will set the
67 * gpio pin low if value is 0 otherwise it will be high.
68 */
69static void msp71xx_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
70{
71 struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip);
72 unsigned long flags;
73 u32 data;
74
75 spin_lock_irqsave(&gpio_lock, flags);
76
77 data = __raw_readl(msp_chip->data_reg);
78 if (value)
79 data |= (1 << offset);
80 else
81 data &= ~(1 << offset);
82 __raw_writel(data, msp_chip->data_reg);
83
84 spin_unlock_irqrestore(&gpio_lock, flags);
85}
86
87/*
88 * msp71xx_set_gpio_mode() - declare the mode for a gpio
89 * @chip: chip structure which controls the specified gpio
90 * @offset: gpio whose value will be assigned
91 * @mode: desired configuration for the gpio (see datasheet)
92 *
93 * It will set the gpio pin config to the @mode value passed in.
94 */
95static int msp71xx_set_gpio_mode(struct gpio_chip *chip,
96 unsigned offset, int mode)
97{
98 struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip);
99 const unsigned bit_offset = MSP71XX_CFG_OFFSET(offset);
100 unsigned long flags;
101 u32 cfg;
102
103 spin_lock_irqsave(&gpio_lock, flags);
104
105 cfg = __raw_readl(msp_chip->config_reg);
106 cfg &= ~(CONF_MASK << bit_offset);
107 cfg |= (mode << bit_offset);
108 __raw_writel(cfg, msp_chip->config_reg);
109
110 spin_unlock_irqrestore(&gpio_lock, flags);
111
112 return 0;
113}
114
115/*
116 * msp71xx_direction_output() - declare the direction mode for a gpio
117 * @chip: chip structure which controls the specified gpio
118 * @offset: gpio whose value will be assigned
119 * @value: logic level to assign to the gpio initially
120 *
121 * This call will set the mode for the @gpio to output. It will set the
122 * gpio pin low if value is 0 otherwise it will be high.
123 */
124static int msp71xx_direction_output(struct gpio_chip *chip,
125 unsigned offset, int value)
126{
127 msp71xx_gpio_set(chip, offset, value);
128
129 return msp71xx_set_gpio_mode(chip, offset, MSP71XX_GPIO_OUTPUT);
130}
131
132/*
133 * msp71xx_direction_input() - declare the direction mode for a gpio
134 * @chip: chip structure which controls the specified gpio
135 * @offset: gpio whose to which the value will be assigned
136 *
137 * This call will set the mode for the @gpio to input.
138 */
139static int msp71xx_direction_input(struct gpio_chip *chip, unsigned offset)
140{
141 return msp71xx_set_gpio_mode(chip, offset, MSP71XX_GPIO_INPUT);
142}
143
144/*
145 * msp71xx_set_output_drive() - declare the output drive for the gpio line
146 * @gpio: gpio pin whose output drive you wish to modify
147 * @value: zero for active drain 1 for open drain drive
148 *
149 * This call will set the output drive mode for the @gpio to output.
150 */
151int msp71xx_set_output_drive(unsigned gpio, int value)
152{
153 unsigned long flags;
154 u32 data;
155
156 if (gpio > 15 || gpio < 0)
157 return -EINVAL;
158
159 spin_lock_irqsave(&gpio_lock, flags);
160
161 data = __raw_readl((void __iomem *)(MSP71XX_GPIO_BASE + 0x190));
162 if (value)
163 data |= (1 << gpio);
164 else
165 data &= ~(1 << gpio);
166 __raw_writel(data, (void __iomem *)(MSP71XX_GPIO_BASE + 0x190));
167
168 spin_unlock_irqrestore(&gpio_lock, flags);
169
170 return 0;
171}
172EXPORT_SYMBOL(msp71xx_set_output_drive);
173
174#define MSP71XX_GPIO_BANK(name, dr, cr, base_gpio, num_gpio) \
175{ \
176 .chip = { \
177 .label = name, \
178 .direction_input = msp71xx_direction_input, \
179 .direction_output = msp71xx_direction_output, \
180 .get = msp71xx_gpio_get, \
181 .set = msp71xx_gpio_set, \
182 .base = base_gpio, \
183 .ngpio = num_gpio \
184 }, \
185 .data_reg = (void __iomem *)(MSP71XX_GPIO_BASE + dr), \
186 .config_reg = (void __iomem *)(MSP71XX_GPIO_BASE + cr), \
187 .out_drive_reg = (void __iomem *)(MSP71XX_GPIO_BASE + 0x190), \
188}
189
190/*
191 * struct msp71xx_gpio_banks[] - container array of gpio banks
192 * @chip: chip structure for the specified gpio bank
193 * @data_reg: register for reading and writing the gpio pin value
194 * @config_reg: register to set the mode for the gpio pin bank
195 *
196 * This array structure defines the gpio banks for the PMC MIPS Processor.
197 * We specify the bank name, the data register, the config register, base
198 * starting gpio number, and the number of gpios exposed by the bank.
199 */
200static struct msp71xx_gpio_chip msp71xx_gpio_banks[] = {
201
202 MSP71XX_GPIO_BANK("GPIO_1_0", 0x170, 0x180, 0, 2),
203 MSP71XX_GPIO_BANK("GPIO_5_2", 0x174, 0x184, 2, 4),
204 MSP71XX_GPIO_BANK("GPIO_9_6", 0x178, 0x188, 6, 4),
205 MSP71XX_GPIO_BANK("GPIO_15_10", 0x17C, 0x18C, 10, 6),
206};
207
208void __init msp71xx_init_gpio(void)
209{
210 int i;
211
212 spin_lock_init(&gpio_lock);
213
214 for (i = 0; i < ARRAY_SIZE(msp71xx_gpio_banks); i++)
215 gpiochip_add(&msp71xx_gpio_banks[i].chip);
216}
diff --git a/arch/mips/pmcs-msp71xx/gpio_extended.c b/arch/mips/pmcs-msp71xx/gpio_extended.c
deleted file mode 100644
index 2a99f360fae4..000000000000
--- a/arch/mips/pmcs-msp71xx/gpio_extended.c
+++ /dev/null
@@ -1,146 +0,0 @@
1/*
2 * Generic PMC MSP71xx EXTENDED (EXD) GPIO handling. The extended gpio is
3 * a set of hardware registers that have no need for explicit locking as
4 * it is handled by unique method of writing individual set/clr bits.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * @author Patrick Glass <patrickglass@gmail.com>
11 */
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/gpio.h>
17#include <linux/io.h>
18
19#define MSP71XX_DATA_OFFSET(gpio) (2 * (gpio))
20#define MSP71XX_READ_OFFSET(gpio) (MSP71XX_DATA_OFFSET(gpio) + 1)
21#define MSP71XX_CFG_OUT_OFFSET(gpio) (MSP71XX_DATA_OFFSET(gpio) + 16)
22#define MSP71XX_CFG_IN_OFFSET(gpio) (MSP71XX_CFG_OUT_OFFSET(gpio) + 1)
23
24#define MSP71XX_EXD_GPIO_BASE 0x0BC000000L
25
26#define to_msp71xx_exd_gpio_chip(c) \
27 container_of(c, struct msp71xx_exd_gpio_chip, chip)
28
29/*
30 * struct msp71xx_exd_gpio_chip - container for gpio chip and registers
31 * @chip: chip structure for the specified gpio bank
32 * @reg: register for control and data of gpio pin
33 */
34struct msp71xx_exd_gpio_chip {
35 struct gpio_chip chip;
36 void __iomem *reg;
37};
38
39/*
40 * msp71xx_exd_gpio_get() - return the chip's gpio value
41 * @chip: chip structure which controls the specified gpio
42 * @offset: gpio whose value will be returned
43 *
44 * It will return 0 if gpio value is low and other if high.
45 */
46static int msp71xx_exd_gpio_get(struct gpio_chip *chip, unsigned offset)
47{
48 struct msp71xx_exd_gpio_chip *msp71xx_chip =
49 to_msp71xx_exd_gpio_chip(chip);
50 const unsigned bit = MSP71XX_READ_OFFSET(offset);
51
52 return __raw_readl(msp71xx_chip->reg) & (1 << bit);
53}
54
55/*
56 * msp71xx_exd_gpio_set() - set the output value for the gpio
57 * @chip: chip structure who controls the specified gpio
58 * @offset: gpio whose value will be assigned
59 * @value: logic level to assign to the gpio initially
60 *
61 * This will set the gpio bit specified to the desired value. It will set the
62 * gpio pin low if value is 0 otherwise it will be high.
63 */
64static void msp71xx_exd_gpio_set(struct gpio_chip *chip,
65 unsigned offset, int value)
66{
67 struct msp71xx_exd_gpio_chip *msp71xx_chip =
68 to_msp71xx_exd_gpio_chip(chip);
69 const unsigned bit = MSP71XX_DATA_OFFSET(offset);
70
71 __raw_writel(1 << (bit + (value ? 1 : 0)), msp71xx_chip->reg);
72}
73
74/*
75 * msp71xx_exd_direction_output() - declare the direction mode for a gpio
76 * @chip: chip structure which controls the specified gpio
77 * @offset: gpio whose value will be assigned
78 * @value: logic level to assign to the gpio initially
79 *
80 * This call will set the mode for the @gpio to output. It will set the
81 * gpio pin low if value is 0 otherwise it will be high.
82 */
83static int msp71xx_exd_direction_output(struct gpio_chip *chip,
84 unsigned offset, int value)
85{
86 struct msp71xx_exd_gpio_chip *msp71xx_chip =
87 to_msp71xx_exd_gpio_chip(chip);
88
89 msp71xx_exd_gpio_set(chip, offset, value);
90 __raw_writel(1 << MSP71XX_CFG_OUT_OFFSET(offset), msp71xx_chip->reg);
91 return 0;
92}
93
94/*
95 * msp71xx_exd_direction_input() - declare the direction mode for a gpio
96 * @chip: chip structure which controls the specified gpio
97 * @offset: gpio whose to which the value will be assigned
98 *
99 * This call will set the mode for the @gpio to input.
100 */
101static int msp71xx_exd_direction_input(struct gpio_chip *chip, unsigned offset)
102{
103 struct msp71xx_exd_gpio_chip *msp71xx_chip =
104 to_msp71xx_exd_gpio_chip(chip);
105
106 __raw_writel(1 << MSP71XX_CFG_IN_OFFSET(offset), msp71xx_chip->reg);
107 return 0;
108}
109
110#define MSP71XX_EXD_GPIO_BANK(name, exd_reg, base_gpio, num_gpio) \
111{ \
112 .chip = { \
113 .label = name, \
114 .direction_input = msp71xx_exd_direction_input, \
115 .direction_output = msp71xx_exd_direction_output, \
116 .get = msp71xx_exd_gpio_get, \
117 .set = msp71xx_exd_gpio_set, \
118 .base = base_gpio, \
119 .ngpio = num_gpio, \
120 }, \
121 .reg = (void __iomem *)(MSP71XX_EXD_GPIO_BASE + exd_reg), \
122}
123
124/*
125 * struct msp71xx_exd_gpio_banks[] - container array of gpio banks
126 * @chip: chip structure for the specified gpio bank
127 * @reg: register for reading and writing the gpio pin value
128 *
129 * This array structure defines the extended gpio banks for the
130 * PMC MIPS Processor. We specify the bank name, the data/config
131 * register,the base starting gpio number, and the number of
132 * gpios exposed by the bank of gpios.
133 */
134static struct msp71xx_exd_gpio_chip msp71xx_exd_gpio_banks[] = {
135
136 MSP71XX_EXD_GPIO_BANK("GPIO_23_16", 0x188, 16, 8),
137 MSP71XX_EXD_GPIO_BANK("GPIO_27_24", 0x18C, 24, 4),
138};
139
140void __init msp71xx_init_gpio_extended(void)
141{
142 int i;
143
144 for (i = 0; i < ARRAY_SIZE(msp71xx_exd_gpio_banks); i++)
145 gpiochip_add(&msp71xx_exd_gpio_banks[i].chip);
146}
diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c
index d38b095fd0d0..9f64c2387808 100644
--- a/arch/mips/powertv/asic/asic_devices.c
+++ b/arch/mips/powertv/asic/asic_devices.c
@@ -529,17 +529,8 @@ EXPORT_SYMBOL(asic_resource_get);
529 */ 529 */
530void platform_release_memory(void *ptr, int size) 530void platform_release_memory(void *ptr, int size)
531{ 531{
532 unsigned long addr; 532 free_reserved_area((unsigned long)ptr, (unsigned long)(ptr + size),
533 unsigned long end; 533 -1, NULL);
534
535 addr = ((unsigned long)ptr + (PAGE_SIZE - 1)) & PAGE_MASK;
536 end = ((unsigned long)ptr + size) & PAGE_MASK;
537
538 for (; addr < end; addr += PAGE_SIZE) {
539 ClearPageReserved(virt_to_page(__va(addr)));
540 init_page_count(virt_to_page(__va(addr)));
541 free_page((unsigned long)__va(addr));
542 }
543} 534}
544EXPORT_SYMBOL(platform_release_memory); 535EXPORT_SYMBOL(platform_release_memory);
545 536
diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c
index 6b5f3406f414..f25ea5b45051 100644
--- a/arch/mips/ralink/of.c
+++ b/arch/mips/ralink/of.c
@@ -104,7 +104,7 @@ static int __init plat_of_setup(void)
104 if (!of_have_populated_dt()) 104 if (!of_have_populated_dt())
105 panic("device tree not present"); 105 panic("device tree not present");
106 106
107 strncpy(of_ids[0].compatible, soc_info.compatible, len); 107 strlcpy(of_ids[0].compatible, soc_info.compatible, len);
108 strncpy(of_ids[1].compatible, "palmbus", len); 108 strncpy(of_ids[1].compatible, "palmbus", len);
109 109
110 if (of_platform_populate(NULL, of_ids, NULL, NULL)) 110 if (of_platform_populate(NULL, of_ids, NULL, NULL))
diff --git a/arch/mips/sgi-ip27/Makefile b/arch/mips/sgi-ip27/Makefile
index 1f29e761d691..da8f6816d346 100644
--- a/arch/mips/sgi-ip27/Makefile
+++ b/arch/mips/sgi-ip27/Makefile
@@ -7,4 +7,5 @@ obj-y := ip27-berr.o ip27-irq.o ip27-init.o ip27-klconfig.o ip27-klnuma.o \
7 ip27-xtalk.o 7 ip27-xtalk.o
8 8
9obj-$(CONFIG_EARLY_PRINTK) += ip27-console.o 9obj-$(CONFIG_EARLY_PRINTK) += ip27-console.o
10obj-$(CONFIG_PCI) += ip27-irq-pci.o
10obj-$(CONFIG_SMP) += ip27-smp.o 11obj-$(CONFIG_SMP) += ip27-smp.o
diff --git a/arch/mips/sgi-ip27/ip27-irq-pci.c b/arch/mips/sgi-ip27/ip27-irq-pci.c
new file mode 100644
index 000000000000..ec22ec5600f3
--- /dev/null
+++ b/arch/mips/sgi-ip27/ip27-irq-pci.c
@@ -0,0 +1,266 @@
1/*
2 * ip27-irq.c: Highlevel interrupt handling for IP27 architecture.
3 *
4 * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org)
5 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
6 * Copyright (C) 1999 - 2001 Kanoj Sarcar
7 */
8
9#undef DEBUG
10
11#include <linux/init.h>
12#include <linux/irq.h>
13#include <linux/errno.h>
14#include <linux/signal.h>
15#include <linux/sched.h>
16#include <linux/types.h>
17#include <linux/interrupt.h>
18#include <linux/ioport.h>
19#include <linux/timex.h>
20#include <linux/smp.h>
21#include <linux/random.h>
22#include <linux/kernel.h>
23#include <linux/kernel_stat.h>
24#include <linux/delay.h>
25#include <linux/bitops.h>
26
27#include <asm/bootinfo.h>
28#include <asm/io.h>
29#include <asm/mipsregs.h>
30
31#include <asm/processor.h>
32#include <asm/pci/bridge.h>
33#include <asm/sn/addrs.h>
34#include <asm/sn/agent.h>
35#include <asm/sn/arch.h>
36#include <asm/sn/hub.h>
37#include <asm/sn/intr.h>
38
39/*
40 * Linux has a controller-independent x86 interrupt architecture.
41 * every controller has a 'controller-template', that is used
42 * by the main code to do the right thing. Each driver-visible
43 * interrupt source is transparently wired to the appropriate
44 * controller. Thus drivers need not be aware of the
45 * interrupt-controller.
46 *
47 * Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC,
48 * PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC.
49 * (IO-APICs assumed to be messaging to Pentium local-APICs)
50 *
51 * the code is designed to be easily extended with new/different
52 * interrupt controllers, without having to do assembly magic.
53 */
54
55extern struct bridge_controller *irq_to_bridge[];
56extern int irq_to_slot[];
57
58/*
59 * use these macros to get the encoded nasid and widget id
60 * from the irq value
61 */
62#define IRQ_TO_BRIDGE(i) irq_to_bridge[(i)]
63#define SLOT_FROM_PCI_IRQ(i) irq_to_slot[i]
64
65static inline int alloc_level(int cpu, int irq)
66{
67 struct hub_data *hub = hub_data(cpu_to_node(cpu));
68 struct slice_data *si = cpu_data[cpu].data;
69 int level;
70
71 level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE);
72 if (level >= LEVELS_PER_SLICE)
73 panic("Cpu %d flooded with devices", cpu);
74
75 __set_bit(level, hub->irq_alloc_mask);
76 si->level_to_irq[level] = irq;
77
78 return level;
79}
80
81static inline int find_level(cpuid_t *cpunum, int irq)
82{
83 int cpu, i;
84
85 for_each_online_cpu(cpu) {
86 struct slice_data *si = cpu_data[cpu].data;
87
88 for (i = BASE_PCI_IRQ; i < LEVELS_PER_SLICE; i++)
89 if (si->level_to_irq[i] == irq) {
90 *cpunum = cpu;
91
92 return i;
93 }
94 }
95
96 panic("Could not identify cpu/level for irq %d", irq);
97}
98
99static int intr_connect_level(int cpu, int bit)
100{
101 nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
102 struct slice_data *si = cpu_data[cpu].data;
103
104 set_bit(bit, si->irq_enable_mask);
105
106 if (!cputoslice(cpu)) {
107 REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
108 REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
109 } else {
110 REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
111 REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
112 }
113
114 return 0;
115}
116
117static int intr_disconnect_level(int cpu, int bit)
118{
119 nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
120 struct slice_data *si = cpu_data[cpu].data;
121
122 clear_bit(bit, si->irq_enable_mask);
123
124 if (!cputoslice(cpu)) {
125 REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
126 REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
127 } else {
128 REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
129 REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
130 }
131
132 return 0;
133}
134
135/* Startup one of the (PCI ...) IRQs routes over a bridge. */
136static unsigned int startup_bridge_irq(struct irq_data *d)
137{
138 struct bridge_controller *bc;
139 bridgereg_t device;
140 bridge_t *bridge;
141 int pin, swlevel;
142 cpuid_t cpu;
143
144 pin = SLOT_FROM_PCI_IRQ(d->irq);
145 bc = IRQ_TO_BRIDGE(d->irq);
146 bridge = bc->base;
147
148 pr_debug("bridge_startup(): irq= 0x%x pin=%d\n", d->irq, pin);
149 /*
150 * "map" irq to a swlevel greater than 6 since the first 6 bits
151 * of INT_PEND0 are taken
152 */
153 swlevel = find_level(&cpu, d->irq);
154 bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (bc->nasid << 8));
155 bridge->b_int_enable |= (1 << pin);
156 bridge->b_int_enable |= 0x7ffffe00; /* more stuff in int_enable */
157
158 /*
159 * Enable sending of an interrupt clear packt to the hub on a high to
160 * low transition of the interrupt pin.
161 *
162 * IRIX sets additional bits in the address which are documented as
163 * reserved in the bridge docs.
164 */
165 bridge->b_int_mode |= (1UL << pin);
166
167 /*
168 * We assume the bridge to have a 1:1 mapping between devices
169 * (slots) and intr pins.
170 */
171 device = bridge->b_int_device;
172 device &= ~(7 << (pin*3));
173 device |= (pin << (pin*3));
174 bridge->b_int_device = device;
175
176 bridge->b_wid_tflush;
177
178 intr_connect_level(cpu, swlevel);
179
180 return 0; /* Never anything pending. */
181}
182
183/* Shutdown one of the (PCI ...) IRQs routes over a bridge. */
184static void shutdown_bridge_irq(struct irq_data *d)
185{
186 struct bridge_controller *bc = IRQ_TO_BRIDGE(d->irq);
187 bridge_t *bridge = bc->base;
188 int pin, swlevel;
189 cpuid_t cpu;
190
191 pr_debug("bridge_shutdown: irq 0x%x\n", d->irq);
192 pin = SLOT_FROM_PCI_IRQ(d->irq);
193
194 /*
195 * map irq to a swlevel greater than 6 since the first 6 bits
196 * of INT_PEND0 are taken
197 */
198 swlevel = find_level(&cpu, d->irq);
199 intr_disconnect_level(cpu, swlevel);
200
201 bridge->b_int_enable &= ~(1 << pin);
202 bridge->b_wid_tflush;
203}
204
205static inline void enable_bridge_irq(struct irq_data *d)
206{
207 cpuid_t cpu;
208 int swlevel;
209
210 swlevel = find_level(&cpu, d->irq); /* Criminal offence */
211 intr_connect_level(cpu, swlevel);
212}
213
214static inline void disable_bridge_irq(struct irq_data *d)
215{
216 cpuid_t cpu;
217 int swlevel;
218
219 swlevel = find_level(&cpu, d->irq); /* Criminal offence */
220 intr_disconnect_level(cpu, swlevel);
221}
222
223static struct irq_chip bridge_irq_type = {
224 .name = "bridge",
225 .irq_startup = startup_bridge_irq,
226 .irq_shutdown = shutdown_bridge_irq,
227 .irq_mask = disable_bridge_irq,
228 .irq_unmask = enable_bridge_irq,
229};
230
231void register_bridge_irq(unsigned int irq)
232{
233 irq_set_chip_and_handler(irq, &bridge_irq_type, handle_level_irq);
234}
235
236int request_bridge_irq(struct bridge_controller *bc)
237{
238 int irq = allocate_irqno();
239 int swlevel, cpu;
240 nasid_t nasid;
241
242 if (irq < 0)
243 return irq;
244
245 /*
246 * "map" irq to a swlevel greater than 6 since the first 6 bits
247 * of INT_PEND0 are taken
248 */
249 cpu = bc->irq_cpu;
250 swlevel = alloc_level(cpu, irq);
251 if (unlikely(swlevel < 0)) {
252 free_irqno(irq);
253
254 return -EAGAIN;
255 }
256
257 /* Make sure it's not already pending when we connect it. */
258 nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
259 REMOTE_HUB_CLR_INTR(nasid, swlevel);
260
261 intr_connect_level(cpu, swlevel);
262
263 register_bridge_irq(irq);
264
265 return irq;
266}
diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c
index 2315cfeb2687..3fbaef97a1b8 100644
--- a/arch/mips/sgi-ip27/ip27-irq.c
+++ b/arch/mips/sgi-ip27/ip27-irq.c
@@ -29,7 +29,6 @@
29#include <asm/mipsregs.h> 29#include <asm/mipsregs.h>
30 30
31#include <asm/processor.h> 31#include <asm/processor.h>
32#include <asm/pci/bridge.h>
33#include <asm/sn/addrs.h> 32#include <asm/sn/addrs.h>
34#include <asm/sn/agent.h> 33#include <asm/sn/agent.h>
35#include <asm/sn/arch.h> 34#include <asm/sn/arch.h>
@@ -54,50 +53,6 @@
54 53
55extern asmlinkage void ip27_irq(void); 54extern asmlinkage void ip27_irq(void);
56 55
57extern struct bridge_controller *irq_to_bridge[];
58extern int irq_to_slot[];
59
60/*
61 * use these macros to get the encoded nasid and widget id
62 * from the irq value
63 */
64#define IRQ_TO_BRIDGE(i) irq_to_bridge[(i)]
65#define SLOT_FROM_PCI_IRQ(i) irq_to_slot[i]
66
67static inline int alloc_level(int cpu, int irq)
68{
69 struct hub_data *hub = hub_data(cpu_to_node(cpu));
70 struct slice_data *si = cpu_data[cpu].data;
71 int level;
72
73 level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE);
74 if (level >= LEVELS_PER_SLICE)
75 panic("Cpu %d flooded with devices", cpu);
76
77 __set_bit(level, hub->irq_alloc_mask);
78 si->level_to_irq[level] = irq;
79
80 return level;
81}
82
83static inline int find_level(cpuid_t *cpunum, int irq)
84{
85 int cpu, i;
86
87 for_each_online_cpu(cpu) {
88 struct slice_data *si = cpu_data[cpu].data;
89
90 for (i = BASE_PCI_IRQ; i < LEVELS_PER_SLICE; i++)
91 if (si->level_to_irq[i] == irq) {
92 *cpunum = cpu;
93
94 return i;
95 }
96 }
97
98 panic("Could not identify cpu/level for irq %d", irq);
99}
100
101/* 56/*
102 * Find first bit set 57 * Find first bit set
103 */ 58 */
@@ -204,175 +159,6 @@ static void ip27_hub_error(void)
204 panic("CPU %d got a hub error interrupt", smp_processor_id()); 159 panic("CPU %d got a hub error interrupt", smp_processor_id());
205} 160}
206 161
207static int intr_connect_level(int cpu, int bit)
208{
209 nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
210 struct slice_data *si = cpu_data[cpu].data;
211
212 set_bit(bit, si->irq_enable_mask);
213
214 if (!cputoslice(cpu)) {
215 REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
216 REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
217 } else {
218 REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
219 REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
220 }
221
222 return 0;
223}
224
225static int intr_disconnect_level(int cpu, int bit)
226{
227 nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
228 struct slice_data *si = cpu_data[cpu].data;
229
230 clear_bit(bit, si->irq_enable_mask);
231
232 if (!cputoslice(cpu)) {
233 REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
234 REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
235 } else {
236 REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
237 REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
238 }
239
240 return 0;
241}
242
243/* Startup one of the (PCI ...) IRQs routes over a bridge. */
244static unsigned int startup_bridge_irq(struct irq_data *d)
245{
246 struct bridge_controller *bc;
247 bridgereg_t device;
248 bridge_t *bridge;
249 int pin, swlevel;
250 cpuid_t cpu;
251
252 pin = SLOT_FROM_PCI_IRQ(d->irq);
253 bc = IRQ_TO_BRIDGE(d->irq);
254 bridge = bc->base;
255
256 pr_debug("bridge_startup(): irq= 0x%x pin=%d\n", d->irq, pin);
257 /*
258 * "map" irq to a swlevel greater than 6 since the first 6 bits
259 * of INT_PEND0 are taken
260 */
261 swlevel = find_level(&cpu, d->irq);
262 bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (bc->nasid << 8));
263 bridge->b_int_enable |= (1 << pin);
264 bridge->b_int_enable |= 0x7ffffe00; /* more stuff in int_enable */
265
266 /*
267 * Enable sending of an interrupt clear packt to the hub on a high to
268 * low transition of the interrupt pin.
269 *
270 * IRIX sets additional bits in the address which are documented as
271 * reserved in the bridge docs.
272 */
273 bridge->b_int_mode |= (1UL << pin);
274
275 /*
276 * We assume the bridge to have a 1:1 mapping between devices
277 * (slots) and intr pins.
278 */
279 device = bridge->b_int_device;
280 device &= ~(7 << (pin*3));
281 device |= (pin << (pin*3));
282 bridge->b_int_device = device;
283
284 bridge->b_wid_tflush;
285
286 intr_connect_level(cpu, swlevel);
287
288 return 0; /* Never anything pending. */
289}
290
291/* Shutdown one of the (PCI ...) IRQs routes over a bridge. */
292static void shutdown_bridge_irq(struct irq_data *d)
293{
294 struct bridge_controller *bc = IRQ_TO_BRIDGE(d->irq);
295 bridge_t *bridge = bc->base;
296 int pin, swlevel;
297 cpuid_t cpu;
298
299 pr_debug("bridge_shutdown: irq 0x%x\n", d->irq);
300 pin = SLOT_FROM_PCI_IRQ(d->irq);
301
302 /*
303 * map irq to a swlevel greater than 6 since the first 6 bits
304 * of INT_PEND0 are taken
305 */
306 swlevel = find_level(&cpu, d->irq);
307 intr_disconnect_level(cpu, swlevel);
308
309 bridge->b_int_enable &= ~(1 << pin);
310 bridge->b_wid_tflush;
311}
312
313static inline void enable_bridge_irq(struct irq_data *d)
314{
315 cpuid_t cpu;
316 int swlevel;
317
318 swlevel = find_level(&cpu, d->irq); /* Criminal offence */
319 intr_connect_level(cpu, swlevel);
320}
321
322static inline void disable_bridge_irq(struct irq_data *d)
323{
324 cpuid_t cpu;
325 int swlevel;
326
327 swlevel = find_level(&cpu, d->irq); /* Criminal offence */
328 intr_disconnect_level(cpu, swlevel);
329}
330
331static struct irq_chip bridge_irq_type = {
332 .name = "bridge",
333 .irq_startup = startup_bridge_irq,
334 .irq_shutdown = shutdown_bridge_irq,
335 .irq_mask = disable_bridge_irq,
336 .irq_unmask = enable_bridge_irq,
337};
338
339void register_bridge_irq(unsigned int irq)
340{
341 irq_set_chip_and_handler(irq, &bridge_irq_type, handle_level_irq);
342}
343
344int request_bridge_irq(struct bridge_controller *bc)
345{
346 int irq = allocate_irqno();
347 int swlevel, cpu;
348 nasid_t nasid;
349
350 if (irq < 0)
351 return irq;
352
353 /*
354 * "map" irq to a swlevel greater than 6 since the first 6 bits
355 * of INT_PEND0 are taken
356 */
357 cpu = bc->irq_cpu;
358 swlevel = alloc_level(cpu, irq);
359 if (unlikely(swlevel < 0)) {
360 free_irqno(irq);
361
362 return -EAGAIN;
363 }
364
365 /* Make sure it's not already pending when we connect it. */
366 nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
367 REMOTE_HUB_CLR_INTR(nasid, swlevel);
368
369 intr_connect_level(cpu, swlevel);
370
371 register_bridge_irq(irq);
372
373 return irq;
374}
375
376asmlinkage void plat_irq_dispatch(void) 162asmlinkage void plat_irq_dispatch(void)
377{ 163{
378 unsigned long pending = read_c0_cause() & read_c0_status(); 164 unsigned long pending = read_c0_cause() & read_c0_status();
diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig
index 01cc1a749c73..5fbd3605d24f 100644
--- a/arch/mips/sibyte/Kconfig
+++ b/arch/mips/sibyte/Kconfig
@@ -147,7 +147,8 @@ config SIBYTE_CFE_CONSOLE
147 147
148config SIBYTE_BUS_WATCHER 148config SIBYTE_BUS_WATCHER
149 bool "Support for Bus Watcher statistics" 149 bool "Support for Bus Watcher statistics"
150 depends on SIBYTE_SB1xxx_SOC 150 depends on SIBYTE_SB1xxx_SOC && \
151 (SIBYTE_BCM112X || SIBYTE_SB1250)
151 help 152 help
152 Handle and keep statistics on the bus error interrupts (COR_ECC, 153 Handle and keep statistics on the bus error interrupts (COR_ECC,
153 BAD_ECC, IO_BUS). 154 BAD_ECC, IO_BUS).
diff --git a/arch/mips/sibyte/Platform b/arch/mips/sibyte/Platform
index d03a07516f83..af117330ce14 100644
--- a/arch/mips/sibyte/Platform
+++ b/arch/mips/sibyte/Platform
@@ -13,7 +13,6 @@ cflags-$(CONFIG_SIBYTE_BCM112X) += \
13 -I$(srctree)/arch/mips/include/asm/mach-sibyte \ 13 -I$(srctree)/arch/mips/include/asm/mach-sibyte \
14 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL 14 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
15 15
16platform-$(CONFIG_SIBYTE_SB1250) += sibyte/
17cflags-$(CONFIG_SIBYTE_SB1250) += \ 16cflags-$(CONFIG_SIBYTE_SB1250) += \
18 -I$(srctree)/arch/mips/include/asm/mach-sibyte \ 17 -I$(srctree)/arch/mips/include/asm/mach-sibyte \
19 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL 18 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
@@ -31,7 +30,8 @@ cflags-$(CONFIG_SIBYTE_BCM1x80) += \
31# Sibyte BCM91120C (CRhine) board 30# Sibyte BCM91120C (CRhine) board
32# Sibyte BCM91125C (CRhone) board 31# Sibyte BCM91125C (CRhone) board
33# Sibyte BCM91125E (Rhone) board 32# Sibyte BCM91125E (Rhone) board
34# Sibyte SWARM board 33# Sibyte BCM91250A (SWARM) board
34# Sibyte BCM91250C2 (LittleSur) board
35# Sibyte BCM91x80 (BigSur) board 35# Sibyte BCM91x80 (BigSur) board
36# 36#
37load-$(CONFIG_SIBYTE_CARMEL) := 0xffffffff80100000 37load-$(CONFIG_SIBYTE_CARMEL) := 0xffffffff80100000
@@ -41,3 +41,4 @@ load-$(CONFIG_SIBYTE_RHONE) := 0xffffffff80100000
41load-$(CONFIG_SIBYTE_SENTOSA) := 0xffffffff80100000 41load-$(CONFIG_SIBYTE_SENTOSA) := 0xffffffff80100000
42load-$(CONFIG_SIBYTE_SWARM) := 0xffffffff80100000 42load-$(CONFIG_SIBYTE_SWARM) := 0xffffffff80100000
43load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000 43load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000
44load-$(CONFIG_SIBYTE_LITTLESUR) := 0xffffffff80100000
diff --git a/arch/mips/sibyte/common/Makefile b/arch/mips/sibyte/common/Makefile
index 36aa700cc40c..b3d6bf23a662 100644
--- a/arch/mips/sibyte/common/Makefile
+++ b/arch/mips/sibyte/common/Makefile
@@ -1,3 +1,4 @@
1obj-y := cfe.o 1obj-y := cfe.o
2obj-$(CONFIG_SIBYTE_BUS_WATCHER) += bus_watcher.o
2obj-$(CONFIG_SIBYTE_CFE_CONSOLE) += cfe_console.o 3obj-$(CONFIG_SIBYTE_CFE_CONSOLE) += cfe_console.o
3obj-$(CONFIG_SIBYTE_TBPROF) += sb_tbprof.o 4obj-$(CONFIG_SIBYTE_TBPROF) += sb_tbprof.o
diff --git a/arch/mips/sibyte/sb1250/bus_watcher.c b/arch/mips/sibyte/common/bus_watcher.c
index 8871e3345bff..5581844c9194 100644
--- a/arch/mips/sibyte/sb1250/bus_watcher.c
+++ b/arch/mips/sibyte/common/bus_watcher.c
@@ -37,6 +37,9 @@
37#include <asm/sibyte/sb1250_regs.h> 37#include <asm/sibyte/sb1250_regs.h>
38#include <asm/sibyte/sb1250_int.h> 38#include <asm/sibyte/sb1250_int.h>
39#include <asm/sibyte/sb1250_scd.h> 39#include <asm/sibyte/sb1250_scd.h>
40#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
41#include <asm/sibyte/bcm1480_regs.h>
42#endif
40 43
41 44
42struct bw_stats_struct { 45struct bw_stats_struct {
@@ -81,9 +84,15 @@ void check_bus_watcher(void)
81#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS 84#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
82 /* Destructive read, clears register and interrupt */ 85 /* Destructive read, clears register and interrupt */
83 status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS)); 86 status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS));
84#else 87#elif defined(CONFIG_SIBYTE_BCM112X) || defined(CONFIG_SIBYTE_SB1250)
85 /* Use non-destructive register */ 88 /* Use non-destructive register */
86 status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS_DEBUG)); 89 status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS_DEBUG));
90#elif defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
91 /* Use non-destructive register */
92 /* Same as 1250 except BUS_ERR_STATUS_DEBUG is in a different place. */
93 status = csr_in32(IOADDR(A_BCM1480_BUS_ERR_STATUS_DEBUG));
94#else
95#error bus watcher being built for unknown Sibyte SOC!
87#endif 96#endif
88 if (!(status & 0x7fffffff)) { 97 if (!(status & 0x7fffffff)) {
89 printk("Using last values reaped by bus watcher driver\n"); 98 printk("Using last values reaped by bus watcher driver\n");
@@ -175,9 +184,6 @@ static irqreturn_t sibyte_bw_int(int irq, void *data)
175#ifdef CONFIG_SIBYTE_BW_TRACE 184#ifdef CONFIG_SIBYTE_BW_TRACE
176 int i; 185 int i;
177#endif 186#endif
178#ifndef CONFIG_PROC_FS
179 char bw_buf[1024];
180#endif
181 187
182#ifdef CONFIG_SIBYTE_BW_TRACE 188#ifdef CONFIG_SIBYTE_BW_TRACE
183 csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG)); 189 csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG));
diff --git a/arch/mips/sibyte/common/sb_tbprof.c b/arch/mips/sibyte/common/sb_tbprof.c
index 2188b39a1251..059e28c8fd97 100644
--- a/arch/mips/sibyte/common/sb_tbprof.c
+++ b/arch/mips/sibyte/common/sb_tbprof.c
@@ -27,6 +27,7 @@
27#include <linux/types.h> 27#include <linux/types.h>
28#include <linux/init.h> 28#include <linux/init.h>
29#include <linux/interrupt.h> 29#include <linux/interrupt.h>
30#include <linux/sched.h>
30#include <linux/vmalloc.h> 31#include <linux/vmalloc.h>
31#include <linux/fs.h> 32#include <linux/fs.h>
32#include <linux/errno.h> 33#include <linux/errno.h>
diff --git a/arch/mips/sibyte/sb1250/Makefile b/arch/mips/sibyte/sb1250/Makefile
index d3d969de407b..cdc4c56c3e29 100644
--- a/arch/mips/sibyte/sb1250/Makefile
+++ b/arch/mips/sibyte/sb1250/Makefile
@@ -1,4 +1,3 @@
1obj-y := setup.o irq.o time.o 1obj-y := setup.o irq.o time.o
2 2
3obj-$(CONFIG_SMP) += smp.o 3obj-$(CONFIG_SMP) += smp.o
4obj-$(CONFIG_SIBYTE_BUS_WATCHER) += bus_watcher.o
diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c
index cec4b8ca1438..12336c2a649c 100644
--- a/arch/mips/sni/pcimt.c
+++ b/arch/mips/sni/pcimt.c
@@ -185,6 +185,7 @@ static void __init sni_pcimt_resource_init(void)
185 185
186extern struct pci_ops sni_pcimt_ops; 186extern struct pci_ops sni_pcimt_ops;
187 187
188#ifdef CONFIG_PCI
188static struct pci_controller sni_controller = { 189static struct pci_controller sni_controller = {
189 .pci_ops = &sni_pcimt_ops, 190 .pci_ops = &sni_pcimt_ops,
190 .mem_resource = &sni_mem_resource, 191 .mem_resource = &sni_mem_resource,
@@ -193,6 +194,7 @@ static struct pci_controller sni_controller = {
193 .io_offset = 0x00000000UL, 194 .io_offset = 0x00000000UL,
194 .io_map_base = SNI_PORT_BASE 195 .io_map_base = SNI_PORT_BASE
195}; 196};
197#endif
196 198
197static void enable_pcimt_irq(struct irq_data *d) 199static void enable_pcimt_irq(struct irq_data *d)
198{ 200{
diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c
index 7cddd03d1fea..05bb51676e82 100644
--- a/arch/mips/sni/pcit.c
+++ b/arch/mips/sni/pcit.c
@@ -128,13 +128,6 @@ static struct resource pcit_io_resources[] = {
128 } 128 }
129}; 129};
130 130
131static struct resource sni_mem_resource = {
132 .start = 0x18000000UL,
133 .end = 0x1fbfffffUL,
134 .name = "PCIT PCI MEM",
135 .flags = IORESOURCE_MEM
136};
137
138static void __init sni_pcit_resource_init(void) 131static void __init sni_pcit_resource_init(void)
139{ 132{
140 int i; 133 int i;
@@ -147,6 +140,14 @@ static void __init sni_pcit_resource_init(void)
147 140
148extern struct pci_ops sni_pcit_ops; 141extern struct pci_ops sni_pcit_ops;
149 142
143#ifdef CONFIG_PCI
144static struct resource sni_mem_resource = {
145 .start = 0x18000000UL,
146 .end = 0x1fbfffffUL,
147 .name = "PCIT PCI MEM",
148 .flags = IORESOURCE_MEM
149};
150
150static struct pci_controller sni_pcit_controller = { 151static struct pci_controller sni_pcit_controller = {
151 .pci_ops = &sni_pcit_ops, 152 .pci_ops = &sni_pcit_ops,
152 .mem_resource = &sni_mem_resource, 153 .mem_resource = &sni_mem_resource,
@@ -155,6 +156,7 @@ static struct pci_controller sni_pcit_controller = {
155 .io_offset = 0x00000000UL, 156 .io_offset = 0x00000000UL,
156 .io_map_base = SNI_PORT_BASE 157 .io_map_base = SNI_PORT_BASE
157}; 158};
159#endif /* CONFIG_PCI */
158 160
159static void enable_pcit_irq(struct irq_data *d) 161static void enable_pcit_irq(struct irq_data *d)
160{ 162{
diff --git a/arch/mips/wrppmc/Makefile b/arch/mips/wrppmc/Makefile
deleted file mode 100644
index 307cc6920ce6..000000000000
--- a/arch/mips/wrppmc/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
1#
2# This file is subject to the terms and conditions of the GNU General Public
3# License. See the file "COPYING" in the main directory of this archive
4# for more details.
5#
6# Copyright 2006 Wind River System, Inc.
7# Author: Rongkai.Zhan <rongkai.zhan@windriver.com>
8#
9# Makefile for the Wind River MIPS 4Kc PPMC Eval Board
10#
11
12obj-y += irq.o pci.o reset.o serial.o setup.o time.o
diff --git a/arch/mips/wrppmc/Platform b/arch/mips/wrppmc/Platform
deleted file mode 100644
index dc78b25b95fe..000000000000
--- a/arch/mips/wrppmc/Platform
+++ /dev/null
@@ -1,7 +0,0 @@
1#
2# Wind River PPMC Board (4KC + GT64120)
3#
4platform-$(CONFIG_WR_PPMC) += wrppmc/
5cflags-$(CONFIG_WR_PPMC) += \
6 -I$(srctree)/arch/mips/include/asm/mach-wrppmc
7load-$(CONFIG_WR_PPMC) += 0xffffffff80100000
diff --git a/arch/mips/wrppmc/irq.c b/arch/mips/wrppmc/irq.c
deleted file mode 100644
index f237bf4d5c3a..000000000000
--- a/arch/mips/wrppmc/irq.c
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * irq.c: GT64120 Interrupt Controller
3 *
4 * Copyright (C) 2006, Wind River System Inc.
5 * Author: Rongkai.Zhan, <rongkai.zhan@windriver.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12#include <linux/hardirq.h>
13#include <linux/init.h>
14#include <linux/irq.h>
15
16#include <asm/gt64120.h>
17#include <asm/irq_cpu.h>
18#include <asm/mipsregs.h>
19
20asmlinkage void plat_irq_dispatch(void)
21{
22 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
23
24 if (pending & STATUSF_IP7)
25 do_IRQ(WRPPMC_MIPS_TIMER_IRQ); /* CPU Compare/Count internal timer */
26 else if (pending & STATUSF_IP6)
27 do_IRQ(WRPPMC_UART16550_IRQ); /* UART 16550 port */
28 else if (pending & STATUSF_IP3)
29 do_IRQ(WRPPMC_PCI_INTA_IRQ); /* PCI INT_A */
30 else
31 spurious_interrupt();
32}
33
34/**
35 * Initialize GT64120 Interrupt Controller
36 */
37void gt64120_init_pic(void)
38{
39 /* clear CPU Interrupt Cause Registers */
40 GT_WRITE(GT_INTRCAUSE_OFS, (0x1F << 21));
41 GT_WRITE(GT_HINTRCAUSE_OFS, 0x00);
42
43 /* Disable all interrupts from GT64120 bridge chip */
44 GT_WRITE(GT_INTRMASK_OFS, 0x00);
45 GT_WRITE(GT_HINTRMASK_OFS, 0x00);
46 GT_WRITE(GT_PCI0_ICMASK_OFS, 0x00);
47 GT_WRITE(GT_PCI0_HICMASK_OFS, 0x00);
48}
49
50void __init arch_init_irq(void)
51{
52 /* IRQ 0 - 7 are for MIPS common irq_cpu controller */
53 mips_cpu_irq_init();
54
55 gt64120_init_pic();
56}
diff --git a/arch/mips/wrppmc/pci.c b/arch/mips/wrppmc/pci.c
deleted file mode 100644
index 8b8a0e1a40ca..000000000000
--- a/arch/mips/wrppmc/pci.c
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * pci.c: GT64120 PCI support.
3 *
4 * Copyright (C) 2006, Wind River System Inc. Rongkai.Zhan <rongkai.zhan@windriver.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/init.h>
11#include <linux/ioport.h>
12#include <linux/types.h>
13#include <linux/pci.h>
14
15#include <asm/gt64120.h>
16
17extern struct pci_ops gt64xxx_pci0_ops;
18
19static struct resource pci0_io_resource = {
20 .name = "pci_0 io",
21 .start = GT_PCI_IO_BASE,
22 .end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1,
23 .flags = IORESOURCE_IO,
24};
25
26static struct resource pci0_mem_resource = {
27 .name = "pci_0 memory",
28 .start = GT_PCI_MEM_BASE,
29 .end = GT_PCI_MEM_BASE + GT_PCI_MEM_SIZE - 1,
30 .flags = IORESOURCE_MEM,
31};
32
33static struct pci_controller hose_0 = {
34 .pci_ops = &gt64xxx_pci0_ops,
35 .io_resource = &pci0_io_resource,
36 .mem_resource = &pci0_mem_resource,
37};
38
39static int __init gt64120_pci_init(void)
40{
41 (void) GT_READ(GT_PCI0_CMD_OFS); /* Huh??? -- Ralf */
42 (void) GT_READ(GT_PCI0_BARE_OFS);
43
44 /* reset the whole PCI I/O space range */
45 ioport_resource.start = GT_PCI_IO_BASE;
46 ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1;
47
48 register_pci_controller(&hose_0);
49 return 0;
50}
51
52arch_initcall(gt64120_pci_init);
diff --git a/arch/mips/wrppmc/reset.c b/arch/mips/wrppmc/reset.c
deleted file mode 100644
index 80beb188ed47..000000000000
--- a/arch/mips/wrppmc/reset.c
+++ /dev/null
@@ -1,41 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1997 Ralf Baechle
7 */
8#include <linux/irqflags.h>
9#include <linux/kernel.h>
10
11#include <asm/cacheflush.h>
12#include <asm/idle.h>
13#include <asm/mipsregs.h>
14#include <asm/processor.h>
15
16void wrppmc_machine_restart(char *command)
17{
18 /*
19 * Ouch, we're still alive ... This time we take the silver bullet ...
20 * ... and find that we leave the hardware in a state in which the
21 * kernel in the flush locks up somewhen during of after the PCI
22 * detection stuff.
23 */
24 local_irq_disable();
25 set_c0_status(ST0_BEV | ST0_ERL);
26 change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
27 flush_cache_all();
28 write_c0_wired(0);
29 __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
30}
31
32void wrppmc_machine_halt(void)
33{
34 local_irq_disable();
35
36 printk(KERN_NOTICE "You can safely turn off the power\n");
37 while (1) {
38 if (cpu_wait)
39 cpu_wait();
40 }
41}
diff --git a/arch/mips/wrppmc/serial.c b/arch/mips/wrppmc/serial.c
deleted file mode 100644
index 83f0f7d05187..000000000000
--- a/arch/mips/wrppmc/serial.c
+++ /dev/null
@@ -1,80 +0,0 @@
1/*
2 * Registration of WRPPMC UART platform device.
3 *
4 * Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/errno.h>
21#include <linux/init.h>
22#include <linux/ioport.h>
23#include <linux/platform_device.h>
24#include <linux/serial_8250.h>
25
26#include <asm/gt64120.h>
27
28static struct resource wrppmc_uart_resource[] __initdata = {
29 {
30 .start = WRPPMC_UART16550_BASE,
31 .end = WRPPMC_UART16550_BASE + 7,
32 .flags = IORESOURCE_MEM,
33 },
34 {
35 .start = WRPPMC_UART16550_IRQ,
36 .end = WRPPMC_UART16550_IRQ,
37 .flags = IORESOURCE_IRQ,
38 },
39};
40
41static struct plat_serial8250_port wrppmc_serial8250_port[] = {
42 {
43 .irq = WRPPMC_UART16550_IRQ,
44 .uartclk = WRPPMC_UART16550_CLOCK,
45 .iotype = UPIO_MEM,
46 .flags = UPF_IOREMAP | UPF_SKIP_TEST,
47 .mapbase = WRPPMC_UART16550_BASE,
48 },
49 {},
50};
51
52static __init int wrppmc_uart_add(void)
53{
54 struct platform_device *pdev;
55 int retval;
56
57 pdev = platform_device_alloc("serial8250", -1);
58 if (!pdev)
59 return -ENOMEM;
60
61 pdev->id = PLAT8250_DEV_PLATFORM;
62 pdev->dev.platform_data = wrppmc_serial8250_port;
63
64 retval = platform_device_add_resources(pdev, wrppmc_uart_resource,
65 ARRAY_SIZE(wrppmc_uart_resource));
66 if (retval)
67 goto err_free_device;
68
69 retval = platform_device_add(pdev);
70 if (retval)
71 goto err_free_device;
72
73 return 0;
74
75err_free_device:
76 platform_device_put(pdev);
77
78 return retval;
79}
80device_initcall(wrppmc_uart_add);
diff --git a/arch/mips/wrppmc/setup.c b/arch/mips/wrppmc/setup.c
deleted file mode 100644
index ca65c84031a7..000000000000
--- a/arch/mips/wrppmc/setup.c
+++ /dev/null
@@ -1,128 +0,0 @@
1/*
2 * setup.c: Setup pointers to hardware dependent routines.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1996, 1997, 2004 by Ralf Baechle (ralf@linux-mips.org)
9 * Copyright (C) 2006, Wind River System Inc. Rongkai.zhan <rongkai.zhan@windriver.com>
10 */
11#include <linux/init.h>
12#include <linux/string.h>
13#include <linux/kernel.h>
14#include <linux/pm.h>
15
16#include <asm/io.h>
17#include <asm/bootinfo.h>
18#include <asm/reboot.h>
19#include <asm/time.h>
20#include <asm/gt64120.h>
21
22unsigned long gt64120_base = KSEG1ADDR(0x14000000);
23
24#ifdef WRPPMC_EARLY_DEBUG
25
26static volatile unsigned char * wrppmc_led = \
27 (volatile unsigned char *)KSEG1ADDR(WRPPMC_LED_BASE);
28
29/*
30 * PPMC LED control register:
31 * -) bit[0] controls DS1 LED (1 - OFF, 0 - ON)
32 * -) bit[1] controls DS2 LED (1 - OFF, 0 - ON)
33 * -) bit[2] controls DS4 LED (1 - OFF, 0 - ON)
34 */
35void wrppmc_led_on(int mask)
36{
37 unsigned char value = *wrppmc_led;
38
39 value &= (0xF8 | mask);
40 *wrppmc_led = value;
41}
42
43/* If mask = 0, turn off all LEDs */
44void wrppmc_led_off(int mask)
45{
46 unsigned char value = *wrppmc_led;
47
48 value |= (0x7 & mask);
49 *wrppmc_led = value;
50}
51
52/*
53 * We assume that bootloader has initialized UART16550 correctly
54 */
55void __init wrppmc_early_putc(char ch)
56{
57 static volatile unsigned char *wrppmc_uart = \
58 (volatile unsigned char *)KSEG1ADDR(WRPPMC_UART16550_BASE);
59 unsigned char value;
60
61 /* Wait until Transmit-Holding-Register is empty */
62 while (1) {
63 value = *(wrppmc_uart + 5);
64 if (value & 0x20)
65 break;
66 }
67
68 *wrppmc_uart = ch;
69}
70
71void __init wrppmc_early_printk(const char *fmt, ...)
72{
73 static char pbuf[256] = {'\0', };
74 char *ch = pbuf;
75 va_list args;
76 unsigned int i;
77
78 memset(pbuf, 0, 256);
79 va_start(args, fmt);
80 i = vsprintf(pbuf, fmt, args);
81 va_end(args);
82
83 /* Print the string */
84 while (*ch != '\0') {
85 wrppmc_early_putc(*ch);
86 /* if print '\n', also print '\r' */
87 if (*ch++ == '\n')
88 wrppmc_early_putc('\r');
89 }
90}
91#endif /* WRPPMC_EARLY_DEBUG */
92
93void __init prom_free_prom_memory(void)
94{
95}
96
97void __init plat_mem_setup(void)
98{
99 extern void wrppmc_machine_restart(char *command);
100 extern void wrppmc_machine_halt(void);
101
102 _machine_restart = wrppmc_machine_restart;
103 _machine_halt = wrppmc_machine_halt;
104 pm_power_off = wrppmc_machine_halt;
105
106 /* This makes the operations of 'in/out[bwl]' to the
107 * physical address ( < KSEG0) can work via KSEG1
108 */
109 set_io_port_base(KSEG1);
110}
111
112const char *get_system_type(void)
113{
114 return "Wind River PPMC (GT64120)";
115}
116
117/*
118 * Initializes basic routines and structures pointers, memory size (as
119 * given by the bios and saves the command line.
120 */
121void __init prom_init(void)
122{
123 add_memory_region(WRPPMC_SDRAM_SCS0_BASE, WRPPMC_SDRAM_SCS0_SIZE, BOOT_MEM_RAM);
124 add_memory_region(WRPPMC_BOOTROM_BASE, WRPPMC_BOOTROM_SIZE, BOOT_MEM_ROM_DATA);
125
126 wrppmc_early_printk("prom_init: GT64120 SDRAM Bank 0: 0x%x - 0x%08lx\n",
127 WRPPMC_SDRAM_SCS0_BASE, (WRPPMC_SDRAM_SCS0_BASE + WRPPMC_SDRAM_SCS0_SIZE));
128}
diff --git a/arch/mips/wrppmc/time.c b/arch/mips/wrppmc/time.c
deleted file mode 100644
index 668dbd5f12c5..000000000000
--- a/arch/mips/wrppmc/time.c
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * time.c: MIPS CPU Count/Compare timer hookup
3 *
4 * Author: Mark.Zhan, <rongkai.zhan@windriver.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 1996, 1997, 2004 by Ralf Baechle (ralf@linux-mips.org)
11 * Copyright (C) 2006, Wind River System Inc.
12 */
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16
17#include <asm/gt64120.h>
18#include <asm/time.h>
19
20#define WRPPMC_CPU_CLK_FREQ 40000000 /* 40MHZ */
21
22/*
23 * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
24 *
25 * NOTE: We disable all GT64120 timers, and use MIPS processor internal
26 * timer as the source of kernel clock tick.
27 */
28void __init plat_time_init(void)
29{
30 /* Disable GT64120 timers */
31 GT_WRITE(GT_TC_CONTROL_OFS, 0x00);
32 GT_WRITE(GT_TC0_OFS, 0x00);
33 GT_WRITE(GT_TC1_OFS, 0x00);
34 GT_WRITE(GT_TC2_OFS, 0x00);
35 GT_WRITE(GT_TC3_OFS, 0x00);
36
37 /* Use MIPS compare/count internal timer */
38 mips_hpt_frequency = WRPPMC_CPU_CLK_FREQ;
39}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-24 15:33:46 -0500