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authorRalf Baechle <ralf@linux-mips.org>2013-07-02 11:19:04 -0400
committerRalf Baechle <ralf@linux-mips.org>2013-07-12 12:11:43 -0400
commit6ac5310e649df5fcd240d764503bf16a1317ea39 (patch)
tree286700815b3f30dc13cc3b2d9980b0244b244d33 /arch
parent704e6460ab75af0735b1ca7c0dcaa4ff0a4001b2 (diff)
parent3f90b82df110ef9cb33761b56ca85ae0d0372d4a (diff)
Merge branch '3.10-fixes' into mips-for-linux-next
This that should have been fixed but weren't, way to much, intrusive and late.
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/Kconfig1
-rw-r--r--arch/mips/ath79/mach-ap136.c2
-rw-r--r--arch/mips/bcm63xx/Kconfig5
-rw-r--r--arch/mips/cavium-octeon/Makefile3
-rw-r--r--arch/mips/cavium-octeon/setup.c5
-rw-r--r--arch/mips/fw/cfe/cfe_api.c4
-rw-r--r--arch/mips/include/asm/fw/cfe/cfe_api.h4
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h7
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/spaces.h24
-rw-r--r--arch/mips/include/asm/mach-ip27/kernel-entry-init.h47
-rw-r--r--arch/mips/include/asm/mips-boards/generic.h6
-rw-r--r--arch/mips/include/asm/mmu_context.h2
-rw-r--r--arch/mips/include/asm/xtalk/xtalk.h9
-rw-r--r--arch/mips/include/uapi/asm/fcntl.h6
-rw-r--r--arch/mips/include/uapi/asm/inst.h9
-rw-r--r--arch/mips/include/uapi/asm/msgbuf.h12
-rw-r--r--arch/mips/include/uapi/asm/resource.h2
-rw-r--r--arch/mips/include/uapi/asm/siginfo.h4
-rw-r--r--arch/mips/include/uapi/asm/swab.h12
-rw-r--r--arch/mips/kernel/ftrace.c4
-rw-r--r--arch/mips/kernel/head.S39
-rw-r--r--arch/mips/kernel/idle.c13
-rw-r--r--arch/mips/kernel/rtlx.c1
-rw-r--r--arch/mips/kernel/traps.c2
-rw-r--r--arch/mips/kernel/watch.c8
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_isa.c14
-rw-r--r--arch/mips/mm/cerr-sb1.c4
-rw-r--r--arch/mips/mm/tlbex.c56
-rw-r--r--arch/mips/mti-malta/malta-reset.c33
-rw-r--r--arch/mips/mti-sead3/sead3-reset.c5
-rw-r--r--arch/mips/pci/pci-ip27.c2
-rw-r--r--arch/mips/sgi-ip27/Makefile1
-rw-r--r--arch/mips/sgi-ip27/ip27-irq-pci.c266
-rw-r--r--arch/mips/sgi-ip27/ip27-irq.c214
-rw-r--r--arch/mips/sibyte/Kconfig3
-rw-r--r--arch/mips/sibyte/Platform1
-rw-r--r--arch/mips/sibyte/common/Makefile1
-rw-r--r--arch/mips/sibyte/common/bus_watcher.c (renamed from arch/mips/sibyte/sb1250/bus_watcher.c)14
-rw-r--r--arch/mips/sibyte/common/sb_tbprof.c1
-rw-r--r--arch/mips/sibyte/sb1250/Makefile1
-rw-r--r--arch/mips/sni/pcimt.c2
-rw-r--r--arch/mips/sni/pcit.c16
42 files changed, 503 insertions, 362 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 1e7a40e00bc0..5589699aa832 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -420,7 +420,6 @@ config POWERTV
420 select CSRC_POWERTV 420 select CSRC_POWERTV
421 select DMA_NONCOHERENT 421 select DMA_NONCOHERENT
422 select HW_HAS_PCI 422 select HW_HAS_PCI
423 select SYS_HAS_EARLY_PRINTK
424 select SYS_HAS_CPU_MIPS32_R2 423 select SYS_HAS_CPU_MIPS32_R2
425 select SYS_SUPPORTS_32BIT_KERNEL 424 select SYS_SUPPORTS_32BIT_KERNEL
426 select SYS_SUPPORTS_BIG_ENDIAN 425 select SYS_SUPPORTS_BIG_ENDIAN
diff --git a/arch/mips/ath79/mach-ap136.c b/arch/mips/ath79/mach-ap136.c
index 479dd4b1d0d2..07eac58c3641 100644
--- a/arch/mips/ath79/mach-ap136.c
+++ b/arch/mips/ath79/mach-ap136.c
@@ -132,7 +132,7 @@ static void __init ap136_pci_init(u8 *eeprom)
132 ath79_register_pci(); 132 ath79_register_pci();
133} 133}
134#else 134#else
135static inline void ap136_pci_init(void) {} 135static inline void ap136_pci_init(u8 *eeprom) {}
136#endif /* CONFIG_PCI */ 136#endif /* CONFIG_PCI */
137 137
138static void __init ap136_setup(void) 138static void __init ap136_setup(void)
diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig
index afe52d4ed3b9..b78306ce56c7 100644
--- a/arch/mips/bcm63xx/Kconfig
+++ b/arch/mips/bcm63xx/Kconfig
@@ -12,14 +12,9 @@ config BCM63XX_CPU_6328
12config BCM63XX_CPU_6338 12config BCM63XX_CPU_6338
13 bool "support 6338 CPU" 13 bool "support 6338 CPU"
14 select HW_HAS_PCI 14 select HW_HAS_PCI
15 select USB_ARCH_HAS_OHCI
16 select USB_OHCI_BIG_ENDIAN_DESC
17 select USB_OHCI_BIG_ENDIAN_MMIO
18 15
19config BCM63XX_CPU_6345 16config BCM63XX_CPU_6345
20 bool "support 6345 CPU" 17 bool "support 6345 CPU"
21 select USB_OHCI_BIG_ENDIAN_DESC
22 select USB_OHCI_BIG_ENDIAN_MMIO
23 18
24config BCM63XX_CPU_6348 19config BCM63XX_CPU_6348
25 bool "support 6348 CPU" 20 bool "support 6348 CPU"
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index b703583779fb..4e952043c922 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -13,10 +13,11 @@ CFLAGS_octeon-platform.o = -I$(src)/../../../scripts/dtc/libfdt
13CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt 13CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt
14 14
15obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o 15obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o
16obj-y += dma-octeon.o flash_setup.o 16obj-y += dma-octeon.o
17obj-y += octeon-memcpy.o 17obj-y += octeon-memcpy.o
18obj-y += executive/ 18obj-y += executive/
19 19
20obj-$(CONFIG_MTD) += flash_setup.o
20obj-$(CONFIG_SMP) += smp.o 21obj-$(CONFIG_SMP) += smp.o
21obj-$(CONFIG_OCTEON_ILM) += oct_ilm.o 22obj-$(CONFIG_OCTEON_ILM) += oct_ilm.o
22 23
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 0acc8ef86907..48b08eb9d9e4 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -7,6 +7,7 @@
7 * Copyright (C) 2008, 2009 Wind River Systems 7 * Copyright (C) 2008, 2009 Wind River Systems
8 * written by Ralf Baechle <ralf@linux-mips.org> 8 * written by Ralf Baechle <ralf@linux-mips.org>
9 */ 9 */
10#include <linux/compiler.h>
10#include <linux/init.h> 11#include <linux/init.h>
11#include <linux/kernel.h> 12#include <linux/kernel.h>
12#include <linux/console.h> 13#include <linux/console.h>
@@ -694,7 +695,7 @@ void __init prom_init(void)
694 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) { 695 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) {
695 pr_info("Skipping L2 locking due to reduced L2 cache size\n"); 696 pr_info("Skipping L2 locking due to reduced L2 cache size\n");
696 } else { 697 } else {
697 uint32_t ebase = read_c0_ebase() & 0x3ffff000; 698 uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000;
698#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB 699#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB
699 /* TLB refill */ 700 /* TLB refill */
700 cvmx_l2c_lock_mem_region(ebase, 0x100); 701 cvmx_l2c_lock_mem_region(ebase, 0x100);
@@ -978,7 +979,7 @@ void __init plat_mem_setup(void)
978 cvmx_bootmem_unlock(); 979 cvmx_bootmem_unlock();
979 /* Add the memory region for the kernel. */ 980 /* Add the memory region for the kernel. */
980 kernel_start = (unsigned long) _text; 981 kernel_start = (unsigned long) _text;
981 kernel_size = ALIGN(_end - _text, 0x100000); 982 kernel_size = _end - _text;
982 983
983 /* Adjust for physical offset. */ 984 /* Adjust for physical offset. */
984 kernel_start &= ~0xffffffff80000000ULL; 985 kernel_start &= ~0xffffffff80000000ULL;
diff --git a/arch/mips/fw/cfe/cfe_api.c b/arch/mips/fw/cfe/cfe_api.c
index d06dc5a6b8d3..cf84f01931c5 100644
--- a/arch/mips/fw/cfe/cfe_api.c
+++ b/arch/mips/fw/cfe/cfe_api.c
@@ -406,12 +406,12 @@ int cfe_setenv(char *name, char *val)
406 return xiocb.xiocb_status; 406 return xiocb.xiocb_status;
407} 407}
408 408
409int cfe_write(int handle, unsigned char *buffer, int length) 409int cfe_write(int handle, const char *buffer, int length)
410{ 410{
411 return cfe_writeblk(handle, 0, buffer, length); 411 return cfe_writeblk(handle, 0, buffer, length);
412} 412}
413 413
414int cfe_writeblk(int handle, s64 offset, unsigned char *buffer, int length) 414int cfe_writeblk(int handle, s64 offset, const char *buffer, int length)
415{ 415{
416 struct cfe_xiocb xiocb; 416 struct cfe_xiocb xiocb;
417 417
diff --git a/arch/mips/include/asm/fw/cfe/cfe_api.h b/arch/mips/include/asm/fw/cfe/cfe_api.h
index 17347551a1b2..a0ea69e91e2e 100644
--- a/arch/mips/include/asm/fw/cfe/cfe_api.h
+++ b/arch/mips/include/asm/fw/cfe/cfe_api.h
@@ -115,8 +115,8 @@ int cfe_read(int handle, unsigned char *buffer, int length);
115int cfe_readblk(int handle, int64_t offset, unsigned char *buffer, 115int cfe_readblk(int handle, int64_t offset, unsigned char *buffer,
116 int length); 116 int length);
117int cfe_setenv(char *name, char *val); 117int cfe_setenv(char *name, char *val);
118int cfe_write(int handle, unsigned char *buffer, int length); 118int cfe_write(int handle, const char *buffer, int length);
119int cfe_writeblk(int handle, int64_t offset, unsigned char *buffer, 119int cfe_writeblk(int handle, int64_t offset, const char *buffer,
120 int length); 120 int length);
121 121
122#endif /* CFE_API_H */ 122#endif /* CFE_API_H */
diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
index be8fb4240cec..47fb247f9663 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
@@ -13,6 +13,8 @@
13#ifndef __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H 13#ifndef __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
14#define __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H 14#define __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
15 15
16#include <linux/bug.h>
17
16struct device; 18struct device;
17 19
18extern void octeon_pci_dma_init(void); 20extern void octeon_pci_dma_init(void);
@@ -21,18 +23,21 @@ static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
21 size_t size) 23 size_t size)
22{ 24{
23 BUG(); 25 BUG();
26 return 0;
24} 27}
25 28
26static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, 29static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
27 struct page *page) 30 struct page *page)
28{ 31{
29 BUG(); 32 BUG();
33 return 0;
30} 34}
31 35
32static inline unsigned long plat_dma_addr_to_phys(struct device *dev, 36static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
33 dma_addr_t dma_addr) 37 dma_addr_t dma_addr)
34{ 38{
35 BUG(); 39 BUG();
40 return 0;
36} 41}
37 42
38static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, 43static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
@@ -44,6 +49,7 @@ static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
44static inline int plat_dma_supported(struct device *dev, u64 mask) 49static inline int plat_dma_supported(struct device *dev, u64 mask)
45{ 50{
46 BUG(); 51 BUG();
52 return 0;
47} 53}
48 54
49static inline void plat_extra_sync_for_device(struct device *dev) 55static inline void plat_extra_sync_for_device(struct device *dev)
@@ -60,6 +66,7 @@ static inline int plat_dma_mapping_error(struct device *dev,
60 dma_addr_t dma_addr) 66 dma_addr_t dma_addr)
61{ 67{
62 BUG(); 68 BUG();
69 return 0;
63} 70}
64 71
65dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr); 72dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);
diff --git a/arch/mips/include/asm/mach-cavium-octeon/spaces.h b/arch/mips/include/asm/mach-cavium-octeon/spaces.h
new file mode 100644
index 000000000000..daa91accf5ab
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/spaces.h
@@ -0,0 +1,24 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 Cavium, Inc.
7 */
8#ifndef _ASM_MACH_CAVIUM_OCTEON_SPACES_H
9#define _ASM_MACH_CAVIUM_OCTEON_SPACES_H
10
11#include <linux/const.h>
12
13#ifdef CONFIG_64BIT
14/* They are all the same and some OCTEON II cores cannot handle 0xa8.. */
15#define CAC_BASE _AC(0x8000000000000000, UL)
16#define UNCAC_BASE _AC(0x8000000000000000, UL)
17#define IO_BASE _AC(0x8000000000000000, UL)
18
19
20#endif /* CONFIG_64BIT */
21
22#include <asm/mach-generic/spaces.h>
23
24#endif /* _ASM_MACH_CAVIUM_OCTEON_SPACES_H */
diff --git a/arch/mips/include/asm/mach-ip27/kernel-entry-init.h b/arch/mips/include/asm/mach-ip27/kernel-entry-init.h
index a323efb720dc..b087cb83da3a 100644
--- a/arch/mips/include/asm/mach-ip27/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-ip27/kernel-entry-init.h
@@ -24,6 +24,53 @@
24 .endm 24 .endm
25 25
26/* 26/*
27 * TLB bits
28 */
29#define PAGE_GLOBAL (1 << 6)
30#define PAGE_VALID (1 << 7)
31#define PAGE_DIRTY (1 << 8)
32#define CACHE_CACHABLE_COW (5 << 9)
33
34 /*
35 * inputs are the text nasid in t1, data nasid in t2.
36 */
37 .macro MAPPED_KERNEL_SETUP_TLB
38#ifdef CONFIG_MAPPED_KERNEL
39 /*
40 * This needs to read the nasid - assume 0 for now.
41 * Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0,
42 * 0+DVG in tlblo_1.
43 */
44 dli t0, 0xffffffffc0000000
45 dmtc0 t0, CP0_ENTRYHI
46 li t0, 0x1c000 # Offset of text into node memory
47 dsll t1, NASID_SHFT # Shift text nasid into place
48 dsll t2, NASID_SHFT # Same for data nasid
49 or t1, t1, t0 # Physical load address of kernel text
50 or t2, t2, t0 # Physical load address of kernel data
51 dsrl t1, 12 # 4K pfn
52 dsrl t2, 12 # 4K pfn
53 dsll t1, 6 # Get pfn into place
54 dsll t2, 6 # Get pfn into place
55 li t0, ((PAGE_GLOBAL | PAGE_VALID | CACHE_CACHABLE_COW) >> 6)
56 or t0, t0, t1
57 mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr
58 li t0, ((PAGE_GLOBAL | PAGE_VALID | PAGE_DIRTY | CACHE_CACHABLE_COW) >> 6)
59 or t0, t0, t2
60 mtc0 t0, CP0_ENTRYLO1 # physaddr, DVG, cach exlwr
61 li t0, 0x1ffe000 # MAPPED_KERN_TLBMASK, TLBPGMASK_16M
62 mtc0 t0, CP0_PAGEMASK
63 li t0, 0 # KMAP_INX
64 mtc0 t0, CP0_INDEX
65 li t0, 1
66 mtc0 t0, CP0_WIRED
67 tlbwi
68#else
69 mtc0 zero, CP0_WIRED
70#endif
71 .endm
72
73/*
27 * Intentionally empty macro, used in head.S. Override in 74 * Intentionally empty macro, used in head.S. Override in
28 * arch/mips/mach-xxx/kernel-entry-init.h when necessary. 75 * arch/mips/mach-xxx/kernel-entry-init.h when necessary.
29 */ 76 */
diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h
index bd9746fbe4af..48616816bcbc 100644
--- a/arch/mips/include/asm/mips-boards/generic.h
+++ b/arch/mips/include/asm/mips-boards/generic.h
@@ -24,12 +24,6 @@
24#define ASCII_DISPLAY_POS_BASE 0x1f000418 24#define ASCII_DISPLAY_POS_BASE 0x1f000418
25 25
26/* 26/*
27 * Reset register.
28 */
29#define SOFTRES_REG 0x1f000500
30#define GORESET 0x42
31
32/*
33 * Revision register. 27 * Revision register.
34 */ 28 */
35#define MIPS_REVISION_REG 0x1fc00010 29#define MIPS_REVISION_REG 0x1fc00010
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 1fed8bdcf2a0..3b29079b5424 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -113,7 +113,7 @@ get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
113 if (! ((asid += ASID_INC) & ASID_MASK) ) { 113 if (! ((asid += ASID_INC) & ASID_MASK) ) {
114 if (cpu_has_vtag_icache) 114 if (cpu_has_vtag_icache)
115 flush_icache_all(); 115 flush_icache_all();
116#ifdef CONFIG_VIRTUALIZATION 116#ifdef CONFIG_KVM
117 kvm_local_flush_tlb_all(); /* start new asid cycle */ 117 kvm_local_flush_tlb_all(); /* start new asid cycle */
118#else 118#else
119 local_flush_tlb_all(); /* start new asid cycle */ 119 local_flush_tlb_all(); /* start new asid cycle */
diff --git a/arch/mips/include/asm/xtalk/xtalk.h b/arch/mips/include/asm/xtalk/xtalk.h
index 680e7efebbaf..26d2ed1fa917 100644
--- a/arch/mips/include/asm/xtalk/xtalk.h
+++ b/arch/mips/include/asm/xtalk/xtalk.h
@@ -47,6 +47,15 @@ typedef struct xtalk_piomap_s *xtalk_piomap_t;
47#define XIO_PORT(x) ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT)) 47#define XIO_PORT(x) ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT))
48#define XIO_PACK(p, o) ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS)) 48#define XIO_PACK(p, o) ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS))
49 49
50#ifdef CONFIG_PCI
51extern int bridge_probe(nasid_t nasid, int widget, int masterwid);
52#else
53static inline int bridge_probe(nasid_t nasid, int widget, int masterwid)
54{
55 return 0;
56}
57#endif
58
50#endif /* !__ASSEMBLY__ */ 59#endif /* !__ASSEMBLY__ */
51 60
52#endif /* _ASM_XTALK_XTALK_H */ 61#endif /* _ASM_XTALK_XTALK_H */
diff --git a/arch/mips/include/uapi/asm/fcntl.h b/arch/mips/include/uapi/asm/fcntl.h
index 314c79b76d2a..6ca432f00860 100644
--- a/arch/mips/include/uapi/asm/fcntl.h
+++ b/arch/mips/include/uapi/asm/fcntl.h
@@ -8,6 +8,7 @@
8#ifndef _UAPI_ASM_FCNTL_H 8#ifndef _UAPI_ASM_FCNTL_H
9#define _UAPI_ASM_FCNTL_H 9#define _UAPI_ASM_FCNTL_H
10 10
11#include <asm/sgidefs.h>
11 12
12#define O_APPEND 0x0008 13#define O_APPEND 0x0008
13#define O_DSYNC 0x0010 /* used to be O_SYNC, see below */ 14#define O_DSYNC 0x0010 /* used to be O_SYNC, see below */
@@ -55,7 +56,8 @@
55 * contain all the same fields as struct flock. 56 * contain all the same fields as struct flock.
56 */ 57 */
57 58
58#ifdef CONFIG_32BIT 59#if _MIPS_SIM != _MIPS_SIM_ABI64
60
59#include <linux/types.h> 61#include <linux/types.h>
60 62
61struct flock { 63struct flock {
@@ -70,7 +72,7 @@ struct flock {
70 72
71#define HAVE_ARCH_STRUCT_FLOCK 73#define HAVE_ARCH_STRUCT_FLOCK
72 74
73#endif /* CONFIG_32BIT */ 75#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
74 76
75#include <asm-generic/fcntl.h> 77#include <asm-generic/fcntl.h>
76 78
diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index 0f4aec2ad1e6..e5a676e3d3c0 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -409,10 +409,11 @@ enum mm_32f_73_minor_op {
409enum mm_16c_minor_op { 409enum mm_16c_minor_op {
410 mm_lwm16_op = 0x04, 410 mm_lwm16_op = 0x04,
411 mm_swm16_op = 0x05, 411 mm_swm16_op = 0x05,
412 mm_jr16_op = 0x18, 412 mm_jr16_op = 0x0c,
413 mm_jrc_op = 0x1a, 413 mm_jrc_op = 0x0d,
414 mm_jalr16_op = 0x1c, 414 mm_jalr16_op = 0x0e,
415 mm_jalrs16_op = 0x1e, 415 mm_jalrs16_op = 0x0f,
416 mm_jraddiusp_op = 0x18,
416}; 417};
417 418
418/* 419/*
diff --git a/arch/mips/include/uapi/asm/msgbuf.h b/arch/mips/include/uapi/asm/msgbuf.h
index 0d6c7f14de31..df849e87d9ae 100644
--- a/arch/mips/include/uapi/asm/msgbuf.h
+++ b/arch/mips/include/uapi/asm/msgbuf.h
@@ -14,25 +14,25 @@
14 14
15struct msqid64_ds { 15struct msqid64_ds {
16 struct ipc64_perm msg_perm; 16 struct ipc64_perm msg_perm;
17#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN) 17#if !defined(__mips64) && defined(__MIPSEB__)
18 unsigned long __unused1; 18 unsigned long __unused1;
19#endif 19#endif
20 __kernel_time_t msg_stime; /* last msgsnd time */ 20 __kernel_time_t msg_stime; /* last msgsnd time */
21#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN) 21#if !defined(__mips64) && defined(__MIPSEL__)
22 unsigned long __unused1; 22 unsigned long __unused1;
23#endif 23#endif
24#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN) 24#if !defined(__mips64) && defined(__MIPSEB__)
25 unsigned long __unused2; 25 unsigned long __unused2;
26#endif 26#endif
27 __kernel_time_t msg_rtime; /* last msgrcv time */ 27 __kernel_time_t msg_rtime; /* last msgrcv time */
28#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN) 28#if !defined(__mips64) && defined(__MIPSEL__)
29 unsigned long __unused2; 29 unsigned long __unused2;
30#endif 30#endif
31#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN) 31#if !defined(__mips64) && defined(__MIPSEB__)
32 unsigned long __unused3; 32 unsigned long __unused3;
33#endif 33#endif
34 __kernel_time_t msg_ctime; /* last change time */ 34 __kernel_time_t msg_ctime; /* last change time */
35#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN) 35#if !defined(__mips64) && defined(__MIPSEL__)
36 unsigned long __unused3; 36 unsigned long __unused3;
37#endif 37#endif
38 unsigned long msg_cbytes; /* current number of bytes on queue */ 38 unsigned long msg_cbytes; /* current number of bytes on queue */
diff --git a/arch/mips/include/uapi/asm/resource.h b/arch/mips/include/uapi/asm/resource.h
index 87cb3085269c..b26439d4ab0b 100644
--- a/arch/mips/include/uapi/asm/resource.h
+++ b/arch/mips/include/uapi/asm/resource.h
@@ -26,7 +26,7 @@
26 * but we keep the old value on MIPS32, 26 * but we keep the old value on MIPS32,
27 * for compatibility: 27 * for compatibility:
28 */ 28 */
29#ifdef CONFIG_32BIT 29#ifndef __mips64
30# define RLIM_INFINITY 0x7fffffffUL 30# define RLIM_INFINITY 0x7fffffffUL
31#endif 31#endif
32 32
diff --git a/arch/mips/include/uapi/asm/siginfo.h b/arch/mips/include/uapi/asm/siginfo.h
index 6a8714193fb9..b7a23064841f 100644
--- a/arch/mips/include/uapi/asm/siginfo.h
+++ b/arch/mips/include/uapi/asm/siginfo.h
@@ -25,10 +25,10 @@ struct siginfo;
25/* 25/*
26 * Careful to keep union _sifields from shifting ... 26 * Careful to keep union _sifields from shifting ...
27 */ 27 */
28#ifdef CONFIG_32BIT 28#if __SIZEOF_LONG__ == 4
29#define __ARCH_SI_PREAMBLE_SIZE (3 * sizeof(int)) 29#define __ARCH_SI_PREAMBLE_SIZE (3 * sizeof(int))
30#endif 30#endif
31#ifdef CONFIG_64BIT 31#if __SIZEOF_LONG__ == 8
32#define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int)) 32#define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
33#endif 33#endif
34 34
diff --git a/arch/mips/include/uapi/asm/swab.h b/arch/mips/include/uapi/asm/swab.h
index 97c2f81b4b43..ac9a8f9cd1fb 100644
--- a/arch/mips/include/uapi/asm/swab.h
+++ b/arch/mips/include/uapi/asm/swab.h
@@ -13,7 +13,7 @@
13 13
14#define __SWAB_64_THRU_32__ 14#define __SWAB_64_THRU_32__
15 15
16#ifdef CONFIG_CPU_MIPSR2 16#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
17 17
18static inline __attribute_const__ __u16 __arch_swab16(__u16 x) 18static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
19{ 19{
@@ -39,10 +39,10 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
39#define __arch_swab32 __arch_swab32 39#define __arch_swab32 __arch_swab32
40 40
41/* 41/*
42 * Having already checked for CONFIG_CPU_MIPSR2, enable the 42 * Having already checked for MIPS R2, enable the optimized version for
43 * optimized version for 64-bit kernel on r2 CPUs. 43 * 64-bit kernel on r2 CPUs.
44 */ 44 */
45#ifdef CONFIG_64BIT 45#ifdef __mips64
46static inline __attribute_const__ __u64 __arch_swab64(__u64 x) 46static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
47{ 47{
48 __asm__( 48 __asm__(
@@ -54,6 +54,6 @@ static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
54 return x; 54 return x;
55} 55}
56#define __arch_swab64 __arch_swab64 56#define __arch_swab64 __arch_swab64
57#endif /* CONFIG_64BIT */ 57#endif /* __mips64 */
58#endif /* CONFIG_CPU_MIPSR2 */ 58#endif /* MIPS R2 or newer */
59#endif /* _ASM_SWAB_H */ 59#endif /* _ASM_SWAB_H */
diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c
index cf5509f13dd5..dba90ec0dc38 100644
--- a/arch/mips/kernel/ftrace.c
+++ b/arch/mips/kernel/ftrace.c
@@ -25,12 +25,16 @@
25#define MCOUNT_OFFSET_INSNS 4 25#define MCOUNT_OFFSET_INSNS 4
26#endif 26#endif
27 27
28#ifdef CONFIG_DYNAMIC_FTRACE
29
28/* Arch override because MIPS doesn't need to run this from stop_machine() */ 30/* Arch override because MIPS doesn't need to run this from stop_machine() */
29void arch_ftrace_update_code(int command) 31void arch_ftrace_update_code(int command)
30{ 32{
31 ftrace_modify_all_code(command); 33 ftrace_modify_all_code(command);
32} 34}
33 35
36#endif
37
34/* 38/*
35 * Check if the address is in kernel space 39 * Check if the address is in kernel space
36 * 40 *
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index c61cdaed2b1d..099912324423 100644
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -28,45 +28,6 @@
28#include <kernel-entry-init.h> 28#include <kernel-entry-init.h>
29 29
30 /* 30 /*
31 * inputs are the text nasid in t1, data nasid in t2.
32 */
33 .macro MAPPED_KERNEL_SETUP_TLB
34#ifdef CONFIG_MAPPED_KERNEL
35 /*
36 * This needs to read the nasid - assume 0 for now.
37 * Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0,
38 * 0+DVG in tlblo_1.
39 */
40 dli t0, 0xffffffffc0000000
41 dmtc0 t0, CP0_ENTRYHI
42 li t0, 0x1c000 # Offset of text into node memory
43 dsll t1, NASID_SHFT # Shift text nasid into place
44 dsll t2, NASID_SHFT # Same for data nasid
45 or t1, t1, t0 # Physical load address of kernel text
46 or t2, t2, t0 # Physical load address of kernel data
47 dsrl t1, 12 # 4K pfn
48 dsrl t2, 12 # 4K pfn
49 dsll t1, 6 # Get pfn into place
50 dsll t2, 6 # Get pfn into place
51 li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _CACHE_CACHABLE_COW) >> 6)
52 or t0, t0, t1
53 mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr
54 li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _PAGE_DIRTY|_CACHE_CACHABLE_COW) >> 6)
55 or t0, t0, t2
56 mtc0 t0, CP0_ENTRYLO1 # physaddr, DVG, cach exlwr
57 li t0, 0x1ffe000 # MAPPED_KERN_TLBMASK, TLBPGMASK_16M
58 mtc0 t0, CP0_PAGEMASK
59 li t0, 0 # KMAP_INX
60 mtc0 t0, CP0_INDEX
61 li t0, 1
62 mtc0 t0, CP0_WIRED
63 tlbwi
64#else
65 mtc0 zero, CP0_WIRED
66#endif
67 .endm
68
69 /*
70 * For the moment disable interrupts, mark the kernel mode and 31 * For the moment disable interrupts, mark the kernel mode and
71 * set ST0_KX so that the CPU does not spit fire when using 32 * set ST0_KX so that the CPU does not spit fire when using
72 * 64-bit addresses. A full initialization of the CPU's status 33 * 64-bit addresses. A full initialization of the CPU's status
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 3b09b888afa9..0c655deeea4a 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -93,26 +93,27 @@ static void rm7k_wait_irqoff(void)
93} 93}
94 94
95/* 95/*
96 * The Au1xxx wait is available only if using 32khz counter or 96 * Au1 'wait' is only useful when the 32kHz counter is used as timer,
97 * external timer source, but specifically not CP0 Counter. 97 * since coreclock (and the cp0 counter) stops upon executing it. Only an
98 * alchemy/common/time.c may override cpu_wait! 98 * interrupt can wake it, so they must be enabled before entering idle modes.
99 */ 99 */
100static void au1k_wait(void) 100static void au1k_wait(void)
101{ 101{
102 unsigned long c0status = read_c0_status() | 1; /* irqs on */
103
102 __asm__( 104 __asm__(
103 " .set mips3 \n" 105 " .set mips3 \n"
104 " cache 0x14, 0(%0) \n" 106 " cache 0x14, 0(%0) \n"
105 " cache 0x14, 32(%0) \n" 107 " cache 0x14, 32(%0) \n"
106 " sync \n" 108 " sync \n"
107 " nop \n" 109 " mtc0 %1, $12 \n" /* wr c0status */
108 " wait \n" 110 " wait \n"
109 " nop \n" 111 " nop \n"
110 " nop \n" 112 " nop \n"
111 " nop \n" 113 " nop \n"
112 " nop \n" 114 " nop \n"
113 " .set mips0 \n" 115 " .set mips0 \n"
114 : : "r" (au1k_wait)); 116 : : "r" (au1k_wait), "r" (c0status));
115 local_irq_enable();
116} 117}
117 118
118static int __initdata nowait; 119static int __initdata nowait;
diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c
index 6fa198db8999..d763f11e35e2 100644
--- a/arch/mips/kernel/rtlx.c
+++ b/arch/mips/kernel/rtlx.c
@@ -437,7 +437,6 @@ static ssize_t file_write(struct file *file, const char __user * buffer,
437 size_t count, loff_t * ppos) 437 size_t count, loff_t * ppos)
438{ 438{
439 int minor = iminor(file_inode(file)); 439 int minor = iminor(file_inode(file));
440 struct rtlx_channel *rt = &rtlx->channel[minor];
441 440
442 /* any space left... */ 441 /* any space left... */
443 if (!rtlx_write_poll(minor)) { 442 if (!rtlx_write_poll(minor)) {
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index b0f3ad26063e..0903d70b2cfe 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1668,7 +1668,6 @@ void *set_vi_handler(int n, vi_handler_t addr)
1668} 1668}
1669 1669
1670extern void tlb_init(void); 1670extern void tlb_init(void);
1671extern void flush_tlb_handlers(void);
1672 1671
1673/* 1672/*
1674 * Timer interrupt 1673 * Timer interrupt
@@ -2006,7 +2005,6 @@ void __init trap_init(void)
2006 set_handler(0x080, &except_vec3_generic, 0x80); 2005 set_handler(0x080, &except_vec3_generic, 0x80);
2007 2006
2008 local_flush_icache_range(ebase, ebase + 0x400); 2007 local_flush_icache_range(ebase, ebase + 0x400);
2009 flush_tlb_handlers();
2010 2008
2011 sort_extable(__start___dbe_table, __stop___dbe_table); 2009 sort_extable(__start___dbe_table, __stop___dbe_table);
2012 2010
diff --git a/arch/mips/kernel/watch.c b/arch/mips/kernel/watch.c
index 7726f6157d9e..cbdc4de85bb4 100644
--- a/arch/mips/kernel/watch.c
+++ b/arch/mips/kernel/watch.c
@@ -111,6 +111,7 @@ __cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c)
111 * disable the register. 111 * disable the register.
112 */ 112 */
113 write_c0_watchlo0(7); 113 write_c0_watchlo0(7);
114 back_to_back_c0_hazard();
114 t = read_c0_watchlo0(); 115 t = read_c0_watchlo0();
115 write_c0_watchlo0(0); 116 write_c0_watchlo0(0);
116 c->watch_reg_masks[0] = t & 7; 117 c->watch_reg_masks[0] = t & 7;
@@ -121,12 +122,14 @@ __cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c)
121 c->watch_reg_use_cnt = 1; 122 c->watch_reg_use_cnt = 1;
122 t = read_c0_watchhi0(); 123 t = read_c0_watchhi0();
123 write_c0_watchhi0(t | 0xff8); 124 write_c0_watchhi0(t | 0xff8);
125 back_to_back_c0_hazard();
124 t = read_c0_watchhi0(); 126 t = read_c0_watchhi0();
125 c->watch_reg_masks[0] |= (t & 0xff8); 127 c->watch_reg_masks[0] |= (t & 0xff8);
126 if ((t & 0x80000000) == 0) 128 if ((t & 0x80000000) == 0)
127 return; 129 return;
128 130
129 write_c0_watchlo1(7); 131 write_c0_watchlo1(7);
132 back_to_back_c0_hazard();
130 t = read_c0_watchlo1(); 133 t = read_c0_watchlo1();
131 write_c0_watchlo1(0); 134 write_c0_watchlo1(0);
132 c->watch_reg_masks[1] = t & 7; 135 c->watch_reg_masks[1] = t & 7;
@@ -135,12 +138,14 @@ __cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c)
135 c->watch_reg_use_cnt = 2; 138 c->watch_reg_use_cnt = 2;
136 t = read_c0_watchhi1(); 139 t = read_c0_watchhi1();
137 write_c0_watchhi1(t | 0xff8); 140 write_c0_watchhi1(t | 0xff8);
141 back_to_back_c0_hazard();
138 t = read_c0_watchhi1(); 142 t = read_c0_watchhi1();
139 c->watch_reg_masks[1] |= (t & 0xff8); 143 c->watch_reg_masks[1] |= (t & 0xff8);
140 if ((t & 0x80000000) == 0) 144 if ((t & 0x80000000) == 0)
141 return; 145 return;
142 146
143 write_c0_watchlo2(7); 147 write_c0_watchlo2(7);
148 back_to_back_c0_hazard();
144 t = read_c0_watchlo2(); 149 t = read_c0_watchlo2();
145 write_c0_watchlo2(0); 150 write_c0_watchlo2(0);
146 c->watch_reg_masks[2] = t & 7; 151 c->watch_reg_masks[2] = t & 7;
@@ -149,12 +154,14 @@ __cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c)
149 c->watch_reg_use_cnt = 3; 154 c->watch_reg_use_cnt = 3;
150 t = read_c0_watchhi2(); 155 t = read_c0_watchhi2();
151 write_c0_watchhi2(t | 0xff8); 156 write_c0_watchhi2(t | 0xff8);
157 back_to_back_c0_hazard();
152 t = read_c0_watchhi2(); 158 t = read_c0_watchhi2();
153 c->watch_reg_masks[2] |= (t & 0xff8); 159 c->watch_reg_masks[2] |= (t & 0xff8);
154 if ((t & 0x80000000) == 0) 160 if ((t & 0x80000000) == 0)
155 return; 161 return;
156 162
157 write_c0_watchlo3(7); 163 write_c0_watchlo3(7);
164 back_to_back_c0_hazard();
158 t = read_c0_watchlo3(); 165 t = read_c0_watchlo3();
159 write_c0_watchlo3(0); 166 write_c0_watchlo3(0);
160 c->watch_reg_masks[3] = t & 7; 167 c->watch_reg_masks[3] = t & 7;
@@ -163,6 +170,7 @@ __cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c)
163 c->watch_reg_use_cnt = 4; 170 c->watch_reg_use_cnt = 4;
164 t = read_c0_watchhi3(); 171 t = read_c0_watchhi3();
165 write_c0_watchhi3(t | 0xff8); 172 write_c0_watchhi3(t | 0xff8);
173 back_to_back_c0_hazard();
166 t = read_c0_watchhi3(); 174 t = read_c0_watchhi3();
167 c->watch_reg_masks[3] |= (t & 0xff8); 175 c->watch_reg_masks[3] |= (t & 0xff8);
168 if ((t & 0x80000000) == 0) 176 if ((t & 0x80000000) == 0)
diff --git a/arch/mips/loongson/common/cs5536/cs5536_isa.c b/arch/mips/loongson/common/cs5536/cs5536_isa.c
index a6eb2e853d94..924be39e7733 100644
--- a/arch/mips/loongson/common/cs5536/cs5536_isa.c
+++ b/arch/mips/loongson/common/cs5536/cs5536_isa.c
@@ -13,6 +13,7 @@
13 * option) any later version. 13 * option) any later version.
14 */ 14 */
15 15
16#include <linux/pci.h>
16#include <cs5536/cs5536.h> 17#include <cs5536/cs5536.h>
17#include <cs5536/cs5536_pci.h> 18#include <cs5536/cs5536_pci.h>
18 19
@@ -314,3 +315,16 @@ u32 pci_isa_read_reg(int reg)
314 315
315 return conf_data; 316 return conf_data;
316} 317}
318
319/*
320 * The mfgpt timer interrupt is running early, so we must keep the south bridge
321 * mmio always enabled. Otherwise we may race with the PCI configuration which
322 * may temporarily disable it. When that happens and the timer interrupt fires,
323 * we are not able to clear it and the system will hang.
324 */
325static void cs5536_isa_mmio_always_on(struct pci_dev *dev)
326{
327 dev->mmio_always_on = 1;
328}
329DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA,
330 PCI_CLASS_BRIDGE_ISA, 8, cs5536_isa_mmio_always_on);
diff --git a/arch/mips/mm/cerr-sb1.c b/arch/mips/mm/cerr-sb1.c
index 576add33bf5b..ee5c1ff861ae 100644
--- a/arch/mips/mm/cerr-sb1.c
+++ b/arch/mips/mm/cerr-sb1.c
@@ -182,11 +182,7 @@ asmlinkage void sb1_cache_error(void)
182 182
183#ifdef CONFIG_SIBYTE_BW_TRACE 183#ifdef CONFIG_SIBYTE_BW_TRACE
184 /* Freeze the trace buffer now */ 184 /* Freeze the trace buffer now */
185#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
186 csr_out32(M_BCM1480_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG));
187#else
188 csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG)); 185 csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG));
189#endif
190 printk("Trace buffer frozen\n"); 186 printk("Trace buffer frozen\n");
191#endif 187#endif
192 188
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 357e0fd65e94..9ab0f907a52c 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -1948,6 +1948,19 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
1948 uasm_i_nop(&p); 1948 uasm_i_nop(&p);
1949 1949
1950 uasm_i_tlbr(&p); 1950 uasm_i_tlbr(&p);
1951
1952 switch (current_cpu_type()) {
1953 default:
1954 if (cpu_has_mips_r2) {
1955 uasm_i_ehb(&p);
1956
1957 case CPU_CAVIUM_OCTEON:
1958 case CPU_CAVIUM_OCTEON_PLUS:
1959 case CPU_CAVIUM_OCTEON2:
1960 break;
1961 }
1962 }
1963
1951 /* Examine entrylo 0 or 1 based on ptr. */ 1964 /* Examine entrylo 0 or 1 based on ptr. */
1952 if (use_bbit_insns()) { 1965 if (use_bbit_insns()) {
1953 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); 1966 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
@@ -2002,6 +2015,19 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
2002 uasm_i_nop(&p); 2015 uasm_i_nop(&p);
2003 2016
2004 uasm_i_tlbr(&p); 2017 uasm_i_tlbr(&p);
2018
2019 switch (current_cpu_type()) {
2020 default:
2021 if (cpu_has_mips_r2) {
2022 uasm_i_ehb(&p);
2023
2024 case CPU_CAVIUM_OCTEON:
2025 case CPU_CAVIUM_OCTEON_PLUS:
2026 case CPU_CAVIUM_OCTEON2:
2027 break;
2028 }
2029 }
2030
2005 /* Examine entrylo 0 or 1 based on ptr. */ 2031 /* Examine entrylo 0 or 1 based on ptr. */
2006 if (use_bbit_insns()) { 2032 if (use_bbit_insns()) {
2007 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); 2033 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
@@ -2170,6 +2196,20 @@ static void __cpuinit build_r4000_tlb_modify_handler(void)
2170 dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_size); 2196 dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_size);
2171} 2197}
2172 2198
2199static void __cpuinit flush_tlb_handlers(void)
2200{
2201 local_flush_icache_range((unsigned long)handle_tlbl,
2202 (unsigned long)handle_tlbl_end);
2203 local_flush_icache_range((unsigned long)handle_tlbs,
2204 (unsigned long)handle_tlbs_end);
2205 local_flush_icache_range((unsigned long)handle_tlbm,
2206 (unsigned long)handle_tlbm_end);
2207#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
2208 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd,
2209 (unsigned long)tlbmiss_handler_setup_pgd_end);
2210#endif
2211}
2212
2173void __cpuinit build_tlb_refill_handler(void) 2213void __cpuinit build_tlb_refill_handler(void)
2174{ 2214{
2175 /* 2215 /*
@@ -2202,6 +2242,7 @@ void __cpuinit build_tlb_refill_handler(void)
2202 build_r3000_tlb_load_handler(); 2242 build_r3000_tlb_load_handler();
2203 build_r3000_tlb_store_handler(); 2243 build_r3000_tlb_store_handler();
2204 build_r3000_tlb_modify_handler(); 2244 build_r3000_tlb_modify_handler();
2245 flush_tlb_handlers();
2205 run_once++; 2246 run_once++;
2206 } 2247 }
2207#else 2248#else
@@ -2229,23 +2270,10 @@ void __cpuinit build_tlb_refill_handler(void)
2229 build_r4000_tlb_modify_handler(); 2270 build_r4000_tlb_modify_handler();
2230 if (!cpu_has_local_ebase) 2271 if (!cpu_has_local_ebase)
2231 build_r4000_tlb_refill_handler(); 2272 build_r4000_tlb_refill_handler();
2273 flush_tlb_handlers();
2232 run_once++; 2274 run_once++;
2233 } 2275 }
2234 if (cpu_has_local_ebase) 2276 if (cpu_has_local_ebase)
2235 build_r4000_tlb_refill_handler(); 2277 build_r4000_tlb_refill_handler();
2236 } 2278 }
2237} 2279}
2238
2239void __cpuinit flush_tlb_handlers(void)
2240{
2241 local_flush_icache_range((unsigned long)handle_tlbl,
2242 (unsigned long)handle_tlbl_end);
2243 local_flush_icache_range((unsigned long)handle_tlbs,
2244 (unsigned long)handle_tlbs_end);
2245 local_flush_icache_range((unsigned long)handle_tlbm,
2246 (unsigned long)handle_tlbm_end);
2247#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
2248 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd,
2249 (unsigned long)tlbmiss_handler_setup_pgd_end);
2250#endif
2251}
diff --git a/arch/mips/mti-malta/malta-reset.c b/arch/mips/mti-malta/malta-reset.c
index 329420536241..d627d4b2b47f 100644
--- a/arch/mips/mti-malta/malta-reset.c
+++ b/arch/mips/mti-malta/malta-reset.c
@@ -1,33 +1,18 @@
1/* 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
2 * Carsten Langgaard, carstenl@mips.com 6 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. 7 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 * Reset the MIPS boards.
23 *
24 */ 8 */
25#include <linux/init.h> 9#include <linux/io.h>
26#include <linux/pm.h> 10#include <linux/pm.h>
27 11
28#include <asm/io.h>
29#include <asm/reboot.h> 12#include <asm/reboot.h>
30#include <asm/mips-boards/generic.h> 13
14#define SOFTRES_REG 0x1f000500
15#define GORESET 0x42
31 16
32static void mips_machine_restart(char *command) 17static void mips_machine_restart(char *command)
33{ 18{
@@ -45,7 +30,6 @@ static void mips_machine_halt(void)
45 __raw_writel(GORESET, softres_reg); 30 __raw_writel(GORESET, softres_reg);
46} 31}
47 32
48
49static int __init mips_reboot_setup(void) 33static int __init mips_reboot_setup(void)
50{ 34{
51 _machine_restart = mips_machine_restart; 35 _machine_restart = mips_machine_restart;
@@ -54,5 +38,4 @@ static int __init mips_reboot_setup(void)
54 38
55 return 0; 39 return 0;
56} 40}
57
58arch_initcall(mips_reboot_setup); 41arch_initcall(mips_reboot_setup);
diff --git a/arch/mips/mti-sead3/sead3-reset.c b/arch/mips/mti-sead3/sead3-reset.c
index 20475c5e7b9c..e6fb24414a70 100644
--- a/arch/mips/mti-sead3/sead3-reset.c
+++ b/arch/mips/mti-sead3/sead3-reset.c
@@ -9,7 +9,9 @@
9#include <linux/pm.h> 9#include <linux/pm.h>
10 10
11#include <asm/reboot.h> 11#include <asm/reboot.h>
12#include <asm/mips-boards/generic.h> 12
13#define SOFTRES_REG 0x1f000050
14#define GORESET 0x4d
13 15
14static void mips_machine_restart(char *command) 16static void mips_machine_restart(char *command)
15{ 17{
@@ -35,5 +37,4 @@ static int __init mips_reboot_setup(void)
35 37
36 return 0; 38 return 0;
37} 39}
38
39arch_initcall(mips_reboot_setup); 40arch_initcall(mips_reboot_setup);
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index 6eb65e44d9e4..7b2ac81e1f59 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -217,6 +217,7 @@ static void pci_fixup_ioc3(struct pci_dev *d)
217 pci_disable_swapping(d); 217 pci_disable_swapping(d);
218} 218}
219 219
220#ifdef CONFIG_NUMA
220int pcibus_to_node(struct pci_bus *bus) 221int pcibus_to_node(struct pci_bus *bus)
221{ 222{
222 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); 223 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
@@ -224,6 +225,7 @@ int pcibus_to_node(struct pci_bus *bus)
224 return bc->nasid; 225 return bc->nasid;
225} 226}
226EXPORT_SYMBOL(pcibus_to_node); 227EXPORT_SYMBOL(pcibus_to_node);
228#endif /* CONFIG_NUMA */
227 229
228DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 230DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
229 pci_fixup_ioc3); 231 pci_fixup_ioc3);
diff --git a/arch/mips/sgi-ip27/Makefile b/arch/mips/sgi-ip27/Makefile
index 1f29e761d691..da8f6816d346 100644
--- a/arch/mips/sgi-ip27/Makefile
+++ b/arch/mips/sgi-ip27/Makefile
@@ -7,4 +7,5 @@ obj-y := ip27-berr.o ip27-irq.o ip27-init.o ip27-klconfig.o ip27-klnuma.o \
7 ip27-xtalk.o 7 ip27-xtalk.o
8 8
9obj-$(CONFIG_EARLY_PRINTK) += ip27-console.o 9obj-$(CONFIG_EARLY_PRINTK) += ip27-console.o
10obj-$(CONFIG_PCI) += ip27-irq-pci.o
10obj-$(CONFIG_SMP) += ip27-smp.o 11obj-$(CONFIG_SMP) += ip27-smp.o
diff --git a/arch/mips/sgi-ip27/ip27-irq-pci.c b/arch/mips/sgi-ip27/ip27-irq-pci.c
new file mode 100644
index 000000000000..ec22ec5600f3
--- /dev/null
+++ b/arch/mips/sgi-ip27/ip27-irq-pci.c
@@ -0,0 +1,266 @@
1/*
2 * ip27-irq.c: Highlevel interrupt handling for IP27 architecture.
3 *
4 * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org)
5 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
6 * Copyright (C) 1999 - 2001 Kanoj Sarcar
7 */
8
9#undef DEBUG
10
11#include <linux/init.h>
12#include <linux/irq.h>
13#include <linux/errno.h>
14#include <linux/signal.h>
15#include <linux/sched.h>
16#include <linux/types.h>
17#include <linux/interrupt.h>
18#include <linux/ioport.h>
19#include <linux/timex.h>
20#include <linux/smp.h>
21#include <linux/random.h>
22#include <linux/kernel.h>
23#include <linux/kernel_stat.h>
24#include <linux/delay.h>
25#include <linux/bitops.h>
26
27#include <asm/bootinfo.h>
28#include <asm/io.h>
29#include <asm/mipsregs.h>
30
31#include <asm/processor.h>
32#include <asm/pci/bridge.h>
33#include <asm/sn/addrs.h>
34#include <asm/sn/agent.h>
35#include <asm/sn/arch.h>
36#include <asm/sn/hub.h>
37#include <asm/sn/intr.h>
38
39/*
40 * Linux has a controller-independent x86 interrupt architecture.
41 * every controller has a 'controller-template', that is used
42 * by the main code to do the right thing. Each driver-visible
43 * interrupt source is transparently wired to the appropriate
44 * controller. Thus drivers need not be aware of the
45 * interrupt-controller.
46 *
47 * Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC,
48 * PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC.
49 * (IO-APICs assumed to be messaging to Pentium local-APICs)
50 *
51 * the code is designed to be easily extended with new/different
52 * interrupt controllers, without having to do assembly magic.
53 */
54
55extern struct bridge_controller *irq_to_bridge[];
56extern int irq_to_slot[];
57
58/*
59 * use these macros to get the encoded nasid and widget id
60 * from the irq value
61 */
62#define IRQ_TO_BRIDGE(i) irq_to_bridge[(i)]
63#define SLOT_FROM_PCI_IRQ(i) irq_to_slot[i]
64
65static inline int alloc_level(int cpu, int irq)
66{
67 struct hub_data *hub = hub_data(cpu_to_node(cpu));
68 struct slice_data *si = cpu_data[cpu].data;
69 int level;
70
71 level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE);
72 if (level >= LEVELS_PER_SLICE)
73 panic("Cpu %d flooded with devices", cpu);
74
75 __set_bit(level, hub->irq_alloc_mask);
76 si->level_to_irq[level] = irq;
77
78 return level;
79}
80
81static inline int find_level(cpuid_t *cpunum, int irq)
82{
83 int cpu, i;
84
85 for_each_online_cpu(cpu) {
86 struct slice_data *si = cpu_data[cpu].data;
87
88 for (i = BASE_PCI_IRQ; i < LEVELS_PER_SLICE; i++)
89 if (si->level_to_irq[i] == irq) {
90 *cpunum = cpu;
91
92 return i;
93 }
94 }
95
96 panic("Could not identify cpu/level for irq %d", irq);
97}
98
99static int intr_connect_level(int cpu, int bit)
100{
101 nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
102 struct slice_data *si = cpu_data[cpu].data;
103
104 set_bit(bit, si->irq_enable_mask);
105
106 if (!cputoslice(cpu)) {
107 REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
108 REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
109 } else {
110 REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
111 REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
112 }
113
114 return 0;
115}
116
117static int intr_disconnect_level(int cpu, int bit)
118{
119 nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
120 struct slice_data *si = cpu_data[cpu].data;
121
122 clear_bit(bit, si->irq_enable_mask);
123
124 if (!cputoslice(cpu)) {
125 REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
126 REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
127 } else {
128 REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
129 REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
130 }
131
132 return 0;
133}
134
135/* Startup one of the (PCI ...) IRQs routes over a bridge. */
136static unsigned int startup_bridge_irq(struct irq_data *d)
137{
138 struct bridge_controller *bc;
139 bridgereg_t device;
140 bridge_t *bridge;
141 int pin, swlevel;
142 cpuid_t cpu;
143
144 pin = SLOT_FROM_PCI_IRQ(d->irq);
145 bc = IRQ_TO_BRIDGE(d->irq);
146 bridge = bc->base;
147
148 pr_debug("bridge_startup(): irq= 0x%x pin=%d\n", d->irq, pin);
149 /*
150 * "map" irq to a swlevel greater than 6 since the first 6 bits
151 * of INT_PEND0 are taken
152 */
153 swlevel = find_level(&cpu, d->irq);
154 bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (bc->nasid << 8));
155 bridge->b_int_enable |= (1 << pin);
156 bridge->b_int_enable |= 0x7ffffe00; /* more stuff in int_enable */
157
158 /*
159 * Enable sending of an interrupt clear packt to the hub on a high to
160 * low transition of the interrupt pin.
161 *
162 * IRIX sets additional bits in the address which are documented as
163 * reserved in the bridge docs.
164 */
165 bridge->b_int_mode |= (1UL << pin);
166
167 /*
168 * We assume the bridge to have a 1:1 mapping between devices
169 * (slots) and intr pins.
170 */
171 device = bridge->b_int_device;
172 device &= ~(7 << (pin*3));
173 device |= (pin << (pin*3));
174 bridge->b_int_device = device;
175
176 bridge->b_wid_tflush;
177
178 intr_connect_level(cpu, swlevel);
179
180 return 0; /* Never anything pending. */
181}
182
183/* Shutdown one of the (PCI ...) IRQs routes over a bridge. */
184static void shutdown_bridge_irq(struct irq_data *d)
185{
186 struct bridge_controller *bc = IRQ_TO_BRIDGE(d->irq);
187 bridge_t *bridge = bc->base;
188 int pin, swlevel;
189 cpuid_t cpu;
190
191 pr_debug("bridge_shutdown: irq 0x%x\n", d->irq);
192 pin = SLOT_FROM_PCI_IRQ(d->irq);
193
194 /*
195 * map irq to a swlevel greater than 6 since the first 6 bits
196 * of INT_PEND0 are taken
197 */
198 swlevel = find_level(&cpu, d->irq);
199 intr_disconnect_level(cpu, swlevel);
200
201 bridge->b_int_enable &= ~(1 << pin);
202 bridge->b_wid_tflush;
203}
204
205static inline void enable_bridge_irq(struct irq_data *d)
206{
207 cpuid_t cpu;
208 int swlevel;
209
210 swlevel = find_level(&cpu, d->irq); /* Criminal offence */
211 intr_connect_level(cpu, swlevel);
212}
213
214static inline void disable_bridge_irq(struct irq_data *d)
215{
216 cpuid_t cpu;
217 int swlevel;
218
219 swlevel = find_level(&cpu, d->irq); /* Criminal offence */
220 intr_disconnect_level(cpu, swlevel);
221}
222
223static struct irq_chip bridge_irq_type = {
224 .name = "bridge",
225 .irq_startup = startup_bridge_irq,
226 .irq_shutdown = shutdown_bridge_irq,
227 .irq_mask = disable_bridge_irq,
228 .irq_unmask = enable_bridge_irq,
229};
230
231void register_bridge_irq(unsigned int irq)
232{
233 irq_set_chip_and_handler(irq, &bridge_irq_type, handle_level_irq);
234}
235
236int request_bridge_irq(struct bridge_controller *bc)
237{
238 int irq = allocate_irqno();
239 int swlevel, cpu;
240 nasid_t nasid;
241
242 if (irq < 0)
243 return irq;
244
245 /*
246 * "map" irq to a swlevel greater than 6 since the first 6 bits
247 * of INT_PEND0 are taken
248 */
249 cpu = bc->irq_cpu;
250 swlevel = alloc_level(cpu, irq);
251 if (unlikely(swlevel < 0)) {
252 free_irqno(irq);
253
254 return -EAGAIN;
255 }
256
257 /* Make sure it's not already pending when we connect it. */
258 nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
259 REMOTE_HUB_CLR_INTR(nasid, swlevel);
260
261 intr_connect_level(cpu, swlevel);
262
263 register_bridge_irq(irq);
264
265 return irq;
266}
diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c
index 2315cfeb2687..3fbaef97a1b8 100644
--- a/arch/mips/sgi-ip27/ip27-irq.c
+++ b/arch/mips/sgi-ip27/ip27-irq.c
@@ -29,7 +29,6 @@
29#include <asm/mipsregs.h> 29#include <asm/mipsregs.h>
30 30
31#include <asm/processor.h> 31#include <asm/processor.h>
32#include <asm/pci/bridge.h>
33#include <asm/sn/addrs.h> 32#include <asm/sn/addrs.h>
34#include <asm/sn/agent.h> 33#include <asm/sn/agent.h>
35#include <asm/sn/arch.h> 34#include <asm/sn/arch.h>
@@ -54,50 +53,6 @@
54 53
55extern asmlinkage void ip27_irq(void); 54extern asmlinkage void ip27_irq(void);
56 55
57extern struct bridge_controller *irq_to_bridge[];
58extern int irq_to_slot[];
59
60/*
61 * use these macros to get the encoded nasid and widget id
62 * from the irq value
63 */
64#define IRQ_TO_BRIDGE(i) irq_to_bridge[(i)]
65#define SLOT_FROM_PCI_IRQ(i) irq_to_slot[i]
66
67static inline int alloc_level(int cpu, int irq)
68{
69 struct hub_data *hub = hub_data(cpu_to_node(cpu));
70 struct slice_data *si = cpu_data[cpu].data;
71 int level;
72
73 level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE);
74 if (level >= LEVELS_PER_SLICE)
75 panic("Cpu %d flooded with devices", cpu);
76
77 __set_bit(level, hub->irq_alloc_mask);
78 si->level_to_irq[level] = irq;
79
80 return level;
81}
82
83static inline int find_level(cpuid_t *cpunum, int irq)
84{
85 int cpu, i;
86
87 for_each_online_cpu(cpu) {
88 struct slice_data *si = cpu_data[cpu].data;
89
90 for (i = BASE_PCI_IRQ; i < LEVELS_PER_SLICE; i++)
91 if (si->level_to_irq[i] == irq) {
92 *cpunum = cpu;
93
94 return i;
95 }
96 }
97
98 panic("Could not identify cpu/level for irq %d", irq);
99}
100
101/* 56/*
102 * Find first bit set 57 * Find first bit set
103 */ 58 */
@@ -204,175 +159,6 @@ static void ip27_hub_error(void)
204 panic("CPU %d got a hub error interrupt", smp_processor_id()); 159 panic("CPU %d got a hub error interrupt", smp_processor_id());
205} 160}
206 161
207static int intr_connect_level(int cpu, int bit)
208{
209 nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
210 struct slice_data *si = cpu_data[cpu].data;
211
212 set_bit(bit, si->irq_enable_mask);
213
214 if (!cputoslice(cpu)) {
215 REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
216 REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
217 } else {
218 REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
219 REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
220 }
221
222 return 0;
223}
224
225static int intr_disconnect_level(int cpu, int bit)
226{
227 nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
228 struct slice_data *si = cpu_data[cpu].data;
229
230 clear_bit(bit, si->irq_enable_mask);
231
232 if (!cputoslice(cpu)) {
233 REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
234 REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
235 } else {
236 REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
237 REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
238 }
239
240 return 0;
241}
242
243/* Startup one of the (PCI ...) IRQs routes over a bridge. */
244static unsigned int startup_bridge_irq(struct irq_data *d)
245{
246 struct bridge_controller *bc;
247 bridgereg_t device;
248 bridge_t *bridge;
249 int pin, swlevel;
250 cpuid_t cpu;
251
252 pin = SLOT_FROM_PCI_IRQ(d->irq);
253 bc = IRQ_TO_BRIDGE(d->irq);
254 bridge = bc->base;
255
256 pr_debug("bridge_startup(): irq= 0x%x pin=%d\n", d->irq, pin);
257 /*
258 * "map" irq to a swlevel greater than 6 since the first 6 bits
259 * of INT_PEND0 are taken
260 */
261 swlevel = find_level(&cpu, d->irq);
262 bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (bc->nasid << 8));
263 bridge->b_int_enable |= (1 << pin);
264 bridge->b_int_enable |= 0x7ffffe00; /* more stuff in int_enable */
265
266 /*
267 * Enable sending of an interrupt clear packt to the hub on a high to
268 * low transition of the interrupt pin.
269 *
270 * IRIX sets additional bits in the address which are documented as
271 * reserved in the bridge docs.
272 */
273 bridge->b_int_mode |= (1UL << pin);
274
275 /*
276 * We assume the bridge to have a 1:1 mapping between devices
277 * (slots) and intr pins.
278 */
279 device = bridge->b_int_device;
280 device &= ~(7 << (pin*3));
281 device |= (pin << (pin*3));
282 bridge->b_int_device = device;
283
284 bridge->b_wid_tflush;
285
286 intr_connect_level(cpu, swlevel);
287
288 return 0; /* Never anything pending. */
289}
290
291/* Shutdown one of the (PCI ...) IRQs routes over a bridge. */
292static void shutdown_bridge_irq(struct irq_data *d)
293{
294 struct bridge_controller *bc = IRQ_TO_BRIDGE(d->irq);
295 bridge_t *bridge = bc->base;
296 int pin, swlevel;
297 cpuid_t cpu;
298
299 pr_debug("bridge_shutdown: irq 0x%x\n", d->irq);
300 pin = SLOT_FROM_PCI_IRQ(d->irq);
301
302 /*
303 * map irq to a swlevel greater than 6 since the first 6 bits
304 * of INT_PEND0 are taken
305 */
306 swlevel = find_level(&cpu, d->irq);
307 intr_disconnect_level(cpu, swlevel);
308
309 bridge->b_int_enable &= ~(1 << pin);
310 bridge->b_wid_tflush;
311}
312
313static inline void enable_bridge_irq(struct irq_data *d)
314{
315 cpuid_t cpu;
316 int swlevel;
317
318 swlevel = find_level(&cpu, d->irq); /* Criminal offence */
319 intr_connect_level(cpu, swlevel);
320}
321
322static inline void disable_bridge_irq(struct irq_data *d)
323{
324 cpuid_t cpu;
325 int swlevel;
326
327 swlevel = find_level(&cpu, d->irq); /* Criminal offence */
328 intr_disconnect_level(cpu, swlevel);
329}
330
331static struct irq_chip bridge_irq_type = {
332 .name = "bridge",
333 .irq_startup = startup_bridge_irq,
334 .irq_shutdown = shutdown_bridge_irq,
335 .irq_mask = disable_bridge_irq,
336 .irq_unmask = enable_bridge_irq,
337};
338
339void register_bridge_irq(unsigned int irq)
340{
341 irq_set_chip_and_handler(irq, &bridge_irq_type, handle_level_irq);
342}
343
344int request_bridge_irq(struct bridge_controller *bc)
345{
346 int irq = allocate_irqno();
347 int swlevel, cpu;
348 nasid_t nasid;
349
350 if (irq < 0)
351 return irq;
352
353 /*
354 * "map" irq to a swlevel greater than 6 since the first 6 bits
355 * of INT_PEND0 are taken
356 */
357 cpu = bc->irq_cpu;
358 swlevel = alloc_level(cpu, irq);
359 if (unlikely(swlevel < 0)) {
360 free_irqno(irq);
361
362 return -EAGAIN;
363 }
364
365 /* Make sure it's not already pending when we connect it. */
366 nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
367 REMOTE_HUB_CLR_INTR(nasid, swlevel);
368
369 intr_connect_level(cpu, swlevel);
370
371 register_bridge_irq(irq);
372
373 return irq;
374}
375
376asmlinkage void plat_irq_dispatch(void) 162asmlinkage void plat_irq_dispatch(void)
377{ 163{
378 unsigned long pending = read_c0_cause() & read_c0_status(); 164 unsigned long pending = read_c0_cause() & read_c0_status();
diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig
index 01cc1a749c73..5fbd3605d24f 100644
--- a/arch/mips/sibyte/Kconfig
+++ b/arch/mips/sibyte/Kconfig
@@ -147,7 +147,8 @@ config SIBYTE_CFE_CONSOLE
147 147
148config SIBYTE_BUS_WATCHER 148config SIBYTE_BUS_WATCHER
149 bool "Support for Bus Watcher statistics" 149 bool "Support for Bus Watcher statistics"
150 depends on SIBYTE_SB1xxx_SOC 150 depends on SIBYTE_SB1xxx_SOC && \
151 (SIBYTE_BCM112X || SIBYTE_SB1250)
151 help 152 help
152 Handle and keep statistics on the bus error interrupts (COR_ECC, 153 Handle and keep statistics on the bus error interrupts (COR_ECC,
153 BAD_ECC, IO_BUS). 154 BAD_ECC, IO_BUS).
diff --git a/arch/mips/sibyte/Platform b/arch/mips/sibyte/Platform
index 6cb6dcf241f2..af117330ce14 100644
--- a/arch/mips/sibyte/Platform
+++ b/arch/mips/sibyte/Platform
@@ -41,3 +41,4 @@ load-$(CONFIG_SIBYTE_RHONE) := 0xffffffff80100000
41load-$(CONFIG_SIBYTE_SENTOSA) := 0xffffffff80100000 41load-$(CONFIG_SIBYTE_SENTOSA) := 0xffffffff80100000
42load-$(CONFIG_SIBYTE_SWARM) := 0xffffffff80100000 42load-$(CONFIG_SIBYTE_SWARM) := 0xffffffff80100000
43load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000 43load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000
44load-$(CONFIG_SIBYTE_LITTLESUR) := 0xffffffff80100000
diff --git a/arch/mips/sibyte/common/Makefile b/arch/mips/sibyte/common/Makefile
index 36aa700cc40c..b3d6bf23a662 100644
--- a/arch/mips/sibyte/common/Makefile
+++ b/arch/mips/sibyte/common/Makefile
@@ -1,3 +1,4 @@
1obj-y := cfe.o 1obj-y := cfe.o
2obj-$(CONFIG_SIBYTE_BUS_WATCHER) += bus_watcher.o
2obj-$(CONFIG_SIBYTE_CFE_CONSOLE) += cfe_console.o 3obj-$(CONFIG_SIBYTE_CFE_CONSOLE) += cfe_console.o
3obj-$(CONFIG_SIBYTE_TBPROF) += sb_tbprof.o 4obj-$(CONFIG_SIBYTE_TBPROF) += sb_tbprof.o
diff --git a/arch/mips/sibyte/sb1250/bus_watcher.c b/arch/mips/sibyte/common/bus_watcher.c
index 8871e3345bff..5581844c9194 100644
--- a/arch/mips/sibyte/sb1250/bus_watcher.c
+++ b/arch/mips/sibyte/common/bus_watcher.c
@@ -37,6 +37,9 @@
37#include <asm/sibyte/sb1250_regs.h> 37#include <asm/sibyte/sb1250_regs.h>
38#include <asm/sibyte/sb1250_int.h> 38#include <asm/sibyte/sb1250_int.h>
39#include <asm/sibyte/sb1250_scd.h> 39#include <asm/sibyte/sb1250_scd.h>
40#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
41#include <asm/sibyte/bcm1480_regs.h>
42#endif
40 43
41 44
42struct bw_stats_struct { 45struct bw_stats_struct {
@@ -81,9 +84,15 @@ void check_bus_watcher(void)
81#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS 84#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
82 /* Destructive read, clears register and interrupt */ 85 /* Destructive read, clears register and interrupt */
83 status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS)); 86 status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS));
84#else 87#elif defined(CONFIG_SIBYTE_BCM112X) || defined(CONFIG_SIBYTE_SB1250)
85 /* Use non-destructive register */ 88 /* Use non-destructive register */
86 status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS_DEBUG)); 89 status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS_DEBUG));
90#elif defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
91 /* Use non-destructive register */
92 /* Same as 1250 except BUS_ERR_STATUS_DEBUG is in a different place. */
93 status = csr_in32(IOADDR(A_BCM1480_BUS_ERR_STATUS_DEBUG));
94#else
95#error bus watcher being built for unknown Sibyte SOC!
87#endif 96#endif
88 if (!(status & 0x7fffffff)) { 97 if (!(status & 0x7fffffff)) {
89 printk("Using last values reaped by bus watcher driver\n"); 98 printk("Using last values reaped by bus watcher driver\n");
@@ -175,9 +184,6 @@ static irqreturn_t sibyte_bw_int(int irq, void *data)
175#ifdef CONFIG_SIBYTE_BW_TRACE 184#ifdef CONFIG_SIBYTE_BW_TRACE
176 int i; 185 int i;
177#endif 186#endif
178#ifndef CONFIG_PROC_FS
179 char bw_buf[1024];
180#endif
181 187
182#ifdef CONFIG_SIBYTE_BW_TRACE 188#ifdef CONFIG_SIBYTE_BW_TRACE
183 csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG)); 189 csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG));
diff --git a/arch/mips/sibyte/common/sb_tbprof.c b/arch/mips/sibyte/common/sb_tbprof.c
index 2188b39a1251..059e28c8fd97 100644
--- a/arch/mips/sibyte/common/sb_tbprof.c
+++ b/arch/mips/sibyte/common/sb_tbprof.c
@@ -27,6 +27,7 @@
27#include <linux/types.h> 27#include <linux/types.h>
28#include <linux/init.h> 28#include <linux/init.h>
29#include <linux/interrupt.h> 29#include <linux/interrupt.h>
30#include <linux/sched.h>
30#include <linux/vmalloc.h> 31#include <linux/vmalloc.h>
31#include <linux/fs.h> 32#include <linux/fs.h>
32#include <linux/errno.h> 33#include <linux/errno.h>
diff --git a/arch/mips/sibyte/sb1250/Makefile b/arch/mips/sibyte/sb1250/Makefile
index d3d969de407b..cdc4c56c3e29 100644
--- a/arch/mips/sibyte/sb1250/Makefile
+++ b/arch/mips/sibyte/sb1250/Makefile
@@ -1,4 +1,3 @@
1obj-y := setup.o irq.o time.o 1obj-y := setup.o irq.o time.o
2 2
3obj-$(CONFIG_SMP) += smp.o 3obj-$(CONFIG_SMP) += smp.o
4obj-$(CONFIG_SIBYTE_BUS_WATCHER) += bus_watcher.o
diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c
index cec4b8ca1438..12336c2a649c 100644
--- a/arch/mips/sni/pcimt.c
+++ b/arch/mips/sni/pcimt.c
@@ -185,6 +185,7 @@ static void __init sni_pcimt_resource_init(void)
185 185
186extern struct pci_ops sni_pcimt_ops; 186extern struct pci_ops sni_pcimt_ops;
187 187
188#ifdef CONFIG_PCI
188static struct pci_controller sni_controller = { 189static struct pci_controller sni_controller = {
189 .pci_ops = &sni_pcimt_ops, 190 .pci_ops = &sni_pcimt_ops,
190 .mem_resource = &sni_mem_resource, 191 .mem_resource = &sni_mem_resource,
@@ -193,6 +194,7 @@ static struct pci_controller sni_controller = {
193 .io_offset = 0x00000000UL, 194 .io_offset = 0x00000000UL,
194 .io_map_base = SNI_PORT_BASE 195 .io_map_base = SNI_PORT_BASE
195}; 196};
197#endif
196 198
197static void enable_pcimt_irq(struct irq_data *d) 199static void enable_pcimt_irq(struct irq_data *d)
198{ 200{
diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c
index 7cddd03d1fea..05bb51676e82 100644
--- a/arch/mips/sni/pcit.c
+++ b/arch/mips/sni/pcit.c
@@ -128,13 +128,6 @@ static struct resource pcit_io_resources[] = {
128 } 128 }
129}; 129};
130 130
131static struct resource sni_mem_resource = {
132 .start = 0x18000000UL,
133 .end = 0x1fbfffffUL,
134 .name = "PCIT PCI MEM",
135 .flags = IORESOURCE_MEM
136};
137
138static void __init sni_pcit_resource_init(void) 131static void __init sni_pcit_resource_init(void)
139{ 132{
140 int i; 133 int i;
@@ -147,6 +140,14 @@ static void __init sni_pcit_resource_init(void)
147 140
148extern struct pci_ops sni_pcit_ops; 141extern struct pci_ops sni_pcit_ops;
149 142
143#ifdef CONFIG_PCI
144static struct resource sni_mem_resource = {
145 .start = 0x18000000UL,
146 .end = 0x1fbfffffUL,
147 .name = "PCIT PCI MEM",
148 .flags = IORESOURCE_MEM
149};
150
150static struct pci_controller sni_pcit_controller = { 151static struct pci_controller sni_pcit_controller = {
151 .pci_ops = &sni_pcit_ops, 152 .pci_ops = &sni_pcit_ops,
152 .mem_resource = &sni_mem_resource, 153 .mem_resource = &sni_mem_resource,
@@ -155,6 +156,7 @@ static struct pci_controller sni_pcit_controller = {
155 .io_offset = 0x00000000UL, 156 .io_offset = 0x00000000UL,
156 .io_map_base = SNI_PORT_BASE 157 .io_map_base = SNI_PORT_BASE
157}; 158};
159#endif /* CONFIG_PCI */
158 160
159static void enable_pcit_irq(struct irq_data *d) 161static void enable_pcit_irq(struct irq_data *d)
160{ 162{
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 11:04:20 -0500