1 files changed, 48 insertions, 1 deletions

diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
index fd698087fbfd..8ac4e095e68e 100644
--- a/arch/mips/bcm63xx/prom.c
+++ b/arch/mips/bcm63xx/prom.c
@@ -8,7 +8,11 @@
 
 #include <linux/init.h>
 #include <linux/bootmem.h>
+#include <linux/smp.h>
 #include <asm/bootinfo.h>
+#include <asm/bmips.h>
+#include <asm/smp-ops.h>
+#include <asm/mipsregs.h>
 #include <bcm63xx_board.h>
 #include <bcm63xx_cpu.h>
 #include <bcm63xx_io.h>
@@ -26,7 +30,9 @@ void __init prom_init(void)
         bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG);
 
         /* disable all hardware blocks clock for now */
-        if (BCMCPU_IS_6328())
+        if (BCMCPU_IS_3368())
+                mask = CKCTL_3368_ALL_SAFE_EN;
+        else if (BCMCPU_IS_6328())
                 mask = CKCTL_6328_ALL_SAFE_EN;
         else if (BCMCPU_IS_6338())
                 mask = CKCTL_6338_ALL_SAFE_EN;
@@ -52,6 +58,47 @@ void __init prom_init(void)
 
         /* do low level board init */
         board_prom_init();
+
+        if (IS_ENABLED(CONFIG_CPU_BMIPS4350) && IS_ENABLED(CONFIG_SMP)) {
+                /* set up SMP */
+                register_smp_ops(&bmips_smp_ops);
+
+                /*
+                 * BCM6328 might not have its second CPU enabled, while BCM6358
+                 * needs special handling for its shared TLB, so disable SMP
+                 * for now.
+                 */
+                if (BCMCPU_IS_6328()) {
+                        reg = bcm_readl(BCM_6328_OTP_BASE +
+                                        OTP_USER_BITS_6328_REG(3));
+
+                        if (reg & OTP_6328_REG3_TP1_DISABLED)
+                                bmips_smp_enabled = 0;
+                } else if (BCMCPU_IS_6358()) {
+                        bmips_smp_enabled = 0;
+                }
+
+                if (!bmips_smp_enabled)
+                        return;
+
+                /*
+                 * The bootloader has set up the CPU1 reset vector at
+                 * 0xa000_0200.
+                 * This conflicts with the special interrupt vector (IV).
+                 * The bootloader has also set up CPU1 to respond to the wrong
+                 * IPI interrupt.
+                 * Here we will start up CPU1 in the background and ask it to
+                 * reconfigure itself then go back to sleep.
+                 */
+                memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20);
+                __sync();
+                set_c0_cause(C_SW0);
+                cpumask_set_cpu(1, &bmips_booted_mask);
+
+                /*
+                 * FIXME: we really should have some sort of hazard barrier here
+                 */
+        }
 }
 
 void __init prom_free_prom_memory(void)