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* ARM: tegra: decouple uncompress.h and debug-macro.SStephen Warren2012-11-16
| | | | | | | | | | | | | | | | | | Prior to this change, Tegra's debug-macro.S relied on uncompress.h having determined which UART to use, and whether it was safe to use the UART (i.e. is it not in reset, and is clocked). This determination was communicated from uncompress.h to debug-macro.S using a few bytes of Tegra's IRAM (an on-SoC RAM). This had the disadvantage that uncompress.h was a required part of the kernel boot process; booting a non-compressed kernel would not allow earlyprintk to operate. This change duplicates the UART selection and validation logic into debug-macro.S so that the reliance on uncompress.h is removed. This also helps out with single-zImage work, since there is currently no support for using any uncompress.h with single-zImage. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: simplify DEBUG_LL UART selection optionsStephen Warren2012-11-16
| | | | | | | | | | | | | | | | | Delete CONFIG_TEGRA_DEBUG_UART_AUTO_SCRATCH; it's not useful any more: * No upstream bootloader currently or will ever support this option. * CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA is a much more direct alternative. Merge the fixed and automatic UART selection menus into a single choice for simplicity; now you either pick AUTO_ODMDATA or a single fixed UART, rather than potentially having an AUTO option override whatever fixed option was chosen. Remove TEGRA_DEBUG_UART_NONE; if you don't want a Tegra DEBUG_LL UART, simply don't turn on DEBUG_LL. NONE used to be the default option, so pick AUTO_ODMDATA as the new default. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: select SPARSE_IRQStephen Warren2012-11-16
| | | | | | | | | | | SPARSE_IRQ is required for single zImage support. With this enabled, we can delete <mach/irqs.h>. This requires removing one unnecessary include of that file, and hard-coding the PCIe IRQ into the PCIe driver. This is a hack that will be dealt with as part of converting the PCIe driver into a true DT-supporting driver. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: enhance timer.c to get IO address from device treeStephen Warren2012-11-16
| | | | | | | | Modify Tegra's timer code to parse the IO address from device tree, hence removing the dependency on <mach/iomap.h>. This will allow the driver to be moved to drivers/clocksource/. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: enhance timer.c to get IRQ info from device treeStephen Warren2012-11-16
| | | | | | | | Modify Tegra's timer code to parse the Tegra timer IRQ from device tree, and to instantiate the TWD from device tree, rather than relying on hard- coded values from <mach/irqs.h>. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: timer: fix checkpatch warningsStephen Warren2012-11-16
| | | | | | | This prevents checkpatch complaining when this file is moved in a later patch. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add TWD to device treeStephen Warren2012-11-16
| | | | | | | This will allow timer.c to use twd_local_timer_of_register(), and hence not need to hard-code the TWD address or IRQ. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: define DT bindings for and instantiate RTCStephen Warren2012-11-16
| | | | | | | | | | | The Tegra RTC maintains seconds and milliseconds counters, and five alarm registers. The alarms and other interrupts may wake the system from low-power state. Define a DT binding for this HW module, and add the module into the Tegra device tree files. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: define DT bindings for and instantiate timerStephen Warren2012-11-16
| | | | | | | | | | | The Tegra timer provides a number of 29-bit timer channels, a single 32-bit free running counter, and in the Tegra30 variant, 5 watchdog modules. The first two channels may also trigger a legacy watchdog reset. Define a DT binding for this HW module, and add the module into the Tegra device tree files. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Merge remote-tracking branch 'korg_arm-soc/devel/debug_ll_init' into ↵Stephen Warren2012-11-16
|\ | | | | | | for-3.8/single-zimage
| * ARM: implement debug_ll_io_init()Rob Herring2012-11-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using DEBUG_LL, the UART's (or other HW's) registers are mapped into early page tables based on the results of assembly macro addruart. Later, when the page tables are replaced, the same virtual address must remain valid. Historically, this has been ensured by using defines from <mach/iomap.h> in both the implementation of addruart, and the machine's .map_io() function. However, with the move to single zImage, we wish to remove <mach/iomap.h>. To enable this, the macro addruart may be used when constructing the late page tables too; addruart is exposed as a C function debug_ll_addr(), and used to set up the required mapping in debug_ll_io_init(), which may called on an opt-in basis from a machine's .map_io() function. Signed-off-by: Rob Herring <rob.herring@calxeda.com> [swarren: Mask map.virtual with PAGE_MASK. Checked for NULL results from debug_ll_addr (e.g. when selected UART isn't valid). Fixed compile when either !CONFIG_DEBUG_LL or CONFIG_DEBUG_SEMIHOSTING.] Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* | ARM: tegra: whistler: enable HDMI portStephen Warren2012-11-16
| | | | | | | | | | | | | | | | | | | | Enable host1x, and the HDMI output. Whistler also has a DSI-based LCD, and a VGA output. tegradrm doesn't support either of those output types yet. Based on work by Thierry Reding for TrimSlice. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: tec: Enable HDMI outputThierry Reding2012-11-16
| | | | | | | | | | | | | | Enable the HDMI output found on Tamonten Evaluation Carrier boards. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: plutux: Enable HDMI outputThierry Reding2012-11-16
| | | | | | | | | | | | | | Enable the HDMI output found on Plutux boards. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: tamonten: Add host1x supportThierry Reding2012-11-16
| | | | | | | | | | | | | | | | | | Hook up the required regulators, I2C DDC adapter and hotplug detect GPIO to the Tamonten HDMI output. Carrier boards still need to explicitly enable the output to use it. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: trimslice: enable HDMI portThierry Reding2012-11-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable host1x, and the HDMI output. Harmony also has a DVI port with an HDMI form-factor connector, driven by Tegra's LVDS output. This isn't enabled yet, due to potential issues with having multiple outputs enabled. Correct DDC I2C frequency to 100KHz. Add dummy/fixed regulators to satisfy the HDMI driver. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> [swarren: add commit description, remove enable of DVI port] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: harmony: enable HDMI portStephen Warren2012-11-16
| | | | | | | | | | | | | | | | | | | | | | | | | | Enable host1x, and the HDMI output. Harmony also has an optional LCD, and a VGA output. The former isn't enabled due to potential issues with having multiple outputs enabled. The latter isn't enabled since the driver doesn't support VGA yet anyway. Correct DDC I2C frequency to 100KHz. Based on work by Thierry Reding for TrimSlice. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: Add Tegra30 host1x supportThierry Reding2012-11-15
| | | | | | | | | | | | | | | | | | Add the host1x node along with its children to the Tegra30 DTSI. Board- specific DTS files are expected to enable the available outputs and complement the device tree with data specific to the hardware. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: Add Tegra20 host1x supportThierry Reding2012-11-15
| | | | | | | | | | | | | | | | | | Add the host1x node along with its children to the Tegra20 DTSI. Board- specific DTS files are expected to enable the available outputs and complement the device tree with data specific to the hardware. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: trimslice: enable SPI flashStephen Warren2012-11-15
| | | | | | | | | | | | TrimSlice contains a 1MiB SPI flash. Represent this in the device tree. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: dts: add sflash controller dt entryLaxman Dewangan2012-11-15
| | | | | | | | | | | | | | | | | | | | Nvidia's Tegra20 have the SPI (SFLASH) controller to interface with spi flash device which is used for system boot. Add DT entry for this controller. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: move sflash node to keep file sorted] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: ventana: Add NCT1008 temperature sensorThierry Reding2012-11-15
| | | | | | | | | | | | | | | | | | | | The Harmony board has an ON Semiconductors NCT1008 temperature sensor connected to the DVC bus. It can be used to monitor the ambient (local) and on-die (remote) temperatures. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: tamonten: Add NCT1008 temperature sensorThierry Reding2012-11-15
| | | | | | | | | | | | | | | | | | The Tamonten SOM has an ON Semiconductor NCT1008 connected to the DVC bus which is used to measure the ambient (local) temperature as well as the on-die (remote) temperature. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: harmony: Add ADT7641 temperature sensorThierry Reding2012-11-15
| | | | | | | | | | | | | | | | | | | | The Harmony board has an Analog Devices ADT7461 temperature sensor connected to the DVC bus. It can be used to monitor the ambient (local) and on-die (remote) temperatures. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: tec: Remove redundant DT propertiesThierry Reding2012-11-15
| | | | | | | | | | | | | | | | These properties are already set by the tegra20-tamonten.dtsi, so they don't need to be repeated. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: tamonten: Add DDC/PTA pinmuxThierry Reding2012-11-15
| | | | | | | | | | | | | | | | | | | | This commit allows the I2C2 controller on Tegra20 to be routed either to the DDC or the PTA pin group at runtime. On Tamonten this allows the I2C bus to be used for the DDC of the HDMI connector or to access I2C chips on the carrier board. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: dts: cardhu: enable SLINK4Laxman Dewangan2012-11-15
| | | | | | | | | | | | | | | | | | | | | | | | | | Enable SLINK4 and connected device in Tegra30 based platform Cardhu. Setting maximum spi frequency to 25MHz. SPI serial flash is connected on CS1 of SLINK4 on cardhu platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: swapped reg/compatible order to be consistent] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: dts: add slink controller dt entryLaxman Dewangan2012-11-15
| | | | | | | | | | | | | | | | Add slink controller details in the dts file of Tegra20 and Tegra30. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: dt: tegra: ventana: define pinmux for ddcMark Zhang2012-11-15
| | | | | | | | | | | | | | | | | | | | Tegra 2's I2C2 controller can be routed to either the PTA or DDC pin group on Ventana. So: - Remove the HDMI function definition of pta pingroup - Define child i2c adapters(ddc & pta) for I2C2 controller Signed-off-by: Mark Zhang <markz@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: dt: t30 cardhu: set pinmux and power for wlanWei Ni2012-11-15
| | | | | | | | | | | | | | | | | | | | Configure pinmux as required for WiFi. Enable the SDHCI1 controller for a02 and a04 board, which is connected to the WiFi module. For now, always enable the regulator that provides power to the Wifi module. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: dt: t20 ventana: set pinmux and power for wlanWei Ni2012-11-15
| | | | | | | | | | | | | | | | Configure pinmux as required for WiFi. Enable the SDHCI1 controller, which is connectted to the WiFi module. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: dt: t20 seaboard: turn on the power for wlanWei Ni2012-11-15
| | | | | | | | | | | | | | Enable the SDHCI1 controller. This is connected to the WiFi module. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: Add Tegra30 host1x clock supportThierry Reding2012-11-15
| | | | | | | | | | | | | | Setup the clock parents for the two display controllers and HDMI. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: Add AUXDATA for Tegra30 host1xThierry Reding2012-11-15
| | | | | | | | | | | | | | | | | | Add the OF_DEV_AUXDATA table entries required to associate the proper names with host1x and its children. In turn, this allows the devices to find the required clocks. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: Add Tegra20 host1x clock supportThierry Reding2012-11-15
| | | | | | | | | | | | | | | | | | Extend the pll_d frequency table with a few entries to support common HDMI and LVDS display modes and setup the clock parents for the two display controllers and HDMI. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: Add AUXDATA for Tegra20 host1xThierry Reding2012-11-15
| | | | | | | | | | | | | | | | | | Add the OF_DEV_AUXDATA table entries required to associate the proper names with host1x and its children. In turn, this allows the devices to find the required clocks. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: Tegra30 speedo-based process identificationDanny Huang2012-11-15
| | | | | | | | | | | | | | | | | | This patch adds speedo-based process identification support for Tegra30. Signed-off-by: Danny Huang <dahuang@nvidia.com> [swarren s/Tegra3/Tegra30/ in log print, s/T30/Tegra30/ in commit description] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: Add speedo-based process identificationDanny Huang2012-11-15
| | | | | | | | | | | | | | | | | | Detect CPU and core process ID by checking speedo corner tables. This can provide a more accurate process ID. Signed-off-by: Danny Huang <dahuang@nvidia.com> [swarren s/Tegra2/Tegra20/ in log print] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: flexible spare fuse read functionDanny Huang2012-11-15
| | | | | | | | | | | | | | | | Change the spare fuse base from a definition to a variable. It provides flexibilty to read spare fuse on different chip. Signed-off-by: Danny Huang <dahuang@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: Implement 6395/1 for TegraPeter De Schrijver2012-11-14
| | | | | | | | | | | | | | | | | | | | This patch implements ARM linux patch 6395/1 for Tegra. See commit 1a8e41c "ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache controller) AuxCtlr register" for details. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> [swarren: added commit subject for referenced patch] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: Add OF_DEV_AUXDATA for sflash driver in board dtLaxman Dewangan2012-11-13
| | | | | | | | | | | | | | | | | | | | Add OF_DEV_AUXDATA for sflash controller driver for Tegra20 board dt files. Set the parent clock of sflash controller to PLLP and configure clock to 20MHz. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: enable data prefetch on L2Joseph Lo2012-11-09
| | | | | | | | | | | | | | | | Enable the data prefetch on L2. The bit28 in aux ctrl register. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
* | ARM: tegra: Add OF_DEV_AUXDATA for SLINK driver in board dtLaxman Dewangan2012-11-05
| | | | | | | | | | | | | | | | | | | | Add OF_DEV_AUXDATA for slink driver for Tegra20 and Tegra30 board dt files. Set the parent clock of slink controller to PLLP and configure clock to 100MHz. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: common: using OF api for L2 cache initJoseph Lo2012-11-05
| | | | | | | | | | | | | | Moving L2 cache init to DT support. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: dt: add L2 cache controllerJoseph Lo2012-11-05
| | | | | | | | | | | | | | Add L2 cache controller binding into DT for Tegra. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra30: clocks: add AHB and APB clocksJoseph Lo2012-11-05
| | | | | | | | | | | | | | Adding the AHB and APB bus clock for Tegra30. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: set up wlan clocks for tegra dtWei Ni2012-11-05
| | | | | | | | | | | | | | Set up the wlan clock tree for Tegra20 and Tegra30. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: move irammap.h to mach-tegraStephen Warren2012-11-05
| | | | | | | | | | | | | | | | | | | | | | | | Nothing outside mach-tegra uses this file, so there's no need for it to be in <mach/>. Since uncompress.h and debug-macro.S remain in include/mach, they need to include "../../irammap.h" becaue of this change. Both these usages will be removed shortly, when Tegra's DEBUG_LL implementation is updated not to pass information through IRAM. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: move iomap.h to mach-tegraStephen Warren2012-11-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Nothing outside mach-tegra uses this file, so there's no need for it to be in <mach/>. Since uncompress.h and debug-macro.S remain in include/mach, they need to include "../../iomap.h" becaue of this change. uncompress.h will soon be deleted in later multi-platform/single-zImage patches. debug-macro.S will need to continue to include this header using an explicit relative path, to avoid duplicating the physical->virtual address mapping that iomap.h dictates. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: remove <mach/dma.h>Stephen Warren2012-11-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove includes of <mach/dma.h> from sound/soc; nothing from it is used. Remove include of <mach/dma.h> from mach-tegra/apbio.c; since the DMA transfers made by this file don't need flow-control with any peripheral, there's no need to set any slave ID. Once those changes are made, there are no remaining users of <mach/dma.h> so remove it. Drivers should get this information from device tree. This removal is necessary for single zImage. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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