diff options
author | Thierry Reding <thierry.reding@avionic-design.de> | 2012-11-15 16:07:54 -0500 |
---|---|---|
committer | Stephen Warren <swarren@nvidia.com> | 2012-11-15 17:07:30 -0500 |
commit | ed821f07090ce13a45ea0aaf8945bcdbc59548c0 (patch) | |
tree | afec6d3491a9de19f9680fd584ec110b915758a3 | |
parent | fea221e254e9842df0740688f30f1ce5a692a775 (diff) |
ARM: tegra: Add Tegra20 host1x support
Add the host1x node along with its children to the Tegra20 DTSI. Board-
specific DTS files are expected to enable the available outputs and
complement the device tree with data specific to the hardware.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
-rw-r--r-- | arch/arm/boot/dts/tegra20.dtsi | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 7850df896f9..fba998e3954 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi | |||
@@ -4,6 +4,93 @@ | |||
4 | compatible = "nvidia,tegra20"; | 4 | compatible = "nvidia,tegra20"; |
5 | interrupt-parent = <&intc>; | 5 | interrupt-parent = <&intc>; |
6 | 6 | ||
7 | host1x { | ||
8 | compatible = "nvidia,tegra20-host1x", "simple-bus"; | ||
9 | reg = <0x50000000 0x00024000>; | ||
10 | interrupts = <0 65 0x04 /* mpcore syncpt */ | ||
11 | 0 67 0x04>; /* mpcore general */ | ||
12 | |||
13 | #address-cells = <1>; | ||
14 | #size-cells = <1>; | ||
15 | |||
16 | ranges = <0x54000000 0x54000000 0x04000000>; | ||
17 | |||
18 | mpe { | ||
19 | compatible = "nvidia,tegra20-mpe"; | ||
20 | reg = <0x54040000 0x00040000>; | ||
21 | interrupts = <0 68 0x04>; | ||
22 | }; | ||
23 | |||
24 | vi { | ||
25 | compatible = "nvidia,tegra20-vi"; | ||
26 | reg = <0x54080000 0x00040000>; | ||
27 | interrupts = <0 69 0x04>; | ||
28 | }; | ||
29 | |||
30 | epp { | ||
31 | compatible = "nvidia,tegra20-epp"; | ||
32 | reg = <0x540c0000 0x00040000>; | ||
33 | interrupts = <0 70 0x04>; | ||
34 | }; | ||
35 | |||
36 | isp { | ||
37 | compatible = "nvidia,tegra20-isp"; | ||
38 | reg = <0x54100000 0x00040000>; | ||
39 | interrupts = <0 71 0x04>; | ||
40 | }; | ||
41 | |||
42 | gr2d { | ||
43 | compatible = "nvidia,tegra20-gr2d"; | ||
44 | reg = <0x54140000 0x00040000>; | ||
45 | interrupts = <0 72 0x04>; | ||
46 | }; | ||
47 | |||
48 | gr3d { | ||
49 | compatible = "nvidia,tegra20-gr3d"; | ||
50 | reg = <0x54180000 0x00040000>; | ||
51 | }; | ||
52 | |||
53 | dc@54200000 { | ||
54 | compatible = "nvidia,tegra20-dc"; | ||
55 | reg = <0x54200000 0x00040000>; | ||
56 | interrupts = <0 73 0x04>; | ||
57 | |||
58 | rgb { | ||
59 | status = "disabled"; | ||
60 | }; | ||
61 | }; | ||
62 | |||
63 | dc@54240000 { | ||
64 | compatible = "nvidia,tegra20-dc"; | ||
65 | reg = <0x54240000 0x00040000>; | ||
66 | interrupts = <0 74 0x04>; | ||
67 | |||
68 | rgb { | ||
69 | status = "disabled"; | ||
70 | }; | ||
71 | }; | ||
72 | |||
73 | hdmi { | ||
74 | compatible = "nvidia,tegra20-hdmi"; | ||
75 | reg = <0x54280000 0x00040000>; | ||
76 | interrupts = <0 75 0x04>; | ||
77 | status = "disabled"; | ||
78 | }; | ||
79 | |||
80 | tvo { | ||
81 | compatible = "nvidia,tegra20-tvo"; | ||
82 | reg = <0x542c0000 0x00040000>; | ||
83 | interrupts = <0 76 0x04>; | ||
84 | status = "disabled"; | ||
85 | }; | ||
86 | |||
87 | dsi { | ||
88 | compatible = "nvidia,tegra20-dsi"; | ||
89 | reg = <0x54300000 0x00040000>; | ||
90 | status = "disabled"; | ||
91 | }; | ||
92 | }; | ||
93 | |||
7 | cache-controller@50043000 { | 94 | cache-controller@50043000 { |
8 | compatible = "arm,pl310-cache"; | 95 | compatible = "arm,pl310-cache"; |
9 | reg = <0x50043000 0x1000>; | 96 | reg = <0x50043000 0x1000>; |