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authorStephen Warren <swarren@nvidia.com>2012-09-19 16:17:24 -0400
committerStephen Warren <swarren@nvidia.com>2012-11-16 14:22:16 -0500
commit73368ba0e168f28ec0b3e689bd428edc92505b62 (patch)
tree5ded0d35584b6c8070f503082581dd6666b65da2
parent380e04ac2cd96a4c36ad164fce556427dcd2ea0f (diff)
ARM: tegra: add TWD to device tree
This will allow timer.c to use twd_local_timer_of_register(), and hence not need to hard-code the TWD address or IRQ. Signed-off-by: Stephen Warren <swarren@nvidia.com>
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi6
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi6
2 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 63c25cefaad..b8effa1cbda 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -91,6 +91,12 @@
91 }; 91 };
92 }; 92 };
93 93
94 timer@50004600 {
95 compatible = "arm,cortex-a9-twd-timer";
96 reg = <0x50040600 0x20>;
97 interrupts = <1 13 0x304>;
98 };
99
94 cache-controller@50043000 { 100 cache-controller@50043000 {
95 compatible = "arm,pl310-cache"; 101 compatible = "arm,pl310-cache";
96 reg = <0x50043000 0x1000>; 102 reg = <0x50043000 0x1000>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index f7af06621cc..547db83af26 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -91,6 +91,12 @@
91 }; 91 };
92 }; 92 };
93 93
94 timer@50004600 {
95 compatible = "arm,cortex-a9-twd-timer";
96 reg = <0x50040600 0x20>;
97 interrupts = <1 13 0xf04>;
98 };
99
94 cache-controller@50043000 { 100 cache-controller@50043000 {
95 compatible = "arm,pl310-cache"; 101 compatible = "arm,pl310-cache";
96 reg = <0x50043000 0x1000>; 102 reg = <0x50043000 0x1000>;