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authorThierry Reding <thierry.reding@avionic-design.de>2012-11-09 08:04:50 -0500
committerStephen Warren <swarren@nvidia.com>2012-11-15 17:07:29 -0500
commitec319903726322198972dd6f95674fdff8d39336 (patch)
treeb41c223f43e2de31725aac9ac79b7d32def80e8c
parentc42cb1c379a6e59e2a04380616f530713658c68b (diff)
ARM: tegra: tamonten: Add DDC/PTA pinmux
This commit allows the I2C2 controller on Tegra20 to be routed either to the DDC or the PTA pin group at runtime. On Tamonten this allows the I2C bus to be used for the DDC of the HDMI connector or to access I2C chips on the carrier board. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
-rw-r--r--arch/arm/boot/dts/tegra20-tamonten.dtsi69
1 files changed, 64 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index 5b3d8b157b3..c3540e033e8 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -62,10 +62,6 @@
62 nvidia,pins = "dap4"; 62 nvidia,pins = "dap4";
63 nvidia,function = "dap4"; 63 nvidia,function = "dap4";
64 }; 64 };
65 ddc {
66 nvidia,pins = "ddc";
67 nvidia,function = "i2c2";
68 };
69 dta { 65 dta {
70 nvidia,pins = "dta", "dtd"; 66 nvidia,pins = "dta", "dtd";
71 nvidia,function = "sdio2"; 67 nvidia,function = "sdio2";
@@ -91,7 +87,7 @@
91 nvidia,function = "pcie"; 87 nvidia,function = "pcie";
92 }; 88 };
93 hdint { 89 hdint {
94 nvidia,pins = "hdint", "pta"; 90 nvidia,pins = "hdint";
95 nvidia,function = "hdmi"; 91 nvidia,function = "hdmi";
96 }; 92 };
97 i2cp { 93 i2cp {
@@ -230,6 +226,39 @@
230 nvidia,pull = <1>; 226 nvidia,pull = <1>;
231 }; 227 };
232 }; 228 };
229
230 state_i2cmux_ddc: pinmux_i2cmux_ddc {
231 ddc {
232 nvidia,pins = "ddc";
233 nvidia,function = "i2c2";
234 };
235 pta {
236 nvidia,pins = "pta";
237 nvidia,function = "rsvd4";
238 };
239 };
240
241 state_i2cmux_pta: pinmux_i2cmux_pta {
242 ddc {
243 nvidia,pins = "ddc";
244 nvidia,function = "rsvd4";
245 };
246 pta {
247 nvidia,pins = "pta";
248 nvidia,function = "i2c2";
249 };
250 };
251
252 state_i2cmux_idle: pinmux_i2cmux_idle {
253 ddc {
254 nvidia,pins = "ddc";
255 nvidia,function = "rsvd4";
256 };
257 pta {
258 nvidia,pins = "pta";
259 nvidia,function = "rsvd4";
260 };
261 };
233 }; 262 };
234 263
235 i2s@70002800 { 264 i2s@70002800 {
@@ -246,6 +275,36 @@
246 status = "okay"; 275 status = "okay";
247 }; 276 };
248 277
278 i2c@7000c400 {
279 clock-frequency = <100000>;
280 status = "okay";
281 };
282
283 i2cmux {
284 compatible = "i2c-mux-pinctrl";
285 #address-cells = <1>;
286 #size-cells = <0>;
287
288 i2c-parent = <&{/i2c@7000c400}>;
289
290 pinctrl-names = "ddc", "pta", "idle";
291 pinctrl-0 = <&state_i2cmux_ddc>;
292 pinctrl-1 = <&state_i2cmux_pta>;
293 pinctrl-2 = <&state_i2cmux_idle>;
294
295 i2c@0 {
296 reg = <0>;
297 #address-cells = <1>;
298 #size-cells = <0>;
299 };
300
301 i2c@1 {
302 reg = <1>;
303 #address-cells = <1>;
304 #size-cells = <0>;
305 };
306 };
307
249 i2c@7000d000 { 308 i2c@7000d000 {
250 clock-frequency = <400000>; 309 clock-frequency = <400000>;
251 status = "okay"; 310 status = "okay";