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-rw-r--r--arch/arm/mach-tegra/p852/Kconfig110
-rw-r--r--arch/arm/mach-tegra/p852/Makefile39
-rw-r--r--arch/arm/mach-tegra/p852/board-p852-gpio.c158
-rw-r--r--arch/arm/mach-tegra/p852/board-p852-i2c.c180
-rw-r--r--arch/arm/mach-tegra/p852/board-p852-panel.c196
-rw-r--r--arch/arm/mach-tegra/p852/board-p852-pinmux.c439
-rw-r--r--arch/arm/mach-tegra/p852/board-p852-power.c209
-rw-r--r--arch/arm/mach-tegra/p852/board-p852-sdhci.c199
-rw-r--r--arch/arm/mach-tegra/p852/board-p852-sku1-b00.c98
-rw-r--r--arch/arm/mach-tegra/p852/board-p852-sku1-c0x.c98
-rw-r--r--arch/arm/mach-tegra/p852/board-p852-sku1.c89
-rw-r--r--arch/arm/mach-tegra/p852/board-p852-sku13-b00.c114
-rw-r--r--arch/arm/mach-tegra/p852/board-p852-sku13.c112
-rw-r--r--arch/arm/mach-tegra/p852/board-p852-sku23-b00.c115
-rw-r--r--arch/arm/mach-tegra/p852/board-p852-sku23-c01.c87
-rw-r--r--arch/arm/mach-tegra/p852/board-p852-sku23.c113
-rw-r--r--arch/arm/mach-tegra/p852/board-p852-sku3.c103
-rw-r--r--arch/arm/mach-tegra/p852/board-p852-sku5-b00.c115
-rw-r--r--arch/arm/mach-tegra/p852/board-p852-sku5-c01.c93
-rw-r--r--arch/arm/mach-tegra/p852/board-p852-sku8-b00.c88
-rw-r--r--arch/arm/mach-tegra/p852/board-p852-sku8-c01.c87
-rw-r--r--arch/arm/mach-tegra/p852/board-p852-sku9-b00.c93
-rw-r--r--arch/arm/mach-tegra/p852/board-p852-sku9-c01.c92
-rw-r--r--arch/arm/mach-tegra/p852/board-p852.c763
-rw-r--r--arch/arm/mach-tegra/p852/board-p852.h300
25 files changed, 4090 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/p852/Kconfig b/arch/arm/mach-tegra/p852/Kconfig
new file mode 100644
index 00000000000..ca44f9543be
--- /dev/null
+++ b/arch/arm/mach-tegra/p852/Kconfig
@@ -0,0 +1,110 @@
1config MACH_P852
2 bool "P852 board"
3 depends on ARCH_TEGRA_2x_SOC
4 help
5 Support for NVIDIA P852 platform
6
7config P852_SKU1
8 bool "P852 SKU1 board"
9 depends on MACH_P852
10 default MACH_P852
11 help
12 Support for NVIDIA P852 SKU1 platform
13
14config P852_SKU1_B00
15 bool "P852 SKU1 rev B board"
16 depends on MACH_P852
17 default MACH_P852
18 help
19 Support for NVIDIA P852 SKU1 B00 platform
20
21config P852_SKU1_C0x
22 bool "P852 SKU1 rev C boards"
23 depends on MACH_P852
24 default MACH_P852
25 help
26 Support for NVIDIA P852 SKU1 C0x platform
27
28config P852_SKU3
29 bool "P852 SKU3 board"
30 depends on MACH_P852
31 default MACH_P852
32 help
33 Support for NVIDIA P852 SKU3 platform
34
35config P852_SKU5_B00
36 bool "P852 SKU5 rev B board"
37 depends on MACH_P852
38 default MACH_P852
39 help
40 Support for NVIDIA P852 SKU5 B00 platform
41
42config P852_SKU5_C01
43 bool "P852 SKU5 rev C board"
44 depends on MACH_P852
45 default MACH_P852
46 help
47 Support for NVIDIA P852 SKU5 C01 platform
48
49config P852_SKU8_B00
50 bool "P852 SKU8 rev B board"
51 depends on MACH_P852
52 default MACH_P852
53 help
54 Support for NVIDIA P852 SKU8 B00 platform
55
56config P852_SKU8_C01
57 bool "P852 SKU8 rev C board"
58 depends on MACH_P852
59 default MACH_P852
60 help
61 Support for NVIDIA P852 SKU8 C01 platform
62
63config P852_SKU9_B00
64 bool "P852 SKU9 rev B board"
65 depends on MACH_P852
66 default MACH_P852
67 help
68 Support for NVIDIA P852 SKU9 B00 platform
69
70config P852_SKU9_C01
71 bool "P852 SKU9 rev C board"
72 depends on MACH_P852
73 default MACH_P852
74 help
75 Support for NVIDIA P852 SKU9 C01 platform
76
77config P852_SKU13
78 bool "P852 SKU13 board"
79 depends on MACH_P852
80 default MACH_P852
81 help
82 Support for NVIDIA P852 SKU13 platform
83
84config P852_SKU13_B00
85 bool "P852 SKU13 rev B board"
86 depends on MACH_P852
87 default MACH_P852
88 help
89 Support for NVIDIA P852 SKU23 B00 platform
90
91config P852_SKU23
92 bool "P852 SKU23 board"
93 depends on MACH_P852
94 default MACH_P852
95 help
96 Support for NVIDIA P852 SKU23 platform
97
98config P852_SKU23_B00
99 bool "P852 SKU23 rev B board"
100 depends on MACH_P852
101 default MACH_P852
102 help
103 Support for NVIDIA P852 SKU23 B00 platform
104
105config P852_SKU23_C01
106 bool "P852 SKU23 rev C board"
107 depends on MACH_P852
108 default MACH_P852
109 help
110 Support for NVIDIA P852 SKU23 C01 platform
diff --git a/arch/arm/mach-tegra/p852/Makefile b/arch/arm/mach-tegra/p852/Makefile
new file mode 100644
index 00000000000..2f04ba08f71
--- /dev/null
+++ b/arch/arm/mach-tegra/p852/Makefile
@@ -0,0 +1,39 @@
1#
2# arch/arm/mach-tegra/p852/Makefile
3#
4# Copyright (c) 2010-2011, NVIDIA Corporation.
5#
6# This software is licensed under the terms of the GNU General Public
7# License version 2, as published by the Free Software Foundation, and
8# may be copied, distributed, and modified under those terms.
9#
10# This program is distributed in the hope that it will be useful,
11# but WITHOUT ANY WARRANTY; without even the implied warranty of
12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13# GNU General Public License for more details.
14#
15#
16
17obj-${CONFIG_MACH_P852} += board-p852.o
18obj-${CONFIG_MACH_P852} += board-p852-sdhci.o
19obj-${CONFIG_MACH_P852} += board-p852-i2c.o
20obj-${CONFIG_MACH_P852} += board-p852-power.o
21obj-${CONFIG_MACH_P852} += board-p852-pinmux.o
22obj-${CONFIG_MACH_P852} += board-p852-gpio.o
23obj-${CONFIG_MACH_P852} += board-p852-panel.o
24
25obj-${CONFIG_P852_SKU1} += board-p852-sku1.o
26obj-${CONFIG_P852_SKU1_B00} += board-p852-sku1-b00.o
27obj-${CONFIG_P852_SKU1_C0x} += board-p852-sku1-c0x.o
28obj-${CONFIG_P852_SKU3} += board-p852-sku3.o
29obj-${CONFIG_P852_SKU5_B00} += board-p852-sku5-b00.o
30obj-${CONFIG_P852_SKU5_C01} += board-p852-sku5-c01.o
31obj-${CONFIG_P852_SKU8_B00} += board-p852-sku8-b00.o
32obj-${CONFIG_P852_SKU8_C01} += board-p852-sku8-c01.o
33obj-${CONFIG_P852_SKU9_B00} += board-p852-sku9-b00.o
34obj-${CONFIG_P852_SKU9_C01} += board-p852-sku9-c01.o
35obj-${CONFIG_P852_SKU13} += board-p852-sku13.o
36obj-${CONFIG_P852_SKU13_B00} += board-p852-sku13-b00.o
37obj-${CONFIG_P852_SKU23} += board-p852-sku23.o
38obj-${CONFIG_P852_SKU23_B00} += board-p852-sku23-b00.o
39obj-${CONFIG_P852_SKU23_C01} += board-p852-sku23-c01.o
diff --git a/arch/arm/mach-tegra/p852/board-p852-gpio.c b/arch/arm/mach-tegra/p852/board-p852-gpio.c
new file mode 100644
index 00000000000..71f568087c5
--- /dev/null
+++ b/arch/arm/mach-tegra/p852/board-p852-gpio.c
@@ -0,0 +1,158 @@
1/*
2 * arch/arm/mach-tegra/board-p852-gpio.c
3 *
4 * Copyright (C) 2010-2011 NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/gpio.h>
19#include <linux/irq.h>
20
21#include "board-p852.h"
22
23static struct gpio p852_sku23_gpios[] = {
24 {TEGRA_GPIO_PW1, GPIOF_OUT_INIT_LOW, "usbpwr0_ena"},
25 {TEGRA_GPIO_PB2, GPIOF_OUT_INIT_LOW, "usbpwr1_ena"},
26 {TEGRA_GPIO_PA0, GPIOF_OUT_INIT_LOW, "a0"},
27 {TEGRA_GPIO_PV2, GPIOF_OUT_INIT_HIGH, "v2"},
28 {TEGRA_GPIO_PT4, GPIOF_OUT_INIT_LOW, "t4"},
29 {TEGRA_GPIO_PD6, GPIOF_OUT_INIT_HIGH, "d6"},
30 {TEGRA_GPIO_PI3, GPIOF_OUT_INIT_LOW, "i3"},
31 {TEGRA_GPIO_PV3, GPIOF_OUT_INIT_HIGH, "v3"},
32 {TEGRA_GPIO_PW4, GPIOF_IN, "w4"},
33 {TEGRA_GPIO_PW5, GPIOF_IN, "w5"},
34 {TEGRA_GPIO_PT1, GPIOF_OUT_INIT_LOW, "t1"},
35 {TEGRA_GPIO_PW3, GPIOF_OUT_INIT_HIGH, "w3"},
36 {TEGRA_GPIO_PD5, GPIOF_IN, "d5"},
37 {TEGRA_GPIO_PBB1, GPIOF_OUT_INIT_LOW, "bb1"},
38};
39
40static struct gpio p852_sku23_b00_gpios[] = {
41 {TEGRA_GPIO_PW1, GPIOF_OUT_INIT_HIGH, "usbpwr0_ena"},
42 {TEGRA_GPIO_PB2, GPIOF_OUT_INIT_HIGH, "usbpwr1_ena"},
43 {TEGRA_GPIO_PA0, GPIOF_OUT_INIT_LOW, "a0"},
44 {TEGRA_GPIO_PV2, GPIOF_OUT_INIT_HIGH, "v2"},
45 {TEGRA_GPIO_PT4, GPIOF_OUT_INIT_LOW, "t4"},
46 {TEGRA_GPIO_PD6, GPIOF_OUT_INIT_HIGH, "d6"},
47 {TEGRA_GPIO_PI3, GPIOF_OUT_INIT_LOW, "i3"},
48 {TEGRA_GPIO_PV3, GPIOF_OUT_INIT_HIGH, "v3"},
49 {TEGRA_GPIO_PW4, GPIOF_IN, "w4"},
50 {TEGRA_GPIO_PW5, GPIOF_IN, "w5"},
51 {TEGRA_GPIO_PT1, GPIOF_OUT_INIT_LOW, "t1"},
52 {TEGRA_GPIO_PW3, GPIOF_OUT_INIT_HIGH, "w3"},
53 {TEGRA_GPIO_PD5, GPIOF_IN, "d5"},
54 {TEGRA_GPIO_PBB1, GPIOF_OUT_INIT_LOW, "bb1"},
55};
56
57static struct gpio p852_sku5_gpios[] = {
58 {TEGRA_GPIO_PW1, GPIOF_OUT_INIT_HIGH, "usbpwr0_ena"},
59 {TEGRA_GPIO_PB2, GPIOF_OUT_INIT_HIGH, "usbpwr1_ena"},
60 {TEGRA_GPIO_PA0, GPIOF_OUT_INIT_LOW, "a0"},
61 {TEGRA_GPIO_PV2, GPIOF_OUT_INIT_HIGH, "v2"},
62 {TEGRA_GPIO_PT4, GPIOF_OUT_INIT_LOW, "t4"},
63 {TEGRA_GPIO_PD6, GPIOF_OUT_INIT_HIGH, "d6"},
64 {TEGRA_GPIO_PI3, GPIOF_OUT_INIT_LOW, "i3"},
65 {TEGRA_GPIO_PV3, GPIOF_OUT_INIT_HIGH, "v3"},
66 {TEGRA_GPIO_PW4, GPIOF_IN, "w4"},
67 {TEGRA_GPIO_PW5, GPIOF_IN, "w5"},
68 {TEGRA_GPIO_PT1, GPIOF_OUT_INIT_LOW, "t1"},
69 {TEGRA_GPIO_PW3, GPIOF_OUT_INIT_HIGH, "w3"},
70 {TEGRA_GPIO_PD5, GPIOF_IN, "d5"},
71 {TEGRA_GPIO_PBB1, GPIOF_OUT_INIT_LOW, "bb1"},
72 {TEGRA_GPIO_PS3, GPIOF_IN, "s3"},
73};
74
75static struct gpio p852_sku8_gpios[] = {
76 {TEGRA_GPIO_PW1, GPIOF_OUT_INIT_HIGH, "w1"},
77 {TEGRA_GPIO_PB2, GPIOF_OUT_INIT_HIGH, "b2"},
78};
79
80static struct gpio p852_sku13_b00_gpios[] = {
81 {TEGRA_GPIO_PW1, GPIOF_OUT_INIT_HIGH, "w1"},
82 {TEGRA_GPIO_PB2, GPIOF_OUT_INIT_HIGH, "b2"},
83 {TEGRA_GPIO_PW2, GPIOF_IN, "w2"},
84 {TEGRA_GPIO_PW3, GPIOF_IN, "w3"},
85 {TEGRA_GPIO_PD5, GPIOF_OUT_INIT_LOW, "d5"},
86 {TEGRA_GPIO_PBB1, GPIOF_OUT_INIT_LOW, "bb1"},
87 {TEGRA_GPIO_PN7, GPIOF_OUT_INIT_LOW, "n7"},
88 {TEGRA_GPIO_PA6, GPIOF_OUT_INIT_HIGH, "a6"},
89 {TEGRA_GPIO_PA7, GPIOF_OUT_INIT_HIGH, "a7"},
90};
91
92static struct gpio p852_gpios[] = {
93 {TEGRA_GPIO_PW1, GPIOF_OUT_INIT_LOW, "w1"},
94 {TEGRA_GPIO_PB2, GPIOF_OUT_INIT_LOW, "b2"},
95 {TEGRA_GPIO_PW2, GPIOF_IN, "w2"},
96 {TEGRA_GPIO_PW3, GPIOF_IN, "w3"},
97 {TEGRA_GPIO_PD5, GPIOF_OUT_INIT_LOW, "d5"},
98 {TEGRA_GPIO_PBB1, GPIOF_OUT_INIT_LOW, "bb1"},
99 {TEGRA_GPIO_PN7, GPIOF_OUT_INIT_LOW, "n7"},
100 {TEGRA_GPIO_PA6, GPIOF_OUT_INIT_HIGH, "a6"},
101 {TEGRA_GPIO_PA7, GPIOF_OUT_INIT_HIGH, "a7"},
102};
103
104void __init p852_gpio_init(void)
105{
106 int pin_count = 0;
107 int i;
108 struct gpio *gpios_info = NULL;
109
110 switch (system_rev) {
111 case P852_SKU23:
112 {
113 gpios_info = p852_sku23_gpios;
114 pin_count = ARRAY_SIZE(p852_sku23_gpios);
115 }
116 break;
117 case P852_SKU23_B00:
118 case P852_SKU23_C01:
119 {
120 gpios_info = p852_sku23_b00_gpios;
121 pin_count = ARRAY_SIZE(p852_sku23_b00_gpios);
122 }
123 break;
124 case P852_SKU5_B00:
125 case P852_SKU5_C01:
126 {
127 gpios_info = p852_sku5_gpios;
128 pin_count = ARRAY_SIZE(p852_sku5_gpios);
129 }
130 break;
131 case P852_SKU8_B00:
132 case P852_SKU8_C01:
133 case P852_SKU9_B00:
134 case P852_SKU9_C01:
135 {
136 gpios_info = p852_sku8_gpios;
137 pin_count = ARRAY_SIZE(p852_sku8_gpios);
138 }
139 break;
140 case P852_SKU13_B00:
141 {
142 gpios_info = p852_sku13_b00_gpios;
143 pin_count = ARRAY_SIZE(p852_sku13_b00_gpios);
144 }
145 break;
146 default:
147 {
148 gpios_info = p852_gpios;
149 pin_count = ARRAY_SIZE(p852_gpios);
150 }
151 }
152
153 gpio_request_array(gpios_info, pin_count);
154 for (i = 0; i < pin_count; i++) {
155 tegra_gpio_enable(gpios_info[i].gpio);
156 gpio_export(gpios_info[i].gpio, true);
157 }
158}
diff --git a/arch/arm/mach-tegra/p852/board-p852-i2c.c b/arch/arm/mach-tegra/p852/board-p852-i2c.c
new file mode 100644
index 00000000000..041ec252b6c
--- /dev/null
+++ b/arch/arm/mach-tegra/p852/board-p852-i2c.c
@@ -0,0 +1,180 @@
1/*
2 * arch/arm/mach-tegra/board-p852-i2c.c
3 *
4 * Copyright (c) 2010-2011, NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/resource.h>
18#include <linux/platform_device.h>
19#include <linux/delay.h>
20#include <linux/gpio.h>
21
22#include <asm/mach-types.h>
23#include <mach/irqs.h>
24#include <mach/iomap.h>
25#include <linux/i2c.h>
26#include <mach/pinmux.h>
27#include <asm/mach-types.h>
28
29#include "board-p852.h"
30
31static struct resource i2c_resource1[] = {
32 [0] = {
33 .start = INT_I2C,
34 .end = INT_I2C,
35 .flags = IORESOURCE_IRQ,
36 },
37 [1] = {
38 .start = TEGRA_I2C_BASE,
39 .end = TEGRA_I2C_BASE + TEGRA_I2C_SIZE - 1,
40 .flags = IORESOURCE_MEM,
41 },
42};
43
44static struct resource i2c_resource2[] = {
45 [0] = {
46 .start = INT_I2C2,
47 .end = INT_I2C2,
48 .flags = IORESOURCE_IRQ,
49 },
50 [1] = {
51 .start = TEGRA_I2C2_BASE,
52 .end = TEGRA_I2C2_BASE + TEGRA_I2C2_SIZE - 1,
53 .flags = IORESOURCE_MEM,
54 },
55};
56
57static struct resource i2c_resource3[] = {
58 [0] = {
59 .start = INT_I2C3,
60 .end = INT_I2C3,
61 .flags = IORESOURCE_IRQ,
62 },
63 [1] = {
64 .start = TEGRA_I2C3_BASE,
65 .end = TEGRA_I2C3_BASE + TEGRA_I2C3_SIZE - 1,
66 .flags = IORESOURCE_MEM,
67 },
68};
69
70static struct resource i2c_resource4[] = {
71 [0] = {
72 .start = INT_DVC,
73 .end = INT_DVC,
74 .flags = IORESOURCE_IRQ,
75 },
76 [1] = {
77 .start = TEGRA_DVC_BASE,
78 .end = TEGRA_DVC_BASE + TEGRA_DVC_SIZE - 1,
79 .flags = IORESOURCE_MEM,
80 },
81};
82
83static const struct tegra_pingroup_config i2c2_ddc = {
84 .pingroup = TEGRA_PINGROUP_DDC,
85 .func = TEGRA_MUX_I2C2,
86};
87
88static const struct tegra_pingroup_config i2c_i2cp = {
89 .pingroup = TEGRA_PINGROUP_I2CP,
90 .func = TEGRA_MUX_I2C,
91};
92
93static struct tegra_i2c_platform_data p852_i2c1_platform_data = {
94 .adapter_nr = 0,
95 .bus_count = 1,
96 .bus_clk_rate = {400000},
97};
98
99static struct tegra_i2c_platform_data p852_i2c2_platform_data = {
100 .adapter_nr = 1,
101 .bus_count = 1,
102 .bus_clk_rate = {100000},
103 .bus_mux = {&i2c2_ddc},
104 .bus_mux_len = {1},
105};
106
107static struct tegra_i2c_platform_data p852_i2c3_platform_data = {
108 .adapter_nr = 2,
109 .bus_count = 1,
110 .bus_clk_rate = {400000},
111};
112
113static struct tegra_i2c_platform_data p852_dvc_platform_data = {
114 .adapter_nr = 3,
115 .bus_count = 1,
116 .bus_clk_rate = {100000},
117 .bus_mux = {&i2c_i2cp},
118 .bus_mux_len = {1},
119 .is_dvc = true,
120};
121
122struct platform_device tegra_i2c_device[] = {
123 {
124 .name = "tegra-i2c",
125 .id = 0,
126 .resource = i2c_resource1,
127 .num_resources = ARRAY_SIZE(i2c_resource1),
128 .dev = {
129 .platform_data = &p852_i2c1_platform_data,
130 },
131 },
132 {
133 .name = "tegra-i2c",
134 .id = 1,
135 .resource = i2c_resource2,
136 .num_resources = ARRAY_SIZE(i2c_resource2),
137 .dev = {
138 .platform_data = &p852_i2c2_platform_data,
139 },
140 },
141 {
142 .name = "tegra-i2c",
143 .id = 2,
144 .resource = i2c_resource3,
145 .num_resources = ARRAY_SIZE(i2c_resource3),
146 .dev = {
147 .platform_data = &p852_i2c3_platform_data,
148 },
149 },
150 {
151 .name = "tegra-i2c",
152 .id = 3,
153 .resource = i2c_resource4,
154 .num_resources = ARRAY_SIZE(i2c_resource4),
155 .dev = {
156 .platform_data = &p852_dvc_platform_data,
157 },
158 }
159};
160
161void __init p852_i2c_set_default_clock(int adapter, unsigned long clock)
162{
163 if (adapter >= 0 && adapter < ARRAY_SIZE(tegra_i2c_device))
164 ((struct tegra_i2c_platform_data *)tegra_i2c_device[adapter].
165 dev.platform_data)->bus_clk_rate[0] = clock;
166}
167
168void __init p852_i2c_init(void)
169{
170 int i;
171 unsigned int i2c_config = 0;
172 if (p852_sku_peripherals & P852_SKU_I2C_ENABLE) {
173 for (i = 0; i < P852_MAX_I2C; i++) {
174 i2c_config =
175 (p852_i2c_peripherals >> (P852_I2C_SHIFT * i));
176 if (i2c_config & P852_I2C_ENABLE)
177 platform_device_register(&tegra_i2c_device[i]);
178 }
179 }
180}
diff --git a/arch/arm/mach-tegra/p852/board-p852-panel.c b/arch/arm/mach-tegra/p852/board-p852-panel.c
new file mode 100644
index 00000000000..c47032dd4f0
--- /dev/null
+++ b/arch/arm/mach-tegra/p852/board-p852-panel.c
@@ -0,0 +1,196 @@
1/*
2 * arch/arm/mach-tegra/board-p852-panel.c
3 *
4 * Copyright (c) 2010-2012, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
19 */
20
21#include <linux/delay.h>
22#include <linux/gpio.h>
23#include <linux/regulator/consumer.h>
24#include <linux/resource.h>
25#include <linux/nvhost.h>
26#include <linux/platform_device.h>
27#include <asm/mach-types.h>
28#include <mach/nvmap.h>
29#include <mach/irqs.h>
30#include <mach/iomap.h>
31#include <mach/dc.h>
32#include <mach/fb.h>
33
34#include "board-p852.h"
35
36#define CARVEOUT_IRAM {\
37 .name = "iram",\
38 .usage_mask = NVMAP_HEAP_CARVEOUT_IRAM,\
39 .base = TEGRA_IRAM_BASE,\
40 .size = TEGRA_IRAM_SIZE,\
41 .buddy_size = 0, /* no buddy allocation for IRAM */\
42}
43
44static int p852_panel_enable(void)
45{
46 pr_info("%s\n", __func__);
47 return 0;
48}
49
50static int p852_panel_disable(void)
51{
52 pr_info("%s\n", __func__);
53 return 0;
54}
55
56static struct resource p852_disp_resources[] = {
57 {
58 .name = "irq",
59 .start = INT_DISPLAY_GENERAL,
60 .end = INT_DISPLAY_GENERAL,
61 .flags = IORESOURCE_IRQ,
62 },
63 {
64 .name = "regs",
65 .start = TEGRA_DISPLAY_BASE,
66 .end = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1,
67 .flags = IORESOURCE_MEM,
68 },
69 {
70 .name = "fbmem",
71 .start = 0,
72 .end = 0,
73 .flags = IORESOURCE_MEM,
74 },
75};
76
77static struct tegra_dc_mode p852_panel_modes[] = {
78/* Timings for the LG LB070WV4 panel */
79 {
80 .pclk = 33230769,
81
82 .h_ref_to_sync = 1,
83 .v_ref_to_sync = 1,
84
85 .h_sync_width = 128,
86 .v_sync_width = 2,
87
88 .h_back_porch = 88,
89 .v_back_porch = 30,
90
91 .h_front_porch = 40,
92 .v_front_porch = 13,
93
94 .h_active = 800,
95 .v_active = 480,
96 },
97};
98
99static struct tegra_fb_data p852_fb_data = {
100 .win = 0,
101 .xres = 800,
102 .yres = 480,
103 .bits_per_pixel = 16,
104};
105
106static struct tegra_dc_out p852_disp_out = {
107 .type = TEGRA_DC_OUT_RGB,
108
109 .align = TEGRA_DC_ALIGN_MSB,
110 .order = TEGRA_DC_ORDER_RED_BLUE,
111
112 .modes = p852_panel_modes,
113 .n_modes = ARRAY_SIZE(p852_panel_modes),
114
115 .enable = p852_panel_enable,
116 .disable = p852_panel_disable,
117};
118
119static struct tegra_dc_platform_data p852_disp_pdata = {
120 .flags = TEGRA_DC_FLAG_ENABLED,
121 .default_out = &p852_disp_out,
122 .fb = &p852_fb_data,
123};
124
125static struct nvhost_device p852_disp_device = {
126 .name = "tegradc",
127 .id = 0,
128 .resource = p852_disp_resources,
129 .num_resources = ARRAY_SIZE(p852_disp_resources),
130 .dev = {
131 .platform_data = &p852_disp_pdata,
132 },
133};
134
135static struct nvmap_platform_carveout p852_carveouts[] = {
136 [0] = CARVEOUT_IRAM,
137 [1] = {
138 .name = "generic-0",
139 .usage_mask = NVMAP_HEAP_CARVEOUT_GENERIC,
140 .base = 0,
141 .size = 0,
142 .buddy_size = SZ_32K,
143 },
144};
145
146static struct nvmap_platform_data p852_nvmap_data = {
147 .carveouts = p852_carveouts,
148 .nr_carveouts = ARRAY_SIZE(p852_carveouts),
149};
150
151static struct platform_device p852_nvmap_device = {
152 .name = "tegra-nvmap",
153 .id = -1,
154 .dev = {
155 .platform_data = &p852_nvmap_data,
156 },
157};
158
159static struct platform_device *p852_gfx_devices[] __initdata = {
160 &tegra_pwfm2_device,
161};
162
163int __init p852_panel_init(void)
164{
165 int err;
166 struct resource *res;
167
168 pr_info("%s\n", __func__);
169
170 p852_carveouts[1].base = tegra_carveout_start;
171 p852_carveouts[1].size = tegra_carveout_size;
172
173 err = platform_device_register(&p852_nvmap_device);
174 if (err)
175 return err;
176
177#ifdef CONFIG_TEGRA_GRHOST
178 err = nvhost_device_register(&tegra_grhost_device);
179 if (err)
180 return err;
181#endif
182
183 err = platform_add_devices(p852_gfx_devices,
184 ARRAY_SIZE(p852_gfx_devices));
185
186 res = nvhost_get_resource_byname(&p852_disp_device,
187 IORESOURCE_MEM, "fbmem");
188
189 res->start = tegra_fb_start;
190 res->end = tegra_fb_start + tegra_fb_size - 1;
191
192 if (!err)
193 err = nvhost_device_register(&p852_disp_device);
194
195 return err;
196}
diff --git a/arch/arm/mach-tegra/p852/board-p852-pinmux.c b/arch/arm/mach-tegra/p852/board-p852-pinmux.c
new file mode 100644
index 00000000000..0ded989f7a1
--- /dev/null
+++ b/arch/arm/mach-tegra/p852/board-p852-pinmux.c
@@ -0,0 +1,439 @@
1/*
2 * arch/arm/mach-tegra/board-p852-pinmux.c
3 *
4 * Copyright (c) 2010-2011, NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <mach/pinmux.h>
20#include <asm/mach-types.h>
21
22#include "board-p852.h"
23
24#define DEFAULT_DRIVE(_name) \
25 { \
26 .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \
27 .hsm = TEGRA_HSM_DISABLE, \
28 .schmitt = TEGRA_SCHMITT_ENABLE, \
29 .drive = TEGRA_DRIVE_DIV_1, \
30 .pull_down = TEGRA_PULL_31, \
31 .pull_up = TEGRA_PULL_31, \
32 .slew_rising = TEGRA_SLEW_SLOWEST, \
33 .slew_falling = TEGRA_SLEW_SLOWEST, \
34 }
35
36#define P852_PAD_DRIVE(_name) \
37 { \
38 .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \
39 .hsm = TEGRA_HSM_DISABLE, \
40 .schmitt = TEGRA_SCHMITT_DISABLE, \
41 .drive = TEGRA_DRIVE_DIV_1, \
42 .pull_down = TEGRA_PULL_18, \
43 .pull_up = TEGRA_PULL_22, \
44 .slew_rising = TEGRA_SLEW_SLOWEST, \
45 .slew_falling = TEGRA_SLEW_SLOWEST, \
46 }
47
48#define P852_PAD_DRIVE_HSM(_name) \
49 { \
50 .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \
51 .hsm = TEGRA_HSM_ENABLE, \
52 .schmitt = TEGRA_SCHMITT_ENABLE, \
53 .drive = TEGRA_DRIVE_DIV_1, \
54 .pull_down = TEGRA_PULL_31, \
55 .pull_up = TEGRA_PULL_31, \
56 .slew_rising = TEGRA_SLEW_SLOWEST, \
57 .slew_falling = TEGRA_SLEW_SLOWEST, \
58 }
59
60#define DAP_PAD_DRIVE(_name) \
61 { \
62 .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \
63 .hsm = TEGRA_HSM_DISABLE, \
64 .schmitt = TEGRA_SCHMITT_ENABLE, \
65 .drive = TEGRA_DRIVE_DIV_1, \
66 .pull_down = TEGRA_PULL_3, \
67 .pull_up = TEGRA_PULL_3, \
68 .slew_rising = TEGRA_SLEW_SLOWEST, \
69 .slew_falling = TEGRA_SLEW_SLOWEST, \
70 }
71
72static __initdata struct tegra_drive_pingroup_config p852_drive_pinmux[] = {
73 DEFAULT_DRIVE(DBG),
74 DEFAULT_DRIVE(DDC),
75 DEFAULT_DRIVE(VI1),
76 DEFAULT_DRIVE(VI2),
77 DEFAULT_DRIVE(SDIO1),
78 P852_PAD_DRIVE(SPI),
79 DAP_PAD_DRIVE(DAP1),
80 DAP_PAD_DRIVE(DAP2),
81 DEFAULT_DRIVE(CDEV1),
82 DEFAULT_DRIVE(CDEV2),
83};
84
85static __initdata struct tegra_drive_pingroup_config
86 p852_drive_pinmux_sku8_sku9[] = {
87 DAP_PAD_DRIVE(DAP3),
88};
89
90
91static __initdata struct tegra_pingroup_config p852_common_pinmux[] = {
92 {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
93 {TEGRA_PINGROUP_LSDI, TEGRA_MUX_SPI3, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
94 {TEGRA_PINGROUP_LSDA, TEGRA_MUX_SPI3, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
95 {TEGRA_PINGROUP_LCSN, TEGRA_MUX_SPI3, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
96 {TEGRA_PINGROUP_LSCK, TEGRA_MUX_SPI3, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
97 {TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
98 {TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
99 {TEGRA_PINGROUP_DTD, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
100 {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
101 {TEGRA_PINGROUP_DTB, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
102 {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
103 {TEGRA_PINGROUP_DTE, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
104 {TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
105 /* IRDA is same as UART2 option for the pingroup */
106 {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
107 {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
108 {TEGRA_PINGROUP_KBCA, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
109 {TEGRA_PINGROUP_KBCD, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
110 {TEGRA_PINGROUP_KBCB, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
111 {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
112 {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
113 {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
114 {TEGRA_PINGROUP_SPDI, TEGRA_MUX_SPDIF, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
115 {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
116 {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
117 {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
118 {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
119 {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
120 {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
121 {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
122 {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
123 {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
124 {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
125 {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
126 {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
127 {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
128 {TEGRA_PINGROUP_UAC, TEGRA_MUX_OWR, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
129 {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
130 {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
131 {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
132 {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
133 {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
134 {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
135 {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
136 {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
137 {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
138 {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
139 {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
140 {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
141 {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
142 {TEGRA_PINGROUP_GMD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
143 {TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
144};
145
146static __initdata struct tegra_pingroup_config p852_nand_pinmux[] = {
147 {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
148 {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
149 {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
150 {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
151 {TEGRA_PINGROUP_GPU, TEGRA_MUX_UARTA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
152 {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
153 {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
154 {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
155 {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
156 {TEGRA_PINGROUP_ATA, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
157 {TEGRA_PINGROUP_GMB, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
158 {TEGRA_PINGROUP_DAP4, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
159 {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
160 {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
161 {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
162 {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
163 {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
164 {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
165};
166
167static __initdata struct tegra_pingroup_config p852_sdio3_pinmux[] = {
168 {TEGRA_PINGROUP_SDD, TEGRA_MUX_SDIO3, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
169 {TEGRA_PINGROUP_SDC, TEGRA_MUX_SDIO3, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
170 {TEGRA_PINGROUP_SDB, TEGRA_MUX_SDIO3, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
171};
172
173static __initdata struct tegra_pingroup_config p852_uarta_pinmux[] = {
174 {TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
175 {TEGRA_PINGROUP_SDC, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
176 {TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
177};
178
179static __initdata struct tegra_pingroup_config p852_ulpi_pinmux[] = {
180 {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
181 {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
182 {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
183};
184
185static __initdata struct tegra_pingroup_config p852_uarta_1_pinmux[] = {
186 {TEGRA_PINGROUP_UAA, TEGRA_MUX_UARTA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
187 {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
188 {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
189};
190
191static __initdata struct tegra_pingroup_config p852_uartd_pinmux[] = {
192 {TEGRA_PINGROUP_GMC, TEGRA_MUX_UARTD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
193};
194
195static __initdata struct tegra_pingroup_config p852_spi4_pinmux[] = {
196 {TEGRA_PINGROUP_GMC, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
197 {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
198 {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
199 {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
200 {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
201};
202
203static __initdata struct tegra_pingroup_config p852_spi4_1_pinmux[] = {
204 {TEGRA_PINGROUP_SLXA, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
205 {TEGRA_PINGROUP_SLXK, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
206 {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
207 {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
208};
209
210static __initdata struct tegra_pingroup_config p852_nor_pinmux[] = {
211 {TEGRA_PINGROUP_IRRX, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
212 {TEGRA_PINGROUP_IRTX, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
213 {TEGRA_PINGROUP_UCA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
214 {TEGRA_PINGROUP_UCB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
215 {TEGRA_PINGROUP_GPU, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
216 {TEGRA_PINGROUP_DAP2, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
217 {TEGRA_PINGROUP_SPID, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
218 {TEGRA_PINGROUP_SPIE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
219 {TEGRA_PINGROUP_ATC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
220 {TEGRA_PINGROUP_ATA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
221 {TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
222 {TEGRA_PINGROUP_DAP4, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
223 {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
224 {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
225 {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
226 {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
227 {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
228 {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
229};
230
231static __initdata struct tegra_pingroup_config p852_display_a_pinmux[] = {
232 {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
233 {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
234 {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
235 {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
236 {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
237 {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
238 {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
239 {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
240 {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
241 {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
242 {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
243 {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
244 {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
245 {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
246 {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
247 {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
248 {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
249 {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
250 {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
251 {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
252 {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
253 {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
254 {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
255 {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
256 {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
257 {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
258 {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
259 {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
260 {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
261 {TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
262 {TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
263 {TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
264 {TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
265 {TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
266 {TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
267 {TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
268};
269
270static __initdata struct tegra_pingroup_config p852_display_b_pinmux[] = {
271 {TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
272 {TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
273 {TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
274 {TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
275 {TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
276 {TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
277 {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
278 {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
279 {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
280 {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
281 {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
282 {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
283 {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
284 {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
285 {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
286 {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
287 {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
288 {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
289 {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
290 {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
291 {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
292 {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
293 {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
294 {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
295 {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
296 {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
297 {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
298 {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
299 {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
300 {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
301 {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
302 {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
303 {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
304 {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
305 {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
306 {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
307 {TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
308};
309
310static __initdata struct tegra_drive_pingroup_config
311 p852_drive_pinmux_sku23[] = {
312 P852_PAD_DRIVE_HSM(SDMMC3),
313};
314
315static __initdata struct tegra_drive_pingroup_config
316 p852_drive_pinmux_sku13[] = {
317 P852_PAD_DRIVE_HSM(SDMMC3),
318};
319
320static __initdata struct tegra_pingroup_config p852_pupd_sku23[] = {
321 {TEGRA_PINGROUP_GPV, TEGRA_MUX_NONE, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
322 {TEGRA_PINGROUP_GMC, TEGRA_MUX_NONE, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
323 {TEGRA_PINGROUP_DTB, TEGRA_MUX_NONE, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
324};
325
326
327static __initdata struct tegra_pingroup_config p852_pupd_sku13[] = {
328 {TEGRA_PINGROUP_GPV, TEGRA_MUX_NONE, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
329};
330
331static __initdata struct tegra_pingroup_config p852_pupd_sku5[] = {
332 {TEGRA_PINGROUP_GMC, TEGRA_MUX_NONE, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
333 {TEGRA_PINGROUP_DTB, TEGRA_MUX_NONE, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
334};
335
336static void tegra_pinmux_config_pupd_table(
337 const struct tegra_pingroup_config *config,
338 int len)
339{
340 int i;
341 for (i = 0; i < len; i++) {
342 /* config.func, the pin_mux setting is not used here */
343 tegra_pinmux_config_pullupdown_table(&config[i], 1,
344 config[i].pupd);
345 }
346}
347
348void __init p852_pinmux_init(void)
349{
350 unsigned int sdio3_config = (p852_sdhci_peripherals >>
351 P852_SDHCI3_SHIFT) & P852_SDHCI_MASK;
352 unsigned int uartd_config = (p852_uart_peripherals >> P852_UARTD_SHIFT)
353 & P852_UART_MASK;
354 unsigned int uarta_config = (p852_uart_peripherals >> P852_UARTA_SHIFT)
355 & P852_UART_MASK;
356 unsigned int spi4_config = (p852_spi_peripherals >> P852_SPI4_SHIFT)
357 & P852_SPI_MASK;
358 unsigned int displayb_config = (p852_display_peripherals >>
359 P852_DISPB_SHIFT) & P852_DISP_MASK;
360
361 tegra_pinmux_config_table(p852_common_pinmux,
362 ARRAY_SIZE(p852_common_pinmux));
363
364 if ((uarta_config & P852_UART_ENABLE)
365 && (uarta_config & P852_UART_ALT_PIN_CFG)) {
366 tegra_pinmux_config_table(p852_uarta_1_pinmux,
367 ARRAY_SIZE(p852_uarta_1_pinmux));
368 } else {
369 tegra_pinmux_config_table(p852_ulpi_pinmux,
370 ARRAY_SIZE(p852_ulpi_pinmux));
371 }
372
373 if (sdio3_config & P852_SDHCI_ENABLE) {
374 tegra_pinmux_config_table(p852_sdio3_pinmux,
375 ARRAY_SIZE(p852_sdio3_pinmux));
376 } else {
377 tegra_pinmux_config_table(p852_uarta_pinmux,
378 ARRAY_SIZE(p852_uarta_pinmux));
379 }
380
381 if ((uartd_config & P852_UART_ENABLE) &&
382 (spi4_config & P852_SPI_ENABLE)) {
383 tegra_pinmux_config_table(p852_uartd_pinmux,
384 ARRAY_SIZE(p852_uartd_pinmux));
385 tegra_pinmux_config_table(p852_spi4_1_pinmux,
386 ARRAY_SIZE(p852_spi4_1_pinmux));
387 } else {
388 tegra_pinmux_config_table(p852_spi4_pinmux,
389 ARRAY_SIZE(p852_spi4_pinmux));
390 }
391
392 if (p852_sku_peripherals & P852_SKU_NOR_ENABLE) {
393 tegra_pinmux_config_table(p852_nor_pinmux,
394 ARRAY_SIZE(p852_nor_pinmux));
395 } else {
396 tegra_pinmux_config_table(p852_nand_pinmux,
397 ARRAY_SIZE(p852_nand_pinmux));
398 }
399
400 if (p852_sku_peripherals & P852_SKU_DISPLAY_ENABLE) {
401 if (displayb_config) {
402 tegra_pinmux_config_table(p852_display_b_pinmux,
403 ARRAY_SIZE(p852_display_b_pinmux));
404 } else {
405 tegra_pinmux_config_table(p852_display_a_pinmux,
406 ARRAY_SIZE(p852_display_a_pinmux));
407 }
408 }
409
410 tegra_drive_pinmux_config_table(p852_drive_pinmux,
411 ARRAY_SIZE(p852_drive_pinmux));
412
413 if (system_rev == P852_SKU23 ||
414 system_rev == P852_SKU23_B00 ||
415 system_rev == P852_SKU23_C01) {
416 tegra_drive_pinmux_config_table(p852_drive_pinmux_sku23,
417 ARRAY_SIZE(p852_drive_pinmux_sku23));
418
419 tegra_pinmux_config_pupd_table(p852_pupd_sku23,
420 ARRAY_SIZE(p852_pupd_sku23));
421 } else if (system_rev == P852_SKU13 ||
422 system_rev == P852_SKU13_B00) {
423 tegra_drive_pinmux_config_table(p852_drive_pinmux_sku13,
424 ARRAY_SIZE(p852_drive_pinmux_sku13));
425
426 tegra_pinmux_config_pupd_table(p852_pupd_sku13,
427 ARRAY_SIZE(p852_pupd_sku13));
428 } else if (system_rev == P852_SKU5_B00 || system_rev == P852_SKU5_C01) {
429 tegra_pinmux_config_pupd_table(p852_pupd_sku5,
430 ARRAY_SIZE(p852_pupd_sku5));
431 } else if (system_rev == P852_SKU8_B00 || system_rev == P852_SKU9_B00 ||
432 system_rev == P852_SKU8_C01 || system_rev == P852_SKU9_C01) {
433 tegra_drive_pinmux_config_table(p852_drive_pinmux_sku8_sku9,
434 ARRAY_SIZE(p852_drive_pinmux_sku8_sku9));
435 }
436
437}
438
439
diff --git a/arch/arm/mach-tegra/p852/board-p852-power.c b/arch/arm/mach-tegra/p852/board-p852-power.c
new file mode 100644
index 00000000000..71f6e85d25c
--- /dev/null
+++ b/arch/arm/mach-tegra/p852/board-p852-power.c
@@ -0,0 +1,209 @@
1/*
2 * arch/arm/mach-tegra/p852/board-p852-power.c
3 *
4 * Copyright (c) 2010-2011, NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/i2c.h>
18#include <linux/pda_power.h>
19#include <linux/platform_device.h>
20#include <linux/resource.h>
21#include <linux/regulator/machine.h>
22#include <linux/mfd/tps6586x.h>
23#include <linux/gpio.h>
24#include <linux/io.h>
25#include <mach/iomap.h>
26#include <mach/irqs.h>
27#include "board-p852.h"
28
29#define PMC_CTRL 0x0
30#define PMC_CTRL_INTR_LOW (1 << 17)
31
32static struct regulator_consumer_supply tps658621_sm0_supply[] = {
33 REGULATOR_SUPPLY("vdd_core", NULL),
34};
35static struct regulator_consumer_supply tps658621_sm1_supply[] = {
36 REGULATOR_SUPPLY("vdd_cpu", NULL),
37};
38static struct regulator_consumer_supply tps658621_sm2_supply[] = {
39 REGULATOR_SUPPLY("vdd_sm2", NULL),
40};
41static struct regulator_consumer_supply tps658621_ldo0_supply[] = {
42 REGULATOR_SUPPLY("vddio_pex_clk", NULL),
43};
44static struct regulator_consumer_supply tps658621_ldo1_supply[] = {
45 REGULATOR_SUPPLY("avdd_pll", NULL),
46 REGULATOR_SUPPLY("avdd_plla_pc", NULL),
47 REGULATOR_SUPPLY("avdd_pllm", NULL),
48 REGULATOR_SUPPLY("avdd_pllu", NULL),
49 REGULATOR_SUPPLY("avdd_pllx6", NULL),
50};
51static struct regulator_consumer_supply tps658621_ldo2_supply[] = {
52 REGULATOR_SUPPLY("vdd_rtc", NULL),
53};
54static struct regulator_consumer_supply tps658621_ldo3_supply[] = {
55 REGULATOR_SUPPLY("avdd_usb", NULL),
56 REGULATOR_SUPPLY("avdd_usb_pll", NULL),
57 REGULATOR_SUPPLY("avdd_lvds", NULL),
58};
59static struct regulator_consumer_supply tps658621_ldo4_supply[] = {
60 REGULATOR_SUPPLY("avdd_osc", NULL),
61 REGULATOR_SUPPLY("vddio_sys", "panjit_touch"),
62};
63static struct regulator_consumer_supply tps658621_ldo5_supply[] = {
64 REGULATOR_SUPPLY("vddio_lcd", NULL),
65};
66static struct regulator_consumer_supply tps658621_ldo6_supply[] = {
67 REGULATOR_SUPPLY("avdd_vdac", NULL),
68};
69static struct regulator_consumer_supply tps658621_ldo7_supply[] = {
70 REGULATOR_SUPPLY("vddio_vi", NULL),
71 REGULATOR_SUPPLY("vdd_fuse", NULL),
72 REGULATOR_SUPPLY("vspi", "spi_tegra.0"),
73};
74static struct regulator_consumer_supply tps658621_ldo8_supply[] = {
75 REGULATOR_SUPPLY("vddio_bb", NULL),
76 REGULATOR_SUPPLY("vmmc", "sdhci-tegra.0"),
77 REGULATOR_SUPPLY("vmmc", "sdhci-tegra.2"),
78};
79static struct regulator_consumer_supply tps658621_ldo9_supply[] = {
80 REGULATOR_SUPPLY("vdd_ddr_rx", NULL),
81 REGULATOR_SUPPLY("vmmc", "sdhci-tegra.3"),
82};
83
84#define REGULATOR_INIT(_id, _minmv, _maxmv) \
85 { \
86 .constraints = { \
87 .min_uV = (_minmv)*1000, \
88 .max_uV = (_maxmv)*1000, \
89 .valid_modes_mask = (REGULATOR_MODE_NORMAL | \
90 REGULATOR_MODE_STANDBY), \
91 .valid_ops_mask = (REGULATOR_CHANGE_MODE | \
92 REGULATOR_CHANGE_STATUS | \
93 REGULATOR_CHANGE_VOLTAGE), \
94 }, \
95 .num_consumer_supplies = ARRAY_SIZE(tps658621_##_id##_supply),\
96 .consumer_supplies = tps658621_##_id##_supply, \
97 }
98
99static struct regulator_init_data sm0_data = REGULATOR_INIT(sm0, 725, 1500);
100static struct regulator_init_data sm1_data = REGULATOR_INIT(sm1, 725, 1500);
101static struct regulator_init_data sm2_data = REGULATOR_INIT(sm2, 3000, 4550);
102static struct regulator_init_data ldo0_data = REGULATOR_INIT(ldo0, 1250, 3300);
103static struct regulator_init_data ldo1_data = REGULATOR_INIT(ldo1, 725, 1500);
104static struct regulator_init_data ldo2_data = REGULATOR_INIT(ldo2, 725, 1225);
105static struct regulator_init_data ldo3_data = REGULATOR_INIT(ldo3, 1250, 3300);
106static struct regulator_init_data ldo4_data = REGULATOR_INIT(ldo4, 1700, 2475);
107static struct regulator_init_data ldo5_data = REGULATOR_INIT(ldo5, 1250, 3300);
108static struct regulator_init_data ldo6_data = REGULATOR_INIT(ldo6, 1250, 3300);
109static struct regulator_init_data ldo7_data = REGULATOR_INIT(ldo7, 1250, 3300);
110static struct regulator_init_data ldo8_data = REGULATOR_INIT(ldo8, 1250, 3300);
111static struct regulator_init_data ldo9_data = REGULATOR_INIT(ldo9, 1250, 3300);
112
113
114static struct tps6586x_rtc_platform_data rtc_data = {
115 .irq = TEGRA_NR_IRQS + TPS6586X_INT_RTC_ALM1,
116 .cl_sel = 0,
117};
118
119
120#define TPS_REG(_id, _data) \
121 { \
122 .id = TPS6586X_ID_##_id, \
123 .name = "tps6586x-regulator", \
124 .platform_data = _data, \
125 }
126
127static struct tps6586x_subdev_info tps_devs[] = {
128 TPS_REG(SM_0, &sm0_data),
129 TPS_REG(SM_1, &sm1_data),
130 TPS_REG(SM_2, &sm2_data),
131 TPS_REG(LDO_0, &ldo0_data),
132 TPS_REG(LDO_1, &ldo1_data),
133 TPS_REG(LDO_2, &ldo2_data),
134 TPS_REG(LDO_3, &ldo3_data),
135 TPS_REG(LDO_4, &ldo4_data),
136 TPS_REG(LDO_5, &ldo5_data),
137 TPS_REG(LDO_6, &ldo6_data),
138 TPS_REG(LDO_7, &ldo7_data),
139 TPS_REG(LDO_8, &ldo8_data),
140 TPS_REG(LDO_9, &ldo9_data),
141 {
142 .id = 0,
143 .name = "tps6586x-rtc",
144 .platform_data = &rtc_data,
145 },
146};
147
148static struct tps6586x_platform_data tps_platform = {
149 .irq_base = TEGRA_NR_IRQS,
150 .num_subdevs = ARRAY_SIZE(tps_devs),
151 .subdevs = tps_devs,
152 .gpio_base = TEGRA_NR_GPIOS,
153 .use_power_off = true,
154};
155
156static struct i2c_board_info __initdata p852_regulators[] = {
157 {
158 I2C_BOARD_INFO("tps6586x", 0x34),
159 .irq = INT_EXTERNAL_PMU,
160 .platform_data = &tps_platform,
161 },
162};
163
164static struct tegra_suspend_platform_data p852_suspend_data = {
165 .cpu_timer = 2000,
166 .cpu_off_timer = 0,
167 .suspend_mode = TEGRA_SUSPEND_LP1,
168 .core_timer = 0x7e7e,
169 .core_off_timer = 0,
170 .corereq_high = false,
171 .sysclkreq_high = true,
172};
173
174static void __init tps6586x_rtc_preinit(void)
175{
176 int i;
177 struct tps6586x_rtc_platform_data *rtc_pdata;
178
179 if (system_rev == P852_SKU23_B00 ||
180 system_rev == P852_SKU23_C01 ||
181 system_rev == P852_SKU13_B00 ||
182 system_rev == P852_SKU5_B00 ||
183 system_rev == P852_SKU5_C01) {
184 for (i = 0; i < tps_platform.num_subdevs; ++i)
185 if (!strcmp(tps_platform.subdevs[i].name,
186 "tps6586x-rtc"))
187 rtc_pdata =
188 (struct tps6586x_rtc_platform_data *)
189 (tps_platform.subdevs[i].platform_data);
190 rtc_pdata->cl_sel = TPS6586X_RTC_CL_SEL_1_5PF;
191 }
192}
193
194int __init p852_regulator_init(void)
195{
196 void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
197 u32 pmc_ctrl;
198
199 /* configure the power management controller to trigger PMU
200 * interrupts when low */
201 pmc_ctrl = readl(pmc + PMC_CTRL);
202 writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
203 i2c_register_board_info(3, p852_regulators, 1);
204 tegra_init_suspend(&p852_suspend_data);
205
206 tps6586x_rtc_preinit();
207
208 return 0;
209}
diff --git a/arch/arm/mach-tegra/p852/board-p852-sdhci.c b/arch/arm/mach-tegra/p852/board-p852-sdhci.c
new file mode 100644
index 00000000000..dc5b81fa372
--- /dev/null
+++ b/arch/arm/mach-tegra/p852/board-p852-sdhci.c
@@ -0,0 +1,199 @@
1/*
2 * arch/arm/mach-tegra/board-p852-sdhci.c
3 *
4 * Copyright (c) 2010-2011, NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/resource.h>
18#include <linux/platform_device.h>
19#include <linux/delay.h>
20#include <linux/gpio.h>
21
22#include <asm/mach-types.h>
23#include <mach/irqs.h>
24#include <mach/iomap.h>
25#include <mach/sdhci.h>
26#include <mach/pinmux.h>
27#include <asm/mach-types.h>
28
29#include "board-p852.h"
30
31static struct resource sdhci_resource1[] = {
32 [0] = {
33 .start = INT_SDMMC1,
34 .end = INT_SDMMC1,
35 .flags = IORESOURCE_IRQ,
36 },
37 [1] = {
38 .start = TEGRA_SDMMC1_BASE,
39 .end = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE - 1,
40 .flags = IORESOURCE_MEM,
41 },
42};
43
44static struct resource sdhci_resource2[] = {
45 [0] = {
46 .start = INT_SDMMC2,
47 .end = INT_SDMMC2,
48 .flags = IORESOURCE_IRQ,
49 },
50 [1] = {
51 .start = TEGRA_SDMMC2_BASE,
52 .end = TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE - 1,
53 .flags = IORESOURCE_MEM,
54 },
55};
56
57static struct resource sdhci_resource3[] = {
58 [0] = {
59 .start = INT_SDMMC3,
60 .end = INT_SDMMC3,
61 .flags = IORESOURCE_IRQ,
62 },
63 [1] = {
64 .start = TEGRA_SDMMC3_BASE,
65 .end = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE - 1,
66 .flags = IORESOURCE_MEM,
67 },
68};
69
70static struct resource sdhci_resource4[] = {
71 [0] = {
72 .start = INT_SDMMC4,
73 .end = INT_SDMMC4,
74 .flags = IORESOURCE_IRQ,
75 },
76 [1] = {
77 .start = TEGRA_SDMMC4_BASE,
78 .end = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE - 1,
79 .flags = IORESOURCE_MEM,
80 },
81};
82
83struct tegra_sdhci_platform_data p852_sdhci_platform_data[] = {
84 {
85 .cd_gpio = -1,
86 .wp_gpio = -1,
87 .power_gpio = -1,
88 },
89 {
90 .cd_gpio = -1,
91 .wp_gpio = -1,
92 .power_gpio = -1,
93 },
94 {
95 .cd_gpio = -1,
96 .wp_gpio = -1,
97 .power_gpio = -1,
98 },
99 {
100 .cd_gpio = -1,
101 .wp_gpio = -1,
102 .power_gpio = -1,
103 },
104};
105
106static struct platform_device tegra_sdhci_device[] = {
107 {
108 .name = "sdhci-tegra",
109 .id = 0,
110 .resource = sdhci_resource1,
111 .num_resources = ARRAY_SIZE(sdhci_resource1),
112 .dev = {
113 .platform_data = &p852_sdhci_platform_data[0],
114 },
115 },
116 {
117 .name = "sdhci-tegra",
118 .id = 1,
119 .resource = sdhci_resource2,
120 .num_resources = ARRAY_SIZE(sdhci_resource2),
121 .dev = {
122 .platform_data = &p852_sdhci_platform_data[1],
123 },
124 },
125 {
126 .name = "sdhci-tegra",
127 .id = 2,
128 .resource = sdhci_resource3,
129 .num_resources = ARRAY_SIZE(sdhci_resource3),
130 .dev = {
131 .platform_data = &p852_sdhci_platform_data[2],
132 },
133 },
134 {
135 .name = "sdhci-tegra",
136 .id = 3,
137 .resource = sdhci_resource4,
138 .num_resources = ARRAY_SIZE(sdhci_resource4),
139 .dev = {
140 .platform_data = &p852_sdhci_platform_data[3],
141 },
142 },
143
144};
145
146void __init p852_sdhci_init(void)
147{
148
149 int i, count = 10;
150 int cd = 0, wp = 0, pw = 0;
151 static char gpio_name[12][10];
152 unsigned int sdhci_config = 0;
153
154 if (p852_sku_peripherals & P852_SKU_SDHCI_ENABLE)
155 for (i = 0; i < P852_MAX_SDHCI; i++) {
156 sdhci_config =
157 (p852_sdhci_peripherals >> (P852_SDHCI_SHIFT * i));
158 cd = i * 3;
159 wp = cd + 1;
160 pw = wp + 1;
161 if (sdhci_config & P852_SDHCI_ENABLE) {
162 if (sdhci_config & P852_SDHCI_CD_EN) {
163 snprintf(gpio_name[cd], count,
164 "sdhci%d_cd", i);
165 gpio_request(p852_sdhci_platform_data
166 [i].cd_gpio,
167 gpio_name[cd]);
168 tegra_gpio_enable
169 (p852_sdhci_platform_data[i].
170 cd_gpio);
171 }
172
173 if (sdhci_config & P852_SDHCI_WP_EN) {
174 snprintf(gpio_name[wp], count,
175 "sdhci%d_wp", i);
176 gpio_request(p852_sdhci_platform_data
177 [i].wp_gpio,
178 gpio_name[wp]);
179 tegra_gpio_enable
180 (p852_sdhci_platform_data[i].
181 wp_gpio);
182 }
183
184 if (sdhci_config & P852_SDHCI_PW_EN) {
185 snprintf(gpio_name[pw], count,
186 "sdhci%d_pw", i);
187 gpio_request(p852_sdhci_platform_data
188 [i].power_gpio,
189 gpio_name[pw]);
190 tegra_gpio_enable
191 (p852_sdhci_platform_data[i].
192 power_gpio);
193 }
194
195 platform_device_register(&tegra_sdhci_device
196 [i]);
197 }
198 }
199}
diff --git a/arch/arm/mach-tegra/p852/board-p852-sku1-b00.c b/arch/arm/mach-tegra/p852/board-p852-sku1-b00.c
new file mode 100644
index 00000000000..1cd89c5dfd7
--- /dev/null
+++ b/arch/arm/mach-tegra/p852/board-p852-sku1-b00.c
@@ -0,0 +1,98 @@
1/*
2 * arch/arm/mach-tegra/board-p852-sku1-b00.c
3 *
4 * Copyright (C) 2010-2011, NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include "board-p852.h"
18
19static inline void p852_sku1_b00_spi_init(void)
20{
21 p852_sku_peripherals |= P852_SKU_SPI_ENABLE;
22 p852_spi_peripherals |=
23 ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI1_SHIFT) |
24 ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI4_SHIFT);
25}
26
27static inline void p852_sku1_b00_i2s_init(void)
28{
29 p852_sku_peripherals |= P852_SKU_I2S_ENABLE;
30 p852_i2s_peripherals |= ((P852_I2S_ENABLE | P852_I2S_TDM)
31 << P852_I2S1_SHIFT) | ((P852_I2S_ENABLE | P852_I2S_TDM)
32 << P852_I2S2_SHIFT);
33}
34
35static inline void p852_sku1_b00_sdhci_init(void)
36{
37 p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE;
38 p852_sdhci_peripherals |=
39 ((P852_SDHCI_ENABLE)
40 << P852_SDHCI4_SHIFT) |
41 ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN)
42 << P852_SDHCI1_SHIFT) |
43 ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN)
44 << P852_SDHCI3_SHIFT);
45
46 p852_sdhci_platform_data[0].cd_gpio = TEGRA_GPIO_PV0;
47 p852_sdhci_platform_data[0].wp_gpio = TEGRA_GPIO_PV1;
48 p852_sdhci_platform_data[2].cd_gpio = TEGRA_GPIO_PD7;
49 p852_sdhci_platform_data[2].wp_gpio = TEGRA_GPIO_PT4;
50}
51
52static inline void p852_sku1_b00_uart_init(void)
53{
54 p852_sku_peripherals |= P852_SKU_UART_ENABLE;
55 p852_uart_peripherals |=
56 ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTD_SHIFT) |
57 ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT) |
58 ((P852_UART_ENABLE | P852_UART_HS | P852_UART_ALT_PIN_CFG)
59 << P852_UARTA_SHIFT);
60}
61
62static inline void p852_sku1_b00_display_init(void)
63{
64 p852_sku_peripherals |= P852_SKU_DISPLAY_ENABLE;
65 p852_display_peripherals |=
66 (P852_DISP_ENABLE << P852_DISPB_SHIFT);
67}
68
69static inline void p852_sku1_b00_ulpi_init(void)
70{
71 p852_sku_peripherals |= P852_SKU_ULPI_DISABLE;
72}
73
74static inline void p852_sku1_b00_i2c_init(void)
75{
76 p852_sku_peripherals |= P852_SKU_I2C_ENABLE;
77 p852_i2c_peripherals |=
78 ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) |
79 ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) |
80 ((P852_I2C_ENABLE) << P852_I2C3_SHIFT) |
81 ((P852_I2C_ENABLE) << P852_I2C4_SHIFT);
82}
83
84void __init p852_sku1_b00_init(void)
85{
86 p852_sku_peripherals |= P852_SKU_NOR_ENABLE;
87
88 p852_sku1_b00_spi_init();
89 p852_sku1_b00_i2s_init();
90 p852_sku1_b00_uart_init();
91 p852_sku1_b00_sdhci_init();
92 p852_sku1_b00_i2c_init();
93 p852_sku1_b00_display_init();
94 p852_sku1_b00_ulpi_init();
95
96 p852_common_init();
97}
98
diff --git a/arch/arm/mach-tegra/p852/board-p852-sku1-c0x.c b/arch/arm/mach-tegra/p852/board-p852-sku1-c0x.c
new file mode 100644
index 00000000000..4a783fb9b63
--- /dev/null
+++ b/arch/arm/mach-tegra/p852/board-p852-sku1-c0x.c
@@ -0,0 +1,98 @@
1/*
2 * arch/arm/mach-tegra/board-p852-sku1-c0x.c
3 *
4 * Copyright (C) 2010-2011, NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include "board-p852.h"
18
19static inline void p852_sku1_c0x_spi_init(void)
20{
21 p852_sku_peripherals |= P852_SKU_SPI_ENABLE;
22 p852_spi_peripherals |=
23 ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI1_SHIFT) |
24 ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI4_SHIFT);
25}
26
27static inline void p852_sku1_c0x_i2s_init(void)
28{
29 p852_sku_peripherals |= P852_SKU_I2S_ENABLE;
30 p852_i2s_peripherals |= ((P852_I2S_ENABLE | P852_I2S_TDM)
31 << P852_I2S1_SHIFT) | ((P852_I2S_ENABLE | P852_I2S_TDM)
32 << P852_I2S2_SHIFT);
33}
34
35static inline void p852_sku1_c0x_sdhci_init(void)
36{
37 p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE;
38 p852_sdhci_peripherals |=
39 ((P852_SDHCI_ENABLE)
40 << P852_SDHCI4_SHIFT) |
41 ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN)
42 << P852_SDHCI1_SHIFT) |
43 ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN)
44 << P852_SDHCI3_SHIFT);
45
46 p852_sdhci_platform_data[0].cd_gpio = TEGRA_GPIO_PV0;
47 p852_sdhci_platform_data[0].wp_gpio = TEGRA_GPIO_PV1;
48 p852_sdhci_platform_data[2].cd_gpio = TEGRA_GPIO_PD7;
49 p852_sdhci_platform_data[2].wp_gpio = TEGRA_GPIO_PT4;
50}
51
52static inline void p852_sku1_c0x_uart_init(void)
53{
54 p852_sku_peripherals |= P852_SKU_UART_ENABLE;
55 p852_uart_peripherals |=
56 ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTD_SHIFT) |
57 ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT) |
58 ((P852_UART_ENABLE | P852_UART_HS | P852_UART_ALT_PIN_CFG)
59 << P852_UARTA_SHIFT);
60}
61
62static inline void p852_sku1_c0x_display_init(void)
63{
64 p852_sku_peripherals |= P852_SKU_DISPLAY_ENABLE;
65 p852_display_peripherals |=
66 (P852_DISP_ENABLE << P852_DISPB_SHIFT);
67}
68
69static inline void p852_sku1_c0x_ulpi_init(void)
70{
71 p852_sku_peripherals |= P852_SKU_ULPI_DISABLE;
72}
73
74static inline void p852_sku1_c0x_i2c_init(void)
75{
76 p852_sku_peripherals |= P852_SKU_I2C_ENABLE;
77 p852_i2c_peripherals |=
78 ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) |
79 ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) |
80 ((P852_I2C_ENABLE) << P852_I2C3_SHIFT) |
81 ((P852_I2C_ENABLE) << P852_I2C4_SHIFT);
82}
83
84void __init p852_sku1_c0x_init(void)
85{
86 p852_sku_peripherals |= P852_SKU_NOR_ENABLE;
87
88 p852_sku1_c0x_spi_init();
89 p852_sku1_c0x_i2s_init();
90 p852_sku1_c0x_uart_init();
91 p852_sku1_c0x_sdhci_init();
92 p852_sku1_c0x_i2c_init();
93 p852_sku1_c0x_display_init();
94 p852_sku1_c0x_ulpi_init();
95
96 p852_common_init();
97}
98
diff --git a/arch/arm/mach-tegra/p852/board-p852-sku1.c b/arch/arm/mach-tegra/p852/board-p852-sku1.c
new file mode 100644
index 00000000000..387ba054bd8
--- /dev/null
+++ b/arch/arm/mach-tegra/p852/board-p852-sku1.c
@@ -0,0 +1,89 @@
1/*
2 * arch/arm/mach-tegra/board-p852-sku1.c
3 *
4 * Copyright (c) 2010-2011, NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include "board-p852.h"
18
19static inline void p852_sku1_spi_init(void)
20{
21 p852_sku_peripherals |= P852_SKU_SPI_ENABLE;
22 p852_spi_peripherals |=
23 ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI1_SHIFT) |
24 ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI4_SHIFT);
25}
26
27static inline void p852_sku1_i2s_init(void)
28{
29 p852_sku_peripherals |= P852_SKU_I2S_ENABLE;
30 p852_i2s_peripherals |= ((P852_I2S_ENABLE | P852_I2S_TDM)
31 << P852_I2S1_SHIFT) | ((P852_I2S_ENABLE | P852_I2S_TDM)
32 << P852_I2S2_SHIFT);
33}
34
35static inline void p852_sku1_sdhci_init(void)
36{
37 p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE;
38 p852_sdhci_peripherals |=
39 ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN)
40 << P852_SDHCI1_SHIFT) |
41 ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN)
42 << P852_SDHCI3_SHIFT) |
43 (P852_SDHCI_ENABLE << P852_SDHCI4_SHIFT);
44
45 p852_sdhci_platform_data[0].cd_gpio = TEGRA_GPIO_PV0;
46 p852_sdhci_platform_data[0].wp_gpio = TEGRA_GPIO_PV1;
47 p852_sdhci_platform_data[2].cd_gpio = TEGRA_GPIO_PD7;
48 p852_sdhci_platform_data[2].wp_gpio = TEGRA_GPIO_PT4;
49}
50
51static inline void p852_sku1_uart_init(void)
52{
53 p852_sku_peripherals |= P852_SKU_UART_ENABLE;
54 p852_uart_peripherals |=
55 ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTD_SHIFT) |
56 ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT);
57}
58
59static inline void p852_sku1_display_init(void)
60{
61 p852_sku_peripherals |= P852_SKU_DISPLAY_ENABLE;
62 p852_display_peripherals |=
63 (P852_DISP_ENABLE << P852_DISPB_SHIFT);
64}
65
66static inline void p852_sku1_i2c_init(void)
67{
68 p852_sku_peripherals |= P852_SKU_I2C_ENABLE;
69 p852_i2c_peripherals |=
70 ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) |
71 ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) |
72 ((P852_I2C_ENABLE) << P852_I2C3_SHIFT) |
73 ((P852_I2C_ENABLE) << P852_I2C4_SHIFT);
74}
75
76void __init p852_sku1_init(void)
77{
78 p852_sku_peripherals |= P852_SKU_NOR_ENABLE;
79
80 p852_sku1_spi_init();
81 p852_sku1_i2s_init();
82 p852_sku1_uart_init();
83 p852_sku1_sdhci_init();
84 p852_sku1_i2c_init();
85 p852_sku1_display_init();
86
87 p852_common_init();
88}
89
diff --git a/arch/arm/mach-tegra/p852/board-p852-sku13-b00.c b/arch/arm/mach-tegra/p852/board-p852-sku13-b00.c
new file mode 100644
index 00000000000..39e01f660ea
--- /dev/null
+++ b/arch/arm/mach-tegra/p852/board-p852-sku13-b00.c
@@ -0,0 +1,114 @@
1/*
2 * arch/arm/mach-tegra/board-p852-sku13-b00.c
3 *
4 * Copyright (c) 2010-2011, NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include "board-p852.h"
18
19static inline void p852_sku13_b00_spi_init(void)
20{
21 p852_sku_peripherals |= P852_SKU_SPI_ENABLE;
22 p852_spi_peripherals |=
23 ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI1_SHIFT) |
24 ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI2_SHIFT) |
25 ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI3_SHIFT) |
26 ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI4_SHIFT);
27}
28
29static inline void p852_sku13_b00_i2s_init(void)
30{
31 p852_sku_peripherals |= P852_SKU_I2S_ENABLE;
32 p852_i2s_peripherals |= (P852_I2S_ENABLE << P852_I2S1_SHIFT) |
33 (P852_I2S_ENABLE << P852_I2S2_SHIFT);
34}
35
36static inline void p852_sku13_b00_sdhci_init(void)
37{
38 p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE;
39 p852_sdhci_peripherals |=
40 (P852_SDHCI_ENABLE << P852_SDHCI1_SHIFT) |
41 (P852_SDHCI_ENABLE << P852_SDHCI2_SHIFT);
42
43 p852_sdhci_platform_data[1].is_8bit = true;
44}
45
46static inline void p852_sku13_b00_uart_init(void)
47{
48 p852_sku_peripherals |= P852_SKU_UART_ENABLE;
49 p852_uart_peripherals |=
50 ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTA_SHIFT) |
51 ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT) |
52 ((P852_UART_ENABLE) << P852_UARTC_SHIFT);
53}
54
55static inline void p852_sku13_b00_display_init(void)
56{
57 p852_sku_peripherals |= P852_SKU_DISPLAY_ENABLE;
58 p852_display_peripherals |=
59 (P852_DISP_ENABLE << P852_DISPA_SHIFT);
60}
61
62static inline void p852_sku13_b00_i2c_init(void)
63{
64 p852_sku_peripherals |= P852_SKU_I2C_ENABLE;
65 p852_i2c_peripherals |=
66 ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) |
67 ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) |
68 ((P852_I2C_ENABLE) << P852_I2C3_SHIFT) |
69 ((P852_I2C_ENABLE) << P852_I2C4_SHIFT);
70 p852_i2c_set_default_clock(0, 40000);
71}
72
73#ifdef CONFIG_TEGRA_SPI_I2S
74static struct tegra_spi_i2s_platform_data spi_i2s_data = {
75 .gpio_i2s = {
76 .gpio_no = TEGRA_GPIO_PT5,
77 .active_state = 1,
78 },
79 .gpio_spi = {
80 .gpio_no = TEGRA_GPIO_PV7,
81 .active_state = 1,
82 },
83 .spi_i2s_timeout_ms = 25,
84};
85
86static inline void p852_sku13_b00_spi_i2s_init(void)
87{
88 tegra_spi_i2s_device.platform_data = &spi_i2s_data;
89 /* cpld_gpio_dir1 */
90 tegra_pinmux_set_tristate(TEGRA_PINGROUP_PTA, TEGRA_TRI_NORMAL);
91 /* cpld_gpio_dir2 */
92 tegra_pinmux_set_tristate(TEGRA_PINGROUP_LVP0, TEGRA_TRI_NORMAL);
93 p852_spi_i2s_init();
94}
95#endif
96
97void __init p852_sku13_b00_init(void)
98{
99 p852_sku_peripherals |= P852_SKU_NAND_ENABLE;
100
101
102 p852_sku13_b00_spi_init();
103 p852_sku13_b00_i2s_init();
104 p852_sku13_b00_uart_init();
105 p852_sku13_b00_sdhci_init();
106 p852_sku13_b00_i2c_init();
107 p852_sku13_b00_display_init();
108
109 p852_common_init();
110
111#ifdef CONFIG_TEGRA_SPI_I2S
112 p852_sku13_b00_spi_i2s_init();
113#endif
114}
diff --git a/arch/arm/mach-tegra/p852/board-p852-sku13.c b/arch/arm/mach-tegra/p852/board-p852-sku13.c
new file mode 100644
index 00000000000..92d917e6e2c
--- /dev/null
+++ b/arch/arm/mach-tegra/p852/board-p852-sku13.c
@@ -0,0 +1,112 @@
1/*
2 * arch/arm/mach-tegra/board-p852-sku13.c
3 *
4 * Copyright (c) 2010-2011, NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include "board-p852.h"
18
19static inline void p852_sku13_spi_init(void)
20{
21 p852_sku_peripherals |= P852_SKU_SPI_ENABLE;
22 p852_spi_peripherals |=
23 ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI1_SHIFT) |
24 ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI2_SHIFT) |
25 ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI3_SHIFT) |
26 ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI4_SHIFT);
27
28}
29
30static inline void p852_sku13_i2s_init(void)
31{
32 p852_sku_peripherals |= P852_SKU_I2S_ENABLE;
33 p852_i2s_peripherals |= (P852_I2S_ENABLE << P852_I2S1_SHIFT) |
34 (P852_I2S_ENABLE << P852_I2S2_SHIFT);
35}
36
37static inline void p852_sku13_sdhci_init(void)
38{
39 p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE;
40 p852_sdhci_peripherals |=
41 (P852_SDHCI_ENABLE << P852_SDHCI1_SHIFT) |
42 (P852_SDHCI_ENABLE << P852_SDHCI2_SHIFT);
43
44 p852_sdhci_platform_data[1].is_8bit = true;
45}
46
47static inline void p852_sku13_uart_init(void)
48{
49 p852_sku_peripherals |= P852_SKU_UART_ENABLE;
50 p852_uart_peripherals |=
51 ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTA_SHIFT) |
52 ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT) |
53 ((P852_UART_ENABLE) << P852_UARTC_SHIFT);
54}
55
56static inline void p852_sku13_display_init(void)
57{
58 p852_sku_peripherals |= P852_SKU_DISPLAY_ENABLE;
59 p852_display_peripherals |=
60 (P852_DISP_ENABLE << P852_DISPA_SHIFT);
61}
62
63static inline void p852_sku13_i2c_init(void)
64{
65 p852_sku_peripherals |= P852_SKU_I2C_ENABLE;
66 p852_i2c_peripherals |=
67 ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) |
68 ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) |
69 ((P852_I2C_ENABLE) << P852_I2C3_SHIFT) |
70 ((P852_I2C_ENABLE) << P852_I2C4_SHIFT);
71 p852_i2c_set_default_clock(0, 40000);
72}
73
74#ifdef CONFIG_TEGRA_SPI_I2S
75static struct tegra_spi_i2s_platform_data spi_i2s_data = {
76 .gpio_i2s = {
77 .gpio_no = TEGRA_GPIO_PS3,
78 .active_state = 0,
79 },
80 .gpio_spi = {
81 .gpio_no = TEGRA_GPIO_PS4,
82 .active_state = 0,
83 },
84 .spi_i2s_timeout_ms = 25,
85};
86
87static inline void p852_sku13_spi_i2s_init(void)
88{
89 tegra_spi_i2s_device.platform_data = &spi_i2s_data;
90 /* cpld_gpio_dir1 and cpld_gpio_dir2*/
91 tegra_pinmux_set_tristate(TEGRA_PINGROUP_KBCB, TEGRA_TRI_NORMAL);
92 p852_spi_i2s_init();
93}
94#endif
95
96void __init p852_sku13_init(void)
97{
98 p852_sku_peripherals |= P852_SKU_NAND_ENABLE;
99
100 p852_sku13_spi_init();
101 p852_sku13_i2s_init();
102 p852_sku13_uart_init();
103 p852_sku13_sdhci_init();
104 p852_sku13_i2c_init();
105 p852_sku13_display_init();
106
107 p852_common_init();
108
109#ifdef CONFIG_TEGRA_SPI_I2S
110 p852_sku13_spi_i2s_init();
111#endif
112}
diff --git a/arch/arm/mach-tegra/p852/board-p852-sku23-b00.c b/arch/arm/mach-tegra/p852/board-p852-sku23-b00.c
new file mode 100644
index 00000000000..6f464ec3620
--- /dev/null
+++ b/arch/arm/mach-tegra/p852/board-p852-sku23-b00.c
@@ -0,0 +1,115 @@
1/*
2 * arch/arm/mach-tegra/board-p852-sku23-b00.c
3 *
4 * Copyright (c) 2010-2011, NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include "board-p852.h"
18
19static inline void p852_sku23_b00_spi_init(void)
20{
21 p852_sku_peripherals |= P852_SKU_SPI_ENABLE;
22 p852_spi_peripherals |=
23 ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI1_SHIFT) |
24 ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI2_SHIFT) |
25 ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI3_SHIFT) |
26 ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI4_SHIFT);
27}
28
29static inline void p852_sku23_b00_i2s_init(void)
30{
31 p852_sku_peripherals |= P852_SKU_I2S_ENABLE;
32 p852_i2s_peripherals |=
33 ((P852_I2S_TDM | P852_I2S_ENABLE) << P852_I2S1_SHIFT) |
34 ((P852_I2S_TDM | P852_I2S_ENABLE) << P852_I2S2_SHIFT);
35}
36
37static inline void p852_sku23_b00_sdhci_init(void)
38{
39 p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE;
40 p852_sdhci_peripherals |= (P852_SDHCI_ENABLE << P852_SDHCI1_SHIFT) |
41 (P852_SDHCI_ENABLE << P852_SDHCI2_SHIFT) |
42 ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN) << P852_SDHCI3_SHIFT);
43
44 p852_sdhci_platform_data[1].is_8bit = true;
45 p852_sdhci_platform_data[2].cd_gpio = TEGRA_GPIO_PD7;
46}
47
48static inline void p852_sku23_b00_uart_init(void)
49{
50 p852_sku_peripherals |= P852_SKU_UART_ENABLE;
51 p852_uart_peripherals |=
52 ((P852_UART_ENABLE) << P852_UARTA_SHIFT) |
53 ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT) |
54 ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTC_SHIFT);
55}
56
57static inline void p852_sku23_b00_display_init(void)
58{
59 p852_sku_peripherals |= P852_SKU_DISPLAY_ENABLE;
60 p852_display_peripherals |=
61 (P852_DISP_ENABLE << P852_DISPA_SHIFT);
62}
63
64static inline void p852_sku23_b00_i2c_init(void)
65{
66 p852_sku_peripherals |= P852_SKU_I2C_ENABLE;
67 p852_i2c_peripherals |=
68 ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) |
69 ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) |
70 ((P852_I2C_ENABLE) << P852_I2C3_SHIFT) |
71 ((P852_I2C_ENABLE) << P852_I2C4_SHIFT);
72}
73
74#ifdef CONFIG_TEGRA_SPI_I2S
75static struct tegra_spi_i2s_platform_data spi_i2s_data = {
76 .gpio_i2s = {
77 .gpio_no = TEGRA_GPIO_PT5,
78 .active_state = 1,
79 },
80 .gpio_spi = {
81 .gpio_no = TEGRA_GPIO_PV7,
82 .active_state = 1,
83 },
84 .spi_i2s_timeout_ms = 25,
85};
86
87static inline void p852_sku23_b00_spi_i2s_init(void)
88{
89 tegra_spi_i2s_device.platform_data = &spi_i2s_data;
90 /* cpld_gpio_dir1 */
91 tegra_pinmux_set_tristate(TEGRA_PINGROUP_PTA, TEGRA_TRI_NORMAL);
92 /* cpld_gpio_dir2 */
93 tegra_pinmux_set_tristate(TEGRA_PINGROUP_LVP0, TEGRA_TRI_NORMAL);
94 p852_spi_i2s_init();
95}
96#endif
97
98void __init p852_sku23_b00_init(void)
99{
100 p852_sku_peripherals |= P852_SKU_NAND_ENABLE;
101
102 p852_sku23_b00_spi_init();
103 p852_sku23_b00_i2s_init();
104 p852_sku23_b00_uart_init();
105 p852_sku23_b00_sdhci_init();
106 p852_sku23_b00_i2c_init();
107 p852_sku23_b00_display_init();
108
109 p852_common_init();
110
111#ifdef CONFIG_TEGRA_SPI_I2S
112 p852_sku23_b00_spi_i2s_init();
113#endif
114}
115
diff --git a/arch/arm/mach-tegra/p852/board-p852-sku23-c01.c b/arch/arm/mach-tegra/p852/board-p852-sku23-c01.c
new file mode 100644
index 00000000000..f946e0ed35e
--- /dev/null
+++ b/arch/arm/mach-tegra/p852/board-p852-sku23-c01.c
@@ -0,0 +1,87 @@
1/*
2 * arch/arm/mach-tegra/board-p852-sku23-c01.c
3 *
4 * Copyright (c) 2010-2011, NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include "board-p852.h"
18
19static inline void p852_sku23_c01_spi_init(void)
20{
21 p852_sku_peripherals |= P852_SKU_SPI_ENABLE;
22 p852_spi_peripherals |=
23 ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI1_SHIFT) |
24 ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI2_SHIFT) |
25 ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI3_SHIFT) |
26 ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI4_SHIFT);
27}
28
29static inline void p852_sku23_c01_i2s_init(void)
30{
31 p852_sku_peripherals |= P852_SKU_I2S_ENABLE;
32 p852_i2s_peripherals |=
33 ((P852_I2S_TDM | P852_I2S_ENABLE) << P852_I2S1_SHIFT) |
34 ((P852_I2S_TDM | P852_I2S_ENABLE) << P852_I2S2_SHIFT);
35}
36
37static inline void p852_sku23_c01_sdhci_init(void)
38{
39 p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE;
40 p852_sdhci_peripherals |= (P852_SDHCI_ENABLE << P852_SDHCI1_SHIFT) |
41 (P852_SDHCI_ENABLE << P852_SDHCI2_SHIFT) |
42 ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN) << P852_SDHCI3_SHIFT);
43
44 p852_sdhci_platform_data[1].is_8bit = true;
45 p852_sdhci_platform_data[2].cd_gpio = TEGRA_GPIO_PD7;
46}
47
48static inline void p852_sku23_c01_uart_init(void)
49{
50 p852_sku_peripherals |= P852_SKU_UART_ENABLE;
51 p852_uart_peripherals |=
52 ((P852_UART_ENABLE) << P852_UARTA_SHIFT) |
53 ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT) |
54 ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTC_SHIFT);
55}
56
57static inline void p852_sku23_c01_display_init(void)
58{
59 p852_sku_peripherals |= P852_SKU_DISPLAY_ENABLE;
60 p852_display_peripherals |=
61 (P852_DISP_ENABLE << P852_DISPA_SHIFT);
62}
63
64static inline void p852_sku23_c01_i2c_init(void)
65{
66 p852_sku_peripherals |= P852_SKU_I2C_ENABLE;
67 p852_i2c_peripherals |=
68 ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) |
69 ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) |
70 ((P852_I2C_ENABLE) << P852_I2C3_SHIFT) |
71 ((P852_I2C_ENABLE) << P852_I2C4_SHIFT);
72}
73
74void __init p852_sku23_c01_init(void)
75{
76 p852_sku_peripherals |= P852_SKU_NAND_ENABLE;
77
78 p852_sku23_c01_spi_init();
79 p852_sku23_c01_i2s_init();
80 p852_sku23_c01_uart_init();
81 p852_sku23_c01_sdhci_init();
82 p852_sku23_c01_i2c_init();
83 p852_sku23_c01_display_init();
84
85 p852_common_init();
86}
87
diff --git a/arch/arm/mach-tegra/p852/board-p852-sku23.c b/arch/arm/mach-tegra/p852/board-p852-sku23.c
new file mode 100644
index 00000000000..a2bc9b4ca0b
--- /dev/null
+++ b/arch/arm/mach-tegra/p852/board-p852-sku23.c
@@ -0,0 +1,113 @@
1/*
2 * arch/arm/mach-tegra/board-p852-sku23.c
3 *
4 * Copyright (c) 2010-2011, NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include "board-p852.h"
18
19static inline void __init p852_sku23_spi_init(void)
20{
21 p852_sku_peripherals |= P852_SKU_SPI_ENABLE;
22 p852_spi_peripherals |=
23 ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI1_SHIFT) |
24 ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI2_SHIFT) |
25 ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI3_SHIFT) |
26 ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI4_SHIFT);
27}
28
29static inline void p852_sku23_sdhci_init(void)
30{
31 p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE;
32 p852_sdhci_peripherals |= (P852_SDHCI_ENABLE << P852_SDHCI1_SHIFT) |
33 (P852_SDHCI_ENABLE << P852_SDHCI2_SHIFT) |
34 ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN) << P852_SDHCI3_SHIFT);
35
36 p852_sdhci_platform_data[1].is_8bit = true;
37 p852_sdhci_platform_data[2].cd_gpio = TEGRA_GPIO_PD7;
38}
39
40static inline void p852_sku23_i2s_init(void)
41{
42 p852_sku_peripherals |= P852_SKU_I2S_ENABLE;
43 p852_i2s_peripherals |=
44 ((P852_I2S_TDM | P852_I2S_ENABLE) << P852_I2S1_SHIFT) |
45 ((P852_I2S_TDM | P852_I2S_ENABLE) << P852_I2S2_SHIFT);
46}
47
48static inline void p852_sku23_uart_init(void)
49{
50 p852_sku_peripherals |= P852_SKU_UART_ENABLE;
51 p852_uart_peripherals |=
52 ((P852_UART_ENABLE) << P852_UARTA_SHIFT) |
53 ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT) |
54 ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTC_SHIFT);
55}
56
57static inline void p852_sku23_display_init(void)
58{
59 p852_sku_peripherals |= P852_SKU_DISPLAY_ENABLE;
60 p852_display_peripherals |=
61 (P852_DISP_ENABLE << P852_DISPA_SHIFT);
62}
63
64static inline void p852_sku23_i2c_init(void)
65{
66 p852_sku_peripherals |= P852_SKU_I2C_ENABLE;
67 p852_i2c_peripherals |=
68 ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) |
69 ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) |
70 ((P852_I2C_ENABLE) << P852_I2C3_SHIFT) |
71 ((P852_I2C_ENABLE) << P852_I2C4_SHIFT);
72}
73
74#ifdef CONFIG_TEGRA_SPI_I2S
75static struct tegra_spi_i2s_platform_data spi_i2s_data = {
76 .gpio_i2s = {
77 .gpio_no = TEGRA_GPIO_PS3,
78 .active_state = 0,
79 },
80 .gpio_spi = {
81 .gpio_no = TEGRA_GPIO_PS4,
82 .active_state = 0,
83 },
84 .spi_i2s_timeout_ms = 25,
85};
86
87static inline void p852_sku23_spi_i2s_init(void)
88{
89 tegra_spi_i2s_device.platform_data = &spi_i2s_data;
90 /* cpld_gpio_dir1 and cpld_gpio_dir2*/
91 tegra_pinmux_set_tristate(TEGRA_PINGROUP_KBCB, TEGRA_TRI_NORMAL);
92 p852_spi_i2s_init();
93}
94#endif
95
96void __init p852_sku23_init(void)
97{
98 p852_sku_peripherals |= P852_SKU_NAND_ENABLE;
99
100 p852_sku23_spi_init();
101 p852_sku23_i2s_init();
102 p852_sku23_uart_init();
103 p852_sku23_sdhci_init();
104 p852_sku23_i2c_init();
105 p852_sku23_display_init();
106
107 p852_common_init();
108
109#ifdef CONFIG_TEGRA_SPI_I2S
110 p852_sku23_spi_i2s_init();
111#endif
112}
113
diff --git a/arch/arm/mach-tegra/p852/board-p852-sku3.c b/arch/arm/mach-tegra/p852/board-p852-sku3.c
new file mode 100644
index 00000000000..380df9a7439
--- /dev/null
+++ b/arch/arm/mach-tegra/p852/board-p852-sku3.c
@@ -0,0 +1,103 @@
1/*
2 * arch/arm/mach-tegra/board-p852-sku3.c
3 *
4 * Copyright (c) 2010-2011, NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include "board-p852.h"
18
19static inline void p852_sku3_spi_init(void)
20{
21 p852_sku_peripherals |= P852_SKU_SPI_ENABLE;
22 p852_spi_peripherals |=
23 ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI1_SHIFT) |
24 ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI2_SHIFT) |
25 ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI3_SHIFT) |
26 ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI4_SHIFT);
27}
28
29static inline void p852_sku3_i2s_init(void)
30{
31 p852_sku_peripherals |= P852_SKU_I2S_ENABLE;
32 p852_i2s_peripherals |= (P852_I2S_ENABLE << P852_I2S1_SHIFT) |
33 (P852_I2S_ENABLE << P852_I2S2_SHIFT);
34}
35
36static inline void p852_sku3_sdhci_init(void)
37{
38 p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE;
39 p852_sdhci_peripherals |=
40 (P852_SDHCI_ENABLE << P852_SDHCI1_SHIFT) |
41 (P852_SDHCI_ENABLE << P852_SDHCI2_SHIFT);
42
43 p852_sdhci_platform_data[1].is_8bit = true;
44}
45
46static inline void p852_sku3_uart_init(void)
47{
48 p852_sku_peripherals |= P852_SKU_UART_ENABLE;
49 p852_uart_peripherals |=
50 ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTA_SHIFT) |
51 ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT) |
52 ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTC_SHIFT);
53}
54
55static inline void p852_sku3_i2c_init(void)
56{
57 p852_sku_peripherals |= P852_SKU_I2C_ENABLE;
58 p852_i2c_peripherals |=
59 ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) |
60 ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) |
61 ((P852_I2C_ENABLE) << P852_I2C3_SHIFT) |
62 ((P852_I2C_ENABLE) << P852_I2C4_SHIFT);
63 p852_i2c_set_default_clock(0, 40000);
64}
65
66#ifdef CONFIG_TEGRA_SPI_I2S
67static struct tegra_spi_i2s_platform_data spi_i2s_data = {
68 .gpio_i2s = {
69 .gpio_no = TEGRA_GPIO_PS3,
70 .active_state = 0,
71 },
72 .gpio_spi = {
73 .gpio_no = TEGRA_GPIO_PS4,
74 .active_state = 0,
75 },
76 .spi_i2s_timeout_ms = 25,
77};
78
79static inline void p852_sku3_spi_i2s_init(void)
80{
81 tegra_spi_i2s_device.platform_data = &spi_i2s_data;
82 /* cpld_gpio_dir1 and cpld_gpio_dir2*/
83 tegra_pinmux_set_tristate(TEGRA_PINGROUP_KBCB, TEGRA_TRI_NORMAL);
84 p852_spi_i2s_init();
85}
86#endif
87
88void __init p852_sku3_init(void)
89{
90 p852_sku_peripherals |= P852_SKU_NAND_ENABLE;
91
92 p852_sku3_spi_init();
93 p852_sku3_i2s_init();
94 p852_sku3_uart_init();
95 p852_sku3_sdhci_init();
96 p852_sku3_i2c_init();
97
98 p852_common_init();
99
100#ifdef CONFIG_TEGRA_SPI_I2S
101 p852_sku3_spi_i2s_init();
102#endif
103}
diff --git a/arch/arm/mach-tegra/p852/board-p852-sku5-b00.c b/arch/arm/mach-tegra/p852/board-p852-sku5-b00.c
new file mode 100644
index 00000000000..59f6f13f772
--- /dev/null
+++ b/arch/arm/mach-tegra/p852/board-p852-sku5-b00.c
@@ -0,0 +1,115 @@
1/*
2 * arch/arm/mach-tegra/board-p852-sku5_b00.c
3 *
4 * Copyright (c) 2010-2011, NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include "board-p852.h"
18
19static inline void p852_sku5_b00_spi_init(void)
20{
21 p852_sku_peripherals |= P852_SKU_SPI_ENABLE;
22 p852_spi_peripherals |=
23 ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI1_SHIFT) |
24 ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI2_SHIFT) |
25 ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI3_SHIFT) |
26 ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI4_SHIFT);
27}
28
29static inline void p852_sku5_b00_i2s_init(void)
30{
31 p852_sku_peripherals |= P852_SKU_I2S_ENABLE;
32 p852_i2s_peripherals |=
33 ((P852_I2S_TDM | P852_I2S_ENABLE) << P852_I2S1_SHIFT) |
34 ((P852_I2S_TDM | P852_I2S_ENABLE) << P852_I2S2_SHIFT);
35}
36
37static inline void p852_sku5_b00_sdhci_init(void)
38{
39 p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE;
40
41 p852_sdhci_peripherals |=
42 ((P852_SDHCI_ENABLE << P852_SDHCI1_SHIFT) |
43 (P852_SDHCI_ENABLE << P852_SDHCI2_SHIFT));
44
45 p852_sdhci_platform_data[1].is_8bit = true;
46}
47
48static inline void p852_sku5_b00_uart_init(void)
49{
50 p852_sku_peripherals |= P852_SKU_UART_ENABLE;
51 p852_uart_peripherals |=
52 ((P852_UART_ENABLE) << P852_UARTA_SHIFT) |
53 ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT) |
54 ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTC_SHIFT);
55}
56
57static inline void p852_sku5_b00_display_init(void)
58{
59 p852_sku_peripherals |= P852_SKU_DISPLAY_ENABLE;
60 p852_display_peripherals |=
61 (P852_DISP_ENABLE << P852_DISPA_SHIFT);
62}
63
64static inline void p852_sku5_b00_i2c_init(void)
65{
66 p852_sku_peripherals |= P852_SKU_I2C_ENABLE;
67 p852_i2c_peripherals |=
68 ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) |
69 ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) |
70 ((P852_I2C_ENABLE) << P852_I2C3_SHIFT) |
71 ((P852_I2C_ENABLE) << P852_I2C4_SHIFT);
72}
73
74#ifdef CONFIG_TEGRA_SPI_I2S
75static struct tegra_spi_i2s_platform_data spi_i2s_data = {
76 .gpio_i2s = {
77 .gpio_no = TEGRA_GPIO_PT5,
78 .active_state = 1,
79 },
80 .gpio_spi = {
81 .gpio_no = TEGRA_GPIO_PV7,
82 .active_state = 1,
83 },
84 .spi_i2s_timeout_ms = 25,
85};
86
87static inline void p852_sku5_b00_spi_i2s_init(void)
88{
89 tegra_spi_i2s_device.platform_data = &spi_i2s_data;
90 /* cpld_gpio_dir1 */
91 tegra_pinmux_set_tristate(TEGRA_PINGROUP_PTA, TEGRA_TRI_NORMAL);
92 /* cpld_gpio_dir2 */
93 tegra_pinmux_set_tristate(TEGRA_PINGROUP_LVP0, TEGRA_TRI_NORMAL);
94 p852_spi_i2s_init();
95}
96#endif
97
98void __init p852_sku5_b00_init(void)
99{
100 p852_sku_peripherals |= P852_SKU_NAND_ENABLE;
101
102 p852_sku5_b00_spi_init();
103 p852_sku5_b00_i2s_init();
104 p852_sku5_b00_uart_init();
105 p852_sku5_b00_sdhci_init();
106 p852_sku5_b00_i2c_init();
107 p852_sku5_b00_display_init();
108
109 p852_common_init();
110
111#ifdef CONFIG_TEGRA_SPI_I2S
112 p852_sku5_b00_spi_i2s_init();
113#endif
114}
115
diff --git a/arch/arm/mach-tegra/p852/board-p852-sku5-c01.c b/arch/arm/mach-tegra/p852/board-p852-sku5-c01.c
new file mode 100644
index 00000000000..f9c8e72911b
--- /dev/null
+++ b/arch/arm/mach-tegra/p852/board-p852-sku5-c01.c
@@ -0,0 +1,93 @@
1/*
2 * arch/arm/mach-tegra/board-p852-sku5-c01.c
3 *
4 * Copyright (c) 2010-2011, NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include "board-p852.h"
18
19static inline void p852_sku5_c01_spi_init(void)
20{
21 p852_sku_peripherals |= P852_SKU_SPI_ENABLE;
22 p852_spi_peripherals |=
23 ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI1_SHIFT) |
24 ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI2_SHIFT) |
25 ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI3_SHIFT) |
26 ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI4_SHIFT);
27}
28
29static inline void p852_sku5_c01_i2s_init(void)
30{
31 p852_sku_peripherals |= P852_SKU_I2S_ENABLE;
32 p852_i2s_peripherals |=
33 ((P852_I2S_TDM | P852_I2S_ENABLE) << P852_I2S1_SHIFT) |
34 ((P852_I2S_TDM | P852_I2S_ENABLE) << P852_I2S2_SHIFT);
35}
36
37static inline void p852_sku5_c01_sdhci_init(void)
38{
39 p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE;
40 p852_sdhci_peripherals |=
41 ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN)
42 << P852_SDHCI1_SHIFT);
43
44 p852_sdhci_platform_data[0].cd_gpio = TEGRA_GPIO_PV0;
45 p852_sdhci_platform_data[0].wp_gpio = TEGRA_GPIO_PV1;
46}
47
48static inline void p852_sku5_c01_uart_init(void)
49{
50 p852_sku_peripherals |= P852_SKU_UART_ENABLE;
51 p852_uart_peripherals |=
52 ((P852_UART_ENABLE) << P852_UARTA_SHIFT) |
53 ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT) |
54 ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTC_SHIFT);
55}
56
57static inline void p852_sku5_c01_display_init(void)
58{
59 p852_sku_peripherals |= P852_SKU_DISPLAY_ENABLE;
60 p852_display_peripherals |=
61 (P852_DISP_ENABLE << P852_DISPA_SHIFT);
62}
63
64static inline void p852_sku5_c01_i2c_init(void)
65{
66 p852_sku_peripherals |= P852_SKU_I2C_ENABLE;
67 p852_i2c_peripherals |=
68 ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) |
69 ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) |
70 ((P852_I2C_ENABLE) << P852_I2C3_SHIFT) |
71 ((P852_I2C_ENABLE) << P852_I2C4_SHIFT);
72}
73
74static inline void p852_sku5_c01_ulpi_init(void)
75{
76 p852_sku_peripherals |= P852_SKU_ULPI_DISABLE;
77}
78
79void __init p852_sku5_c01_init(void)
80{
81 p852_sku_peripherals |= P852_SKU_NAND_ENABLE;
82
83 p852_sku5_c01_spi_init();
84 p852_sku5_c01_i2s_init();
85 p852_sku5_c01_uart_init();
86 p852_sku5_c01_sdhci_init();
87 p852_sku5_c01_i2c_init();
88 p852_sku5_c01_display_init();
89 p852_sku5_c01_ulpi_init();
90
91 p852_common_init();
92}
93
diff --git a/arch/arm/mach-tegra/p852/board-p852-sku8-b00.c b/arch/arm/mach-tegra/p852/board-p852-sku8-b00.c
new file mode 100644
index 00000000000..4cc4d53d980
--- /dev/null
+++ b/arch/arm/mach-tegra/p852/board-p852-sku8-b00.c
@@ -0,0 +1,88 @@
1/*
2 * arch/arm/mach-tegra/board-p852-sku8-b00.c
3 *
4 * Copyright (C) 2010-2011, NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include "board-p852.h"
18
19static inline void p852_sku8_b00_spi_init(void)
20{
21 p852_sku_peripherals |= P852_SKU_SPI_ENABLE;
22 p852_spi_peripherals |=
23 ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI1_SHIFT) |
24 ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI4_SHIFT);
25}
26
27static inline void p852_sku8_b00_i2s_init(void)
28{
29 p852_sku_peripherals |= P852_SKU_I2S_ENABLE;
30 p852_i2s_peripherals |= ((P852_I2S_ENABLE | P852_I2S_TDM)
31 << P852_I2S1_SHIFT) | ((P852_I2S_ENABLE | P852_I2S_TDM)
32 << P852_I2S2_SHIFT);
33}
34
35static inline void p852_sku8_b00_sdhci_init(void)
36{
37 p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE;
38 p852_sdhci_peripherals |=
39 ((P852_SDHCI_ENABLE)
40 << P852_SDHCI4_SHIFT) |
41 ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN)
42 << P852_SDHCI1_SHIFT) |
43 ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN)
44 << P852_SDHCI3_SHIFT);
45
46 p852_sdhci_platform_data[0].cd_gpio = TEGRA_GPIO_PV0;
47 p852_sdhci_platform_data[0].wp_gpio = TEGRA_GPIO_PV1;
48 p852_sdhci_platform_data[2].cd_gpio = TEGRA_GPIO_PD7;
49 p852_sdhci_platform_data[2].wp_gpio = TEGRA_GPIO_PT4;
50}
51
52static inline void p852_sku8_b00_uart_init(void)
53{
54 p852_sku_peripherals |= P852_SKU_UART_ENABLE;
55 p852_uart_peripherals |=
56 ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTD_SHIFT) |
57 ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT);
58}
59
60static inline void p852_sku8_b00_display_init(void)
61{
62 p852_sku_peripherals |= P852_SKU_DISPLAY_ENABLE;
63}
64
65static inline void p852_sku8_b00_i2c_init(void)
66{
67 p852_sku_peripherals |= P852_SKU_I2C_ENABLE;
68 p852_i2c_peripherals |=
69 ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) |
70 ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) |
71 ((P852_I2C_ENABLE) << P852_I2C4_SHIFT);
72}
73
74
75void __init p852_sku8_b00_init(void)
76{
77 p852_sku_peripherals |= P852_SKU_NOR_ENABLE;
78
79 p852_sku8_b00_spi_init();
80 p852_sku8_b00_i2s_init();
81 p852_sku8_b00_uart_init();
82 p852_sku8_b00_sdhci_init();
83 p852_sku8_b00_display_init();
84 p852_sku8_b00_i2c_init();
85
86 p852_common_init();
87}
88
diff --git a/arch/arm/mach-tegra/p852/board-p852-sku8-c01.c b/arch/arm/mach-tegra/p852/board-p852-sku8-c01.c
new file mode 100644
index 00000000000..71210cd12b9
--- /dev/null
+++ b/arch/arm/mach-tegra/p852/board-p852-sku8-c01.c
@@ -0,0 +1,87 @@
1/*
2 * arch/arm/mach-tegra/board-p852-sku8-c00.c
3 *
4 * Copyright (C) 2010-2011, NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include "board-p852.h"
18
19static inline void p852_sku8_c00_spi_init(void)
20{
21 p852_sku_peripherals |= P852_SKU_SPI_ENABLE;
22 p852_spi_peripherals |=
23 ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI1_SHIFT) |
24 ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI4_SHIFT);
25}
26
27static inline void p852_sku8_c00_i2s_init(void)
28{
29 p852_sku_peripherals |= P852_SKU_I2S_ENABLE;
30 p852_i2s_peripherals |= ((P852_I2S_ENABLE | P852_I2S_TDM)
31 << P852_I2S1_SHIFT) | ((P852_I2S_ENABLE | P852_I2S_TDM)
32 << P852_I2S2_SHIFT);
33}
34
35static inline void p852_sku8_c00_sdhci_init(void)
36{
37 p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE;
38 p852_sdhci_peripherals |=
39 ((P852_SDHCI_ENABLE)
40 << P852_SDHCI4_SHIFT) |
41 ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN)
42 << P852_SDHCI1_SHIFT) |
43 ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN)
44 << P852_SDHCI3_SHIFT);
45
46 p852_sdhci_platform_data[0].cd_gpio = TEGRA_GPIO_PV0;
47 p852_sdhci_platform_data[0].wp_gpio = TEGRA_GPIO_PV1;
48 p852_sdhci_platform_data[2].cd_gpio = TEGRA_GPIO_PD7;
49 p852_sdhci_platform_data[2].wp_gpio = TEGRA_GPIO_PT4;
50}
51
52static inline void p852_sku8_c00_uart_init(void)
53{
54 p852_sku_peripherals |= P852_SKU_UART_ENABLE;
55 p852_uart_peripherals |=
56 ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTD_SHIFT) |
57 ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT);
58}
59
60static inline void p852_sku8_c00_display_init(void)
61{
62 p852_sku_peripherals |= P852_SKU_DISPLAY_ENABLE;
63}
64
65static inline void p852_sku8_c00_i2c_init(void)
66{
67 p852_sku_peripherals |= P852_SKU_I2C_ENABLE;
68 p852_i2c_peripherals |=
69 ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) |
70 ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) |
71 ((P852_I2C_ENABLE) << P852_I2C4_SHIFT);
72}
73
74
75void __init p852_sku8_c00_init(void)
76{
77 p852_sku_peripherals |= P852_SKU_NOR_ENABLE;
78
79 p852_sku8_c00_spi_init();
80 p852_sku8_c00_i2s_init();
81 p852_sku8_c00_uart_init();
82 p852_sku8_c00_sdhci_init();
83 p852_sku8_c00_display_init();
84 p852_sku8_c00_i2c_init();
85
86 p852_common_init();
87}
diff --git a/arch/arm/mach-tegra/p852/board-p852-sku9-b00.c b/arch/arm/mach-tegra/p852/board-p852-sku9-b00.c
new file mode 100644
index 00000000000..7c3d9c3d9a3
--- /dev/null
+++ b/arch/arm/mach-tegra/p852/board-p852-sku9-b00.c
@@ -0,0 +1,93 @@
1/*
2 * arch/arm/mach-tegra/board-p852-sku9-b00.c
3 *
4 * Copyright (C) 2010-2011, NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include "board-p852.h"
18
19static inline void p852_sku9_b00_spi_init(void)
20{
21 p852_sku_peripherals |= P852_SKU_SPI_ENABLE;
22 p852_spi_peripherals |=
23 ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI1_SHIFT) |
24 ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI4_SHIFT);
25}
26
27static inline void p852_sku9_b00_i2s_init(void)
28{
29 p852_sku_peripherals |= P852_SKU_I2S_ENABLE;
30 p852_i2s_peripherals |= ((P852_I2S_ENABLE | P852_I2S_TDM)
31 << P852_I2S1_SHIFT) | ((P852_I2S_ENABLE | P852_I2S_TDM)
32 << P852_I2S2_SHIFT);
33}
34
35static inline void p852_sku9_b00_sdhci_init(void)
36{
37 p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE;
38 p852_sdhci_peripherals |=
39 ((P852_SDHCI_ENABLE)
40 << P852_SDHCI4_SHIFT) |
41 ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN)
42 << P852_SDHCI1_SHIFT) |
43 ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN)
44 << P852_SDHCI3_SHIFT);
45
46 p852_sdhci_platform_data[0].cd_gpio = TEGRA_GPIO_PV0;
47 p852_sdhci_platform_data[0].wp_gpio = TEGRA_GPIO_PV1;
48 p852_sdhci_platform_data[2].cd_gpio = TEGRA_GPIO_PD7;
49 p852_sdhci_platform_data[2].wp_gpio = TEGRA_GPIO_PT4;
50}
51
52static inline void p852_sku9_b00_uart_init(void)
53{
54 p852_sku_peripherals |= P852_SKU_UART_ENABLE;
55 p852_uart_peripherals |=
56 ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTD_SHIFT) |
57 ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT);
58}
59
60static inline void p852_sku9_b00_display_init(void)
61{
62 p852_sku_peripherals |= P852_SKU_DISPLAY_ENABLE;
63}
64
65static inline void p852_sku9_b00_ulpi_init(void)
66{
67 p852_sku_peripherals |= P852_SKU_ULPI_DISABLE;
68}
69
70static inline void p852_sku9_b00_i2c_init(void)
71{
72 p852_sku_peripherals |= P852_SKU_I2C_ENABLE;
73 p852_i2c_peripherals |=
74 ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) |
75 ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) |
76 ((P852_I2C_ENABLE) << P852_I2C4_SHIFT);
77}
78
79void __init p852_sku9_b00_init(void)
80{
81 p852_sku_peripherals |= P852_SKU_NOR_ENABLE;
82
83 p852_sku9_b00_spi_init();
84 p852_sku9_b00_i2s_init();
85 p852_sku9_b00_uart_init();
86 p852_sku9_b00_sdhci_init();
87 p852_sku9_b00_display_init();
88 p852_sku9_b00_ulpi_init();
89 p852_sku9_b00_i2c_init();
90
91 p852_common_init();
92}
93
diff --git a/arch/arm/mach-tegra/p852/board-p852-sku9-c01.c b/arch/arm/mach-tegra/p852/board-p852-sku9-c01.c
new file mode 100644
index 00000000000..94c79294fb4
--- /dev/null
+++ b/arch/arm/mach-tegra/p852/board-p852-sku9-c01.c
@@ -0,0 +1,92 @@
1/*
2 * arch/arm/mach-tegra/board-p852-sku9-c00.c
3 *
4 * Copyright (C) 2010-2011, NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include "board-p852.h"
18
19static inline void p852_sku9_c00_spi_init(void)
20{
21 p852_sku_peripherals |= P852_SKU_SPI_ENABLE;
22 p852_spi_peripherals |=
23 ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI1_SHIFT) |
24 ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI4_SHIFT);
25}
26
27static inline void p852_sku9_c00_i2s_init(void)
28{
29 p852_sku_peripherals |= P852_SKU_I2S_ENABLE;
30 p852_i2s_peripherals |= ((P852_I2S_ENABLE | P852_I2S_TDM)
31 << P852_I2S1_SHIFT) | ((P852_I2S_ENABLE | P852_I2S_TDM)
32 << P852_I2S2_SHIFT);
33}
34
35static inline void p852_sku9_c00_sdhci_init(void)
36{
37 p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE;
38 p852_sdhci_peripherals |=
39 ((P852_SDHCI_ENABLE)
40 << P852_SDHCI4_SHIFT) |
41 ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN)
42 << P852_SDHCI1_SHIFT) |
43 ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN)
44 << P852_SDHCI3_SHIFT);
45
46 p852_sdhci_platform_data[0].cd_gpio = TEGRA_GPIO_PV0;
47 p852_sdhci_platform_data[0].wp_gpio = TEGRA_GPIO_PV1;
48 p852_sdhci_platform_data[2].cd_gpio = TEGRA_GPIO_PD7;
49 p852_sdhci_platform_data[2].wp_gpio = TEGRA_GPIO_PT4;
50}
51
52static inline void p852_sku9_c00_uart_init(void)
53{
54 p852_sku_peripherals |= P852_SKU_UART_ENABLE;
55 p852_uart_peripherals |=
56 ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTD_SHIFT) |
57 ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT);
58}
59
60static inline void p852_sku9_c00_display_init(void)
61{
62 p852_sku_peripherals |= P852_SKU_DISPLAY_ENABLE;
63}
64
65static inline void p852_sku9_c00_ulpi_init(void)
66{
67 p852_sku_peripherals |= P852_SKU_ULPI_DISABLE;
68}
69
70static inline void p852_sku9_c00_i2c_init(void)
71{
72 p852_sku_peripherals |= P852_SKU_I2C_ENABLE;
73 p852_i2c_peripherals |=
74 ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) |
75 ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) |
76 ((P852_I2C_ENABLE) << P852_I2C4_SHIFT);
77}
78
79void __init p852_sku9_c00_init(void)
80{
81 p852_sku_peripherals |= P852_SKU_NOR_ENABLE;
82
83 p852_sku9_c00_spi_init();
84 p852_sku9_c00_i2s_init();
85 p852_sku9_c00_uart_init();
86 p852_sku9_c00_sdhci_init();
87 p852_sku9_c00_display_init();
88 p852_sku9_c00_ulpi_init();
89 p852_sku9_c00_i2c_init();
90
91 p852_common_init();
92}
diff --git a/arch/arm/mach-tegra/p852/board-p852.c b/arch/arm/mach-tegra/p852/board-p852.c
new file mode 100644
index 00000000000..8e6551ed8c5
--- /dev/null
+++ b/arch/arm/mach-tegra/p852/board-p852.c
@@ -0,0 +1,763 @@
1/*
2 * arch/arm/mach-tegra/board-p852.c
3 *
4 * Copyright (c) 2010-2011, NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include "board-p852.h"
18#include <mach/spdif.h>
19
20unsigned int p852_sku_peripherals;
21unsigned int p852_spi_peripherals;
22unsigned int p852_i2s_peripherals;
23unsigned int p852_uart_peripherals;
24unsigned int p852_i2c_peripherals;
25unsigned int p852_sdhci_peripherals;
26unsigned int p852_display_peripherals;
27
28/* If enable_usb3 can have two options ehci3=eth or usb*/
29static char enable_usb3[4];
30
31int __init parse_enable_usb3(char *arg)
32{
33 if (!arg)
34 return 0;
35
36 strncpy(enable_usb3, arg, sizeof(enable_usb3));
37 return 0;
38}
39
40early_param("ehci3", parse_enable_usb3);
41
42static __initdata struct tegra_clk_init_table p852_clk_init_table[] = {
43 /* name parent rate enabled */
44 {"uarta", "pll_p", 216000000, true},
45 {"uartb", "pll_p", 216000000, true},
46 {"uartc", "pll_p", 216000000, true},
47 {"uartd", "pll_p", 216000000, true},
48 {"pll_m", "clk_m", 600000000, true},
49 {"pll_m_out1", "pll_m", 240000000, true},
50 {"pll_p_out4", "pll_p", 240000000, true},
51 {"host1x", "pll_p", 166000000, true},
52 {"disp1", "pll_p", 216000000, true},
53 {"vi", "pll_m", 100000000, true},
54 {"csus", "pll_m", 100000000, true},
55 {"emc", "pll_m", 600000000, true},
56 {"pll_c", "clk_m", 600000000, true},
57 {"pll_c_out1", "pll_c", 240000000, true},
58 {"pwm", "clk_32k", 32768, false},
59 {"clk_32k", NULL, 32768, true},
60 {"pll_a", NULL, 56448000, true},
61 {"pll_a_out0", "pll_a", 11289600, true},
62 {"audio", "pll_a_out0", 11289600, true},
63 {"audio_2x", "audio", 22579200, false},
64 {"vde", "pll_c", 240000000, false},
65 {"vi_sensor", "pll_m", 111000000, true},
66 {"epp", "pll_m", 111000000, true},
67 {"mpe", "pll_m", 111000000, true},
68 {"i2s1", "pll_a_out0", 11289600, true},
69 {"i2s2", "pll_a_out0", 11289600, true},
70 {"ndflash", "pll_p", 86500000, true},
71 {"sbc1", "pll_p", 12000000, false},
72 {"spdif_in", "pll_m", 22579000, true},
73 {"spdif_out", "pll_a_out0", 5644800, true},
74 {"sbc2", "pll_p", 12000000, false},
75 {"sbc3", "pll_p", 12000000, false},
76 {"sbc4", "pll_p", 12000000, false},
77 {"nor", "pll_p", 86500000, true},
78 {NULL, NULL, 0, 0},
79};
80
81static struct tegra_nand_chip_parms nand_chip_parms[] = {
82 /* Micron 29F4G08ABADA */
83 [0] = {
84 .vendor_id = 0x2C,
85 .device_id = 0xDC,
86 .capacity = 512,
87 .read_id_fourth_byte = 0x95,
88 .timing = {
89 .trp = 1,
90 .trh = 1,
91 .twp = 12,
92 .twh = 12,
93 .tcs = 24,
94 .twhr = 58,
95 .tcr_tar_trr = 12,
96 .twb = 116,
97 .trp_resp = 24,
98 .tadl = 24,
99 },
100 },
101 /* Micron 29F4G16ABADA */
102 [1] = {
103 .vendor_id = 0x2C,
104 .device_id = 0xCC,
105 .capacity = 512,
106 .read_id_fourth_byte = 0xD5,
107 .timing = {
108 .trp = 10,
109 .trh = 7,
110 .twp = 10,
111 .twh = 7,
112 .tcs = 15,
113 .twhr = 60,
114 .tcr_tar_trr = 20,
115 .twb = 100,
116 .trp_resp = 20,
117 .tadl = 70,
118 },
119 },
120 /* Hynix HY27UF084G2B */
121 [2] = {
122 .vendor_id = 0xAD,
123 .device_id = 0xDC,
124 .read_id_fourth_byte = 0x95,
125 .capacity = 512,
126 .timing = {
127 .trp = 12,
128 .trh = 1,
129 .twp = 12,
130 .twh = 0,
131 .tcs = 24,
132 .twhr = 58,
133 .tcr_tar_trr = 0,
134 .twb = 116,
135 .trp_resp = 24,
136 .tadl = 24,
137 },
138 },
139};
140
141struct tegra_nand_platform p852_nand_data = {
142 .max_chips = 8,
143 .chip_parms = nand_chip_parms,
144 .nr_chip_parms = ARRAY_SIZE(nand_chip_parms),
145 .wp_gpio = TEGRA_GPIO_PC7,
146};
147
148static struct resource resources_nand[] = {
149 [0] = {
150 .start = INT_NANDFLASH,
151 .end = INT_NANDFLASH,
152 .flags = IORESOURCE_IRQ,
153 },
154};
155
156static struct platform_device p852_nand_device = {
157 .name = "tegra_nand",
158 .id = -1,
159 .num_resources = ARRAY_SIZE(resources_nand),
160 .resource = resources_nand,
161 .dev = {
162 .platform_data = &p852_nand_data,
163 },
164};
165
166unsigned int p852_uart_irqs[] = {
167 INT_UARTA,
168 INT_UARTB,
169 INT_UARTC,
170 INT_UARTD,
171};
172
173unsigned int p852_uart_bases[] = {
174 TEGRA_UARTA_BASE,
175 TEGRA_UARTB_BASE,
176 TEGRA_UARTC_BASE,
177 TEGRA_UARTD_BASE,
178};
179
180static struct platform_device *p852_spi_devices[] __initdata = {
181 &tegra_spi_device1,
182 &tegra_spi_device2,
183 &tegra_spi_device3,
184 &tegra_spi_device4,
185};
186
187static struct plat_serial8250_port debug_uart_platform_data[] = {
188 {
189 .flags = UPF_BOOT_AUTOCONF,
190 .iotype = UPIO_MEM,
191 .regshift = 2,
192 .uartclk = 216000000,
193 },
194 {
195 .flags = 0,
196 }
197};
198
199#define DEF_8250_PLATFORM_DATA(_base, _irq) { \
200 .flags = UPF_BOOT_AUTOCONF, \
201 .iotype = UPIO_MEM, \
202 .membase = IO_ADDRESS(_base), \
203 .mapbase = _base, \
204 .irq = _irq, \
205 .regshift = 2, \
206 .uartclk = 216000000, \
207}
208
209static struct plat_serial8250_port tegra_8250_uarta_platform_data[] = {
210 DEF_8250_PLATFORM_DATA(TEGRA_UARTA_BASE, INT_UARTA),
211 {
212 .flags = 0,
213 }
214};
215
216static struct plat_serial8250_port tegra_8250_uartb_platform_data[] = {
217 DEF_8250_PLATFORM_DATA(TEGRA_UARTB_BASE, INT_UARTB),
218 {
219 .flags = 0,
220 }
221};
222
223static struct plat_serial8250_port tegra_8250_uartc_platform_data[] = {
224 DEF_8250_PLATFORM_DATA(TEGRA_UARTC_BASE, INT_UARTC),
225 {
226 .flags = 0,
227 }
228};
229
230static struct plat_serial8250_port tegra_8250_uartd_platform_data[] = {
231 DEF_8250_PLATFORM_DATA(TEGRA_UARTD_BASE, INT_UARTD),
232 {
233 .flags = 0,
234 }
235};
236
237static struct plat_serial8250_port tegra_8250_uarte_platform_data[] = {
238 DEF_8250_PLATFORM_DATA(TEGRA_UARTE_BASE, INT_UARTE),
239 {
240 .flags = 0,
241 }
242};
243
244struct platform_device tegra_8250_uarta_device = {
245 .name = "serial8250",
246 .id = PLAT8250_DEV_PLATFORM,
247 .dev = {
248 .platform_data = tegra_8250_uarta_platform_data,
249 },
250};
251
252struct platform_device tegra_8250_uartb_device = {
253 .name = "serial8250",
254 .id = PLAT8250_DEV_PLATFORM1,
255 .dev = {
256 .platform_data = tegra_8250_uartb_platform_data,
257 },
258};
259
260struct platform_device tegra_8250_uartc_device = {
261 .name = "serial8250",
262 .id = PLAT8250_DEV_PLATFORM2,
263 .dev = {
264 .platform_data = tegra_8250_uartc_platform_data,
265 },
266};
267
268struct platform_device tegra_8250_uartd_device = {
269 .name = "serial8250",
270 .id = PLAT8250_DEV_FOURPORT,
271 .dev = {
272 .platform_data = tegra_8250_uartd_platform_data,
273 },
274};
275
276struct platform_device tegra_8250_uarte_device = {
277 .name = "serial8250",
278 .id = PLAT8250_DEV_ACCENT,
279 .dev = {
280 .platform_data = tegra_8250_uarte_platform_data,
281 },
282};
283
284static struct platform_device debug_uart = {
285 .name = "serial8250",
286 .id = PLAT8250_DEV_PLATFORM,
287 .dev = {
288 .platform_data = debug_uart_platform_data,
289 },
290};
291
292static struct tegra_utmip_config utmi_phy_config[] = {
293 [0] = {
294 .hssync_start_delay = 0,
295 .idle_wait_delay = 17,
296 .elastic_limit = 16,
297 .term_range_adj = 6,
298 .xcvr_setup = 15,
299 .xcvr_lsfslew = 2,
300 .xcvr_lsrslew = 2,
301 },
302 [1] = {
303 .hssync_start_delay = 0,
304 .idle_wait_delay = 17,
305 .elastic_limit = 16,
306 .term_range_adj = 6,
307 .xcvr_setup = 8,
308 .xcvr_lsfslew = 2,
309 .xcvr_lsrslew = 2,
310 },
311};
312
313static struct tegra_ulpi_config ulpi_usb2_config = {
314 .reset_gpio = TEGRA_GPIO_PI5,
315};
316
317static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
318 [0] = {
319 .phy_config = &utmi_phy_config[0],
320 .operating_mode = TEGRA_USB_HOST,
321 .power_down_on_bus_suspend = 0,
322 },
323 [1] = {
324 .phy_config = &ulpi_usb2_config,
325 .operating_mode = TEGRA_USB_HOST,
326 .power_down_on_bus_suspend = 0,
327 .phy_type = TEGRA_USB_PHY_TYPE_LINK_ULPI,
328 },
329 [2] = {
330 .phy_config = &utmi_phy_config[1],
331 .operating_mode = TEGRA_USB_HOST,
332 .power_down_on_bus_suspend = 0,
333 },
334};
335
336static void p852_usb_gpio_config(void)
337{
338 unsigned int usbeth_mux_gpio = 0, usb_ena_val;
339 unsigned int has_onboard_ethernet = 0;
340 unsigned int p852_eth_reset = TEGRA_GPIO_PD3;
341
342 switch (system_rev) {
343 case P852_SKU13_B00:
344 case P852_SKU23_B00:
345 case P852_SKU23_C01:
346 case P852_SKU8_B00:
347 case P852_SKU8_C01:
348 case P852_SKU9_B00:
349 case P852_SKU9_C01:
350 {
351 usbeth_mux_gpio = TEGRA_GPIO_PS3;
352 has_onboard_ethernet = 1;
353 usb_ena_val = 1;
354 }
355 break;
356 case P852_SKU5_B00:
357 case P852_SKU5_C01:
358 {
359 usb_ena_val = 1;
360 has_onboard_ethernet = 0;
361 }
362 break;
363 case P852_SKU1:
364 {
365 has_onboard_ethernet = 0;
366 usb_ena_val = 0;
367 strncpy(enable_usb3, "usb", sizeof(enable_usb3));
368 }
369 break;
370 case P852_SKU1_B00:
371 case P852_SKU1_C0X:
372 {
373 has_onboard_ethernet = 0;
374 usb_ena_val = 1;
375 strncpy(enable_usb3, "usb", sizeof(enable_usb3));
376 }
377 break;
378 default:
379 {
380 usbeth_mux_gpio = TEGRA_GPIO_PD4;
381 has_onboard_ethernet = 1;
382 usb_ena_val = 0;
383 }
384 }
385
386 if (has_onboard_ethernet) {
387 gpio_request_one(usbeth_mux_gpio, GPIOF_OUT_INIT_LOW,
388 "eth_ena");
389 tegra_gpio_enable(usbeth_mux_gpio);
390
391 /* eth reset */
392 gpio_request_one(p852_eth_reset, GPIOF_OUT_INIT_LOW,
393 "eth_reset");
394 tegra_gpio_enable(p852_eth_reset);
395 udelay(1);
396 gpio_direction_output(p852_eth_reset, 1);
397
398 if (!strcmp(enable_usb3, "eth"))
399 gpio_direction_output(usbeth_mux_gpio, 1);
400
401 /* exporting usbeth_mux_gpio */
402 gpio_export(usbeth_mux_gpio, true);
403 }
404
405 if (!strcmp(enable_usb3, "usb")) {
406 gpio_direction_output(TEGRA_GPIO_PB2, usb_ena_val);
407 gpio_direction_output(TEGRA_GPIO_PW1, usb_ena_val);
408 }
409}
410
411static struct platform_device *p852_uart_devices[] __initdata = {
412 &tegra_uarta_device,
413 &tegra_uartb_device,
414 &tegra_uartc_device,
415 &tegra_uartd_device,
416};
417
418static struct platform_device *p852_8250_uart_devices[] __initdata = {
419 &tegra_8250_uarta_device,
420 &tegra_8250_uartb_device,
421 &tegra_8250_uartc_device,
422 &tegra_8250_uartd_device,
423 &tegra_8250_uarte_device,
424};
425
426static struct platform_device tegra_itu656 = {
427 .name = "tegra_itu656",
428 .id = -1,
429};
430
431static struct platform_device *p852_devices[] __initdata = {
432 &tegra_gart_device,
433 &tegra_avp_device,
434 &tegra_itu656,
435};
436
437static struct tegra_nor_platform_data p852_nor_data = {
438 .flash = {
439 .map_name = "cfi_probe",
440 .width = 2,
441 },
442 .chip_parms = {
443 /* FIXME: use characterized clock freq */
444 .timing_default = {
445 .timing0 = 0xA0200253,
446 .timing1 = 0x00040406,
447 },
448 .timing_read = {
449 .timing0 = 0xA0200253,
450 .timing1 = 0x00000A00,
451 },
452 },
453};
454
455#ifdef CONFIG_TEGRA_SPI_I2S
456struct spi_board_info tegra_spi_i2s_device __initdata = {
457 .modalias = "spi_i2s_pcm",
458 .bus_num = 2,
459 .chip_select = 2,
460 .mode = SPI_MODE_0,
461 .max_speed_hz = 18000000,
462 .platform_data = NULL,
463 .irq = 0,
464};
465
466void __init p852_spi_i2s_init(void)
467{
468 struct tegra_spi_i2s_platform_data *pdata;
469
470 pdata = (struct tegra_spi_i2s_platform_data *)
471 tegra_spi_i2s_device.platform_data;
472 if (pdata->gpio_i2s.active_state) {
473 gpio_request_one(pdata->gpio_i2s.gpio_no, GPIOF_OUT_INIT_LOW,
474 "i2s_cpld_dir1");
475 } else {
476 gpio_request_one(pdata->gpio_i2s.gpio_no, GPIOF_OUT_INIT_HIGH,
477 "i2s_cpld_dir1");
478 }
479 tegra_gpio_enable(pdata->gpio_i2s.gpio_no);
480 if (pdata->gpio_spi.active_state) {
481 gpio_request_one(pdata->gpio_spi.gpio_no, GPIOF_OUT_INIT_LOW,
482 "spi_cpld_dir2");
483 } else {
484 gpio_request_one(pdata->gpio_spi.gpio_no, GPIOF_OUT_INIT_HIGH,
485 "spi_cpld_dir2");
486 }
487
488 tegra_gpio_enable(pdata->gpio_spi.gpio_no);
489 spi_register_board_info(&tegra_spi_i2s_device, 1);
490}
491#endif
492
493#if defined(CONFIG_SPI_TEGRA) && defined(CONFIG_SPI_SPIDEV)
494static struct spi_board_info tegra_spi_devices[] __initdata = {
495 {
496 .modalias = "spidev",
497 .bus_num = 0,
498 .chip_select = 0,
499 .mode = SPI_MODE_0,
500 .max_speed_hz = 18000000,
501 .platform_data = NULL,
502 .irq = 0,
503 },
504 {
505 .modalias = "spidev",
506 .bus_num = 1,
507 .chip_select = 1,
508 .mode = SPI_MODE_0,
509 .max_speed_hz = 18000000,
510 .platform_data = NULL,
511 .irq = 0,
512 },
513 {
514 .modalias = "spidev",
515 .bus_num = 3,
516 .chip_select = 1,
517 .mode = SPI_MODE_0,
518 .max_speed_hz = 18000000,
519 .platform_data = NULL,
520 .irq = 0,
521 },
522};
523
524static void __init p852_register_spidev(void)
525{
526 spi_register_board_info(tegra_spi_devices,
527 ARRAY_SIZE(tegra_spi_devices));
528}
529#else
530#define p852_register_spidev() do {} while (0)
531#endif
532
533static void __init p852_usb_init(void)
534{
535
536 p852_usb_gpio_config();
537 /*
538 if (system_rev == P852_SKU8)
539 {
540 platform_device_register(&tegra_udc_device);
541 }
542 else
543 */
544 {
545 tegra_ehci1_device.dev.platform_data = &tegra_ehci_pdata[0];
546 platform_device_register(&tegra_ehci1_device);
547 }
548
549 if (!(p852_sku_peripherals & P852_SKU_ULPI_DISABLE)) {
550 tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1];
551 platform_device_register(&tegra_ehci2_device);
552 }
553
554 tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata[2];
555 platform_device_register(&tegra_ehci3_device);
556}
557
558static void __init spi3_pingroup_clear_tristate(void)
559{
560 /* spi3 mosi, miso, cs, clk */
561 tegra_pinmux_set_tristate(TEGRA_PINGROUP_LSDI, TEGRA_TRI_NORMAL);
562 tegra_pinmux_set_tristate(TEGRA_PINGROUP_LSDA, TEGRA_TRI_NORMAL);
563 tegra_pinmux_set_tristate(TEGRA_PINGROUP_LCSN, TEGRA_TRI_NORMAL);
564 tegra_pinmux_set_tristate(TEGRA_PINGROUP_LSCK, TEGRA_TRI_NORMAL);
565}
566
567static void __init p852_spi_init(void)
568{
569 if (p852_sku_peripherals & P852_SKU_SPI_ENABLE) {
570 int i = 0;
571 unsigned int spi_config = 0;
572 unsigned int spi3_config =
573 (p852_spi_peripherals >> P852_SPI3_SHIFT) & P852_SPI_MASK;
574
575 for (i = 0; i < P852_MAX_SPI; i++) {
576 spi_config =
577 (p852_spi_peripherals >> (P852_SPI_SHIFT * i)) &
578 P852_SPI_MASK;
579 if (spi_config & P852_SPI_ENABLE) {
580 if (spi_config & P852_SPI_SLAVE)
581 p852_spi_devices[i]->name =
582 "tegra_spi_slave";
583 platform_device_register(p852_spi_devices[i]);
584 }
585 }
586 /* Default spi3 pingroups are in tristate */
587 if (spi3_config & P852_SPI_ENABLE)
588 spi3_pingroup_clear_tristate();
589 }
590}
591
592static void __init p852_uart_init(void)
593{
594 if (p852_sku_peripherals & P852_SKU_UART_ENABLE) {
595 int i = 0;
596 unsigned int uart_config = 0, uart8250Id = 0;
597 int debug_console = -1;
598
599 /* register the debug console as the first serial console */
600 for (i = 0; i < P852_MAX_UART; i++) {
601 uart_config =
602 (p852_uart_peripherals >> (P852_UART_SHIFT * i));
603 if (uart_config & P852_UART_DB) {
604 debug_console = i;
605 debug_uart_platform_data[0].membase =
606 IO_ADDRESS(p852_uart_bases[i]);
607 debug_uart_platform_data[0].mapbase =
608 p852_uart_bases[i];
609 debug_uart_platform_data[0].irq =
610 p852_uart_irqs[i];
611 uart8250Id++;
612 platform_device_register(&debug_uart);
613 break;
614 }
615 }
616
617 /* register remaining UARTS */
618 for (i = 0; i < P852_MAX_UART; i++) {
619 uart_config =
620 (p852_uart_peripherals >> (P852_UART_SHIFT * i)) &
621 P852_UART_MASK;
622 if ((uart_config & P852_UART_ENABLE)
623 && i != debug_console) {
624 if (uart_config & P852_UART_HS) {
625 platform_device_register
626 (p852_uart_devices[i]);
627 } else {
628 p852_8250_uart_devices[i]->id =
629 uart8250Id++;
630 platform_device_register
631 (p852_8250_uart_devices[i]);
632 }
633 }
634 }
635 }
636}
637
638static struct platform_device generic_codec_driver = {
639 .name = "generic-dit",
640};
641
642static void __init p852_flash_init(void)
643{
644 if (p852_sku_peripherals & P852_SKU_NAND_ENABLE)
645 platform_device_register(&p852_nand_device);
646
647 if (p852_sku_peripherals & P852_SKU_NOR_ENABLE) {
648 tegra_nor_device.resource[2].end = TEGRA_NOR_FLASH_BASE + SZ_64M - 1;
649 tegra_nor_device.dev.platform_data = &p852_nor_data;
650 platform_device_register(&tegra_nor_device);
651 }
652}
653
654void __init p852_common_init(void)
655{
656 tegra_clk_init_from_table(p852_clk_init_table);
657
658 p852_pinmux_init();
659
660 p852_i2c_init();
661
662 p852_regulator_init();
663
664 p852_uart_init();
665
666 p852_flash_init();
667
668 platform_add_devices(p852_devices, ARRAY_SIZE(p852_devices));
669
670 //p852_panel_init();
671
672 p852_spi_init();
673
674 p852_register_spidev();
675
676 p852_usb_init();
677
678 p852_sdhci_init();
679
680 p852_gpio_init();
681}
682
683void __init tegra_p852_init(void)
684{
685 switch (system_rev) {
686 case P852_SKU3:
687 p852_sku3_init();
688 break;
689 case P852_SKU13:
690 p852_sku13_init();
691 break;
692 case P852_SKU13_B00:
693 case P852_SKU13_C01:
694 p852_sku13_b00_init();
695 break;
696 case P852_SKU23:
697 p852_sku23_init();
698 break;
699 case P852_SKU23_B00:
700 p852_sku23_b00_init();
701 break;
702 case P852_SKU23_C01:
703 p852_sku23_c01_init();
704 break;
705 case P852_SKU1:
706 p852_sku1_init();
707 break;
708 case P852_SKU11:
709 case P852_SKU1_B00:
710 p852_sku1_b00_init();
711 break;
712 case P852_SKU1_C0X:
713 p852_sku1_c0x_init();
714 break;
715 case P852_SKU5_B00:
716 p852_sku5_b00_init();
717 break;
718 case P852_SKU5_C01:
719 p852_sku5_c01_init();
720 break;
721 case P852_SKU8_B00:
722 p852_sku8_b00_init();
723 break;
724 case P852_SKU8_C01:
725 p852_sku8_c00_init();
726 break;
727 case P852_SKU9_B00:
728 p852_sku9_b00_init();
729 break;
730 case P852_SKU9_C01:
731 p852_sku9_c00_init();
732 break;
733 default:
734 printk(KERN_ERR "Unknow Board Revision\n");
735 break;
736 }
737}
738
739static void __init tegra_p852_reserve(void)
740{
741 switch (system_rev) {
742 case P852_SKU3:
743 case P852_SKU5_B00:
744 case P852_SKU5_C01:
745 case P852_SKU9_B00:
746 case P852_SKU9_C01:
747 tegra_reserve(SZ_64M + SZ_16M, SZ_8M, 0);
748 break;
749 default:
750 tegra_reserve(SZ_128M, SZ_8M, 0);
751 break;
752 }
753}
754
755MACHINE_START(P852, "Tegra P852")
756 .boot_params = 0x00000100,
757 .map_io = tegra_map_common_io,
758 .reserve = tegra_p852_reserve,
759 .init_early = tegra_init_early,
760 .init_irq = tegra_init_irq,
761 .timer = &tegra_timer,
762 .init_machine = tegra_p852_init,
763MACHINE_END
diff --git a/arch/arm/mach-tegra/p852/board-p852.h b/arch/arm/mach-tegra/p852/board-p852.h
new file mode 100644
index 00000000000..bb43febb4a2
--- /dev/null
+++ b/arch/arm/mach-tegra/p852/board-p852.h
@@ -0,0 +1,300 @@
1/*
2 * arch/arm/mach-tegra/board-p852.h
3 *
4 * Copyright (c) 2010-2011, NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef _MACH_TEGRA_BOARD_P852M_H
18#define _MACH_TEGRA_BOARD_P852M_H
19
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/platform_device.h>
23#include <linux/serial_8250.h>
24#include <linux/clk.h>
25#include <linux/mtd/mtd.h>
26#include <linux/mtd/partitions.h>
27#include <linux/dma-mapping.h>
28#include <linux/io.h>
29#include <linux/delay.h>
30#include <linux/i2c.h>
31#include <linux/spi/spi.h>
32#include <linux/i2c-tegra.h>
33#include <linux/platform_data/tegra_usb.h>
34#include <linux/platform_data/tegra_nor.h>
35#include <linux/gpio.h>
36
37#include <asm/mach-types.h>
38#include <asm/mach/arch.h>
39#include <asm/mach/time.h>
40#include <asm/setup.h>
41#include <asm/mach-types.h>
42#include <asm/mach/flash.h>
43
44#include <mach/sdhci.h>
45#include <mach/iomap.h>
46#include <mach/irqs.h>
47#include <mach/nand.h>
48#include <mach/usb_phy.h>
49#include <mach/clk.h>
50#include <mach/i2s.h>
51#include <mach/audio.h>
52
53#include "../clock.h"
54#include "../board.h"
55#include "../pm.h"
56#include "../devices.h"
57#include "../gpio-names.h"
58#include "../wakeups-t2.h"
59
60
61#define P852_SKU3 0x030000UL
62#define P852_SKU13 0x130000UL
63#define P852_SKU13_B00 0x130200UL
64#define P852_SKU13_C01 0x130401UL
65#define P852_SKU23 0x230000UL
66#define P852_SKU23_B00 0x230200UL
67#define P852_SKU23_C01 0x230401UL
68#define P852_SKU1 0x010000UL
69#define P852_SKU1_B00 0x010200UL
70#define P852_SKU1_C0X 0x010400UL
71#define P852_SKU11 0x110000UL
72#define P852_SKU5_B00 0x040200UL
73#define P852_SKU5_C01 0x050401UL
74#define P852_SKU8_B00 0x080200UL
75#define P852_SKU8_C01 0x080401UL
76#define P852_SKU9_B00 0x090200UL
77#define P852_SKU9_C01 0x090401UL
78
79int p852_regulator_init(void);
80int p852_panel_init(void);
81void p852_sdhci_init(void);
82void p852_i2c_init(void);
83void p852_i2c_set_default_clock(int adapter, unsigned long clock);
84void p852_pinmux_init(void);
85void p852_gpio_init(void);
86
87void p852_sku1_init(void);
88void p852_sku1_b00_init(void);
89void p852_sku1_c0x_init(void);
90void p852_sku3_init(void);
91void p852_sku5_b00_init(void);
92void p852_sku5_c01_init(void);
93void p852_sku8_b00_init(void);
94void p852_sku8_c00_init(void);
95void p852_sku9_b00_init(void);
96void p852_sku9_c00_init(void);
97void p852_sku13_init(void);
98void p852_sku13_b00_init(void);
99void p852_sku23_init(void);
100void p852_sku23_b00_init(void);
101void p852_sku23_c01_init(void);
102
103#ifndef CONFIG_P852_SKU1
104void p852_sku1_init(void);
105#endif
106#ifndef CONFIG_P852_SKU1_B00
107void p852_sku1_b00_init(void);
108#endif
109#ifndef CONFIG_P852_SKU1_C0x
110void p852_sku1_c0x_init(void);
111#endif
112#ifndef CONFIG_P852_SKU3
113void p852_sku3_init(void);
114#endif
115#ifndef CONFIG_P852_SKU5_B00
116void p852_sku5_b00_init(void){};
117#endif
118#ifndef CONFIG_P852_SKU5_C01
119void p852_sku5_c01_init(void){};
120#endif
121#ifndef CONFIG_P852_SKU8_B00
122void p852_sku8_b00_init(void){};
123#endif
124#ifndef CONFIG_P852_SKU8_C01
125void p852_sku8_c00_init(void){};
126#endif
127#ifndef CONFIG_P852_SKU9_B00
128void p852_sku9_b00_init(void){};
129#endif
130#ifndef CONFIG_P852_SKU9_C01
131void p852_sku9_c00_init(void){};
132#endif
133#ifndef CONFIG_P852_SKU13
134void p852_sku13_init(void){};
135#endif
136#ifndef CONFIG_P852_SKU13_B00
137void p852_sku13_b00_init(void){};
138#endif
139#ifndef CONFIG_P852_SKU23
140void p852_sku23_init(void){};
141#endif
142#ifndef CONFIG_P852_SKU23_B00
143void p852_sku23_b00_init(void){};
144#endif
145#ifndef CONFIG_P852_SKU23_C01
146void p852_sku23_c01_init(void){};
147#endif
148
149extern unsigned int system_rev;
150extern unsigned int p852_sku_peripherals;
151extern unsigned int p852_spi_peripherals;
152extern unsigned int p852_i2s_peripherals;
153extern unsigned int p852_uart_peripherals;
154extern unsigned int p852_sdhci_peripherals;
155extern unsigned int p852_display_peripherals;
156extern unsigned int p852_i2c_peripherals;
157extern struct tegra_sdhci_platform_data p852_sdhci_platform_data[];
158extern struct platform_device tegra_8250_uarta_device;
159extern struct platform_device tegra_8250_uartb_device;
160extern struct platform_device tegra_8250_uartc_device;
161extern struct platform_device tegra_8250_uartd_device;
162extern struct platform_device tegra_8250_uarte_device;
163
164#ifdef CONFIG_TEGRA_SPI_I2S
165extern void p852_spi_i2s_init(void);
166extern struct spi_board_info tegra_spi_i2s_device;
167#endif
168
169void tegra_p852_fixup(struct machine_desc *desc,
170 struct tag *tags, char **cmdline, struct meminfo *mi);
171
172void p852_common_init(void);
173
174#define P852_SDIO3_PINMUX_ENABLE 0x01
175
176#define P852_SKU_SPI_SHIFT 0x00
177#define P852_SKU_SPI_ENABLE (1 << P852_SKU_SPI_SHIFT)
178#define P852_SKU_SPI_MASK (1 << P852_SKU_SPI_SHIFT)
179
180#define P852_SKU_I2S_SHIFT 0x01
181#define P852_SKU_I2S_ENABLE (1 << P852_SKU_I2S_SHIFT)
182#define P852_SKU_I2S_MASK (1 << P852_SKU_I2S_SHIFT)
183
184#define P852_SKU_SDHCI_SHIFT 0x02
185#define P852_SKU_SDHCI_ENABLE (1 << P852_SKU_SDHCI_SHIFT)
186#define P852_SKU_SDHCI_MASK (1 << P852_SKU_SDHCI_SHIFT)
187
188#define P852_SKU_UART_SHIFT 0x03
189#define P852_SKU_UART_ENABLE (1 << P852_SKU_UART_SHIFT)
190#define P852_SKU_UART_MASK (1 << P852_SKU_UART_SHIFT)
191
192#define P852_SKU_NAND_SHIFT 0x04
193#define P852_SKU_NAND_ENABLE (1 << P852_SKU_NAND_SHIFT)
194#define P852_SKU_NAND_MASK (1 << P852_SKU_NAND_SHIFT)
195
196#define P852_SKU_NOR_SHIFT 0x05
197#define P852_SKU_NOR_ENABLE (1 << P852_SKU_NOR_SHIFT)
198#define P852_SKU_NOR_MASK (1 << P852_SKU_NOR_SHIFT)
199
200#define P852_SKU_DISPLAY_SHIFT 0x06
201#define P852_SKU_DISPLAY_ENABLE (1 << P852_SKU_DISPLAY_SHIFT)
202#define P852_SKU_DISPLAY_MASK (1 << P852_SKU_DISPLAY_SHIFT)
203
204#define P852_SKU_ULPI_SHIFT 0x07
205#define P852_SKU_ULPI_DISABLE (1 << P852_SKU_ULPI_SHIFT)
206
207#define P852_SKU_I2C_SHIFT 0x08
208#define P852_SKU_I2C_ENABLE (1 << P852_SKU_I2C_SHIFT)
209#define P852_SKU_I2C_MASK (1 << P852_SKU_I2C_SHIFT)
210
211#define P852_MAX_DISP 0x2
212#define P852_DISP_SHIFT 0x16
213#define P852_DISPA_SHIFT 0x0
214#define P852_DISPB_SHIFT 0x16
215
216#define P852_DISP_MASK 0x1
217#define P852_DISP_ENABLE 0x1
218#define P852_DISPA_MASK (P852_DISP_MASK << P852_DISPA_SHIFT)
219#define P852_DISPB_MASK (P852_DISP_MASK << P852_DISPB_SHIFT)
220
221#define P852_MAX_SPI 0x04
222#define P852_SPI_SHIFT 0x03
223#define P852_SPI1_SHIFT 0x00
224#define P852_SPI2_SHIFT 0x03
225#define P852_SPI3_SHIFT 0x06
226#define P852_SPI4_SHIFT 0x09
227
228#define P852_SPI_MASK 0x07
229#define P852_SPI1_MASK (P852_SPI_MASK << P852_SPI1_SHIFT)
230#define P852_SPI2_MASK (P852_SPI_MASK << P852_SPI2_SHIFT)
231#define P852_SPI3_MASK (P852_SPI_MASK << P852_SPI3_SHIFT)
232#define P852_SPI4_MASK (P852_SPI_MASK << P852_SPI4_SHIFT)
233
234#define P852_SPI_ENABLE 0x01
235#define P852_SPI_MASTER 0x02
236#define P852_SPI_SLAVE 0x04
237
238#define P852_I2S_SHIFT 0x05
239#define P852_I2S1_SHIFT 0x00
240#define P852_I2S2_SHIFT 0x05
241
242#define P852_I2S_MASK 0x1F
243#define P852_I2S1_MASK (P852_I2S_MASK << P852_I2S1_SHIFT)
244#define P852_I2S2_MASK (P852_I2S_MASK << P852_I2S2_SHIFT)
245
246#define P852_I2S_ENABLE 0x10
247#define P852_I2S_TDM 0x08
248#define P852_MAX_SDHCI 0x04
249#define P852_SDHCI_SHIFT 0x04
250#define P852_SDHCI1_SHIFT 0x00
251#define P852_SDHCI2_SHIFT 0x04
252#define P852_SDHCI3_SHIFT 0x08
253#define P852_SDHCI4_SHIFT 0x0C
254
255#define P852_SDHCI_MASK 0x0F
256#define P852_SDHCI1_MASK (P852_SDHCI_MASK << P852_SDHCI1_SHIFT)
257#define P852_SDHCI2_MASK (P852_SDHCI_MASK << P852_SDHCI2_SHIFT)
258#define P852_SDHCI3_MASK (P852_SDHCI_MASK << P852_SDHCI3_SHIFT)
259#define P852_SDHCI4_MASK (P852_SDHCI_MASK << P852_SDHCI4_SHIFT)
260
261#define P852_SDHCI_ENABLE 0x01
262#define P852_SDHCI_CD_EN 0x02
263#define P852_SDHCI_WP_EN 0x04
264#define P852_SDHCI_PW_EN 0x08
265
266#define P852_UART_SHIFT 0x04
267#define P852_UARTA_SHIFT 0x00
268#define P852_UARTB_SHIFT 0x04
269#define P852_UARTC_SHIFT 0x08
270#define P852_UARTD_SHIFT 0x0C
271
272#define P852_UART_MASK 0x0F
273#define P852_UARTA_MASK (P852_UART_MASK << P852_UARTA_SHIFT)
274#define P852_UARTB_MASK (P852_UART_MASK << P852_UARTB_SHIFT)
275#define P852_UARTC_MASK (P852_UART_MASK << P852_UARTC_SHIFT)
276#define P852_UARTD_MASK (P852_UART_MASK << P852_UARTD_SHIFT)
277
278#define P852_MAX_UART 0x4
279#define P852_UART_ALT_PIN_CFG 0x8
280#define P852_UART_ENABLE 0x4
281#define P852_UART_DB 0x1
282#define P852_UART_HS 0x2
283
284#define P852_MAX_I2C 0x4
285#define P852_I2C_SHIFT 0x01
286#define P852_I2C1_SHIFT 0x00
287#define P852_I2C2_SHIFT 0x01
288#define P852_I2C3_SHIFT 0x02
289#define P852_I2C4_SHIFT 0x03
290
291
292#define P852_I2C_MASK 0x01
293#define P852_I2C1_MASK (P852_I2C_MASK << P852_I2C1_SHIFT)
294#define P852_I2C2_MASK (P852_I2C_MASK << P852_I2C2_SHIFT)
295#define P852_I2C3_MASK (P852_I2C_MASK << P852_I2C3_SHIFT)
296#define P852_I2C4_MASK (P852_I2C_MASK << P852_I2C4_SHIFT)
297
298#define P852_I2C_ENABLE 0x01
299
300#endif
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