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diff --git a/arch/arm/mach-tegra/p852/board-p852.c b/arch/arm/mach-tegra/p852/board-p852.c
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1/*
2 * arch/arm/mach-tegra/board-p852.c
3 *
4 * Copyright (c) 2010-2011, NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include "board-p852.h"
18#include <mach/spdif.h>
19
20unsigned int p852_sku_peripherals;
21unsigned int p852_spi_peripherals;
22unsigned int p852_i2s_peripherals;
23unsigned int p852_uart_peripherals;
24unsigned int p852_i2c_peripherals;
25unsigned int p852_sdhci_peripherals;
26unsigned int p852_display_peripherals;
27
28/* If enable_usb3 can have two options ehci3=eth or usb*/
29static char enable_usb3[4];
30
31int __init parse_enable_usb3(char *arg)
32{
33 if (!arg)
34 return 0;
35
36 strncpy(enable_usb3, arg, sizeof(enable_usb3));
37 return 0;
38}
39
40early_param("ehci3", parse_enable_usb3);
41
42static __initdata struct tegra_clk_init_table p852_clk_init_table[] = {
43 /* name parent rate enabled */
44 {"uarta", "pll_p", 216000000, true},
45 {"uartb", "pll_p", 216000000, true},
46 {"uartc", "pll_p", 216000000, true},
47 {"uartd", "pll_p", 216000000, true},
48 {"pll_m", "clk_m", 600000000, true},
49 {"pll_m_out1", "pll_m", 240000000, true},
50 {"pll_p_out4", "pll_p", 240000000, true},
51 {"host1x", "pll_p", 166000000, true},
52 {"disp1", "pll_p", 216000000, true},
53 {"vi", "pll_m", 100000000, true},
54 {"csus", "pll_m", 100000000, true},
55 {"emc", "pll_m", 600000000, true},
56 {"pll_c", "clk_m", 600000000, true},
57 {"pll_c_out1", "pll_c", 240000000, true},
58 {"pwm", "clk_32k", 32768, false},
59 {"clk_32k", NULL, 32768, true},
60 {"pll_a", NULL, 56448000, true},
61 {"pll_a_out0", "pll_a", 11289600, true},
62 {"audio", "pll_a_out0", 11289600, true},
63 {"audio_2x", "audio", 22579200, false},
64 {"vde", "pll_c", 240000000, false},
65 {"vi_sensor", "pll_m", 111000000, true},
66 {"epp", "pll_m", 111000000, true},
67 {"mpe", "pll_m", 111000000, true},
68 {"i2s1", "pll_a_out0", 11289600, true},
69 {"i2s2", "pll_a_out0", 11289600, true},
70 {"ndflash", "pll_p", 86500000, true},
71 {"sbc1", "pll_p", 12000000, false},
72 {"spdif_in", "pll_m", 22579000, true},
73 {"spdif_out", "pll_a_out0", 5644800, true},
74 {"sbc2", "pll_p", 12000000, false},
75 {"sbc3", "pll_p", 12000000, false},
76 {"sbc4", "pll_p", 12000000, false},
77 {"nor", "pll_p", 86500000, true},
78 {NULL, NULL, 0, 0},
79};
80
81static struct tegra_nand_chip_parms nand_chip_parms[] = {
82 /* Micron 29F4G08ABADA */
83 [0] = {
84 .vendor_id = 0x2C,
85 .device_id = 0xDC,
86 .capacity = 512,
87 .read_id_fourth_byte = 0x95,
88 .timing = {
89 .trp = 1,
90 .trh = 1,
91 .twp = 12,
92 .twh = 12,
93 .tcs = 24,
94 .twhr = 58,
95 .tcr_tar_trr = 12,
96 .twb = 116,
97 .trp_resp = 24,
98 .tadl = 24,
99 },
100 },
101 /* Micron 29F4G16ABADA */
102 [1] = {
103 .vendor_id = 0x2C,
104 .device_id = 0xCC,
105 .capacity = 512,
106 .read_id_fourth_byte = 0xD5,
107 .timing = {
108 .trp = 10,
109 .trh = 7,
110 .twp = 10,
111 .twh = 7,
112 .tcs = 15,
113 .twhr = 60,
114 .tcr_tar_trr = 20,
115 .twb = 100,
116 .trp_resp = 20,
117 .tadl = 70,
118 },
119 },
120 /* Hynix HY27UF084G2B */
121 [2] = {
122 .vendor_id = 0xAD,
123 .device_id = 0xDC,
124 .read_id_fourth_byte = 0x95,
125 .capacity = 512,
126 .timing = {
127 .trp = 12,
128 .trh = 1,
129 .twp = 12,
130 .twh = 0,
131 .tcs = 24,
132 .twhr = 58,
133 .tcr_tar_trr = 0,
134 .twb = 116,
135 .trp_resp = 24,
136 .tadl = 24,
137 },
138 },
139};
140
141struct tegra_nand_platform p852_nand_data = {
142 .max_chips = 8,
143 .chip_parms = nand_chip_parms,
144 .nr_chip_parms = ARRAY_SIZE(nand_chip_parms),
145 .wp_gpio = TEGRA_GPIO_PC7,
146};
147
148static struct resource resources_nand[] = {
149 [0] = {
150 .start = INT_NANDFLASH,
151 .end = INT_NANDFLASH,
152 .flags = IORESOURCE_IRQ,
153 },
154};
155
156static struct platform_device p852_nand_device = {
157 .name = "tegra_nand",
158 .id = -1,
159 .num_resources = ARRAY_SIZE(resources_nand),
160 .resource = resources_nand,
161 .dev = {
162 .platform_data = &p852_nand_data,
163 },
164};
165
166unsigned int p852_uart_irqs[] = {
167 INT_UARTA,
168 INT_UARTB,
169 INT_UARTC,
170 INT_UARTD,
171};
172
173unsigned int p852_uart_bases[] = {
174 TEGRA_UARTA_BASE,
175 TEGRA_UARTB_BASE,
176 TEGRA_UARTC_BASE,
177 TEGRA_UARTD_BASE,
178};
179
180static struct platform_device *p852_spi_devices[] __initdata = {
181 &tegra_spi_device1,
182 &tegra_spi_device2,
183 &tegra_spi_device3,
184 &tegra_spi_device4,
185};
186
187static struct plat_serial8250_port debug_uart_platform_data[] = {
188 {
189 .flags = UPF_BOOT_AUTOCONF,
190 .iotype = UPIO_MEM,
191 .regshift = 2,
192 .uartclk = 216000000,
193 },
194 {
195 .flags = 0,
196 }
197};
198
199#define DEF_8250_PLATFORM_DATA(_base, _irq) { \
200 .flags = UPF_BOOT_AUTOCONF, \
201 .iotype = UPIO_MEM, \
202 .membase = IO_ADDRESS(_base), \
203 .mapbase = _base, \
204 .irq = _irq, \
205 .regshift = 2, \
206 .uartclk = 216000000, \
207}
208
209static struct plat_serial8250_port tegra_8250_uarta_platform_data[] = {
210 DEF_8250_PLATFORM_DATA(TEGRA_UARTA_BASE, INT_UARTA),
211 {
212 .flags = 0,
213 }
214};
215
216static struct plat_serial8250_port tegra_8250_uartb_platform_data[] = {
217 DEF_8250_PLATFORM_DATA(TEGRA_UARTB_BASE, INT_UARTB),
218 {
219 .flags = 0,
220 }
221};
222
223static struct plat_serial8250_port tegra_8250_uartc_platform_data[] = {
224 DEF_8250_PLATFORM_DATA(TEGRA_UARTC_BASE, INT_UARTC),
225 {
226 .flags = 0,
227 }
228};
229
230static struct plat_serial8250_port tegra_8250_uartd_platform_data[] = {
231 DEF_8250_PLATFORM_DATA(TEGRA_UARTD_BASE, INT_UARTD),
232 {
233 .flags = 0,
234 }
235};
236
237static struct plat_serial8250_port tegra_8250_uarte_platform_data[] = {
238 DEF_8250_PLATFORM_DATA(TEGRA_UARTE_BASE, INT_UARTE),
239 {
240 .flags = 0,
241 }
242};
243
244struct platform_device tegra_8250_uarta_device = {
245 .name = "serial8250",
246 .id = PLAT8250_DEV_PLATFORM,
247 .dev = {
248 .platform_data = tegra_8250_uarta_platform_data,
249 },
250};
251
252struct platform_device tegra_8250_uartb_device = {
253 .name = "serial8250",
254 .id = PLAT8250_DEV_PLATFORM1,
255 .dev = {
256 .platform_data = tegra_8250_uartb_platform_data,
257 },
258};
259
260struct platform_device tegra_8250_uartc_device = {
261 .name = "serial8250",
262 .id = PLAT8250_DEV_PLATFORM2,
263 .dev = {
264 .platform_data = tegra_8250_uartc_platform_data,
265 },
266};
267
268struct platform_device tegra_8250_uartd_device = {
269 .name = "serial8250",
270 .id = PLAT8250_DEV_FOURPORT,
271 .dev = {
272 .platform_data = tegra_8250_uartd_platform_data,
273 },
274};
275
276struct platform_device tegra_8250_uarte_device = {
277 .name = "serial8250",
278 .id = PLAT8250_DEV_ACCENT,
279 .dev = {
280 .platform_data = tegra_8250_uarte_platform_data,
281 },
282};
283
284static struct platform_device debug_uart = {
285 .name = "serial8250",
286 .id = PLAT8250_DEV_PLATFORM,
287 .dev = {
288 .platform_data = debug_uart_platform_data,
289 },
290};
291
292static struct tegra_utmip_config utmi_phy_config[] = {
293 [0] = {
294 .hssync_start_delay = 0,
295 .idle_wait_delay = 17,
296 .elastic_limit = 16,
297 .term_range_adj = 6,
298 .xcvr_setup = 15,
299 .xcvr_lsfslew = 2,
300 .xcvr_lsrslew = 2,
301 },
302 [1] = {
303 .hssync_start_delay = 0,
304 .idle_wait_delay = 17,
305 .elastic_limit = 16,
306 .term_range_adj = 6,
307 .xcvr_setup = 8,
308 .xcvr_lsfslew = 2,
309 .xcvr_lsrslew = 2,
310 },
311};
312
313static struct tegra_ulpi_config ulpi_usb2_config = {
314 .reset_gpio = TEGRA_GPIO_PI5,
315};
316
317static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
318 [0] = {
319 .phy_config = &utmi_phy_config[0],
320 .operating_mode = TEGRA_USB_HOST,
321 .power_down_on_bus_suspend = 0,
322 },
323 [1] = {
324 .phy_config = &ulpi_usb2_config,
325 .operating_mode = TEGRA_USB_HOST,
326 .power_down_on_bus_suspend = 0,
327 .phy_type = TEGRA_USB_PHY_TYPE_LINK_ULPI,
328 },
329 [2] = {
330 .phy_config = &utmi_phy_config[1],
331 .operating_mode = TEGRA_USB_HOST,
332 .power_down_on_bus_suspend = 0,
333 },
334};
335
336static void p852_usb_gpio_config(void)
337{
338 unsigned int usbeth_mux_gpio = 0, usb_ena_val;
339 unsigned int has_onboard_ethernet = 0;
340 unsigned int p852_eth_reset = TEGRA_GPIO_PD3;
341
342 switch (system_rev) {
343 case P852_SKU13_B00:
344 case P852_SKU23_B00:
345 case P852_SKU23_C01:
346 case P852_SKU8_B00:
347 case P852_SKU8_C01:
348 case P852_SKU9_B00:
349 case P852_SKU9_C01:
350 {
351 usbeth_mux_gpio = TEGRA_GPIO_PS3;
352 has_onboard_ethernet = 1;
353 usb_ena_val = 1;
354 }
355 break;
356 case P852_SKU5_B00:
357 case P852_SKU5_C01:
358 {
359 usb_ena_val = 1;
360 has_onboard_ethernet = 0;
361 }
362 break;
363 case P852_SKU1:
364 {
365 has_onboard_ethernet = 0;
366 usb_ena_val = 0;
367 strncpy(enable_usb3, "usb", sizeof(enable_usb3));
368 }
369 break;
370 case P852_SKU1_B00:
371 case P852_SKU1_C0X:
372 {
373 has_onboard_ethernet = 0;
374 usb_ena_val = 1;
375 strncpy(enable_usb3, "usb", sizeof(enable_usb3));
376 }
377 break;
378 default:
379 {
380 usbeth_mux_gpio = TEGRA_GPIO_PD4;
381 has_onboard_ethernet = 1;
382 usb_ena_val = 0;
383 }
384 }
385
386 if (has_onboard_ethernet) {
387 gpio_request_one(usbeth_mux_gpio, GPIOF_OUT_INIT_LOW,
388 "eth_ena");
389 tegra_gpio_enable(usbeth_mux_gpio);
390
391 /* eth reset */
392 gpio_request_one(p852_eth_reset, GPIOF_OUT_INIT_LOW,
393 "eth_reset");
394 tegra_gpio_enable(p852_eth_reset);
395 udelay(1);
396 gpio_direction_output(p852_eth_reset, 1);
397
398 if (!strcmp(enable_usb3, "eth"))
399 gpio_direction_output(usbeth_mux_gpio, 1);
400
401 /* exporting usbeth_mux_gpio */
402 gpio_export(usbeth_mux_gpio, true);
403 }
404
405 if (!strcmp(enable_usb3, "usb")) {
406 gpio_direction_output(TEGRA_GPIO_PB2, usb_ena_val);
407 gpio_direction_output(TEGRA_GPIO_PW1, usb_ena_val);
408 }
409}
410
411static struct platform_device *p852_uart_devices[] __initdata = {
412 &tegra_uarta_device,
413 &tegra_uartb_device,
414 &tegra_uartc_device,
415 &tegra_uartd_device,
416};
417
418static struct platform_device *p852_8250_uart_devices[] __initdata = {
419 &tegra_8250_uarta_device,
420 &tegra_8250_uartb_device,
421 &tegra_8250_uartc_device,
422 &tegra_8250_uartd_device,
423 &tegra_8250_uarte_device,
424};
425
426static struct platform_device tegra_itu656 = {
427 .name = "tegra_itu656",
428 .id = -1,
429};
430
431static struct platform_device *p852_devices[] __initdata = {
432 &tegra_gart_device,
433 &tegra_avp_device,
434 &tegra_itu656,
435};
436
437static struct tegra_nor_platform_data p852_nor_data = {
438 .flash = {
439 .map_name = "cfi_probe",
440 .width = 2,
441 },
442 .chip_parms = {
443 /* FIXME: use characterized clock freq */
444 .timing_default = {
445 .timing0 = 0xA0200253,
446 .timing1 = 0x00040406,
447 },
448 .timing_read = {
449 .timing0 = 0xA0200253,
450 .timing1 = 0x00000A00,
451 },
452 },
453};
454
455#ifdef CONFIG_TEGRA_SPI_I2S
456struct spi_board_info tegra_spi_i2s_device __initdata = {
457 .modalias = "spi_i2s_pcm",
458 .bus_num = 2,
459 .chip_select = 2,
460 .mode = SPI_MODE_0,
461 .max_speed_hz = 18000000,
462 .platform_data = NULL,
463 .irq = 0,
464};
465
466void __init p852_spi_i2s_init(void)
467{
468 struct tegra_spi_i2s_platform_data *pdata;
469
470 pdata = (struct tegra_spi_i2s_platform_data *)
471 tegra_spi_i2s_device.platform_data;
472 if (pdata->gpio_i2s.active_state) {
473 gpio_request_one(pdata->gpio_i2s.gpio_no, GPIOF_OUT_INIT_LOW,
474 "i2s_cpld_dir1");
475 } else {
476 gpio_request_one(pdata->gpio_i2s.gpio_no, GPIOF_OUT_INIT_HIGH,
477 "i2s_cpld_dir1");
478 }
479 tegra_gpio_enable(pdata->gpio_i2s.gpio_no);
480 if (pdata->gpio_spi.active_state) {
481 gpio_request_one(pdata->gpio_spi.gpio_no, GPIOF_OUT_INIT_LOW,
482 "spi_cpld_dir2");
483 } else {
484 gpio_request_one(pdata->gpio_spi.gpio_no, GPIOF_OUT_INIT_HIGH,
485 "spi_cpld_dir2");
486 }
487
488 tegra_gpio_enable(pdata->gpio_spi.gpio_no);
489 spi_register_board_info(&tegra_spi_i2s_device, 1);
490}
491#endif
492
493#if defined(CONFIG_SPI_TEGRA) && defined(CONFIG_SPI_SPIDEV)
494static struct spi_board_info tegra_spi_devices[] __initdata = {
495 {
496 .modalias = "spidev",
497 .bus_num = 0,
498 .chip_select = 0,
499 .mode = SPI_MODE_0,
500 .max_speed_hz = 18000000,
501 .platform_data = NULL,
502 .irq = 0,
503 },
504 {
505 .modalias = "spidev",
506 .bus_num = 1,
507 .chip_select = 1,
508 .mode = SPI_MODE_0,
509 .max_speed_hz = 18000000,
510 .platform_data = NULL,
511 .irq = 0,
512 },
513 {
514 .modalias = "spidev",
515 .bus_num = 3,
516 .chip_select = 1,
517 .mode = SPI_MODE_0,
518 .max_speed_hz = 18000000,
519 .platform_data = NULL,
520 .irq = 0,
521 },
522};
523
524static void __init p852_register_spidev(void)
525{
526 spi_register_board_info(tegra_spi_devices,
527 ARRAY_SIZE(tegra_spi_devices));
528}
529#else
530#define p852_register_spidev() do {} while (0)
531#endif
532
533static void __init p852_usb_init(void)
534{
535
536 p852_usb_gpio_config();
537 /*
538 if (system_rev == P852_SKU8)
539 {
540 platform_device_register(&tegra_udc_device);
541 }
542 else
543 */
544 {
545 tegra_ehci1_device.dev.platform_data = &tegra_ehci_pdata[0];
546 platform_device_register(&tegra_ehci1_device);
547 }
548
549 if (!(p852_sku_peripherals & P852_SKU_ULPI_DISABLE)) {
550 tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1];
551 platform_device_register(&tegra_ehci2_device);
552 }
553
554 tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata[2];
555 platform_device_register(&tegra_ehci3_device);
556}
557
558static void __init spi3_pingroup_clear_tristate(void)
559{
560 /* spi3 mosi, miso, cs, clk */
561 tegra_pinmux_set_tristate(TEGRA_PINGROUP_LSDI, TEGRA_TRI_NORMAL);
562 tegra_pinmux_set_tristate(TEGRA_PINGROUP_LSDA, TEGRA_TRI_NORMAL);
563 tegra_pinmux_set_tristate(TEGRA_PINGROUP_LCSN, TEGRA_TRI_NORMAL);
564 tegra_pinmux_set_tristate(TEGRA_PINGROUP_LSCK, TEGRA_TRI_NORMAL);
565}
566
567static void __init p852_spi_init(void)
568{
569 if (p852_sku_peripherals & P852_SKU_SPI_ENABLE) {
570 int i = 0;
571 unsigned int spi_config = 0;
572 unsigned int spi3_config =
573 (p852_spi_peripherals >> P852_SPI3_SHIFT) & P852_SPI_MASK;
574
575 for (i = 0; i < P852_MAX_SPI; i++) {
576 spi_config =
577 (p852_spi_peripherals >> (P852_SPI_SHIFT * i)) &
578 P852_SPI_MASK;
579 if (spi_config & P852_SPI_ENABLE) {
580 if (spi_config & P852_SPI_SLAVE)
581 p852_spi_devices[i]->name =
582 "tegra_spi_slave";
583 platform_device_register(p852_spi_devices[i]);
584 }
585 }
586 /* Default spi3 pingroups are in tristate */
587 if (spi3_config & P852_SPI_ENABLE)
588 spi3_pingroup_clear_tristate();
589 }
590}
591
592static void __init p852_uart_init(void)
593{
594 if (p852_sku_peripherals & P852_SKU_UART_ENABLE) {
595 int i = 0;
596 unsigned int uart_config = 0, uart8250Id = 0;
597 int debug_console = -1;
598
599 /* register the debug console as the first serial console */
600 for (i = 0; i < P852_MAX_UART; i++) {
601 uart_config =
602 (p852_uart_peripherals >> (P852_UART_SHIFT * i));
603 if (uart_config & P852_UART_DB) {
604 debug_console = i;
605 debug_uart_platform_data[0].membase =
606 IO_ADDRESS(p852_uart_bases[i]);
607 debug_uart_platform_data[0].mapbase =
608 p852_uart_bases[i];
609 debug_uart_platform_data[0].irq =
610 p852_uart_irqs[i];
611 uart8250Id++;
612 platform_device_register(&debug_uart);
613 break;
614 }
615 }
616
617 /* register remaining UARTS */
618 for (i = 0; i < P852_MAX_UART; i++) {
619 uart_config =
620 (p852_uart_peripherals >> (P852_UART_SHIFT * i)) &
621 P852_UART_MASK;
622 if ((uart_config & P852_UART_ENABLE)
623 && i != debug_console) {
624 if (uart_config & P852_UART_HS) {
625 platform_device_register
626 (p852_uart_devices[i]);
627 } else {
628 p852_8250_uart_devices[i]->id =
629 uart8250Id++;
630 platform_device_register
631 (p852_8250_uart_devices[i]);
632 }
633 }
634 }
635 }
636}
637
638static struct platform_device generic_codec_driver = {
639 .name = "generic-dit",
640};
641
642static void __init p852_flash_init(void)
643{
644 if (p852_sku_peripherals & P852_SKU_NAND_ENABLE)
645 platform_device_register(&p852_nand_device);
646
647 if (p852_sku_peripherals & P852_SKU_NOR_ENABLE) {
648 tegra_nor_device.resource[2].end = TEGRA_NOR_FLASH_BASE + SZ_64M - 1;
649 tegra_nor_device.dev.platform_data = &p852_nor_data;
650 platform_device_register(&tegra_nor_device);
651 }
652}
653
654void __init p852_common_init(void)
655{
656 tegra_clk_init_from_table(p852_clk_init_table);
657
658 p852_pinmux_init();
659
660 p852_i2c_init();
661
662 p852_regulator_init();
663
664 p852_uart_init();
665
666 p852_flash_init();
667
668 platform_add_devices(p852_devices, ARRAY_SIZE(p852_devices));
669
670 //p852_panel_init();
671
672 p852_spi_init();
673
674 p852_register_spidev();
675
676 p852_usb_init();
677
678 p852_sdhci_init();
679
680 p852_gpio_init();
681}
682
683void __init tegra_p852_init(void)
684{
685 switch (system_rev) {
686 case P852_SKU3:
687 p852_sku3_init();
688 break;
689 case P852_SKU13:
690 p852_sku13_init();
691 break;
692 case P852_SKU13_B00:
693 case P852_SKU13_C01:
694 p852_sku13_b00_init();
695 break;
696 case P852_SKU23:
697 p852_sku23_init();
698 break;
699 case P852_SKU23_B00:
700 p852_sku23_b00_init();
701 break;
702 case P852_SKU23_C01:
703 p852_sku23_c01_init();
704 break;
705 case P852_SKU1:
706 p852_sku1_init();
707 break;
708 case P852_SKU11:
709 case P852_SKU1_B00:
710 p852_sku1_b00_init();
711 break;
712 case P852_SKU1_C0X:
713 p852_sku1_c0x_init();
714 break;
715 case P852_SKU5_B00:
716 p852_sku5_b00_init();
717 break;
718 case P852_SKU5_C01:
719 p852_sku5_c01_init();
720 break;
721 case P852_SKU8_B00:
722 p852_sku8_b00_init();
723 break;
724 case P852_SKU8_C01:
725 p852_sku8_c00_init();
726 break;
727 case P852_SKU9_B00:
728 p852_sku9_b00_init();
729 break;
730 case P852_SKU9_C01:
731 p852_sku9_c00_init();
732 break;
733 default:
734 printk(KERN_ERR "Unknow Board Revision\n");
735 break;
736 }
737}
738
739static void __init tegra_p852_reserve(void)
740{
741 switch (system_rev) {
742 case P852_SKU3:
743 case P852_SKU5_B00:
744 case P852_SKU5_C01:
745 case P852_SKU9_B00:
746 case P852_SKU9_C01:
747 tegra_reserve(SZ_64M + SZ_16M, SZ_8M, 0);
748 break;
749 default:
750 tegra_reserve(SZ_128M, SZ_8M, 0);
751 break;
752 }
753}
754
755MACHINE_START(P852, "Tegra P852")
756 .boot_params = 0x00000100,
757 .map_io = tegra_map_common_io,
758 .reserve = tegra_p852_reserve,
759 .init_early = tegra_init_early,
760 .init_irq = tegra_init_irq,
761 .timer = &tegra_timer,
762 .init_machine = tegra_p852_init,
763MACHINE_END
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-20 11:32:36 -0400