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-rw-r--r--arch/arm/mach-tegra/include/mach/arb_sema.h35
-rw-r--r--arch/arm/mach-tegra/include/mach/audio.h57
-rw-r--r--arch/arm/mach-tegra/include/mach/csi.h40
-rw-r--r--arch/arm/mach-tegra/include/mach/dc.h570
-rw-r--r--arch/arm/mach-tegra/include/mach/debug-macro.S35
-rw-r--r--arch/arm/mach-tegra/include/mach/delay.h41
-rw-r--r--arch/arm/mach-tegra/include/mach/dma.h202
-rw-r--r--arch/arm/mach-tegra/include/mach/edp.h80
-rw-r--r--arch/arm/mach-tegra/include/mach/entry-macro.S37
-rw-r--r--arch/arm/mach-tegra/include/mach/fb.h61
-rw-r--r--arch/arm/mach-tegra/include/mach/fiq.h25
-rw-r--r--arch/arm/mach-tegra/include/mach/gpio.h80
-rw-r--r--arch/arm/mach-tegra/include/mach/gpufuse.h19
-rw-r--r--arch/arm/mach-tegra/include/mach/hardware.h50
-rw-r--r--arch/arm/mach-tegra/include/mach/hdmi-audio.h46
-rw-r--r--arch/arm/mach-tegra/include/mach/i2s.h316
-rw-r--r--arch/arm/mach-tegra/include/mach/io.h136
-rw-r--r--arch/arm/mach-tegra/include/mach/io_dpd.h40
-rw-r--r--arch/arm/mach-tegra/include/mach/iomap.h523
-rw-r--r--arch/arm/mach-tegra/include/mach/iovmm.h323
-rw-r--r--arch/arm/mach-tegra/include/mach/irqs.h391
-rw-r--r--arch/arm/mach-tegra/include/mach/kbc.h86
-rw-r--r--arch/arm/mach-tegra/include/mach/kfuse.h20
-rw-r--r--arch/arm/mach-tegra/include/mach/latency_allowance.h121
-rw-r--r--arch/arm/mach-tegra/include/mach/legacy_irq.h23
-rw-r--r--arch/arm/mach-tegra/include/mach/mc.h109
-rw-r--r--arch/arm/mach-tegra/include/mach/memory.h42
-rw-r--r--arch/arm/mach-tegra/include/mach/nand.h55
-rw-r--r--arch/arm/mach-tegra/include/mach/nvmap.h158
-rw-r--r--arch/arm/mach-tegra/include/mach/pci.h38
-rw-r--r--arch/arm/mach-tegra/include/mach/pinmux-t2.h184
-rw-r--r--arch/arm/mach-tegra/include/mach/pinmux-t3.h321
-rw-r--r--arch/arm/mach-tegra/include/mach/pinmux.h375
-rw-r--r--arch/arm/mach-tegra/include/mach/sdhci.h35
-rw-r--r--arch/arm/mach-tegra/include/mach/smmu.h63
-rw-r--r--arch/arm/mach-tegra/include/mach/spdif.h392
-rw-r--r--arch/arm/mach-tegra/include/mach/spi.h42
-rw-r--r--arch/arm/mach-tegra/include/mach/system.h34
-rw-r--r--arch/arm/mach-tegra/include/mach/tegra-bb-power.h61
-rw-r--r--arch/arm/mach-tegra/include/mach/tegra_aic326x_pdata.h39
-rw-r--r--arch/arm/mach-tegra/include/mach/tegra_asoc_pdata.h36
-rw-r--r--arch/arm/mach-tegra/include/mach/tegra_dc_ext.h77
-rw-r--r--arch/arm/mach-tegra/include/mach/tegra_fb.h27
-rw-r--r--arch/arm/mach-tegra/include/mach/tegra_fiq_debugger.h30
-rw-r--r--arch/arm/mach-tegra/include/mach/tegra_fuse.h27
-rw-r--r--arch/arm/mach-tegra/include/mach/tegra_max98088_pdata.h35
-rw-r--r--arch/arm/mach-tegra/include/mach/tegra_odm_fuses.h107
-rw-r--r--arch/arm/mach-tegra/include/mach/tegra_p1852_pdata.h45
-rw-r--r--arch/arm/mach-tegra/include/mach/tegra_rt5640_pdata.h25
-rw-r--r--arch/arm/mach-tegra/include/mach/tegra_smmu.h24
-rw-r--r--arch/arm/mach-tegra/include/mach/tegra_usb_modem_power.h47
-rw-r--r--arch/arm/mach-tegra/include/mach/tegra_wm8753_pdata.h24
-rw-r--r--arch/arm/mach-tegra/include/mach/tegra_wm8903_pdata.h23
-rw-r--r--arch/arm/mach-tegra/include/mach/thermal.h62
-rw-r--r--arch/arm/mach-tegra/include/mach/tsensor.h48
-rw-r--r--arch/arm/mach-tegra/include/mach/usb_phy.h166
-rw-r--r--arch/arm/mach-tegra/include/mach/vmalloc.h28
-rw-r--r--arch/arm/mach-tegra/include/mach/w1.h84
58 files changed, 6220 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/include/mach/arb_sema.h b/arch/arm/mach-tegra/include/mach/arb_sema.h
new file mode 100644
index 00000000000..9283f079cf6
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/arb_sema.h
@@ -0,0 +1,35 @@
1/*
2 * arch/arm/mach-tegra/include/mach/arb_sema.h
3 *
4 * Hardware arbitration semaphore interface
5 *
6 * Copyright (c) 2010, NVIDIA Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
21 */
22
23#ifndef __MACH_TEGRA_ARB_SEMA_H
24#define __MACH_TEGRA_ARB_SEMA_H
25
26enum tegra_arb_module {
27 TEGRA_ARB_BSEV = 0,
28 TEGRA_ARB_BSEA,
29};
30
31int tegra_arb_mutex_lock_timeout(enum tegra_arb_module lock, int msecs);
32
33int tegra_arb_mutex_unlock(enum tegra_arb_module lock);
34
35#endif
diff --git a/arch/arm/mach-tegra/include/mach/audio.h b/arch/arm/mach-tegra/include/mach/audio.h
new file mode 100644
index 00000000000..5950ececae0
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/audio.h
@@ -0,0 +1,57 @@
1/*
2 * arch/arm/mach-tegra/include/mach/audio.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Iliyan Malchev <malchev@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#ifndef __ARCH_ARM_MACH_TEGRA_AUDIO_H
21#define __ARCH_ARM_MACH_TEGRA_AUDIO_H
22
23#include <linux/kernel.h>
24#include <linux/types.h>
25#include <mach/i2s.h>
26
27#define FIFO1 0
28#define FIFO2 1
29
30/* FIXME: this is not enforced by the hardware. */
31#define I2S_FIFO_TX FIFO1
32#define I2S_FIFO_RX FIFO2
33
34#define TEGRA_AUDIO_ENABLE_TX 1
35#define TEGRA_AUDIO_ENABLE_RX 2
36
37struct tegra_audio_platform_data {
38 bool i2s_master;
39 bool dsp_master;
40 int i2s_master_clk; /* When I2S mode and master, the framesync rate. */
41 int dsp_master_clk; /* When DSP mode and master, the framesync rate. */
42 bool dma_on;
43 unsigned long i2s_clk_rate;
44 const char *dap_clk;
45 const char *audio_sync_clk;
46
47 int mode; /* I2S, LJM, RJM, etc. */
48 int fifo_fmt;
49 int bit_size;
50 int i2s_bus_width; /* 32-bit for 16-bit packed I2S */
51 int dsp_bus_width; /* 16-bit for DSP data format */
52 int mask; /* enable tx and rx? */
53 bool stereo_capture; /* True if hardware supports stereo */
54 void *driver_data;
55};
56
57#endif /* __ARCH_ARM_MACH_TEGRA_AUDIO_H */
diff --git a/arch/arm/mach-tegra/include/mach/csi.h b/arch/arm/mach-tegra/include/mach/csi.h
new file mode 100644
index 00000000000..575de6fb497
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/csi.h
@@ -0,0 +1,40 @@
1/*
2 * arch/arm/mach-tegra/include/mach/csi.h
3 *
4 * Copyright (C) 2010-2011 NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef __MACH_TEGRA_CSI_H
18#define __MACH_TEGRA_CSI_H
19
20#define CSI_CILA_MIPI_CAL_CONFIG_0 0x22a
21#define MIPI_CAL_TERMOSA(x) (((x) & 0x1f) << 0)
22
23#define CSI_CILB_MIPI_CAL_CONFIG_0 0x22b
24#define MIPI_CAL_TERMOSB(x) (((x) & 0x1f) << 0)
25
26#define CSI_CIL_PAD_CONFIG 0x229
27#define PAD_CIL_PDVREG(x) (((x) & 0x01) << 1)
28
29#define CSI_DSI_MIPI_CAL_CONFIG 0x234
30#define MIPI_CAL_HSPDOSD(x) (((x) & 0x1f) << 16)
31#define MIPI_CAL_HSPUOSD(x) (((x) & 0x1f) << 8)
32
33#define CSI_MIPIBIAS_PAD_CONFIG 0x235
34#define PAD_DRIV_DN_REF(x) (((x) & 0x7) << 16)
35#define PAD_DRIV_UP_REF(x) (((x) & 0x7) << 8)
36
37int tegra_vi_csi_readl(u32 offset, u32 *val);
38int tegra_vi_csi_writel(u32 value, u32 offset);
39
40#endif
diff --git a/arch/arm/mach-tegra/include/mach/dc.h b/arch/arm/mach-tegra/include/mach/dc.h
new file mode 100644
index 00000000000..a5f7210f2b2
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/dc.h
@@ -0,0 +1,570 @@
1/*
2 * arch/arm/mach-tegra/include/mach/dc.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 *
9 * Copyright (C) 2010-2011 NVIDIA Corporation
10 *
11 * This software is licensed under the terms of the GNU General Public
12 * License version 2, as published by the Free Software Foundation, and
13 * may be copied, distributed, and modified under those terms.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 */
21
22#ifndef __MACH_TEGRA_DC_H
23#define __MACH_TEGRA_DC_H
24
25#include <linux/pm.h>
26#include <linux/types.h>
27#include <drm/drm_fixed.h>
28
29#define TEGRA_MAX_DC 2
30#define DC_N_WINDOWS 3
31
32
33/* DSI pixel data format */
34enum {
35 TEGRA_DSI_PIXEL_FORMAT_16BIT_P,
36 TEGRA_DSI_PIXEL_FORMAT_18BIT_P,
37 TEGRA_DSI_PIXEL_FORMAT_18BIT_NP,
38 TEGRA_DSI_PIXEL_FORMAT_24BIT_P,
39};
40
41/* DSI virtual channel number */
42enum {
43 TEGRA_DSI_VIRTUAL_CHANNEL_0,
44 TEGRA_DSI_VIRTUAL_CHANNEL_1,
45 TEGRA_DSI_VIRTUAL_CHANNEL_2,
46 TEGRA_DSI_VIRTUAL_CHANNEL_3,
47};
48
49/* DSI transmit method for video data */
50enum {
51 TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE,
52 TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE,
53};
54
55/* DSI HS clock mode */
56enum {
57 TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS,
58 TEGRA_DSI_VIDEO_CLOCK_TX_ONLY,
59};
60
61/* DSI burst mode setting in video mode. Each mode is assigned with a
62 * fixed value. The rationale behind this is to avoid change of these
63 * values, since the calculation of dsi clock depends on them. */
64enum {
65 TEGRA_DSI_VIDEO_NONE_BURST_MODE = 0,
66 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END = 1,
67 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED = 2,
68 TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED = 3,
69 TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED = 4,
70 TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED = 5,
71 TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED = 6,
72};
73
74enum {
75 TEGRA_DSI_PACKET_CMD,
76 TEGRA_DSI_DELAY_MS,
77};
78
79struct tegra_dsi_cmd {
80 u8 cmd_type;
81 u8 data_id;
82 union {
83 u16 data_len;
84 u16 delay_ms;
85 struct {
86 u8 data0;
87 u8 data1;
88 } sp;
89 } sp_len_dly;
90 u8 *pdata;
91};
92
93#define DSI_CMD_SHORT(di, p0, p1) { \
94 .cmd_type = TEGRA_DSI_PACKET_CMD, \
95 .data_id = di, \
96 .sp_len_dly.sp.data0 = p0, \
97 .sp_len_dly.sp.data1 = p1, \
98 }
99#define DSI_DLY_MS(ms) { \
100 .cmd_type = TEGRA_DSI_DELAY_MS, \
101 .sp_len_dly.delay_ms = ms, \
102 }
103
104#define DSI_CMD_LONG(di, ptr) { \
105 .cmd_type = TEGRA_DSI_PACKET_CMD, \
106 .data_id = di, \
107 .sp_len_dly.data_len = ARRAY_SIZE(ptr), \
108 .pdata = ptr, \
109 }
110
111struct dsi_phy_timing_ns {
112 u16 t_hsdexit_ns;
113 u16 t_hstrail_ns;
114 u16 t_datzero_ns;
115 u16 t_hsprepare_ns;
116
117 u16 t_clktrail_ns;
118 u16 t_clkpost_ns;
119 u16 t_clkzero_ns;
120 u16 t_tlpx_ns;
121
122 u16 t_clkprepare_ns;
123 u16 t_clkpre_ns;
124 u16 t_wakeup_ns;
125
126 u16 t_taget_ns;
127 u16 t_tasure_ns;
128 u16 t_tago_ns;
129};
130
131struct tegra_dsi_out {
132 u8 n_data_lanes; /* required */
133 u8 pixel_format; /* required */
134 u8 refresh_rate; /* required */
135 u8 rated_refresh_rate;
136 u8 panel_reset; /* required */
137 u8 virtual_channel; /* required */
138 u8 dsi_instance;
139 u8 chip_id;
140 u8 chip_rev;
141
142 bool panel_has_frame_buffer; /* required*/
143
144 struct tegra_dsi_cmd *dsi_init_cmd; /* required */
145 u16 n_init_cmd; /* required */
146
147 struct tegra_dsi_cmd *dsi_early_suspend_cmd;
148 u16 n_early_suspend_cmd;
149
150 struct tegra_dsi_cmd *dsi_late_resume_cmd;
151 u16 n_late_resume_cmd;
152
153 struct tegra_dsi_cmd *dsi_suspend_cmd; /* required */
154 u16 n_suspend_cmd; /* required */
155
156 u8 video_data_type; /* required */
157 u8 video_clock_mode;
158 u8 video_burst_mode;
159
160 u16 panel_buffer_size_byte;
161 u16 panel_reset_timeout_msec;
162
163 bool hs_cmd_mode_supported;
164 bool hs_cmd_mode_on_blank_supported;
165 bool enable_hs_clock_on_lp_cmd_mode;
166 bool no_pkt_seq_eot; /* 1st generation panel may not
167 * support eot. Don't set it for
168 * most panels. */
169 bool te_polarity_low;
170 bool power_saving_suspend;
171
172 u32 max_panel_freq_khz;
173 u32 lp_cmd_mode_freq_khz;
174 u32 lp_read_cmd_mode_freq_khz;
175 u32 hs_clk_in_lp_cmd_mode_freq_khz;
176 u32 burst_mode_freq_khz;
177
178 struct dsi_phy_timing_ns phy_timing;
179};
180
181enum {
182 TEGRA_DC_STEREO_MODE_2D,
183 TEGRA_DC_STEREO_MODE_3D
184};
185
186enum {
187 TEGRA_DC_STEREO_LANDSCAPE,
188 TEGRA_DC_STEREO_PORTRAIT
189};
190
191struct tegra_stereo_out {
192 int mode_2d_3d;
193 int orientation;
194
195 void (*set_mode)(int mode);
196 void (*set_orientation)(int orientation);
197};
198
199struct tegra_dc_mode {
200 int pclk;
201 int rated_pclk;
202 int h_ref_to_sync;
203 int v_ref_to_sync;
204 int h_sync_width;
205 int v_sync_width;
206 int h_back_porch;
207 int v_back_porch;
208 int h_active;
209 int v_active;
210 int h_front_porch;
211 int v_front_porch;
212 int stereo_mode;
213 u32 flags;
214};
215
216#define TEGRA_DC_MODE_FLAG_NEG_V_SYNC (1 << 0)
217#define TEGRA_DC_MODE_FLAG_NEG_H_SYNC (1 << 1)
218
219enum {
220 TEGRA_DC_OUT_RGB,
221 TEGRA_DC_OUT_HDMI,
222 TEGRA_DC_OUT_DSI,
223};
224
225struct tegra_dc_out_pin {
226 int name;
227 int pol;
228};
229
230enum {
231 TEGRA_DC_OUT_PIN_DATA_ENABLE,
232 TEGRA_DC_OUT_PIN_H_SYNC,
233 TEGRA_DC_OUT_PIN_V_SYNC,
234 TEGRA_DC_OUT_PIN_PIXEL_CLOCK,
235};
236
237enum {
238 TEGRA_DC_OUT_PIN_POL_LOW,
239 TEGRA_DC_OUT_PIN_POL_HIGH,
240};
241
242enum {
243 TEGRA_DC_DISABLE_DITHER = 1,
244 TEGRA_DC_ORDERED_DITHER,
245 TEGRA_DC_ERRDIFF_DITHER,
246};
247
248typedef u8 tegra_dc_bl_output[256];
249typedef u8 *p_tegra_dc_bl_output;
250
251struct tegra_dc_sd_blp {
252 u16 time_constant;
253 u8 step;
254};
255
256struct tegra_dc_sd_fc {
257 u8 time_limit;
258 u8 threshold;
259};
260
261struct tegra_dc_sd_rgb {
262 u8 r;
263 u8 g;
264 u8 b;
265};
266
267struct tegra_dc_sd_agg_priorities {
268 u8 pri_lvl;
269 u8 agg[4];
270};
271
272struct tegra_dc_sd_settings {
273 unsigned enable;
274 bool use_auto_pwm;
275 u8 hw_update_delay;
276 u8 aggressiveness;
277 short bin_width;
278 u8 phase_in_settings;
279 u8 phase_in_adjustments;
280 u8 cmd;
281 u8 final_agg;
282 u16 cur_agg_step;
283 u16 phase_settings_step;
284 u16 phase_adj_step;
285 u16 num_phase_in_steps;
286
287 struct tegra_dc_sd_agg_priorities agg_priorities;
288
289 bool use_vid_luma;
290 struct tegra_dc_sd_rgb coeff;
291
292 struct tegra_dc_sd_fc fc;
293 struct tegra_dc_sd_blp blp;
294 u8 bltf[4][4][4];
295 struct tegra_dc_sd_rgb lut[4][9];
296
297 atomic_t *sd_brightness;
298 struct platform_device *bl_device;
299};
300
301enum {
302 NO_CMD = 0x0,
303 ENABLE = 0x1,
304 DISABLE = 0x2,
305 PHASE_IN = 0x4,
306 AGG_CHG = 0x8,
307};
308
309enum {
310 TEGRA_PIN_OUT_CONFIG_SEL_LHP0_LD21,
311 TEGRA_PIN_OUT_CONFIG_SEL_LHP1_LD18,
312 TEGRA_PIN_OUT_CONFIG_SEL_LHP2_LD19,
313 TEGRA_PIN_OUT_CONFIG_SEL_LVP0_LVP0_Out,
314 TEGRA_PIN_OUT_CONFIG_SEL_LVP1_LD20,
315
316 TEGRA_PIN_OUT_CONFIG_SEL_LM1_M1,
317 TEGRA_PIN_OUT_CONFIG_SEL_LM1_LD21,
318 TEGRA_PIN_OUT_CONFIG_SEL_LM1_PM1,
319
320 TEGRA_PIN_OUT_CONFIG_SEL_LDI_LD22,
321 TEGRA_PIN_OUT_CONFIG_SEL_LPP_LD23,
322 TEGRA_PIN_OUT_CONFIG_SEL_LDC_SDC,
323 TEGRA_PIN_OUT_CONFIG_SEL_LSPI_DE,
324};
325
326struct tegra_dc_out {
327 int type;
328 unsigned flags;
329
330 /* size in mm */
331 unsigned h_size;
332 unsigned v_size;
333
334 int dcc_bus;
335 int hotplug_gpio;
336 const char *parent_clk;
337 const char *parent_clk_backup;
338
339 unsigned max_pixclock;
340 unsigned order;
341 unsigned align;
342 unsigned depth;
343 unsigned dither;
344
345 struct tegra_dc_mode *modes;
346 int n_modes;
347
348 struct tegra_dsi_out *dsi;
349 struct tegra_stereo_out *stereo;
350
351 unsigned height; /* mm */
352 unsigned width; /* mm */
353
354 struct tegra_dc_out_pin *out_pins;
355 unsigned n_out_pins;
356
357 struct tegra_dc_sd_settings *sd_settings;
358
359 u8 *out_sel_configs;
360 unsigned n_out_sel_configs;
361
362 int (*enable)(void);
363 int (*postpoweron)(void);
364 int (*disable)(void);
365
366 int (*hotplug_init)(void);
367 int (*postsuspend)(void);
368};
369
370/* bits for tegra_dc_out.flags */
371#define TEGRA_DC_OUT_HOTPLUG_HIGH (0 << 1)
372#define TEGRA_DC_OUT_HOTPLUG_LOW (1 << 1)
373#define TEGRA_DC_OUT_HOTPLUG_MASK (1 << 1)
374#define TEGRA_DC_OUT_NVHDCP_POLICY_ALWAYS_ON (0 << 2)
375#define TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND (1 << 2)
376#define TEGRA_DC_OUT_NVHDCP_POLICY_MASK (1 << 2)
377#define TEGRA_DC_OUT_CONTINUOUS_MODE (0 << 3)
378#define TEGRA_DC_OUT_ONE_SHOT_MODE (1 << 3)
379#define TEGRA_DC_OUT_N_SHOT_MODE (1 << 4)
380
381#define TEGRA_DC_ALIGN_MSB 0
382#define TEGRA_DC_ALIGN_LSB 1
383
384#define TEGRA_DC_ORDER_RED_BLUE 0
385#define TEGRA_DC_ORDER_BLUE_RED 1
386
387struct tegra_dc;
388struct nvmap_handle_ref;
389
390struct tegra_dc_csc {
391 unsigned short yof;
392 unsigned short kyrgb;
393 unsigned short kur;
394 unsigned short kvr;
395 unsigned short kug;
396 unsigned short kvg;
397 unsigned short kub;
398 unsigned short kvb;
399};
400
401/* palette lookup table */
402struct tegra_dc_lut {
403 u8 r[256];
404 u8 g[256];
405 u8 b[256];
406};
407
408struct tegra_dc_win {
409 u8 idx;
410 u8 fmt;
411 u8 ppflags; /* see TEGRA_WIN_PPFLAG* */
412 u32 flags;
413
414 void *virt_addr;
415 dma_addr_t phys_addr;
416 dma_addr_t phys_addr_u;
417 dma_addr_t phys_addr_v;
418 unsigned stride;
419 unsigned stride_uv;
420 fixed20_12 x;
421 fixed20_12 y;
422 fixed20_12 w;
423 fixed20_12 h;
424 unsigned out_x;
425 unsigned out_y;
426 unsigned out_w;
427 unsigned out_h;
428 unsigned z;
429
430 struct tegra_dc_csc csc;
431
432 int dirty;
433 int underflows;
434 struct tegra_dc *dc;
435
436 struct nvmap_handle_ref *cur_handle;
437 unsigned bandwidth;
438 unsigned new_bandwidth;
439 struct tegra_dc_lut lut;
440};
441
442#define TEGRA_WIN_PPFLAG_CP_ENABLE (1 << 0) /* enable RGB color lut */
443#define TEGRA_WIN_PPFLAG_CP_FBOVERRIDE (1 << 1) /* override fbdev color lut */
444
445#define TEGRA_WIN_FLAG_ENABLED (1 << 0)
446#define TEGRA_WIN_FLAG_BLEND_PREMULT (1 << 1)
447#define TEGRA_WIN_FLAG_BLEND_COVERAGE (1 << 2)
448#define TEGRA_WIN_FLAG_INVERT_H (1 << 3)
449#define TEGRA_WIN_FLAG_INVERT_V (1 << 4)
450#define TEGRA_WIN_FLAG_TILED (1 << 5)
451#define TEGRA_WIN_FLAG_H_FILTER (1 << 6)
452#define TEGRA_WIN_FLAG_V_FILTER (1 << 7)
453
454
455#define TEGRA_WIN_BLEND_FLAGS_MASK \
456 (TEGRA_WIN_FLAG_BLEND_PREMULT | TEGRA_WIN_FLAG_BLEND_COVERAGE)
457
458/* Note: These are the actual values written to the DC_WIN_COLOR_DEPTH register
459 * and may change in new tegra architectures.
460 */
461#define TEGRA_WIN_FMT_P1 0
462#define TEGRA_WIN_FMT_P2 1
463#define TEGRA_WIN_FMT_P4 2
464#define TEGRA_WIN_FMT_P8 3
465#define TEGRA_WIN_FMT_B4G4R4A4 4
466#define TEGRA_WIN_FMT_B5G5R5A 5
467#define TEGRA_WIN_FMT_B5G6R5 6
468#define TEGRA_WIN_FMT_AB5G5R5 7
469#define TEGRA_WIN_FMT_B8G8R8A8 12
470#define TEGRA_WIN_FMT_R8G8B8A8 13
471#define TEGRA_WIN_FMT_B6x2G6x2R6x2A8 14
472#define TEGRA_WIN_FMT_R6x2G6x2B6x2A8 15
473#define TEGRA_WIN_FMT_YCbCr422 16
474#define TEGRA_WIN_FMT_YUV422 17
475#define TEGRA_WIN_FMT_YCbCr420P 18
476#define TEGRA_WIN_FMT_YUV420P 19
477#define TEGRA_WIN_FMT_YCbCr422P 20
478#define TEGRA_WIN_FMT_YUV422P 21
479#define TEGRA_WIN_FMT_YCbCr422R 22
480#define TEGRA_WIN_FMT_YUV422R 23
481#define TEGRA_WIN_FMT_YCbCr422RA 24
482#define TEGRA_WIN_FMT_YUV422RA 25
483
484struct tegra_fb_data {
485 int win;
486
487 int xres;
488 int yres;
489 int bits_per_pixel; /* -1 means autodetect */
490
491 unsigned long flags;
492};
493
494#define TEGRA_FB_FLIP_ON_PROBE (1 << 0)
495
496struct tegra_dc_platform_data {
497 unsigned long flags;
498 unsigned long emc_clk_rate;
499 struct tegra_dc_out *default_out;
500 struct tegra_fb_data *fb;
501};
502
503#define TEGRA_DC_FLAG_ENABLED (1 << 0)
504
505struct tegra_dc *tegra_dc_get_dc(unsigned idx);
506struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win);
507bool tegra_dc_get_connected(struct tegra_dc *);
508
509void tegra_dc_blank(struct tegra_dc *dc);
510
511void tegra_dc_enable(struct tegra_dc *dc);
512void tegra_dc_disable(struct tegra_dc *dc);
513
514u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i);
515u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i);
516void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val);
517
518/* tegra_dc_update_windows and tegra_dc_sync_windows do not support windows
519 * with differenct dcs in one call
520 */
521int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n);
522int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n);
523
524int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode);
525struct fb_videomode;
526int tegra_dc_set_fb_mode(struct tegra_dc *dc, const struct fb_videomode *fbmode,
527 bool stereo_mode);
528
529unsigned tegra_dc_get_out_height(const struct tegra_dc *dc);
530unsigned tegra_dc_get_out_width(const struct tegra_dc *dc);
531unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc);
532
533/* PM0 and PM1 signal control */
534#define TEGRA_PWM_PM0 0
535#define TEGRA_PWM_PM1 1
536
537struct tegra_dc_pwm_params {
538 int which_pwm;
539 void (*switch_to_sfio)(int);
540 int gpio_conf_to_sfio;
541 unsigned int period;
542 unsigned int clk_div;
543 unsigned int clk_select;
544 unsigned int duty_cycle;
545};
546
547void tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg);
548
549int tegra_dsi_send_panel_short_cmd(struct tegra_dc *dc, u8 *pdata, u8 data_len);
550void tegra_dc_host_trigger(struct tegra_dc *dc);
551
552int tegra_dc_update_csc(struct tegra_dc *dc, int win_index);
553
554int tegra_dc_update_lut(struct tegra_dc *dc, int win_index, int fboveride);
555
556/*
557 * In order to get a dc's current EDID, first call tegra_dc_get_edid() from an
558 * interruptible context. The returned value (if non-NULL) points to a
559 * snapshot of the current state; after copying data from it, call
560 * tegra_dc_put_edid() on that pointer. Do not dereference anything through
561 * that pointer after calling tegra_dc_put_edid().
562 */
563struct tegra_dc_edid {
564 size_t len;
565 u8 buf[0];
566};
567struct tegra_dc_edid *tegra_dc_get_edid(struct tegra_dc *dc);
568void tegra_dc_put_edid(struct tegra_dc_edid *edid);
569
570#endif
diff --git a/arch/arm/mach-tegra/include/mach/debug-macro.S b/arch/arm/mach-tegra/include/mach/debug-macro.S
new file mode 100644
index 00000000000..e0ebe65c165
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/debug-macro.S
@@ -0,0 +1,35 @@
1/*
2 * arch/arm/mach-tegra/include/mach/debug-macro.S
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 * Erik Gilling <konkers@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#include <mach/io.h>
22#include <mach/iomap.h>
23
24 .macro addruart, rp, rv
25 ldr \rp, =IO_APB_PHYS @ physical
26 ldr \rv, =IO_APB_VIRT @ virtual
27 orr \rp, \rp, #(TEGRA_DEBUG_UART_BASE & 0xFF)
28 orr \rp, \rp, #(TEGRA_DEBUG_UART_BASE & 0xFF00)
29 orr \rv, \rv, #(TEGRA_DEBUG_UART_BASE & 0xFF)
30 orr \rv, \rv, #(TEGRA_DEBUG_UART_BASE & 0xFF00)
31 .endm
32
33#define UART_SHIFT 2
34#include <asm/hardware/debug-8250.S>
35
diff --git a/arch/arm/mach-tegra/include/mach/delay.h b/arch/arm/mach-tegra/include/mach/delay.h
new file mode 100644
index 00000000000..2defb7b9b65
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/delay.h
@@ -0,0 +1,41 @@
1/*
2 * arch/arm/mach-tegra/include/mach/delay.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19#ifndef __MACH_TEGRA_DELAY_H
20#define __MACH_TEGRA_DELAY_H
21
22/* needed by loops_per_jiffy calculations */
23extern void __delay(int loops);
24
25extern void __udelay(unsigned long usecs);
26extern void __const_udelay(unsigned long usecs);
27
28/* we don't have any restrictions on maximum udelay length, but we'll enforce
29 * the same restriction as the ARM default so we don't introduce any
30 * incompatibilties in drivers.
31 */
32extern void __bad_udelay(void);
33
34#define MAX_UDELAY_MS 2
35
36#define udelay(n) \
37 ((__builtin_constant_p(n) && (n) > (MAX_UDELAY_MS * 1000)) ? \
38 __bad_udelay() : \
39 __udelay(n))
40
41#endif /* defined(__MACH_TEGRA_DELAY_H) */
diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h
new file mode 100644
index 00000000000..0b0a5d9fd1d
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/dma.h
@@ -0,0 +1,202 @@
1/*
2 * arch/arm/mach-tegra/include/mach/dma.h
3 *
4 * Copyright (c) 2008-2010, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
19 */
20
21#ifndef __MACH_TEGRA_DMA_H
22#define __MACH_TEGRA_DMA_H
23
24#include <linux/list.h>
25
26#if defined(CONFIG_TEGRA_SYSTEM_DMA)
27
28struct tegra_dma_req;
29struct tegra_dma_channel;
30
31#define TEGRA_DMA_REQ_SEL_CNTR 0
32#define TEGRA_DMA_REQ_SEL_I2S_2 1
33#define TEGRA_DMA_REQ_SEL_APBIF_CH0 TEGRA_DMA_REQ_SEL_I2S_2
34#define TEGRA_DMA_REQ_SEL_I2S_1 2
35#define TEGRA_DMA_REQ_SEL_APBIF_CH1 TEGRA_DMA_REQ_SEL_I2S_1
36#define TEGRA_DMA_REQ_SEL_SPD_I 3
37#define TEGRA_DMA_REQ_SEL_APBIF_CH2 TEGRA_DMA_REQ_SEL_SPD_I
38#define TEGRA_DMA_REQ_SEL_UI_I 4
39#define TEGRA_DMA_REQ_SEL_APBIF_CH3 TEGRA_DMA_REQ_SEL_UI_I
40#define TEGRA_DMA_REQ_SEL_MIPI 5
41#define TEGRA_DMA_REQ_SEL_I2S2_2 6
42#define TEGRA_DMA_REQ_SEL_I2S2_1 7
43#define TEGRA_DMA_REQ_SEL_UARTA 8
44#define TEGRA_DMA_REQ_SEL_UARTB 9
45#define TEGRA_DMA_REQ_SEL_UARTC 10
46#define TEGRA_DMA_REQ_SEL_SPI 11
47#define TEGRA_DMA_REQ_SEL_DTV TEGRA_DMA_REQ_SEL_SPI
48#define TEGRA_DMA_REQ_SEL_AC97 12
49#define TEGRA_DMA_REQ_SEL_ACMODEM 13
50#define TEGRA_DMA_REQ_SEL_SL4B 14
51#define TEGRA_DMA_REQ_SEL_SL2B1 15
52#define TEGRA_DMA_REQ_SEL_SL2B2 16
53#define TEGRA_DMA_REQ_SEL_SL2B3 17
54#define TEGRA_DMA_REQ_SEL_SL2B4 18
55#define TEGRA_DMA_REQ_SEL_UARTD 19
56#define TEGRA_DMA_REQ_SEL_UARTE 20
57#define TEGRA_DMA_REQ_SEL_I2C 21
58#define TEGRA_DMA_REQ_SEL_I2C2 22
59#define TEGRA_DMA_REQ_SEL_I2C3 23
60#define TEGRA_DMA_REQ_SEL_DVC_I2C 24
61#define TEGRA_DMA_REQ_SEL_OWR 25
62#define TEGRA_DMA_REQ_SEL_I2C4 26
63#define TEGRA_DMA_REQ_SEL_SL2B5 27
64#define TEGRA_DMA_REQ_SEL_SL2B6 28
65#define TEGRA_DMA_REQ_SEL_INVALID 31
66
67enum tegra_dma_mode {
68 TEGRA_DMA_SHARED = 1,
69 TEGRA_DMA_MODE_CONTINUOUS = 2,
70 TEGRA_DMA_MODE_CONTINUOUS_DOUBLE = TEGRA_DMA_MODE_CONTINUOUS,
71 TEGRA_DMA_MODE_CONTINUOUS_SINGLE = 4,
72 TEGRA_DMA_MODE_ONESHOT = 8,
73};
74
75/*
76 * tegra_dma_req_status: Dma request status
77 * TEGRA_DMA_REQ_SUCCESS: The request has been successfully completed.
78 * The byte_transferred tells number of bytes transferred.
79 * TEGRA_DMA_REQ_ERROR_ABORTED: The request is aborted by client after
80 * calling tegra_dma_dequeue_req.
81 * The byte_transferred tells number of bytes transferred
82 * which may be more than request size due to buffer
83 * wrap-up in continuous mode.
84 * TEGRA_DMA_REQ_ERROR_STOPPED: Applicable in continuous mode.
85 * The request is stopped forcefully. This may be becasue of
86 * - due to non-available of next request.
87 * - not able to serve current interrupt before next buffer
88 * completed by dma. This can happen if buffer req size is
89 * not enough and it transfer completes before system actually
90 * serve the previous dma interrupts.
91 * The byte_transferred will not be accurate in this case. It will
92 * just give an idea that how much approximately have been
93 * transferred by dma.
94 * TEGRA_DMA_REQ_INFLIGHT: The request is configured in the dma register
95 * for transfer.
96 */
97
98enum tegra_dma_req_status {
99 TEGRA_DMA_REQ_SUCCESS = 0,
100 TEGRA_DMA_REQ_ERROR_ABORTED,
101 TEGRA_DMA_REQ_ERROR_STOPPED,
102 TEGRA_DMA_REQ_INFLIGHT,
103};
104
105enum tegra_dma_req_buff_status {
106 TEGRA_DMA_REQ_BUF_STATUS_EMPTY = 0,
107 TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL,
108 TEGRA_DMA_REQ_BUF_STATUS_FULL,
109};
110
111typedef void (*dma_callback)(struct tegra_dma_req *req);
112
113struct tegra_dma_req {
114 struct list_head node;
115 unsigned int modid;
116 int instance;
117
118 /* Called when the req is complete and from the DMA ISR context.
119 * When this is called the req structure is no longer queued by
120 * the DMA channel.
121 *
122 * State of the DMA depends on the number of req it has. If there are
123 * no DMA requests queued up, then it will STOP the DMA. It there are
124 * more requests in the DMA, then it will queue the next request.
125 */
126 dma_callback complete;
127
128 /* This is a called from the DMA ISR context when the DMA is still in
129 * progress and is actively filling same buffer.
130 *
131 * In case of continuous mode receive, this threshold is 1/2 the buffer
132 * size. In other cases, this will not even be called as there is no
133 * hardware support for it.
134 *
135 * In the case of continuous mode receive, if there is next req already
136 * queued, DMA programs the HW to use that req when this req is
137 * completed. If there is no "next req" queued, then DMA ISR doesn't do
138 * anything before calling this callback.
139 *
140 * This is mainly used by the cases, where the clients has queued
141 * only one req and want to get some sort of DMA threshold
142 * callback to program the next buffer.
143 *
144 */
145 dma_callback threshold;
146
147 /* 1 to copy to memory.
148 * 0 to copy from the memory to device FIFO */
149 int to_memory;
150
151 void *virt_addr;
152
153 unsigned long source_addr;
154 unsigned long dest_addr;
155 unsigned long dest_wrap;
156 unsigned long source_wrap;
157 unsigned long source_bus_width;
158 unsigned long dest_bus_width;
159 unsigned long req_sel;
160 unsigned int size;
161
162 int fixed_burst_size; /* only for dtv */
163
164 /* Updated by the DMA driver on the conpletion of the request. */
165 int bytes_transferred;
166 int status;
167
168 /* DMA completion tracking information */
169 int buffer_status;
170
171 /* Client specific data */
172 void *dev;
173};
174
175int tegra_dma_enqueue_req(struct tegra_dma_channel *ch,
176 struct tegra_dma_req *req);
177int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
178 struct tegra_dma_req *req);
179void tegra_dma_flush(struct tegra_dma_channel *ch);
180
181bool tegra_dma_is_req_inflight(struct tegra_dma_channel *ch,
182 struct tegra_dma_req *req);
183int tegra_dma_get_transfer_count(struct tegra_dma_channel *ch,
184 struct tegra_dma_req *req);
185bool tegra_dma_is_empty(struct tegra_dma_channel *ch);
186
187struct tegra_dma_channel *tegra_dma_allocate_channel(int mode,
188 const char namefmt[], ...);
189void tegra_dma_free_channel(struct tegra_dma_channel *ch);
190int tegra_dma_cancel(struct tegra_dma_channel *ch);
191
192int __init tegra_dma_init(void);
193
194#else /* !defined(CONFIG_TEGRA_SYSTEM_DMA) */
195static inline int tegra_dma_init(void)
196{
197 return 0;
198}
199
200#endif
201
202#endif
diff --git a/arch/arm/mach-tegra/include/mach/edp.h b/arch/arm/mach-tegra/include/mach/edp.h
new file mode 100644
index 00000000000..48321cae495
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/edp.h
@@ -0,0 +1,80 @@
1/*
2 * arch/arm/mach-tegra/include/mach/edp.h
3 *
4 * Copyright (c) 2011, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
19 */
20
21#ifndef __MACH_EDP_H
22#define __MACH_EDP_H
23
24#include <linux/debugfs.h>
25
26struct tegra_edp_entry {
27 char speedo_id;
28 char regulator_100mA;
29 char temperature;
30 char freq_limits[4];
31};
32
33struct tegra_edp_limits {
34 int temperature;
35 unsigned int freq_limits[4];
36};
37
38struct system_edp_entry {
39 char speedo_id;
40 char power_limit_100mW;
41 char freq_limits[4];
42};
43
44#ifdef CONFIG_TEGRA_EDP_LIMITS
45
46
47int tegra_edp_update_thermal_zone(int temperature);
48void tegra_init_cpu_edp_limits(unsigned int regulator_mA);
49void tegra_init_system_edp_limits(unsigned int power_limit_mW);
50void tegra_get_cpu_edp_limits(const struct tegra_edp_limits **limits, int *size);
51unsigned int tegra_get_edp_limit(void);
52void tegra_get_system_edp_limits(const unsigned int **limits);
53int tegra_system_edp_alarm(bool alarm);
54
55#else
56static inline void tegra_init_cpu_edp_limits(int regulator_mA)
57{}
58static inline void tegra_init_system_edp_limits(int power_limit_mW)
59{}
60static inline int tegra_edp_update_thermal_zone(int temperature)
61{ return -1; }
62static inline void tegra_get_cpu_edp_limits(struct tegra_edp_limits **limits,
63 int *size)
64{}
65static inline unsigned int tegra_get_edp_limit(void)
66{ return -1; }
67static inline void tegra_get_system_edp_limits(unsigned int **limits)
68{}
69static inline int tegra_system_edp_alarm(bool alarm)
70{ return -1; }
71#endif
72
73#ifdef CONFIG_ARCH_TEGRA_2x_SOC
74static inline void tegra_edp_throttle_cpu_now(u8 factor)
75{}
76#else
77void tegra_edp_throttle_cpu_now(u8 factor);
78#endif
79
80#endif /* __MACH_EDP_H */
diff --git a/arch/arm/mach-tegra/include/mach/entry-macro.S b/arch/arm/mach-tegra/include/mach/entry-macro.S
new file mode 100644
index 00000000000..50d1b212da2
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/entry-macro.S
@@ -0,0 +1,37 @@
1/* arch/arm/mach-tegra/include/mach/entry-macro.S
2 *
3 * Copyright (C) 2009 Palm, Inc.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15#include <mach/iomap.h>
16#include <mach/io.h>
17
18#if defined(CONFIG_ARM_GIC)
19#define HAVE_GET_IRQNR_PREAMBLE
20#include <asm/hardware/entry-macro-gic.S>
21
22 /* Uses the GIC interrupt controller built into the cpu */
23#define ICTRL_BASE (IO_CPU_VIRT + 0x40100)
24
25 .macro disable_fiq
26 .endm
27
28 .macro get_irqnr_preamble, base, tmp
29 movw \base, #(ICTRL_BASE & 0x0000ffff)
30 movt \base, #((ICTRL_BASE & 0xffff0000) >> 16)
31 .endm
32
33 .macro arch_ret_to_user, tmp1, tmp2
34 .endm
35#else
36#error "Unsupported configuration"
37#endif
diff --git a/arch/arm/mach-tegra/include/mach/fb.h b/arch/arm/mach-tegra/include/mach/fb.h
new file mode 100644
index 00000000000..ced6f9c2cb4
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/fb.h
@@ -0,0 +1,61 @@
1/*
2 * arch/arm/mach-tegra/include/mach/fb.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#ifndef __MACH_TEGRA_FB_H
21#define __MACH_TEGRA_FB_H
22
23#include <linux/fb.h>
24
25struct nvhost_device;
26struct tegra_dc;
27struct tegra_fb_data;
28struct tegra_fb_info;
29struct resource;
30
31#ifdef CONFIG_FB_TEGRA
32struct tegra_fb_info *tegra_fb_register(struct nvhost_device *ndev,
33 struct tegra_dc *dc,
34 struct tegra_fb_data *fb_data,
35 struct resource *fb_mem);
36void tegra_fb_unregister(struct tegra_fb_info *fb_info);
37void tegra_fb_update_monspecs(struct tegra_fb_info *fb_info,
38 struct fb_monspecs *specs,
39 bool (*mode_filter)(const struct tegra_dc *dc,
40 struct fb_videomode *mode));
41#else
42static inline struct tegra_fb_info *tegra_fb_register(struct nvhost_device *ndev,
43 struct tegra_dc *dc,
44 struct tegra_fb_data *fb_data,
45 struct resource *fb_mem)
46{
47 return NULL;
48}
49
50static inline void tegra_fb_unregister(struct tegra_fb_info *fb_info)
51{
52}
53
54static inline void tegra_fb_update_monspecs(struct tegra_fb_info *fb_info,
55 struct fb_monspecs *specs,
56 bool (*mode_filter)(struct fb_videomode *mode))
57{
58}
59#endif
60
61#endif
diff --git a/arch/arm/mach-tegra/include/mach/fiq.h b/arch/arm/mach-tegra/include/mach/fiq.h
new file mode 100644
index 00000000000..17625facf62
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/fiq.h
@@ -0,0 +1,25 @@
1/*
2 * Copyright (C) 2010 Google, Inc.
3 *
4 * Author:
5 * Iliyan Malchev <malchev@google.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#ifndef __ASM_ARCH_TEGRA_FIQ_H
19#define __ASM_ARCH_TEGRA_FIQ_H
20
21/* enable/disable an interrupt that is an FIQ (safe from FIQ context?) */
22void tegra_fiq_enable(int n);
23void tegra_fiq_disable(int n);
24
25#endif
diff --git a/arch/arm/mach-tegra/include/mach/gpio.h b/arch/arm/mach-tegra/include/mach/gpio.h
new file mode 100644
index 00000000000..b7357ab0c4d
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/gpio.h
@@ -0,0 +1,80 @@
1/*
2 * arch/arm/mach-tegra/include/mach/gpio.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#ifndef __MACH_TEGRA_GPIO_H
21#define __MACH_TEGRA_GPIO_H
22
23#include <linux/init.h>
24#include <mach/irqs.h>
25
26#define TEGRA_NR_GPIOS INT_GPIO_NR
27#define ARCH_NR_GPIOS (TEGRA_NR_GPIOS + 128)
28
29#include <asm-generic/gpio.h>
30#include "pinmux.h"
31
32struct gpio_init_pin_info {
33 char name[16];
34 int gpio_nr;
35 bool is_gpio;
36 bool is_input;
37 int value; /* Value if it is output*/
38};
39
40#define gpio_get_value __gpio_get_value
41#define gpio_set_value __gpio_set_value
42#define gpio_cansleep __gpio_cansleep
43
44#define TEGRA_GPIO_TO_IRQ(gpio) (INT_GPIO_BASE + (gpio))
45#define TEGRA_IRQ_TO_GPIO(irq) ((irq) - INT_GPIO_BASE)
46
47static inline int gpio_to_irq(unsigned int gpio)
48{
49 /* SOC gpio */
50 if (gpio < TEGRA_NR_GPIOS)
51 return INT_GPIO_BASE + gpio;
52
53 /* For non soc gpio, the external peripheral driver need to
54 * provide the implementation */
55 return __gpio_to_irq(gpio);
56}
57
58static inline int irq_to_gpio(unsigned int irq)
59{
60 /* SOC gpio */
61 if ((irq >= INT_GPIO_BASE) && (irq < INT_GPIO_BASE + INT_GPIO_NR))
62 return irq - INT_GPIO_BASE;
63
64 /* we don't supply reverse mappings for non-SOC gpios */
65 return -EIO;
66}
67
68struct tegra_gpio_table {
69 int gpio; /* GPIO number */
70 bool enable; /* Enable for GPIO at init? */
71};
72
73void tegra_gpio_config(struct tegra_gpio_table *table, int num);
74void tegra_gpio_enable(int gpio);
75void tegra_gpio_disable(int gpio);
76int tegra_gpio_resume_init(void);
77void tegra_gpio_init_configure(unsigned gpio, bool is_input, int value);
78void tegra_gpio_set_tristate(int gpio, enum tegra_tristate ts);
79int tegra_gpio_get_bank_int_nr(int gpio);
80#endif
diff --git a/arch/arm/mach-tegra/include/mach/gpufuse.h b/arch/arm/mach-tegra/include/mach/gpufuse.h
new file mode 100644
index 00000000000..4aa6cb66d5d
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/gpufuse.h
@@ -0,0 +1,19 @@
1/*
2 * arch/arm/mach-tegra/include/mach/gpufuse.h
3 *
4 * Copyright (C) 2010-2011 NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17/* Number of register sets to handle in host context switching */
18int tegra_gpu_register_sets(void);
19
diff --git a/arch/arm/mach-tegra/include/mach/hardware.h b/arch/arm/mach-tegra/include/mach/hardware.h
new file mode 100644
index 00000000000..92600f75fd4
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/hardware.h
@@ -0,0 +1,50 @@
1/*
2 * Copyright (C) 2010 Google, Inc.
3 * Copyright (C) 2011 NVIDIA Corp.
4 *
5 * Author:
6 * Colin Cross <ccross@google.com>
7 * Erik Gilling <konkers@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef MACH_TEGRA_HARDWARE_H
20#define MACH_TEGRA_HARDWARE_H
21
22#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
23#define pcibios_assign_all_busses() 1
24
25#else
26
27#define pcibios_assign_all_busses() 0
28#endif
29
30enum tegra_chipid {
31 TEGRA_CHIPID_UNKNOWN = 0,
32 TEGRA_CHIPID_TEGRA2 = 0x20,
33 TEGRA_CHIPID_TEGRA3 = 0x30,
34};
35
36enum tegra_revision {
37 TEGRA_REVISION_UNKNOWN = 0,
38 TEGRA_REVISION_A01,
39 TEGRA_REVISION_A02,
40 TEGRA_REVISION_A03,
41 TEGRA_REVISION_A03p,
42 TEGRA_REVISION_A04,
43 TEGRA_REVISION_A04p,
44 TEGRA_REVISION_MAX,
45};
46
47enum tegra_chipid tegra_get_chipid(void);
48enum tegra_revision tegra_get_revision(void);
49
50#endif
diff --git a/arch/arm/mach-tegra/include/mach/hdmi-audio.h b/arch/arm/mach-tegra/include/mach/hdmi-audio.h
new file mode 100644
index 00000000000..7d760690081
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/hdmi-audio.h
@@ -0,0 +1,46 @@
1/*
2 * arch/arm/mach-tegra/include/mach/hdmi-audio.h
3 *
4 * Copyright (c) 2008-2011, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
19 */
20
21#ifndef __MACH_TEGRA_HDMI_AUDIO_H
22#define __MACH_TEGRA_HDMI_AUDIO_H
23
24#include <linux/kernel.h>
25#include <linux/types.h>
26
27enum {
28 AUDIO_FREQ_32K = 32000,
29 AUDIO_FREQ_44_1K = 44100,
30 AUDIO_FREQ_48K = 48000,
31 AUDIO_FREQ_88_2K = 88200,
32 AUDIO_FREQ_96K = 96000,
33 AUDIO_FREQ_176_4K = 176400,
34 AUDIO_FREQ_192K = 192000,
35};
36
37enum {
38 AUTO = 0,
39 SPDIF,
40 HDA,
41};
42
43int tegra_hdmi_setup_audio_freq_source(unsigned audio_freq, unsigned audio_source);
44int tegra_hdmi_setup_hda_presence(void);
45
46#endif /* __MACH_TEGRA_HDMI_AUDIO_H */
diff --git a/arch/arm/mach-tegra/include/mach/i2s.h b/arch/arm/mach-tegra/include/mach/i2s.h
new file mode 100644
index 00000000000..42cce885cda
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/i2s.h
@@ -0,0 +1,316 @@
1/*
2 * arch/arm/mach-tegra/include/mach/i2s.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Iliyan Malchev <malchev@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#ifndef __ARCH_ARM_MACH_TEGRA_I2S_H
21#define __ARCH_ARM_MACH_TEGRA_I2S_H
22
23#include <linux/kernel.h>
24#include <linux/types.h>
25#include <linux/platform_device.h>
26
27/* Offsets from TEGRA_I2S1_BASE and TEGRA_I2S2_BASE */
28
29#define I2S_I2S_CTRL_0 0
30#define I2S_I2S_STATUS_0 4
31#define I2S_I2S_TIMING_0 8
32#define I2S_I2S_FIFO_SCR_0 0x0c
33#define I2S_I2S_PCM_CTRL_0 0x10
34#define I2S_I2S_NW_CTRL_0 0x14
35#define I2S_I2S_TDM_CTRL_0 0x20
36#define I2S_I2S_TDM_TX_RX_CTRL_0 0x24
37#define I2S_I2S_FIFO1_0 0x40
38#define I2S_I2S_FIFO2_0 0x80
39
40/*
41 * I2S_I2S_CTRL_0
42 */
43
44#define I2S_I2S_CTRL_FIFO2_TX_ENABLE (1<<30)
45#define I2S_I2S_CTRL_FIFO1_ENABLE (1<<29)
46#define I2S_I2S_CTRL_FIFO2_ENABLE (1<<28)
47#define I2S_I2S_CTRL_FIFO1_RX_ENABLE (1<<27)
48#define I2S_I2S_CTRL_FIFO_LPBK_ENABLE (1<<26)
49#define I2S_I2S_CTRL_MASTER_ENABLE (1<<25)
50#define I2S_I2S_CTRL_L_R_CTRL (1<<24) /* 0 = L/R: low/high */
51
52#define I2S_BIT_FORMAT_I2S 0
53#define I2S_BIT_FORMAT_RJM 1
54#define I2S_BIT_FORMAT_LJM 2
55#define I2S_BIT_FORMAT_DSP 3
56#define I2S_BIT_FORMAT_SHIFT 10
57
58#define I2S_I2S_CTRL_BIT_FORMAT_MASK (3<<10)
59#define I2S_I2S_CTRL_BIT_FORMAT_I2S (I2S_BIT_FORMAT_I2S<<10)
60#define I2S_I2S_CTRL_BIT_FORMAT_RJM (I2S_BIT_FORMAT_RJM<<10)
61#define I2S_I2S_CTRL_BIT_FORMAT_LJM (I2S_BIT_FORMAT_LJM<<10)
62#define I2S_I2S_CTRL_BIT_FORMAT_DSP (I2S_BIT_FORMAT_DSP<<10)
63
64#define I2S_BIT_SIZE_16 0
65#define I2S_BIT_SIZE_20 1
66#define I2S_BIT_SIZE_24 2
67#define I2S_BIT_SIZE_32 3
68#define I2S_BIT_SIZE_SHIFT 8
69
70#define I2S_I2S_CTRL_BIT_SIZE_MASK (3 << I2S_BIT_SIZE_SHIFT)
71#define I2S_I2S_CTRL_BIT_SIZE_16 (I2S_BIT_SIZE_16 << I2S_BIT_SIZE_SHIFT)
72#define I2S_I2S_CTRL_BIT_SIZE_20 (I2S_BIT_SIZE_20 << I2S_BIT_SIZE_SHIFT)
73#define I2S_I2S_CTRL_BIT_SIZE_24 (I2S_BIT_SIZE_24 << I2S_BIT_SIZE_SHIFT)
74#define I2S_I2S_CTRL_BIT_SIZE_32 (I2S_BIT_SIZE_32 << I2S_BIT_SIZE_SHIFT)
75
76#define I2S_FIFO_16_LSB 0
77#define I2S_FIFO_20_LSB 1
78#define I2S_FIFO_24_LSB 2
79#define I2S_FIFO_32 3
80#define I2S_FIFO_PACKED 7
81#define I2S_FIFO_SHIFT 4
82
83#define I2S_I2S_CTRL_FIFO_FORMAT_MASK (7<<4)
84#define I2S_I2S_CTRL_FIFO_FORMAT_16_LSB \
85 (I2S_FIFO_16_LSB << I2S_FIFO_SHIFT)
86#define I2S_I2S_CTRL_FIFO_FORMAT_20_LSB \
87 (I2S_FIFO_20_LSB << I2S_FIFO_SHIFT)
88#define I2S_I2S_CTRL_FIFO_FORMAT_24_LSB \
89 (I2S_FIFO_24_LSB << I2S_FIFO_SHIFT)
90#define I2S_I2S_CTRL_FIFO_FORMAT_32 \
91 (I2S_FIFO_32 << I2S_FIFO_SHIFT)
92#define I2S_I2S_CTRL_FIFO_FORMAT_PACKED \
93 (I2S_FIFO_PACKED << I2S_FIFO_SHIFT)
94
95#define I2S_I2S_IE_FIFO1_ERR (1<<3)
96#define I2S_I2S_IE_FIFO2_ERR (1<<2)
97#define I2S_I2S_QE_FIFO1 (1<<1)
98#define I2S_I2S_QE_FIFO2 (1<<0)
99
100/*
101 * I2S_I2S_STATUS_0
102 */
103
104#define I2S_I2S_STATUS_FIFO1_RDY (1<<31)
105#define I2S_I2S_STATUS_FIFO2_RDY (1<<30)
106#define I2S_I2S_STATUS_FIFO1_BSY (1<<29)
107#define I2S_I2S_STATUS_FIFO2_BSY (1<<28)
108#define I2S_I2S_STATUS_FIFO1_ERR (1<<3)
109#define I2S_I2S_STATUS_FIFO2_ERR (1<<2)
110#define I2S_I2S_STATUS_QS_FIFO1 (1<<1)
111#define I2S_I2S_STATUS_QS_FIFO2 (1<<0)
112
113/*
114 * I2S_I2S_TIMING_0
115 */
116
117#define I2S_I2S_TIMING_NON_SYM_ENABLE (1<<12)
118#define I2S_I2S_TIMING_CHANNEL_BIT_COUNT_MASK 0x7ff
119#define I2S_I2S_TIMING_CHANNEL_BIT_COUNT (1<<0)
120
121/*
122 * I2S_I2S_FIFO_SCR_0
123 */
124
125#define I2S_I2S_FIFO_SCR_FIFO_FULL_EMPTY_COUNT_MASK 0x3f
126#define I2S_I2S_FIFO_SCR_FIFO2_FULL_EMPTY_COUNT_SHIFT 24
127#define I2S_I2S_FIFO_SCR_FIFO1_FULL_EMPTY_COUNT_SHIFT 16
128
129#define I2S_I2S_FIFO_SCR_FIFO2_FULL_EMPTY_COUNT_MASK (0x3f<<24)
130#define I2S_I2S_FIFO_SCR_FIFO1_FULL_EMPTY_COUNT_MASK (0x3f<<16)
131
132#define I2S_I2S_FIFO_SCR_FIFO2_CLR (1<<12)
133#define I2S_I2S_FIFO_SCR_FIFO1_CLR (1<<8)
134
135#define I2S_FIFO_ATN_LVL_ONE_SLOT 0
136#define I2S_FIFO_ATN_LVL_FOUR_SLOTS 1
137#define I2S_FIFO_ATN_LVL_EIGHT_SLOTS 2
138#define I2S_FIFO_ATN_LVL_TWELVE_SLOTS 3
139#define I2S_FIFO2_ATN_LVL_SHIFT 4
140#define I2S_FIFO1_ATN_LVL_SHIFT 0
141
142#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_MASK \
143 (3 << I2S_FIFO2_ATN_LVL_SHIFT)
144#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_ONE_SLOT \
145 (I2S_FIFO_ATN_LVL_ONE_SLOT << I2S_FIFO2_ATN_LVL_SHIFT)
146#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS \
147 (I2S_FIFO_ATN_LVL_FOUR_SLOTS << I2S_FIFO2_ATN_LVL_SHIFT)
148#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_EIGHT_SLOTS \
149 (I2S_FIFO_ATN_LVL_EIGHT_SLOTS << I2S_FIFO2_ATN_LVL_SHIFT)
150#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_TWELVE_SLOTS \
151 (I2S_FIFO_ATN_LVL_TWELVE_SLOTS << I2S_FIFO2_ATN_LVL_SHIFT)
152
153#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_MASK \
154 (3 << I2S_FIFO1_ATN_LVL_SHIFT)
155#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_ONE_SLOT \
156 (I2S_FIFO_ATN_LVL_ONE_SLOT << I2S_FIFO1_ATN_LVL_SHIFT)
157#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS \
158 (I2S_FIFO_ATN_LVL_FOUR_SLOTS << I2S_FIFO1_ATN_LVL_SHIFT)
159#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_EIGHT_SLOTS \
160 (I2S_FIFO_ATN_LVL_EIGHT_SLOTS << I2S_FIFO1_ATN_LVL_SHIFT)
161#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_TWELVE_SLOTS \
162 (I2S_FIFO_ATN_LVL_TWELVE_SLOTS << I2S_FIFO1_ATN_LVL_SHIFT)
163/*
164 * I2S_I2S_PCM_CTRL_0
165 */
166#define I2S_PCM_TRM_EDGE_POS_EDGE_NO_HIGHZ 0
167#define I2S_PCM_TRM_EDGE_POS_EDGE_HIGHZ 1
168#define I2S_PCM_TRM_EDGE_NEG_EDGE_NO_HIGHZ 2
169#define I2S_PCM_TRM_EDGE_NEG_EDGE_HIGHZ 3
170#define I2S_PCM_TRM_EDGE_CTRL_SHIFT 9
171
172#define I2S_I2S_PCM_TRM_EDGE_CTRL_MASK \
173 (3 << I2S_I2S_PCM_TRM_EDGE_CTRL_SHIFT)
174#define I2S_I2S_PCM_TRM_EDGE_POS_EDGE_NO_HIGHZ \
175 (I2S_PCM_TRM_EDGE_POS_EDGE_HIGHZ \
176 << I2S_PCM_TRM_EDGE_CTRL_SHIFT)
177#define I2S_I2S_PCM_TRM_EDGE_POS_EDGE_HIGHZ \
178 (I2S_PCM_TRM_EDGE_POS_EDGE_NO_HIGHZ \
179 << I2S_PCM_TRM_EDGE_CTRL_SHIFT)
180#define I2S_I2S_PCM_TRM_EDGE_NEG_EDGE_NO_HIGHZ \
181 (I2S_PCM_TRM_EDGE_NEG_EDGE_NO_HIGHZ \
182 << I2S_PCM_TRM_EDGE_CTRL_SHIFT)
183#define I2S_I2S_PCM_TRM_EDGE_NEG_EDGE_HIGHZ \
184 (I2S_PCM_TRM_EDGE_NEG_EDGE_HIGHZ \
185 << I2S_PCM_TRM_EDGE_CTRL_SHIFT)
186
187#define I2S_PCM_TRM_MASK_BITS_ZERO 0
188#define I2S_PCM_TRM_MASK_BITS_ONE 1
189#define I2S_PCM_TRM_MASK_BITS_TWO 2
190#define I2S_PCM_TRM_MASK_BITS_THREE 3
191#define I2S_PCM_TRM_MASK_BITS_FOUR 4
192#define I2S_PCM_TRM_MASK_BITS_FIVE 5
193#define I2S_PCM_TRM_MASK_BITS_SIX 6
194#define I2S_PCM_TRM_MASK_BITS_SEVEN 7
195#define I2S_PCM_TRM_MASK_BITS_SHIFT 6
196
197#define I2S_I2S_PCM_TRM_MASK_BITS_MASK \
198 (7 << I2S_PCM_TRM_MASK_BITS_SHIFT)
199#define I2S_I2S_PCM_TRM_MASK_BITS_ZERO \
200 (I2S_PCM_TRM_MASK_BITS_ZERO \
201 << I2S_PCM_TRM_MASK_BITS_SHIFT)
202#define I2S_I2S_PCM_TRM_MASK_BITS_ONE \
203 (I2S_PCM_TRM_MASK_BITS_ONE \
204 << I2S_PCM_TRM_MASK_BITS_SHIFT)
205#define I2S_I2S_PCM_TRM_MASK_BITS_TWO \
206 (I2S_PCM_TRM_MASK_BITS_TWO \
207 << I2S_PCM_TRM_MASK_BITS_SHIFT)
208#define I2S_I2S_PCM_TRM_MASK_BITS_THREE \
209 (I2S_PCM_TRM_MASK_BITS_THREE \
210 << I2S_PCM_TRM_MASK_BITS_SHIFT)
211#define I2S_I2S_PCM_TRM_MASK_BITS_FOUR \
212 (I2S_PCM_TRM_MASK_BITS_FOUR \
213 << I2S_PCM_TRM_MASK_BITS_SHIFT)
214#define I2S_I2S_PCM_TRM_MASK_BITS_FIVE \
215 (I2S_PCM_TRM_MASK_BITS_FIVE \
216 << I2S_PCM_TRM_MASK_BITS_SHIFT)
217#define I2S_I2S_PCM_TRM_MASK_BITS_SIX \
218 (I2S_PCM_TRM_MASK_BITS_SIX \
219 << I2S_PCM_TRM_MASK_BITS_SHIFT)
220#define I2S_I2S_PCM_TRM_MASK_BITS_SEVEN \
221 (I2S_PCM_TRM_MASK_BITS_SEVEN \
222 << I2S_PCM_TRM_MASK_BITS_SHIFT)
223
224#define I2S_I2S_PCM_CTRL_FSYNC_PCM_CTRL (1<<5)
225#define I2S_I2S_PCM_CTRL_TRM_MODE (1<<4)
226
227#define I2S_PCM_RCV_MASK_BITS_ZERO 0
228#define I2S_PCM_RCV_MASK_BITS_ONE 1
229#define I2S_PCM_RCV_MASK_BITS_TWO 2
230#define I2S_PCM_RCV_MASK_BITS_THREE 3
231#define I2S_PCM_RCV_MASK_BITS_FOUR 4
232#define I2S_PCM_RCV_MASK_BITS_FIVE 5
233#define I2S_PCM_RCV_MASK_BITS_SIX 6
234#define I2S_PCM_RCV_MASK_BITS_SEVEN 7
235#define I2S_PCM_RCV_MASK_BITS_SHIFT 1
236
237#define I2S_I2S_PCM_RCV_MASK_BITS_MASK \
238 (7 << I2S_PCM_RCV_MASK_BITS_SHIFT)
239#define I2S_I2S_PCM_RCV_MASK_BITS_ZERO \
240 (I2S_PCM_RCV_MASK_BITS_ZERO \
241 << I2S_PCM_RCV_MASK_BITS_SHIFT)
242#define I2S_I2S_PCM_RCV_MASK_BITS_ONE \
243 (I2S_PCM_RCV_MASK_BITS_ONE \
244 << I2S_PCM_RCV_MASK_BITS_SHIFT)
245#define I2S_I2S_PCM_RCV_MASK_BITS_TWO \
246 (I2S_PCM_RCV_MASK_BITS_TWO \
247 << I2S_PCM_RCV_MASK_BITS_SHIFT)
248#define I2S_I2S_PCM_RCV_MASK_BITS_THREE \
249 (I2S_PCM_RCV_MASK_BITS_THREE \
250 << I2S_PCM_RCV_MASK_BITS_SHIFT)
251#define I2S_I2S_PCM_RCV_MASK_BITS_FOUR \
252 (I2S_PCM_RCV_MASK_BITS_FOUR \
253 << I2S_PCM_RCV_MASK_BITS_SHIFT)
254#define I2S_I2S_PCM_RCV_MASK_BITS_FIVE \
255 (I2S_PCM_RCV_MASK_BITS_FIVE \
256 << I2S_PCM_RCV_MASK_BITS_SHIFT)
257#define I2S_I2S_PCM_RCV_MASK_BITS_SIX \
258 (I2S_PCM_RCV_MASK_BITS_SIX \
259 << I2S_PCM_RCV_MASK_BITS_SHIFT)
260#define I2S_I2S_PCM_RCV_MASK_BITS_SEVEN \
261 (I2S_PCM_RCV_MASK_BITS_SEVEN \
262 << I2S_PCM_RCV_MASK_BITS_SHIFT)
263
264#define I2S_I2S_PCM_CTRL_RCV_MODE (1<<0)
265
266/*
267 * I2S_I2S_NW_CTRL_0
268 */
269
270#define I2S_TRM_TLPHY_SLOT_SEL_SLOT1 0
271#define I2S_TRM_TLPHY_SLOT_SEL_SLOT2 1
272#define I2S_TRM_TLPHY_SLOT_SEL_SLOT3 2
273#define I2S_TRM_TLPHY_SLOT_SEL_SLOT4 3
274#define I2S_I2S_NW_TRM_TLPHY_SLOT_SEL_SHIFT 4
275
276#define I2S_I2S_NW_TRM_TLPHY_SLOT_SEL_MASK \
277 (3 << I2S_TRM_TLPHY_SLOT_SEL_SHIFT)
278#define I2S_I2S_TRM_TLPHY_SLOT_SEL_SLOT1 \
279 (I2S_TRM_TLPHY_SLOT_SEL_SLOT1 \
280 << I2S_I2S_NW_TRM_TLPHY_SLOT_SEL_SHIFT)
281#define I2S_I2S_TRM_TLPHY_SLOT_SEL_SLOT2 \
282 (I2S_TRM_TLPHY_SLOT_SEL_SLOT2 \
283 << I2S_I2S_NW_TRM_TLPHY_SLOT_SEL_SHIFT)
284#define I2S_I2S_TRM_TLPHY_SLOT_SEL_SLOT3 \
285 (I2S_TRM_TLPHY_SLOT_SEL_SLOT3 \
286 << I2S_I2S_NW_TRM_TLPHY_SLOT_SEL_SHIFT)
287#define I2S_I2S_TRM_TLPHY_SLOT_SEL_SLOT4 \
288 (I2S_TRM_TLPHY_SLOT_SEL_SLOT4 \
289 << I2S_I2S_NW_TRM_TLPHY_SLOT_SEL_SHIFT)
290
291#define I2S_I2S_NW_CTRL_TRM_TLPHY_MODE (1<<3)
292
293#define I2S_RCV_TLPHY_SLOT_SEL_SLOT1 0
294#define I2S_RCV_TLPHY_SLOT_SEL_SLOT2 1
295#define I2S_RCV_TLPHY_SLOT_SEL_SLOT3 2
296#define I2S_RCV_TLPHY_SLOT_SEL_SLOT4 3
297#define I2S_I2S_NW_RCV_TLPHY_SLOT_SEL_SHIFT 1
298
299#define I2S_I2S_NW_RCV_TLPHY_SLOT_SEL_MASK \
300 (3 << I2S_RCV_TLPHY_SLOT_SEL_SHIFT)
301#define I2S_I2S_RCV_TLPHY_SLOT_SEL_SLOT1 \
302 (I2S_RCV_TLPHY_SLOT_SEL_SLOT1 \
303 << I2S_I2S_NW_RCV_TLPHY_SLOT_SEL_SHIFT)
304#define I2S_I2S_RCV_TLPHY_SLOT_SEL_SLOT2 \
305 (I2S_RCV_TLPHY_SLOT_SEL_SLOT2 \
306 << I2S_I2S_NW_RCV_TLPHY_SLOT_SEL_SHIFT)
307#define I2S_I2S_RCV_TLPHY_SLOT_SEL_SLOT3 \
308 (I2S_RCV_TLPHY_SLOT_SEL_SLOT3 \
309 << I2S_I2S_NW_RCV_TLPHY_SLOT_SEL_SHIFT)
310#define I2S_I2S_RCV_TLPHY_SLOT_SEL_SLOT4 \
311 (I2S_RCV_TLPHY_SLOT_SEL_SLOT4 \
312 << I2S_I2S_NW_RCV_TLPHY_SLOT_SEL_SHIFT)
313
314#define I2S_I2S_NW_CTRL_RCV_TLPHY_MODE (1<<0)
315
316#endif /* __ARCH_ARM_MACH_TEGRA_I2S_H */
diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h
new file mode 100644
index 00000000000..2b091bf83f3
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/io.h
@@ -0,0 +1,136 @@
1/*
2 * arch/arm/mach-tegra/include/mach/io.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2011-2012 NVIDIA Corporation.
6 *
7 * Author:
8 * Colin Cross <ccross@google.com>
9 * Erik Gilling <konkers@google.com>
10 *
11 * This software is licensed under the terms of the GNU General Public
12 * License version 2, as published by the Free Software Foundation, and
13 * may be copied, distributed, and modified under those terms.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 */
21
22#ifndef __MACH_TEGRA_IO_H
23#define __MACH_TEGRA_IO_H
24
25#ifdef CONFIG_ARCH_TEGRA_2x_SOC
26#define IO_SPACE_LIMIT 0xffff
27#else
28#define IO_SPACE_LIMIT 0xffffffff
29#endif
30
31/* On TEGRA, many peripherals are very closely packed in
32 * two 256MB io windows (that actually only use about 64KB
33 * at the start of each).
34 *
35 * We will just map the first 1MB of each window (to minimize
36 * pt entries needed) and provide a macro to transform physical
37 * io addresses to an appropriate void __iomem *.
38 *
39 */
40
41#define IO_IRAM_PHYS 0x40000000
42#define IO_IRAM_VIRT 0xFE400000
43#define IO_IRAM_SIZE SZ_256K
44
45#define IO_CPU_PHYS 0x50000000
46#define IO_CPU_VIRT 0xFE000000
47#define IO_CPU_SIZE SZ_1M
48
49#define IO_PPSB_PHYS 0x60000000
50#define IO_PPSB_VIRT 0xFE200000
51#define IO_PPSB_SIZE SZ_1M
52
53#define IO_APB_PHYS 0x70000000
54#define IO_APB_VIRT 0xFE300000
55#define IO_APB_SIZE SZ_1M
56
57#ifdef CONFIG_ARCH_TEGRA_2x_SOC
58#define IO_USB_PHYS 0xC5000000
59#else
60#define IO_USB_PHYS 0x7D000000
61#endif
62#define IO_USB_VIRT 0xFE500000
63#define IO_USB_SIZE SZ_1M
64
65#ifdef CONFIG_ARCH_TEGRA_2x_SOC
66#define IO_SDMMC_PHYS 0xC8000000
67#else
68#define IO_SDMMC_PHYS 0x78000000
69#endif
70#define IO_SDMMC_VIRT 0xFE600000
71#define IO_SDMMC_SIZE SZ_1M
72
73#define IO_HOST1X_PHYS 0x54000000
74#define IO_HOST1X_VIRT 0xFE700000
75#define IO_HOST1X_SIZE SZ_8M
76
77#ifdef CONFIG_ARCH_TEGRA_2x_SOC
78#define IO_PPCS_PHYS 0xC4000000
79#else
80#define IO_PPCS_PHYS 0x7C000000
81#endif
82#define IO_PPCS_VIRT 0xFE100000
83#define IO_PPCS_SIZE SZ_1M
84
85#define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz)))
86#define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst)))
87
88#define IO_TO_VIRT(n) ( \
89 IO_TO_VIRT_BETWEEN((n), IO_PPSB_PHYS, IO_PPSB_SIZE) ? \
90 IO_TO_VIRT_XLATE((n), IO_PPSB_PHYS, IO_PPSB_VIRT) : \
91 IO_TO_VIRT_BETWEEN((n), IO_APB_PHYS, IO_APB_SIZE) ? \
92 IO_TO_VIRT_XLATE((n), IO_APB_PHYS, IO_APB_VIRT) : \
93 IO_TO_VIRT_BETWEEN((n), IO_CPU_PHYS, IO_CPU_SIZE) ? \
94 IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) : \
95 IO_TO_VIRT_BETWEEN((n), IO_IRAM_PHYS, IO_IRAM_SIZE) ? \
96 IO_TO_VIRT_XLATE((n), IO_IRAM_PHYS, IO_IRAM_VIRT) : \
97 IO_TO_VIRT_BETWEEN((n), IO_HOST1X_PHYS, IO_HOST1X_SIZE) ? \
98 IO_TO_VIRT_XLATE((n), IO_HOST1X_PHYS, IO_HOST1X_VIRT) : \
99 IO_TO_VIRT_BETWEEN((n), IO_USB_PHYS, IO_USB_SIZE) ? \
100 IO_TO_VIRT_XLATE((n), IO_USB_PHYS, IO_USB_VIRT) : \
101 IO_TO_VIRT_BETWEEN((n), IO_SDMMC_PHYS, IO_SDMMC_SIZE) ? \
102 IO_TO_VIRT_XLATE((n), IO_SDMMC_PHYS, IO_SDMMC_VIRT) : \
103 IO_TO_VIRT_BETWEEN((n), IO_PPCS_PHYS, IO_PPCS_SIZE) ? \
104 IO_TO_VIRT_XLATE((n), IO_PPCS_PHYS, IO_PPCS_VIRT) : \
105 0)
106
107#ifndef __ASSEMBLER__
108
109#define __arch_ioremap tegra_ioremap
110#define __arch_iounmap tegra_iounmap
111
112void __iomem *tegra_ioremap(unsigned long phys, size_t size, unsigned int type);
113void tegra_iounmap(volatile void __iomem *addr);
114
115#define IO_ADDRESS(n) ((void __iomem *) IO_TO_VIRT(n))
116
117#if defined(CONFIG_TEGRA_PCI)
118extern void __iomem *tegra_pcie_io_base;
119
120static inline void __iomem *__io(unsigned long addr)
121{
122 return tegra_pcie_io_base + (addr & IO_SPACE_LIMIT);
123}
124#else
125static inline void __iomem *__io(unsigned long addr)
126{
127 return (void __iomem *)addr;
128}
129#endif
130
131#define __io(a) __io(a)
132#define __mem_pci(a) (a)
133
134#endif
135
136#endif
diff --git a/arch/arm/mach-tegra/include/mach/io_dpd.h b/arch/arm/mach-tegra/include/mach/io_dpd.h
new file mode 100644
index 00000000000..8d153792b79
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/io_dpd.h
@@ -0,0 +1,40 @@
1/*
2 * arch/arm/mach-tegra/include/mach/io_dpd.h
3 *
4 * Copyright (C) 2012 NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef __MACH_TEGRA_IO_DPD_H
18#define __MACH_TEGRA_IO_DPD_H
19
20/* Tegra io dpd APIs */
21#ifdef CONFIG_PM_SLEEP
22struct tegra_io_dpd *tegra_io_dpd_get(struct device *dev); /* get handle */
23void tegra_io_dpd_enable(struct tegra_io_dpd *hnd); /* enable dpd */
24void tegra_io_dpd_disable(struct tegra_io_dpd *hnd); /* disable dpd */
25#else
26static inline struct tegra_io_dpd *tegra_io_dpd_get(struct device *dev)
27{
28 return NULL;
29}
30static inline void tegra_io_dpd_enable(struct tegra_io_dpd *hnd)
31{
32 /* Do nothing */
33}
34static inline void tegra_io_dpd_disable(struct tegra_io_dpd *hnd)
35{
36 /* Do nothing */
37}
38#endif
39
40#endif /* end __MACH_TEGRA_IO_DPD_H */
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
new file mode 100644
index 00000000000..c491abafb8b
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -0,0 +1,523 @@
1/*
2 * arch/arm/mach-tegra/include/mach/iomap.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2011 NVIDIA Corporation.
6 *
7 * Author:
8 * Colin Cross <ccross@google.com>
9 * Erik Gilling <konkers@google.com>
10 *
11 * Copyright (C) 2010-2011 NVIDIA Corporation
12 *
13 * This software is licensed under the terms of the GNU General Public
14 * License version 2, as published by the Free Software Foundation, and
15 * may be copied, distributed, and modified under those terms.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 */
23
24#ifndef __MACH_TEGRA_IOMAP_H
25#define __MACH_TEGRA_IOMAP_H
26
27#include <asm/sizes.h>
28
29#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
30#define TEGRA_NOR_FLASH_BASE 0xD0000000
31#define TEGRA_NOR_FLASH_SIZE SZ_256M
32#else
33#define TEGRA_NOR_FLASH_BASE 0x48000000
34#define TEGRA_NOR_FLASH_SIZE SZ_128M
35#endif
36
37#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
38#define TEGRA_DRAM_BASE 0x00000000
39#define TEGRA_DRAM_SIZE SZ_1G /* Maximum size */
40#else
41#define TEGRA_DRAM_BASE 0x80000000
42#define TEGRA_DRAM_SIZE (SZ_2G - SZ_1M) /* Maximum size */
43#endif
44
45#define TEGRA_IRAM_BASE 0x40000000
46#define TEGRA_IRAM_SIZE SZ_256K
47
48/* First 1K of IRAM is reserved for cpu reset handler. */
49#define TEGRA_RESET_HANDLER_BASE TEGRA_IRAM_BASE
50#define TEGRA_RESET_HANDLER_SIZE SZ_1K
51
52#define TEGRA_HOST1X_BASE 0x50000000
53#define TEGRA_HOST1X_SIZE 0x24000
54
55#define TEGRA_ARM_PERIF_BASE 0x50040000
56#define TEGRA_ARM_PERIF_SIZE SZ_8K
57
58#define TEGRA_MSELECT_BASE 0x50042000
59#define TEGRA_MSELECT_SIZE 80
60
61#define TEGRA_ARM_PL310_BASE 0x50043000
62#define TEGRA_ARM_PL310_SIZE SZ_4K
63
64#define TEGRA_ARM_INT_DIST_BASE 0x50041000
65#define TEGRA_ARM_INT_DIST_SIZE SZ_4K
66
67#define TEGRA_MPE_BASE 0x54040000
68#define TEGRA_MPE_SIZE SZ_256K
69
70#define TEGRA_VI_BASE 0x54080000
71#define TEGRA_VI_SIZE SZ_256K
72
73#define TEGRA_ISP_BASE 0x54100000
74#define TEGRA_ISP_SIZE SZ_256K
75
76#define TEGRA_DISPLAY_BASE 0x54200000
77#define TEGRA_DISPLAY_SIZE SZ_256K
78
79#define TEGRA_DISPLAY2_BASE 0x54240000
80#define TEGRA_DISPLAY2_SIZE SZ_256K
81
82#define TEGRA_HDMI_BASE 0x54280000
83#define TEGRA_HDMI_SIZE SZ_256K
84
85#define TEGRA_DSI_BASE 0x54300000
86#define TEGRA_DSI_SIZE SZ_256K
87
88#define TEGRA_DSIB_BASE 0x54400000
89#define TEGRA_DSIB_SIZE SZ_256K
90
91#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
92
93#define TEGRA_GART_BASE 0x58000000
94#define TEGRA_GART_SIZE SZ_32M
95
96#else
97
98#define TEGRA_SMMU_BASE_TEGRA3_A01 0xe0000000
99#define TEGRA_SMMU_SIZE_TEGRA3_A01 SZ_256M
100#define TEGRA_SMMU_BASE 0x00001000
101#define TEGRA_SMMU_SIZE (SZ_1G - SZ_4K * 2)
102
103#endif
104
105#define TEGRA_RES_SEMA_SIZE SZ_4K
106#define TEGRA_RES_SEMA_BASE 0x60001000
107
108#define TEGRA_ARB_SEMA_BASE 0x60002000
109#define TEGRA_ARB_SEMA_SIZE SZ_4K
110
111#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000
112#define TEGRA_PRIMARY_ICTLR_SIZE 64
113
114#define TEGRA_ARBGNT_ICTLR_BASE 0x60004040
115#define TEGRA_ARBGNT_ICTLR_SIZE 192
116
117#define TEGRA_SECONDARY_ICTLR_BASE 0x60004100
118#define TEGRA_SECONDARY_ICTLR_SIZE 64
119
120#define TEGRA_TERTIARY_ICTLR_BASE 0x60004200
121#define TEGRA_TERTIARY_ICTLR_SIZE 64
122
123#define TEGRA_QUATERNARY_ICTLR_BASE 0x60004300
124#define TEGRA_QUATERNARY_ICTLR_SIZE 64
125
126#ifndef CONFIG_ARCH_TEGRA_2x_SOC
127
128#define TEGRA_QUINARY_ICTLR_BASE 0x60004400
129#define TEGRA_QUINARY_ICTLR_SIZE SZ_64
130
131#endif
132
133#define TEGRA_TMR1_BASE 0x60005000
134#define TEGRA_TMR1_SIZE SZ_8
135
136#define TEGRA_TMR2_BASE 0x60005008
137#define TEGRA_TMR2_SIZE SZ_8
138
139#define TEGRA_TMRUS_BASE 0x60005010
140#define TEGRA_TMRUS_SIZE 64
141
142#define TEGRA_TMR3_BASE 0x60005050
143#define TEGRA_TMR3_SIZE SZ_8
144
145#define TEGRA_TMR4_BASE 0x60005058
146#define TEGRA_TMR4_SIZE SZ_8
147
148#ifndef CONFIG_ARCH_TEGRA_2x_SOC
149
150#define TEGRA_TMR5_BASE 0x60005060
151#define TEGRA_TMR5_SIZE 8
152
153#define TEGRA_TMR6_BASE 0x60005068
154#define TEGRA_TMR6_SIZE 8
155
156#define TEGRA_TMR7_BASE 0x60005070
157#define TEGRA_TMR7_SIZE 8
158
159#define TEGRA_TMR8_BASE 0x60005078
160#define TEGRA_TMR8_SIZE 8
161
162#define TEGRA_TMR9_BASE 0x60005080
163#define TEGRA_TMR9_SIZE 8
164
165#define TEGRA_TMR10_BASE 0x60005088
166#define TEGRA_TMR10_SIZE 8
167
168#define TEGRA_WDT0_BASE 0x60005100
169#define TEGRA_WDT0_SIZE 32
170
171#define TEGRA_WDT1_BASE 0x60005120
172#define TEGRA_WDT1_SIZE 32
173
174#define TEGRA_WDT2_BASE 0x60005140
175#define TEGRA_WDT2_SIZE 32
176
177#define TEGRA_WDT3_BASE 0x60005160
178#define TEGRA_WDT3_SIZE 32
179
180#define TEGRA_WDT4_BASE 0x60005180
181#define TEGRA_WDT4_SIZE 32
182
183#endif
184
185#define TEGRA_CLK_RESET_BASE 0x60006000
186#define TEGRA_CLK_RESET_SIZE SZ_4K
187
188#define TEGRA_FLOW_CTRL_BASE 0x60007000
189#define TEGRA_FLOW_CTRL_SIZE 20
190
191#define TEGRA_AHB_DMA_BASE 0x60008000
192#define TEGRA_AHB_DMA_SIZE SZ_4K
193
194#define TEGRA_AHB_DMA_CH0_BASE 0x60009000
195#define TEGRA_AHB_DMA_CH0_SIZE 32
196
197#define TEGRA_APB_DMA_BASE 0x6000A000
198#define TEGRA_APB_DMA_SIZE SZ_4K
199
200#define TEGRA_APB_DMA_CH0_BASE 0x6000B000
201#define TEGRA_APB_DMA_CH0_SIZE 32
202
203#ifndef CONFIG_ARCH_TEGRA_2x_SOC
204
205#define TEGRA_AHB_ARB_BASE 0x6000C000
206#define TEGRA_AHB_ARB_SIZE 768 /* Overlaps with GISMO */
207
208#endif
209
210#define TEGRA_AHB_GIZMO_BASE 0x6000C004
211#define TEGRA_AHB_GIZMO_SIZE 0x10C
212
213#define TEGRA_SB_BASE 0x6000C200
214#define TEGRA_SB_SIZE 256
215
216#define TEGRA_STATMON_BASE 0x6000C400
217#define TEGRA_STATMON_SIZE SZ_1K
218
219#if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
220
221#define TEGRA_ACTMON_BASE 0x6000C800
222#define TEGRA_ACTMON_SIZE SZ_1K
223
224#endif
225
226#define TEGRA_GPIO_BASE 0x6000D000
227#define TEGRA_GPIO_SIZE SZ_4K
228
229#define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000
230#define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K
231
232#define TEGRA_BSEA_BASE 0x60010000
233#define TEGRA_BSEA_SIZE SZ_4K
234
235#define TEGRA_VDE_BASE 0x6001A000
236#define TEGRA_VDE_SIZE 0x3c00
237
238#define TEGRA_APB_MISC_BASE 0x70000000
239#define TEGRA_APB_MISC_SIZE SZ_4K
240
241#define TEGRA_APB_MISC_DAS_BASE 0x70000c00
242#define TEGRA_APB_MISC_DAS_SIZE SZ_128
243
244#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
245
246#define TEGRA_AC97_BASE 0x70002000
247#define TEGRA_AC97_SIZE SZ_512
248
249#define TEGRA_SPDIF_BASE 0x70002400
250#define TEGRA_SPDIF_SIZE SZ_512
251
252#define TEGRA_I2S1_BASE 0x70002800
253#define TEGRA_I2S1_SIZE SZ_256
254
255#define TEGRA_I2S2_BASE 0x70002A00
256#define TEGRA_I2S2_SIZE SZ_256
257
258#define TEGRA_PCIE_BASE 0x80000000
259#define TEGRA_PCIE_SIZE SZ_1G
260
261#elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
262
263#define TEGRA_TSENSOR_BASE 0x70014000
264#define TEGRA_TSENSOR_SIZE SZ_4K
265
266#define TEGRA_HDA_BASE 0x70030000
267#define TEGRA_HDA_SIZE SZ_64K
268
269#define TEGRA_AUDIO_CLUSTER_BASE 0x70080000
270#define TEGRA_AUDIO_CLUSTER_SIZE SZ_4K
271
272#define TEGRA_APBIF0_BASE TEGRA_AUDIO_CLUSTER_BASE
273#define TEGRA_APBIF0_SIZE 32
274
275#define TEGRA_APBIF1_BASE 0x70080020
276#define TEGRA_APBIF1_SIZE 32
277
278#define TEGRA_APBIF2_BASE 0x70080040
279#define TEGRA_APBIF2_SIZE 32
280
281#define TEGRA_APBIF3_BASE 0x70080060
282#define TEGRA_APBIF3_SIZE 32
283
284#define TEGRA_AHUB_BASE 0x70080200
285#define TEGRA_AHUB_SIZE SZ_256
286
287#define TEGRA_I2S0_BASE 0x70080300
288#define TEGRA_I2S0_SIZE SZ_256
289
290#define TEGRA_I2S1_BASE 0x70080400
291#define TEGRA_I2S1_SIZE SZ_256
292
293#define TEGRA_I2S2_BASE 0x70080500
294#define TEGRA_I2S2_SIZE SZ_256
295
296#define TEGRA_I2S3_BASE 0x70080600
297#define TEGRA_I2S3_SIZE SZ_256
298
299#define TEGRA_I2S4_BASE 0x70080700
300#define TEGRA_I2S4_SIZE SZ_256
301
302#define TEGRA_DAM0_BASE 0x70080800
303#define TEGRA_DAM0_SIZE SZ_256
304
305#define TEGRA_DAM1_BASE 0x70080900
306#define TEGRA_DAM1_SIZE SZ_256
307
308#define TEGRA_DAM2_BASE 0x70080A00
309#define TEGRA_DAM2_SIZE SZ_256
310
311#define TEGRA_SPDIF_BASE 0x70080B00
312#define TEGRA_SPDIF_SIZE SZ_256
313
314#define TEGRA_PCIE_BASE 0x00000000
315#define TEGRA_PCIE_SIZE SZ_1G
316
317#endif
318
319#define TEGRA_UARTA_BASE 0x70006000
320#define TEGRA_UARTA_SIZE 64
321
322#define TEGRA_UARTB_BASE 0x70006040
323#define TEGRA_UARTB_SIZE 64
324
325#define TEGRA_UARTC_BASE 0x70006200
326#define TEGRA_UARTC_SIZE SZ_256
327
328#define TEGRA_UARTD_BASE 0x70006300
329#define TEGRA_UARTD_SIZE SZ_256
330
331#define TEGRA_UARTE_BASE 0x70006400
332#define TEGRA_UARTE_SIZE SZ_256
333
334#define TEGRA_NAND_BASE 0x70008000
335#define TEGRA_NAND_SIZE SZ_256
336
337#define TEGRA_HSMMC_BASE 0x70008500
338#define TEGRA_HSMMC_SIZE SZ_256
339
340#define TEGRA_SNOR_BASE 0x70009000
341#define TEGRA_SNOR_SIZE SZ_4K
342
343#define TEGRA_PWFM_BASE 0x7000A000
344#define TEGRA_PWFM_SIZE SZ_256
345
346#define TEGRA_PWFM0_BASE 0x7000A000
347#define TEGRA_PWFM0_SIZE 4
348
349#define TEGRA_PWFM1_BASE 0x7000A010
350#define TEGRA_PWFM1_SIZE 4
351
352#define TEGRA_PWFM2_BASE 0x7000A020
353#define TEGRA_PWFM2_SIZE 4
354
355#define TEGRA_PWFM3_BASE 0x7000A030
356#define TEGRA_PWFM3_SIZE 4
357
358#define TEGRA_MIPI_BASE 0x7000B000
359#define TEGRA_MIPI_SIZE SZ_256
360
361#define TEGRA_I2C_BASE 0x7000C000
362#define TEGRA_I2C_SIZE SZ_256
363
364#define TEGRA_TWC_BASE 0x7000C100
365#define TEGRA_TWC_SIZE SZ_256
366
367#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
368
369#define TEGRA_SPI_BASE 0x7000C380
370#define TEGRA_SPI_SIZE 48
371
372#else
373
374#define TEGRA_DTV_BASE 0x7000C300
375#define TEGRA_DTV_SIZE SZ_256
376
377#endif
378
379#define TEGRA_I2C2_BASE 0x7000C400
380#define TEGRA_I2C2_SIZE SZ_256
381
382#define TEGRA_I2C3_BASE 0x7000C500
383#define TEGRA_I2C3_SIZE SZ_256
384
385#define TEGRA_OWR_BASE 0x7000C600
386#define TEGRA_OWR_SIZE 80
387
388#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
389
390#define TEGRA_DVC_BASE 0x7000D000
391#define TEGRA_DVC_SIZE SZ_512
392
393#else
394
395#define TEGRA_I2C4_BASE 0x7000C700
396#define TEGRA_I2C4_SIZE SZ_512
397
398#define TEGRA_I2C5_BASE 0x7000D000
399#define TEGRA_I2C5_SIZE SZ_512
400
401#endif
402
403#define TEGRA_SPI1_BASE 0x7000D400
404#define TEGRA_SPI1_SIZE SZ_512
405
406#define TEGRA_SPI2_BASE 0x7000D600
407#define TEGRA_SPI2_SIZE SZ_512
408
409#define TEGRA_SPI3_BASE 0x7000D800
410#define TEGRA_SPI3_SIZE SZ_512
411
412#define TEGRA_SPI4_BASE 0x7000DA00
413#define TEGRA_SPI4_SIZE SZ_512
414
415#ifndef CONFIG_ARCH_TEGRA_2x_SOC
416
417#define TEGRA_SPI5_BASE 0x7000DC00
418#define TEGRA_SPI5_SIZE SZ_512
419
420#define TEGRA_SPI6_BASE 0x7000DE00
421#define TEGRA_SPI6_SIZE SZ_512
422
423#endif
424
425#define TEGRA_RTC_BASE 0x7000E000
426#define TEGRA_RTC_SIZE SZ_256
427
428#define TEGRA_KBC_BASE 0x7000E200
429#define TEGRA_KBC_SIZE SZ_256
430
431#define TEGRA_PMC_BASE 0x7000E400
432#define TEGRA_PMC_SIZE SZ_256
433
434#define TEGRA_MC_BASE 0x7000F000
435#define TEGRA_MC_SIZE SZ_1K
436
437#define TEGRA_EMC_BASE 0x7000F400
438#define TEGRA_EMC_SIZE SZ_1K
439
440#define TEGRA_FUSE_BASE 0x7000F800
441#define TEGRA_FUSE_SIZE SZ_1K
442
443#define TEGRA_KFUSE_BASE 0x7000FC00
444#define TEGRA_KFUSE_SIZE SZ_1K
445
446#define TEGRA_CSITE_BASE 0x70040000
447#define TEGRA_CSITE_SIZE SZ_256K
448
449#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
450
451#define TEGRA_USB_BASE 0xC5000000
452#define TEGRA_USB_SIZE SZ_16K
453
454#define TEGRA_USB2_BASE 0xC5004000
455#define TEGRA_USB2_SIZE SZ_16K
456
457#define TEGRA_USB3_BASE 0xC5008000
458#define TEGRA_USB3_SIZE SZ_16K
459
460#define TEGRA_SDMMC1_BASE 0xC8000000
461#define TEGRA_SDMMC1_SIZE SZ_512
462
463#define TEGRA_SDMMC2_BASE 0xC8000200
464#define TEGRA_SDMMC2_SIZE SZ_512
465
466#define TEGRA_SDMMC3_BASE 0xC8000400
467#define TEGRA_SDMMC3_SIZE SZ_512
468
469#define TEGRA_SDMMC4_BASE 0xC8000600
470#define TEGRA_SDMMC4_SIZE SZ_512
471
472#else
473
474#define TEGRA_SATA_BASE 0x70020000
475#define TEGRA_SATA_SIZE SZ_64K
476
477#define TEGRA_SATA_CONFIG_BASE 0x70021000
478#define TEGRA_SATA_CONFIG_SIZE SZ_4K
479
480#define TEGRA_SATA_BAR5_BASE 0x70027000
481#define TEGRA_SATA_BAR5_SIZE SZ_8K
482
483#define TEGRA_SDMMC1_BASE 0x78000000
484#define TEGRA_SDMMC1_SIZE SZ_512
485
486#define TEGRA_SDMMC2_BASE 0x78000200
487#define TEGRA_SDMMC2_SIZE SZ_512
488
489#define TEGRA_SDMMC3_BASE 0x78000400
490#define TEGRA_SDMMC3_SIZE SZ_512
491
492#define TEGRA_SDMMC4_BASE 0x78000600
493#define TEGRA_SDMMC4_SIZE SZ_512
494
495#define TEGRA_USB_BASE 0x7D000000
496#define TEGRA_USB_SIZE SZ_16K
497
498#define TEGRA_USB2_BASE 0x7D004000
499#define TEGRA_USB2_SIZE SZ_16K
500
501#define TEGRA_USB3_BASE 0x7D008000
502#define TEGRA_USB3_SIZE SZ_16K
503
504#define TEGRA_SE_BASE 0x70012000
505#define TEGRA_SE_SIZE SZ_8K
506
507#endif
508
509#if defined(CONFIG_TEGRA_DEBUG_UART_NONE)
510# define TEGRA_DEBUG_UART_BASE 0
511#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
512# define TEGRA_DEBUG_UART_BASE TEGRA_UARTA_BASE
513#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
514# define TEGRA_DEBUG_UART_BASE TEGRA_UARTB_BASE
515#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
516# define TEGRA_DEBUG_UART_BASE TEGRA_UARTC_BASE
517#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
518# define TEGRA_DEBUG_UART_BASE TEGRA_UARTD_BASE
519#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
520# define TEGRA_DEBUG_UART_BASE TEGRA_UARTE_BASE
521#endif
522
523#endif
diff --git a/arch/arm/mach-tegra/include/mach/iovmm.h b/arch/arm/mach-tegra/include/mach/iovmm.h
new file mode 100644
index 00000000000..fd83a326e12
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/iovmm.h
@@ -0,0 +1,323 @@
1/*
2 * arch/arm/mach-tegra/include/mach/iovmm.h
3 *
4 * Copyright (c) 2010-2011, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed i the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
19 */
20
21#include <linux/list.h>
22#include <linux/platform_device.h>
23#include <linux/miscdevice.h>
24#include <linux/rbtree.h>
25#include <linux/rwsem.h>
26#include <linux/spinlock.h>
27#include <linux/types.h>
28
29#ifndef _MACH_TEGRA_IOVMM_H_
30#define _MACH_TEGRA_IOVMM_H_
31
32typedef u32 tegra_iovmm_addr_t;
33
34struct tegra_iovmm_device_ops;
35
36/*
37 * each I/O virtual memory manager unit should register a device with
38 * the iovmm system
39 */
40struct tegra_iovmm_device {
41 struct tegra_iovmm_device_ops *ops;
42 const char *name;
43 struct list_head list;
44 int pgsize_bits;
45};
46
47/*
48 * tegra_iovmm_domain serves a purpose analagous to mm_struct as defined in
49 * <linux/mm_types.h> - it defines a virtual address space within which
50 * tegra_iovmm_areas can be created.
51 */
52struct tegra_iovmm_domain {
53 atomic_t clients;
54 atomic_t locks;
55 spinlock_t block_lock; /* RB-tree for iovmm_area blocks */
56 unsigned long flags;
57 wait_queue_head_t delay_lock; /* when lock_client fails */
58 struct rw_semaphore map_lock;
59 struct rb_root all_blocks; /* ordered by address */
60 struct rb_root free_blocks; /* ordered by size */
61 struct tegra_iovmm_device *dev;
62};
63
64/*
65 * tegra_iovmm_client is analagous to an individual task in the task group
66 * which owns an mm_struct.
67 */
68
69struct iovmm_share_group;
70
71struct tegra_iovmm_client {
72 const char *name;
73 unsigned long flags;
74 struct iovmm_share_group *group;
75 struct tegra_iovmm_domain *domain;
76 struct miscdevice *misc_dev;
77 struct list_head list;
78};
79
80/*
81 * tegra_iovmm_area serves a purpose analagous to vm_area_struct as defined
82 * in <linux/mm_types.h> - it defines a virtual memory area which can be
83 * mapped to physical memory by a client-provided mapping function. */
84
85struct tegra_iovmm_area {
86 struct tegra_iovmm_domain *domain;
87 tegra_iovmm_addr_t iovm_start;
88 size_t iovm_length;
89 pgprot_t pgprot;
90 struct tegra_iovmm_area_ops *ops;
91};
92
93struct tegra_iovmm_device_ops {
94 /* maps a VMA using the page residency functions provided by the VMA */
95 int (*map)(struct tegra_iovmm_domain *domain,
96 struct tegra_iovmm_area *io_vma);
97 /* marks all PTEs in a VMA as invalid; decommits the virtual addres
98 * space (potentially freeing PDEs when decommit is true.) */
99 void (*unmap)(struct tegra_iovmm_domain *domain,
100 struct tegra_iovmm_area *io_vma, bool decommit);
101 void (*map_pfn)(struct tegra_iovmm_domain *domain,
102 struct tegra_iovmm_area *io_vma,
103 unsigned long offs, unsigned long pfn);
104 /*
105 * ensures that a domain is resident in the hardware's mapping region
106 * so that it may be used by a client
107 */
108 int (*lock_domain)(struct tegra_iovmm_domain *domain,
109 struct tegra_iovmm_client *client);
110 void (*unlock_domain)(struct tegra_iovmm_domain *domain,
111 struct tegra_iovmm_client *client);
112 /*
113 * allocates a vmm_domain for the specified client; may return the same
114 * domain for multiple clients
115 */
116 struct tegra_iovmm_domain* (*alloc_domain)(
117 struct tegra_iovmm_device *dev,
118 struct tegra_iovmm_client *client);
119 void (*free_domain)(struct tegra_iovmm_domain *domain,
120 struct tegra_iovmm_client *client);
121 int (*suspend)(struct tegra_iovmm_device *dev);
122 void (*resume)(struct tegra_iovmm_device *dev);
123};
124
125struct tegra_iovmm_area_ops {
126 /*
127 * ensures that the page of data starting at the specified offset
128 * from the start of the iovma is resident and pinned for use by
129 * DMA, returns the system pfn, or an invalid pfn if the
130 * operation fails.
131 */
132 unsigned long (*lock_makeresident)(struct tegra_iovmm_area *area,
133 tegra_iovmm_addr_t offs);
134 /* called when the page is unmapped from the I/O VMA */
135 void (*release)(struct tegra_iovmm_area *area, tegra_iovmm_addr_t offs);
136};
137
138#ifdef CONFIG_TEGRA_IOVMM
139/*
140 * called by clients to allocate an I/O VMM client mapping context which
141 * will be shared by all clients in the same share_group
142 */
143struct tegra_iovmm_client *tegra_iovmm_alloc_client(const char *name,
144 const char *share_group, struct miscdevice *misc_dev);
145
146size_t tegra_iovmm_get_vm_size(struct tegra_iovmm_client *client);
147
148void tegra_iovmm_free_client(struct tegra_iovmm_client *client);
149
150/*
151 * called by clients to ensure that their mapping context is resident
152 * before performing any DMA operations addressing I/O VMM regions.
153 * client_lock may return -EINTR.
154 */
155int tegra_iovmm_client_lock(struct tegra_iovmm_client *client);
156int tegra_iovmm_client_trylock(struct tegra_iovmm_client *client);
157
158/* called by clients after DMA operations are complete */
159void tegra_iovmm_client_unlock(struct tegra_iovmm_client *client);
160
161/*
162 * called by clients to allocate a new iovmm_area and reserve I/O virtual
163 * address space for it. if ops is NULL, clients should subsequently call
164 * tegra_iovmm_vm_map_pages and/or tegra_iovmm_vm_insert_pfn to explicitly
165 * map the I/O virtual address to an OS-allocated page or physical address,
166 * respectively. VM operations may be called before this call returns
167 */
168struct tegra_iovmm_area *tegra_iovmm_create_vm(
169 struct tegra_iovmm_client *client, struct tegra_iovmm_area_ops *ops,
170 size_t size, size_t align, pgprot_t pgprot, unsigned long iovm_start);
171
172/*
173 * called by clients to "zap" an iovmm_area, and replace all mappings
174 * in it with invalid ones, without freeing the virtual address range
175 */
176void tegra_iovmm_zap_vm(struct tegra_iovmm_area *vm);
177
178/*
179 * after zapping a demand-loaded iovmm_area, the client should unzap it
180 * to allow the VMM device to remap the page range.
181 */
182void tegra_iovmm_unzap_vm(struct tegra_iovmm_area *vm);
183
184/* called by clients to return an iovmm_area to the free pool for the domain */
185void tegra_iovmm_free_vm(struct tegra_iovmm_area *vm);
186
187/* returns size of largest free iovm block */
188size_t tegra_iovmm_get_max_free(struct tegra_iovmm_client *client);
189
190/*
191 * called by client software to map the page-aligned I/O address vaddr to
192 * a specific physical address pfn. I/O VMA should have been created with
193 * a NULL tegra_iovmm_area_ops structure.
194 */
195void tegra_iovmm_vm_insert_pfn(struct tegra_iovmm_area *area,
196 tegra_iovmm_addr_t vaddr, unsigned long pfn);
197
198/*
199 * called by clients to return the iovmm_area containing addr, or NULL if
200 * addr has not been allocated. caller should call tegra_iovmm_area_put when
201 * finished using the returned pointer
202 */
203struct tegra_iovmm_area *tegra_iovmm_find_area_get(
204 struct tegra_iovmm_client *client, tegra_iovmm_addr_t addr);
205
206struct tegra_iovmm_area *tegra_iovmm_area_get(struct tegra_iovmm_area *vm);
207void tegra_iovmm_area_put(struct tegra_iovmm_area *vm);
208
209/* called by drivers to initialize a tegra_iovmm_domain structure */
210int tegra_iovmm_domain_init(struct tegra_iovmm_domain *domain,
211 struct tegra_iovmm_device *dev, tegra_iovmm_addr_t start,
212 tegra_iovmm_addr_t end);
213
214/* called by drivers to register an I/O VMM device with the system */
215int tegra_iovmm_register(struct tegra_iovmm_device *dev);
216
217/* called by drivers to remove an I/O VMM device from the system */
218int tegra_iovmm_unregister(struct tegra_iovmm_device *dev);
219
220#else /* CONFIG_TEGRA_IOVMM */
221
222static inline struct tegra_iovmm_client *tegra_iovmm_alloc_client(
223 const char *name, const char *share_group, struct miscdevice *misc_dev)
224{
225 return NULL;
226}
227
228static inline size_t tegra_iovmm_get_vm_size(struct tegra_iovmm_client *client)
229{
230 return 0;
231}
232
233static inline void tegra_iovmm_free_client(struct tegra_iovmm_client *client)
234{
235}
236
237static inline int tegra_iovmm_client_lock(struct tegra_iovmm_client *client)
238{
239 return 0;
240}
241
242static inline int tegra_iovmm_client_trylock(struct tegra_iovmm_client *client)
243{
244 return 0;
245}
246
247static inline void tegra_iovmm_client_unlock(struct tegra_iovmm_client *client)
248{
249}
250
251static inline struct tegra_iovmm_area *tegra_iovmm_create_vm(
252 struct tegra_iovmm_client *client, struct tegra_iovmm_area_ops *ops,
253 size_t size, size_t align, pgprot_t pgprot, unsigned long iovm_start)
254{
255 return NULL;
256}
257
258static inline void tegra_iovmm_zap_vm(struct tegra_iovmm_area *vm)
259{
260}
261
262static inline void tegra_iovmm_unzap_vm(struct tegra_iovmm_area *vm)
263{
264}
265
266static inline void tegra_iovmm_free_vm(struct tegra_iovmm_area *vm)
267{
268}
269
270static inline size_t tegra_iovmm_get_max_free(struct tegra_iovmm_client *client)
271{
272 return 0;
273}
274
275static inline void tegra_iovmm_vm_insert_pfn(struct tegra_iovmm_area *area,
276 tegra_iovmm_addr_t vaddr, unsigned long pfn)
277{
278}
279
280static inline struct tegra_iovmm_area *tegra_iovmm_find_area_get(
281 struct tegra_iovmm_client *client, tegra_iovmm_addr_t addr)
282{
283 return NULL;
284}
285
286static inline struct tegra_iovmm_area *tegra_iovmm_area_get(
287 struct tegra_iovmm_area *vm)
288{
289 return NULL;
290}
291
292static inline void tegra_iovmm_area_put(struct tegra_iovmm_area *vm)
293{
294}
295
296static inline int tegra_iovmm_domain_init(struct tegra_iovmm_domain *domain,
297 struct tegra_iovmm_device *dev, tegra_iovmm_addr_t start,
298 tegra_iovmm_addr_t end)
299{
300 return 0;
301}
302
303static inline int tegra_iovmm_register(struct tegra_iovmm_device *dev)
304{
305 return 0;
306}
307
308static inline int tegra_iovmm_unregister(struct tegra_iovmm_device *dev)
309{
310 return 0;
311}
312
313static inline int tegra_iovmm_suspend(void)
314{
315 return 0;
316}
317
318static inline void tegra_iovmm_resume(void)
319{
320}
321
322#endif /* CONFIG_TEGRA_IOVMM */
323#endif /* _MACH_TEGRA_IOVMM_H_*/
diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h
new file mode 100644
index 00000000000..bf1b12559be
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/irqs.h
@@ -0,0 +1,391 @@
1/*
2 * arch/arm/mach-tegra/include/mach/irqs.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2011 NVIDIA Corporation.
6 *
7 * Author:
8 * Colin Cross <ccross@google.com>
9 * Erik Gilling <konkers@google.com>
10 *
11 * This software is licensed under the terms of the GNU General Public
12 * License version 2, as published by the Free Software Foundation, and
13 * may be copied, distributed, and modified under those terms.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 */
21
22#ifndef __MACH_TEGRA_IRQS_H
23#define __MACH_TEGRA_IRQS_H
24
25#define INT_GIC_BASE 0
26
27#define IRQ_LOCALTIMER 29
28
29#ifdef CONFIG_ARCH_TEGRA_2x_SOC
30/* Primary Interrupt Controller */
31#define INT_PRI_BASE (INT_GIC_BASE + 32)
32#define INT_TMR1 (INT_PRI_BASE + 0)
33#define INT_TMR2 (INT_PRI_BASE + 1)
34#define INT_RTC (INT_PRI_BASE + 2)
35#define INT_I2S2 (INT_PRI_BASE + 3)
36#define INT_SHR_SEM_INBOX_IBF (INT_PRI_BASE + 4)
37#define INT_SHR_SEM_INBOX_IBE (INT_PRI_BASE + 5)
38#define INT_SHR_SEM_OUTBOX_IBF (INT_PRI_BASE + 6)
39#define INT_SHR_SEM_OUTBOX_IBE (INT_PRI_BASE + 7)
40#define INT_VDE_UCQ_ERROR (INT_PRI_BASE + 8)
41#define INT_VDE_SYNC_TOKEN (INT_PRI_BASE + 9)
42#define INT_VDE_BSE_V (INT_PRI_BASE + 10)
43#define INT_VDE_BSE_A (INT_PRI_BASE + 11)
44#define INT_VDE_SXE (INT_PRI_BASE + 12)
45#define INT_I2S1 (INT_PRI_BASE + 13)
46#define INT_SDMMC1 (INT_PRI_BASE + 14)
47#define INT_SDMMC2 (INT_PRI_BASE + 15)
48#define INT_XIO (INT_PRI_BASE + 16)
49#define INT_VDE (INT_PRI_BASE + 17)
50#define INT_AVP_UCQ (INT_PRI_BASE + 18)
51#define INT_SDMMC3 (INT_PRI_BASE + 19)
52#define INT_USB (INT_PRI_BASE + 20)
53#define INT_USB2 (INT_PRI_BASE + 21)
54#define INT_PRI_RES_22 (INT_PRI_BASE + 22)
55#define INT_EIDE (INT_PRI_BASE + 23)
56#define INT_NANDFLASH (INT_PRI_BASE + 24)
57#define INT_VCP (INT_PRI_BASE + 25)
58#define INT_APB_DMA (INT_PRI_BASE + 26)
59#define INT_AHB_DMA (INT_PRI_BASE + 27)
60#define INT_GNT_0 (INT_PRI_BASE + 28)
61#define INT_GNT_1 (INT_PRI_BASE + 29)
62#define INT_OWR (INT_PRI_BASE + 30)
63#define INT_SDMMC4 (INT_PRI_BASE + 31)
64
65/* Secondary Interrupt Controller */
66#define INT_SEC_BASE (INT_PRI_BASE + 32)
67#define INT_GPIO1 (INT_SEC_BASE + 0)
68#define INT_GPIO2 (INT_SEC_BASE + 1)
69#define INT_GPIO3 (INT_SEC_BASE + 2)
70#define INT_GPIO4 (INT_SEC_BASE + 3)
71#define INT_UARTA (INT_SEC_BASE + 4)
72#define INT_UARTB (INT_SEC_BASE + 5)
73#define INT_I2C (INT_SEC_BASE + 6)
74#define INT_SPI (INT_SEC_BASE + 7)
75#define INT_TWC (INT_SEC_BASE + 8)
76#define INT_TMR3 (INT_SEC_BASE + 9)
77#define INT_TMR4 (INT_SEC_BASE + 10)
78#define INT_FLOW_RSM0 (INT_SEC_BASE + 11)
79#define INT_FLOW_RSM1 (INT_SEC_BASE + 12)
80#define INT_SPDIF (INT_SEC_BASE + 13)
81#define INT_UARTC (INT_SEC_BASE + 14)
82#define INT_MIPI (INT_SEC_BASE + 15)
83#define INT_EVENTA (INT_SEC_BASE + 16)
84#define INT_EVENTB (INT_SEC_BASE + 17)
85#define INT_EVENTC (INT_SEC_BASE + 18)
86#define INT_EVENTD (INT_SEC_BASE + 19)
87#define INT_VFIR (INT_SEC_BASE + 20)
88#define INT_DVC (INT_SEC_BASE + 21)
89#define INT_SYS_STATS_MON (INT_SEC_BASE + 22)
90#define INT_GPIO5 (INT_SEC_BASE + 23)
91#define INT_CPU0_PMU_INTR (INT_SEC_BASE + 24)
92#define INT_CPU1_PMU_INTR (INT_SEC_BASE + 25)
93#define INT_SEC_RES_26 (INT_SEC_BASE + 26)
94#define INT_SPI_1 (INT_SEC_BASE + 27)
95#define INT_APB_DMA_COP (INT_SEC_BASE + 28)
96#define INT_AHB_DMA_COP (INT_SEC_BASE + 29)
97#define INT_DMA_TX (INT_SEC_BASE + 30)
98#define INT_DMA_RX (INT_SEC_BASE + 31)
99
100/* Tertiary Interrupt Controller */
101#define INT_TRI_BASE (INT_SEC_BASE + 32)
102#define INT_HOST1X_COP_SYNCPT (INT_TRI_BASE + 0)
103#define INT_HOST1X_MPCORE_SYNCPT (INT_TRI_BASE + 1)
104#define INT_HOST1X_COP_GENERAL (INT_TRI_BASE + 2)
105#define INT_HOST1X_MPCORE_GENERAL (INT_TRI_BASE + 3)
106#define INT_MPE_GENERAL (INT_TRI_BASE + 4)
107#define INT_VI_GENERAL (INT_TRI_BASE + 5)
108#define INT_EPP_GENERAL (INT_TRI_BASE + 6)
109#define INT_ISP_GENERAL (INT_TRI_BASE + 7)
110#define INT_2D_GENERAL (INT_TRI_BASE + 8)
111#define INT_DISPLAY_GENERAL (INT_TRI_BASE + 9)
112#define INT_DISPLAY_B_GENERAL (INT_TRI_BASE + 10)
113#define INT_HDMI (INT_TRI_BASE + 11)
114#define INT_TVO_GENERAL (INT_TRI_BASE + 12)
115#define INT_MC_GENERAL (INT_TRI_BASE + 13)
116#define INT_EMC_GENERAL (INT_TRI_BASE + 14)
117#define INT_TRI_RES_15 (INT_TRI_BASE + 15)
118#define INT_TRI_RES_16 (INT_TRI_BASE + 16)
119#define INT_AC97 (INT_TRI_BASE + 17)
120#define INT_SPI_2 (INT_TRI_BASE + 18)
121#define INT_SPI_3 (INT_TRI_BASE + 19)
122#define INT_I2C2 (INT_TRI_BASE + 20)
123#define INT_KBC (INT_TRI_BASE + 21)
124#define INT_EXTERNAL_PMU (INT_TRI_BASE + 22)
125#define INT_GPIO6 (INT_TRI_BASE + 23)
126#define INT_TVDAC (INT_TRI_BASE + 24)
127#define INT_GPIO7 (INT_TRI_BASE + 25)
128#define INT_UARTD (INT_TRI_BASE + 26)
129#define INT_UARTE (INT_TRI_BASE + 27)
130#define INT_I2C3 (INT_TRI_BASE + 28)
131#define INT_SPI_4 (INT_TRI_BASE + 29)
132#define INT_TRI_RES_30 (INT_TRI_BASE + 30)
133#define INT_SW_RESERVED (INT_TRI_BASE + 31)
134
135/* Quaternary Interrupt Controller */
136#define INT_QUAD_BASE (INT_TRI_BASE + 32)
137#define INT_SNOR (INT_QUAD_BASE + 0)
138#define INT_USB3 (INT_QUAD_BASE + 1)
139#define INT_PCIE_INTR (INT_QUAD_BASE + 2)
140#define INT_PCIE_MSI (INT_QUAD_BASE + 3)
141#define INT_QUAD_RES_4 (INT_QUAD_BASE + 4)
142#define INT_QUAD_RES_5 (INT_QUAD_BASE + 5)
143#define INT_QUAD_RES_6 (INT_QUAD_BASE + 6)
144#define INT_QUAD_RES_7 (INT_QUAD_BASE + 7)
145#define INT_APB_DMA_CH0 (INT_QUAD_BASE + 8)
146#define INT_APB_DMA_CH1 (INT_QUAD_BASE + 9)
147#define INT_APB_DMA_CH2 (INT_QUAD_BASE + 10)
148#define INT_APB_DMA_CH3 (INT_QUAD_BASE + 11)
149#define INT_APB_DMA_CH4 (INT_QUAD_BASE + 12)
150#define INT_APB_DMA_CH5 (INT_QUAD_BASE + 13)
151#define INT_APB_DMA_CH6 (INT_QUAD_BASE + 14)
152#define INT_APB_DMA_CH7 (INT_QUAD_BASE + 15)
153#define INT_APB_DMA_CH8 (INT_QUAD_BASE + 16)
154#define INT_APB_DMA_CH9 (INT_QUAD_BASE + 17)
155#define INT_APB_DMA_CH10 (INT_QUAD_BASE + 18)
156#define INT_APB_DMA_CH11 (INT_QUAD_BASE + 19)
157#define INT_APB_DMA_CH12 (INT_QUAD_BASE + 20)
158#define INT_APB_DMA_CH13 (INT_QUAD_BASE + 21)
159#define INT_APB_DMA_CH14 (INT_QUAD_BASE + 22)
160#define INT_APB_DMA_CH15 (INT_QUAD_BASE + 23)
161#define INT_QUAD_RES_24 (INT_QUAD_BASE + 24)
162#define INT_QUAD_RES_25 (INT_QUAD_BASE + 25)
163#define INT_QUAD_RES_26 (INT_QUAD_BASE + 26)
164#define INT_QUAD_RES_27 (INT_QUAD_BASE + 27)
165#define INT_QUAD_RES_28 (INT_QUAD_BASE + 28)
166#define INT_QUAD_RES_29 (INT_QUAD_BASE + 29)
167#define INT_QUAD_RES_30 (INT_QUAD_BASE + 30)
168#define INT_QUAD_RES_31 (INT_QUAD_BASE + 31)
169
170#define INT_GIC_NR (INT_QUAD_BASE + 32)
171
172#define INT_MAIN_NR (INT_GIC_NR - INT_PRI_BASE)
173
174#define INT_SYNCPT_THRESH_BASE (INT_QUAD_BASE + 32)
175#define INT_SYNCPT_THRESH_NR 32
176
177#define INT_GPIO_BASE (INT_SYNCPT_THRESH_BASE + \
178 INT_SYNCPT_THRESH_NR)
179#define INT_GPIO_NR (28 * 8)
180
181#define INT_PCI_MSI_BASE (INT_GPIO_BASE + \
182 INT_GPIO_NR)
183#define INT_PCI_MSI_NR (0)
184
185#elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
186
187/* Primary Interrupt Controller */
188#define INT_PRI_BASE (INT_GIC_BASE + 32)
189#define INT_TMR1 (INT_PRI_BASE + 0)
190#define INT_TMR2 (INT_PRI_BASE + 1)
191#define INT_RTC (INT_PRI_BASE + 2)
192#define INT_CEC (INT_PRI_BASE + 3)
193#define INT_SHR_SEM_INBOX_IBF (INT_PRI_BASE + 4)
194#define INT_SHR_SEM_INBOX_IBE (INT_PRI_BASE + 5)
195#define INT_SHR_SEM_OUTBOX_IBF (INT_PRI_BASE + 6)
196#define INT_SHR_SEM_OUTBOX_IBE (INT_PRI_BASE + 7)
197#define INT_VDE_UCQ_ERROR (INT_PRI_BASE + 8)
198#define INT_VDE_SYNC_TOKEN (INT_PRI_BASE + 9)
199#define INT_VDE_BSE_V (INT_PRI_BASE + 10)
200#define INT_VDE_BSE_A (INT_PRI_BASE + 11)
201#define INT_VDE_SXE (INT_PRI_BASE + 12)
202#define INT_SATA_RX_STAT (INT_PRI_BASE + 13)
203#define INT_SDMMC1 (INT_PRI_BASE + 14)
204#define INT_SDMMC2 (INT_PRI_BASE + 15)
205#define INT_XIO (INT_PRI_BASE + 16)
206#define INT_VDE (INT_PRI_BASE + 17)
207#define INT_AVP_UCQ (INT_PRI_BASE + 18)
208#define INT_SDMMC3 (INT_PRI_BASE + 19)
209#define INT_USB (INT_PRI_BASE + 20)
210#define INT_USB2 (INT_PRI_BASE + 21)
211#define INT_HSMMC (INT_PRI_BASE + 22)
212#define INT_SATA_CTL (INT_PRI_BASE + 23)
213#define INT_NANDFLASH (INT_PRI_BASE + 24)
214#define INT_VCP (INT_PRI_BASE + 25)
215#define INT_APB_DMA (INT_PRI_BASE + 26)
216#define INT_AHB_DMA (INT_PRI_BASE + 27)
217#define INT_GNT_0 (INT_PRI_BASE + 28)
218#define INT_GNT_1 (INT_PRI_BASE + 29)
219#define INT_OWR (INT_PRI_BASE + 30)
220#define INT_SDMMC4 (INT_PRI_BASE + 31)
221
222/* Secondary Interrupt Controller */
223#define INT_SEC_BASE (INT_PRI_BASE + 32)
224#define INT_GPIO1 (INT_SEC_BASE + 0)
225#define INT_GPIO2 (INT_SEC_BASE + 1)
226#define INT_GPIO3 (INT_SEC_BASE + 2)
227#define INT_GPIO4 (INT_SEC_BASE + 3)
228#define INT_UARTA (INT_SEC_BASE + 4)
229#define INT_UARTB (INT_SEC_BASE + 5)
230#define INT_I2C (INT_SEC_BASE + 6)
231#define INT_SPI (INT_SEC_BASE + 7)
232#define INT_DTV INT_SPI
233#define INT_TWC (INT_SEC_BASE + 8)
234#define INT_TMR3 (INT_SEC_BASE + 9)
235#define INT_TMR4 (INT_SEC_BASE + 10)
236#define INT_FLOW_RSM0 (INT_SEC_BASE + 11)
237#define INT_FLOW_RSM1 (INT_SEC_BASE + 12)
238#define INT_ACTMON (INT_SEC_BASE + 13)
239#define INT_UARTC (INT_SEC_BASE + 14)
240#define INT_MIPI (INT_SEC_BASE + 15)
241#define INT_EVENTA (INT_SEC_BASE + 16)
242#define INT_EVENTB (INT_SEC_BASE + 17)
243#define INT_EVENTC (INT_SEC_BASE + 18)
244#define INT_EVENTD (INT_SEC_BASE + 19)
245#define INT_VFIR (INT_SEC_BASE + 20)
246#define INT_I2C5 (INT_SEC_BASE + 21)
247#define INT_SYS_STATS_MON (INT_SEC_BASE + 22)
248#define INT_GPIO5 (INT_SEC_BASE + 23)
249#define INT_SPEEDO_PMON_0 (INT_SEC_BASE + 24)
250#define INT_SPEEDO_PMON_1 (INT_SEC_BASE + 25)
251#define INT_SE (INT_SEC_BASE + 26)
252#define INT_SPI_1 (INT_SEC_BASE + 27)
253#define INT_APB_DMA_COP (INT_SEC_BASE + 28)
254#define INT_AHB_DMA_COP (INT_SEC_BASE + 29)
255#define INT_DMA_TX (INT_SEC_BASE + 30)
256#define INT_DMA_RX (INT_SEC_BASE + 31)
257
258/* Tertiary Interrupt Controller */
259#define INT_TRI_BASE (INT_SEC_BASE + 32)
260#define INT_HOST1X_COP_SYNCPT (INT_TRI_BASE + 0)
261#define INT_HOST1X_MPCORE_SYNCPT (INT_TRI_BASE + 1)
262#define INT_HOST1X_COP_GENERAL (INT_TRI_BASE + 2)
263#define INT_HOST1X_MPCORE_GENERAL (INT_TRI_BASE + 3)
264#define INT_MPE_GENERAL (INT_TRI_BASE + 4)
265#define INT_VI_GENERAL (INT_TRI_BASE + 5)
266#define INT_EPP_GENERAL (INT_TRI_BASE + 6)
267#define INT_ISP_GENERAL (INT_TRI_BASE + 7)
268#define INT_2D_GENERAL (INT_TRI_BASE + 8)
269#define INT_DISPLAY_GENERAL (INT_TRI_BASE + 9)
270#define INT_DISPLAY_B_GENERAL (INT_TRI_BASE + 10)
271#define INT_HDMI (INT_TRI_BASE + 11)
272#define INT_TVO_GENERAL (INT_TRI_BASE + 12)
273#define INT_MC_GENERAL (INT_TRI_BASE + 13)
274#define INT_EMC_GENERAL (INT_TRI_BASE + 14)
275#define INT_SPI_6 (INT_SEC_BASE + 15)
276#define INT_NOR_FLASH (INT_TRI_BASE + 16)
277#define INT_HDA (INT_TRI_BASE + 17)
278#define INT_SPI_2 (INT_TRI_BASE + 18)
279#define INT_SPI_3 (INT_TRI_BASE + 19)
280#define INT_I2C2 (INT_TRI_BASE + 20)
281#define INT_KBC (INT_TRI_BASE + 21)
282#define INT_EXTERNAL_PMU (INT_TRI_BASE + 22)
283#define INT_GPIO6 (INT_TRI_BASE + 23)
284#define INT_TVDAC (INT_TRI_BASE + 24)
285#define INT_GPIO7 (INT_TRI_BASE + 25)
286#define INT_UARTD (INT_TRI_BASE + 26)
287#define INT_UARTE (INT_TRI_BASE + 27)
288#define INT_I2C3 (INT_TRI_BASE + 28)
289#define INT_SPI_4 (INT_TRI_BASE + 29)
290#define INT_SPI_5 (INT_TRI_BASE + 30)
291#define INT_SW_RESERVED (INT_TRI_BASE + 31)
292
293/* Quaternary Interrupt Controller */
294#define INT_QUAD_BASE (INT_TRI_BASE + 32)
295#define INT_SNOR (INT_QUAD_BASE + 0)
296#define INT_USB3 (INT_QUAD_BASE + 1)
297#define INT_PCIE_INTR (INT_QUAD_BASE + 2)
298#define INT_PCIE_MSI (INT_QUAD_BASE + 3)
299#define INT_PCIE (INT_QUAD_BASE + 4)
300#define INT_AVP_CACHE (INT_QUAD_BASE + 5)
301#define INT_TSENSOR (INT_QUAD_BASE + 6)
302#define INT_AUDIO_CLUSTER (INT_QUAD_BASE + 7)
303#define INT_APB_DMA_CH0 (INT_QUAD_BASE + 8)
304#define INT_APB_DMA_CH1 (INT_QUAD_BASE + 9)
305#define INT_APB_DMA_CH2 (INT_QUAD_BASE + 10)
306#define INT_APB_DMA_CH3 (INT_QUAD_BASE + 11)
307#define INT_APB_DMA_CH4 (INT_QUAD_BASE + 12)
308#define INT_APB_DMA_CH5 (INT_QUAD_BASE + 13)
309#define INT_APB_DMA_CH6 (INT_QUAD_BASE + 14)
310#define INT_APB_DMA_CH7 (INT_QUAD_BASE + 15)
311#define INT_APB_DMA_CH8 (INT_QUAD_BASE + 16)
312#define INT_APB_DMA_CH9 (INT_QUAD_BASE + 17)
313#define INT_APB_DMA_CH10 (INT_QUAD_BASE + 18)
314#define INT_APB_DMA_CH11 (INT_QUAD_BASE + 19)
315#define INT_APB_DMA_CH12 (INT_QUAD_BASE + 20)
316#define INT_APB_DMA_CH13 (INT_QUAD_BASE + 21)
317#define INT_APB_DMA_CH14 (INT_QUAD_BASE + 22)
318#define INT_APB_DMA_CH15 (INT_QUAD_BASE + 23)
319#define INT_I2C4 (INT_QUAD_BASE + 24)
320#define INT_TMR5 (INT_QUAD_BASE + 25)
321#define INT_TMR_SHARED (INT_QUAD_BASE + 26) /* Deprecated */
322#define INT_WDT_CPU (INT_QUAD_BASE + 27)
323#define INT_WDT_AVP (INT_QUAD_BASE + 28)
324#define INT_GPIO8 (INT_QUAD_BASE + 29)
325#define INT_CAR (INT_QUAD_BASE + 30)
326#define INT_QUAD_RES_31 (INT_QUAD_BASE + 31)
327
328/* Quintary Interrupt Controller */
329#define INT_QUINT_BASE (INT_QUAD_BASE + 32)
330#define INT_APB_DMA_CH16 (INT_QUINT_BASE + 0)
331#define INT_APB_DMA_CH17 (INT_QUINT_BASE + 1)
332#define INT_APB_DMA_CH18 (INT_QUINT_BASE + 2)
333#define INT_APB_DMA_CH19 (INT_QUINT_BASE + 3)
334#define INT_APB_DMA_CH20 (INT_QUINT_BASE + 4)
335#define INT_APB_DMA_CH21 (INT_QUINT_BASE + 5)
336#define INT_APB_DMA_CH22 (INT_QUINT_BASE + 6)
337#define INT_APB_DMA_CH23 (INT_QUINT_BASE + 7)
338#define INT_APB_DMA_CH24 (INT_QUINT_BASE + 8)
339#define INT_APB_DMA_CH25 (INT_QUINT_BASE + 9)
340#define INT_APB_DMA_CH26 (INT_QUINT_BASE + 10)
341#define INT_APB_DMA_CH27 (INT_QUINT_BASE + 11)
342#define INT_APB_DMA_CH28 (INT_QUINT_BASE + 12)
343#define INT_APB_DMA_CH29 (INT_QUINT_BASE + 13)
344#define INT_APB_DMA_CH30 (INT_QUINT_BASE + 14)
345#define INT_APB_DMA_CH31 (INT_QUINT_BASE + 15)
346#define INT_CPU0_PMU_INTR (INT_QUINT_BASE + 16)
347#define INT_CPU1_PMU_INTR (INT_QUINT_BASE + 17)
348#define INT_CPU2_PMU_INTR (INT_QUINT_BASE + 18)
349#define INT_CPU3_PMU_INTR (INT_QUINT_BASE + 19)
350#define INT_CPU4_PMU_INTR (INT_QUINT_BASE + 20)
351#define INT_CPU5_PMU_INTR (INT_QUINT_BASE + 21)
352#define INT_CPU6_PMU_INTR (INT_QUINT_BASE + 22)
353#define INT_CPU7_PMU_INTR (INT_QUINT_BASE + 23)
354#define INT_TMR6 (INT_QUINT_BASE + 24)
355#define INT_TMR7 (INT_QUINT_BASE + 25)
356#define INT_TMR8 (INT_QUINT_BASE + 26)
357#define INT_TMR9 (INT_QUINT_BASE + 27)
358#define INT_TMR10 (INT_QUINT_BASE + 28)
359#define INT_QUINT_RES_29 (INT_QUINT_BASE + 29)
360#define INT_QUINT_RES_30 (INT_QUINT_BASE + 30)
361#define INT_QUINT_RES_31 (INT_QUINT_BASE + 31)
362
363#define INT_GIC_NR (INT_QUINT_BASE + 32)
364
365#define INT_MAIN_NR (INT_GIC_NR - INT_PRI_BASE)
366
367#define INT_SYNCPT_THRESH_BASE (INT_QUINT_BASE + 32)
368#define INT_SYNCPT_THRESH_NR 32
369
370#define INT_GPIO_BASE (INT_SYNCPT_THRESH_BASE + \
371 INT_SYNCPT_THRESH_NR)
372#define INT_GPIO_NR (32 * 8)
373
374#define INT_PCI_MSI_BASE (INT_GPIO_BASE + \
375 INT_GPIO_NR)
376#define INT_PCI_MSI_NR (32 * 8)
377
378#endif
379
380#define FIQ_START INT_GIC_BASE
381
382#define TEGRA_NR_IRQS (INT_PCI_MSI_BASE + \
383 INT_PCI_MSI_NR)
384
385#define INT_BOARD_BASE TEGRA_NR_IRQS
386
387#define NR_BOARD_IRQS 64
388
389#define NR_IRQS (INT_BOARD_BASE + NR_BOARD_IRQS)
390
391#endif
diff --git a/arch/arm/mach-tegra/include/mach/kbc.h b/arch/arm/mach-tegra/include/mach/kbc.h
new file mode 100644
index 00000000000..7b68baa04f1
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/kbc.h
@@ -0,0 +1,86 @@
1/*
2 * Platform definitions for tegra-kbc keyboard input driver
3 *
4 * Copyright (c) 2010-2011, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
19 */
20
21#ifndef ASMARM_ARCH_TEGRA_KBC_H
22#define ASMARM_ARCH_TEGRA_KBC_H
23
24#include <linux/types.h>
25#include <linux/input/matrix_keypad.h>
26
27#define KBC_MAX_GPIO 24
28#define KBC_MAX_KPENT 8
29
30#define KBC_MAX_ROW 16
31#define KBC_MAX_COL 8
32#define KBC_MAX_KEY (KBC_MAX_ROW * KBC_MAX_COL)
33
34#define KBC_PIN_GPIO_0 0
35#define KBC_PIN_GPIO_1 1
36#define KBC_PIN_GPIO_2 2
37#define KBC_PIN_GPIO_3 3
38#define KBC_PIN_GPIO_4 4
39#define KBC_PIN_GPIO_5 5
40#define KBC_PIN_GPIO_6 6
41#define KBC_PIN_GPIO_7 7
42#define KBC_PIN_GPIO_8 8
43#define KBC_PIN_GPIO_9 9
44#define KBC_PIN_GPIO_10 10
45#define KBC_PIN_GPIO_11 11
46#define KBC_PIN_GPIO_12 12
47#define KBC_PIN_GPIO_13 13
48#define KBC_PIN_GPIO_14 14
49#define KBC_PIN_GPIO_15 15
50#define KBC_PIN_GPIO_16 16
51#define KBC_PIN_GPIO_17 17
52#define KBC_PIN_GPIO_18 18
53#define KBC_PIN_GPIO_19 19
54#define KBC_PIN_GPIO_20 20
55#define KBC_PIN_GPIO_21 21
56#define KBC_PIN_GPIO_22 22
57#define KBC_PIN_GPIO_23 23
58
59struct tegra_kbc_pin_cfg {
60 bool is_row;
61 bool en;
62 unsigned char num;
63};
64
65struct tegra_kbc_wake_key {
66 u8 row:4;
67 u8 col:4;
68};
69
70struct tegra_kbc_platform_data {
71 unsigned int debounce_cnt;
72 unsigned int repeat_cnt;
73 unsigned int scan_count;
74
75 unsigned int wake_cnt; /* 0:wake on any key >1:wake on wake_cfg */
76 const struct tegra_kbc_wake_key *wake_cfg;
77
78 struct tegra_kbc_pin_cfg pin_cfg[KBC_MAX_GPIO];
79 const struct matrix_keymap_data *keymap_data;
80
81 bool wakeup;
82 bool use_fn_map;
83 bool use_ghost_filter;
84 bool disable_ev_rep;
85};
86#endif
diff --git a/arch/arm/mach-tegra/include/mach/kfuse.h b/arch/arm/mach-tegra/include/mach/kfuse.h
new file mode 100644
index 00000000000..cfe85cc86ff
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/kfuse.h
@@ -0,0 +1,20 @@
1/*
2 * arch/arm/mach-tegra/kfuse.h
3 *
4 * Copyright (C) 2010-2011 NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17/* there are 144 32-bit values in total */
18#define KFUSE_DATA_SZ (144 * 4)
19
20int tegra_kfuse_read(void *dest, size_t len);
diff --git a/arch/arm/mach-tegra/include/mach/latency_allowance.h b/arch/arm/mach-tegra/include/mach/latency_allowance.h
new file mode 100644
index 00000000000..f0d27f0b8ba
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/latency_allowance.h
@@ -0,0 +1,121 @@
1/*
2 * arch/arm/mach-tegra/include/mach/latency_allowance.h
3 *
4 * Copyright (C) 2011, NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef _MACH_TEGRA_LATENCY_ALLOWANCE_H_
18#define _MACH_TEGRA_LATENCY_ALLOWANCE_H_
19
20enum tegra_la_id {
21 TEGRA_LA_AFIR = 0,
22 TEGRA_LA_AFIW,
23 TEGRA_LA_AVPC_ARM7R,
24 TEGRA_LA_AVPC_ARM7W,
25 TEGRA_LA_DISPLAY_0A,
26 TEGRA_LA_DISPLAY_0B,
27 TEGRA_LA_DISPLAY_0C,
28 TEGRA_LA_DISPLAY_1B,
29 TEGRA_LA_DISPLAY_HC,
30 TEGRA_LA_DISPLAY_0AB,
31 TEGRA_LA_DISPLAY_0BB,
32 TEGRA_LA_DISPLAY_0CB,
33 TEGRA_LA_DISPLAY_1BB,
34 TEGRA_LA_DISPLAY_HCB,
35 TEGRA_LA_EPPUP,
36 TEGRA_LA_EPPU,
37 TEGRA_LA_EPPV,
38 TEGRA_LA_EPPY,
39 TEGRA_LA_G2PR,
40 TEGRA_LA_G2SR,
41 TEGRA_LA_G2DR,
42 TEGRA_LA_G2DW,
43 TEGRA_LA_HOST1X_DMAR,
44 TEGRA_LA_HOST1XR,
45 TEGRA_LA_HOST1XW,
46 TEGRA_LA_HDAR,
47 TEGRA_LA_HDAW,
48 TEGRA_LA_ISPW,
49 TEGRA_LA_MPCORER,
50 TEGRA_LA_MPCOREW,
51 TEGRA_LA_MPCORE_LPR,
52 TEGRA_LA_MPCORE_LPW,
53 TEGRA_LA_MPE_UNIFBR,
54 TEGRA_LA_MPE_IPRED,
55 TEGRA_LA_MPE_AMEMRD,
56 TEGRA_LA_MPE_CSRD,
57 TEGRA_LA_MPE_UNIFBW,
58 TEGRA_LA_MPE_CSWR,
59 TEGRA_LA_FDCDRD,
60 TEGRA_LA_IDXSRD,
61 TEGRA_LA_TEXSRD,
62 TEGRA_LA_FDCDWR,
63 TEGRA_LA_FDCDRD2,
64 TEGRA_LA_IDXSRD2,
65 TEGRA_LA_TEXSRD2,
66 TEGRA_LA_FDCDWR2,
67 TEGRA_LA_PPCS_AHBDMAR,
68 TEGRA_LA_PPCS_AHBSLVR,
69 TEGRA_LA_PPCS_AHBDMAW,
70 TEGRA_LA_PPCS_AHBSLVW,
71 TEGRA_LA_PTCR,
72 TEGRA_LA_SATAR,
73 TEGRA_LA_SATAW,
74 TEGRA_LA_VDE_BSEVR,
75 TEGRA_LA_VDE_MBER,
76 TEGRA_LA_VDE_MCER,
77 TEGRA_LA_VDE_TPER,
78 TEGRA_LA_VDE_BSEVW,
79 TEGRA_LA_VDE_DBGW,
80 TEGRA_LA_VDE_MBEW,
81 TEGRA_LA_VDE_TPMW,
82 TEGRA_LA_VI_RUV,
83 TEGRA_LA_VI_WSB,
84 TEGRA_LA_VI_WU,
85 TEGRA_LA_VI_WV,
86 TEGRA_LA_VI_WY,
87 TEGRA_LA_MAX_ID
88};
89
90#if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_TEGRA_FPGA_PLATFORM)
91static inline int tegra_set_latency_allowance(enum tegra_la_id id,
92 int bandwidth_in_mbps)
93{
94 return 0;
95}
96
97static inline int tegra_enable_latency_scaling(enum tegra_la_id id,
98 unsigned int threshold_low,
99 unsigned int threshold_mid,
100 unsigned int threshold_high)
101{
102 return 0;
103}
104
105static inline void tegra_disable_latency_scaling(enum tegra_la_id id)
106{
107 return 0;
108}
109#else
110int tegra_set_latency_allowance(enum tegra_la_id id,
111 unsigned int bandwidth_in_mbps);
112
113int tegra_enable_latency_scaling(enum tegra_la_id id,
114 unsigned int threshold_low,
115 unsigned int threshold_mid,
116 unsigned int threshold_high);
117
118void tegra_disable_latency_scaling(enum tegra_la_id id);
119#endif
120
121#endif /* _MACH_TEGRA_LATENCY_ALLOWANCE_H_ */
diff --git a/arch/arm/mach-tegra/include/mach/legacy_irq.h b/arch/arm/mach-tegra/include/mach/legacy_irq.h
new file mode 100644
index 00000000000..86f1ff7d06b
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/legacy_irq.h
@@ -0,0 +1,23 @@
1/*
2 * arch/arm/mach-tegra/include/mach/legacy_irq.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Colin Cross <ccross@android.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#ifndef _ARCH_ARM_MACH_TEGRA_LEGARY_IRQ_H
19#define _ARCH_ARM_MACH_TEGRA_LEGARY_IRQ_H
20
21void tegra_init_legacy_irq_cop(void);
22
23#endif
diff --git a/arch/arm/mach-tegra/include/mach/mc.h b/arch/arm/mach-tegra/include/mach/mc.h
new file mode 100644
index 00000000000..576153ad08d
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/mc.h
@@ -0,0 +1,109 @@
1/*
2 * arch/arm/mach-tegra/include/mach/mc.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#ifndef __MACH_TEGRA_MC_H
21#define __MACH_TEGRA_MC_H
22
23#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
24#define TEGRA_MC_FPRI_CTRL_AVPC 0x17c
25#define TEGRA_MC_FPRI_CTRL_DC 0x180
26#define TEGRA_MC_FPRI_CTRL_DCB 0x184
27#define TEGRA_MC_FPRI_CTRL_EPP 0x188
28#define TEGRA_MC_FPRI_CTRL_G2 0x18c
29#define TEGRA_MC_FPRI_CTRL_HC 0x190
30#define TEGRA_MC_FPRI_CTRL_ISP 0x194
31#define TEGRA_MC_FPRI_CTRL_MPCORE 0x198
32#define TEGRA_MC_FPRI_CTRL_MPEA 0x19c
33#define TEGRA_MC_FPRI_CTRL_MPEB 0x1a0
34#define TEGRA_MC_FPRI_CTRL_MPEC 0x1a4
35#define TEGRA_MC_FPRI_CTRL_NV 0x1a8
36#define TEGRA_MC_FPRI_CTRL_PPCS 0x1ac
37#define TEGRA_MC_FPRI_CTRL_VDE 0x1b0
38#define TEGRA_MC_FPRI_CTRL_VI 0x1b4
39
40#define TEGRA_MC_CLIENT_AVPCARM7R ((TEGRA_MC_FPRI_CTRL_AVPC << 8) | 0)
41#define TEGRA_MC_CLIENT_AVPCARM7W ((TEGRA_MC_FPRI_CTRL_AVPC << 8) | 2)
42#define TEGRA_MC_CLIENT_DISPLAY0A ((TEGRA_MC_FPRI_CTRL_DC << 8) | 0)
43#define TEGRA_MC_CLIENT_DISPLAY0B ((TEGRA_MC_FPRI_CTRL_DC << 8) | 2)
44#define TEGRA_MC_CLIENT_DISPLAY0C ((TEGRA_MC_FPRI_CTRL_DC << 8) | 4)
45#define TEGRA_MC_CLIENT_DISPLAY1B ((TEGRA_MC_FPRI_CTRL_DC << 8) | 6)
46#define TEGRA_MC_CLIENT_DISPLAYHC ((TEGRA_MC_FPRI_CTRL_DC << 8) | 8)
47#define TEGRA_MC_CLIENT_DISPLAY0AB ((TEGRA_MC_FPRI_CTRL_DCB << 8) | 0)
48#define TEGRA_MC_CLIENT_DISPLAY0BB ((TEGRA_MC_FPRI_CTRL_DCB << 8) | 2)
49#define TEGRA_MC_CLIENT_DISPLAY0CB ((TEGRA_MC_FPRI_CTRL_DCB << 8) | 4)
50#define TEGRA_MC_CLIENT_DISPLAY1BB ((TEGRA_MC_FPRI_CTRL_DCB << 8) | 6)
51#define TEGRA_MC_CLIENT_DISPLAYHCB ((TEGRA_MC_FPRI_CTRL_DCB << 8) | 8)
52#define TEGRA_MC_CLIENT_EPPUP ((TEGRA_MC_FPRI_CTRL_EPP << 8) | 0)
53#define TEGRA_MC_CLIENT_EPPU ((TEGRA_MC_FPRI_CTRL_EPP << 8) | 2)
54#define TEGRA_MC_CLIENT_EPPV ((TEGRA_MC_FPRI_CTRL_EPP << 8) | 4)
55#define TEGRA_MC_CLIENT_EPPY ((TEGRA_MC_FPRI_CTRL_EPP << 8) | 6)
56#define TEGRA_MC_CLIENT_G2PR ((TEGRA_MC_FPRI_CTRL_G2 << 8) | 0)
57#define TEGRA_MC_CLIENT_G2SR ((TEGRA_MC_FPRI_CTRL_G2 << 8) | 2)
58#define TEGRA_MC_CLIENT_G2DR ((TEGRA_MC_FPRI_CTRL_G2 << 8) | 4)
59#define TEGRA_MC_CLIENT_G2DW ((TEGRA_MC_FPRI_CTRL_G2 << 8) | 6)
60#define TEGRA_MC_CLIENT_HOST1XDMAR ((TEGRA_MC_FPRI_CTRL_HC << 8) | 0)
61#define TEGRA_MC_CLIENT_HOST1XR ((TEGRA_MC_FPRI_CTRL_HC << 8) | 2)
62#define TEGRA_MC_CLIENT_HOST1XW ((TEGRA_MC_FPRI_CTRL_HC << 8) | 4)
63#define TEGRA_MC_CLIENT_ISPW ((TEGRA_MC_FPRI_CTRL_ISP << 8) | 0)
64#define TEGRA_MC_CLIENT_MPCORER ((TEGRA_MC_FPRI_CTRL_MPCORE << 8) | 0)
65#define TEGRA_MC_CLIENT_MPCOREW ((TEGRA_MC_FPRI_CTRL_MPCORE << 8) | 2)
66#define TEGRA_MC_CLIENT_MPEAMEMRD ((TEGRA_MC_FPRI_CTRL_MPEA << 8) | 0)
67#define TEGRA_MC_CLIENT_MPEUNIFBR ((TEGRA_MC_FPRI_CTRL_MPEB << 8) | 0)
68#define TEGRA_MC_CLIENT_MPE_IPRED ((TEGRA_MC_FPRI_CTRL_MPEB << 8) | 2)
69#define TEGRA_MC_CLIENT_MPEUNIFBW ((TEGRA_MC_FPRI_CTRL_MPEB << 8) | 4)
70#define TEGRA_MC_CLIENT_MPECSRD ((TEGRA_MC_FPRI_CTRL_MPEC << 8) | 0)
71#define TEGRA_MC_CLIENT_MPECSWR ((TEGRA_MC_FPRI_CTRL_MPEC << 8) | 2)
72#define TEGRA_MC_CLIENT_FDCDRD ((TEGRA_MC_FPRI_CTRL_NV << 8) | 0)
73#define TEGRA_MC_CLIENT_IDXSRD ((TEGRA_MC_FPRI_CTRL_NV << 8) | 2)
74#define TEGRA_MC_CLIENT_TEXSRD ((TEGRA_MC_FPRI_CTRL_NV << 8) | 4)
75#define TEGRA_MC_CLIENT_FDCDWR ((TEGRA_MC_FPRI_CTRL_NV << 8) | 6)
76#define TEGRA_MC_CLIENT_PPCSAHBDMAR ((TEGRA_MC_FPRI_CTRL_PPCS << 8) | 0)
77#define TEGRA_MC_CLIENT_PPCSAHBSLVR ((TEGRA_MC_FPRI_CTRL_PPCS << 8) | 2)
78#define TEGRA_MC_CLIENT_PPCSAHBDMAW ((TEGRA_MC_FPRI_CTRL_PPCS << 8) | 4)
79#define TEGRA_MC_CLIENT_PPCSAHBSLVW ((TEGRA_MC_FPRI_CTRL_PPCS << 8) | 6)
80#define TEGRA_MC_CLIENT_VDEBSEVR ((TEGRA_MC_FPRI_CTRL_VDE << 8) | 0)
81#define TEGRA_MC_CLIENT_VDEMBER ((TEGRA_MC_FPRI_CTRL_VDE << 8) | 2)
82#define TEGRA_MC_CLIENT_VDEMCER ((TEGRA_MC_FPRI_CTRL_VDE << 8) | 4)
83#define TEGRA_MC_CLIENT_VDETPER ((TEGRA_MC_FPRI_CTRL_VDE << 8) | 6)
84#define TEGRA_MC_CLIENT_VDEBSEVW ((TEGRA_MC_FPRI_CTRL_VDE << 8) | 8)
85#define TEGRA_MC_CLIENT_VDEMBEW ((TEGRA_MC_FPRI_CTRL_VDE << 8) | 10)
86#define TEGRA_MC_CLIENT_VDETPMW ((TEGRA_MC_FPRI_CTRL_VDE << 8) | 12)
87#define TEGRA_MC_CLIENT_VIRUV ((TEGRA_MC_FPRI_CTRL_VI << 8) | 0)
88#define TEGRA_MC_CLIENT_VIWSB ((TEGRA_MC_FPRI_CTRL_VI << 8) | 2)
89#define TEGRA_MC_CLIENT_VIWU ((TEGRA_MC_FPRI_CTRL_VI << 8) | 4)
90#define TEGRA_MC_CLIENT_VIWV ((TEGRA_MC_FPRI_CTRL_VI << 8) | 6)
91#define TEGRA_MC_CLIENT_VIWY ((TEGRA_MC_FPRI_CTRL_VI << 8) | 8)
92
93#define TEGRA_MC_PRIO_LOWEST 0
94#define TEGRA_MC_PRIO_LOW 1
95#define TEGRA_MC_PRIO_MED 2
96#define TEGRA_MC_PRIO_HIGH 3
97#define TEGRA_MC_PRIO_MASK 3
98
99void tegra_mc_set_priority(unsigned long client, unsigned long prio);
100
101#else
102 /* !!!FIXME!!! IMPLEMENT ME */
103#define tegra_mc_set_priority(client, prio) \
104 do { /* nothing for now */ } while (0)
105#endif
106
107int tegra_mc_get_tiled_memory_bandwidth_multiplier(void);
108
109#endif
diff --git a/arch/arm/mach-tegra/include/mach/memory.h b/arch/arm/mach-tegra/include/mach/memory.h
new file mode 100644
index 00000000000..5f51066482e
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/memory.h
@@ -0,0 +1,42 @@
1/*
2 * arch/arm/mach-tegra/include/mach/memory.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2011 NVIDIA Corporation.
6 *
7 * Author:
8 * Colin Cross <ccross@google.com>
9 * Erik Gilling <konkers@google.com>
10 *
11 * This software is licensed under the terms of the GNU General Public
12 * License version 2, as published by the Free Software Foundation, and
13 * may be copied, distributed, and modified under those terms.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 */
21
22#ifndef __MACH_TEGRA_MEMORY_H
23#define __MACH_TEGRA_MEMORY_H
24
25/* physical offset of RAM */
26#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
27#define PLAT_PHYS_OFFSET UL(0)
28#else
29#define PLAT_PHYS_OFFSET UL(0x80000000)
30#endif
31
32/*
33 * Unaligned DMA causes tegra dma to place data on 4-byte boundary after
34 * expected address. Call to skb_reserve(skb, NET_IP_ALIGN) was causing skb
35 * buffers in usbnet.c to become unaligned.
36 */
37#define NET_IP_ALIGN 0
38
39#define CONSISTENT_DMA_SIZE (14 * SZ_1M)
40
41#endif
42
diff --git a/arch/arm/mach-tegra/include/mach/nand.h b/arch/arm/mach-tegra/include/mach/nand.h
new file mode 100644
index 00000000000..91ad7d1c9ae
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/nand.h
@@ -0,0 +1,55 @@
1/*
2 * arch/arm/mach-tegra/include/mach/nand.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 * Dima Zavin <dmitriyz@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#ifndef __MACH_TEGRA_NAND_H
22#define __MACH_TEGRA_NAND_H
23
24struct tegra_nand_chip_parms {
25 uint8_t vendor_id;
26 uint8_t device_id;
27 uint32_t flags;
28 uint8_t read_id_fourth_byte;
29 uint32_t capacity;
30
31 /* all timing info is in nanoseconds */
32 struct {
33 uint32_t trp;
34 uint32_t trh;
35 uint32_t twp;
36 uint32_t twh;
37 uint32_t tcs;
38 uint32_t twhr;
39 uint32_t tcr_tar_trr;
40 uint32_t twb;
41 uint32_t trp_resp;
42 uint32_t tadl;
43 } timing;
44};
45
46struct tegra_nand_platform {
47 uint8_t max_chips;
48 struct tegra_nand_chip_parms *chip_parms;
49 unsigned int nr_chip_parms;
50 struct mtd_partition *parts;
51 unsigned int nr_parts;
52 int wp_gpio;
53};
54
55#endif
diff --git a/arch/arm/mach-tegra/include/mach/nvmap.h b/arch/arm/mach-tegra/include/mach/nvmap.h
new file mode 100644
index 00000000000..88f913fc29d
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/nvmap.h
@@ -0,0 +1,158 @@
1/*
2 * arch/arm/mach-tegra/include/mach/nvmap.h
3 *
4 * structure declarations for nvmem and nvmap user-space ioctls
5 *
6 * Copyright (c) 2009-2011, NVIDIA Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
21 */
22
23#include <linux/ioctl.h>
24#include <linux/file.h>
25#include <linux/rbtree.h>
26
27#if !defined(__KERNEL__)
28#define __user
29#endif
30
31#ifndef __NVMAP_H
32#define __NVMAP_H
33
34#define NVMAP_HEAP_SYSMEM (1ul<<31)
35#define NVMAP_HEAP_IOVMM (1ul<<30)
36
37/* common carveout heaps */
38#define NVMAP_HEAP_CARVEOUT_IRAM (1ul<<29)
39#define NVMAP_HEAP_CARVEOUT_VPR (1ul<<28)
40#define NVMAP_HEAP_CARVEOUT_GENERIC (1ul<<0)
41
42#define NVMAP_HEAP_CARVEOUT_MASK (NVMAP_HEAP_IOVMM - 1)
43
44/* allocation flags */
45#define NVMAP_HANDLE_UNCACHEABLE (0x0ul << 0)
46#define NVMAP_HANDLE_WRITE_COMBINE (0x1ul << 0)
47#define NVMAP_HANDLE_INNER_CACHEABLE (0x2ul << 0)
48#define NVMAP_HANDLE_CACHEABLE (0x3ul << 0)
49#define NVMAP_HANDLE_CACHE_FLAG (0x3ul << 0)
50
51#define NVMAP_HANDLE_SECURE (0x1ul << 2)
52
53
54#if defined(__KERNEL__)
55
56#if defined(CONFIG_TEGRA_NVMAP)
57struct nvmap_handle;
58struct nvmap_client;
59struct nvmap_device;
60#define nvmap_ref_to_handle(_ref) (*(struct nvmap_handle **)(_ref))
61/* Convert User space handle to Kernel. */
62#define nvmap_convert_handle_u2k(h) (h)
63#elif defined(CONFIG_ION_TEGRA)
64/* For Ion Mem Manager support through nvmap_* API's. */
65#include "../../../../../drivers/gpu/ion/ion_priv.h"
66
67#define nvmap_client ion_client
68#define nvmap_device ion_device
69#define nvmap_handle ion_handle
70#define nvmap_handle_ref ion_handle
71#define nvmap_ref_to_handle(_ref) (struct ion_handle *)_ref
72/* Convert User space handle to Kernel. */
73#define nvmap_convert_handle_u2k(h) ({ \
74 if ((u32)h >= TASK_SIZE) { \
75 pr_err("Invalid user space handle."); \
76 BUG(); \
77 } \
78 (*((u32 *)h)); })
79#endif
80
81#define nvmap_id_to_handle(_id) ((struct nvmap_handle *)(_id))
82
83
84struct nvmap_pinarray_elem {
85 __u32 patch_mem;
86 __u32 patch_offset;
87 __u32 pin_mem;
88 __u32 pin_offset;
89 __u32 reloc_shift;
90};
91
92#if defined(CONFIG_TEGRA_NVMAP)
93/* handle_ref objects are client-local references to an nvmap_handle;
94 * they are distinct objects so that handles can be unpinned and
95 * unreferenced the correct number of times when a client abnormally
96 * terminates */
97struct nvmap_handle_ref {
98 struct nvmap_handle *handle;
99 struct rb_node node;
100 atomic_t dupes; /* number of times to free on file close */
101 atomic_t pin; /* number of times to unpin on free */
102};
103#endif
104
105struct nvmap_client *nvmap_create_client(struct nvmap_device *dev,
106 const char *name);
107
108struct nvmap_handle_ref *nvmap_alloc(struct nvmap_client *client, size_t size,
109 size_t align, unsigned int flags,
110 unsigned int heap_mask);
111
112void nvmap_free(struct nvmap_client *client, struct nvmap_handle_ref *r);
113
114void *nvmap_mmap(struct nvmap_handle_ref *r);
115
116void nvmap_munmap(struct nvmap_handle_ref *r, void *addr);
117
118struct nvmap_client *nvmap_client_get_file(int fd);
119
120struct nvmap_client *nvmap_client_get(struct nvmap_client *client);
121
122void nvmap_client_put(struct nvmap_client *c);
123
124phys_addr_t nvmap_pin(struct nvmap_client *c, struct nvmap_handle_ref *r);
125
126phys_addr_t nvmap_handle_address(struct nvmap_client *c, unsigned long id);
127
128void nvmap_unpin(struct nvmap_client *client, struct nvmap_handle_ref *r);
129
130int nvmap_pin_array(struct nvmap_client *client, struct nvmap_handle *gather,
131 const struct nvmap_pinarray_elem *arr, int nr,
132 struct nvmap_handle **unique);
133
134void nvmap_unpin_handles(struct nvmap_client *client,
135 struct nvmap_handle **h, int nr);
136
137int nvmap_patch_word(struct nvmap_client *client,
138 struct nvmap_handle *patch,
139 u32 patch_offset, u32 patch_value);
140
141struct nvmap_platform_carveout {
142 const char *name;
143 unsigned int usage_mask;
144 phys_addr_t base;
145 size_t size;
146 size_t buddy_size;
147};
148
149struct nvmap_platform_data {
150 const struct nvmap_platform_carveout *carveouts;
151 unsigned int nr_carveouts;
152};
153
154extern struct nvmap_device *nvmap_dev;
155
156#endif
157
158#endif
diff --git a/arch/arm/mach-tegra/include/mach/pci.h b/arch/arm/mach-tegra/include/mach/pci.h
new file mode 100644
index 00000000000..388ad320775
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/pci.h
@@ -0,0 +1,38 @@
1/*
2 * arch/arm/mach-tegra/include/mach/pci.h
3 *
4 * Header file containing constants for the tegra PCIe driver.
5 *
6 * Copyright (c) 2011, NVIDIA Corporation.
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 */
21
22#ifndef __MACH_PCI_H
23#define __MACH_PCI_H
24
25#include <linux/pci.h>
26
27#ifdef CONFIG_ARCH_TEGRA_2x_SOC
28 #define MAX_PCIE_SUPPORTED_PORTS 2
29#else
30 #define MAX_PCIE_SUPPORTED_PORTS 3
31#endif
32
33struct tegra_pci_platform_data {
34 int port_status[MAX_PCIE_SUPPORTED_PORTS];
35 bool use_dock_detect;
36 int gpio;
37};
38#endif
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-t2.h b/arch/arm/mach-tegra/include/mach/pinmux-t2.h
new file mode 100644
index 00000000000..4c262634726
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/pinmux-t2.h
@@ -0,0 +1,184 @@
1/*
2 * linux/arch/arm/mach-tegra/include/mach/pinmux-t2.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef __MACH_TEGRA_PINMUX_T2_H
18#define __MACH_TEGRA_PINMUX_T2_H
19
20enum tegra_pingroup {
21 TEGRA_PINGROUP_ATA = 0,
22 TEGRA_PINGROUP_ATB,
23 TEGRA_PINGROUP_ATC,
24 TEGRA_PINGROUP_ATD,
25 TEGRA_PINGROUP_ATE,
26 TEGRA_PINGROUP_CDEV1,
27 TEGRA_PINGROUP_CDEV2,
28 TEGRA_PINGROUP_CRTP,
29 TEGRA_PINGROUP_CSUS,
30 TEGRA_PINGROUP_DAP1,
31 TEGRA_PINGROUP_DAP2,
32 TEGRA_PINGROUP_DAP3,
33 TEGRA_PINGROUP_DAP4,
34 TEGRA_PINGROUP_DDC,
35 TEGRA_PINGROUP_DTA,
36 TEGRA_PINGROUP_DTB,
37 TEGRA_PINGROUP_DTC,
38 TEGRA_PINGROUP_DTD,
39 TEGRA_PINGROUP_DTE,
40 TEGRA_PINGROUP_DTF,
41 TEGRA_PINGROUP_GMA,
42 TEGRA_PINGROUP_GMB,
43 TEGRA_PINGROUP_GMC,
44 TEGRA_PINGROUP_GMD,
45 TEGRA_PINGROUP_GME,
46 TEGRA_PINGROUP_GPU,
47 TEGRA_PINGROUP_GPU7,
48 TEGRA_PINGROUP_GPV,
49 TEGRA_PINGROUP_HDINT,
50 TEGRA_PINGROUP_I2CP,
51 TEGRA_PINGROUP_IRRX,
52 TEGRA_PINGROUP_IRTX,
53 TEGRA_PINGROUP_KBCA,
54 TEGRA_PINGROUP_KBCB,
55 TEGRA_PINGROUP_KBCC,
56 TEGRA_PINGROUP_KBCD,
57 TEGRA_PINGROUP_KBCE,
58 TEGRA_PINGROUP_KBCF,
59 TEGRA_PINGROUP_LCSN,
60 TEGRA_PINGROUP_LD0,
61 TEGRA_PINGROUP_LD1,
62 TEGRA_PINGROUP_LD10,
63 TEGRA_PINGROUP_LD11,
64 TEGRA_PINGROUP_LD12,
65 TEGRA_PINGROUP_LD13,
66 TEGRA_PINGROUP_LD14,
67 TEGRA_PINGROUP_LD15,
68 TEGRA_PINGROUP_LD16,
69 TEGRA_PINGROUP_LD17,
70 TEGRA_PINGROUP_LD2,
71 TEGRA_PINGROUP_LD3,
72 TEGRA_PINGROUP_LD4,
73 TEGRA_PINGROUP_LD5,
74 TEGRA_PINGROUP_LD6,
75 TEGRA_PINGROUP_LD7,
76 TEGRA_PINGROUP_LD8,
77 TEGRA_PINGROUP_LD9,
78 TEGRA_PINGROUP_LDC,
79 TEGRA_PINGROUP_LDI,
80 TEGRA_PINGROUP_LHP0,
81 TEGRA_PINGROUP_LHP1,
82 TEGRA_PINGROUP_LHP2,
83 TEGRA_PINGROUP_LHS,
84 TEGRA_PINGROUP_LM0,
85 TEGRA_PINGROUP_LM1,
86 TEGRA_PINGROUP_LPP,
87 TEGRA_PINGROUP_LPW0,
88 TEGRA_PINGROUP_LPW1,
89 TEGRA_PINGROUP_LPW2,
90 TEGRA_PINGROUP_LSC0,
91 TEGRA_PINGROUP_LSC1,
92 TEGRA_PINGROUP_LSCK,
93 TEGRA_PINGROUP_LSDA,
94 TEGRA_PINGROUP_LSDI,
95 TEGRA_PINGROUP_LSPI,
96 TEGRA_PINGROUP_LVP0,
97 TEGRA_PINGROUP_LVP1,
98 TEGRA_PINGROUP_LVS,
99 TEGRA_PINGROUP_OWC,
100 TEGRA_PINGROUP_PMC,
101 TEGRA_PINGROUP_PTA,
102 TEGRA_PINGROUP_RM,
103 TEGRA_PINGROUP_SDB,
104 TEGRA_PINGROUP_SDC,
105 TEGRA_PINGROUP_SDD,
106 TEGRA_PINGROUP_SDIO1,
107 TEGRA_PINGROUP_SLXA,
108 TEGRA_PINGROUP_SLXC,
109 TEGRA_PINGROUP_SLXD,
110 TEGRA_PINGROUP_SLXK,
111 TEGRA_PINGROUP_SPDI,
112 TEGRA_PINGROUP_SPDO,
113 TEGRA_PINGROUP_SPIA,
114 TEGRA_PINGROUP_SPIB,
115 TEGRA_PINGROUP_SPIC,
116 TEGRA_PINGROUP_SPID,
117 TEGRA_PINGROUP_SPIE,
118 TEGRA_PINGROUP_SPIF,
119 TEGRA_PINGROUP_SPIG,
120 TEGRA_PINGROUP_SPIH,
121 TEGRA_PINGROUP_UAA,
122 TEGRA_PINGROUP_UAB,
123 TEGRA_PINGROUP_UAC,
124 TEGRA_PINGROUP_UAD,
125 TEGRA_PINGROUP_UCA,
126 TEGRA_PINGROUP_UCB,
127 TEGRA_PINGROUP_UDA,
128 /* these pin groups only have pullup and pull down control */
129 TEGRA_PINGROUP_CK32,
130 TEGRA_PINGROUP_DDRC,
131 TEGRA_PINGROUP_PMCA,
132 TEGRA_PINGROUP_PMCB,
133 TEGRA_PINGROUP_PMCC,
134 TEGRA_PINGROUP_PMCD,
135 TEGRA_PINGROUP_PMCE,
136 TEGRA_PINGROUP_XM2C,
137 TEGRA_PINGROUP_XM2D,
138 TEGRA_MAX_PINGROUP,
139};
140
141enum tegra_drive_pingroup {
142 TEGRA_DRIVE_PINGROUP_AO1 = 0,
143 TEGRA_DRIVE_PINGROUP_AO2,
144 TEGRA_DRIVE_PINGROUP_AT1,
145 TEGRA_DRIVE_PINGROUP_AT2,
146 TEGRA_DRIVE_PINGROUP_CDEV1,
147 TEGRA_DRIVE_PINGROUP_CDEV2,
148 TEGRA_DRIVE_PINGROUP_CSUS,
149 TEGRA_DRIVE_PINGROUP_DAP1,
150 TEGRA_DRIVE_PINGROUP_DAP2,
151 TEGRA_DRIVE_PINGROUP_DAP3,
152 TEGRA_DRIVE_PINGROUP_DAP4,
153 TEGRA_DRIVE_PINGROUP_DBG,
154 TEGRA_DRIVE_PINGROUP_LCD1,
155 TEGRA_DRIVE_PINGROUP_LCD2,
156 TEGRA_DRIVE_PINGROUP_SDMMC2,
157 TEGRA_DRIVE_PINGROUP_SDMMC3,
158 TEGRA_DRIVE_PINGROUP_SPI,
159 TEGRA_DRIVE_PINGROUP_UAA,
160 TEGRA_DRIVE_PINGROUP_UAB,
161 TEGRA_DRIVE_PINGROUP_UART2,
162 TEGRA_DRIVE_PINGROUP_UART3,
163 TEGRA_DRIVE_PINGROUP_VI1,
164 TEGRA_DRIVE_PINGROUP_VI2,
165 TEGRA_DRIVE_PINGROUP_XM2A,
166 TEGRA_DRIVE_PINGROUP_XM2C,
167 TEGRA_DRIVE_PINGROUP_XM2D,
168 TEGRA_DRIVE_PINGROUP_XM2CLK,
169 TEGRA_DRIVE_PINGROUP_MEMCOMP,
170 TEGRA_DRIVE_PINGROUP_SDIO1,
171 TEGRA_DRIVE_PINGROUP_CRT,
172 TEGRA_DRIVE_PINGROUP_DDC,
173 TEGRA_DRIVE_PINGROUP_GMA,
174 TEGRA_DRIVE_PINGROUP_GMB,
175 TEGRA_DRIVE_PINGROUP_GMC,
176 TEGRA_DRIVE_PINGROUP_GMD,
177 TEGRA_DRIVE_PINGROUP_GME,
178 TEGRA_DRIVE_PINGROUP_OWR,
179 TEGRA_DRIVE_PINGROUP_UAD,
180 TEGRA_MAX_DRIVE_PINGROUP,
181};
182
183#endif
184
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-t3.h b/arch/arm/mach-tegra/include/mach/pinmux-t3.h
new file mode 100644
index 00000000000..12fd5e8ffc1
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/pinmux-t3.h
@@ -0,0 +1,321 @@
1/*
2 * linux/arch/arm/mach-tegra/include/mach/pinmux-t3.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2011 NVIDIA Corporation.
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#ifndef __MACH_TEGRA_PINMUX_T3_H
19#define __MACH_TEGRA_PINMUX_T3_H
20
21#define TEGRA_PINMUX_HAS_IO_DIRECTION 1
22
23enum tegra_pingroup {
24 TEGRA_PINGROUP_ULPI_DATA0 = 0,
25 TEGRA_PINGROUP_ULPI_DATA1,
26 TEGRA_PINGROUP_ULPI_DATA2,
27 TEGRA_PINGROUP_ULPI_DATA3,
28 TEGRA_PINGROUP_ULPI_DATA4,
29 TEGRA_PINGROUP_ULPI_DATA5,
30 TEGRA_PINGROUP_ULPI_DATA6,
31 TEGRA_PINGROUP_ULPI_DATA7,
32 TEGRA_PINGROUP_ULPI_CLK,
33 TEGRA_PINGROUP_ULPI_DIR,
34 TEGRA_PINGROUP_ULPI_NXT,
35 TEGRA_PINGROUP_ULPI_STP,
36 TEGRA_PINGROUP_DAP3_FS,
37 TEGRA_PINGROUP_DAP3_DIN,
38 TEGRA_PINGROUP_DAP3_DOUT,
39 TEGRA_PINGROUP_DAP3_SCLK,
40 TEGRA_PINGROUP_GPIO_PV0,
41 TEGRA_PINGROUP_GPIO_PV1,
42 TEGRA_PINGROUP_SDMMC1_CLK,
43 TEGRA_PINGROUP_SDMMC1_CMD,
44 TEGRA_PINGROUP_SDMMC1_DAT3,
45 TEGRA_PINGROUP_SDMMC1_DAT2,
46 TEGRA_PINGROUP_SDMMC1_DAT1,
47 TEGRA_PINGROUP_SDMMC1_DAT0,
48 TEGRA_PINGROUP_GPIO_PV2,
49 TEGRA_PINGROUP_GPIO_PV3,
50 TEGRA_PINGROUP_CLK2_OUT,
51 TEGRA_PINGROUP_CLK2_REQ,
52 TEGRA_PINGROUP_LCD_PWR1,
53 TEGRA_PINGROUP_LCD_PWR2,
54 TEGRA_PINGROUP_LCD_SDIN,
55 TEGRA_PINGROUP_LCD_SDOUT,
56 TEGRA_PINGROUP_LCD_WR_N,
57 TEGRA_PINGROUP_LCD_CS0_N,
58 TEGRA_PINGROUP_LCD_DC0,
59 TEGRA_PINGROUP_LCD_SCK,
60 TEGRA_PINGROUP_LCD_PWR0,
61 TEGRA_PINGROUP_LCD_PCLK,
62 TEGRA_PINGROUP_LCD_DE,
63 TEGRA_PINGROUP_LCD_HSYNC,
64 TEGRA_PINGROUP_LCD_VSYNC,
65 TEGRA_PINGROUP_LCD_D0,
66 TEGRA_PINGROUP_LCD_D1,
67 TEGRA_PINGROUP_LCD_D2,
68 TEGRA_PINGROUP_LCD_D3,
69 TEGRA_PINGROUP_LCD_D4,
70 TEGRA_PINGROUP_LCD_D5,
71 TEGRA_PINGROUP_LCD_D6,
72 TEGRA_PINGROUP_LCD_D7,
73 TEGRA_PINGROUP_LCD_D8,
74 TEGRA_PINGROUP_LCD_D9,
75 TEGRA_PINGROUP_LCD_D10,
76 TEGRA_PINGROUP_LCD_D11,
77 TEGRA_PINGROUP_LCD_D12,
78 TEGRA_PINGROUP_LCD_D13,
79 TEGRA_PINGROUP_LCD_D14,
80 TEGRA_PINGROUP_LCD_D15,
81 TEGRA_PINGROUP_LCD_D16,
82 TEGRA_PINGROUP_LCD_D17,
83 TEGRA_PINGROUP_LCD_D18,
84 TEGRA_PINGROUP_LCD_D19,
85 TEGRA_PINGROUP_LCD_D20,
86 TEGRA_PINGROUP_LCD_D21,
87 TEGRA_PINGROUP_LCD_D22,
88 TEGRA_PINGROUP_LCD_D23,
89 TEGRA_PINGROUP_LCD_CS1_N,
90 TEGRA_PINGROUP_LCD_M1,
91 TEGRA_PINGROUP_LCD_DC1,
92 TEGRA_PINGROUP_HDMI_INT,
93 TEGRA_PINGROUP_DDC_SCL,
94 TEGRA_PINGROUP_DDC_SDA,
95 TEGRA_PINGROUP_CRT_HSYNC,
96 TEGRA_PINGROUP_CRT_VSYNC,
97 TEGRA_PINGROUP_VI_D0,
98 TEGRA_PINGROUP_VI_D1,
99 TEGRA_PINGROUP_VI_D2,
100 TEGRA_PINGROUP_VI_D3,
101 TEGRA_PINGROUP_VI_D4,
102 TEGRA_PINGROUP_VI_D5,
103 TEGRA_PINGROUP_VI_D6,
104 TEGRA_PINGROUP_VI_D7,
105 TEGRA_PINGROUP_VI_D8,
106 TEGRA_PINGROUP_VI_D9,
107 TEGRA_PINGROUP_VI_D10,
108 TEGRA_PINGROUP_VI_D11,
109 TEGRA_PINGROUP_VI_PCLK,
110 TEGRA_PINGROUP_VI_MCLK,
111 TEGRA_PINGROUP_VI_VSYNC,
112 TEGRA_PINGROUP_VI_HSYNC,
113 TEGRA_PINGROUP_UART2_RXD,
114 TEGRA_PINGROUP_UART2_TXD,
115 TEGRA_PINGROUP_UART2_RTS_N,
116 TEGRA_PINGROUP_UART2_CTS_N,
117 TEGRA_PINGROUP_UART3_TXD,
118 TEGRA_PINGROUP_UART3_RXD,
119 TEGRA_PINGROUP_UART3_CTS_N,
120 TEGRA_PINGROUP_UART3_RTS_N,
121 TEGRA_PINGROUP_GPIO_PU0,
122 TEGRA_PINGROUP_GPIO_PU1,
123 TEGRA_PINGROUP_GPIO_PU2,
124 TEGRA_PINGROUP_GPIO_PU3,
125 TEGRA_PINGROUP_GPIO_PU4,
126 TEGRA_PINGROUP_GPIO_PU5,
127 TEGRA_PINGROUP_GPIO_PU6,
128 TEGRA_PINGROUP_GEN1_I2C_SDA,
129 TEGRA_PINGROUP_GEN1_I2C_SCL,
130 TEGRA_PINGROUP_DAP4_FS,
131 TEGRA_PINGROUP_DAP4_DIN,
132 TEGRA_PINGROUP_DAP4_DOUT,
133 TEGRA_PINGROUP_DAP4_SCLK,
134 TEGRA_PINGROUP_CLK3_OUT,
135 TEGRA_PINGROUP_CLK3_REQ,
136 TEGRA_PINGROUP_GMI_WP_N,
137 TEGRA_PINGROUP_GMI_IORDY,
138 TEGRA_PINGROUP_GMI_WAIT,
139 TEGRA_PINGROUP_GMI_ADV_N,
140 TEGRA_PINGROUP_GMI_CLK,
141 TEGRA_PINGROUP_GMI_CS0_N,
142 TEGRA_PINGROUP_GMI_CS1_N,
143 TEGRA_PINGROUP_GMI_CS2_N,
144 TEGRA_PINGROUP_GMI_CS3_N,
145 TEGRA_PINGROUP_GMI_CS4_N,
146 TEGRA_PINGROUP_GMI_CS6_N,
147 TEGRA_PINGROUP_GMI_CS7_N,
148 TEGRA_PINGROUP_GMI_AD0,
149 TEGRA_PINGROUP_GMI_AD1,
150 TEGRA_PINGROUP_GMI_AD2,
151 TEGRA_PINGROUP_GMI_AD3,
152 TEGRA_PINGROUP_GMI_AD4,
153 TEGRA_PINGROUP_GMI_AD5,
154 TEGRA_PINGROUP_GMI_AD6,
155 TEGRA_PINGROUP_GMI_AD7,
156 TEGRA_PINGROUP_GMI_AD8,
157 TEGRA_PINGROUP_GMI_AD9,
158 TEGRA_PINGROUP_GMI_AD10,
159 TEGRA_PINGROUP_GMI_AD11,
160 TEGRA_PINGROUP_GMI_AD12,
161 TEGRA_PINGROUP_GMI_AD13,
162 TEGRA_PINGROUP_GMI_AD14,
163 TEGRA_PINGROUP_GMI_AD15,
164 TEGRA_PINGROUP_GMI_A16,
165 TEGRA_PINGROUP_GMI_A17,
166 TEGRA_PINGROUP_GMI_A18,
167 TEGRA_PINGROUP_GMI_A19,
168 TEGRA_PINGROUP_GMI_WR_N,
169 TEGRA_PINGROUP_GMI_OE_N,
170 TEGRA_PINGROUP_GMI_DQS,
171 TEGRA_PINGROUP_GMI_RST_N,
172 TEGRA_PINGROUP_GEN2_I2C_SCL,
173 TEGRA_PINGROUP_GEN2_I2C_SDA,
174 TEGRA_PINGROUP_SDMMC4_CLK,
175 TEGRA_PINGROUP_SDMMC4_CMD,
176 TEGRA_PINGROUP_SDMMC4_DAT0,
177 TEGRA_PINGROUP_SDMMC4_DAT1,
178 TEGRA_PINGROUP_SDMMC4_DAT2,
179 TEGRA_PINGROUP_SDMMC4_DAT3,
180 TEGRA_PINGROUP_SDMMC4_DAT4,
181 TEGRA_PINGROUP_SDMMC4_DAT5,
182 TEGRA_PINGROUP_SDMMC4_DAT6,
183 TEGRA_PINGROUP_SDMMC4_DAT7,
184 TEGRA_PINGROUP_SDMMC4_RST_N,
185 TEGRA_PINGROUP_CAM_MCLK,
186 TEGRA_PINGROUP_GPIO_PCC1,
187 TEGRA_PINGROUP_GPIO_PBB0,
188 TEGRA_PINGROUP_CAM_I2C_SCL,
189 TEGRA_PINGROUP_CAM_I2C_SDA,
190 TEGRA_PINGROUP_GPIO_PBB3,
191 TEGRA_PINGROUP_GPIO_PBB4,
192 TEGRA_PINGROUP_GPIO_PBB5,
193 TEGRA_PINGROUP_GPIO_PBB6,
194 TEGRA_PINGROUP_GPIO_PBB7,
195 TEGRA_PINGROUP_GPIO_PCC2,
196 TEGRA_PINGROUP_JTAG_RTCK,
197 TEGRA_PINGROUP_PWR_I2C_SCL,
198 TEGRA_PINGROUP_PWR_I2C_SDA,
199 TEGRA_PINGROUP_KB_ROW0,
200 TEGRA_PINGROUP_KB_ROW1,
201 TEGRA_PINGROUP_KB_ROW2,
202 TEGRA_PINGROUP_KB_ROW3,
203 TEGRA_PINGROUP_KB_ROW4,
204 TEGRA_PINGROUP_KB_ROW5,
205 TEGRA_PINGROUP_KB_ROW6,
206 TEGRA_PINGROUP_KB_ROW7,
207 TEGRA_PINGROUP_KB_ROW8,
208 TEGRA_PINGROUP_KB_ROW9,
209 TEGRA_PINGROUP_KB_ROW10,
210 TEGRA_PINGROUP_KB_ROW11,
211 TEGRA_PINGROUP_KB_ROW12,
212 TEGRA_PINGROUP_KB_ROW13,
213 TEGRA_PINGROUP_KB_ROW14,
214 TEGRA_PINGROUP_KB_ROW15,
215 TEGRA_PINGROUP_KB_COL0,
216 TEGRA_PINGROUP_KB_COL1,
217 TEGRA_PINGROUP_KB_COL2,
218 TEGRA_PINGROUP_KB_COL3,
219 TEGRA_PINGROUP_KB_COL4,
220 TEGRA_PINGROUP_KB_COL5,
221 TEGRA_PINGROUP_KB_COL6,
222 TEGRA_PINGROUP_KB_COL7,
223 TEGRA_PINGROUP_CLK_32K_OUT,
224 TEGRA_PINGROUP_SYS_CLK_REQ,
225 TEGRA_PINGROUP_CORE_PWR_REQ,
226 TEGRA_PINGROUP_CPU_PWR_REQ,
227 TEGRA_PINGROUP_PWR_INT_N,
228 TEGRA_PINGROUP_CLK_32K_IN,
229 TEGRA_PINGROUP_OWR,
230 TEGRA_PINGROUP_DAP1_FS,
231 TEGRA_PINGROUP_DAP1_DIN,
232 TEGRA_PINGROUP_DAP1_DOUT,
233 TEGRA_PINGROUP_DAP1_SCLK,
234 TEGRA_PINGROUP_CLK1_REQ,
235 TEGRA_PINGROUP_CLK1_OUT,
236 TEGRA_PINGROUP_SPDIF_IN,
237 TEGRA_PINGROUP_SPDIF_OUT,
238 TEGRA_PINGROUP_DAP2_FS,
239 TEGRA_PINGROUP_DAP2_DIN,
240 TEGRA_PINGROUP_DAP2_DOUT,
241 TEGRA_PINGROUP_DAP2_SCLK,
242 TEGRA_PINGROUP_SPI2_MOSI,
243 TEGRA_PINGROUP_SPI2_MISO,
244 TEGRA_PINGROUP_SPI2_CS0_N,
245 TEGRA_PINGROUP_SPI2_SCK,
246 TEGRA_PINGROUP_SPI1_MOSI,
247 TEGRA_PINGROUP_SPI1_SCK,
248 TEGRA_PINGROUP_SPI1_CS0_N,
249 TEGRA_PINGROUP_SPI1_MISO,
250 TEGRA_PINGROUP_SPI2_CS1_N,
251 TEGRA_PINGROUP_SPI2_CS2_N,
252 TEGRA_PINGROUP_SDMMC3_CLK,
253 TEGRA_PINGROUP_SDMMC3_CMD,
254 TEGRA_PINGROUP_SDMMC3_DAT0,
255 TEGRA_PINGROUP_SDMMC3_DAT1,
256 TEGRA_PINGROUP_SDMMC3_DAT2,
257 TEGRA_PINGROUP_SDMMC3_DAT3,
258 TEGRA_PINGROUP_SDMMC3_DAT4,
259 TEGRA_PINGROUP_SDMMC3_DAT5,
260 TEGRA_PINGROUP_SDMMC3_DAT6,
261 TEGRA_PINGROUP_SDMMC3_DAT7,
262 TEGRA_PINGROUP_PEX_L0_PRSNT_N,
263 TEGRA_PINGROUP_PEX_L0_RST_N,
264 TEGRA_PINGROUP_PEX_L0_CLKREQ_N,
265 TEGRA_PINGROUP_PEX_WAKE_N,
266 TEGRA_PINGROUP_PEX_L1_PRSNT_N,
267 TEGRA_PINGROUP_PEX_L1_RST_N,
268 TEGRA_PINGROUP_PEX_L1_CLKREQ_N,
269 TEGRA_PINGROUP_PEX_L2_PRSNT_N,
270 TEGRA_PINGROUP_PEX_L2_RST_N,
271 TEGRA_PINGROUP_PEX_L2_CLKREQ_N,
272 TEGRA_PINGROUP_HDMI_CEC,
273 TEGRA_MAX_PINGROUP,
274};
275
276enum tegra_drive_pingroup {
277 TEGRA_DRIVE_PINGROUP_AO1 = 0,
278 TEGRA_DRIVE_PINGROUP_AO2,
279 TEGRA_DRIVE_PINGROUP_AT1,
280 TEGRA_DRIVE_PINGROUP_AT2,
281 TEGRA_DRIVE_PINGROUP_AT3,
282 TEGRA_DRIVE_PINGROUP_AT4,
283 TEGRA_DRIVE_PINGROUP_AT5,
284 TEGRA_DRIVE_PINGROUP_CDEV1,
285 TEGRA_DRIVE_PINGROUP_CDEV2,
286 TEGRA_DRIVE_PINGROUP_CSUS,
287 TEGRA_DRIVE_PINGROUP_DAP1,
288 TEGRA_DRIVE_PINGROUP_DAP2,
289 TEGRA_DRIVE_PINGROUP_DAP3,
290 TEGRA_DRIVE_PINGROUP_DAP4,
291 TEGRA_DRIVE_PINGROUP_DBG,
292 TEGRA_DRIVE_PINGROUP_LCD1,
293 TEGRA_DRIVE_PINGROUP_LCD2,
294 TEGRA_DRIVE_PINGROUP_SDIO2,
295 TEGRA_DRIVE_PINGROUP_SDIO3,
296 TEGRA_DRIVE_PINGROUP_SPI,
297 TEGRA_DRIVE_PINGROUP_UAA,
298 TEGRA_DRIVE_PINGROUP_UAB,
299 TEGRA_DRIVE_PINGROUP_UART2,
300 TEGRA_DRIVE_PINGROUP_UART3,
301 TEGRA_DRIVE_PINGROUP_VI1,
302 TEGRA_DRIVE_PINGROUP_SDIO1,
303 TEGRA_DRIVE_PINGROUP_CRT,
304 TEGRA_DRIVE_PINGROUP_DDC,
305 TEGRA_DRIVE_PINGROUP_GMA,
306 TEGRA_DRIVE_PINGROUP_GMB,
307 TEGRA_DRIVE_PINGROUP_GMC,
308 TEGRA_DRIVE_PINGROUP_GMD,
309 TEGRA_DRIVE_PINGROUP_GME,
310 TEGRA_DRIVE_PINGROUP_GMF,
311 TEGRA_DRIVE_PINGROUP_GMG,
312 TEGRA_DRIVE_PINGROUP_GMH,
313 TEGRA_DRIVE_PINGROUP_OWR,
314 TEGRA_DRIVE_PINGROUP_UAD,
315 TEGRA_DRIVE_PINGROUP_GPV,
316 TEGRA_DRIVE_PINGROUP_DEV3,
317 TEGRA_DRIVE_PINGROUP_CEC,
318 TEGRA_MAX_DRIVE_PINGROUP,
319};
320
321#endif
diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h
new file mode 100644
index 00000000000..f485d0bb072
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/pinmux.h
@@ -0,0 +1,375 @@
1/*
2 * linux/arch/arm/mach-tegra/include/mach/pinmux.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2011 NVIDIA Corporation.
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#ifndef __MACH_TEGRA_PINMUX_H
19#define __MACH_TEGRA_PINMUX_H
20
21#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
22#include "pinmux-t2.h"
23#elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
24#include "pinmux-t3.h"
25#else
26#error "Undefined Tegra architecture"
27#endif
28
29#define TEGRA_MUX_LIST \
30 TEGRA_MUX(NONE) \
31 TEGRA_MUX(AHB_CLK) \
32 TEGRA_MUX(APB_CLK) \
33 TEGRA_MUX(AUDIO_SYNC) \
34 TEGRA_MUX(CRT) \
35 TEGRA_MUX(DAP1) \
36 TEGRA_MUX(DAP2) \
37 TEGRA_MUX(DAP3) \
38 TEGRA_MUX(DAP4) \
39 TEGRA_MUX(DAP5) \
40 TEGRA_MUX(DISPLAYA) \
41 TEGRA_MUX(DISPLAYB) \
42 TEGRA_MUX(EMC_TEST0_DLL) \
43 TEGRA_MUX(EMC_TEST1_DLL) \
44 TEGRA_MUX(GMI) \
45 TEGRA_MUX(GMI_INT) \
46 TEGRA_MUX(HDMI) \
47 TEGRA_MUX(I2C1) \
48 TEGRA_MUX(I2C2) \
49 TEGRA_MUX(I2C3) \
50 TEGRA_MUX(IDE) \
51 TEGRA_MUX(IRDA) \
52 TEGRA_MUX(KBC) \
53 TEGRA_MUX(MIO) \
54 TEGRA_MUX(MIPI_HS) \
55 TEGRA_MUX(NAND) \
56 TEGRA_MUX(OSC) \
57 TEGRA_MUX(OWR) \
58 TEGRA_MUX(PCIE) \
59 TEGRA_MUX(PLLA_OUT) \
60 TEGRA_MUX(PLLC_OUT1) \
61 TEGRA_MUX(PLLM_OUT1) \
62 TEGRA_MUX(PLLP_OUT2) \
63 TEGRA_MUX(PLLP_OUT3) \
64 TEGRA_MUX(PLLP_OUT4) \
65 TEGRA_MUX(PWM) \
66 TEGRA_MUX(PWR_INTR) \
67 TEGRA_MUX(PWR_ON) \
68 TEGRA_MUX(RTCK) \
69 TEGRA_MUX(SDIO1) \
70 TEGRA_MUX(SDIO2) \
71 TEGRA_MUX(SDIO3) \
72 TEGRA_MUX(SDIO4) \
73 TEGRA_MUX(SFLASH) \
74 TEGRA_MUX(SPDIF) \
75 TEGRA_MUX(SPI1) \
76 TEGRA_MUX(SPI2) \
77 TEGRA_MUX(SPI2_ALT) \
78 TEGRA_MUX(SPI3) \
79 TEGRA_MUX(SPI4) \
80 TEGRA_MUX(TRACE) \
81 TEGRA_MUX(TWC) \
82 TEGRA_MUX(UARTA) \
83 TEGRA_MUX(UARTB) \
84 TEGRA_MUX(UARTC) \
85 TEGRA_MUX(UARTD) \
86 TEGRA_MUX(UARTE) \
87 TEGRA_MUX(ULPI) \
88 TEGRA_MUX(VI) \
89 TEGRA_MUX(VI_SENSOR_CLK) \
90 TEGRA_MUX(XIO) \
91 /* End of Tegra2 MUX selectors */ \
92 TEGRA_MUX(BLINK) \
93 TEGRA_MUX(CEC) \
94 TEGRA_MUX(CLK12) \
95 TEGRA_MUX(DAP) \
96 TEGRA_MUX(DAPSDMMC2) \
97 TEGRA_MUX(DDR) \
98 TEGRA_MUX(DEV3) \
99 TEGRA_MUX(DTV) \
100 TEGRA_MUX(VI_ALT1) \
101 TEGRA_MUX(VI_ALT2) \
102 TEGRA_MUX(VI_ALT3) \
103 TEGRA_MUX(EMC_DLL) \
104 TEGRA_MUX(EXTPERIPH1) \
105 TEGRA_MUX(EXTPERIPH2) \
106 TEGRA_MUX(EXTPERIPH3) \
107 TEGRA_MUX(GMI_ALT) \
108 TEGRA_MUX(HDA) \
109 TEGRA_MUX(HSI) \
110 TEGRA_MUX(I2C4) \
111 TEGRA_MUX(I2C5) \
112 TEGRA_MUX(I2CPWR) \
113 TEGRA_MUX(I2S0) \
114 TEGRA_MUX(I2S1) \
115 TEGRA_MUX(I2S2) \
116 TEGRA_MUX(I2S3) \
117 TEGRA_MUX(I2S4) \
118 TEGRA_MUX(NAND_ALT) \
119 TEGRA_MUX(POPSDIO4) \
120 TEGRA_MUX(POPSDMMC4) \
121 TEGRA_MUX(PWM0) \
122 TEGRA_MUX(PWM1) \
123 TEGRA_MUX(PWM2) \
124 TEGRA_MUX(PWM3) \
125 TEGRA_MUX(SATA) \
126 TEGRA_MUX(SPI5) \
127 TEGRA_MUX(SPI6) \
128 TEGRA_MUX(SYSCLK) \
129 TEGRA_MUX(VGP1) \
130 TEGRA_MUX(VGP2) \
131 TEGRA_MUX(VGP3) \
132 TEGRA_MUX(VGP4) \
133 TEGRA_MUX(VGP5) \
134 TEGRA_MUX(VGP6) \
135 /* End of Tegra3 MUX selectors */
136
137enum tegra_mux_func {
138#define TEGRA_MUX(mux) TEGRA_MUX_##mux,
139 TEGRA_MUX_LIST
140#undef TEGRA_MUX
141 TEGRA_MUX_SAFE, /* "Safe" default mux selector */
142 TEGRA_MAX_MUX, /* Number of mux selectors */
143 TEGRA_MUX_TEGRA2_LAST = TEGRA_MUX_XIO,
144 TEGRA_MUX_TEGRA3_LAST = TEGRA_MUX_VGP6,
145
146 /* Mux selector aliases */
147 TEGRA_MUX_I2C = TEGRA_MUX_I2C1,
148 TEGRA_MUX_SDMMC1 = TEGRA_MUX_SDIO1,
149 TEGRA_MUX_SDMMC2 = TEGRA_MUX_SDIO2,
150 TEGRA_MUX_SDMMC3 = TEGRA_MUX_SDIO3,
151 TEGRA_MUX_SDMMC4 = TEGRA_MUX_SDIO4,
152
153 /* Special mux selector values */
154 TEGRA_MUX_INVALID = 0x4000,
155 TEGRA_MUX_RSVD = 0x8000,
156 TEGRA_MUX_RSVD0 = TEGRA_MUX_RSVD,
157 TEGRA_MUX_RSVD1 = 0x8001,
158 TEGRA_MUX_RSVD2 = 0x8002,
159 TEGRA_MUX_RSVD3 = 0x8003,
160 TEGRA_MUX_RSVD4 = 0x8004,
161};
162
163enum tegra_pullupdown {
164 TEGRA_PUPD_NORMAL = 0,
165 TEGRA_PUPD_PULL_DOWN,
166 TEGRA_PUPD_PULL_UP,
167};
168
169enum tegra_tristate {
170 TEGRA_TRI_NORMAL = 0,
171 TEGRA_TRI_TRISTATE = 1,
172};
173
174enum tegra_pin_io {
175 TEGRA_PIN_OUTPUT = 0,
176 TEGRA_PIN_INPUT = 1,
177};
178
179enum tegra_pin_lock {
180 TEGRA_PIN_LOCK_DEFAULT = 0,
181 TEGRA_PIN_LOCK_DISABLE,
182 TEGRA_PIN_LOCK_ENABLE,
183};
184
185enum tegra_pin_od {
186 TEGRA_PIN_OD_DEFAULT = 0,
187 TEGRA_PIN_OD_DISABLE,
188 TEGRA_PIN_OD_ENABLE,
189};
190
191enum tegra_pin_ioreset {
192 TEGRA_PIN_IO_RESET_DEFAULT = 0,
193 TEGRA_PIN_IO_RESET_DISABLE,
194 TEGRA_PIN_IO_RESET_ENABLE,
195};
196
197enum tegra_vddio {
198 TEGRA_VDDIO_BB = 0,
199 TEGRA_VDDIO_LCD,
200 TEGRA_VDDIO_VI,
201 TEGRA_VDDIO_UART,
202 TEGRA_VDDIO_DDR,
203 TEGRA_VDDIO_NAND,
204 TEGRA_VDDIO_SYS,
205 TEGRA_VDDIO_AUDIO,
206 TEGRA_VDDIO_SD,
207#ifndef CONFIG_ARCH_TEGRA_2x_SOC
208 TEGRA_VDDIO_CAM,
209 TEGRA_VDDIO_GMI,
210 TEGRA_VDDIO_PEXCTL,
211 TEGRA_VDDIO_SDMMC1,
212 TEGRA_VDDIO_SDMMC3,
213 TEGRA_VDDIO_SDMMC4,
214#endif
215};
216
217struct tegra_pingroup_config {
218 enum tegra_pingroup pingroup;
219 enum tegra_mux_func func;
220 enum tegra_pullupdown pupd;
221 enum tegra_tristate tristate;
222 enum tegra_pin_io io;
223 enum tegra_pin_lock lock;
224 enum tegra_pin_od od;
225 enum tegra_pin_ioreset ioreset;
226};
227
228enum tegra_slew {
229 TEGRA_SLEW_FASTEST = 0,
230 TEGRA_SLEW_FAST,
231 TEGRA_SLEW_SLOW,
232 TEGRA_SLEW_SLOWEST,
233 TEGRA_MAX_SLEW,
234};
235
236enum tegra_pull_strength {
237 TEGRA_PULL_0 = 0,
238 TEGRA_PULL_1,
239 TEGRA_PULL_2,
240 TEGRA_PULL_3,
241 TEGRA_PULL_4,
242 TEGRA_PULL_5,
243 TEGRA_PULL_6,
244 TEGRA_PULL_7,
245 TEGRA_PULL_8,
246 TEGRA_PULL_9,
247 TEGRA_PULL_10,
248 TEGRA_PULL_11,
249 TEGRA_PULL_12,
250 TEGRA_PULL_13,
251 TEGRA_PULL_14,
252 TEGRA_PULL_15,
253 TEGRA_PULL_16,
254 TEGRA_PULL_17,
255 TEGRA_PULL_18,
256 TEGRA_PULL_19,
257 TEGRA_PULL_20,
258 TEGRA_PULL_21,
259 TEGRA_PULL_22,
260 TEGRA_PULL_23,
261 TEGRA_PULL_24,
262 TEGRA_PULL_25,
263 TEGRA_PULL_26,
264 TEGRA_PULL_27,
265 TEGRA_PULL_28,
266 TEGRA_PULL_29,
267 TEGRA_PULL_30,
268 TEGRA_PULL_31,
269 TEGRA_PULL_32,
270 TEGRA_PULL_33,
271 TEGRA_PULL_34,
272 TEGRA_PULL_35,
273 TEGRA_PULL_36,
274 TEGRA_PULL_37,
275 TEGRA_PULL_38,
276 TEGRA_PULL_39,
277 TEGRA_PULL_40,
278 TEGRA_PULL_41,
279 TEGRA_PULL_42,
280 TEGRA_PULL_43,
281 TEGRA_PULL_44,
282 TEGRA_PULL_45,
283 TEGRA_PULL_46,
284 TEGRA_MAX_PULL,
285};
286
287enum tegra_drive {
288 TEGRA_DRIVE_DIV_8 = 0,
289 TEGRA_DRIVE_DIV_4,
290 TEGRA_DRIVE_DIV_2,
291 TEGRA_DRIVE_DIV_1,
292 TEGRA_MAX_DRIVE,
293};
294
295enum tegra_hsm {
296 TEGRA_HSM_DISABLE = 0,
297 TEGRA_HSM_ENABLE,
298};
299
300enum tegra_schmitt {
301 TEGRA_SCHMITT_DISABLE = 0,
302 TEGRA_SCHMITT_ENABLE,
303};
304
305struct tegra_drive_pingroup_config {
306 enum tegra_drive_pingroup pingroup;
307 enum tegra_hsm hsm;
308 enum tegra_schmitt schmitt;
309 enum tegra_drive drive;
310 enum tegra_pull_strength pull_down;
311 enum tegra_pull_strength pull_up;
312 enum tegra_slew slew_rising;
313 enum tegra_slew slew_falling;
314};
315
316struct tegra_drive_pingroup_desc {
317 const char *name;
318 s16 reg;
319 u8 drvup_offset;
320 u16 drvup_mask;
321 u8 drvdown_offset;
322 u16 drvdown_mask;
323 u8 slewrise_offset;
324 u16 slewrise_mask;
325 u8 slewfall_offset;
326 u16 slewfall_mask;
327};
328
329struct tegra_pingroup_desc {
330 const char *name;
331 int funcs[4];
332 int func_safe;
333 int vddio;
334 s16 tri_reg; /* offset into the TRISTATE_REG_* register bank */
335 s16 mux_reg; /* offset into the PIN_MUX_CTL_* register bank */
336 s16 pupd_reg; /* offset into the PULL_UPDOWN_REG_* register bank */
337 s8 tri_bit; /* offset into the TRISTATE_REG_* register bit */
338 s8 mux_bit; /* offset into the PIN_MUX_CTL_* register bit */
339 s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */
340 s8 lock_bit; /* offser of the LOCK bit into mux register bit */
341 s8 od_bit; /* offset of the OD bit into mux register bit */
342 s8 ioreset_bit; /* offset of the IO_RESET bit into mux register bit */
343 s8 io_default;
344 int gpionr;
345};
346
347extern const struct tegra_pingroup_desc tegra_soc_pingroups[];
348extern const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[];
349extern const int gpio_to_pingroup[];
350
351int tegra_pinmux_get_func(enum tegra_pingroup pg);
352int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
353 enum tegra_tristate tristate);
354int tegra_pinmux_set_io(enum tegra_pingroup pg,
355 enum tegra_pin_io input);
356int tegra_pinmux_get_pingroup(int gpio_nr);
357int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
358 enum tegra_pullupdown pupd);
359
360void tegra_pinmux_config_table(const struct tegra_pingroup_config *config,
361 int len);
362
363void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
364 int len);
365void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
366 int len);
367void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
368 int len);
369void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
370 int len, enum tegra_tristate tristate);
371void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
372 int len, enum tegra_pullupdown pupd);
373
374void __init tegra_init_pinmux(void);
375#endif
diff --git a/arch/arm/mach-tegra/include/mach/sdhci.h b/arch/arm/mach-tegra/include/mach/sdhci.h
new file mode 100644
index 00000000000..b48a9288707
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/sdhci.h
@@ -0,0 +1,35 @@
1/*
2 * include/asm-arm/arch-tegra/include/mach/sdhci.h
3 *
4 * Copyright (C) 2009 Palm, Inc.
5 * Author: Yvonne Yip <y@palm.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17#ifndef __ASM_ARM_ARCH_TEGRA_SDHCI_H
18#define __ASM_ARM_ARCH_TEGRA_SDHCI_H
19
20#include <linux/mmc/host.h>
21#include <asm/mach/mmc.h>
22
23struct tegra_sdhci_platform_data {
24 int cd_gpio;
25 int wp_gpio;
26 int power_gpio;
27 int is_8bit;
28 int pm_flags;
29 int pm_caps;
30 unsigned int max_clk_limit;
31 unsigned int tap_delay;
32 struct mmc_platform_data mmc_data;
33};
34
35#endif
diff --git a/arch/arm/mach-tegra/include/mach/smmu.h b/arch/arm/mach-tegra/include/mach/smmu.h
new file mode 100644
index 00000000000..dad403a9cf0
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/smmu.h
@@ -0,0 +1,63 @@
1/*
2 * IOMMU API for SMMU in Tegra30
3 *
4 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 */
19
20#ifndef MACH_SMMU_H
21#define MACH_SMMU_H
22
23enum smmu_hwgrp {
24 HWGRP_AFI,
25 HWGRP_AVPC,
26 HWGRP_DC,
27 HWGRP_DCB,
28 HWGRP_EPP,
29 HWGRP_G2,
30 HWGRP_HC,
31 HWGRP_HDA,
32 HWGRP_ISP,
33 HWGRP_MPE,
34 HWGRP_NV,
35 HWGRP_NV2,
36 HWGRP_PPCS,
37 HWGRP_SATA,
38 HWGRP_VDE,
39 HWGRP_VI,
40
41 HWGRP_COUNT,
42
43 HWGRP_END = ~0,
44};
45
46#define HWG_AFI (1 << HWGRP_AFI)
47#define HWG_AVPC (1 << HWGRP_AVPC)
48#define HWG_DC (1 << HWGRP_DC)
49#define HWG_DCB (1 << HWGRP_DCB)
50#define HWG_EPP (1 << HWGRP_EPP)
51#define HWG_G2 (1 << HWGRP_G2)
52#define HWG_HC (1 << HWGRP_HC)
53#define HWG_HDA (1 << HWGRP_HDA)
54#define HWG_ISP (1 << HWGRP_ISP)
55#define HWG_MPE (1 << HWGRP_MPE)
56#define HWG_NV (1 << HWGRP_NV)
57#define HWG_NV2 (1 << HWGRP_NV2)
58#define HWG_PPCS (1 << HWGRP_PPCS)
59#define HWG_SATA (1 << HWGRP_SATA)
60#define HWG_VDE (1 << HWGRP_VDE)
61#define HWG_VI (1 << HWGRP_VI)
62
63#endif /* MACH_SMMU_H */
diff --git a/arch/arm/mach-tegra/include/mach/spdif.h b/arch/arm/mach-tegra/include/mach/spdif.h
new file mode 100644
index 00000000000..96103fae91b
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/spdif.h
@@ -0,0 +1,392 @@
1/*
2 * arch/arm/mach-tegra/include/mach/spdif.h
3 *
4 *
5 * Copyright (c) 2008-2009, NVIDIA Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
15 * See the GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 * MA 02110-1301, USA.
21 */
22
23
24#ifndef __ARCH_ARM_MACH_TEGRA_SPDIF_H
25#define __ARCH_ARM_MACH_TEGRA_SPDIF_H
26
27#include <linux/kernel.h>
28#include <linux/types.h>
29#include <linux/platform_device.h>
30
31/* Offsets from TEGRA_SPDIF_BASE */
32
33#define SPDIF_CTRL_0 0x0
34#define SPDIF_STATUS_0 0x4
35#define SPDIF_STROBE_CTRL_0 0x8
36#define SPDIF_DATA_FIFO_CSR_0 0x0C
37#define SPDIF_DATA_OUT_0 0x40
38#define SPDIF_DATA_IN_0 0x80
39#define SPDIF_CH_STA_RX_A_0 0x100
40#define SPDIF_CH_STA_RX_B_0 0x104
41#define SPDIF_CH_STA_RX_C_0 0x108
42#define SPDIF_CH_STA_RX_D_0 0x10C
43#define SPDIF_CH_STA_RX_E_0 0x110
44#define SPDIF_CH_STA_RX_F_0 0x114
45#define SPDIF_CH_STA_TX_A_0 0x140
46#define SPDIF_CH_STA_TX_B_0 0x144
47#define SPDIF_CH_STA_TX_C_0 0x148
48#define SPDIF_CH_STA_TX_D_0 0x14C
49#define SPDIF_CH_STA_TX_E_0 0x150
50#define SPDIF_CH_STA_TX_F_0 0x154
51#define SPDIF_USR_STA_RX_A_0 0x180
52#define SPDIF_USR_DAT_TX_A_0 0x1C0
53
54/*
55 * Register SPDIF_CTRL_0
56 */
57
58/*
59 * 1=start capturing from left channel,0=start
60 * capturing from right channel.
61 */
62#define SPDIF_CTRL_0_CAP_LC (1<<30)
63
64/* SPDIF receiver(RX): 1=enable, 0=disable. */
65#define SPDIF_CTRL_0_RX_EN (1<<29)
66
67/* SPDIF Transmitter(TX): 1=enable, 0=disable. */
68#define SPDIF_CTRL_0_TX_EN (1<<28)
69
70/* Transmit Channel status: 1=enable, 0=disable. */
71#define SPDIF_CTRL_0_TC_EN (1<<27)
72
73/* Transmit user Data: 1=enable, 0=disable. */
74#define SPDIF_CTRL_0_TU_EN (1<<26)
75
76/* Interrupt on transmit error: 1=enable, 0=disable. */
77#define SPDIF_CTRL_0_IE_TXE (1<<25)
78
79/* Interrupt on receive error: 1=enable, 0=disable. */
80#define SPDIF_CTRL_0_IE_RXE (1<<24)
81
82/* Interrupt on invalid preamble: 1=enable, 0=disable. */
83#define SPDIF_CTRL_0_IE_P (1<<23)
84
85/* Interrupt on "B" preamble: 1=enable, 0=disable. */
86#define SPDIF_CTRL_0_IE_B (1<<22)
87
88/*
89 * Interrupt when block of channel status received:
90 * 1=enable, 0=disable.
91 */
92#define SPDIF_CTRL_0_IE_C (1<<21)
93
94/*
95 * Interrupt when a valid information unit (IU) recieve:
96 * 1=enable, 0=disable.
97 */
98#define SPDIF_CTRL_0_IE_U (1<<20)
99
100/*
101 * Interrupt when RX user FIFO attn. level is reached:
102 * 1=enable, 0=disable.
103 */
104#define SPDIF_CTRL_0_QE_RU (1<<19)
105
106/*
107 * Interrupt when TX user FIFO attn. level is reached:
108 * 1=enable, 0=disable.
109 */
110#define SPDIF_CTRL_0_QE_TU (1<<18)
111
112/*
113 * Interrupt when RX data FIFO attn. level is reached:
114 * 1=enable, 0=disable.
115 */
116#define SPDIF_CTRL_0_QE_RX (1<<17)
117
118/*
119 * Interrupt when TX data FIFO attn. level is reached:
120 * 1=enable, 0=disable.
121 */
122#define SPDIF_CTRL_0_QE_TX (1<<16)
123
124/* Loopback test mode: 1=enable internal loopback, 0=Normal mode. */
125#define SPDIF_CTRL_0_LBK_EN (1<<15)
126
127/*
128 * Pack data mode:
129 * 1=Packeted left/right channel data into a single word,
130 * 0=Single data (16 bit needs to be padded to match the
131 * interface data bit size)
132 */
133#define SPDIF_CTRL_0_PACK (1<<14)
134
135/*
136 * 00=16bit data
137 * 01=20bit data
138 * 10=24bit data
139 * 11=raw data
140 */
141#define SPDIF_BIT_MODE_MODE16BIT (0)
142#define SPDIF_BIT_MODE_MODE20BIT (1)
143#define SPDIF_BIT_MODE_MODE24BIT (2)
144#define SPDIF_BIT_MODE_MODERAW (3)
145#define SPDIF_CTRL_0_BIT_MODE_SHIFT (12)
146
147#define SPDIF_CTRL_0_BIT_MODE_MASK \
148 ((0x3) << SPDIF_CTRL_0_BIT_MODE_SHIFT)
149#define SPDIF_CTRL_0_BIT_MODE_MODE16BIT \
150 (SPDIF_BIT_MODE_MODE16BIT << SPDIF_CTRL_0_BIT_MODE_SHIFT)
151#define SPDIF_CTRL_0_BIT_MODE_MODE20BIT \
152 (SPDIF_BIT_MODE_MODE20BIT << SPDIF_CTRL_0_BIT_MODE_SHIFT)
153#define SPDIF_CTRL_0_BIT_MODE_MODE24BIT \
154 (SPDIF_BIT_MODE_MODE24BIT << SPDIF_CTRL_0_BIT_MODE_SHIFT)
155#define SPDIF_CTRL_0_BIT_MODE_MODERAW \
156 (SPDIF_BIT_MODE_MODERAW << SPDIF_CTRL_0_BIT_MODE_SHIFT)
157
158
159/*
160 * SPDIF Status Register
161 * -------------------------
162 * Note: IS_P, IS_B, IS_C, and IS_U are sticky bits.
163 * Software must write a 1 to the corresponding bit location
164 * to clear the status.
165 */
166
167/* Register SPDIF_STATUS_0 */
168
169/*
170 * Receiver(RX) shifter is busy receiving data. 1=busy, 0=not busy.
171 * This bit is asserted when the receiver first locked onto the
172 * preamble of the data stream after RX_EN is asserted. This bit is
173 * deasserted when either,
174 * (a) the end of a frame is reached after RX_EN is deeasserted, or
175 * (b) the SPDIF data stream becomes inactive.
176 */
177#define SPDIF_STATUS_0_RX_BSY (1<<29)
178
179
180/*
181 * Transmitter(TX) shifter is busy transmitting data.
182 * 1=busy, 0=not busy.
183 * This bit is asserted when TX_EN is asserted.
184 * This bit is deasserted when the end of a frame is reached after
185 * TX_EN is deasserted.
186 */
187#define SPDIF_STATUS_0_TX_BSY (1<<28)
188
189/*
190 * TX is busy shifting out channel status. 1=busy, 0=not busy.
191 * This bit is asserted when both TX_EN and TC_EN are asserted and
192 * data from CH_STA_TX_A register is loaded into the internal shifter.
193 * This bit is deasserted when either,
194 * (a) the end of a frame is reached after TX_EN is deasserted, or
195 * (b) CH_STA_TX_F register is loaded into the internal shifter.
196 */
197#define SPDIF_STATUS_0_TC_BSY (1<<27)
198
199/*
200 * TX User data FIFO busy. 1=busy, 0=not busy.
201 * This bit is asserted when TX_EN and TXU_EN are asserted and
202 * there's data in the TX user FIFO. This bit is deassert when either,
203 * (a) the end of a frame is reached after TX_EN is deasserted, or
204 * (b) there's no data left in the TX user FIFO.
205 */
206#define SPDIF_STATUS_0_TU_BSY (1<<26)
207
208/* Tx FIFO Underrun error status: 1=error, 0=no error */
209#define SPDIF_STATUS_0_TX_ERR (1<<25)
210
211/* Rx FIFO Overrun error status: 1=error, 0=no error */
212#define SPDIF_STATUS_0_RX_ERR (1<<24)
213
214/* Preamble status: 1=bad/missing preamble, 0=Preamble ok */
215#define SPDIF_STATUS_0_IS_P (1<<23)
216
217/* B-preamble detection status: 0=not detected, 1=B-preamble detected */
218#define SPDIF_STATUS_0_IS_B (1<<22)
219
220/*
221 * RX channel block data receive status:
222 * 1=received entire block of channel status,
223 * 0=entire block not recieved yet.
224 */
225#define SPDIF_STATUS_0_IS_C (1<<21)
226
227/* RX User Data Valid flag: 1=valid IU detected, 0 = no IU detected. */
228#define SPDIF_STATUS_0_IS_U (1<<20)
229
230/*
231 * RX User FIFO Status:
232 * 1=attention level reached, 0=attention level not reached.
233 */
234#define SPDIF_STATUS_0_QS_RU (1<<19)
235
236/*
237 * TX User FIFO Status:
238 * 1=attention level reached, 0=attention level not reached.
239 */
240#define SPDIF_STATUS_0_QS_TU (1<<18)
241
242/*
243 * RX Data FIFO Status:
244 * 1=attention level reached, 0=attention level not reached.
245 */
246#define SPDIF_STATUS_0_QS_RX (1<<17)
247
248/*
249 * TX Data FIFO Status:
250 * 1=attention level reached, 0=attention level not reached.
251 */
252#define SPDIF_STATUS_0_QS_TX (1<<16)
253
254
255/* SPDIF FIFO Configuration and Status Register */
256
257/* Register SPDIF_DATA_FIFO_CSR_0 */
258
259#define SPDIF_FIFO_ATN_LVL_ONE_SLOT 0
260#define SPDIF_FIFO_ATN_LVL_FOUR_SLOTS 1
261#define SPDIF_FIFO_ATN_LVL_EIGHT_SLOTS 2
262#define SPDIF_FIFO_ATN_LVL_TWELVE_SLOTS 3
263
264
265/* Clear Receiver User FIFO (RX USR.FIFO) */
266#define SPDIF_DATA_FIFO_CSR_0_RU_CLR (1<<31)
267
268/*
269 * RX USR.FIFO Attention Level:
270 * 00=1-slot-full, 01=2-slots-full, 10=3-slots-full, 11=4-slots-full.
271 */
272
273#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU1 (0)
274#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU2 (1)
275#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU3 (2)
276#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU4 (3)
277
278#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_SHIFT (29)
279#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_MASK \
280 (0x3 << SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_SHIFT)
281#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU1_WORD_FULL \
282 (SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU1 << \
283 SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_SHIF)
284#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU2_WORD_FULL \
285 (SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU2 << \
286 SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_SHIF)
287#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU3_WORD_FULL \
288 (SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU3 << \
289 SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_SHIF)
290#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU4_WORD_FULL \
291 (SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU4 << \
292 SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_SHIF)
293
294/* Number of RX USR.FIFO levels with valid data. */
295#define SPDIF_DATA_FIFO_CSR_0_FULL_COUNT_SHIFT (24)
296#define SPDIF_DATA_FIFO_CSR_0_FULL_COUNT_MASK \
297 (0x1f << SPDIF_DATA_FIFO_CSR_0_FULL_COUNT_SHIFT)
298
299/* Clear Transmitter User FIFO (TX USR.FIFO) */
300#define SPDIF_DATA_FIFO_CSR_0_TU_CLR (1<<23)
301
302/*
303 * TxUSR.FIFO Attention Level:
304 * 11=4-slots-empty, 10=3-slots-empty, 01=2-slots-empty, 00=1-slot-empty.
305 */
306
307#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU1 (0)
308#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU2 (1)
309#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU3 (2)
310#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU4 (3)
311
312#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_SHIFT (21)
313#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_MASK \
314 (0x3 << SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_SHIFT)
315#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU1_WORD_EMPTY \
316 (SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU1 << \
317 SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_SHIFT)
318#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU2_WORD_EMPTY \
319 (SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU2 << \
320 SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_SHIFT)
321#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU3_WORD_EMPTY \
322 (SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU3 << \
323 SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_SHIFT)
324#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU4_WORD_EMPTY \
325 (SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU4 << \
326 SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_SHIFT)
327
328/* Number of Tx USR.FIFO levels that could be filled. */
329#define SPDIF_DATA_FIFO_CSR_0_TU_EMPTY_COUNT_SHIFT (16)
330#define SPDIF_DATA_FIFO_CSR_0_TU_EMPTY_COUNT_FIELD \
331 ((0x1f) << SPDIF_DATA_FIFO_CSR_0_TU_EMPTY_COUNT_SHIFT)
332
333/* Clear Receiver Data FIFO (RX DATA.FIFO). */
334#define SPDIF_DATA_FIFO_CSR_0_RX_CLR (1<<15)
335
336/*
337 * Rx FIFO Attention Level:
338 * 11=12-slots-full, 10=8-slots-full, 01=4-slots-full, 00=1-slot-full.
339 */
340#define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_SHIFT (13)
341#define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_MASK \
342 (0x3 << SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_SHIFT)
343#define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_RX1_WORD_FULL \
344 (SPDIF_FIFO_ATN_LVL_ONE_SLOT << \
345 SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_SHIFT)
346#define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_RX4_WORD_FULL \
347 (SPDIF_FIFO_ATN_LVL_FOUR_SLOTS << \
348 SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_SHIFT)
349#define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_RX8_WORD_FULL \
350 (SPDIF_FIFO_ATN_LVL_EIGHT_SLOTS << \
351 SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_SHIFT)
352#define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_RX12_WORD_FULL \
353 (SPDIF_FIFO_ATN_LVL_TWELVE_SLOTS << \
354 SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_SHIFT)
355
356
357/* Number of RX DATA.FIFO levels with valid data */
358#define SPDIF_DATA_FIFO_CSR_0_RX_DATA_FIFO_FULL_COUNT_SHIFT (8)
359#define SPDIF_DATA_FIFO_CSR_0_RX_DATA_FIFO_FULL_COUNT_FIELD \
360 ((0x1f) << SPDIF_DATA_FIFO_CSR_0_RX_DATA_FIFO_FULL_COUNT_SHIFT)
361
362/* Clear Transmitter Data FIFO (TX DATA.FIFO) */
363#define SPDIF_DATA_FIFO_CSR_0_TX_CLR (1<<7)
364
365/*
366 * Tx FIFO Attention Level:
367 * 11=12-slots-empty, 10=8-slots-empty, 01=4-slots-empty, 00=1-slot-empty
368 */
369#define SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_SHIFT (5)
370#define SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_MASK \
371 (0x3 << SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_SHIFT)
372#define SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_TX1_WORD_FULL \
373 (SPDIF_FIFO_ATN_LVL_ONE_SLOT << \
374 SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_SHIFT)
375#define SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_TX4_WORD_FULL \
376 (SPDIF_FIFO_ATN_LVL_FOUR_SLOTS << \
377 SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_SHIFT)
378#define SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_TX8_WORD_FULL \
379 (SPDIF_FIFO_ATN_LVL_EIGHT_SLOTS << \
380 SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_SHIFT)
381#define SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_TX12_WORD_FULL \
382 (SPDIF_FIFO_ATN_LVL_TWELVE_SLOTS << \
383 SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_SHIFT)
384
385
386/* Number of Tx DATA.FIFO levels that could be filled. */
387#define SPDIF_DATA_FIFO_CSR_0_TD_EMPTY_COUNT_SHIFT (0)
388#define SPDIF_DATA_FIFO_CSR_0_TD_EMPTY_COUNT_MASK \
389 ((0x1f) << SPDIF_DATA_FIFO_CSR_0_TD_EMPTY_COUNT_SHIFT)
390
391
392#endif /* __ARCH_ARM_MACH_TEGRA_SPDIF_H */
diff --git a/arch/arm/mach-tegra/include/mach/spi.h b/arch/arm/mach-tegra/include/mach/spi.h
new file mode 100644
index 00000000000..171e4007b4b
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/spi.h
@@ -0,0 +1,42 @@
1/*
2 * arch/arm/mach-tegra/include/mach/spi.h
3 *
4 * Copyright (c) 2010, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
19 */
20
21#ifndef __MACH_TEGRA_SPI_H
22#define __MACH_TEGRA_SPI_H
23
24#include <linux/types.h>
25#include <linux/spi/spi.h>
26
27typedef int (*callback)(void *client_data);
28
29/**
30 * register_spi_slave_callback - registers notification callback provided by
31 * the client.
32 * This callback indicate that the controller is all set to receive/transfer
33 * data.
34 * @spi: struct spi_device - refer to linux/spi/spi.h
35 * @func: Callback function
36 * @client_data: Data to be passed in callback
37 * Context: can not sleep
38 */
39int spi_tegra_register_callback(struct spi_device *spi, callback func,
40 void *client_data);
41
42#endif
diff --git a/arch/arm/mach-tegra/include/mach/system.h b/arch/arm/mach-tegra/include/mach/system.h
new file mode 100644
index 00000000000..7bc605e5dc8
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/system.h
@@ -0,0 +1,34 @@
1/*
2 * arch/arm/mach-tegra/include/mach/system.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 * Erik Gilling <konkers@google.com>
9 *
10 * Copyright (C) 2010-2011 NVIDIA Corporation
11 *
12 * This software is licensed under the terms of the GNU General Public
13 * License version 2, as published by the Free Software Foundation, and
14 * may be copied, distributed, and modified under those terms.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 */
22
23#ifndef __MACH_TEGRA_SYSTEM_H
24#define __MACH_TEGRA_SYSTEM_H
25
26#include <mach/iomap.h>
27
28extern void (*arch_reset)(char mode, const char *cmd);
29
30static inline void arch_idle(void)
31{
32}
33
34#endif
diff --git a/arch/arm/mach-tegra/include/mach/tegra-bb-power.h b/arch/arm/mach-tegra/include/mach/tegra-bb-power.h
new file mode 100644
index 00000000000..e0b7e3de326
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra-bb-power.h
@@ -0,0 +1,61 @@
1/*
2 * arch/arm/mach-tegra/include/mach/tegra-bb-power.h
3 *
4 * Copyright (C) 2011 NVIDIA Corporation
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#define GPIO_INVALID UINT_MAX
18
19union tegra_bb_gpio_id {
20 struct {
21 int mdm_reset;
22 int mdm_on;
23 int ap2mdm_ack;
24 int mdm2ap_ack;
25 int ap2mdm_ack2;
26 int mdm2ap_ack2;
27 int rsvd1;
28 int rsvd2;
29 } generic;
30 struct {
31 int bb_rst;
32 int bb_on;
33 int ipc_bb_wake;
34 int ipc_ap_wake;
35 int ipc_hsic_active;
36 int ipc_hsic_sus_req;
37 int rsvd1;
38 int rsvd2;
39 } xmm;
40 struct {
41 int pwr_status;
42 int pwr_on;
43 int uart_awr;
44 int uart_cwr;
45 int usb_awr;
46 int usb_cwr;
47 int service;
48 int resout2;
49 } m7400;
50};
51
52typedef struct platform_device* (*ehci_register_cb)(void);
53typedef void (*ehci_unregister_cb)(struct platform_device *);
54
55struct tegra_bb_pdata {
56 union tegra_bb_gpio_id *id;
57 struct platform_device *device;
58 ehci_register_cb ehci_register;
59 ehci_unregister_cb ehci_unregister;
60 int bb_id;
61};
diff --git a/arch/arm/mach-tegra/include/mach/tegra_aic326x_pdata.h b/arch/arm/mach-tegra/include/mach/tegra_aic326x_pdata.h
new file mode 100644
index 00000000000..a47ef1982e4
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_aic326x_pdata.h
@@ -0,0 +1,39 @@
1/*
2 * arch/arm/mach-tegra/include/mach/tegra_aic326x_pdata.h
3 *
4 * Copyright 2011 NVIDIA, Inc.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16#ifndef __MACH_TEGRA_TLVAIC326X_H
17#define __MACH_TEGRA_TLVAIC326X_H
18
19#define HIFI_CODEC 0
20#define BASEBAND 1
21#define BT_SCO 2
22#define NUM_I2S_DEVICES 3
23
24struct baseband_config {
25 int rate;
26 int channels;
27};
28
29struct tegra_aic326x_platform_data {
30 int gpio_spkr_en;
31 int gpio_hp_det;
32 int gpio_hp_mute;
33 int gpio_int_mic_en;
34 int gpio_ext_mic_en;
35 int audio_port_id[NUM_I2S_DEVICES];
36 struct baseband_config baseband_param;
37};
38#endif
39
diff --git a/arch/arm/mach-tegra/include/mach/tegra_asoc_pdata.h b/arch/arm/mach-tegra/include/mach/tegra_asoc_pdata.h
new file mode 100644
index 00000000000..34eb2f4fc37
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_asoc_pdata.h
@@ -0,0 +1,36 @@
1/*
2 * arch/arm/mach-tegra/include/mach/tegra_asoc_pdata.h
3 *
4 * Copyright 2012 NVIDIA, Inc.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#define HIFI_CODEC 0
18#define BASEBAND 1
19#define BT_SCO 2
20#define NUM_I2S_DEVICES 3
21
22struct baseband_config {
23 int rate;
24 int channels;
25};
26
27struct tegra_asoc_platform_data {
28 int gpio_spkr_en;
29 int gpio_hp_det;
30 int gpio_hp_mute;
31 int gpio_int_mic_en;
32 int gpio_ext_mic_en;
33 unsigned int debounce_time_hp;
34 int audio_port_id[NUM_I2S_DEVICES];
35 struct baseband_config baseband_param;
36};
diff --git a/arch/arm/mach-tegra/include/mach/tegra_dc_ext.h b/arch/arm/mach-tegra/include/mach/tegra_dc_ext.h
new file mode 100644
index 00000000000..521039283d8
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_dc_ext.h
@@ -0,0 +1,77 @@
1/*
2 * arch/arm/mach-tegra/include/mach/tegra_dc_ext.h
3 *
4 * Copyright (C) 2011, NVIDIA Corporation
5 *
6 * Author: Robert Morell <rmorell@nvidia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 */
18
19#ifndef __MACH_TEGRA_DC_EXT_H
20#define __MACH_TEGRA_DC_EXT_H
21
22#include <linux/nvhost.h>
23
24struct tegra_dc_ext;
25
26#ifdef CONFIG_TEGRA_DC_EXTENSIONS
27int __init tegra_dc_ext_module_init(void);
28void __exit tegra_dc_ext_module_exit(void);
29
30struct tegra_dc_ext *tegra_dc_ext_register(struct nvhost_device *ndev,
31 struct tegra_dc *dc);
32void tegra_dc_ext_unregister(struct tegra_dc_ext *dc_ext);
33
34/* called by display controller on enable/disable */
35void tegra_dc_ext_enable(struct tegra_dc_ext *dc_ext);
36void tegra_dc_ext_disable(struct tegra_dc_ext *dc_ext);
37
38int tegra_dc_ext_process_hotplug(int output);
39
40#else /* CONFIG_TEGRA_DC_EXTENSIONS */
41
42static inline
43int tegra_dc_ext_module_init(void)
44{
45 return 0;
46}
47static inline
48void tegra_dc_ext_module_exit(void)
49{
50}
51
52static inline
53struct tegra_dc_ext *tegra_dc_ext_register(struct nvhost_device *ndev,
54 struct tegra_dc *dc)
55{
56 return NULL;
57}
58static inline
59void tegra_dc_ext_unregister(struct tegra_dc_ext *dc_ext)
60{
61}
62static inline
63void tegra_dc_ext_enable(struct tegra_dc_ext *dc_ext)
64{
65}
66static inline
67void tegra_dc_ext_disable(struct tegra_dc_ext *dc_ext)
68{
69}
70static inline
71int tegra_dc_ext_process_hotplug(int output)
72{
73 return 0;
74}
75#endif /* CONFIG_TEGRA_DC_EXTENSIONS */
76
77#endif /* __MACH_TEGRA_DC_EXT_H */
diff --git a/arch/arm/mach-tegra/include/mach/tegra_fb.h b/arch/arm/mach-tegra/include/mach/tegra_fb.h
new file mode 100644
index 00000000000..84ae8869b24
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_fb.h
@@ -0,0 +1,27 @@
1/*
2 * arch/arm/mach-tegra/include/mach/tegra_fb.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Colin Cross <ccross@android.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18/* Platform data structure to be passed to the driver */
19struct tegra_fb_lcd_data {
20 int fb_xres;
21 int fb_yres;
22 /* Resolution of the output to the LCD. If different from the
23 framebuffer resolution, the Tegra display block will scale it */
24 int lcd_xres;
25 int lcd_yres;
26 int bits_per_pixel;
27};
diff --git a/arch/arm/mach-tegra/include/mach/tegra_fiq_debugger.h b/arch/arm/mach-tegra/include/mach/tegra_fiq_debugger.h
new file mode 100644
index 00000000000..4d1a0b54f2a
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_fiq_debugger.h
@@ -0,0 +1,30 @@
1/*
2 * linux/arch/arm/mach-tegra/include/mach/tegra_fiq_debugger.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef __MACH_TEGRA_FIQ_DEBUGGER_H
18#define __MACH_TEGRA_FIQ_DEBUGGER_H
19
20#ifdef CONFIG_TEGRA_FIQ_DEBUGGER
21void tegra_serial_debug_init(unsigned int base, int irq,
22 struct clk *clk, int signal_irq, int wakeup_irq);
23#else
24static inline void tegra_serial_debug_init(unsigned int base, int irq,
25 struct clk *clk, int signal_irq, int wakeup_irq)
26{
27}
28#endif
29
30#endif
diff --git a/arch/arm/mach-tegra/include/mach/tegra_fuse.h b/arch/arm/mach-tegra/include/mach/tegra_fuse.h
new file mode 100644
index 00000000000..d264745c70c
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_fuse.h
@@ -0,0 +1,27 @@
1/*
2 * arch/arm/mach-tegra/include/mach/tegra_fuse.h
3 *
4 * Tegra Public Fuse header file
5 *
6 * Copyright (c) 2011, NVIDIA Corporation.
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 */
18
19#ifndef _MACH_TEGRA_PUBLIC_FUSE_H_
20#define _MACH_TEGRA_PUBLIC_FUSE_H_
21
22int tegra_fuse_get_revision(u32 *rev);
23int tegra_fuse_get_tsensor_calibration_data(u32 *calib);
24int tegra_fuse_get_tsensor_spare_bits(u32 *spare_bits);
25
26#endif /* _MACH_TEGRA_PUBLIC_FUSE_H_*/
27
diff --git a/arch/arm/mach-tegra/include/mach/tegra_max98088_pdata.h b/arch/arm/mach-tegra/include/mach/tegra_max98088_pdata.h
new file mode 100644
index 00000000000..eb59cf0962b
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_max98088_pdata.h
@@ -0,0 +1,35 @@
1/*
2 * arch/arm/mach-tegra/include/mach/tegra_max98088_pdata.h
3 *
4 * Copyright 2011 NVIDIA, Inc.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#define HIFI_CODEC 0
18#define BASEBAND 1
19#define BT_SCO 2
20#define NUM_I2S_DEVICES 3
21
22struct baseband_config {
23 int rate;
24 int channels;
25};
26
27struct tegra_max98088_platform_data {
28 int gpio_spkr_en;
29 int gpio_hp_det;
30 int gpio_hp_mute;
31 int gpio_int_mic_en;
32 int gpio_ext_mic_en;
33 int audio_port_id[NUM_I2S_DEVICES];
34 struct baseband_config baseband_param;
35};
diff --git a/arch/arm/mach-tegra/include/mach/tegra_odm_fuses.h b/arch/arm/mach-tegra/include/mach/tegra_odm_fuses.h
new file mode 100644
index 00000000000..4ab8433dbbf
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_odm_fuses.h
@@ -0,0 +1,107 @@
1/*
2 * arch/arm/mach-tegra/include/mach/tegra_odm_fuses.h
3 *
4 * Copyright (c) 2011, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
19 */
20
21#ifndef __MACH_TEGRA_ODM_FUSES_H
22#define __MACH_TEGRA_ODM_FUSES_H
23
24#define SBK_DEVKEY_STATUS_SZ sizeof(u32)
25
26/*
27 * fuse io parameters: params with sizes less than a byte are
28 * explicitly mentioned
29 */
30enum fuse_io_param {
31 DEVKEY,
32 JTAG_DIS, /* 1 bit long */
33 /*
34 * Programming the odm production fuse at the same
35 * time as the sbk or dev_key is not allowed as it is not possible to
36 * verify that the sbk or dev_key were programmed correctly.
37 */
38 ODM_PROD_MODE, /* 1 bit long */
39 SEC_BOOT_DEV_CFG,
40 SEC_BOOT_DEV_SEL, /* 3 bits long */
41 SBK,
42 SW_RSVD, /* 4 bits long */
43 IGNORE_DEV_SEL_STRAPS, /* 1 bit long */
44 ODM_RSVD,
45 SBK_DEVKEY_STATUS,
46 _PARAMS_U32 = 0x7FFFFFFF
47};
48
49#define MAX_PARAMS SBK_DEVKEY_STATUS
50
51/* the order of the members is pre-decided. please do not change */
52struct fuse_data {
53 u32 devkey;
54 u32 jtag_dis;
55 u32 odm_prod_mode;
56 u32 bootdev_cfg;
57 u32 bootdev_sel;
58 u32 sbk[4];
59 u32 sw_rsvd;
60 u32 ignore_devsel_straps;
61 u32 odm_rsvd[8];
62};
63
64/* secondary boot device options */
65enum {
66 SECBOOTDEV_SDMMC,
67 SECBOOTDEV_NOR,
68 SECBOOTDEV_SPI,
69 SECBOOTDEV_NAND,
70 SECBOOTDEV_LBANAND,
71 SECBOOTDEV_MUXONENAND,
72 _SECBOOTDEV_MAX,
73 _SECBOOTDEV_U32 = 0x7FFFFFFF
74};
75
76/*
77 * read the fuse settings
78 * @param: io_param_type - param type enum
79 * @param: size - read size in bytes
80 */
81int tegra_fuse_read(enum fuse_io_param io_param_type, u32 *data, int size);
82
83#define FLAGS_DEVKEY BIT(DEVKEY)
84#define FLAGS_JTAG_DIS BIT(JTAG_DIS)
85#define FLAGS_SBK_DEVKEY_STATUS BIT(SBK_DEVKEY_STATUS)
86#define FLAGS_ODM_PROD_MODE BIT(ODM_PROD_MODE)
87#define FLAGS_SEC_BOOT_DEV_CFG BIT(SEC_BOOT_DEV_CFG)
88#define FLAGS_SEC_BOOT_DEV_SEL BIT(SEC_BOOT_DEV_SEL)
89#define FLAGS_SBK BIT(SBK)
90#define FLAGS_SW_RSVD BIT(SW_RSVD)
91#define FLAGS_IGNORE_DEV_SEL_STRAPS BIT(IGNORE_DEV_SEL_STRAPS)
92#define FLAGS_ODMRSVD BIT(ODM_RSVD)
93
94/*
95 * Prior to invoking this routine, the caller is responsible for supplying
96 * valid fuse programming voltage.
97 *
98 * @param: pgm_data - entire data to be programmed
99 * @flags: program flags (e.g. FLAGS_DEVKEY)
100 */
101int tegra_fuse_program(struct fuse_data *pgm_data, u32 flags);
102
103/* Disables the fuse programming until the next system reset */
104void tegra_fuse_program_disable(void);
105
106extern int (*tegra_fuse_regulator_en)(int);
107#endif
diff --git a/arch/arm/mach-tegra/include/mach/tegra_p1852_pdata.h b/arch/arm/mach-tegra/include/mach/tegra_p1852_pdata.h
new file mode 100644
index 00000000000..bfd61c46005
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_p1852_pdata.h
@@ -0,0 +1,45 @@
1/*
2 * arch/arm/mach-tegra/include/mach/tegra_p1852_pdata.h
3 *
4 * Copyright 2012 NVIDIA, Inc.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef __MACH_TEGRA_P1852_PDATA_H
18#define __MACH_TEGRA_P1852_PDATA_H
19
20#define NUM_AUDIO_CONTROLLERS 4
21
22/* data format supported */
23enum i2s_data_format {
24 format_i2s = 0x1,
25 format_dsp = 0x2,
26 format_rjm = 0x4,
27 format_ljm = 0x8,
28 format_tdm = 0x10
29};
30
31struct codec_info_s {
32 /* Name of the Codec Dai on the system */
33 char *codec_dai_name;
34 /* Name of the I2S controller dai its connected to */
35 char *cpu_dai_name;
36 char *codec_name; /* Name of the Codec Driver */
37 char *name; /* Name of the Codec-Dai-Link */
38 enum i2s_data_format i2s_format;
39 int master; /* Codec is Master or Slave */
40};
41
42struct tegra_p1852_platform_data {
43 struct codec_info_s codec_info[NUM_AUDIO_CONTROLLERS];
44};
45#endif
diff --git a/arch/arm/mach-tegra/include/mach/tegra_rt5640_pdata.h b/arch/arm/mach-tegra/include/mach/tegra_rt5640_pdata.h
new file mode 100644
index 00000000000..87dcda8e61f
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_rt5640_pdata.h
@@ -0,0 +1,25 @@
1/*
2 * arch/arm/mach-tegra/include/mach/tegra_rt5640_pdata.h
3 *
4 * Copyright 2011 NVIDIA, Inc.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17struct tegra_rt5640_platform_data {
18 const char *codec_name;
19 const char *codec_dai_name;
20 int gpio_spkr_en;
21 int gpio_hp_det;
22 int gpio_hp_mute;
23 int gpio_int_mic_en;
24 int gpio_ext_mic_en;
25};
diff --git a/arch/arm/mach-tegra/include/mach/tegra_smmu.h b/arch/arm/mach-tegra/include/mach/tegra_smmu.h
new file mode 100644
index 00000000000..c4401c45a48
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_smmu.h
@@ -0,0 +1,24 @@
1/*
2 * arch/arm/mach-tegra/include/mach/tegra_smmu.h
3 *
4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16#if defined(CONFIG_TEGRA_IOVMM_SMMU) || defined(CONFIG_TEGRA_IOMMU_SMMU)
17struct tegra_smmu_window {
18 unsigned long start;
19 unsigned long end;
20};
21
22extern struct tegra_smmu_window *tegra_smmu_window(int wnum);
23extern int tegra_smmu_window_count(void);
24#endif
diff --git a/arch/arm/mach-tegra/include/mach/tegra_usb_modem_power.h b/arch/arm/mach-tegra/include/mach/tegra_usb_modem_power.h
new file mode 100644
index 00000000000..0ce7fa40eb2
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_usb_modem_power.h
@@ -0,0 +1,47 @@
1/*
2 * arch/arm/mach-tegra/include/mach/tegra_usb_modem_power.c
3 *
4 * Copyright (c) 2011, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
19 */
20
21#ifndef __MACH_TEGRA_USB_MODEM_POWER_H
22#define __MACH_TEGRA_USB_MODEM_POWER_H
23
24#include <linux/interrupt.h>
25
26/* modem capabilities */
27#define TEGRA_MODEM_AUTOSUSPEND 0x01
28#define TEGRA_MODEM_RECOVERY 0x02
29
30/* modem operations */
31struct tegra_modem_operations {
32 int (*init) (void); /* modem init */
33 void (*start) (void); /* modem start */
34 void (*stop) (void); /* modem stop */
35 void (*suspend) (void); /* send L3 hint during system suspend */
36 void (*resume) (void); /* send L3->0 hint during system resume */
37 void (*reset) (void); /* modem reset */
38};
39
40/* tegra usb modem power platform data */
41struct tegra_usb_modem_power_platform_data {
42 const struct tegra_modem_operations *ops;
43 unsigned int wake_gpio; /* remote wakeup gpio */
44 unsigned int flags; /* remote wakeup irq flags */
45};
46
47#endif /* __MACH_TEGRA_USB_MODEM_POWER_H */
diff --git a/arch/arm/mach-tegra/include/mach/tegra_wm8753_pdata.h b/arch/arm/mach-tegra/include/mach/tegra_wm8753_pdata.h
new file mode 100644
index 00000000000..944e410b4ae
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_wm8753_pdata.h
@@ -0,0 +1,24 @@
1/*
2 * arch/arm/mach-tegra/include/mach/tegra_wm8903_pdata.h
3 *
4 * Copyright 2011 NVIDIA, Inc.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17struct tegra_wm8753_platform_data {
18 int gpio_spkr_en;
19 int gpio_hp_det;
20 int gpio_hp_mute;
21 int gpio_int_mic_en;
22 int gpio_ext_mic_en;
23 unsigned int debounce_time_hp;
24};
diff --git a/arch/arm/mach-tegra/include/mach/tegra_wm8903_pdata.h b/arch/arm/mach-tegra/include/mach/tegra_wm8903_pdata.h
new file mode 100644
index 00000000000..9d293344a7f
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_wm8903_pdata.h
@@ -0,0 +1,23 @@
1/*
2 * arch/arm/mach-tegra/include/mach/tegra_wm8903_pdata.h
3 *
4 * Copyright 2011 NVIDIA, Inc.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17struct tegra_wm8903_platform_data {
18 int gpio_spkr_en;
19 int gpio_hp_det;
20 int gpio_hp_mute;
21 int gpio_int_mic_en;
22 int gpio_ext_mic_en;
23};
diff --git a/arch/arm/mach-tegra/include/mach/thermal.h b/arch/arm/mach-tegra/include/mach/thermal.h
new file mode 100644
index 00000000000..ab7b34492d9
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/thermal.h
@@ -0,0 +1,62 @@
1/*
2 * arch/arm/mach-tegra/thermal.h
3 *
4 * Copyright (C) 2010-2011 NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef __MACH_THERMAL_H
18#define __MACH_THERMAL_H
19
20/* All units in millicelsius */
21struct tegra_thermal_data {
22 long temp_throttle;
23 long temp_shutdown;
24 long temp_offset;
25#ifdef CONFIG_TEGRA_EDP_LIMITS
26 long edp_offset;
27 long hysteresis_edp;
28#endif
29#ifdef CONFIG_TEGRA_THERMAL_SYSFS
30 int tc1;
31 int tc2;
32 long passive_delay;
33#else
34 long hysteresis_throttle;
35#endif
36};
37
38struct tegra_thermal_device {
39 char *name;
40 void *data;
41 long offset;
42 int (*get_temp) (void *, long *);
43 int (*get_temp_low)(void *, long *);
44 int (*set_limits) (void *, long, long);
45 int (*set_alert)(void *, void (*)(void *), void *);
46 int (*set_shutdown_temp)(void *, long);
47};
48
49#ifndef CONFIG_ARCH_TEGRA_2x_SOC
50int tegra_thermal_init(struct tegra_thermal_data *data);
51int tegra_thermal_set_device(struct tegra_thermal_device *device);
52int tegra_thermal_exit(void);
53#else
54static inline int tegra_thermal_init(struct tegra_thermal_data *data)
55{ return 0; }
56static inline int tegra_thermal_set_device(struct tegra_thermal_device *dev)
57{ return 0; }
58static inline int tegra_thermal_exit(void)
59{ return 0; }
60#endif
61
62#endif /* __MACH_THERMAL_H */
diff --git a/arch/arm/mach-tegra/include/mach/tsensor.h b/arch/arm/mach-tegra/include/mach/tsensor.h
new file mode 100644
index 00000000000..190a38586c5
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tsensor.h
@@ -0,0 +1,48 @@
1/*
2 * arch/arm/mach-tegra/include/mach/tsensor.h
3 *
4 * Tegra tsensor header file
5 *
6 * Copyright (c) 2011, NVIDIA Corporation.
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 */
18
19#ifndef __MACH_TEGRA_TSENSOR_H
20#define __MACH_TEGRA_TSENSOR_H
21
22#include <linux/types.h>
23
24#include <mach/edp.h>
25
26#define MAX_ZONES 16
27
28struct tegra_tsensor_data;
29
30struct tegra_tsensor_platform_data {
31 void (*probe_callback)(struct tegra_tsensor_data *);
32};
33
34int tsensor_thermal_get_temp(struct tegra_tsensor_data *data,
35 long *milli_temp);
36int tsensor_thermal_get_temp_low(struct tegra_tsensor_data *data,
37 long *milli_temp);
38int tsensor_thermal_set_limits(struct tegra_tsensor_data *data,
39 long lo_limit_milli,
40 long hi_limit_milli);
41int tsensor_thermal_set_alert(struct tegra_tsensor_data *data,
42 void (*alert_func)(void *),
43 void *alert_data);
44int tsensor_thermal_set_shutdown_temp(struct tegra_tsensor_data *data,
45 long shutdown_temp_milli);
46
47#endif /* __MACH_TEGRA_TSENSOR_H */
48
diff --git a/arch/arm/mach-tegra/include/mach/usb_phy.h b/arch/arm/mach-tegra/include/mach/usb_phy.h
new file mode 100644
index 00000000000..b5bf001d613
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/usb_phy.h
@@ -0,0 +1,166 @@
1/*
2 * arch/arm/mach-tegra/include/mach/usb_phy.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2011 NVIDIA Corporation.
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#ifndef __MACH_USB_PHY_H
19#define __MACH_USB_PHY_H
20
21#include <linux/clk.h>
22#include <linux/regulator/consumer.h>
23#include <linux/usb/otg.h>
24#include <linux/platform_data/tegra_usb.h>
25
26struct tegra_utmip_config {
27 u8 hssync_start_delay;
28 u8 elastic_limit;
29 u8 idle_wait_delay;
30 u8 term_range_adj;
31 u8 xcvr_setup;
32 signed char xcvr_setup_offset;
33 u8 xcvr_use_fuses;
34 u8 xcvr_lsfslew;
35 u8 xcvr_lsrslew;
36};
37
38struct tegra_ulpi_trimmer {
39 u8 shadow_clk_delay; /* 0 ~ 31 */
40 u8 clock_out_delay; /* 0 ~ 31 */
41 u8 data_trimmer; /* 0 ~ 7 */
42 u8 stpdirnxt_trimmer; /* 0 ~ 7 */
43};
44
45struct tegra_ulpi_config {
46 int enable_gpio;
47 int reset_gpio;
48 const char *clk;
49 const struct tegra_ulpi_trimmer *trimmer;
50 int (*pre_phy_on)(void);
51 int (*post_phy_on)(void);
52 int (*pre_phy_off)(void);
53 int (*post_phy_off)(void);
54 void (*phy_restore_start)(void);
55 void (*phy_restore_end)(void);
56 int phy_restore_gpio; /* null phy restore ack from device */
57 int ulpi_dir_gpio; /* ulpi dir */
58 int ulpi_d0_gpio; /* usb linestate[0] */
59 int ulpi_d1_gpio; /* usb linestate[1] */
60};
61
62struct tegra_uhsic_config {
63 int enable_gpio;
64 int reset_gpio;
65 u8 sync_start_delay;
66 u8 idle_wait_delay;
67 u8 term_range_adj;
68 u8 elastic_underrun_limit;
69 u8 elastic_overrun_limit;
70 int (*postsuspend)(void);
71 int (*preresume)(void);
72 int (*usb_phy_ready)(void);
73 int (*post_phy_off)(void);
74};
75
76enum tegra_usb_phy_port_speed {
77 TEGRA_USB_PHY_PORT_SPEED_FULL = 0,
78 TEGRA_USB_PHY_PORT_SPEED_LOW,
79 TEGRA_USB_PHY_PORT_SPEED_HIGH,
80};
81
82enum tegra_usb_phy_mode {
83 TEGRA_USB_PHY_MODE_DEVICE,
84 TEGRA_USB_PHY_MODE_HOST,
85};
86
87struct usb_phy_plat_data {
88 int instance;
89 int vbus_irq;
90 int vbus_gpio;
91 char * vbus_reg_supply;
92};
93
94struct tegra_xtal_freq;
95
96struct tegra_usb_phy {
97 int instance;
98 const struct tegra_xtal_freq *freq;
99 void __iomem *regs;
100 void __iomem *pad_regs;
101 struct clk *clk;
102 struct clk *pll_u;
103 struct clk *pad_clk;
104 enum tegra_usb_phy_mode mode;
105 void *config;
106 struct regulator *reg_vdd;
107 struct regulator *reg_vbus;
108 enum tegra_usb_phy_type usb_phy_type;
109 bool regulator_on;
110 struct otg_transceiver *ulpi;
111 int initialized;
112 bool power_on;
113 bool remote_wakeup;
114 int hotplug;
115 unsigned int xcvr_setup_value;
116};
117
118typedef int (*tegra_phy_fp)(struct tegra_usb_phy *phy, bool is_dpd);
119typedef void (*tegra_phy_restore_start_fp)(struct tegra_usb_phy *phy,
120 enum tegra_usb_phy_port_speed);
121typedef void (*tegra_phy_restore_end_fp)(struct tegra_usb_phy *phy);
122
123struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
124 void *config, enum tegra_usb_phy_mode phy_mode,
125 enum tegra_usb_phy_type usb_phy_type);
126
127int tegra_usb_phy_power_on(struct tegra_usb_phy *phy, bool is_dpd);
128
129void tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy);
130
131void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy);
132
133void tegra_usb_phy_power_off(struct tegra_usb_phy *phy, bool is_dpd);
134
135void tegra_usb_phy_postsuspend(struct tegra_usb_phy *phy, bool is_dpd);
136
137void tegra_usb_phy_preresume(struct tegra_usb_phy *phy, bool is_dpd);
138
139void tegra_usb_phy_postresume(struct tegra_usb_phy *phy, bool is_dpd);
140
141void tegra_ehci_pre_reset(struct tegra_usb_phy *phy, bool is_dpd);
142
143void tegra_ehci_post_reset(struct tegra_usb_phy *phy, bool is_dpd);
144
145void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
146 enum tegra_usb_phy_port_speed port_speed);
147
148void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy);
149
150void tegra_usb_phy_close(struct tegra_usb_phy *phy);
151
152int tegra_usb_phy_bus_connect(struct tegra_usb_phy *phy);
153
154int tegra_usb_phy_bus_reset(struct tegra_usb_phy *phy);
155
156int tegra_usb_phy_bus_idle(struct tegra_usb_phy *phy);
157
158bool tegra_usb_phy_is_device_connected(struct tegra_usb_phy *phy);
159
160bool tegra_usb_phy_charger_detect(struct tegra_usb_phy *phy);
161
162int __init tegra_usb_phy_init(struct usb_phy_plat_data *pdata, int size);
163
164bool tegra_usb_phy_is_remotewake_detected(struct tegra_usb_phy *phy);
165
166#endif /* __MACH_USB_PHY_H */
diff --git a/arch/arm/mach-tegra/include/mach/vmalloc.h b/arch/arm/mach-tegra/include/mach/vmalloc.h
new file mode 100644
index 00000000000..db488e890b9
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/vmalloc.h
@@ -0,0 +1,28 @@
1/*
2 * arch/arm/mach-tegra/include/mach/vmalloc.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 * Erik Gilling <konkers@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#ifndef __MACH_TEGRA_VMALLOC_H
22#define __MACH_TEGRA_VMALLOC_H
23
24#include <asm/sizes.h>
25
26#define VMALLOC_END 0xF8000000UL
27
28#endif
diff --git a/arch/arm/mach-tegra/include/mach/w1.h b/arch/arm/mach-tegra/include/mach/w1.h
new file mode 100644
index 00000000000..c96df7abdf9
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/w1.h
@@ -0,0 +1,84 @@
1/*
2 * include/mach/w1.h
3 *
4 * Copyright (C) 2010 Motorola, Inc
5 * Author: Andrei Warkentin <andreiw@motorola.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17#ifndef __ASM_ARM_ARCH_TEGRA_W1_H
18#define __ASM_ARM_ARCH_TEGRA_W1_H
19
20struct tegra_w1_timings {
21
22 /* tsu, trelease, trdv, tlow0, tlow1 and tslot are formed
23 into the value written into OWR_RST_PRESENCE_TCTL_0 register. */
24
25 /* Read data setup, Tsu = N owr clks, Range = tsu < 1,
26 Typical value = 0x1 */
27 uint32_t tsu;
28
29 /* Release 1-wire time, Trelease = N owr clks,
30 Range = 0 <= trelease < 45, Typical value = 0xf */
31 uint32_t trelease;
32
33 /* Read data valid time, Trdv = N+1 owr clks, Range = Exactly 15 */
34 uint32_t trdv;
35
36 /* Write zero time low, Tlow0 = N+1 owr clks,
37 Range = 60 <= tlow0 < tslot < 120, typical value = 0x3c. */
38 uint32_t tlow0;
39
40 /* Write one time low, or TLOWR both are same Tlow1 = N+1 owr clks,
41 Range = 1 <= tlow1 < 15 TlowR = N+1 owr clks,
42 Range = 1 <= tlowR < 15, Typical value = 0x1. */
43 uint32_t tlow1;
44
45 /* Active time slot for write or read data, Tslot = N+1 owr clks,
46 Range = 60 <= tslot < 120, Typical value = 0x77. */
47 uint32_t tslot;
48
49 /* tpdl, tpdh, trstl, trsth are formed in the the value written
50 into the OWR_RST_PRESENCE_TCTL_0 register. */
51
52 /* Tpdl = N owr clks, Range = 60 <= tpdl < 240,
53 Typical value = 0x78. */
54 uint32_t tpdl;
55
56 /* Tpdh = N+1 owr clks, Range = 15 <= tpdh < 60.
57 Typical value = 0x1e. */
58 uint32_t tpdh;
59
60 /* Trstl = N+1 owr clks, Range = 480 <= trstl < infinity,
61 Typical value = 0x1df. */
62 uint32_t trstl;
63
64 /* Trsth = N+1 owr clks, Range = 480 <= trsth < infinity,
65 Typical value = 0x1df. */
66 uint32_t trsth;
67
68 /* Read data sample clock. Should be <= to (tlow1 - 6) clks,
69 6 clks are used for deglitch. If deglitch bypassed it
70 is 3 clks, Typical value = 0x7. */
71 uint32_t rdsclk;
72
73 /* Presence sample clock. Should be <= to (tpdl - 6) clks,
74 6 clks are used for deglitch. If deglitch bypassed it is 3 clks,
75 Typical value = 0x50. */
76 uint32_t psclk;
77};
78
79struct tegra_w1_platform_data {
80 const char *clk_id;
81 struct tegra_w1_timings *timings;
82};
83
84#endif