diff options
Diffstat (limited to 'arch/arm/mach-tegra/include/mach/spdif.h')
-rw-r--r-- | arch/arm/mach-tegra/include/mach/spdif.h | 392 |
1 files changed, 392 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/include/mach/spdif.h b/arch/arm/mach-tegra/include/mach/spdif.h new file mode 100644 index 00000000000..96103fae91b --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/spdif.h | |||
@@ -0,0 +1,392 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-tegra/include/mach/spdif.h | ||
3 | * | ||
4 | * | ||
5 | * Copyright (c) 2008-2009, NVIDIA Corporation. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | ||
15 | * See the GNU General Public License for more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License | ||
18 | * along with this program; if not, write to the Free Software | ||
19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
20 | * MA 02110-1301, USA. | ||
21 | */ | ||
22 | |||
23 | |||
24 | #ifndef __ARCH_ARM_MACH_TEGRA_SPDIF_H | ||
25 | #define __ARCH_ARM_MACH_TEGRA_SPDIF_H | ||
26 | |||
27 | #include <linux/kernel.h> | ||
28 | #include <linux/types.h> | ||
29 | #include <linux/platform_device.h> | ||
30 | |||
31 | /* Offsets from TEGRA_SPDIF_BASE */ | ||
32 | |||
33 | #define SPDIF_CTRL_0 0x0 | ||
34 | #define SPDIF_STATUS_0 0x4 | ||
35 | #define SPDIF_STROBE_CTRL_0 0x8 | ||
36 | #define SPDIF_DATA_FIFO_CSR_0 0x0C | ||
37 | #define SPDIF_DATA_OUT_0 0x40 | ||
38 | #define SPDIF_DATA_IN_0 0x80 | ||
39 | #define SPDIF_CH_STA_RX_A_0 0x100 | ||
40 | #define SPDIF_CH_STA_RX_B_0 0x104 | ||
41 | #define SPDIF_CH_STA_RX_C_0 0x108 | ||
42 | #define SPDIF_CH_STA_RX_D_0 0x10C | ||
43 | #define SPDIF_CH_STA_RX_E_0 0x110 | ||
44 | #define SPDIF_CH_STA_RX_F_0 0x114 | ||
45 | #define SPDIF_CH_STA_TX_A_0 0x140 | ||
46 | #define SPDIF_CH_STA_TX_B_0 0x144 | ||
47 | #define SPDIF_CH_STA_TX_C_0 0x148 | ||
48 | #define SPDIF_CH_STA_TX_D_0 0x14C | ||
49 | #define SPDIF_CH_STA_TX_E_0 0x150 | ||
50 | #define SPDIF_CH_STA_TX_F_0 0x154 | ||
51 | #define SPDIF_USR_STA_RX_A_0 0x180 | ||
52 | #define SPDIF_USR_DAT_TX_A_0 0x1C0 | ||
53 | |||
54 | /* | ||
55 | * Register SPDIF_CTRL_0 | ||
56 | */ | ||
57 | |||
58 | /* | ||
59 | * 1=start capturing from left channel,0=start | ||
60 | * capturing from right channel. | ||
61 | */ | ||
62 | #define SPDIF_CTRL_0_CAP_LC (1<<30) | ||
63 | |||
64 | /* SPDIF receiver(RX): 1=enable, 0=disable. */ | ||
65 | #define SPDIF_CTRL_0_RX_EN (1<<29) | ||
66 | |||
67 | /* SPDIF Transmitter(TX): 1=enable, 0=disable. */ | ||
68 | #define SPDIF_CTRL_0_TX_EN (1<<28) | ||
69 | |||
70 | /* Transmit Channel status: 1=enable, 0=disable. */ | ||
71 | #define SPDIF_CTRL_0_TC_EN (1<<27) | ||
72 | |||
73 | /* Transmit user Data: 1=enable, 0=disable. */ | ||
74 | #define SPDIF_CTRL_0_TU_EN (1<<26) | ||
75 | |||
76 | /* Interrupt on transmit error: 1=enable, 0=disable. */ | ||
77 | #define SPDIF_CTRL_0_IE_TXE (1<<25) | ||
78 | |||
79 | /* Interrupt on receive error: 1=enable, 0=disable. */ | ||
80 | #define SPDIF_CTRL_0_IE_RXE (1<<24) | ||
81 | |||
82 | /* Interrupt on invalid preamble: 1=enable, 0=disable. */ | ||
83 | #define SPDIF_CTRL_0_IE_P (1<<23) | ||
84 | |||
85 | /* Interrupt on "B" preamble: 1=enable, 0=disable. */ | ||
86 | #define SPDIF_CTRL_0_IE_B (1<<22) | ||
87 | |||
88 | /* | ||
89 | * Interrupt when block of channel status received: | ||
90 | * 1=enable, 0=disable. | ||
91 | */ | ||
92 | #define SPDIF_CTRL_0_IE_C (1<<21) | ||
93 | |||
94 | /* | ||
95 | * Interrupt when a valid information unit (IU) recieve: | ||
96 | * 1=enable, 0=disable. | ||
97 | */ | ||
98 | #define SPDIF_CTRL_0_IE_U (1<<20) | ||
99 | |||
100 | /* | ||
101 | * Interrupt when RX user FIFO attn. level is reached: | ||
102 | * 1=enable, 0=disable. | ||
103 | */ | ||
104 | #define SPDIF_CTRL_0_QE_RU (1<<19) | ||
105 | |||
106 | /* | ||
107 | * Interrupt when TX user FIFO attn. level is reached: | ||
108 | * 1=enable, 0=disable. | ||
109 | */ | ||
110 | #define SPDIF_CTRL_0_QE_TU (1<<18) | ||
111 | |||
112 | /* | ||
113 | * Interrupt when RX data FIFO attn. level is reached: | ||
114 | * 1=enable, 0=disable. | ||
115 | */ | ||
116 | #define SPDIF_CTRL_0_QE_RX (1<<17) | ||
117 | |||
118 | /* | ||
119 | * Interrupt when TX data FIFO attn. level is reached: | ||
120 | * 1=enable, 0=disable. | ||
121 | */ | ||
122 | #define SPDIF_CTRL_0_QE_TX (1<<16) | ||
123 | |||
124 | /* Loopback test mode: 1=enable internal loopback, 0=Normal mode. */ | ||
125 | #define SPDIF_CTRL_0_LBK_EN (1<<15) | ||
126 | |||
127 | /* | ||
128 | * Pack data mode: | ||
129 | * 1=Packeted left/right channel data into a single word, | ||
130 | * 0=Single data (16 bit needs to be padded to match the | ||
131 | * interface data bit size) | ||
132 | */ | ||
133 | #define SPDIF_CTRL_0_PACK (1<<14) | ||
134 | |||
135 | /* | ||
136 | * 00=16bit data | ||
137 | * 01=20bit data | ||
138 | * 10=24bit data | ||
139 | * 11=raw data | ||
140 | */ | ||
141 | #define SPDIF_BIT_MODE_MODE16BIT (0) | ||
142 | #define SPDIF_BIT_MODE_MODE20BIT (1) | ||
143 | #define SPDIF_BIT_MODE_MODE24BIT (2) | ||
144 | #define SPDIF_BIT_MODE_MODERAW (3) | ||
145 | #define SPDIF_CTRL_0_BIT_MODE_SHIFT (12) | ||
146 | |||
147 | #define SPDIF_CTRL_0_BIT_MODE_MASK \ | ||
148 | ((0x3) << SPDIF_CTRL_0_BIT_MODE_SHIFT) | ||
149 | #define SPDIF_CTRL_0_BIT_MODE_MODE16BIT \ | ||
150 | (SPDIF_BIT_MODE_MODE16BIT << SPDIF_CTRL_0_BIT_MODE_SHIFT) | ||
151 | #define SPDIF_CTRL_0_BIT_MODE_MODE20BIT \ | ||
152 | (SPDIF_BIT_MODE_MODE20BIT << SPDIF_CTRL_0_BIT_MODE_SHIFT) | ||
153 | #define SPDIF_CTRL_0_BIT_MODE_MODE24BIT \ | ||
154 | (SPDIF_BIT_MODE_MODE24BIT << SPDIF_CTRL_0_BIT_MODE_SHIFT) | ||
155 | #define SPDIF_CTRL_0_BIT_MODE_MODERAW \ | ||
156 | (SPDIF_BIT_MODE_MODERAW << SPDIF_CTRL_0_BIT_MODE_SHIFT) | ||
157 | |||
158 | |||
159 | /* | ||
160 | * SPDIF Status Register | ||
161 | * ------------------------- | ||
162 | * Note: IS_P, IS_B, IS_C, and IS_U are sticky bits. | ||
163 | * Software must write a 1 to the corresponding bit location | ||
164 | * to clear the status. | ||
165 | */ | ||
166 | |||
167 | /* Register SPDIF_STATUS_0 */ | ||
168 | |||
169 | /* | ||
170 | * Receiver(RX) shifter is busy receiving data. 1=busy, 0=not busy. | ||
171 | * This bit is asserted when the receiver first locked onto the | ||
172 | * preamble of the data stream after RX_EN is asserted. This bit is | ||
173 | * deasserted when either, | ||
174 | * (a) the end of a frame is reached after RX_EN is deeasserted, or | ||
175 | * (b) the SPDIF data stream becomes inactive. | ||
176 | */ | ||
177 | #define SPDIF_STATUS_0_RX_BSY (1<<29) | ||
178 | |||
179 | |||
180 | /* | ||
181 | * Transmitter(TX) shifter is busy transmitting data. | ||
182 | * 1=busy, 0=not busy. | ||
183 | * This bit is asserted when TX_EN is asserted. | ||
184 | * This bit is deasserted when the end of a frame is reached after | ||
185 | * TX_EN is deasserted. | ||
186 | */ | ||
187 | #define SPDIF_STATUS_0_TX_BSY (1<<28) | ||
188 | |||
189 | /* | ||
190 | * TX is busy shifting out channel status. 1=busy, 0=not busy. | ||
191 | * This bit is asserted when both TX_EN and TC_EN are asserted and | ||
192 | * data from CH_STA_TX_A register is loaded into the internal shifter. | ||
193 | * This bit is deasserted when either, | ||
194 | * (a) the end of a frame is reached after TX_EN is deasserted, or | ||
195 | * (b) CH_STA_TX_F register is loaded into the internal shifter. | ||
196 | */ | ||
197 | #define SPDIF_STATUS_0_TC_BSY (1<<27) | ||
198 | |||
199 | /* | ||
200 | * TX User data FIFO busy. 1=busy, 0=not busy. | ||
201 | * This bit is asserted when TX_EN and TXU_EN are asserted and | ||
202 | * there's data in the TX user FIFO. This bit is deassert when either, | ||
203 | * (a) the end of a frame is reached after TX_EN is deasserted, or | ||
204 | * (b) there's no data left in the TX user FIFO. | ||
205 | */ | ||
206 | #define SPDIF_STATUS_0_TU_BSY (1<<26) | ||
207 | |||
208 | /* Tx FIFO Underrun error status: 1=error, 0=no error */ | ||
209 | #define SPDIF_STATUS_0_TX_ERR (1<<25) | ||
210 | |||
211 | /* Rx FIFO Overrun error status: 1=error, 0=no error */ | ||
212 | #define SPDIF_STATUS_0_RX_ERR (1<<24) | ||
213 | |||
214 | /* Preamble status: 1=bad/missing preamble, 0=Preamble ok */ | ||
215 | #define SPDIF_STATUS_0_IS_P (1<<23) | ||
216 | |||
217 | /* B-preamble detection status: 0=not detected, 1=B-preamble detected */ | ||
218 | #define SPDIF_STATUS_0_IS_B (1<<22) | ||
219 | |||
220 | /* | ||
221 | * RX channel block data receive status: | ||
222 | * 1=received entire block of channel status, | ||
223 | * 0=entire block not recieved yet. | ||
224 | */ | ||
225 | #define SPDIF_STATUS_0_IS_C (1<<21) | ||
226 | |||
227 | /* RX User Data Valid flag: 1=valid IU detected, 0 = no IU detected. */ | ||
228 | #define SPDIF_STATUS_0_IS_U (1<<20) | ||
229 | |||
230 | /* | ||
231 | * RX User FIFO Status: | ||
232 | * 1=attention level reached, 0=attention level not reached. | ||
233 | */ | ||
234 | #define SPDIF_STATUS_0_QS_RU (1<<19) | ||
235 | |||
236 | /* | ||
237 | * TX User FIFO Status: | ||
238 | * 1=attention level reached, 0=attention level not reached. | ||
239 | */ | ||
240 | #define SPDIF_STATUS_0_QS_TU (1<<18) | ||
241 | |||
242 | /* | ||
243 | * RX Data FIFO Status: | ||
244 | * 1=attention level reached, 0=attention level not reached. | ||
245 | */ | ||
246 | #define SPDIF_STATUS_0_QS_RX (1<<17) | ||
247 | |||
248 | /* | ||
249 | * TX Data FIFO Status: | ||
250 | * 1=attention level reached, 0=attention level not reached. | ||
251 | */ | ||
252 | #define SPDIF_STATUS_0_QS_TX (1<<16) | ||
253 | |||
254 | |||
255 | /* SPDIF FIFO Configuration and Status Register */ | ||
256 | |||
257 | /* Register SPDIF_DATA_FIFO_CSR_0 */ | ||
258 | |||
259 | #define SPDIF_FIFO_ATN_LVL_ONE_SLOT 0 | ||
260 | #define SPDIF_FIFO_ATN_LVL_FOUR_SLOTS 1 | ||
261 | #define SPDIF_FIFO_ATN_LVL_EIGHT_SLOTS 2 | ||
262 | #define SPDIF_FIFO_ATN_LVL_TWELVE_SLOTS 3 | ||
263 | |||
264 | |||
265 | /* Clear Receiver User FIFO (RX USR.FIFO) */ | ||
266 | #define SPDIF_DATA_FIFO_CSR_0_RU_CLR (1<<31) | ||
267 | |||
268 | /* | ||
269 | * RX USR.FIFO Attention Level: | ||
270 | * 00=1-slot-full, 01=2-slots-full, 10=3-slots-full, 11=4-slots-full. | ||
271 | */ | ||
272 | |||
273 | #define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU1 (0) | ||
274 | #define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU2 (1) | ||
275 | #define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU3 (2) | ||
276 | #define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU4 (3) | ||
277 | |||
278 | #define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_SHIFT (29) | ||
279 | #define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_MASK \ | ||
280 | (0x3 << SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_SHIFT) | ||
281 | #define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU1_WORD_FULL \ | ||
282 | (SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU1 << \ | ||
283 | SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_SHIF) | ||
284 | #define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU2_WORD_FULL \ | ||
285 | (SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU2 << \ | ||
286 | SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_SHIF) | ||
287 | #define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU3_WORD_FULL \ | ||
288 | (SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU3 << \ | ||
289 | SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_SHIF) | ||
290 | #define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU4_WORD_FULL \ | ||
291 | (SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU4 << \ | ||
292 | SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_SHIF) | ||
293 | |||
294 | /* Number of RX USR.FIFO levels with valid data. */ | ||
295 | #define SPDIF_DATA_FIFO_CSR_0_FULL_COUNT_SHIFT (24) | ||
296 | #define SPDIF_DATA_FIFO_CSR_0_FULL_COUNT_MASK \ | ||
297 | (0x1f << SPDIF_DATA_FIFO_CSR_0_FULL_COUNT_SHIFT) | ||
298 | |||
299 | /* Clear Transmitter User FIFO (TX USR.FIFO) */ | ||
300 | #define SPDIF_DATA_FIFO_CSR_0_TU_CLR (1<<23) | ||
301 | |||
302 | /* | ||
303 | * TxUSR.FIFO Attention Level: | ||
304 | * 11=4-slots-empty, 10=3-slots-empty, 01=2-slots-empty, 00=1-slot-empty. | ||
305 | */ | ||
306 | |||
307 | #define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU1 (0) | ||
308 | #define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU2 (1) | ||
309 | #define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU3 (2) | ||
310 | #define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU4 (3) | ||
311 | |||
312 | #define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_SHIFT (21) | ||
313 | #define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_MASK \ | ||
314 | (0x3 << SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_SHIFT) | ||
315 | #define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU1_WORD_EMPTY \ | ||
316 | (SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU1 << \ | ||
317 | SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_SHIFT) | ||
318 | #define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU2_WORD_EMPTY \ | ||
319 | (SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU2 << \ | ||
320 | SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_SHIFT) | ||
321 | #define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU3_WORD_EMPTY \ | ||
322 | (SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU3 << \ | ||
323 | SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_SHIFT) | ||
324 | #define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU4_WORD_EMPTY \ | ||
325 | (SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU4 << \ | ||
326 | SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_SHIFT) | ||
327 | |||
328 | /* Number of Tx USR.FIFO levels that could be filled. */ | ||
329 | #define SPDIF_DATA_FIFO_CSR_0_TU_EMPTY_COUNT_SHIFT (16) | ||
330 | #define SPDIF_DATA_FIFO_CSR_0_TU_EMPTY_COUNT_FIELD \ | ||
331 | ((0x1f) << SPDIF_DATA_FIFO_CSR_0_TU_EMPTY_COUNT_SHIFT) | ||
332 | |||
333 | /* Clear Receiver Data FIFO (RX DATA.FIFO). */ | ||
334 | #define SPDIF_DATA_FIFO_CSR_0_RX_CLR (1<<15) | ||
335 | |||
336 | /* | ||
337 | * Rx FIFO Attention Level: | ||
338 | * 11=12-slots-full, 10=8-slots-full, 01=4-slots-full, 00=1-slot-full. | ||
339 | */ | ||
340 | #define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_SHIFT (13) | ||
341 | #define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_MASK \ | ||
342 | (0x3 << SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_SHIFT) | ||
343 | #define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_RX1_WORD_FULL \ | ||
344 | (SPDIF_FIFO_ATN_LVL_ONE_SLOT << \ | ||
345 | SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_SHIFT) | ||
346 | #define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_RX4_WORD_FULL \ | ||
347 | (SPDIF_FIFO_ATN_LVL_FOUR_SLOTS << \ | ||
348 | SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_SHIFT) | ||
349 | #define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_RX8_WORD_FULL \ | ||
350 | (SPDIF_FIFO_ATN_LVL_EIGHT_SLOTS << \ | ||
351 | SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_SHIFT) | ||
352 | #define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_RX12_WORD_FULL \ | ||
353 | (SPDIF_FIFO_ATN_LVL_TWELVE_SLOTS << \ | ||
354 | SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_SHIFT) | ||
355 | |||
356 | |||
357 | /* Number of RX DATA.FIFO levels with valid data */ | ||
358 | #define SPDIF_DATA_FIFO_CSR_0_RX_DATA_FIFO_FULL_COUNT_SHIFT (8) | ||
359 | #define SPDIF_DATA_FIFO_CSR_0_RX_DATA_FIFO_FULL_COUNT_FIELD \ | ||
360 | ((0x1f) << SPDIF_DATA_FIFO_CSR_0_RX_DATA_FIFO_FULL_COUNT_SHIFT) | ||
361 | |||
362 | /* Clear Transmitter Data FIFO (TX DATA.FIFO) */ | ||
363 | #define SPDIF_DATA_FIFO_CSR_0_TX_CLR (1<<7) | ||
364 | |||
365 | /* | ||
366 | * Tx FIFO Attention Level: | ||
367 | * 11=12-slots-empty, 10=8-slots-empty, 01=4-slots-empty, 00=1-slot-empty | ||
368 | */ | ||
369 | #define SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_SHIFT (5) | ||
370 | #define SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_MASK \ | ||
371 | (0x3 << SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_SHIFT) | ||
372 | #define SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_TX1_WORD_FULL \ | ||
373 | (SPDIF_FIFO_ATN_LVL_ONE_SLOT << \ | ||
374 | SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_SHIFT) | ||
375 | #define SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_TX4_WORD_FULL \ | ||
376 | (SPDIF_FIFO_ATN_LVL_FOUR_SLOTS << \ | ||
377 | SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_SHIFT) | ||
378 | #define SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_TX8_WORD_FULL \ | ||
379 | (SPDIF_FIFO_ATN_LVL_EIGHT_SLOTS << \ | ||
380 | SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_SHIFT) | ||
381 | #define SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_TX12_WORD_FULL \ | ||
382 | (SPDIF_FIFO_ATN_LVL_TWELVE_SLOTS << \ | ||
383 | SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_SHIFT) | ||
384 | |||
385 | |||
386 | /* Number of Tx DATA.FIFO levels that could be filled. */ | ||
387 | #define SPDIF_DATA_FIFO_CSR_0_TD_EMPTY_COUNT_SHIFT (0) | ||
388 | #define SPDIF_DATA_FIFO_CSR_0_TD_EMPTY_COUNT_MASK \ | ||
389 | ((0x1f) << SPDIF_DATA_FIFO_CSR_0_TD_EMPTY_COUNT_SHIFT) | ||
390 | |||
391 | |||
392 | #endif /* __ARCH_ARM_MACH_TEGRA_SPDIF_H */ | ||