aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-tegra/include/mach/pinmux.h
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-tegra/include/mach/pinmux.h')
-rw-r--r--arch/arm/mach-tegra/include/mach/pinmux.h375
1 files changed, 375 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h
new file mode 100644
index 00000000000..f485d0bb072
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/pinmux.h
@@ -0,0 +1,375 @@
1/*
2 * linux/arch/arm/mach-tegra/include/mach/pinmux.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2011 NVIDIA Corporation.
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#ifndef __MACH_TEGRA_PINMUX_H
19#define __MACH_TEGRA_PINMUX_H
20
21#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
22#include "pinmux-t2.h"
23#elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
24#include "pinmux-t3.h"
25#else
26#error "Undefined Tegra architecture"
27#endif
28
29#define TEGRA_MUX_LIST \
30 TEGRA_MUX(NONE) \
31 TEGRA_MUX(AHB_CLK) \
32 TEGRA_MUX(APB_CLK) \
33 TEGRA_MUX(AUDIO_SYNC) \
34 TEGRA_MUX(CRT) \
35 TEGRA_MUX(DAP1) \
36 TEGRA_MUX(DAP2) \
37 TEGRA_MUX(DAP3) \
38 TEGRA_MUX(DAP4) \
39 TEGRA_MUX(DAP5) \
40 TEGRA_MUX(DISPLAYA) \
41 TEGRA_MUX(DISPLAYB) \
42 TEGRA_MUX(EMC_TEST0_DLL) \
43 TEGRA_MUX(EMC_TEST1_DLL) \
44 TEGRA_MUX(GMI) \
45 TEGRA_MUX(GMI_INT) \
46 TEGRA_MUX(HDMI) \
47 TEGRA_MUX(I2C1) \
48 TEGRA_MUX(I2C2) \
49 TEGRA_MUX(I2C3) \
50 TEGRA_MUX(IDE) \
51 TEGRA_MUX(IRDA) \
52 TEGRA_MUX(KBC) \
53 TEGRA_MUX(MIO) \
54 TEGRA_MUX(MIPI_HS) \
55 TEGRA_MUX(NAND) \
56 TEGRA_MUX(OSC) \
57 TEGRA_MUX(OWR) \
58 TEGRA_MUX(PCIE) \
59 TEGRA_MUX(PLLA_OUT) \
60 TEGRA_MUX(PLLC_OUT1) \
61 TEGRA_MUX(PLLM_OUT1) \
62 TEGRA_MUX(PLLP_OUT2) \
63 TEGRA_MUX(PLLP_OUT3) \
64 TEGRA_MUX(PLLP_OUT4) \
65 TEGRA_MUX(PWM) \
66 TEGRA_MUX(PWR_INTR) \
67 TEGRA_MUX(PWR_ON) \
68 TEGRA_MUX(RTCK) \
69 TEGRA_MUX(SDIO1) \
70 TEGRA_MUX(SDIO2) \
71 TEGRA_MUX(SDIO3) \
72 TEGRA_MUX(SDIO4) \
73 TEGRA_MUX(SFLASH) \
74 TEGRA_MUX(SPDIF) \
75 TEGRA_MUX(SPI1) \
76 TEGRA_MUX(SPI2) \
77 TEGRA_MUX(SPI2_ALT) \
78 TEGRA_MUX(SPI3) \
79 TEGRA_MUX(SPI4) \
80 TEGRA_MUX(TRACE) \
81 TEGRA_MUX(TWC) \
82 TEGRA_MUX(UARTA) \
83 TEGRA_MUX(UARTB) \
84 TEGRA_MUX(UARTC) \
85 TEGRA_MUX(UARTD) \
86 TEGRA_MUX(UARTE) \
87 TEGRA_MUX(ULPI) \
88 TEGRA_MUX(VI) \
89 TEGRA_MUX(VI_SENSOR_CLK) \
90 TEGRA_MUX(XIO) \
91 /* End of Tegra2 MUX selectors */ \
92 TEGRA_MUX(BLINK) \
93 TEGRA_MUX(CEC) \
94 TEGRA_MUX(CLK12) \
95 TEGRA_MUX(DAP) \
96 TEGRA_MUX(DAPSDMMC2) \
97 TEGRA_MUX(DDR) \
98 TEGRA_MUX(DEV3) \
99 TEGRA_MUX(DTV) \
100 TEGRA_MUX(VI_ALT1) \
101 TEGRA_MUX(VI_ALT2) \
102 TEGRA_MUX(VI_ALT3) \
103 TEGRA_MUX(EMC_DLL) \
104 TEGRA_MUX(EXTPERIPH1) \
105 TEGRA_MUX(EXTPERIPH2) \
106 TEGRA_MUX(EXTPERIPH3) \
107 TEGRA_MUX(GMI_ALT) \
108 TEGRA_MUX(HDA) \
109 TEGRA_MUX(HSI) \
110 TEGRA_MUX(I2C4) \
111 TEGRA_MUX(I2C5) \
112 TEGRA_MUX(I2CPWR) \
113 TEGRA_MUX(I2S0) \
114 TEGRA_MUX(I2S1) \
115 TEGRA_MUX(I2S2) \
116 TEGRA_MUX(I2S3) \
117 TEGRA_MUX(I2S4) \
118 TEGRA_MUX(NAND_ALT) \
119 TEGRA_MUX(POPSDIO4) \
120 TEGRA_MUX(POPSDMMC4) \
121 TEGRA_MUX(PWM0) \
122 TEGRA_MUX(PWM1) \
123 TEGRA_MUX(PWM2) \
124 TEGRA_MUX(PWM3) \
125 TEGRA_MUX(SATA) \
126 TEGRA_MUX(SPI5) \
127 TEGRA_MUX(SPI6) \
128 TEGRA_MUX(SYSCLK) \
129 TEGRA_MUX(VGP1) \
130 TEGRA_MUX(VGP2) \
131 TEGRA_MUX(VGP3) \
132 TEGRA_MUX(VGP4) \
133 TEGRA_MUX(VGP5) \
134 TEGRA_MUX(VGP6) \
135 /* End of Tegra3 MUX selectors */
136
137enum tegra_mux_func {
138#define TEGRA_MUX(mux) TEGRA_MUX_##mux,
139 TEGRA_MUX_LIST
140#undef TEGRA_MUX
141 TEGRA_MUX_SAFE, /* "Safe" default mux selector */
142 TEGRA_MAX_MUX, /* Number of mux selectors */
143 TEGRA_MUX_TEGRA2_LAST = TEGRA_MUX_XIO,
144 TEGRA_MUX_TEGRA3_LAST = TEGRA_MUX_VGP6,
145
146 /* Mux selector aliases */
147 TEGRA_MUX_I2C = TEGRA_MUX_I2C1,
148 TEGRA_MUX_SDMMC1 = TEGRA_MUX_SDIO1,
149 TEGRA_MUX_SDMMC2 = TEGRA_MUX_SDIO2,
150 TEGRA_MUX_SDMMC3 = TEGRA_MUX_SDIO3,
151 TEGRA_MUX_SDMMC4 = TEGRA_MUX_SDIO4,
152
153 /* Special mux selector values */
154 TEGRA_MUX_INVALID = 0x4000,
155 TEGRA_MUX_RSVD = 0x8000,
156 TEGRA_MUX_RSVD0 = TEGRA_MUX_RSVD,
157 TEGRA_MUX_RSVD1 = 0x8001,
158 TEGRA_MUX_RSVD2 = 0x8002,
159 TEGRA_MUX_RSVD3 = 0x8003,
160 TEGRA_MUX_RSVD4 = 0x8004,
161};
162
163enum tegra_pullupdown {
164 TEGRA_PUPD_NORMAL = 0,
165 TEGRA_PUPD_PULL_DOWN,
166 TEGRA_PUPD_PULL_UP,
167};
168
169enum tegra_tristate {
170 TEGRA_TRI_NORMAL = 0,
171 TEGRA_TRI_TRISTATE = 1,
172};
173
174enum tegra_pin_io {
175 TEGRA_PIN_OUTPUT = 0,
176 TEGRA_PIN_INPUT = 1,
177};
178
179enum tegra_pin_lock {
180 TEGRA_PIN_LOCK_DEFAULT = 0,
181 TEGRA_PIN_LOCK_DISABLE,
182 TEGRA_PIN_LOCK_ENABLE,
183};
184
185enum tegra_pin_od {
186 TEGRA_PIN_OD_DEFAULT = 0,
187 TEGRA_PIN_OD_DISABLE,
188 TEGRA_PIN_OD_ENABLE,
189};
190
191enum tegra_pin_ioreset {
192 TEGRA_PIN_IO_RESET_DEFAULT = 0,
193 TEGRA_PIN_IO_RESET_DISABLE,
194 TEGRA_PIN_IO_RESET_ENABLE,
195};
196
197enum tegra_vddio {
198 TEGRA_VDDIO_BB = 0,
199 TEGRA_VDDIO_LCD,
200 TEGRA_VDDIO_VI,
201 TEGRA_VDDIO_UART,
202 TEGRA_VDDIO_DDR,
203 TEGRA_VDDIO_NAND,
204 TEGRA_VDDIO_SYS,
205 TEGRA_VDDIO_AUDIO,
206 TEGRA_VDDIO_SD,
207#ifndef CONFIG_ARCH_TEGRA_2x_SOC
208 TEGRA_VDDIO_CAM,
209 TEGRA_VDDIO_GMI,
210 TEGRA_VDDIO_PEXCTL,
211 TEGRA_VDDIO_SDMMC1,
212 TEGRA_VDDIO_SDMMC3,
213 TEGRA_VDDIO_SDMMC4,
214#endif
215};
216
217struct tegra_pingroup_config {
218 enum tegra_pingroup pingroup;
219 enum tegra_mux_func func;
220 enum tegra_pullupdown pupd;
221 enum tegra_tristate tristate;
222 enum tegra_pin_io io;
223 enum tegra_pin_lock lock;
224 enum tegra_pin_od od;
225 enum tegra_pin_ioreset ioreset;
226};
227
228enum tegra_slew {
229 TEGRA_SLEW_FASTEST = 0,
230 TEGRA_SLEW_FAST,
231 TEGRA_SLEW_SLOW,
232 TEGRA_SLEW_SLOWEST,
233 TEGRA_MAX_SLEW,
234};
235
236enum tegra_pull_strength {
237 TEGRA_PULL_0 = 0,
238 TEGRA_PULL_1,
239 TEGRA_PULL_2,
240 TEGRA_PULL_3,
241 TEGRA_PULL_4,
242 TEGRA_PULL_5,
243 TEGRA_PULL_6,
244 TEGRA_PULL_7,
245 TEGRA_PULL_8,
246 TEGRA_PULL_9,
247 TEGRA_PULL_10,
248 TEGRA_PULL_11,
249 TEGRA_PULL_12,
250 TEGRA_PULL_13,
251 TEGRA_PULL_14,
252 TEGRA_PULL_15,
253 TEGRA_PULL_16,
254 TEGRA_PULL_17,
255 TEGRA_PULL_18,
256 TEGRA_PULL_19,
257 TEGRA_PULL_20,
258 TEGRA_PULL_21,
259 TEGRA_PULL_22,
260 TEGRA_PULL_23,
261 TEGRA_PULL_24,
262 TEGRA_PULL_25,
263 TEGRA_PULL_26,
264 TEGRA_PULL_27,
265 TEGRA_PULL_28,
266 TEGRA_PULL_29,
267 TEGRA_PULL_30,
268 TEGRA_PULL_31,
269 TEGRA_PULL_32,
270 TEGRA_PULL_33,
271 TEGRA_PULL_34,
272 TEGRA_PULL_35,
273 TEGRA_PULL_36,
274 TEGRA_PULL_37,
275 TEGRA_PULL_38,
276 TEGRA_PULL_39,
277 TEGRA_PULL_40,
278 TEGRA_PULL_41,
279 TEGRA_PULL_42,
280 TEGRA_PULL_43,
281 TEGRA_PULL_44,
282 TEGRA_PULL_45,
283 TEGRA_PULL_46,
284 TEGRA_MAX_PULL,
285};
286
287enum tegra_drive {
288 TEGRA_DRIVE_DIV_8 = 0,
289 TEGRA_DRIVE_DIV_4,
290 TEGRA_DRIVE_DIV_2,
291 TEGRA_DRIVE_DIV_1,
292 TEGRA_MAX_DRIVE,
293};
294
295enum tegra_hsm {
296 TEGRA_HSM_DISABLE = 0,
297 TEGRA_HSM_ENABLE,
298};
299
300enum tegra_schmitt {
301 TEGRA_SCHMITT_DISABLE = 0,
302 TEGRA_SCHMITT_ENABLE,
303};
304
305struct tegra_drive_pingroup_config {
306 enum tegra_drive_pingroup pingroup;
307 enum tegra_hsm hsm;
308 enum tegra_schmitt schmitt;
309 enum tegra_drive drive;
310 enum tegra_pull_strength pull_down;
311 enum tegra_pull_strength pull_up;
312 enum tegra_slew slew_rising;
313 enum tegra_slew slew_falling;
314};
315
316struct tegra_drive_pingroup_desc {
317 const char *name;
318 s16 reg;
319 u8 drvup_offset;
320 u16 drvup_mask;
321 u8 drvdown_offset;
322 u16 drvdown_mask;
323 u8 slewrise_offset;
324 u16 slewrise_mask;
325 u8 slewfall_offset;
326 u16 slewfall_mask;
327};
328
329struct tegra_pingroup_desc {
330 const char *name;
331 int funcs[4];
332 int func_safe;
333 int vddio;
334 s16 tri_reg; /* offset into the TRISTATE_REG_* register bank */
335 s16 mux_reg; /* offset into the PIN_MUX_CTL_* register bank */
336 s16 pupd_reg; /* offset into the PULL_UPDOWN_REG_* register bank */
337 s8 tri_bit; /* offset into the TRISTATE_REG_* register bit */
338 s8 mux_bit; /* offset into the PIN_MUX_CTL_* register bit */
339 s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */
340 s8 lock_bit; /* offser of the LOCK bit into mux register bit */
341 s8 od_bit; /* offset of the OD bit into mux register bit */
342 s8 ioreset_bit; /* offset of the IO_RESET bit into mux register bit */
343 s8 io_default;
344 int gpionr;
345};
346
347extern const struct tegra_pingroup_desc tegra_soc_pingroups[];
348extern const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[];
349extern const int gpio_to_pingroup[];
350
351int tegra_pinmux_get_func(enum tegra_pingroup pg);
352int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
353 enum tegra_tristate tristate);
354int tegra_pinmux_set_io(enum tegra_pingroup pg,
355 enum tegra_pin_io input);
356int tegra_pinmux_get_pingroup(int gpio_nr);
357int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
358 enum tegra_pullupdown pupd);
359
360void tegra_pinmux_config_table(const struct tegra_pingroup_config *config,
361 int len);
362
363void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
364 int len);
365void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
366 int len);
367void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
368 int len);
369void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
370 int len, enum tegra_tristate tristate);
371void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
372 int len, enum tegra_pullupdown pupd);
373
374void __init tegra_init_pinmux(void);
375#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-21 08:55:26 -0400